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RISCV_picorv32_fpga/rtl/DE0-NANO/output_files/xoro.map.rpt

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2023-09-17 22:32:13 +00:00
Analysis & Synthesis report for xoro
Sat Sep 16 21:12:28 2023
Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis DSP Block Usage Summary
10. State Machine - |xoro_top|picorv32:cpu|mem_wordsize
11. State Machine - |xoro_top|picorv32:cpu|cpu_state
12. State Machine - |xoro_top|AsyncReceiver:uartRx|state
13. State Machine - |xoro_top|uartTx:uartTx|state
14. Registers Removed During Synthesis
15. Removed Registers Triggering Further Register Optimizations
16. General Register Statistics
17. Inverted Register Statistics
18. Registers Added for RAM Pass-Through Logic
19. Multiplexer Restructuring Statistics (Restructuring Performed)
20. Source assignments for Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated
21. Source assignments for Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated
22. Source assignments for picorv32:cpu|altsyncram:cpuregs_rtl_0|altsyncram_trd1:auto_generated
23. Source assignments for picorv32:cpu|altsyncram:cpuregs_rtl_1|altsyncram_trd1:auto_generated
24. Source assignments for Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated
25. Source assignments for Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated
26. Source assignments for AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0|altsyncram_s9c1:auto_generated
27. Parameter Settings for User Entity Instance: pll_sys:pll_sys_inst|altpll:altpll_component
28. Parameter Settings for User Entity Instance: picorv32:cpu
29. Parameter Settings for User Entity Instance: picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul
30. Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol0_rtl_0
31. Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol1_rtl_0
32. Parameter Settings for Inferred Entity Instance: picorv32:cpu|altsyncram:cpuregs_rtl_0
33. Parameter Settings for Inferred Entity Instance: picorv32:cpu|altsyncram:cpuregs_rtl_1
34. Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol3_rtl_0
35. Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol2_rtl_0
36. Parameter Settings for Inferred Entity Instance: AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0
37. Parameter Settings for Inferred Entity Instance: picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0
38. altpll Parameter Settings by Entity Instance
39. altsyncram Parameter Settings by Entity Instance
40. lpm_mult Parameter Settings by Entity Instance
41. Port Connectivity Checks: "picorv32:cpu"
42. Port Connectivity Checks: "busInterface:busInterface"
43. Port Connectivity Checks: "prng:prng|xoroshiro128plus:prng"
44. Port Connectivity Checks: "Memory:mem"
45. Port Connectivity Checks: "hundredMsTick:hundredMsTick"
46. Port Connectivity Checks: "AsyncReceiver:uartRx"
47. Port Connectivity Checks: "gpio:gpio"
48. Port Connectivity Checks: "pll_sys:pll_sys_inst"
49. Post-Synthesis Netlist Statistics for Top Partition
50. Elapsed Time Per Partition
51. Analysis & Synthesis Messages
52. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
+---------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+--------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Sep 16 21:12:28 2023 ;
; Quartus II 64-Bit Version ; 15.0.0 Build 145 04/22/2015 SJ Web Edition ;
; Revision Name ; xoro ;
; Top-level Entity Name ; xoro_top ;
; Family ; Cyclone IV E ;
; Total logic elements ; 3,155 ;
; Total combinational functions ; 2,709 ;
; Dedicated logic registers ; 1,420 ;
; Total registers ; 1420 ;
; Total pins ; 46 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 330,016 ;
; Embedded Multiplier 9-bit elements ; 8 ;
; Total PLLs ; 1 ;
+------------------------------------+--------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP4CE22F17C6 ; ;
; Top-level entity name ; xoro_top ; xoro ;
; Family name ; Cyclone IV E ; Cyclone V ;
; Maximum processors allowed for parallel compilation ; 2 ; ;
; Verilog Show LMF Mapping Messages ; Off ; ;
; Verilog Version ; SystemVerilog_2005 ; Verilog_2001 ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 16 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; < 0.1% ;
; Processors 3-16 ; 0.0% ;
+----------------------------+-------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------------+-----------------+-------------------------------------------------------+----------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------------+-----------------+-------------------------------------------------------+----------------------------------------------------------------------+---------+
; inc/timescale.vh ; yes ; User Unspecified File ; E:/Photonic/RISCV/inc/timescale.vh ; ;
; pll_sys.v ; yes ; User Wizard-Generated File ; E:/Photonic/RISCV/pll_sys.v ; ;
; rtl/timer.v ; yes ; User Verilog HDL File ; E:/Photonic/RISCV/rtl/timer.v ; ;
; rtl/uartTx.v ; yes ; User Verilog HDL File ; E:/Photonic/RISCV/rtl/uartTx.v ; ;
; rtl/xoroshiro128plus.v ; yes ; User Verilog HDL File ; E:/Photonic/RISCV/rtl/xoroshiro128plus.v ; ;
; rtl/prng.v ; yes ; User Verilog HDL File ; E:/Photonic/RISCV/rtl/prng.v ; ;
; rtl/xoro_top.v ; yes ; User Verilog HDL File ; E:/Photonic/RISCV/rtl/xoro_top.v ; ;
; rtl/picorv32.v ; yes ; User Verilog HDL File ; E:/Photonic/RISCV/rtl/picorv32.v ; ;
; rtl/memory.v ; yes ; User Verilog HDL File ; E:/Photonic/RISCV/rtl/memory.v ; ;
; rtl/gpio.v ; yes ; User Verilog HDL File ; E:/Photonic/RISCV/rtl/gpio.v ; ;
; rtl/busInterface.v ; yes ; User Verilog HDL File ; E:/Photonic/RISCV/rtl/busInterface.v ; ;
; rtl/AsyncReceiver.v ; yes ; User Verilog HDL File ; E:/Photonic/RISCV/rtl/AsyncReceiver.v ; ;
; memory.v_toplevel_memory_1_symbol2.bin ; yes ; Auto-Found Unspecified File ; E:/Photonic/RISCV/memory.v_toplevel_memory_1_symbol2.bin ; ;
; memory.v_toplevel_memory_1_symbol1.bin ; yes ; Auto-Found Unspecified File ; E:/Photonic/RISCV/memory.v_toplevel_memory_1_symbol1.bin ; ;
; memory.v_toplevel_memory_1_symbol3.bin ; yes ; Auto-Found Unspecified File ; E:/Photonic/RISCV/memory.v_toplevel_memory_1_symbol3.bin ; ;
; memory.v_toplevel_memory_1_symbol0.bin ; yes ; Auto-Found Unspecified File ; E:/Photonic/RISCV/memory.v_toplevel_memory_1_symbol0.bin ; ;
; altpll.tdf ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/altpll.tdf ; ;
; aglobal150.inc ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/aglobal150.inc ; ;
; stratix_pll.inc ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/stratix_pll.inc ; ;
; stratixii_pll.inc ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/stratixii_pll.inc ; ;
; cycloneii_pll.inc ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/cycloneii_pll.inc ; ;
; db/pll_sys_altpll.v ; yes ; Auto-Generated Megafunction ; E:/Photonic/RISCV/db/pll_sys_altpll.v ; ;
; altsyncram.tdf ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/altsyncram.tdf ; ;
; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
; lpm_mux.inc ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/lpm_mux.inc ; ;
; lpm_decode.inc ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/lpm_decode.inc ; ;
; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
; altrom.inc ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/altrom.inc ; ;
; altram.inc ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/altram.inc ; ;
; altdpram.inc ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/altdpram.inc ; ;
; db/altsyncram_bdi1.tdf ; yes ; Auto-Generated Megafunction ; E:/Photonic/RISCV/db/altsyncram_bdi1.tdf ; ;
; db/xoro.ram0_Memory_a0c6519c.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; E:/Photonic/RISCV/db/xoro.ram0_Memory_a0c6519c.hdl.mif ; ;
; db/decode_jsa.tdf ; yes ; Auto-Generated Megafunction ; E:/Photonic/RISCV/db/decode_jsa.tdf ; ;
; db/decode_c8a.tdf ; yes ; Auto-Generated Megafunction ; E:/Photonic/RISCV/db/decode_c8a.tdf ; ;
; db/mux_3nb.tdf ; yes ; Auto-Generated Megafunction ; E:/Photonic/RISCV/db/mux_3nb.tdf ; ;
; db/altsyncram_cdi1.tdf ; yes ; Auto-Generated Megafunction ; E:/Photonic/RISCV/db/altsyncram_cdi1.tdf ; ;
; db/xoro.ram1_Memory_a0c6519c.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; E:/Photonic/RISCV/db/xoro.ram1_Memory_a0c6519c.hdl.mif ; ;
; db/altsyncram_trd1.tdf ; yes ; Auto-Generated Megafunction ; E:/Photonic/RISCV/db/altsyncram_trd1.tdf ; ;
; db/altsyncram_edi1.tdf ; yes ; Auto-Generated Megafunction ; E:/Photonic/RISCV/db/altsyncram_edi1.tdf ; ;
; db/xoro.ram3_Memory_a0c6519c.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; E:/Photonic/RISCV/db/xoro.ram3_Memory_a0c6519c.hdl.mif ; ;
; db/altsyncram_ddi1.tdf ; yes ; Auto-Generated Megafunction ; E:/Photonic/RISCV/db/altsyncram_ddi1.tdf ; ;
; db/xoro.ram2_Memory_a0c6519c.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; E:/Photonic/RISCV/db/xoro.ram2_Memory_a0c6519c.hdl.mif ; ;
; db/altsyncram_s9c1.tdf ; yes ; Auto-Generated Megafunction ; E:/Photonic/RISCV/db/altsyncram_s9c1.tdf ; ;
; lpm_mult.tdf ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/lpm_mult.tdf ; ;
; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/lpm_add_sub.inc ; ;
; multcore.inc ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/multcore.inc ; ;
; bypassff.inc ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/bypassff.inc ; ;
; altshift.inc ; yes ; Megafunction ; c:/altera/15.0/quartus/libraries/megafunctions/altshift.inc ; ;
; db/mult_86t.tdf ; yes ; Auto-Generated Megafunction ; E:/Photonic/RISCV/db/mult_86t.tdf ; ;
+----------------------------------------+-----------------+-------------------------------------------------------+----------------------------------------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+---------------------------------------------------------------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+---------------------------------------------------------------------------------------------+
; Estimated Total logic elements ; 3,155 ;
; ; ;
; Total combinational functions ; 2709 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 1274 ;
; -- 3 input functions ; 1043 ;
; -- <=2 input functions ; 392 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 2148 ;
; -- arithmetic mode ; 561 ;
; ; ;
; Total registers ; 1420 ;
; -- Dedicated logic registers ; 1420 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 46 ;
; Total memory bits ; 330016 ;
; ; ;
; Embedded Multiplier 9-bit elements ; 8 ;
; ; ;
; Total PLLs ; 1 ;
; -- PLLs ; 1 ;
; ; ;
; Maximum fan-out node ; pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] ;
; Maximum fan-out ; 1399 ;
; Total fan-out ; 16283 ;
; Average fan-out ; 3.73 ;
+---------------------------------------------+---------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------+--------------+
; |xoro_top ; 2709 (11) ; 1420 (9) ; 330016 ; 8 ; 0 ; 4 ; 46 ; 0 ; |xoro_top ; work ;
; |AsyncReceiver:uartRx| ; 110 (75) ; 78 (36) ; 256 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|AsyncReceiver:uartRx ; work ;
; |Fifo:fifo_1| ; 35 (35) ; 42 (42) ; 256 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|AsyncReceiver:uartRx|Fifo:fifo_1 ; work ;
; |altsyncram:mem_rtl_0| ; 0 (0) ; 0 (0) ; 256 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0 ; work ;
; |altsyncram_s9c1:auto_generated| ; 0 (0) ; 0 (0) ; 256 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0|altsyncram_s9c1:auto_generated ; work ;
; |Memory:mem| ; 70 (54) ; 192 (180) ; 327712 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|Memory:mem ; work ;
; |altsyncram:memory_1_symbol0_rtl_0| ; 4 (0) ; 3 (0) ; 81928 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol0_rtl_0 ; work ;
; |altsyncram_bdi1:auto_generated| ; 4 (2) ; 3 (3) ; 81928 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated ; work ;
; |decode_jsa:decode2| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated|decode_jsa:decode2 ; work ;
; |altsyncram:memory_1_symbol1_rtl_0| ; 4 (0) ; 3 (0) ; 81928 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol1_rtl_0 ; work ;
; |altsyncram_cdi1:auto_generated| ; 4 (2) ; 3 (3) ; 81928 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated ; work ;
; |decode_jsa:decode2| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated|decode_jsa:decode2 ; work ;
; |altsyncram:memory_1_symbol2_rtl_0| ; 4 (0) ; 3 (0) ; 81928 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol2_rtl_0 ; work ;
; |altsyncram_ddi1:auto_generated| ; 4 (2) ; 3 (3) ; 81928 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated ; work ;
; |decode_jsa:decode2| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated|decode_jsa:decode2 ; work ;
; |altsyncram:memory_1_symbol3_rtl_0| ; 4 (0) ; 3 (0) ; 81928 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol3_rtl_0 ; work ;
; |altsyncram_edi1:auto_generated| ; 4 (2) ; 3 (3) ; 81928 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated ; work ;
; |decode_jsa:decode2| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated|decode_jsa:decode2 ; work ;
; |busInterface:busInterface| ; 171 (171) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|busInterface:busInterface ; work ;
; |gpio:gpio| ; 10 (10) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|gpio:gpio ; work ;
; |picorv32:cpu| ; 2112 (1671) ; 866 (533) ; 2048 ; 8 ; 0 ; 4 ; 0 ; 0 ; |xoro_top|picorv32:cpu ; work ;
; |altsyncram:cpuregs_rtl_0| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|picorv32:cpu|altsyncram:cpuregs_rtl_0 ; work ;
; |altsyncram_trd1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|picorv32:cpu|altsyncram:cpuregs_rtl_0|altsyncram_trd1:auto_generated ; work ;
; |altsyncram:cpuregs_rtl_1| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|picorv32:cpu|altsyncram:cpuregs_rtl_1 ; work ;
; |altsyncram_trd1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|picorv32:cpu|altsyncram:cpuregs_rtl_1|altsyncram_trd1:auto_generated ; work ;
; |picorv32_pcpi_div:pcpi_div| ; 343 (343) ; 200 (200) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|picorv32:cpu|picorv32_pcpi_div:pcpi_div ; work ;
; |picorv32_pcpi_fast_mul:pcpi_mul| ; 98 (52) ; 133 (133) ; 0 ; 8 ; 0 ; 4 ; 0 ; 0 ; |xoro_top|picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul ; work ;
; |lpm_mult:Mult0| ; 46 (0) ; 0 (0) ; 0 ; 8 ; 0 ; 4 ; 0 ; 0 ; |xoro_top|picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0 ; work ;
; |mult_86t:auto_generated| ; 46 (46) ; 0 (0) ; 0 ; 8 ; 0 ; 4 ; 0 ; 0 ; |xoro_top|picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0|mult_86t:auto_generated ; work ;
; |pll_sys:pll_sys_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|pll_sys:pll_sys_inst ; work ;
; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|pll_sys:pll_sys_inst|altpll:altpll_component ; work ;
; |pll_sys_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated ; work ;
; |prng:prng| ; 160 (1) ; 193 (34) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|prng:prng ; work ;
; |xoroshiro128plus:prng| ; 159 (159) ; 159 (159) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|prng:prng|xoroshiro128plus:prng ; work ;
; |timer:timer| ; 33 (33) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|timer:timer ; work ;
; |uartTx:uartTx| ; 32 (26) ; 32 (26) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|uartTx:uartTx ; work ;
; |BaudRateGenerator:baudRateGenerator| ; 6 (4) ; 6 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|uartTx:uartTx|BaudRateGenerator:baudRateGenerator ; work ;
; |EdgeDetect:baudClockEdgeDetect| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|uartTx:uartTx|BaudRateGenerator:baudRateGenerator|EdgeDetect:baudClockEdgeDetect ; work ;
; |EdgeDetect:bitClockEdgeDetect| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |xoro_top|uartTx:uartTx|BaudRateGenerator:baudRateGenerator|EdgeDetect:bitClockEdgeDetect ; work ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+-------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
; AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0|altsyncram_s9c1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 8 ; 32 ; 8 ; 256 ; None ;
; Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 10241 ; 8 ; 10241 ; 8 ; 81928 ; db/xoro.ram0_Memory_a0c6519c.hdl.mif ;
; Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 10241 ; 8 ; 10241 ; 8 ; 81928 ; db/xoro.ram1_Memory_a0c6519c.hdl.mif ;
; Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 10241 ; 8 ; 10241 ; 8 ; 81928 ; db/xoro.ram2_Memory_a0c6519c.hdl.mif ;
; Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 10241 ; 8 ; 10241 ; 8 ; 81928 ; db/xoro.ram3_Memory_a0c6519c.hdl.mif ;
; picorv32:cpu|altsyncram:cpuregs_rtl_0|altsyncram_trd1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; None ;
; picorv32:cpu|altsyncram:cpuregs_rtl_1|altsyncram_trd1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; None ;
+-------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary ;
+---------------------------------------+-------------+
; Statistic ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit) ; 0 ;
; Simple Multipliers (18-bit) ; 4 ;
; Embedded Multiplier Blocks ; -- ;
; Embedded Multiplier 9-bit elements ; 8 ;
; Signed Embedded Multipliers ; 1 ;
; Unsigned Embedded Multipliers ; 1 ;
; Mixed Sign Embedded Multipliers ; 2 ;
; Variable Sign Embedded Multipliers ; 0 ;
; Dedicated Input Shift Register Chains ; 0 ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.
Encoding Type: One-Hot
+-----------------------------------------------------------------------+
; State Machine - |xoro_top|picorv32:cpu|mem_wordsize ;
+-----------------+-----------------+-----------------+-----------------+
; Name ; mem_wordsize.00 ; mem_wordsize.10 ; mem_wordsize.01 ;
+-----------------+-----------------+-----------------+-----------------+
; mem_wordsize.00 ; 0 ; 0 ; 0 ;
; mem_wordsize.01 ; 1 ; 0 ; 1 ;
; mem_wordsize.10 ; 1 ; 1 ; 0 ;
+-----------------+-----------------+-----------------+-----------------+
Encoding Type: One-Hot
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |xoro_top|picorv32:cpu|cpu_state ;
+----------------------------+--------------------------+---------------------------+----------------------------+----------------------------+--------------------------+---------------------------+---------------------------+---------------------------+
; Name ; cpu_state.cpu_state_trap ; cpu_state.cpu_state_fetch ; cpu_state.cpu_state_ld_rs1 ; cpu_state.cpu_state_ld_rs2 ; cpu_state.cpu_state_exec ; cpu_state.cpu_state_shift ; cpu_state.cpu_state_stmem ; cpu_state.cpu_state_ldmem ;
+----------------------------+--------------------------+---------------------------+----------------------------+----------------------------+--------------------------+---------------------------+---------------------------+---------------------------+
; cpu_state.cpu_state_trap ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; cpu_state.cpu_state_stmem ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ;
; cpu_state.cpu_state_shift ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ;
; cpu_state.cpu_state_exec ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ;
; cpu_state.cpu_state_ld_rs2 ; 1 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ;
; cpu_state.cpu_state_ld_rs1 ; 1 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; cpu_state.cpu_state_fetch ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; cpu_state.cpu_state_ldmem ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+----------------------------+--------------------------+---------------------------+----------------------------+----------------------------+--------------------------+---------------------------+---------------------------+---------------------------+
Encoding Type: One-Hot
+------------------------------------------------------+
; State Machine - |xoro_top|AsyncReceiver:uartRx|state ;
+----------+----------+----------+----------+----------+
; Name ; state.11 ; state.10 ; state.01 ; state.00 ;
+----------+----------+----------+----------+----------+
; state.00 ; 0 ; 0 ; 0 ; 0 ;
; state.01 ; 0 ; 0 ; 1 ; 1 ;
; state.10 ; 0 ; 1 ; 0 ; 1 ;
; state.11 ; 1 ; 0 ; 0 ; 1 ;
+----------+----------+----------+----------+----------+
Encoding Type: One-Hot
+-------------------------------------------------------------------+
; State Machine - |xoro_top|uartTx:uartTx|state ;
+----------------+----------------+----------------+----------------+
; Name ; state.00000000 ; state.00000010 ; state.00000001 ;
+----------------+----------------+----------------+----------------+
; state.00000000 ; 0 ; 0 ; 0 ;
; state.00000001 ; 1 ; 0 ; 1 ;
; state.00000010 ; 1 ; 1 ; 0 ;
+----------------+----------------+----------------+----------------+
+------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------------------+-------------------------------------------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------------------+-------------------------------------------------------------+
; picorv32:cpu|instr_retirq ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|instr_waitirq ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|decoded_imm_uj[0] ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|compressed_instr ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|instr_rdcycle ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|instr_rdcycleh ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|instr_rdinstr ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|instr_rdinstrh ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|instr_getq ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|instr_setq ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|instr_maskirq ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|instr_timer ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|do_waitirq ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|mem_addr[0,1] ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|latched_compr ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|decoded_imm_uj[20..30] ; Merged with picorv32:cpu|decoded_imm_uj[31] ;
; picorv32:cpu|decoded_rs1[4] ; Merged with picorv32:cpu|decoded_imm_uj[19] ;
; picorv32:cpu|decoded_rs1[3] ; Merged with picorv32:cpu|decoded_imm_uj[18] ;
; picorv32:cpu|decoded_rs1[2] ; Merged with picorv32:cpu|decoded_imm_uj[17] ;
; picorv32:cpu|decoded_rs1[1] ; Merged with picorv32:cpu|decoded_imm_uj[16] ;
; picorv32:cpu|decoded_rs1[0] ; Merged with picorv32:cpu|decoded_imm_uj[15] ;
; picorv32:cpu|decoded_rs2[0] ; Merged with picorv32:cpu|decoded_imm_uj[11] ;
; picorv32:cpu|decoded_rs2[4] ; Merged with picorv32:cpu|decoded_imm_uj[4] ;
; picorv32:cpu|decoded_rs2[3] ; Merged with picorv32:cpu|decoded_imm_uj[3] ;
; picorv32:cpu|decoded_rs2[2] ; Merged with picorv32:cpu|decoded_imm_uj[2] ;
; picorv32:cpu|decoded_rs2[1] ; Merged with picorv32:cpu|decoded_imm_uj[1] ;
; picorv32:cpu|reg_next_pc[0] ; Merged with picorv32:cpu|reg_pc[0] ;
; picorv32:cpu|picorv32_pcpi_div:pcpi_div|pcpi_ready ; Merged with picorv32:cpu|picorv32_pcpi_div:pcpi_div|pcpi_wr ;
; AsyncReceiver:uartRx|_zz_3 ; Merged with AsyncReceiver:uartRx|_zz_1 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|_zz_3 ; Merged with AsyncReceiver:uartRx|Fifo:fifo_1|_zz_1 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|_zz_4 ; Merged with AsyncReceiver:uartRx|Fifo:fifo_1|_zz_2 ;
; picorv32:cpu|reg_pc[0] ; Stuck at GND due to stuck port data_in ;
; prng:prng|xoroshiro128plus:prng|s1[36] ; Merged with prng:prng|xoroshiro128plus:prng|ss[0] ;
; picorv32:cpu|latched_is_lu ; Lost fanout ;
; picorv32:cpu|is_lbu_lhu_lw ; Lost fanout ;
; AsyncReceiver:uartRx|state~4 ; Lost fanout ;
; AsyncReceiver:uartRx|state~5 ; Lost fanout ;
; uartTx:uartTx|state~9 ; Lost fanout ;
; uartTx:uartTx|state~10 ; Lost fanout ;
; uartTx:uartTx|state~11 ; Lost fanout ;
; uartTx:uartTx|state~12 ; Lost fanout ;
; uartTx:uartTx|state~13 ; Lost fanout ;
; uartTx:uartTx|state~14 ; Lost fanout ;
; picorv32:cpu|cpu_state.cpu_state_shift ; Stuck at GND due to stuck port data_in ;
; picorv32:cpu|cpu_state.cpu_state_ld_rs2 ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 56 ; ;
+----------------------------------------------------+-------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+-------------------------------+---------------------------+----------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+-------------------------------+---------------------------+----------------------------------------+
; picorv32:cpu|compressed_instr ; Stuck at GND ; picorv32:cpu|latched_compr ;
; ; due to stuck port data_in ; ;
; picorv32:cpu|latched_is_lu ; Lost Fanouts ; picorv32:cpu|is_lbu_lhu_lw ;
+-------------------------------+---------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 1420 ;
; Number of registers using Synchronous Clear ; 129 ;
; Number of registers using Synchronous Load ; 172 ;
; Number of registers using Asynchronous Clear ; 242 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 660 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------+
; Inverted Register Statistics ;
+---------------------------------------------------------------------+---------+
; Inverted Register ; Fan out ;
+---------------------------------------------------------------------+---------+
; uartTx:uartTx|serialOut ; 2 ;
; uartTx:uartTx|bufferEmpty ; 9 ;
; uartTx:uartTx|BaudRateGenerator:baudRateGenerator|baudClockcount[2] ; 2 ;
; uartTx:uartTx|BaudRateGenerator:baudRateGenerator|baudClockcount[0] ; 4 ;
; uartTx:uartTx|BaudRateGenerator:baudRateGenerator|baudClockcount[1] ; 3 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[42] ; 1 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[41] ; 1 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[42] ; 1 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[42] ; 1 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[41] ; 1 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[42] ; 1 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[38] ; 1 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[38] ; 1 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[38] ; 1 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[38] ; 1 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[40] ; 1 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[39] ; 1 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[40] ; 1 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[40] ; 1 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[40] ; 1 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[44] ; 1 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[44] ; 1 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[44] ; 1 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[44] ; 1 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[36] ; 1 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[36] ; 1 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[35] ; 1 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[34] ; 1 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[34] ; 1 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[32] ; 1 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[32] ; 1 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[30] ; 1 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[30] ; 1 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[30] ; 1 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[36] ; 1 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[34] ; 1 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[32] ; 1 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[32] ; 1 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[31] ; 1 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[30] ; 1 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[29] ; 1 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[36] ; 1 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[35] ; 1 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[34] ; 1 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[33] ; 1 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|empty ; 5 ;
; prng:prng|xoroshiro128plus:prng|s0[0] ; 2 ;
; Total number of inverted registers = 47 ; ;
+---------------------------------------------------------------------+---------+
+----------------------------------------------------------------------------------------------------+
; Registers Added for RAM Pass-Through Logic ;
+-------------------------------------------------------+--------------------------------------------+
; Register Name ; RAM Name ;
+-------------------------------------------------------+--------------------------------------------+
; Memory:mem|memory_1_symbol0_rtl_0_bypass[0] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[1] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[2] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[3] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[4] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[5] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[6] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[7] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[8] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[9] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[10] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[11] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[12] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[13] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[14] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[15] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[16] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[17] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[18] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[19] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[20] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[21] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[22] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[23] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[24] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[25] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[26] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[27] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[28] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[29] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[30] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[31] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[32] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[33] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[34] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[35] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[36] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[37] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[38] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[39] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[40] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[41] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[42] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[43] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol0_rtl_0_bypass[44] ; Memory:mem|memory_1_symbol0_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[0] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[1] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[2] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[3] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[4] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[5] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[6] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[7] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[8] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[9] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[10] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[11] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[12] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[13] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[14] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[15] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[16] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[17] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[18] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[19] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[20] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[21] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[22] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[23] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[24] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[25] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[26] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[27] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[28] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[29] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[30] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[31] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[32] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[33] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[34] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[35] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[36] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[37] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[38] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[39] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[40] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[41] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[42] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[43] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; Memory:mem|memory_1_symbol1_rtl_0_bypass[44] ; Memory:mem|memory_1_symbol1_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[0] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[1] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[2] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[3] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[4] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[5] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[6] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[7] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[8] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[9] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[10] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[11] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[12] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[13] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[14] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[15] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[16] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[17] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[18] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[19] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[20] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[21] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[22] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[23] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[24] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[25] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[26] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[27] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[28] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[29] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[30] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[31] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[32] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[33] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[34] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[35] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[36] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[37] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[38] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[39] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[40] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[41] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_0_bypass[42] ; picorv32:cpu|cpuregs_rtl_0 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[0] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[1] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[2] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[3] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[4] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[5] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[6] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[7] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[8] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[9] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[10] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[11] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[12] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[13] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[14] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[15] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[16] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[17] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[18] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[19] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[20] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[21] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[22] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[23] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[24] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[25] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[26] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[27] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[28] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[29] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[30] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[31] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[32] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[33] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[34] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[35] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[36] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[37] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[38] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[39] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[40] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[41] ; picorv32:cpu|cpuregs_rtl_1 ;
; picorv32:cpu|cpuregs_rtl_1_bypass[42] ; picorv32:cpu|cpuregs_rtl_1 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[0] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[1] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[2] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[3] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[4] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[5] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[6] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[7] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[8] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[9] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[10] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[11] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[12] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[13] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[14] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[15] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[16] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[17] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[18] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[19] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[20] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[21] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[22] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[23] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[24] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[25] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[26] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[27] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[28] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[29] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[30] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[31] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[32] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[33] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[34] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[35] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[36] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[37] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[38] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[39] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[40] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[41] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[42] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[43] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol3_rtl_0_bypass[44] ; Memory:mem|memory_1_symbol3_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[0] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[1] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[2] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[3] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[4] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[5] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[6] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[7] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[8] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[9] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[10] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[11] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[12] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[13] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[14] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[15] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[16] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[17] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[18] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[19] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[20] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[21] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[22] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[23] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[24] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[25] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[26] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[27] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[28] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[29] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[30] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[31] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[32] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[33] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[34] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[35] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[36] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[37] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[38] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[39] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[40] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[41] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[42] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[43] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; Memory:mem|memory_1_symbol2_rtl_0_bypass[44] ; Memory:mem|memory_1_symbol2_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[0] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[1] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[2] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[3] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[4] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[5] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[6] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[7] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[8] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[9] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[10] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[11] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[12] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[13] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[14] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[15] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[16] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[17] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0_bypass[18] ; AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0 ;
+-------------------------------------------------------+--------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------+
; 3:1 ; 31 bits ; 62 LEs ; 31 LEs ; 31 LEs ; Yes ; |xoro_top|picorv32:cpu|reg_pc[22] ;
; 3:1 ; 22 bits ; 44 LEs ; 22 LEs ; 22 LEs ; Yes ; |xoro_top|picorv32:cpu|instr_sltiu ;
; 3:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|mem_addr[29] ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |xoro_top|picorv32:cpu|pcpi_timeout_counter[0] ;
; 3:1 ; 62 bits ; 124 LEs ; 62 LEs ; 62 LEs ; Yes ; |xoro_top|picorv32:cpu|picorv32_pcpi_div:pcpi_div|divisor[21] ;
; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|picorv32_pcpi_div:pcpi_div|pcpi_rd[15] ;
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |xoro_top|picorv32:cpu|reg_sh[0] ;
; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|reg_sh[3] ;
; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|mem_wdata[31] ;
; 4:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |xoro_top|gpio:gpio|gpio[0] ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |xoro_top|picorv32:cpu|mem_wstrb[1] ;
; 4:1 ; 31 bits ; 62 LEs ; 62 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|picorv32_pcpi_div:pcpi_div|divisor[31] ;
; 5:1 ; 30 bits ; 90 LEs ; 60 LEs ; 30 LEs ; Yes ; |xoro_top|picorv32:cpu|reg_next_pc[15] ;
; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |xoro_top|picorv32:cpu|latched_rd[4] ;
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|decoded_imm[5] ;
; 3:1 ; 19 bits ; 38 LEs ; 38 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|decoded_imm[14] ;
; 4:1 ; 5 bits ; 10 LEs ; 0 LEs ; 10 LEs ; Yes ; |xoro_top|AsyncReceiver:uartRx|Fifo:fifo_1|head[3] ;
; 5:1 ; 32 bits ; 96 LEs ; 64 LEs ; 32 LEs ; Yes ; |xoro_top|picorv32:cpu|picorv32_pcpi_div:pcpi_div|dividend[26] ;
; 5:1 ; 4 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |xoro_top|uartTx:uartTx|bitCount[3] ;
; 5:1 ; 7 bits ; 21 LEs ; 7 LEs ; 14 LEs ; Yes ; |xoro_top|uartTx:uartTx|shifter[1] ;
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|decoded_imm[4] ;
; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |xoro_top|AsyncReceiver:uartRx|bitTimer[3] ;
; 6:1 ; 5 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |xoro_top|picorv32:cpu|reg_op2[1] ;
; 11:1 ; 2 bits ; 14 LEs ; 6 LEs ; 8 LEs ; Yes ; |xoro_top|picorv32:cpu|mem_state[0] ;
; 10:1 ; 8 bits ; 48 LEs ; 48 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|alu_out_q[19] ;
; 10:1 ; 8 bits ; 48 LEs ; 48 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|alu_out_q[9] ;
; 7:1 ; 27 bits ; 108 LEs ; 54 LEs ; 54 LEs ; Yes ; |xoro_top|picorv32:cpu|reg_op2[28] ;
; 11:1 ; 4 bits ; 28 LEs ; 28 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|alu_out_q[24] ;
; 11:1 ; 4 bits ; 28 LEs ; 28 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|alu_out_q[4] ;
; 7:1 ; 8 bits ; 32 LEs ; 32 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|reg_out[15] ;
; 12:1 ; 2 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|alu_out_q[29] ;
; 12:1 ; 2 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|alu_out_q[3] ;
; 13:1 ; 2 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|alu_out_q[30] ;
; 9:1 ; 16 bits ; 96 LEs ; 96 LEs ; 0 LEs ; Yes ; |xoro_top|picorv32:cpu|reg_out[30] ;
; 9:1 ; 7 bits ; 42 LEs ; 35 LEs ; 7 LEs ; Yes ; |xoro_top|picorv32:cpu|reg_out[1] ;
; 16:1 ; 3 bits ; 30 LEs ; 12 LEs ; 18 LEs ; Yes ; |xoro_top|picorv32:cpu|reg_op1[30] ;
; 17:1 ; 3 bits ; 33 LEs ; 15 LEs ; 18 LEs ; Yes ; |xoro_top|picorv32:cpu|reg_op1[3] ;
; 17:1 ; 24 bits ; 264 LEs ; 144 LEs ; 120 LEs ; Yes ; |xoro_top|picorv32:cpu|reg_op1[17] ;
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |xoro_top|AsyncReceiver:uartRx|state ;
; 3:1 ; 31 bits ; 62 LEs ; 31 LEs ; 31 LEs ; No ; |xoro_top|picorv32:cpu|current_pc ;
; 3:1 ; 14 bits ; 28 LEs ; 28 LEs ; 0 LEs ; No ; |xoro_top|picorv32:cpu|mem_la_addr[15] ;
; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |xoro_top|picorv32:cpu|cpuregs_rs2[0] ;
; 3:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; No ; |xoro_top|AsyncReceiver:uartRx|Fifo:fifo_1|mem ;
; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; No ; |xoro_top|picorv32:cpu|latched_is_lh ;
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |xoro_top|picorv32:cpu|Selector41 ;
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |xoro_top|picorv32:cpu|Selector44 ;
; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; No ; |xoro_top|AsyncReceiver:uartRx|Fifo:fifo_1|tail ;
; 9:1 ; 3 bits ; 18 LEs ; 6 LEs ; 12 LEs ; No ; |xoro_top|picorv32:cpu|mem_wordsize ;
; 19:1 ; 5 bits ; 60 LEs ; 35 LEs ; 25 LEs ; No ; |xoro_top|picorv32:cpu|cpu_state ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------+
; Source assignments for Memory:mem|altsyncram:memory_1_symbol0_rtl_0|altsyncram_bdi1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+--------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+--------------------------------------+
+----------------------------------------------------------------------------------------------------+
; Source assignments for Memory:mem|altsyncram:memory_1_symbol1_rtl_0|altsyncram_cdi1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+--------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+--------------------------------------+
+---------------------------------------------------------------------------------------------+
; Source assignments for picorv32:cpu|altsyncram:cpuregs_rtl_0|altsyncram_trd1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-------------------------------+
+---------------------------------------------------------------------------------------------+
; Source assignments for picorv32:cpu|altsyncram:cpuregs_rtl_1|altsyncram_trd1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-------------------------------+
+----------------------------------------------------------------------------------------------------+
; Source assignments for Memory:mem|altsyncram:memory_1_symbol3_rtl_0|altsyncram_edi1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+--------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+--------------------------------------+
+----------------------------------------------------------------------------------------------------+
; Source assignments for Memory:mem|altsyncram:memory_1_symbol2_rtl_0|altsyncram_ddi1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+--------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+--------------------------------------+
+-------------------------------------------------------------------------------------------------------------+
; Source assignments for AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0|altsyncram_s9c1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-----------------------------------------------+
+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pll_sys:pll_sys_inst|altpll:altpll_component ;
+-------------------------------+---------------------------+-------------------------------+
; Parameter Name ; Value ; Type ;
+-------------------------------+---------------------------+-------------------------------+
; OPERATION_MODE ; NORMAL ; Untyped ;
; PLL_TYPE ; AUTO ; Untyped ;
; LPM_HINT ; CBX_MODULE_PREFIX=pll_sys ; Untyped ;
; QUALIFY_CONF_DONE ; OFF ; Untyped ;
; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
; SCAN_CHAIN ; LONG ; Untyped ;
; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
; INCLK0_INPUT_FREQUENCY ; 20000 ; Signed Integer ;
; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
; GATE_LOCK_SIGNAL ; NO ; Untyped ;
; GATE_LOCK_COUNTER ; 0 ; Untyped ;
; LOCK_HIGH ; 1 ; Untyped ;
; LOCK_LOW ; 1 ; Untyped ;
; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;
; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;
; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
; SKIP_VCO ; OFF ; Untyped ;
; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
; BANDWIDTH ; 0 ; Untyped ;
; BANDWIDTH_TYPE ; AUTO ; Untyped ;
; SPREAD_FREQUENCY ; 0 ; Untyped ;
; DOWN_SPREAD ; 0 ; Untyped ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
; SELF_RESET_ON_LOSS_LOCK ; ON ; Untyped ;
; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
; CLK2_MULTIPLY_BY ; 576 ; Signed Integer ;
; CLK1_MULTIPLY_BY ; 2304 ; Signed Integer ;
; CLK0_MULTIPLY_BY ; 2 ; Signed Integer ;
; CLK9_DIVIDE_BY ; 0 ; Untyped ;
; CLK8_DIVIDE_BY ; 0 ; Untyped ;
; CLK7_DIVIDE_BY ; 0 ; Untyped ;
; CLK6_DIVIDE_BY ; 0 ; Untyped ;
; CLK5_DIVIDE_BY ; 1 ; Untyped ;
; CLK4_DIVIDE_BY ; 1 ; Untyped ;
; CLK3_DIVIDE_BY ; 1 ; Untyped ;
; CLK2_DIVIDE_BY ; 15625 ; Signed Integer ;
; CLK1_DIVIDE_BY ; 15625 ; Signed Integer ;
; CLK0_DIVIDE_BY ; 1 ; Signed Integer ;
; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
; CLK5_TIME_DELAY ; 0 ; Untyped ;
; CLK4_TIME_DELAY ; 0 ; Untyped ;
; CLK3_TIME_DELAY ; 0 ; Untyped ;
; CLK2_TIME_DELAY ; 0 ; Untyped ;
; CLK1_TIME_DELAY ; 0 ; Untyped ;
; CLK0_TIME_DELAY ; 0 ; Untyped ;
; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
; CLK2_DUTY_CYCLE ; 50 ; Signed Integer ;
; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ;
; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;
; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;
; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;
; DPA_MULTIPLY_BY ; 0 ; Untyped ;
; DPA_DIVIDE_BY ; 1 ; Untyped ;
; DPA_DIVIDER ; 0 ; Untyped ;
; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
; VCO_MULTIPLY_BY ; 0 ; Untyped ;
; VCO_DIVIDE_BY ; 0 ; Untyped ;
; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
; VCO_MIN ; 0 ; Untyped ;
; VCO_MAX ; 0 ; Untyped ;
; VCO_CENTER ; 0 ; Untyped ;
; PFD_MIN ; 0 ; Untyped ;
; PFD_MAX ; 0 ; Untyped ;
; M_INITIAL ; 0 ; Untyped ;
; M ; 0 ; Untyped ;
; N ; 1 ; Untyped ;
; M2 ; 1 ; Untyped ;
; N2 ; 1 ; Untyped ;
; SS ; 1 ; Untyped ;
; C0_HIGH ; 0 ; Untyped ;
; C1_HIGH ; 0 ; Untyped ;
; C2_HIGH ; 0 ; Untyped ;
; C3_HIGH ; 0 ; Untyped ;
; C4_HIGH ; 0 ; Untyped ;
; C5_HIGH ; 0 ; Untyped ;
; C6_HIGH ; 0 ; Untyped ;
; C7_HIGH ; 0 ; Untyped ;
; C8_HIGH ; 0 ; Untyped ;
; C9_HIGH ; 0 ; Untyped ;
; C0_LOW ; 0 ; Untyped ;
; C1_LOW ; 0 ; Untyped ;
; C2_LOW ; 0 ; Untyped ;
; C3_LOW ; 0 ; Untyped ;
; C4_LOW ; 0 ; Untyped ;
; C5_LOW ; 0 ; Untyped ;
; C6_LOW ; 0 ; Untyped ;
; C7_LOW ; 0 ; Untyped ;
; C8_LOW ; 0 ; Untyped ;
; C9_LOW ; 0 ; Untyped ;
; C0_INITIAL ; 0 ; Untyped ;
; C1_INITIAL ; 0 ; Untyped ;
; C2_INITIAL ; 0 ; Untyped ;
; C3_INITIAL ; 0 ; Untyped ;
; C4_INITIAL ; 0 ; Untyped ;
; C5_INITIAL ; 0 ; Untyped ;
; C6_INITIAL ; 0 ; Untyped ;
; C7_INITIAL ; 0 ; Untyped ;
; C8_INITIAL ; 0 ; Untyped ;
; C9_INITIAL ; 0 ; Untyped ;
; C0_MODE ; BYPASS ; Untyped ;
; C1_MODE ; BYPASS ; Untyped ;
; C2_MODE ; BYPASS ; Untyped ;
; C3_MODE ; BYPASS ; Untyped ;
; C4_MODE ; BYPASS ; Untyped ;
; C5_MODE ; BYPASS ; Untyped ;
; C6_MODE ; BYPASS ; Untyped ;
; C7_MODE ; BYPASS ; Untyped ;
; C8_MODE ; BYPASS ; Untyped ;
; C9_MODE ; BYPASS ; Untyped ;
; C0_PH ; 0 ; Untyped ;
; C1_PH ; 0 ; Untyped ;
; C2_PH ; 0 ; Untyped ;
; C3_PH ; 0 ; Untyped ;
; C4_PH ; 0 ; Untyped ;
; C5_PH ; 0 ; Untyped ;
; C6_PH ; 0 ; Untyped ;
; C7_PH ; 0 ; Untyped ;
; C8_PH ; 0 ; Untyped ;
; C9_PH ; 0 ; Untyped ;
; L0_HIGH ; 1 ; Untyped ;
; L1_HIGH ; 1 ; Untyped ;
; G0_HIGH ; 1 ; Untyped ;
; G1_HIGH ; 1 ; Untyped ;
; G2_HIGH ; 1 ; Untyped ;
; G3_HIGH ; 1 ; Untyped ;
; E0_HIGH ; 1 ; Untyped ;
; E1_HIGH ; 1 ; Untyped ;
; E2_HIGH ; 1 ; Untyped ;
; E3_HIGH ; 1 ; Untyped ;
; L0_LOW ; 1 ; Untyped ;
; L1_LOW ; 1 ; Untyped ;
; G0_LOW ; 1 ; Untyped ;
; G1_LOW ; 1 ; Untyped ;
; G2_LOW ; 1 ; Untyped ;
; G3_LOW ; 1 ; Untyped ;
; E0_LOW ; 1 ; Untyped ;
; E1_LOW ; 1 ; Untyped ;
; E2_LOW ; 1 ; Untyped ;
; E3_LOW ; 1 ; Untyped ;
; L0_INITIAL ; 1 ; Untyped ;
; L1_INITIAL ; 1 ; Untyped ;
; G0_INITIAL ; 1 ; Untyped ;
; G1_INITIAL ; 1 ; Untyped ;
; G2_INITIAL ; 1 ; Untyped ;
; G3_INITIAL ; 1 ; Untyped ;
; E0_INITIAL ; 1 ; Untyped ;
; E1_INITIAL ; 1 ; Untyped ;
; E2_INITIAL ; 1 ; Untyped ;
; E3_INITIAL ; 1 ; Untyped ;
; L0_MODE ; BYPASS ; Untyped ;
; L1_MODE ; BYPASS ; Untyped ;
; G0_MODE ; BYPASS ; Untyped ;
; G1_MODE ; BYPASS ; Untyped ;
; G2_MODE ; BYPASS ; Untyped ;
; G3_MODE ; BYPASS ; Untyped ;
; E0_MODE ; BYPASS ; Untyped ;
; E1_MODE ; BYPASS ; Untyped ;
; E2_MODE ; BYPASS ; Untyped ;
; E3_MODE ; BYPASS ; Untyped ;
; L0_PH ; 0 ; Untyped ;
; L1_PH ; 0 ; Untyped ;
; G0_PH ; 0 ; Untyped ;
; G1_PH ; 0 ; Untyped ;
; G2_PH ; 0 ; Untyped ;
; G3_PH ; 0 ; Untyped ;
; E0_PH ; 0 ; Untyped ;
; E1_PH ; 0 ; Untyped ;
; E2_PH ; 0 ; Untyped ;
; E3_PH ; 0 ; Untyped ;
; M_PH ; 0 ; Untyped ;
; C1_USE_CASC_IN ; OFF ; Untyped ;
; C2_USE_CASC_IN ; OFF ; Untyped ;
; C3_USE_CASC_IN ; OFF ; Untyped ;
; C4_USE_CASC_IN ; OFF ; Untyped ;
; C5_USE_CASC_IN ; OFF ; Untyped ;
; C6_USE_CASC_IN ; OFF ; Untyped ;
; C7_USE_CASC_IN ; OFF ; Untyped ;
; C8_USE_CASC_IN ; OFF ; Untyped ;
; C9_USE_CASC_IN ; OFF ; Untyped ;
; CLK0_COUNTER ; G0 ; Untyped ;
; CLK1_COUNTER ; G0 ; Untyped ;
; CLK2_COUNTER ; G0 ; Untyped ;
; CLK3_COUNTER ; G0 ; Untyped ;
; CLK4_COUNTER ; G0 ; Untyped ;
; CLK5_COUNTER ; G0 ; Untyped ;
; CLK6_COUNTER ; E0 ; Untyped ;
; CLK7_COUNTER ; E1 ; Untyped ;
; CLK8_COUNTER ; E2 ; Untyped ;
; CLK9_COUNTER ; E3 ; Untyped ;
; L0_TIME_DELAY ; 0 ; Untyped ;
; L1_TIME_DELAY ; 0 ; Untyped ;
; G0_TIME_DELAY ; 0 ; Untyped ;
; G1_TIME_DELAY ; 0 ; Untyped ;
; G2_TIME_DELAY ; 0 ; Untyped ;
; G3_TIME_DELAY ; 0 ; Untyped ;
; E0_TIME_DELAY ; 0 ; Untyped ;
; E1_TIME_DELAY ; 0 ; Untyped ;
; E2_TIME_DELAY ; 0 ; Untyped ;
; E3_TIME_DELAY ; 0 ; Untyped ;
; M_TIME_DELAY ; 0 ; Untyped ;
; N_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK3_COUNTER ; E3 ; Untyped ;
; EXTCLK2_COUNTER ; E2 ; Untyped ;
; EXTCLK1_COUNTER ; E1 ; Untyped ;
; EXTCLK0_COUNTER ; E0 ; Untyped ;
; ENABLE0_COUNTER ; L0 ; Untyped ;
; ENABLE1_COUNTER ; L0 ; Untyped ;
; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
; LOOP_FILTER_R ; 1.000000 ; Untyped ;
; LOOP_FILTER_C ; 5 ; Untyped ;
; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;
; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;
; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;
; VCO_POST_SCALE ; 0 ; Untyped ;
; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; INTENDED_DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ;
; PORT_CLK0 ; PORT_USED ; Untyped ;
; PORT_CLK1 ; PORT_USED ; Untyped ;
; PORT_CLK2 ; PORT_USED ; Untyped ;
; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
; PORT_CLK5 ; PORT_UNUSED ; Untyped ;
; PORT_CLK6 ; PORT_UNUSED ; Untyped ;
; PORT_CLK7 ; PORT_UNUSED ; Untyped ;
; PORT_CLK8 ; PORT_UNUSED ; Untyped ;
; PORT_CLK9 ; PORT_UNUSED ; Untyped ;
; PORT_SCANDATA ; PORT_UNUSED ; Untyped ;
; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ;
; PORT_SCANDONE ; PORT_UNUSED ; Untyped ;
; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ;
; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ;
; PORT_INCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_INCLK0 ; PORT_USED ; Untyped ;
; PORT_FBIN ; PORT_UNUSED ; Untyped ;
; PORT_PLLENA ; PORT_UNUSED ; Untyped ;
; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ;
; PORT_ARESET ; PORT_UNUSED ; Untyped ;
; PORT_PFDENA ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLK ; PORT_UNUSED ; Untyped ;
; PORT_SCANACLR ; PORT_UNUSED ; Untyped ;
; PORT_SCANREAD ; PORT_UNUSED ; Untyped ;
; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ;
; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_LOCKED ; PORT_USED ; Untyped ;
; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ;
; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ;
; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ;
; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ;
; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ;
; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;
; M_TEST_SOURCE ; 5 ; Untyped ;
; C0_TEST_SOURCE ; 5 ; Untyped ;
; C1_TEST_SOURCE ; 5 ; Untyped ;
; C2_TEST_SOURCE ; 5 ; Untyped ;
; C3_TEST_SOURCE ; 5 ; Untyped ;
; C4_TEST_SOURCE ; 5 ; Untyped ;
; C5_TEST_SOURCE ; 5 ; Untyped ;
; C6_TEST_SOURCE ; 5 ; Untyped ;
; C7_TEST_SOURCE ; 5 ; Untyped ;
; C8_TEST_SOURCE ; 5 ; Untyped ;
; C9_TEST_SOURCE ; 5 ; Untyped ;
; CBXI_PARAMETER ; pll_sys_altpll ; Untyped ;
; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
; WIDTH_CLOCK ; 5 ; Signed Integer ;
; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ;
; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+-------------------------------+---------------------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: picorv32:cpu ;
+----------------------+----------------------------------+-----------------+
; Parameter Name ; Value ; Type ;
+----------------------+----------------------------------+-----------------+
; ENABLE_COUNTERS ; 0 ; Signed Integer ;
; ENABLE_COUNTERS64 ; 0 ; Signed Integer ;
; ENABLE_REGS_16_31 ; 1 ; Unsigned Binary ;
; ENABLE_REGS_DUALPORT ; 1 ; Unsigned Binary ;
; LATCHED_MEM_RDATA ; 0 ; Unsigned Binary ;
; TWO_STAGE_SHIFT ; 1 ; Unsigned Binary ;
; BARREL_SHIFTER ; 1 ; Signed Integer ;
; TWO_CYCLE_COMPARE ; 0 ; Signed Integer ;
; TWO_CYCLE_ALU ; 0 ; Signed Integer ;
; COMPRESSED_ISA ; 0 ; Unsigned Binary ;
; CATCH_MISALIGN ; 1 ; Unsigned Binary ;
; CATCH_ILLINSN ; 1 ; Unsigned Binary ;
; ENABLE_PCPI ; 0 ; Signed Integer ;
; ENABLE_MUL ; 0 ; Unsigned Binary ;
; ENABLE_FAST_MUL ; 1 ; Signed Integer ;
; ENABLE_DIV ; 1 ; Signed Integer ;
; ENABLE_IRQ ; 0 ; Unsigned Binary ;
; ENABLE_IRQ_QREGS ; 1 ; Unsigned Binary ;
; ENABLE_IRQ_TIMER ; 1 ; Unsigned Binary ;
; ENABLE_TRACE ; 0 ; Unsigned Binary ;
; REGS_INIT_ZERO ; 0 ; Unsigned Binary ;
; MASKED_IRQ ; 00000000000000000000000000000000 ; Unsigned Binary ;
; LATCHED_IRQ ; 11111111111111111111111111111111 ; Unsigned Binary ;
; PROGADDR_RESET ; 00000000000000000000000000000000 ; Unsigned Binary ;
; PROGADDR_IRQ ; 00000000000000000000000000010000 ; Unsigned Binary ;
; STACKADDR ; 11111111111111111111111111111111 ; Unsigned Binary ;
+----------------------+----------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul ;
+----------------+-------+------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------------------------+
; EXTRA_MUL_FFS ; 0 ; Signed Integer ;
; EXTRA_INSN_FFS ; 0 ; Signed Integer ;
; MUL_CLKGATE ; 0 ; Signed Integer ;
+----------------+-------+------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol0_rtl_0 ;
+------------------------------------+--------------------------------------+-------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+--------------------------------------+-------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 8 ; Untyped ;
; WIDTHAD_A ; 14 ; Untyped ;
; NUMWORDS_A ; 10241 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 8 ; Untyped ;
; WIDTHAD_B ; 14 ; Untyped ;
; NUMWORDS_B ; 10241 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; db/xoro.ram0_Memory_a0c6519c.hdl.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; CBXI_PARAMETER ; altsyncram_bdi1 ; Untyped ;
+------------------------------------+--------------------------------------+-------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol1_rtl_0 ;
+------------------------------------+--------------------------------------+-------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+--------------------------------------+-------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 8 ; Untyped ;
; WIDTHAD_A ; 14 ; Untyped ;
; NUMWORDS_A ; 10241 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 8 ; Untyped ;
; WIDTHAD_B ; 14 ; Untyped ;
; NUMWORDS_B ; 10241 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; db/xoro.ram1_Memory_a0c6519c.hdl.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; CBXI_PARAMETER ; altsyncram_cdi1 ; Untyped ;
+------------------------------------+--------------------------------------+-------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: picorv32:cpu|altsyncram:cpuregs_rtl_0 ;
+------------------------------------+----------------------+----------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+----------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 32 ; Untyped ;
; WIDTHAD_A ; 5 ; Untyped ;
; NUMWORDS_A ; 32 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 32 ; Untyped ;
; WIDTHAD_B ; 5 ; Untyped ;
; NUMWORDS_B ; 32 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; CBXI_PARAMETER ; altsyncram_trd1 ; Untyped ;
+------------------------------------+----------------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: picorv32:cpu|altsyncram:cpuregs_rtl_1 ;
+------------------------------------+----------------------+----------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+----------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 32 ; Untyped ;
; WIDTHAD_A ; 5 ; Untyped ;
; NUMWORDS_A ; 32 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 32 ; Untyped ;
; WIDTHAD_B ; 5 ; Untyped ;
; NUMWORDS_B ; 32 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; CBXI_PARAMETER ; altsyncram_trd1 ; Untyped ;
+------------------------------------+----------------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol3_rtl_0 ;
+------------------------------------+--------------------------------------+-------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+--------------------------------------+-------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 8 ; Untyped ;
; WIDTHAD_A ; 14 ; Untyped ;
; NUMWORDS_A ; 10241 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 8 ; Untyped ;
; WIDTHAD_B ; 14 ; Untyped ;
; NUMWORDS_B ; 10241 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; db/xoro.ram3_Memory_a0c6519c.hdl.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; CBXI_PARAMETER ; altsyncram_edi1 ; Untyped ;
+------------------------------------+--------------------------------------+-------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Memory:mem|altsyncram:memory_1_symbol2_rtl_0 ;
+------------------------------------+--------------------------------------+-------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+--------------------------------------+-------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 8 ; Untyped ;
; WIDTHAD_A ; 14 ; Untyped ;
; NUMWORDS_A ; 10241 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 8 ; Untyped ;
; WIDTHAD_B ; 14 ; Untyped ;
; NUMWORDS_B ; 10241 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; db/xoro.ram2_Memory_a0c6519c.hdl.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; CBXI_PARAMETER ; altsyncram_ddi1 ; Untyped ;
+------------------------------------+--------------------------------------+-------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0 ;
+------------------------------------+----------------------+--------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+--------------------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 8 ; Untyped ;
; WIDTHAD_A ; 5 ; Untyped ;
; NUMWORDS_A ; 32 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 8 ; Untyped ;
; WIDTHAD_B ; 5 ; Untyped ;
; NUMWORDS_B ; 32 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; CBXI_PARAMETER ; altsyncram_s9c1 ; Untyped ;
+------------------------------------+----------------------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0 ;
+------------------------------------------------+--------------+----------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------------------+--------------+----------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTHA ; 33 ; Untyped ;
; LPM_WIDTHB ; 33 ; Untyped ;
; LPM_WIDTHP ; 66 ; Untyped ;
; LPM_WIDTHR ; 66 ; Untyped ;
; LPM_WIDTHS ; 1 ; Untyped ;
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; LATENCY ; 0 ; Untyped ;
; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
; USE_EAB ; OFF ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
; CBXI_PARAMETER ; mult_86t ; Untyped ;
; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
+------------------------------------------------+--------------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance ;
+-------------------------------+----------------------------------------------+
; Name ; Value ;
+-------------------------------+----------------------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; pll_sys:pll_sys_inst|altpll:altpll_component ;
; -- OPERATION_MODE ; NORMAL ;
; -- PLL_TYPE ; AUTO ;
; -- PRIMARY_CLOCK ; INCLK0 ;
; -- INCLK0_INPUT_FREQUENCY ; 20000 ;
; -- INCLK1_INPUT_FREQUENCY ; 0 ;
; -- VCO_MULTIPLY_BY ; 0 ;
; -- VCO_DIVIDE_BY ; 0 ;
+-------------------------------+----------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance ;
+-------------------------------------------+-------------------------------------------------------+
; Name ; Value ;
+-------------------------------------------+-------------------------------------------------------+
; Number of entity instances ; 7 ;
; Entity Instance ; Memory:mem|altsyncram:memory_1_symbol0_rtl_0 ;
; -- OPERATION_MODE ; DUAL_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 10241 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 8 ;
; -- NUMWORDS_B ; 10241 ;
; -- ADDRESS_REG_B ; CLOCK0 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
; Entity Instance ; Memory:mem|altsyncram:memory_1_symbol1_rtl_0 ;
; -- OPERATION_MODE ; DUAL_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 10241 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 8 ;
; -- NUMWORDS_B ; 10241 ;
; -- ADDRESS_REG_B ; CLOCK0 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
; Entity Instance ; picorv32:cpu|altsyncram:cpuregs_rtl_0 ;
; -- OPERATION_MODE ; DUAL_PORT ;
; -- WIDTH_A ; 32 ;
; -- NUMWORDS_A ; 32 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 32 ;
; -- NUMWORDS_B ; 32 ;
; -- ADDRESS_REG_B ; CLOCK0 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
; Entity Instance ; picorv32:cpu|altsyncram:cpuregs_rtl_1 ;
; -- OPERATION_MODE ; DUAL_PORT ;
; -- WIDTH_A ; 32 ;
; -- NUMWORDS_A ; 32 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 32 ;
; -- NUMWORDS_B ; 32 ;
; -- ADDRESS_REG_B ; CLOCK0 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
; Entity Instance ; Memory:mem|altsyncram:memory_1_symbol3_rtl_0 ;
; -- OPERATION_MODE ; DUAL_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 10241 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 8 ;
; -- NUMWORDS_B ; 10241 ;
; -- ADDRESS_REG_B ; CLOCK0 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
; Entity Instance ; Memory:mem|altsyncram:memory_1_symbol2_rtl_0 ;
; -- OPERATION_MODE ; DUAL_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 10241 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 8 ;
; -- NUMWORDS_B ; 10241 ;
; -- ADDRESS_REG_B ; CLOCK0 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
; Entity Instance ; AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0 ;
; -- OPERATION_MODE ; DUAL_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 32 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 8 ;
; -- NUMWORDS_B ; 32 ;
; -- ADDRESS_REG_B ; CLOCK0 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
+-------------------------------------------+-------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance ;
+---------------------------------------+-------------------------------------------------------------+
; Name ; Value ;
+---------------------------------------+-------------------------------------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0 ;
; -- LPM_WIDTHA ; 33 ;
; -- LPM_WIDTHB ; 33 ;
; -- LPM_WIDTHP ; 66 ;
; -- LPM_REPRESENTATION ; SIGNED ;
; -- INPUT_A_IS_CONSTANT ; NO ;
; -- INPUT_B_IS_CONSTANT ; NO ;
; -- USE_EAB ; OFF ;
; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ;
; -- INPUT_A_FIXED_VALUE ; Bx ;
; -- INPUT_B_FIXED_VALUE ; Bx ;
+---------------------------------------+-------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "picorv32:cpu" ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; trap ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; mem_la_read ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; mem_la_write ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; mem_la_addr ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; mem_la_wdata ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; mem_la_wstrb ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; pcpi_valid ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; pcpi_insn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; pcpi_rs1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; pcpi_rs2 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; pcpi_wr ; Input ; Info ; Stuck at GND ;
; pcpi_rd ; Input ; Info ; Stuck at GND ;
; pcpi_wait ; Input ; Info ; Stuck at GND ;
; pcpi_ready ; Input ; Info ; Stuck at GND ;
; irq ; Input ; Info ; Stuck at GND ;
; eoi ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; trace_valid ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; trace_data ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "busInterface:busInterface" ;
+---------------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+---------------+--------+----------+-------------------------------------------------------------------------------------+
; enables[1..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------------+--------+----------+-------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "prng:prng|xoroshiro128plus:prng" ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
; out[63..32] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "Memory:mem" ;
+-------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+-------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; io_mem_addr ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (16 bits) it drives. The 16 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
; reset ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ;
+-------------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "hundredMsTick:hundredMsTick" ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; tick ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------+--------+----------+-------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "AsyncReceiver:uartRx" ;
+-------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+-------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; io_mem_addr ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (4 bits) it drives. The 28 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+-------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "gpio:gpio" ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
; gpio[31..8] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "pll_sys:pll_sys_inst" ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
; locked ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; boundary_port ; 46 ;
; cycloneiii_ff ; 1420 ;
; CLR ; 214 ;
; ENA ; 439 ;
; ENA CLR ; 28 ;
; ENA SCLR ; 54 ;
; ENA SCLR SLD ; 27 ;
; ENA SLD ; 112 ;
; SCLR ; 47 ;
; SCLR SLD ; 1 ;
; SLD ; 32 ;
; plain ; 466 ;
; cycloneiii_lcell_comb ; 2711 ;
; arith ; 561 ;
; 2 data inputs ; 155 ;
; 3 data inputs ; 406 ;
; normal ; 2150 ;
; 0 data inputs ; 1 ;
; 1 data inputs ; 21 ;
; 2 data inputs ; 217 ;
; 3 data inputs ; 637 ;
; 4 data inputs ; 1274 ;
; cycloneiii_mac_mult ; 4 ;
; cycloneiii_mac_out ; 4 ;
; cycloneiii_pll ; 1 ;
; cycloneiii_ram_block ; 136 ;
; ; ;
; Max LUT depth ; 13.00 ;
; Average LUT depth ; 4.99 ;
+-----------------------+-----------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:04 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
Info: Processing started: Sat Sep 16 21:12:14 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off xoro -c xoro
Info (20032): Parallel compilation is enabled and will use up to 2 processors
Info (12021): Found 1 design units, including 1 entities, in source file pll_sys.v
Info (12023): Found entity 1: pll_sys
Info (12021): Found 1 design units, including 1 entities, in source file rtl/timer.v
Info (12023): Found entity 1: timer
Info (12021): Found 3 design units, including 3 entities, in source file rtl/uarttx.v
Info (12023): Found entity 1: EdgeDetect
Info (12023): Found entity 2: BaudRateGenerator
Info (12023): Found entity 3: uartTx
Info (12021): Found 1 design units, including 1 entities, in source file rtl/xoroshiro128plus.v
Info (12023): Found entity 1: xoroshiro128plus
Info (12021): Found 1 design units, including 1 entities, in source file rtl/prng.v
Info (12023): Found entity 1: prng
Info (12021): Found 4 design units, including 4 entities, in source file rtl/xoro_top.v
Info (12023): Found entity 1: hundredMsTick
Info (12023): Found entity 2: gpio_test
Info (12023): Found entity 3: uart_test
Info (12023): Found entity 4: xoro_top
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(315)
Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(386)
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1100)
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1230)
Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1230)
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1247)
Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1247)
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1293)
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1464)
Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1464)
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1476)
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1562)
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1606)
Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1606)
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1714)
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1745)
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1815)
Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1815)
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1823)
Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1823)
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1838)
Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1838)
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1863)
Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1863)
Warning (10335): Unrecognized synthesis attribute "parallel_case" at rtl/picorv32.v(1880)
Warning (10335): Unrecognized synthesis attribute "full_case" at rtl/picorv32.v(1880)
Info (12021): Found 8 design units, including 8 entities, in source file rtl/picorv32.v
Info (12023): Found entity 1: picorv32
Info (12023): Found entity 2: picorv32_regs
Info (12023): Found entity 3: picorv32_pcpi_mul
Info (12023): Found entity 4: picorv32_pcpi_fast_mul
Info (12023): Found entity 5: picorv32_pcpi_div
Info (12023): Found entity 6: picorv32_axi
Info (12023): Found entity 7: picorv32_axi_adapter
Info (12023): Found entity 8: picorv32_wb
Info (12021): Found 1 design units, including 1 entities, in source file rtl/memory.v
Info (12023): Found entity 1: Memory
Info (12021): Found 1 design units, including 1 entities, in source file rtl/gpio.v
Info (12023): Found entity 1: gpio
Info (12021): Found 1 design units, including 1 entities, in source file qram32.v
Info (12023): Found entity 1: qram32
Info (12021): Found 1 design units, including 1 entities, in source file rtl/businterface.v
Info (12023): Found entity 1: busInterface
Info (12021): Found 2 design units, including 2 entities, in source file rtl/asyncreceiver.v
Info (12023): Found entity 1: Fifo
Info (12023): Found entity 2: AsyncReceiver
Warning (10236): Verilog HDL Implicit Net warning at uartTx.v(51): created implicit net for "baudRateClock"
Warning (10236): Verilog HDL Implicit Net warning at uartTx.v(104): created implicit net for "bitStart"
Warning (10236): Verilog HDL Implicit Net warning at xoro_top.v(204): created implicit net for "CLOCK_1843200"
Info (12127): Elaborating entity "xoro_top" for the top level hierarchy
Warning (10030): Net "pcpi_rd" at xoro_top.v(166) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "irq" at xoro_top.v(171) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "pcpi_wr" at xoro_top.v(165) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "pcpi_wait" at xoro_top.v(167) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "pcpi_ready" at xoro_top.v(168) has no driver or initial value, using a default initial value '0'
Warning (10034): Output port "GPIO_1_D[32]" at xoro_top.v(141) has no driver
Warning (10034): Output port "GPIO_1_D[30..0]" at xoro_top.v(141) has no driver
Info (12128): Elaborating entity "pll_sys" for hierarchy "pll_sys:pll_sys_inst"
Info (12128): Elaborating entity "altpll" for hierarchy "pll_sys:pll_sys_inst|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "pll_sys:pll_sys_inst|altpll:altpll_component"
Info (12133): Instantiated megafunction "pll_sys:pll_sys_inst|altpll:altpll_component" with the following parameter:
Info (12134): Parameter "bandwidth_type" = "AUTO"
Info (12134): Parameter "clk0_divide_by" = "1"
Info (12134): Parameter "clk0_duty_cycle" = "50"
Info (12134): Parameter "clk0_multiply_by" = "2"
Info (12134): Parameter "clk0_phase_shift" = "0"
Info (12134): Parameter "clk1_divide_by" = "15625"
Info (12134): Parameter "clk1_duty_cycle" = "50"
Info (12134): Parameter "clk1_multiply_by" = "2304"
Info (12134): Parameter "clk1_phase_shift" = "0"
Info (12134): Parameter "clk2_divide_by" = "15625"
Info (12134): Parameter "clk2_duty_cycle" = "50"
Info (12134): Parameter "clk2_multiply_by" = "576"
Info (12134): Parameter "clk2_phase_shift" = "0"
Info (12134): Parameter "compensate_clock" = "CLK0"
Info (12134): Parameter "inclk0_input_frequency" = "20000"
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll_sys"
Info (12134): Parameter "lpm_type" = "altpll"
Info (12134): Parameter "operation_mode" = "NORMAL"
Info (12134): Parameter "pll_type" = "AUTO"
Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
Info (12134): Parameter "port_areset" = "PORT_UNUSED"
Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
Info (12134): Parameter "port_inclk0" = "PORT_USED"
Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
Info (12134): Parameter "port_locked" = "PORT_USED"
Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
Info (12134): Parameter "port_clk0" = "PORT_USED"
Info (12134): Parameter "port_clk1" = "PORT_USED"
Info (12134): Parameter "port_clk2" = "PORT_USED"
Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
Info (12134): Parameter "self_reset_on_loss_lock" = "ON"
Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/pll_sys_altpll.v
Info (12023): Found entity 1: pll_sys_altpll
Info (12128): Elaborating entity "pll_sys_altpll" for hierarchy "pll_sys:pll_sys_inst|altpll:altpll_component|pll_sys_altpll:auto_generated"
Info (12128): Elaborating entity "gpio" for hierarchy "gpio:gpio"
Warning (10230): Verilog HDL assignment warning at gpio.v(47): truncated value with size 32 to match size of target (8)
Info (12128): Elaborating entity "uartTx" for hierarchy "uartTx:uartTx"
Info (12128): Elaborating entity "BaudRateGenerator" for hierarchy "uartTx:uartTx|BaudRateGenerator:baudRateGenerator"
Warning (10230): Verilog HDL assignment warning at uartTx.v(63): truncated value with size 32 to match size of target (4)
Info (12128): Elaborating entity "EdgeDetect" for hierarchy "uartTx:uartTx|BaudRateGenerator:baudRateGenerator|EdgeDetect:baudClockEdgeDetect"
Info (12128): Elaborating entity "AsyncReceiver" for hierarchy "AsyncReceiver:uartRx"
Info (10264): Verilog HDL Case Statement information at AsyncReceiver.v(154): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at AsyncReceiver.v(194): all case item expressions in this case statement are onehot
Info (12128): Elaborating entity "Fifo" for hierarchy "AsyncReceiver:uartRx|Fifo:fifo_1"
Info (12128): Elaborating entity "hundredMsTick" for hierarchy "hundredMsTick:hundredMsTick"
Info (12128): Elaborating entity "Memory" for hierarchy "Memory:mem"
Warning (10850): Verilog HDL warning at memory.v(32): number of words (16384) in memory file does not match the number of elements in the address range [0:10240]
Warning (10850): Verilog HDL warning at memory.v(33): number of words (16384) in memory file does not match the number of elements in the address range [0:10240]
Warning (10850): Verilog HDL warning at memory.v(34): number of words (16384) in memory file does not match the number of elements in the address range [0:10240]
Warning (10850): Verilog HDL warning at memory.v(35): number of words (16384) in memory file does not match the number of elements in the address range [0:10240]
Warning (10230): Verilog HDL assignment warning at memory.v(56): truncated value with size 16 to match size of target (14)
Info (12128): Elaborating entity "prng" for hierarchy "prng:prng"
Warning (10230): Verilog HDL assignment warning at prng.v(43): truncated value with size 64 to match size of target (32)
Info (12128): Elaborating entity "xoroshiro128plus" for hierarchy "prng:prng|xoroshiro128plus:prng"
Info (12128): Elaborating entity "timer" for hierarchy "timer:timer"
Info (12128): Elaborating entity "busInterface" for hierarchy "busInterface:busInterface"
Info (12128): Elaborating entity "picorv32" for hierarchy "picorv32:cpu"
Warning (10036): Verilog HDL or VHDL warning at picorv32.v(165): object "dbg_insn_addr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at picorv32.v(167): object "dbg_mem_valid" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at picorv32.v(168): object "dbg_mem_instr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at picorv32.v(169): object "dbg_mem_ready" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at picorv32.v(170): object "dbg_mem_addr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at picorv32.v(171): object "dbg_mem_wdata" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at picorv32.v(172): object "dbg_mem_wstrb" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at picorv32.v(173): object "dbg_mem_rdata" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at picorv32.v(359): object "mem_busy" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at picorv32.v(679): object "dbg_rs1val" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at picorv32.v(680): object "dbg_rs2val" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at picorv32.v(681): object "dbg_rs1val_valid" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at picorv32.v(682): object "dbg_rs2val_valid" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at picorv32.v(751): object "dbg_valid_insn" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at picorv32.v(1163): object "dbg_ascii_state" assigned a value but never read
Warning (10763): Verilog HDL warning at picorv32.v(316): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
Warning (10270): Verilog HDL Case Statement warning at picorv32.v(316): incomplete case statement has no default case item
Warning (10230): Verilog HDL assignment warning at picorv32.v(601): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at picorv32.v(1224): truncated value with size 33 to match size of target (32)
Warning (10230): Verilog HDL assignment warning at picorv32.v(1229): truncated value with size 32 to match size of target (1)
Warning (10763): Verilog HDL warning at picorv32.v(1231): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
Warning (10208): Verilog HDL Case Statement warning at picorv32.v(1231): honored full_case synthesis attribute - differences between design synthesis and simulation may occur
Warning (10763): Verilog HDL warning at picorv32.v(1248): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
Warning (10208): Verilog HDL Case Statement warning at picorv32.v(1248): honored full_case synthesis attribute - differences between design synthesis and simulation may occur
Warning (10763): Verilog HDL warning at picorv32.v(1294): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
Warning (10270): Verilog HDL Case Statement warning at picorv32.v(1294): incomplete case statement has no default case item
Warning (10230): Verilog HDL assignment warning at picorv32.v(1322): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at picorv32.v(1377): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at picorv32.v(1399): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at picorv32.v(1401): truncated value with size 32 to match size of target (4)
Warning (10763): Verilog HDL warning at picorv32.v(1477): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
Warning (10230): Verilog HDL assignment warning at picorv32.v(1573): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at picorv32.v(1710): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at picorv32.v(1740): truncated value with size 32 to match size of target (5)
Warning (10763): Verilog HDL warning at picorv32.v(1816): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
Warning (10208): Verilog HDL Case Statement warning at picorv32.v(1816): honored full_case synthesis attribute - differences between design synthesis and simulation may occur
Warning (10230): Verilog HDL assignment warning at picorv32.v(1821): truncated value with size 32 to match size of target (5)
Warning (10763): Verilog HDL warning at picorv32.v(1824): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
Warning (10208): Verilog HDL Case Statement warning at picorv32.v(1824): honored full_case synthesis attribute - differences between design synthesis and simulation may occur
Warning (10230): Verilog HDL assignment warning at picorv32.v(1829): truncated value with size 32 to match size of target (5)
Warning (10763): Verilog HDL warning at picorv32.v(1839): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
Warning (10208): Verilog HDL Case Statement warning at picorv32.v(1839): honored full_case synthesis attribute - differences between design synthesis and simulation may occur
Warning (10763): Verilog HDL warning at picorv32.v(1864): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
Warning (10208): Verilog HDL Case Statement warning at picorv32.v(1864): honored full_case synthesis attribute - differences between design synthesis and simulation may occur
Warning (10763): Verilog HDL warning at picorv32.v(1881): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
Warning (10208): Verilog HDL Case Statement warning at picorv32.v(1881): honored full_case synthesis attribute - differences between design synthesis and simulation may occur
Info (12128): Elaborating entity "picorv32_pcpi_fast_mul" for hierarchy "picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul"
Warning (10270): Verilog HDL Case Statement warning at picorv32.v(2285): incomplete case statement has no default case item
Warning (10230): Verilog HDL assignment warning at picorv32.v(2324): truncated value with size 4 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at picorv32.v(2341): truncated value with size 64 to match size of target (32)
Info (12128): Elaborating entity "picorv32_pcpi_div" for hierarchy "picorv32:cpu|picorv32_pcpi_div:pcpi_div"
Warning (10259): Verilog HDL error at picorv32.v(2408): constant value overflow
Warning (10230): Verilog HDL assignment warning at picorv32.v(2429): truncated value with size 63 to match size of target (32)
Critical Warning (127005): Memory depth (16384) in the design file differs from memory depth (10241) in the Memory Initialization File "E:/Photonic/RISCV/db/xoro.ram0_Memory_a0c6519c.hdl.mif" -- setting initial value for remaining addresses to 0
Warning (276020): Inferred RAM node "Memory:mem|memory_1_symbol0_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
Critical Warning (127005): Memory depth (16384) in the design file differs from memory depth (10241) in the Memory Initialization File "E:/Photonic/RISCV/db/xoro.ram1_Memory_a0c6519c.hdl.mif" -- setting initial value for remaining addresses to 0
Warning (276020): Inferred RAM node "Memory:mem|memory_1_symbol1_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
Warning (276020): Inferred RAM node "picorv32:cpu|cpuregs_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
Warning (276020): Inferred RAM node "picorv32:cpu|cpuregs_rtl_1" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
Critical Warning (127005): Memory depth (16384) in the design file differs from memory depth (10241) in the Memory Initialization File "E:/Photonic/RISCV/db/xoro.ram3_Memory_a0c6519c.hdl.mif" -- setting initial value for remaining addresses to 0
Warning (276020): Inferred RAM node "Memory:mem|memory_1_symbol3_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
Critical Warning (127005): Memory depth (16384) in the design file differs from memory depth (10241) in the Memory Initialization File "E:/Photonic/RISCV/db/xoro.ram2_Memory_a0c6519c.hdl.mif" -- setting initial value for remaining addresses to 0
Warning (276020): Inferred RAM node "Memory:mem|memory_1_symbol2_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
Warning (276020): Inferred RAM node "AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
Info (19000): Inferred 7 megafunctions from design logic
Info (276029): Inferred altsyncram megafunction from the following design logic: "Memory:mem|memory_1_symbol0_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 14
Info (286033): Parameter NUMWORDS_A set to 10241
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 14
Info (286033): Parameter NUMWORDS_B set to 10241
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter INIT_FILE set to db/xoro.ram0_Memory_a0c6519c.hdl.mif
Info (276029): Inferred altsyncram megafunction from the following design logic: "Memory:mem|memory_1_symbol1_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 14
Info (286033): Parameter NUMWORDS_A set to 10241
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 14
Info (286033): Parameter NUMWORDS_B set to 10241
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter INIT_FILE set to db/xoro.ram1_Memory_a0c6519c.hdl.mif
Info (276029): Inferred altsyncram megafunction from the following design logic: "picorv32:cpu|cpuregs_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 32
Info (286033): Parameter WIDTHAD_A set to 5
Info (286033): Parameter NUMWORDS_A set to 32
Info (286033): Parameter WIDTH_B set to 32
Info (286033): Parameter WIDTHAD_B set to 5
Info (286033): Parameter NUMWORDS_B set to 32
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (276029): Inferred altsyncram megafunction from the following design logic: "picorv32:cpu|cpuregs_rtl_1"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 32
Info (286033): Parameter WIDTHAD_A set to 5
Info (286033): Parameter NUMWORDS_A set to 32
Info (286033): Parameter WIDTH_B set to 32
Info (286033): Parameter WIDTHAD_B set to 5
Info (286033): Parameter NUMWORDS_B set to 32
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (276029): Inferred altsyncram megafunction from the following design logic: "Memory:mem|memory_1_symbol3_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 14
Info (286033): Parameter NUMWORDS_A set to 10241
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 14
Info (286033): Parameter NUMWORDS_B set to 10241
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter INIT_FILE set to db/xoro.ram3_Memory_a0c6519c.hdl.mif
Info (276029): Inferred altsyncram megafunction from the following design logic: "Memory:mem|memory_1_symbol2_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 14
Info (286033): Parameter NUMWORDS_A set to 10241
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 14
Info (286033): Parameter NUMWORDS_B set to 10241
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter INIT_FILE set to db/xoro.ram2_Memory_a0c6519c.hdl.mif
Info (276029): Inferred altsyncram megafunction from the following design logic: "AsyncReceiver:uartRx|Fifo:fifo_1|mem_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 5
Info (286033): Parameter NUMWORDS_A set to 32
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 5
Info (286033): Parameter NUMWORDS_B set to 32
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (278001): Inferred 1 megafunctions from design logic
Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|Mult0"
Info (12130): Elaborated megafunction instantiation "Memory:mem|altsyncram:memory_1_symbol0_rtl_0"
Info (12133): Instantiated megafunction "Memory:mem|altsyncram:memory_1_symbol0_rtl_0" with the following parameter:
Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
Info (12134): Parameter "WIDTH_A" = "8"
Info (12134): Parameter "WIDTHAD_A" = "14"
Info (12134): Parameter "NUMWORDS_A" = "10241"
Info (12134): Parameter "WIDTH_B" = "8"
Info (12134): Parameter "WIDTHAD_B" = "14"
Info (12134): Parameter "NUMWORDS_B" = "10241"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12134): Parameter "INIT_FILE" = "db/xoro.ram0_Memory_a0c6519c.hdl.mif"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_bdi1.tdf
Info (12023): Found entity 1: altsyncram_bdi1
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf
Info (12023): Found entity 1: decode_jsa
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf
Info (12023): Found entity 1: decode_c8a
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf
Info (12023): Found entity 1: mux_3nb
Info (12130): Elaborated megafunction instantiation "Memory:mem|altsyncram:memory_1_symbol1_rtl_0"
Info (12133): Instantiated megafunction "Memory:mem|altsyncram:memory_1_symbol1_rtl_0" with the following parameter:
Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
Info (12134): Parameter "WIDTH_A" = "8"
Info (12134): Parameter "WIDTHAD_A" = "14"
Info (12134): Parameter "NUMWORDS_A" = "10241"
Info (12134): Parameter "WIDTH_B" = "8"
Info (12134): Parameter "WIDTHAD_B" = "14"
Info (12134): Parameter "NUMWORDS_B" = "10241"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12134): Parameter "INIT_FILE" = "db/xoro.ram1_Memory_a0c6519c.hdl.mif"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_cdi1.tdf
Info (12023): Found entity 1: altsyncram_cdi1
Info (12130): Elaborated megafunction instantiation "picorv32:cpu|altsyncram:cpuregs_rtl_0"
Info (12133): Instantiated megafunction "picorv32:cpu|altsyncram:cpuregs_rtl_0" with the following parameter:
Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
Info (12134): Parameter "WIDTH_A" = "32"
Info (12134): Parameter "WIDTHAD_A" = "5"
Info (12134): Parameter "NUMWORDS_A" = "32"
Info (12134): Parameter "WIDTH_B" = "32"
Info (12134): Parameter "WIDTHAD_B" = "5"
Info (12134): Parameter "NUMWORDS_B" = "32"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_trd1.tdf
Info (12023): Found entity 1: altsyncram_trd1
Info (12130): Elaborated megafunction instantiation "Memory:mem|altsyncram:memory_1_symbol3_rtl_0"
Info (12133): Instantiated megafunction "Memory:mem|altsyncram:memory_1_symbol3_rtl_0" with the following parameter:
Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
Info (12134): Parameter "WIDTH_A" = "8"
Info (12134): Parameter "WIDTHAD_A" = "14"
Info (12134): Parameter "NUMWORDS_A" = "10241"
Info (12134): Parameter "WIDTH_B" = "8"
Info (12134): Parameter "WIDTHAD_B" = "14"
Info (12134): Parameter "NUMWORDS_B" = "10241"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12134): Parameter "INIT_FILE" = "db/xoro.ram3_Memory_a0c6519c.hdl.mif"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_edi1.tdf
Info (12023): Found entity 1: altsyncram_edi1
Info (12130): Elaborated megafunction instantiation "Memory:mem|altsyncram:memory_1_symbol2_rtl_0"
Info (12133): Instantiated megafunction "Memory:mem|altsyncram:memory_1_symbol2_rtl_0" with the following parameter:
Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
Info (12134): Parameter "WIDTH_A" = "8"
Info (12134): Parameter "WIDTHAD_A" = "14"
Info (12134): Parameter "NUMWORDS_A" = "10241"
Info (12134): Parameter "WIDTH_B" = "8"
Info (12134): Parameter "WIDTHAD_B" = "14"
Info (12134): Parameter "NUMWORDS_B" = "10241"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12134): Parameter "INIT_FILE" = "db/xoro.ram2_Memory_a0c6519c.hdl.mif"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ddi1.tdf
Info (12023): Found entity 1: altsyncram_ddi1
Info (12130): Elaborated megafunction instantiation "AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0"
Info (12133): Instantiated megafunction "AsyncReceiver:uartRx|Fifo:fifo_1|altsyncram:mem_rtl_0" with the following parameter:
Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
Info (12134): Parameter "WIDTH_A" = "8"
Info (12134): Parameter "WIDTHAD_A" = "5"
Info (12134): Parameter "NUMWORDS_A" = "32"
Info (12134): Parameter "WIDTH_B" = "8"
Info (12134): Parameter "WIDTHAD_B" = "5"
Info (12134): Parameter "NUMWORDS_B" = "32"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_s9c1.tdf
Info (12023): Found entity 1: altsyncram_s9c1
Info (12130): Elaborated megafunction instantiation "picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0"
Info (12133): Instantiated megafunction "picorv32:cpu|picorv32_pcpi_fast_mul:pcpi_mul|lpm_mult:Mult0" with the following parameter:
Info (12134): Parameter "LPM_WIDTHA" = "33"
Info (12134): Parameter "LPM_WIDTHB" = "33"
Info (12134): Parameter "LPM_WIDTHP" = "66"
Info (12134): Parameter "LPM_WIDTHR" = "66"
Info (12134): Parameter "LPM_WIDTHS" = "1"
Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED"
Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO"
Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/mult_86t.tdf
Info (12023): Found entity 1: mult_86t
Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Info (13014): Ignored 204 buffer(s)
Info (13019): Ignored 204 SOFT buffer(s)
Info (13000): Registers with preset signals will power-up high
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "GPIO_1_D[0]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[1]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[2]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[3]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[4]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[5]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[6]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[7]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[8]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[9]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[10]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[11]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[12]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[13]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[14]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[15]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[16]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[17]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[18]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[19]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[20]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[21]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[22]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[23]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[24]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[25]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[26]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[27]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[28]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[29]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[30]" is stuck at GND
Warning (13410): Pin "GPIO_1_D[32]" is stuck at GND
Info (286030): Timing-Driven Synthesis is running
Info (17049): 10 registers lost all their fanouts during netlist optimizations.
Info (144001): Generated suppressed messages file E:/Photonic/RISCV/output_files/xoro.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "reset_btn"
Info (21057): Implemented 3480 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 3 input pins
Info (21059): Implemented 43 output pins
Info (21061): Implemented 3289 logic cells
Info (21064): Implemented 136 RAM segments
Info (21065): Implemented 1 PLLs
Info (21062): Implemented 8 DSP elements
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 142 warnings
Info: Peak virtual memory: 4859 megabytes
Info: Processing ended: Sat Sep 16 21:12:28 2023
Info: Elapsed time: 00:00:14
Info: Total CPU time (on all processors): 00:00:11
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/Photonic/RISCV/output_files/xoro.map.smsg.