514 lines
9.1 KiB
ArmAsm
514 lines
9.1 KiB
ArmAsm
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// This is free and unencumbered software released into the public domain.
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//
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// Anyone is free to copy, modify, publish, use, compile, sell, or
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// distribute this software, either in source code form or as a compiled
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// binary, for any purpose, commercial or non-commercial, and by any
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// means.
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//#define ENABLE_INSTRTST
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//#define ENABLE_RVTST
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//#define ENABLE_SIEVE
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//#define ENABLE_MULTST
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//#define ENABLE_STATS
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#ifndef ENABLE_QREGS
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# undef ENABLE_RVTST
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#endif
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// Only save registers in IRQ wrapper that are to be saved by the caller in
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// the RISC-V ABI, with the excpetion of the stack pointer. The IRQ handler
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// will save the rest if necessary. I.e. skip x3, x4, x8, x9, and x18-x27.
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#undef ENABLE_FASTIRQ
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#include "custom_ops.S"
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.section .text
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.global irq
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.global sieve
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.global multest
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.global hard_mul
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.global hard_mulh
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.global hard_mulhsu
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.global hard_mulhu
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.global stats
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reset_vec:
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// no more than 16 bytes here !
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//picorv32_waitirq_insn(zero)
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//picorv32_maskirq_insn(zero, zero)
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j start
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/* Interrupt handler
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**********************************/
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.balign 16
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irq_vec:
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/* save registers */
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#ifdef ENABLE_QREGS
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picorv32_setq_insn(q2, x1)
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picorv32_setq_insn(q3, x2)
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lui x1, %hi(irq_regs)
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addi x1, x1, %lo(irq_regs)
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picorv32_getq_insn(x2, q0)
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sw x2, 0*4(x1)
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picorv32_getq_insn(x2, q2)
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sw x2, 1*4(x1)
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picorv32_getq_insn(x2, q3)
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sw x2, 2*4(x1)
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#ifdef ENABLE_FASTIRQ
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sw x5, 5*4(x1)
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sw x6, 6*4(x1)
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sw x7, 7*4(x1)
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sw x10, 10*4(x1)
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sw x11, 11*4(x1)
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sw x12, 12*4(x1)
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sw x13, 13*4(x1)
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sw x14, 14*4(x1)
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sw x15, 15*4(x1)
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sw x16, 16*4(x1)
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sw x17, 17*4(x1)
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sw x28, 28*4(x1)
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sw x29, 29*4(x1)
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sw x30, 30*4(x1)
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sw x31, 31*4(x1)
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#else
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sw x3, 3*4(x1)
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sw x4, 4*4(x1)
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sw x5, 5*4(x1)
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sw x6, 6*4(x1)
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sw x7, 7*4(x1)
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sw x8, 8*4(x1)
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sw x9, 9*4(x1)
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sw x10, 10*4(x1)
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sw x11, 11*4(x1)
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sw x12, 12*4(x1)
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sw x13, 13*4(x1)
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sw x14, 14*4(x1)
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sw x15, 15*4(x1)
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sw x16, 16*4(x1)
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sw x17, 17*4(x1)
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sw x18, 18*4(x1)
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sw x19, 19*4(x1)
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sw x20, 20*4(x1)
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sw x21, 21*4(x1)
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sw x22, 22*4(x1)
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sw x23, 23*4(x1)
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sw x24, 24*4(x1)
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sw x25, 25*4(x1)
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sw x26, 26*4(x1)
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sw x27, 27*4(x1)
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sw x28, 28*4(x1)
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sw x29, 29*4(x1)
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sw x30, 30*4(x1)
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sw x31, 31*4(x1)
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#endif
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#else // ENABLE_QREGS
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#ifdef ENABLE_FASTIRQ
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sw gp, 0*4+0x200(zero)
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sw x1, 1*4+0x200(zero)
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sw x2, 2*4+0x200(zero)
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sw x5, 5*4+0x200(zero)
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sw x6, 6*4+0x200(zero)
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sw x7, 7*4+0x200(zero)
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sw x10, 10*4+0x200(zero)
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sw x11, 11*4+0x200(zero)
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sw x12, 12*4+0x200(zero)
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sw x13, 13*4+0x200(zero)
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sw x14, 14*4+0x200(zero)
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sw x15, 15*4+0x200(zero)
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sw x16, 16*4+0x200(zero)
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sw x17, 17*4+0x200(zero)
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sw x28, 28*4+0x200(zero)
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sw x29, 29*4+0x200(zero)
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sw x30, 30*4+0x200(zero)
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sw x31, 31*4+0x200(zero)
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#else
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sw gp, 0*4+0x200(zero)
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sw x1, 1*4+0x200(zero)
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sw x2, 2*4+0x200(zero)
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sw x3, 3*4+0x200(zero)
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sw x4, 4*4+0x200(zero)
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sw x5, 5*4+0x200(zero)
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sw x6, 6*4+0x200(zero)
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sw x7, 7*4+0x200(zero)
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sw x8, 8*4+0x200(zero)
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sw x9, 9*4+0x200(zero)
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sw x10, 10*4+0x200(zero)
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sw x11, 11*4+0x200(zero)
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sw x12, 12*4+0x200(zero)
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sw x13, 13*4+0x200(zero)
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sw x14, 14*4+0x200(zero)
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sw x15, 15*4+0x200(zero)
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sw x16, 16*4+0x200(zero)
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sw x17, 17*4+0x200(zero)
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sw x18, 18*4+0x200(zero)
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sw x19, 19*4+0x200(zero)
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sw x20, 20*4+0x200(zero)
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sw x21, 21*4+0x200(zero)
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sw x22, 22*4+0x200(zero)
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sw x23, 23*4+0x200(zero)
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sw x24, 24*4+0x200(zero)
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sw x25, 25*4+0x200(zero)
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sw x26, 26*4+0x200(zero)
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sw x27, 27*4+0x200(zero)
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sw x28, 28*4+0x200(zero)
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sw x29, 29*4+0x200(zero)
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sw x30, 30*4+0x200(zero)
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sw x31, 31*4+0x200(zero)
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#endif
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#endif // ENABLE_QREGS
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/* call interrupt handler C function */
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lui sp, %hi(irq_stack)
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addi sp, sp, %lo(irq_stack)
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// arg0 = address of regs
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lui a0, %hi(irq_regs)
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addi a0, a0, %lo(irq_regs)
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// arg1 = interrupt type
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#ifdef ENABLE_QREGS
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picorv32_getq_insn(a1, q1)
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#else
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addi a1, tp, 0
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#endif
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// call to C function
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jal ra, irq
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/* restore registers */
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#ifdef ENABLE_QREGS
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// new irq_regs address returned from C code in a0
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addi x1, a0, 0
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lw x2, 0*4(x1)
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picorv32_setq_insn(q0, x2)
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lw x2, 1*4(x1)
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picorv32_setq_insn(q1, x2)
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lw x2, 2*4(x1)
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picorv32_setq_insn(q2, x2)
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#ifdef ENABLE_FASTIRQ
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lw x5, 5*4(x1)
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lw x6, 6*4(x1)
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lw x7, 7*4(x1)
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lw x10, 10*4(x1)
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lw x11, 11*4(x1)
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lw x12, 12*4(x1)
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lw x13, 13*4(x1)
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lw x14, 14*4(x1)
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lw x15, 15*4(x1)
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lw x16, 16*4(x1)
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lw x17, 17*4(x1)
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lw x28, 28*4(x1)
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lw x29, 29*4(x1)
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lw x30, 30*4(x1)
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lw x31, 31*4(x1)
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#else
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lw x3, 3*4(x1)
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lw x4, 4*4(x1)
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lw x5, 5*4(x1)
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lw x6, 6*4(x1)
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lw x7, 7*4(x1)
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lw x8, 8*4(x1)
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lw x9, 9*4(x1)
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lw x10, 10*4(x1)
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lw x11, 11*4(x1)
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lw x12, 12*4(x1)
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lw x13, 13*4(x1)
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lw x14, 14*4(x1)
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lw x15, 15*4(x1)
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lw x16, 16*4(x1)
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lw x17, 17*4(x1)
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lw x18, 18*4(x1)
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lw x19, 19*4(x1)
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lw x20, 20*4(x1)
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lw x21, 21*4(x1)
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lw x22, 22*4(x1)
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lw x23, 23*4(x1)
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lw x24, 24*4(x1)
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lw x25, 25*4(x1)
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lw x26, 26*4(x1)
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lw x27, 27*4(x1)
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lw x28, 28*4(x1)
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lw x29, 29*4(x1)
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lw x30, 30*4(x1)
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lw x31, 31*4(x1)
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#endif
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picorv32_getq_insn(x1, q1)
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picorv32_getq_insn(x2, q2)
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#else // ENABLE_QREGS
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// new irq_regs address returned from C code in a0
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addi a1, zero, 0x200
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beq a0, a1, 1f
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ebreak
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1:
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#ifdef ENABLE_FASTIRQ
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lw gp, 0*4+0x200(zero)
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lw x1, 1*4+0x200(zero)
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lw x2, 2*4+0x200(zero)
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lw x5, 5*4+0x200(zero)
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lw x6, 6*4+0x200(zero)
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lw x7, 7*4+0x200(zero)
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lw x10, 10*4+0x200(zero)
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lw x11, 11*4+0x200(zero)
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lw x12, 12*4+0x200(zero)
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lw x13, 13*4+0x200(zero)
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lw x14, 14*4+0x200(zero)
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lw x15, 15*4+0x200(zero)
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lw x16, 16*4+0x200(zero)
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lw x17, 17*4+0x200(zero)
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lw x28, 28*4+0x200(zero)
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lw x29, 29*4+0x200(zero)
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lw x30, 30*4+0x200(zero)
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lw x31, 31*4+0x200(zero)
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#else
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lw gp, 0*4+0x200(zero)
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lw x1, 1*4+0x200(zero)
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lw x2, 2*4+0x200(zero)
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// do not restore x3 (gp)
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lw x4, 4*4+0x200(zero)
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lw x5, 5*4+0x200(zero)
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lw x6, 6*4+0x200(zero)
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lw x7, 7*4+0x200(zero)
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lw x8, 8*4+0x200(zero)
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lw x9, 9*4+0x200(zero)
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lw x10, 10*4+0x200(zero)
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lw x11, 11*4+0x200(zero)
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lw x12, 12*4+0x200(zero)
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lw x13, 13*4+0x200(zero)
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lw x14, 14*4+0x200(zero)
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lw x15, 15*4+0x200(zero)
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lw x16, 16*4+0x200(zero)
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lw x17, 17*4+0x200(zero)
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lw x18, 18*4+0x200(zero)
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lw x19, 19*4+0x200(zero)
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lw x20, 20*4+0x200(zero)
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lw x21, 21*4+0x200(zero)
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lw x22, 22*4+0x200(zero)
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lw x23, 23*4+0x200(zero)
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lw x24, 24*4+0x200(zero)
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lw x25, 25*4+0x200(zero)
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lw x26, 26*4+0x200(zero)
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lw x27, 27*4+0x200(zero)
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lw x28, 28*4+0x200(zero)
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lw x29, 29*4+0x200(zero)
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lw x30, 30*4+0x200(zero)
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lw x31, 31*4+0x200(zero)
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#endif
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#endif // ENABLE_QREGS
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picorv32_retirq_insn()
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#ifndef ENABLE_QREGS
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.balign 0x200
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#endif
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irq_regs:
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// registers are saved to this memory region during interrupt handling
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// the program counter is saved as register 0
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.fill 32,4
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// stack for the interrupt handler
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.fill 128,4
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irq_stack:
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/* Main program
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**********************************/
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start:
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/* zero-initialize all registers */
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addi x1, zero, 0
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|
addi x2, zero, 0
|
||
|
|
addi x3, zero, 0
|
||
|
|
addi x4, zero, 0
|
||
|
|
addi x5, zero, 0
|
||
|
|
addi x6, zero, 0
|
||
|
|
addi x7, zero, 0
|
||
|
|
addi x8, zero, 0
|
||
|
|
addi x9, zero, 0
|
||
|
|
addi x10, zero, 0
|
||
|
|
addi x11, zero, 0
|
||
|
|
addi x12, zero, 0
|
||
|
|
addi x13, zero, 0
|
||
|
|
addi x14, zero, 0
|
||
|
|
addi x15, zero, 0
|
||
|
|
addi x16, zero, 0
|
||
|
|
addi x17, zero, 0
|
||
|
|
addi x18, zero, 0
|
||
|
|
addi x19, zero, 0
|
||
|
|
addi x20, zero, 0
|
||
|
|
addi x21, zero, 0
|
||
|
|
addi x22, zero, 0
|
||
|
|
addi x23, zero, 0
|
||
|
|
addi x24, zero, 0
|
||
|
|
addi x25, zero, 0
|
||
|
|
addi x26, zero, 0
|
||
|
|
addi x27, zero, 0
|
||
|
|
addi x28, zero, 0
|
||
|
|
addi x29, zero, 0
|
||
|
|
addi x30, zero, 0
|
||
|
|
addi x31, zero, 0
|
||
|
|
|
||
|
|
/* running tests from riscv-tests */
|
||
|
|
|
||
|
|
#ifdef ENABLE_RVTST
|
||
|
|
# define TEST(n) \
|
||
|
|
.global n; \
|
||
|
|
addi x1, zero, 1000; \
|
||
|
|
picorv32_timer_insn(zero, x1); \
|
||
|
|
jal zero,n; \
|
||
|
|
.global n ## _ret; \
|
||
|
|
n ## _ret:
|
||
|
|
#else
|
||
|
|
# define TEST(n) \
|
||
|
|
.global n ## _ret; \
|
||
|
|
n ## _ret:
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef ENABLE_INSTRTST
|
||
|
|
TEST(lui)
|
||
|
|
TEST(auipc)
|
||
|
|
TEST(j)
|
||
|
|
TEST(jal)
|
||
|
|
TEST(jalr)
|
||
|
|
|
||
|
|
TEST(beq)
|
||
|
|
TEST(bne)
|
||
|
|
TEST(blt)
|
||
|
|
TEST(bge)
|
||
|
|
TEST(bltu)
|
||
|
|
TEST(bgeu)
|
||
|
|
|
||
|
|
TEST(lb)
|
||
|
|
TEST(lh)
|
||
|
|
TEST(lw)
|
||
|
|
TEST(lbu)
|
||
|
|
TEST(lhu)
|
||
|
|
|
||
|
|
TEST(sb)
|
||
|
|
TEST(sh)
|
||
|
|
TEST(sw)
|
||
|
|
|
||
|
|
TEST(addi)
|
||
|
|
TEST(slti) // also tests sltiu
|
||
|
|
TEST(xori)
|
||
|
|
TEST(ori)
|
||
|
|
TEST(andi)
|
||
|
|
TEST(slli)
|
||
|
|
TEST(srli)
|
||
|
|
TEST(srai)
|
||
|
|
|
||
|
|
TEST(add)
|
||
|
|
TEST(sub)
|
||
|
|
TEST(sll)
|
||
|
|
TEST(slt) // what is with sltu ?
|
||
|
|
TEST(xor)
|
||
|
|
TEST(srl)
|
||
|
|
TEST(sra)
|
||
|
|
TEST(or)
|
||
|
|
TEST(and)
|
||
|
|
|
||
|
|
TEST(mulh)
|
||
|
|
TEST(mulhsu)
|
||
|
|
TEST(mulhu)
|
||
|
|
TEST(mul)
|
||
|
|
|
||
|
|
TEST(div)
|
||
|
|
TEST(divu)
|
||
|
|
TEST(rem)
|
||
|
|
TEST(remu)
|
||
|
|
|
||
|
|
TEST(simple)
|
||
|
|
#endif // ENABLE_INSTRTST
|
||
|
|
|
||
|
|
/* set stack pointer */
|
||
|
|
lui sp,(64*1024)>>12
|
||
|
|
|
||
|
|
/* set gp and tp */
|
||
|
|
lui gp, %hi(0xdeadbeef)
|
||
|
|
addi gp, gp, %lo(0xdeadbeef)
|
||
|
|
addi tp, gp, 0
|
||
|
|
|
||
|
|
#ifdef ENABLE_SIEVE
|
||
|
|
/* call sieve C code */
|
||
|
|
jal ra,sieve
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef ENABLE_MULTST
|
||
|
|
/* call multest C code */
|
||
|
|
jal ra,multest
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef ENABLE_STATS
|
||
|
|
/* call stats C code */
|
||
|
|
jal ra,stats
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
/* call helloWorld C code */
|
||
|
|
jal ra,helloWorld
|
||
|
|
|
||
|
|
|
||
|
|
/* print "DONE\n" */
|
||
|
|
li a0,0xffff0040
|
||
|
|
addi a1,zero,'D'
|
||
|
|
addi a2,zero,'O'
|
||
|
|
addi a3,zero,'N'
|
||
|
|
addi a4,zero,'E'
|
||
|
|
addi a5,zero,'\n'
|
||
|
|
sw a1,0(a0)
|
||
|
|
sw a2,0(a0)
|
||
|
|
sw a3,0(a0)
|
||
|
|
sw a4,0(a0)
|
||
|
|
sw a5,0(a0)
|
||
|
|
|
||
|
|
li a0, 0x20000000
|
||
|
|
li a1, 123456789
|
||
|
|
sw a1,0(a0)
|
||
|
|
|
||
|
|
/* trap */
|
||
|
|
ebreak
|
||
|
|
|
||
|
|
|
||
|
|
/* Hard mul functions for multest.c
|
||
|
|
**********************************/
|
||
|
|
|
||
|
|
hard_mul:
|
||
|
|
mul a0, a0, a1
|
||
|
|
ret
|
||
|
|
|
||
|
|
hard_mulh:
|
||
|
|
mulh a0, a0, a1
|
||
|
|
ret
|
||
|
|
|
||
|
|
hard_mulhsu:
|
||
|
|
mulhsu a0, a0, a1
|
||
|
|
ret
|
||
|
|
|
||
|
|
hard_mulhu:
|
||
|
|
mulhu a0, a0, a1
|
||
|
|
ret
|