From 36e1b7b0345d9885ffda48b7e3d144a152ff6f4e Mon Sep 17 00:00:00 2001 From: FPGALover Date: Sun, 17 Sep 2023 07:44:18 +0000 Subject: [PATCH] Update README.md --- README.md | 44 ++++++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/README.md b/README.md index 77c2e46..1f4bb5f 100644 --- a/README.md +++ b/README.md @@ -1,34 +1,38 @@ # RISCV_picorv32_fpga ##building RISC-V from scratch, using Linux or WSL ->sudo apt-get update ->sudo apt-get install autoconf automake autotools-dev curl python3 python3-pip libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev ninja-build git cmake libglib2.0-dev ->git clone https://github.com/riscv/riscv-gnu-toolchain ->cd riscv-gnu-toolchain/ ->mkdir build/ ->cd build ->sudo mkdir /opt/riscv32im ->sudo chown $USER /opt/riscv32im ->./configure --with-arch=rv32im --prefix=/opt/riscv32im ->make -j$(nproc) +```html +sudo apt-get update +sudo apt-get install autoconf automake autotools-dev curl python3 python3-pip libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev ninja-build git cmake libglib2.0-dev +git clone https://github.com/riscv/riscv-gnu-toolchain +cd riscv-gnu-toolchain/ +mkdir build/ +cd build +sudo mkdir /opt/riscv32im +sudo chown $USER /opt/riscv32im +./configure --with-arch=rv32im --prefix=/opt/riscv32im +make -j$(nproc) +``` # For other architectures or variations of RISC-V -./configure --with-arch=rv32i /opt/riscv32i/ --> for RV32I -./configure --with-arch=rv32ic /opt/riscv32ic/ --> for RV32IC -./configure --with-arch=rv32im /opt/riscv32im/ --> forRV32IM -./configure --with-arch=rv32imc /opt/riscv32imc/--> for RV32IMC +| Command | ISA | +|:---------------------------------------- |:-------- | +|`./configure --with-arch=rv32i --prefix=/opt/riscv32i/ `| `RV32I `| +|`./configure --with-arch=rv32ic --prefix=/opt/riscv32ic/ `| `RV32IC `| +|`./configure --with-arch=rv32im --prefix=/opt/riscv32im/` | `RV32IM `| +|`./configure --with-arch=rv32imc --prefix=/opt/riscv32imc/`| `RV32IMC `| -windows precompiled https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/ for mingw64 - other precompiled windows and linux toolchain for riscv https://gnutoolchains.com/risc-v/ +## Other Linux and Windows precompiled Toolchains + - https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/ for mingw64 + - https://gnutoolchains.com/risc-v/ # Build the firmware +```html git clone https://gitea.squirrelnut.synology.me:5001/FPGALover/RISCV_picorv32_fpga cd RISCV_picorv32_fpga/sw make clean make firmware/firmware.fpga cp firmware/Memory.v_toplevel_memory_1_symbol* ../rtl/DE0-NANO - - - -# Now you can compile or synthesize the FPGA harware using Quartus or any other Design tool \ No newline at end of file +``` +*Now you can compile or synthesize the FPGA harware using Quartus or any other Design tool*