27 lines
519 B
Plaintext
27 lines
519 B
Plaintext
#
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# yosys ASIC (Not FPGA) synthesis script
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#
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# Read the design
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read_verilog mydesign.v
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# generic synthesis, giving top module
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synth -top mytop
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# mapping to mycells.lib (abc is an optimizer)
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dfflibmap -liberty mycells.lib
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abc -liberty mycells.lib
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opt_clean
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# Write synthesized design
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write_edif synth.edif
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----------------------------------------------
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# icoboard flow:
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SEE icoboard Makefile:
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http://svn.clifford.at/handicraft/2015/c3demo/fpga/Makefile
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from x3 demo:
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https://www.youtube.com/watch?v=SOn0g3k0FlE
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