RISCV_picorv32_fpga/rtl/DE0-NANO/inc/timescale.vh

10 lines
217 B
Systemverilog

`timescale 1 ns / 1 ps
// Use this with non-blocking delays if desired.
// e.g. q <= `D d;
// See http://www.sunburst-design.com/papers/CummingsSNUG2002Boston_NBAwithDelays.pdf
//
`ifndef D
`define D (#1)
`endif