45 lines
2.9 KiB
Plaintext
45 lines
2.9 KiB
Plaintext
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# Copyright 2020 Xilinx Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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## enable tx by forcing 0 from design. sfp0,1,2,3 => a12, a13, b13, c13
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set_property PACKAGE_PIN AE22 [get_ports {sfp_tx_dis[0]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {sfp_tx_dis[0]}]
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#sfp2
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set_property PACKAGE_PIN AA2 [get_ports gt_rx_gt_port_0_p]
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set_property PACKAGE_PIN AA1 [get_ports gt_rx_gt_port_0_n]
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set_property PACKAGE_PIN Y4 [get_ports gt_tx_gt_port_0_p]
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set_property PACKAGE_PIN Y3 [get_ports gt_tx_gt_port_0_n]
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#USER_MGT_SI570_CLOCK2_C_P
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set_property PACKAGE_PIN U10 [get_ports gt_ref_clk_clk_p]
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create_clock -period 6.400 -name gt_ref_clk [get_ports gt_ref_clk_clk_p]
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#LED 2 and 3
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# led 0 .. 7 => ag14, af13, ae13, aj14, aj15, ah13, ah14, al12
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#set_property IOSTANDARD LVCMOS25 [get_ports *led]
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#set_property PACKAGE_PIN AF13 [get_ports axil_reset_led]
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#set_property PACKAGE_PIN AJ14 [get_ports {axi_lite_clk_led[0]}]
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#set_property PACKAGE_PIN AH13 [get_ports {mgt_clk_led[0]}]
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#set_property PACKAGE_PIN AH14 [get_ports {rx_clk_led[0]}]
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#set_property PACKAGE_PIN AG14 [get_ports {sys_reset_led}]
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#set_property PACKAGE_PIN AL12 [get_ports {gtwiz_rst_led}]
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#CR 965826
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#set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -datapath_only 6.40
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#set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -datapath_only 6.40
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#set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_0] -datapath_only 6.40
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#set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0] -datapath_only 6.40
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#set_max_delay -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -datapath_only 10.000
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#set_max_delay -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -datapath_only 10.000
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