Added better DMA, images files, results, for ZCu106 10G

2023-10-20 21:33:05 -07:00 · 2023-10-20 21:33:05 -07:00 · 82e0d5b905
parent fc03ac055e
commit 82e0d5b905
173 changed files with 166790 additions and 9331 deletions
--- a/Petalinux/project-spec/attributes
+++ b/Petalinux/project-spec/attributes
@ -0,0 +1,11 @@
+#Virtual Providers
+
+
+
+#defconfigs
+
+UBOOT_DEFAULT_DEFCONFIG="xilinx_zynqmp_virt_defconfig"
+
+#atf
+
+CONFIG_SUBSYSTEM_PRELOADED_BL33_BASE=0x10080000
--- a/Petalinux/project-spec/configs/busybox/inetd.conf
+++ b/Petalinux/project-spec/configs/busybox/inetd.conf
@ -0,0 +1,22 @@
+#/etc/inetd.conf:  see inetd(8) for further informations.
+#
+# Internet server configuration database
+#
+# If you want to disable an entry so it isn't touched during
+# package updates just comment it out with a single '#' character.
+#
+# <service_name> <sock_type> <proto> <flags> <user> <server_path> <args>
+#
+#:INTERNAL: Internal services
+#echo          stream  tcp     nowait  root    internal
+#echo          dgram   udp     wait    root    internal
+#chargen       stream  tcp     nowait  root    internal
+#chargen       dgram   udp     wait    root    internal
+#discard               stream  tcp     nowait  root    internal
+#discard               dgram   udp     wait    root    internal
+#daytime               stream  tcp     nowait  root    internal
+#daytime       dgram   udp     wait    root    internal
+#time          stream  tcp     nowait  root    internal
+#time          dgram   udp     wait    root    internal
+telnet	stream	tcp	nowait	root	telnetd	telnetd -i
+ftp	stream	tcp	nowait	root	ftpd	ftpd -w 
--- a/Petalinux/project-spec/configs/config
+++ b/Petalinux/project-spec/configs/config
@ -0,0 +1,304 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# misc/config System Configuration
+#
+CONFIG_SUBSYSTEM_TYPE_LINUX=y
+CONFIG_SYSTEM_ZYNQMP=y
+
+#
+# Linux Components Selection
+#
+CONFIG_SUBSYSTEM_COMPONENT_DEVICE__TREE_NAME_DEVICE__TREE__GENERATOR=y
+# CONFIG_SUBSYSTEM_COMPONENT_PRE_FSBL is not set
+CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_FSBL=y
+CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_NAME_ZYNQMP_FSBL=y
+CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_PS_INIT=y
+CONFIG_SUBSYSTEM_COMPONENT_PMU_FIRMWARE=y
+CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_U__BOOT__XLNX=y
+# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_REMOTE is not set
+# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_EXT__LOCAL__SRC is not set
+CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_ARM__TRUSTED__FIRMWARE=y
+# CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_REMOTE is not set
+# CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_EXT__LOCAL__SRC is not set
+CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_LINUX__XLNX=y
+# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_REMOTE is not set
+# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_EXT__LOCAL__SRC is not set
+
+#
+# Auto Config Settings
+#
+CONFIG_SUBSYSTEM_AUTOCONFIG_DEVICE__TREE=y
+# CONFIG_SUBSYSTEM_DEVICE_TREE_MANUAL_INCLUDE is not set
+# CONFIG_SUBSYSTEM_AUTOCONFIG_KERNEL is not set
+# CONFIG_SUBSYSTEM_AUTOCONFIG_U__BOOT is not set
+CONFIG_SUBSYSTEM_HARDWARE_AUTO=y
+CONFIG_SUBSYSTEM_PROCESSOR0_IP_NAME="psu_cortexa53_0"
+CONFIG_SUBSYSTEM_PROCESSOR_psu_cortexa53_0_SELECT=y
+CONFIG_SUBSYSTEM_ARCH_AARCH64=y
+
+#
+# Memory Settings
+#
+CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_SELECT=y
+# CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_1_BANKLESS_SELECT is not set
+# CONFIG_SUBSYSTEM_MEMORY_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_BASEADDR=0x0
+CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_SIZE=0x80000000
+CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_KERNEL_BASEADDR=0x0
+CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_U__BOOT_TEXTBASE_OFFSET=0x100000
+CONFIG_SUBSYSTEM_MEMORY_IP_NAME="PSU_DDR_0"
+
+#
+# Serial Settings
+#
+# CONFIG_SUBSYSTEM_PMUFW_SERIAL_PSU_UART_1_SELECT is not set
+CONFIG_SUBSYSTEM_PMUFW_SERIAL_PSU_UART_0_SELECT=y
+# CONFIG_SUBSYSTEM_PMUFW_SERIAL_MANUAL_SELECT is not set
+# CONFIG_SUBSYSTEM_FSBL_SERIAL_PSU_UART_1_SELECT is not set
+CONFIG_SUBSYSTEM_FSBL_SERIAL_PSU_UART_0_SELECT=y
+# CONFIG_SUBSYSTEM_FSBL_SERIAL_MANUAL_SELECT is not set
+# CONFIG_SUBSYSTEM_ATF_SERIAL_PSU_UART_1_SELECT is not set
+CONFIG_SUBSYSTEM_ATF_SERIAL_PSU_UART_0_SELECT=y
+# CONFIG_SUBSYSTEM_ATF_SERIAL_MANUAL_SELECT is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_SELECT is not set
+CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_SELECT=y
+# CONFIG_SUBSYSTEM_SERIAL_MANUAL_SELECT is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_600 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_9600 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_28800 is not set
+CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_115200=y
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_230400 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_460800 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_921600 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_600 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_9600 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_28800 is not set
+CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_115200=y
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_230400 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_460800 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_921600 is not set
+CONFIG_SUBSYSTEM_SERIAL_PMUFW_IP_NAME="psu_uart_0"
+CONFIG_SUBSYSTEM_SERIAL_FSBL_IP_NAME="psu_uart_0"
+CONFIG_SUBSYSTEM_SERIAL_ATF_IP_NAME="cadence"
+CONFIG_SUBSYSTEM_SERIAL_IP_NAME="psu_uart_0"
+
+#
+# Ethernet Settings
+#
+CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_SELECT=y
+# CONFIG_SUBSYSTEM_ETHERNET_MANUAL_SELECT is not set
+# CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC_AUTO is not set
+CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC="00:0a:35:00:22:01"
+CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_USE_DHCP=y
+
+#
+# Flash Settings
+#
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_SELECT=y
+# CONFIG_SUBSYSTEM_FLASH_MANUAL_SELECT is not set
+# CONFIG_SUBSYSTEM_FLASH__ADVANCED_AUTOCONFIG is not set
+
+#
+# partition 0
+#
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_NAME="boot"
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0x01e00000
+
+#
+# partition 1
+#
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_NAME="bootenv"
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x40000
+
+#
+# partition 2
+#
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_NAME="kernel"
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x3c00000
+
+#
+# partition 3
+#
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME=""
+CONFIG_SUBSYSTEM_FLASH_IP_NAME="psu_qspi_0"
+
+#
+# SD/SDIO Settings
+#
+CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
+# CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_SD_PSU_SD_1_SELECT=y
+
+#
+# RTC Settings
+#
+CONFIG_SUBSYSTEM_RTC_PSU_RTC_SELECT=y
+# CONFIG_SUBSYSTEM_RTC_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_SATA_PSU_SATA_SELECT=y
+CONFIG_SUBSYSTEM_I2C_PSU_I2C_1_SELECT=y
+CONFIG_SUBSYSTEM_I2C_PSU_I2C_0_SELECT=y
+CONFIG_SUBSYSTEM_USB_PSU_USB_0_SELECT=y
+CONFIG_SUBSYSTEM_DP_PSU_DP_SELECT=y
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG=y
+
+#
+# boot image settings
+#
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_FLASH_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_SD_SELECT=y
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_IMAGE_NAME="BOOT.BIN"
+
+#
+# u-boot env partition settings
+#
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_FLASH_SELECT=y
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_SD_SELECT is not set
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_PART_NAME="bootenv"
+
+#
+# kernel image settings
+#
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_FLASH_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_SD_SELECT=y
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_ETHERNET_SELECT is not set
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_IMAGE_NAME="image.ub"
+
+#
+# jffs2 rootfs image settings
+#
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_MEDIA_FLASH_SELECT=y
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_MEDIA_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_PART_NAME="jffs2"
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_IMAGE_NAME="rootfs.jffs2"
+
+#
+# dtb image settings
+#
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_BOOTIMAGE_SELECT=y
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_FLASH_SELECT is not set
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_SD_SELECT is not set
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_ETHERNET_SELECT is not set
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_IMAGE_NAME="system.dtb"
+CONFIG_SUBSYSTEM_ENDIAN_LITTLE=y
+
+#
+# DTG Settings
+#
+CONFIG_SUBSYSTEM_MACHINE_NAME="zcu106-reva"
+CONFIG_SUBSYSTEM_EXTRA_DT_FILES=""
+
+#
+# Kernel Bootargs
+#
+CONFIG_SUBSYSTEM_BOOTARGS_AUTO=y
+CONFIG_SUBSYSTEM_BOOTARGS_EARLYPRINTK=y
+CONFIG_SUBSYSTEM_BOOTARGS_GENERATED=" earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/ram0 rw"
+CONFIG_SUBSYSTEM_DEVICETREE_COMPILER_FLAGS="-@"
+# CONFIG_SUBSYSTEM_DTB_OVERLAY is not set
+# CONFIG_SUBSYSTEM_REMOVE_PL_DTB is not set
+
+#
+# PMUFW Configuration
+#
+CONFIG_SUBSYSTEM_PMUFW_COMPILER_EXTRA_FLAGS=""
+
+#
+# FSBL Configuration
+#
+CONFIG_SUBSYSTEM_FSBL_BSPCOMPILER_FLAGS=""
+CONFIG_SUBSYSTEM_FSBL_COMPILER_EXTRA_FLAGS=""
+
+#
+# ARM Trusted Firmware Configuration
+#
+# CONFIG_SUBSYSTEM_ATF_MEMORY_SETTINGS is not set
+CONFIG_SUBSYSTEM_ATF_EXTRA_COMPILER_FLAGS=""
+CONFIG_SUBSYSTEM_PRELOADED_BL33_BASE=0x10080000
+# CONFIG_SUBSYSTEM_ATF_DEBUG is not set
+
+#
+# FPGA Manager
+#
+# CONFIG_SUBSYSTEM_FPGA_MANAGER is not set
+
+#
+# u-boot Configuration
+#
+CONFIG_SUBSYSTEM_UBOOT_CONFIG_TARGET=""
+# CONFIG_SUBSYSTEM_UBOOT_EXT_DTB is not set
+
+#
+# Linux Configuration
+#
+CONFIG_SUBSYSTEM_LINUX_CONFIG_TARGET=""
+
+#
+# Image Packaging Configuration
+#
+# CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set
+CONFIG_SUBSYSTEM_ROOTFS_INITRD=y
+# CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set
+# CONFIG_SUBSYSTEM_ROOTFS_NFS is not set
+# CONFIG_SUBSYSTEM_ROOTFS_EXT4 is not set
+# CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set
+CONFIG_SUBSYSTEM_INITRD_RAMDISK_LOADADDR=0x0
+CONFIG_SUBSYSTEM_INITRAMFS_IMAGE_NAME="petalinux-image-minimal"
+CONFIG_SUBSYSTEM_UIMAGE_NAME="image.ub"
+CONFIG_SUBSYSTEM_RFS_FORMATS="cpio cpio.gz cpio.gz.u-boot tar.gz jffs2"
+CONFIG_SUBSYSTEM_DTB_PADDING_SIZE=0x1000
+CONFIG_SUBSYSTEM_COPY_TO_TFTPBOOT=y
+CONFIG_SUBSYSTEM_TFTPBOOT_DIR="/tftpboot"
+
+#
+# Firmware Version Configuration
+#
+CONFIG_SUBSYSTEM_HOSTNAME="petalinux-photonic"
+CONFIG_SUBSYSTEM_PRODUCT="petalinux-photonic"
+CONFIG_SUBSYSTEM_FW_VERSION="1.00"
+
+#
+# Yocto Settings
+#
+CONFIG_YOCTO_MACHINE_NAME="zynqmp-generic"
+
+#
+# TMPDIR Location
+#
+CONFIG_TMP_DIR_LOCATION="${PROOT}/build/tmp"
+
+#
+# Devtool Workspace Location
+#
+CONFIG_DEVTOOL_WORKSPACE_LOCATION="${PROOT}/components/yocto/workspace"
+
+#
+# Parallel thread execution
+#
+CONFIG_YOCTO_BB_NUMBER_THREADS=""
+CONFIG_YOCTO_PARALLEL_MAKE=""
+
+#
+# Add pre-mirror url 
+#
+CONFIG_PRE_MIRROR_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/downloads"
+
+#
+# Local sstate feeds settings
+#
+CONFIG_YOCTO_LOCAL_SSTATE_FEEDS_URL=""
+CONFIG_YOCTO_NETWORK_SSTATE_FEEDS=y
+
+#
+# Network sstate feeds URL
+#
+CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/aarch64/sstate-cache"
+# CONFIG_YOCTO_BB_NO_NETWORK is not set
+
+#
+# User Layers
+#
+CONFIG_USER_LAYER_0=""
--- a/Petalinux/project-spec/configs/config.old
+++ b/Petalinux/project-spec/configs/config.old
@ -0,0 +1,305 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# misc/config System Configuration
+#
+CONFIG_SUBSYSTEM_TYPE_LINUX=y
+CONFIG_SYSTEM_ZYNQMP=y
+
+#
+# Linux Components Selection
+#
+CONFIG_SUBSYSTEM_COMPONENT_DEVICE__TREE_NAME_DEVICE__TREE__GENERATOR=y
+# CONFIG_SUBSYSTEM_COMPONENT_PRE_FSBL is not set
+CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_FSBL=y
+CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_NAME_ZYNQMP_FSBL=y
+CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_PS_INIT=y
+CONFIG_SUBSYSTEM_COMPONENT_PMU_FIRMWARE=y
+CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_U__BOOT__XLNX=y
+# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_REMOTE is not set
+# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_EXT__LOCAL__SRC is not set
+CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_ARM__TRUSTED__FIRMWARE=y
+# CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_REMOTE is not set
+# CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_EXT__LOCAL__SRC is not set
+CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_LINUX__XLNX=y
+# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_REMOTE is not set
+# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_EXT__LOCAL__SRC is not set
+
+#
+# Auto Config Settings
+#
+CONFIG_SUBSYSTEM_AUTOCONFIG_DEVICE__TREE=y
+# CONFIG_SUBSYSTEM_DEVICE_TREE_MANUAL_INCLUDE is not set
+# CONFIG_SUBSYSTEM_AUTOCONFIG_KERNEL is not set
+# CONFIG_SUBSYSTEM_AUTOCONFIG_U__BOOT is not set
+CONFIG_SUBSYSTEM_HARDWARE_AUTO=y
+CONFIG_SUBSYSTEM_PROCESSOR0_IP_NAME="psu_cortexa53_0"
+CONFIG_SUBSYSTEM_PROCESSOR_psu_cortexa53_0_SELECT=y
+CONFIG_SUBSYSTEM_ARCH_AARCH64=y
+
+#
+# Memory Settings
+#
+CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_SELECT=y
+# CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_1_BANKLESS_SELECT is not set
+# CONFIG_SUBSYSTEM_MEMORY_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_BASEADDR=0x0
+CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_SIZE=0x80000000
+CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_KERNEL_BASEADDR=0x0
+CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_U__BOOT_TEXTBASE_OFFSET=0x100000
+CONFIG_SUBSYSTEM_MEMORY_IP_NAME="PSU_DDR_0"
+
+#
+# Serial Settings
+#
+# CONFIG_SUBSYSTEM_PMUFW_SERIAL_PSU_UART_1_SELECT is not set
+CONFIG_SUBSYSTEM_PMUFW_SERIAL_PSU_UART_0_SELECT=y
+# CONFIG_SUBSYSTEM_PMUFW_SERIAL_MANUAL_SELECT is not set
+# CONFIG_SUBSYSTEM_FSBL_SERIAL_PSU_UART_1_SELECT is not set
+CONFIG_SUBSYSTEM_FSBL_SERIAL_PSU_UART_0_SELECT=y
+# CONFIG_SUBSYSTEM_FSBL_SERIAL_MANUAL_SELECT is not set
+# CONFIG_SUBSYSTEM_ATF_SERIAL_PSU_UART_1_SELECT is not set
+CONFIG_SUBSYSTEM_ATF_SERIAL_PSU_UART_0_SELECT=y
+# CONFIG_SUBSYSTEM_ATF_SERIAL_MANUAL_SELECT is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_SELECT is not set
+CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_SELECT=y
+# CONFIG_SUBSYSTEM_SERIAL_MANUAL_SELECT is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_600 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_9600 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_28800 is not set
+CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_115200=y
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_230400 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_460800 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_921600 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_600 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_9600 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_28800 is not set
+CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_115200=y
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_230400 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_460800 is not set
+# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_921600 is not set
+CONFIG_SUBSYSTEM_SERIAL_PMUFW_IP_NAME="psu_uart_0"
+CONFIG_SUBSYSTEM_SERIAL_FSBL_IP_NAME="psu_uart_0"
+CONFIG_SUBSYSTEM_SERIAL_ATF_IP_NAME="cadence"
+CONFIG_SUBSYSTEM_SERIAL_IP_NAME="psu_uart_0"
+
+#
+# Ethernet Settings
+#
+CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_SELECT=y
+# CONFIG_SUBSYSTEM_ETHERNET_MANUAL_SELECT is not set
+# CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC_AUTO is not set
+CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC="00:0a:35:00:22:01"
+CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_USE_DHCP=y
+
+#
+# Flash Settings
+#
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_SELECT=y
+# CONFIG_SUBSYSTEM_FLASH_MANUAL_SELECT is not set
+# CONFIG_SUBSYSTEM_FLASH__ADVANCED_AUTOCONFIG is not set
+
+#
+# partition 0
+#
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_NAME="boot"
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0x01e00000
+
+#
+# partition 1
+#
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_NAME="bootenv"
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x40000
+
+#
+# partition 2
+#
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_NAME="kernel"
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x3c00000
+
+#
+# partition 3
+#
+CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME=""
+CONFIG_SUBSYSTEM_FLASH_IP_NAME="psu_qspi_0"
+
+#
+# SD/SDIO Settings
+#
+CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
+# CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_SD_PSU_SD_1_SELECT=y
+
+#
+# RTC Settings
+#
+CONFIG_SUBSYSTEM_RTC_PSU_RTC_SELECT=y
+# CONFIG_SUBSYSTEM_RTC_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_SATA_PSU_SATA_SELECT=y
+CONFIG_SUBSYSTEM_I2C_PSU_I2C_1_SELECT=y
+CONFIG_SUBSYSTEM_I2C_PSU_I2C_0_SELECT=y
+CONFIG_SUBSYSTEM_USB_PSU_USB_0_SELECT=y
+CONFIG_SUBSYSTEM_DP_PSU_DP_SELECT=y
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG=y
+
+#
+# boot image settings
+#
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_FLASH_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_SD_SELECT=y
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_IMAGE_NAME="BOOT.BIN"
+
+#
+# u-boot env partition settings
+#
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_FLASH_SELECT=y
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_SD_SELECT is not set
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_PART_NAME="bootenv"
+
+#
+# kernel image settings
+#
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_FLASH_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_SD_SELECT=y
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_ETHERNET_SELECT is not set
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_IMAGE_NAME="image.ub"
+
+#
+# jffs2 rootfs image settings
+#
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_MEDIA_FLASH_SELECT=y
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_MEDIA_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_PART_NAME="jffs2"
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_IMAGE_NAME="rootfs.jffs2"
+
+#
+# dtb image settings
+#
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_BOOTIMAGE_SELECT=y
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_FLASH_SELECT is not set
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_SD_SELECT is not set
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_ETHERNET_SELECT is not set
+# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_MANUAL_SELECT is not set
+CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_IMAGE_NAME="system.dtb"
+CONFIG_SUBSYSTEM_ENDIAN_LITTLE=y
+
+#
+# DTG Settings
+#
+CONFIG_SUBSYSTEM_MACHINE_NAME="zcu106-reva"
+CONFIG_SUBSYSTEM_EXTRA_DT_FILES=""
+
+#
+# Kernel Bootargs
+#
+CONFIG_SUBSYSTEM_BOOTARGS_AUTO=y
+CONFIG_SUBSYSTEM_BOOTARGS_EARLYPRINTK=y
+
+CONFIG_SUBSYSTEM_DEVICETREE_COMPILER_FLAGS="-@"
+# CONFIG_SUBSYSTEM_DTB_OVERLAY is not set
+# CONFIG_SUBSYSTEM_REMOVE_PL_DTB is not set
+
+#
+# PMUFW Configuration
+#
+CONFIG_SUBSYSTEM_PMUFW_COMPILER_EXTRA_FLAGS=""
+
+#
+# FSBL Configuration
+#
+CONFIG_SUBSYSTEM_FSBL_BSPCOMPILER_FLAGS=""
+CONFIG_SUBSYSTEM_FSBL_COMPILER_EXTRA_FLAGS=""
+
+#
+# ARM Trusted Firmware Configuration
+#
+# CONFIG_SUBSYSTEM_ATF_MEMORY_SETTINGS is not set
+CONFIG_SUBSYSTEM_ATF_EXTRA_COMPILER_FLAGS=""
+CONFIG_SUBSYSTEM_PRELOADED_BL33_BASE=0x10080000
+# CONFIG_SUBSYSTEM_ATF_DEBUG is not set
+
+#
+# FPGA Manager
+#
+# CONFIG_SUBSYSTEM_FPGA_MANAGER is not set
+
+#
+# u-boot Configuration
+#
+CONFIG_SUBSYSTEM_UBOOT_CONFIG_TARGET=""
+# CONFIG_SUBSYSTEM_UBOOT_EXT_DTB is not set
+
+#
+# Linux Configuration
+#
+CONFIG_SUBSYSTEM_LINUX_CONFIG_TARGET=""
+
+#
+# Image Packaging Configuration
+#
+# CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set
+CONFIG_SUBSYSTEM_ROOTFS_INITRD=y
+# CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set
+# CONFIG_SUBSYSTEM_ROOTFS_NFS is not set
+# CONFIG_SUBSYSTEM_ROOTFS_EXT4 is not set
+# CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set
+CONFIG_SUBSYSTEM_INITRD_RAMDISK_LOADADDR=0x0
+CONFIG_SUBSYSTEM_INITRAMFS_IMAGE_NAME="petalinux-image-minimal"
+CONFIG_SUBSYSTEM_UIMAGE_NAME="image.ub"
+CONFIG_SUBSYSTEM_RFS_FORMATS="cpio cpio.gz cpio.gz.u-boot tar.gz jffs2"
+CONFIG_SUBSYSTEM_DTB_PADDING_SIZE=0x1000
+CONFIG_SUBSYSTEM_COPY_TO_TFTPBOOT=y
+CONFIG_SUBSYSTEM_TFTPBOOT_DIR="/tftpboot"
+
+#
+# Firmware Version Configuration
+#
+CONFIG_SUBSYSTEM_HOSTNAME="petalinux-photonic"
+CONFIG_SUBSYSTEM_PRODUCT="petalinux-photonic"
+CONFIG_SUBSYSTEM_FW_VERSION="1.00"
+
+#
+# Yocto Settings
+#
+CONFIG_YOCTO_MACHINE_NAME="zynqmp-generic"
+
+#
+# TMPDIR Location
+#
+CONFIG_TMP_DIR_LOCATION="${PROOT}/build/tmp"
+
+#
+# Devtool Workspace Location
+#
+CONFIG_DEVTOOL_WORKSPACE_LOCATION="${PROOT}/components/yocto/workspace"
+
+#
+# Parallel thread execution
+#
+CONFIG_YOCTO_BB_NUMBER_THREADS=""
+CONFIG_YOCTO_PARALLEL_MAKE=""
+
+#
+# Add pre-mirror url 
+#
+CONFIG_PRE_MIRROR_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/downloads"
+
+#
+# Local sstate feeds settings
+#
+CONFIG_YOCTO_LOCAL_SSTATE_FEEDS_URL=""
+CONFIG_YOCTO_NETWORK_SSTATE_FEEDS=y
+
+#
+# Network sstate feeds URL
+#
+CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/aarch64/sstate-cache"
+# CONFIG_YOCTO_BB_NO_NETWORK is not set
+
+#
+# User Layers
+#
+CONFIG_USER_LAYER_0=""
+CONFIG_SUBSYSTEM_BOOTARGS_GENERATED=" earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/ram0 rw"
--- a/Petalinux/project-spec/configs/init-ifupdown/interfaces
+++ b/Petalinux/project-spec/configs/init-ifupdown/interfaces
@ -0,0 +1,31 @@
+# /etc/network/interfaces -- configuration file for ifup(8), ifdown(8)
+ 
+# The loopback interface
+auto lo
+iface lo inet loopback
+
+# Wireless interfaces
+iface wlan0 inet dhcp
+	wireless_mode managed
+	wireless_essid any
+	wpa-driver wext
+	wpa-conf /etc/wpa_supplicant.conf
+
+iface atml0 inet dhcp
+
+# Wired or wireless interfaces
+auto eth0
+iface eth0 inet dhcp
+iface eth1 inet dhcp
+
+# Ethernet/RNDIS gadget (g_ether)
+# ... or on host side, usbnet and random hwaddr
+iface usb0 inet static
+	address 192.168.7.2
+	netmask 255.255.255.0
+	network 192.168.7.0
+	gateway 192.168.7.1
+
+# Bluetooth networking
+iface bnep0 inet dhcp
+
--- a/Petalinux/project-spec/configs/rootfs_config
+++ b/Petalinux/project-spec/configs/rootfs_config
--- a/Petalinux/project-spec/configs/rootfs_config.old
+++ b/Petalinux/project-spec/configs/rootfs_config.old
--- a/Petalinux/project-spec/hw-description/metadata
+++ b/Petalinux/project-spec/hw-description/metadata
--- a/Petalinux/project-spec/hw-description/pl_eth_10g_wrapper2.bit
+++ b/Petalinux/project-spec/hw-description/pl_eth_10g_wrapper2.bit
--- a/Petalinux/project-spec/hw-description/psu_init.c
+++ b/Petalinux/project-spec/hw-description/psu_init.c
--- a/Petalinux/project-spec/hw-description/psu_init.h
+++ b/Petalinux/project-spec/hw-description/psu_init.h
--- a/Petalinux/project-spec/hw-description/psu_init.html
+++ b/Petalinux/project-spec/hw-description/psu_init.html
--- a/Petalinux/project-spec/hw-description/psu_init.tcl
+++ b/Petalinux/project-spec/hw-description/psu_init.tcl
--- a/Petalinux/project-spec/hw-description/psu_init_gpl.c
+++ b/Petalinux/project-spec/hw-description/psu_init_gpl.c
--- a/Petalinux/project-spec/hw-description/psu_init_gpl.h
+++ b/Petalinux/project-spec/hw-description/psu_init_gpl.h
--- a/Petalinux/project-spec/hw-description/system.xsa
+++ b/Petalinux/project-spec/hw-description/system.xsa
--- a/Petalinux/project-spec/meta-user/COPYING.MIT
+++ b/Petalinux/project-spec/meta-user/COPYING.MIT
@ -0,0 +1,17 @@
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
--- a/Petalinux/project-spec/meta-user/README
+++ b/Petalinux/project-spec/meta-user/README
@ -0,0 +1,64 @@
+This README file contains information on the contents of the
+meta-user layer.
+
+Please see the corresponding sections below for details.
+
+
+Dependencies
+============
+
+This layer depends on:
+
+  URI: git://git.openembedded.org/bitbake
+  branch: master
+
+  URI: git://git.openembedded.org/openembedded-core
+  layers: meta
+  branch: master
+
+  URI: git://git.yoctoproject.org/xxxx
+  layers: xxxx
+  branch: master
+
+
+Patches
+=======
+
+Please submit any patches against the meta-user layer to the
+xxxx mailing list (xxxx@zzzz.org) and cc: the maintainer:
+
+Maintainer: XXX YYYYYY <xxx.yyyyyy@zzzzz.com>
+
+
+Table of Contents
+=================
+
+  I. Adding the meta-user layer to your build
+ II. Misc
+
+
+I. Adding the meta-user layer to your build
+=================================================
+
+--- replace with specific instructions for the meta-user layer ---
+
+In order to use this layer, you need to make the build system aware of
+it.
+
+Assuming the meta-user layer exists at the top-level of your
+yocto build tree, you can add it to the build system by adding the
+location of the meta-user layer to bblayers.conf, along with any
+other layers needed. e.g.:
+
+  BBLAYERS ?= " \
+    /path/to/yocto/meta \
+    /path/to/yocto/meta-poky \
+    /path/to/yocto/meta-yocto-bsp \
+    /path/to/yocto/meta-meta-user \
+    "
+
+
+II. Misc
+========
+
+--- replace with specific information about the meta-user layer ---
--- a/Petalinux/project-spec/meta-user/conf/layer.conf
+++ b/Petalinux/project-spec/meta-user/conf/layer.conf
@ -0,0 +1,11 @@
+# We have a conf and classes directory, add to BBPATH
+BBPATH .= ":${LAYERDIR}"
+
+# We have recipes-* directories, add to BBFILES
+BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \
+	${LAYERDIR}/recipes-*/*/*.bbappend"
+
+BBFILE_COLLECTIONS += "meta-user"
+BBFILE_PATTERN_meta-user = "^${LAYERDIR}/"
+BBFILE_PRIORITY_meta-user = "6"
+LAYERSERIES_COMPAT_meta-user = "zeus"
--- a/Petalinux/project-spec/meta-user/conf/petalinuxbsp.conf
+++ b/Petalinux/project-spec/meta-user/conf/petalinuxbsp.conf
@ -0,0 +1,5 @@
+#User Configuration
+
+#OE_TERMINAL = "tmux"
+
+IMAGE_BOOT_FILES_zynqmp = "BOOT.BIN boot.scr Image rootfs.cpio.gz.u-boot"
--- a/Petalinux/project-spec/meta-user/conf/user-rootfsconfig
+++ b/Petalinux/project-spec/meta-user/conf/user-rootfsconfig
@ -0,0 +1,11 @@
+#Note: Mention Each package in individual line
+#These packages will get added into rootfs menu entry
+
+CONFIG_gpio-demo
+CONFIG_peekpoke
+CONFIG_myapp-init
+
+CONFIG_iperf3
+CONFIG_ethtool
+CONFIG_phytool
+
--- a/Petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/Makefile
+++ b/Petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/Makefile
@ -0,0 +1,14 @@
+APP = gpio-demo
+
+# Add any other object files to this list below
+APP_OBJS = gpio-demo.o
+
+all: $(APP)
+
+$(APP): $(APP_OBJS)
+	$(CC) $(LDFLAGS) -o $@ $(APP_OBJS) $(LDLIBS)
+
+clean:
+	-rm -f $(APP) *.elf *.gdb *.o
+
+
--- a/Petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c
+++ b/Petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c
@ -0,0 +1,355 @@
+/*
+*
+* gpio-demo app
+*
+* Copyright (C) 2013 - 2016  Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person
+* obtaining a copy of this software and associated documentation
+* files (the "Software"), to deal in the Software without restriction,
+* including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software,
+* and to permit persons to whom the Software is furnished to do so,
+* subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in this
+* Software without prior written authorization from Xilinx.
+*
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <signal.h>
+
+#define GPIO_ROOT "/sys/class/gpio"
+#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0]))
+
+static enum {NONE, IN, OUT, CYLON, KIT} gpio_opt = NONE;
+
+static const unsigned long cylon[] = {
+	0x00000080, 0x00000040, 0x00000020, 0x00000010,
+	0x00000008, 0x00000004, 0x00000002, 0x00000001,
+		    0x00000002, 0x00000004, 0x00000008,
+	0x00000010, 0x00000020, 0x00000040, 0x00000080,
+};
+
+static const unsigned long kit[] = {
+	0x000000e0, 0x00000070, 0x00000038, 0x0000001c,
+	0x0000000e, 0x00000007, 0x00000003, 0x00000001,
+		    0x00000003, 0x00000007, 0x0000000e,
+	0x0000001c, 0x00000038, 0x00000070, 0x000000e0,
+};
+
+static int gl_gpio_base = 0;
+
+static void usage (char *argv0)
+{
+	char *basename = strrchr(argv0, '/');
+	if (!basename)
+		basename = argv0;
+
+	fprintf(stderr,
+		"Usage: %s [-g GPIO_BASE] COMMAND\n"
+		"\twhere COMMAND is one of:\n"
+		"\t\t-i\t\tInput value from GPIO and print it\n"
+		"\t\t-o\tVALUE\tOutput value to GPIO\n"
+		"\t\t-c\t\tCylon test pattern\n"
+		"\t\t-k\t\t KIT test pattern\n"
+		"\tGPIO_BASE indicates which GPIO chip to talk to (The number can be \n"
+		"\tfound at /sys/class/gpio/gpiochipN).\n"
+		"\tThe highest gpiochipN is the first gpio listed in the dts file, \n"
+		"\tand the lowest gpiochipN is the last gpio listed in the dts file.\n"
+		"\tE.g.If the gpiochip240 is the LED_8bit gpio, and I want to output '1' \n"
+		"\tto the LED_8bit gpio, the command should be:\n"
+		"\t\tgpio-demo -g 240 -o 1\n"
+		"\n"
+		"\tgpio-demo written by Xilinx Inc.\n"
+		"\n"
+		,  basename);
+	exit(-2);
+}
+
+static int open_gpio_channel(int gpio_base)
+{
+	char gpio_nchan_file[128];
+	int gpio_nchan_fd;
+	int gpio_max;
+	int nchannel;
+	char nchannel_str[5];
+	char *cptr;
+	int c;
+	char channel_str[5];
+
+	char *gpio_export_file = "/sys/class/gpio/export";
+	int export_fd=0;
+
+	/* Check how many channels the GPIO chip has */
+	sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base);
+	gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY);
+	if (gpio_nchan_fd < 0) {
+		fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno)); 
+		return -1;
+	}
+	read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str));
+	close(gpio_nchan_fd);
+	nchannel=(int)strtoul(nchannel_str, &cptr, 0);
+	if (cptr == nchannel_str) {
+		fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str);
+		exit(1);
+	}
+
+	/* Open files for each GPIO channel */
+	export_fd=open(gpio_export_file, O_WRONLY);
+	if (export_fd < 0) {
+		fprintf(stderr, "Cannot open GPIO to export %d\n", gpio_base);
+		return -1;
+	}
+
+	gpio_max = gpio_base + nchannel;	
+	for(c = gpio_base; c < gpio_max; c++) {
+		sprintf(channel_str, "%d", c);
+		write(export_fd, channel_str, (strlen(channel_str)+1));
+	}
+	close(export_fd);
+	return nchannel;
+}
+
+static int close_gpio_channel(int gpio_base)
+{
+	char gpio_nchan_file[128];
+	int gpio_nchan_fd;
+	int gpio_max;
+	int nchannel;
+	char nchannel_str[5];
+	char *cptr;
+	int c;
+	char channel_str[5];
+
+	char *gpio_unexport_file = "/sys/class/gpio/unexport";
+	int unexport_fd=0;
+
+	/* Check how many channels the GPIO chip has */
+	sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base);
+	gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY);
+	if (gpio_nchan_fd < 0) {
+		fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno)); 
+		return -1;
+	}
+	read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str));
+	close(gpio_nchan_fd);
+	nchannel=(int)strtoul(nchannel_str, &cptr, 0);
+	if (cptr == nchannel_str) {
+		fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str);
+		exit(1);
+	}
+
+	/* Close opened files for each GPIO channel */
+	unexport_fd=open(gpio_unexport_file, O_WRONLY);
+	if (unexport_fd < 0) {
+		fprintf(stderr, "Cannot close GPIO by writing unexport %d\n", gpio_base);
+		return -1;
+	}
+
+	gpio_max = gpio_base + nchannel;	
+	for(c = gpio_base; c < gpio_max; c++) {
+		sprintf(channel_str, "%d", c);
+		write(unexport_fd, channel_str, (strlen(channel_str)+1));
+	}
+	close(unexport_fd);
+	return 0;
+}
+
+static int set_gpio_direction(int gpio_base, int nchannel, char *direction)
+{
+	char gpio_dir_file[128];
+	int direction_fd=0;
+	int gpio_max;
+	int c;
+
+	gpio_max = gpio_base + nchannel;
+	for(c = gpio_base; c < gpio_max; c++) {
+		sprintf(gpio_dir_file, "/sys/class/gpio/gpio%d/direction",c);
+		direction_fd=open(gpio_dir_file, O_RDWR);
+		if (direction_fd < 0) {
+			fprintf(stderr, "Cannot open the direction file for GPIO %d\n", c);
+			return 1;
+		}
+		write(direction_fd, direction, (strlen(direction)+1));
+		close(direction_fd);
+	}
+	return 0;
+}
+
+static int set_gpio_value(int gpio_base, int nchannel, int value)
+{
+	char gpio_val_file[128];
+	int val_fd=0;
+	int gpio_max;
+	char val_str[2];
+	int c;
+
+	gpio_max = gpio_base + nchannel;
+
+	for(c = gpio_base; c < gpio_max; c++) {
+		sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c);
+		val_fd=open(gpio_val_file, O_RDWR);
+		if (val_fd < 0) {
+			fprintf(stderr, "Cannot open the value file of GPIO %d\n", c);
+			return -1;
+		}
+		sprintf(val_str,"%d", (value & 1));
+		write(val_fd, val_str, sizeof(val_str));
+		close(val_fd);
+		value >>= 1;
+	}
+	return 0;
+}
+
+static int get_gpio_value(int gpio_base, int nchannel)
+{
+	char gpio_val_file[128];
+	int val_fd=0;
+	int gpio_max;
+	char val_str[2];
+	char *cptr;
+	int value = 0;
+	int c;
+
+	gpio_max = gpio_base + nchannel;
+
+	for(c = gpio_max-1; c >= gpio_base; c--) {
+		sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c);
+		val_fd=open(gpio_val_file, O_RDWR);
+		if (val_fd < 0) {
+			fprintf(stderr, "Cannot open GPIO to export %d\n", c);
+			return -1;
+		}
+		read(val_fd, val_str, sizeof(val_str));
+		value <<= 1;
+		value += (int)strtoul(val_str, &cptr, 0);
+		if (cptr == optarg) {
+			fprintf(stderr, "Failed to change %s into integer", val_str);
+		}
+		close(val_fd);
+	}
+	return value;
+}
+
+void signal_handler(int sig)
+{
+	switch (sig) {
+		case SIGTERM:
+		case SIGHUP:
+		case SIGQUIT:
+		case SIGINT:
+			close_gpio_channel(gl_gpio_base);
+			exit(0) ;
+		default:
+			break;
+	}
+}
+
+int main(int argc, char *argv[])
+{
+	extern char *optarg;
+	char *cptr;
+	int gpio_value = 0;
+	int nchannel = 0;
+
+	int c;
+	int i;
+
+	opterr = 0;
+	
+	while ((c = getopt(argc, argv, "g:io:ck")) != -1) {
+		switch (c) {
+			case 'g':
+				gl_gpio_base = (int)strtoul(optarg, &cptr, 0);
+				if (cptr == optarg)
+					usage(argv[0]);
+				break;
+			case 'i':
+				gpio_opt = IN;
+				break;
+			case 'o':
+				gpio_opt = OUT;
+				gpio_value = (int)strtoul(optarg, &cptr, 0);
+				if (cptr == optarg)
+					usage(argv[0]);
+				break;
+			case 'c':
+				gpio_opt = CYLON;
+				break;
+			case 'k':
+				gpio_opt = KIT;
+				break;
+			case '?':
+				usage(argv[0]);
+			default:
+				usage(argv[0]);
+				
+		}
+	}
+
+	if (gl_gpio_base == 0) {
+		usage(argv[0]);
+	}
+
+	nchannel = open_gpio_channel(gl_gpio_base);
+	signal(SIGTERM, signal_handler); /* catch kill signal */
+	signal(SIGHUP, signal_handler); /* catch hang up signal */
+	signal(SIGQUIT, signal_handler); /* catch quit signal */
+	signal(SIGINT, signal_handler); /* catch a CTRL-c signal */
+	switch (gpio_opt) {
+		case IN:
+			set_gpio_direction(gl_gpio_base, nchannel, "in");
+			gpio_value=get_gpio_value(gl_gpio_base, nchannel);
+			fprintf(stdout,"0x%08X\n", gpio_value);
+			break;
+		case OUT:
+			set_gpio_direction(gl_gpio_base, nchannel, "out");
+			set_gpio_value(gl_gpio_base, nchannel, gpio_value);
+			break;
+		case CYLON:
+#define CYLON_DELAY_USECS (10000)
+			set_gpio_direction(gl_gpio_base, nchannel, "out");
+			for (;;) {
+				for(i=0; i < ARRAY_SIZE(cylon); i++) {
+					gpio_value=(int)cylon[i];
+					set_gpio_value(gl_gpio_base, nchannel, gpio_value);
+				}
+				usleep(CYLON_DELAY_USECS);
+			}
+		case KIT:
+#define KIT_DELAY_USECS (10000)
+			set_gpio_direction(gl_gpio_base, nchannel, "out");
+			for (;;) {
+				for (i=0; i<ARRAY_SIZE(kit); i++) {
+					gpio_value=(int)kit[i];
+					set_gpio_value(gl_gpio_base, nchannel, gpio_value);
+				}
+				usleep(KIT_DELAY_USECS);
+			}
+		default:
+			break;
+	}
+	close_gpio_channel(gl_gpio_base);
+	return 0;
+}
+
+
--- a/Petalinux/project-spec/meta-user/recipes-apps/gpio-demo/gpio-demo.bb
+++ b/Petalinux/project-spec/meta-user/recipes-apps/gpio-demo/gpio-demo.bb
@ -0,0 +1,23 @@
+#
+# This is the GPIO-DEMO apllication recipe
+#
+#
+
+SUMMARY = "gpio-demo application"
+SECTION = "PETALINUX/apps"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+SRC_URI = "file://gpio-demo.c \
+           file://Makefile \
+        "
+S = "${WORKDIR}"
+CFLAGS_prepend = "-I ${S}/include"
+do_compile() {
+        oe_runmake
+}
+do_install() {
+        install -d ${D}${bindir}
+        install -m 0755 ${S}/gpio-demo ${D}${bindir}
+
+}
+
--- a/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/.gdbinit
+++ b/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/.gdbinit
@ -0,0 +1,3 @@
+# Load the PetaLinux SDK main gdbinit script
+source plnx_gdbinit
+
--- a/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/README
+++ b/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/README
@ -0,0 +1,30 @@
+PetaLinux User Application Template
+===================================
+
+This directory contains a PetaLinux user application created from a template.
+
+You can easily import any already built application or script by copying
+it into this directory, and editing the automatically generated Makefile 
+as described below.
+
+Modify the "install:" target in Makefile to use $(TARGETINST) to install your
+prebuilt application or script to the host copy of the target file system
+referring to the comments of the "install:" target.
+
+Before building the application, you will need to enable the application
+from PetaLinux menuconfig by running:
+    "petalinux-config -c rootfs"
+You will see your application in the "apps --->" submenu.
+
+To install your prebuilt application or script to the target file system
+copy on the host, simply run the command.
+    "petalinux-build -c rootfs/myapp-init"
+
+You will also need to rebuild PetaLinux bootable images so that the images
+is updated with the updated target filesystem copy, run this command:
+    "petalinux-build -c rootfs"
+
+You can also run one PetaLinux command to install the application to the
+target filesystem host copy and update the bootable images as follows:
+    "petalinux-build"
+
--- a/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/files/myapp-init
+++ b/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/files/myapp-init
@ -0,0 +1,5 @@
+#!/bin/sh
+
+echo "booting from sd card, in myapp"
+cd /mnt/sd-mmcblk0p1
+./startup_script.cmd
--- a/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/files/myapp-init.bak
+++ b/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/files/myapp-init.bak
@ -0,0 +1,63 @@
+#!/bin/sh
+
+echo "Hello PetaLinux World This is an example startup script, ver 4"
+
+reset_counters() {
+  # Read the file into an associative array
+  declare -A counters
+  while read line; do
+    # Split the line into key and value
+    key=$(echo "$line" | cut -d= -f1)
+    value=$(echo "$line" | cut -d= -f2)
+    # Store the key-value pair in the array
+    counters["$key"]=$value
+  done < counter_env
+
+  # Reset the values in the array
+  counters["nu_nw_upgrade_counter"]=0
+  counters["nu_nw_global_counter"]=0
+  counters["nu_lc_boot_counter"]=0
+  counters["nu_lc_backup_counter"]=0
+
+  # Write the array back to the file
+  for key in "${!counters[@]}"; do
+    echo "$key=${counters[$key]}" >> counter_env.tmp
+  done
+
+  # Replace the original file with the updated file
+  mv counter_env.tmp counter_env
+}
+
+# get the user boot mode pins
+boot_mode_reg=`peek 0x00FF5E0204`
+boot_from_sd_card_reg_val="0x00000555"
+boot_from_emmc_reg_val="0x00000666"
+
+if [ "$boot_mode_reg" = "$boot_from_sd_card_reg_val" ]; then
+#
+# SD BOOT
+#
+echo "booting from sd card based on user boot mode"
+cd /mnt/sd-mmcblk1p1
+  echo "Starting Crashkernel Service"
+  kexec -p /mnt/sd-mmcblk1p1/crashkernel/vmlinux --initrd=/mnt/sd-mmcblk1p1/crashkernel/rootfs.cpio
+  echo "Resetting U-Boot Counters"
+  reset_counters
+./startup_script.cmd
+elif [ "$boot_mode_reg" = "$boot_from_emmc_reg_val" ]; then
+#
+# EMMC BOOT
+#
+echo "booting from emmc based on boot mode"
+cd /mnt/sd-mmcblk0p1
+  echo "Starting Crashkernel Service"
+  kexec -p /mnt/sd-mmcblk0p1/crashkernel/vmlinux --initrd=/mnt/sd-mmcblk0p1/crashkernel/rootfs.cpio
+  echo "Resetting U-Boot Counters"
+  reset_counters
+./startup_script.cmd
+else
+#
+# Should never be here
+#
+echo "[ERROR] user boot mode unsupported, waiting for system reset..."
+fi
--- a/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/myapp-init.bb
+++ b/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/myapp-init.bb
@ -0,0 +1,26 @@
+#
+# This file is the myapp-init recipe.
+#
+
+SUMMARY = "Simple myapp-init application"
+SECTION = "PETALINUX/apps"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+
+SRC_URI = "file://myapp-init \
+	"
+
+S = "${WORKDIR}"
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+inherit update-rc.d
+
+INITSCRIPT_NAME = "myapp-init"
+INITSCRIPT_PARAMS = "start 99 S ."
+
+do_install() {
+		install -d ${D}${sysconfdir}/init.d
+		install -m 0755 ${S}/myapp-init ${D}${sysconfdir}/init.d/myapp-init
+}
+FILES_${PN} += "${sysconfdir}/*"
--- a/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/myapp-init.bb.bak
+++ b/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/myapp-init.bb.bak
@ -0,0 +1,18 @@
+#
+# This file is the myapp-init recipe.
+#
+
+SUMMARY = "Simple myapp-init application"
+SECTION = "PETALINUX/apps"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+
+SRC_URI = "file://myapp-init \
+	"
+
+S = "${WORKDIR}"
+
+do_install() {
+	     install -d ${D}/${bindir}
+	     install -m 0755 ${S}/myapp-init ${D}/${bindir}
+}
--- a/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/Makefile
+++ b/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/Makefile
@ -0,0 +1,19 @@
+PEEK = peek
+POKE = poke
+
+# Add any other object files to this list below
+PEEK_OBJS = peek.o
+POKE_OBJS = poke.o
+
+all: $(PEEK) $(POKE)
+
+$(POKE): $(POKE_OBJS)
+	$(CC) $(LDFLAGS) -o $@ $(POKE_OBJS) $(LDLIBS)
+
+$(PEEK): $(PEEK_OBJS)
+	$(CC) $(LDFLAGS) -o $@ $(PEEK_OBJS) $(LDLIBS)
+
+clean:
+	-rm -f $(POKE) $(PEEK) *.elf *.gdb *.o
+
+
--- a/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/peek.c
+++ b/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/peek.c
@ -0,0 +1,77 @@
+/*
+* peek utility - for those who remember the good old days!
+*
+*
+* Copyright (C) 2013 - 2016  Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person
+* obtaining a copy of this software and associated documentation
+* files (the "Software"), to deal in the Software without restriction,
+* including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software,
+* and to permit persons to whom the Software is furnished to do so,
+* subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in this
+* Software without prior written authorization from Xilinx.
+*
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/mman.h>
+#include <fcntl.h>
+
+void usage(char *prog)
+{
+	printf("usage: %s ADDR\n",prog);
+	printf("\n");
+	printf("ADDR may be specified as hex values\n");
+}
+
+
+int main(int argc, char *argv[])
+{
+	int fd;
+	void *ptr;
+	unsigned addr, page_addr, page_offset;
+	unsigned page_size=sysconf(_SC_PAGESIZE);
+
+	if(argc!=2) {
+		usage(argv[0]);
+		exit(-1);
+	}
+
+	fd=open("/dev/mem",O_RDONLY);
+	if(fd<1) {
+		perror(argv[0]);
+		exit(-1);
+	}
+
+	addr=strtoul(argv[1],NULL,0);
+	page_addr=(addr & ~(page_size-1));
+	page_offset=addr-page_addr;
+
+	ptr=mmap(NULL,page_size,PROT_READ,MAP_SHARED,fd,(addr & ~(page_size-1)));
+	if((int)ptr==-1) {
+		perror(argv[0]);
+		exit(-1);
+	}
+
+	printf("0x%08x\n",*((unsigned *)(ptr+page_offset)));
+	return 0;
+}
+
+
--- a/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c
+++ b/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c
@ -0,0 +1,77 @@
+/*
+* poke utility - for those who remember the good old days!
+*
+
+* Copyright (C) 2013 - 2016  Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person
+* obtaining a copy of this software and associated documentation
+* files (the "Software"), to deal in the Software without restriction,
+* including without limitation the rights to use, copy, modify, merge,
+* publish, distribute, sublicense, and/or sell copies of the Software,
+* and to permit persons to whom the Software is furnished to do so,
+* subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in this
+* Software without prior written authorization from Xilinx.
+*
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/mman.h>
+#include <fcntl.h>
+
+void usage(char *prog)
+{
+	printf("usage: %s ADDR VAL\n",prog);
+	printf("\n");
+	printf("ADDR and VAL may be specified as hex values\n");
+}
+
+int main(int argc, char *argv[])
+{
+	int fd;
+	void *ptr;
+	unsigned val;
+	unsigned addr, page_addr, page_offset;
+	unsigned page_size=sysconf(_SC_PAGESIZE);
+
+	fd=open("/dev/mem",O_RDWR);
+	if(fd<1) {
+		perror(argv[0]);
+		exit(-1);
+	}
+
+	if(argc!=3) {
+		usage(argv[0]);
+		exit(-1);
+	}
+
+	addr=strtoul(argv[1],NULL,0);
+	val=strtoul(argv[2],NULL,0);
+
+	page_addr=(addr & ~(page_size-1));
+	page_offset=addr-page_addr;
+
+	ptr=mmap(NULL,page_size,PROT_READ|PROT_WRITE,MAP_SHARED,fd,(addr & ~(page_size-1)));
+	if((int)ptr==-1) {
+		perror(argv[0]);
+		exit(-1);
+	}
+
+	*((unsigned *)(ptr+page_offset))=val;
+	return 0;
+}
--- a/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/peekpoke.bb
+++ b/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/peekpoke.bb
@ -0,0 +1,25 @@
+#
+# This is the peekpoke apllication recipe
+#
+#
+
+SUMMARY = "peekpoke application"
+SECTION = "PETALINUX/apps"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+SRC_URI = "file://peek.c \
+           file://poke.c \
+           file://Makefile \
+          "
+S = "${WORKDIR}"
+CFLAGS_prepend = "-I ${S}/include"
+do_compile() {
+        oe_runmake
+}
+do_install() {
+        install -d ${D}${bindir}
+        install -m 0755 ${S}/peek ${D}${bindir}
+        install -m 0755 ${S}/poke ${D}${bindir}
+
+}
+
--- a/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend
+++ b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend
@ -0,0 +1,17 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+SRC_URI += "file://system-user.dtsi"
+
+python () {
+    if d.getVar("CONFIG_DISABLE"):
+        d.setVarFlag("do_configure", "noexec", "1")
+}
+
+export PETALINUX
+do_configure_append () {
+	script="${PETALINUX}/etc/hsm/scripts/petalinux_hsm_bridge.tcl"
+	data=${PETALINUX}/etc/hsm/data/
+	eval xsct -sdx -nodisp ${script} -c ${WORKDIR}/config \
+	-hdf ${DT_FILES_PATH}/hardware_description.${HDF_EXT} -repo ${S} \
+	-data ${data} -sw ${DT_FILES_PATH} -o ${DT_FILES_PATH} -a "soc_mapping"
+}
--- a/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/openamp.dtsi
+++ b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/openamp.dtsi
@ -0,0 +1,74 @@
+/ {
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		rpu0vdev0vring0: rpu0vdev0vring0@3ed40000 {
+			no-map;
+			reg = <0x0 0x3ed40000 0x0 0x4000>;
+		};
+		rpu0vdev0vring1: rpu0vdev0vring1@3ed44000 {
+			no-map;
+			reg = <0x0 0x3ed44000 0x0 0x4000>;
+		};
+		rpu0vdev0buffer: rpu0vdev0buffer@3ed48000 {
+			no-map;
+			reg = <0x0 0x3ed48000 0x0 0x100000>;
+		};
+		rproc_0_reserved: rproc@3ed00000 {
+			no-map;
+			reg = <0x0 0x3ed00000 0x0 0x40000>;
+		};
+	};
+
+	zynqmp-rpu {
+		compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		core_conf = "split";
+		reg = <0x0 0xFF9A0000 0x0 0x10000>;
+		r5_0: r5@0 {
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			memory-region = <&rproc_0_reserved>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;
+			pnode-id = <0x7>;
+			mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;
+			mbox-names = "tx", "rx";
+			tcm_0_a: tcm_0@0 {
+				reg = <0x0 0xFFE00000 0x0 0x10000>;
+				pnode-id = <0xf>;
+			};
+			tcm_0_b: tcm_0@1 {
+				reg = <0x0 0xFFE20000 0x0 0x10000>;
+				pnode-id = <0x10>;
+			};
+		};
+	};
+
+
+	zynqmp_ipi1 {
+		compatible = "xlnx,zynqmp-ipi-mailbox";
+		interrupt-parent = <&gic>;
+		interrupts = <0 29 4>;
+		xlnx,ipi-id = <7>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* APU<->RPU0 IPI mailbox controller */
+		ipi_mailbox_rpu0: mailbox@ff990600 {
+			reg = <0xff990600 0x20>,
+			      <0xff990620 0x20>,
+			      <0xff9900c0 0x20>,
+			      <0xff9900e0 0x20>;
+			reg-names = "local_request_region",
+				    "local_response_region",
+				    "remote_request_region",
+				    "remote_response_region";
+			#mbox-cells = <1>;
+			xlnx,ipi-id = <1>;
+		};
+	};
+};
--- a/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi
+++ b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi
@ -0,0 +1,2 @@
+/ {
+};
--- a/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
+++ b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
@ -0,0 +1,54 @@
+/include/ "system-conf.dtsi"
+/ {
+	chosen {
+		bootargs = " earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/ram0 rw cpuidle.off=1";
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+
+&uart1 {
+    status = "okay";
+    /delete-property/ pinctrl-0;
+    /delete-property/ pinctrl-names;
+};
+
+&spi0{
+  is-decoded-cs = <0>;
+  num-cs = <1>;
+  status = "okay";
+  bus-num = <0>;
+  spidev@0x00 {
+    compatible = "spidev";
+    spi-max-frequency = <1000000>;
+    spi-cpol;
+    spi-cpha;
+    reg = <0>;
+    bus-num = <0>;
+  };
+};
+
+&i2c1 {
+    status = "okay";
+    clock-frequency = <400000>;
+    i2c-mux@74 { /* u34 */
+        compatible = "nxp,pca9548";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        reg = <0x74>;
+        i2c@3 { /* i2c mw 74 0 8 */
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <3>;
+            si570_2: clock-generator@5d {
+                #clock-cells = <0>;
+                compatible = "silabs,si570";
+                reg = <0x5d>;
+                temperature-stability = <50>;
+                factory-fout = <156250000>;
+                clock-frequency = <156250000>;
+            };
+        };
+    };
+};
+
--- a/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi.bak
+++ b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi.bak
@ -0,0 +1,10 @@
+/include/ "system-conf.dtsi"
+/ {
+};
+
+&uart1 {
+    status = "okay";
+    /delete-property/ pinctrl-0;
+    /delete-property/ pinctrl-names;
+};
+
--- a/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/xen-qemu.dtsi
+++ b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/xen-qemu.dtsi
@ -0,0 +1,16 @@
+/ {
+        cpus {
+                cpu@1 {
+                        //compatible = "disabled";
+                        device_type = "none";
+                };
+                cpu@2 {
+                        //compatible = "disabled";
+                        device_type = "none";
+                };
+                cpu@3 {
+                        //compatible = "disabled";
+                        device_type = "none";
+                };
+        };
+};
--- a/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/xen.dtsi
+++ b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/xen.dtsi
@ -0,0 +1,29 @@
+&smmu {
+	status = "okay";
+	mmu-masters = < &gem0 0x874
+			&gem1 0x875
+			&gem2 0x876
+			&gem3 0x877
+			&dwc3_0 0x860
+			&dwc3_1 0x861
+			&qspi 0x873
+			&lpd_dma_chan1 0x868
+			&lpd_dma_chan2 0x869
+			&lpd_dma_chan3 0x86a
+			&lpd_dma_chan4 0x86b
+			&lpd_dma_chan5 0x86c
+			&lpd_dma_chan6 0x86d
+			&lpd_dma_chan7 0x86e
+			&lpd_dma_chan8 0x86f
+			&fpd_dma_chan1 0x14e8
+			&fpd_dma_chan2 0x14e9
+			&fpd_dma_chan3 0x14ea
+			&fpd_dma_chan4 0x14eb
+			&fpd_dma_chan5 0x14ec
+			&fpd_dma_chan6 0x14ed
+			&fpd_dma_chan7 0x14ee
+			&fpd_dma_chan8 0x14ef
+			&sdhci0 0x870
+			&sdhci1 0x871
+			&nand0 0x872>;
+};
--- a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/0001-ubifs-distroboot-support.patch
+++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/0001-ubifs-distroboot-support.patch
@ -0,0 +1,28 @@
+From 357b3eebaa54be1ec8d14b306625eb73732ee5dc Mon Sep 17 00:00:00 2001
+From: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
+Date: Wed, 19 Aug 2020 05:29:40 -0600
+Subject: [UBOOT PATCH] ubifs: distroboot support
+
+Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
+---
+ include/configs/xilinx_zynqmp.h | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
+index d3f465a..dc231b8 100644
+--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
+@@ -154,7 +154,10 @@
+
+ #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=sf probe " #instance " 0 0 && " \
+-		       "sf read $scriptaddr $script_offset_f $script_size_f && " \
+		       "setenv mtdids 'nor0=nor0' && " \
+		       "setenv mtdparts 'mtdparts=nor0:16m(raw),-(boot)' && " \
+		       "mtdparts && " \
+		       "ubi part boot; ubifsmount ubi0:boot; ubifsload $scriptaddr boot.scr; && " \
+		       "echo QSPI: Trying to boot script at ${scriptaddr} && " \
+		       "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0"
+
+--
+2.7.4
--- a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/bsp.cfg
+++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/bsp.cfg
@ -0,0 +1,5 @@
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_SYS_TEXT_BASE=0x10080000
+CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
--- a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h
+++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h
@ -0,0 +1,2 @@
+#include <configs/xilinx_zynqmp.h>
+#include <configs/platform-auto.h>
--- a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend
+++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend
@ -0,0 +1,18 @@
+SRC_URI_append = " file://platform-top.h"
+SRC_URI += "file://bsp.cfg"
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+do_configure_append () {
+        if [ "${U_BOOT_AUTO_CONFIG}" = "1" ]; then
+                install ${WORKDIR}/platform-auto.h ${S}/include/configs/
+                install ${WORKDIR}/platform-top.h ${S}/include/configs/
+        fi
+}
+
+do_configure_append_microblaze () {
+        if [ "${U_BOOT_AUTO_CONFIG}" = "1" ]; then
+                install -d ${B}/source/board/xilinx/microblaze-generic/
+                install ${WORKDIR}/config.mk ${B}/source/board/xilinx/microblaze-generic/
+        fi
+}
--- a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr.bbappend
+++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr.bbappend
@ -0,0 +1,145 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+
+SRC_URI += "file://boot.cmd.default.initrd \
+	file://boot.cmd.default \
+	file://boot.cmd.default.ubifs"
+
+BOOTMODE = "default"
+BOOTFILE_EXT = ".initrd"
+#Make this value to "1" to skip appending base address to ddr offsets.
+SKIP_APPEND_BASEADDR = "0"
+
+RAMDISK_IMAGE_zynq = "rootfs.cpio.gz.u-boot"
+RAMDISK_IMAGE_zynqmp = "rootfs.cpio.gz.u-boot"
+RAMDISK_IMAGE_versal = "rootfs.cpio.gz.u-boot"
+
+KERNEL_IMAGE_zynq = "uImage"
+KERNEL_IMAGE_zynqmp = "Image"
+KERNEL_IMAGE_versal = "Image"
+
+KERNEL_BOOTCMD_zynq = "bootm"
+KERNEL_BOOTCMD_zynqmp = "booti"
+KERNEL_BOOTCMD_versal = "booti"
+
+DEVICETREE_ADDRESS_zynq = "${@append_baseaddr(d,"0x100000")}"
+DEVICETREE_ADDRESS_zynqmp = "${@append_baseaddr(d,"0x100000")}"
+DEVICETREE_ADDRESS_versal = "${@append_baseaddr(d,"0x1000")}"
+
+KERNEL_LOAD_ADDRESS_zynq = "${@append_baseaddr(d,"0x200000")}"
+KERNEL_LOAD_ADDRESS_zynqmp = "${@append_baseaddr(d,"0x200000")}"
+KERNEL_LOAD_ADDRESS_versal = "${@append_baseaddr(d,"0x80000")}"
+
+RAMDISK_IMAGE_ADDRESS_zynq = "${@append_baseaddr(d,"0x4000000")}"
+RAMDISK_IMAGE_ADDRESS_zynqmp = "${@append_baseaddr(d,"0x4000000")}"
+RAMDISK_IMAGE_ADDRESS_versal = "${@append_baseaddr(d,"0x4000000")}"
+
+## Below offsets and sizes are based on 32MB QSPI Memory for zynq
+## For zynq
+## Load boot.scr at 0xFC0000 -> 15MB of QSPI/NAND Memory
+QSPI_KERNEL_OFFSET_zynq = "0x1000000"
+QSPI_RAMDISK_OFFSET_zynq = "0x1580000"
+
+NAND_KERNEL_OFFSET_zynq = "0x1000000"
+NAND_RAMDISK_OFFSET_zynq = "0x4600000"
+
+QSPI_KERNEL_SIZE_zynq = "0x500000"
+QSPI_RAMDISK_SIZE_zynq = "0xA00000"
+
+NAND_KERNEL_SIZE = "0x3200000"
+NAND_RAMDISK_SIZE = "0x3200000"
+
+## Below offsets and sizes are based on 128MB QSPI Memory for zynqmp/versal
+## For zynqMP
+## Load boot.scr at 0x3E80000 -> 62MB of QSPI/NAND Memory
+QSPI_KERNEL_OFFSET = "0xF00000"
+QSPI_KERNEL_OFFSET_zynqmpdr = "0x3F00000"
+QSPI_RAMDISK_OFFSET = "0x4000000"
+QSPI_RAMDISK_OFFSET_zynqmpdr = "0x5D00000"
+
+NAND_KERNEL_OFFSET_zynqmp = "0x4100000"
+NAND_RAMDISK_OFFSET_zynqmp = "0x7800000"
+
+QSPI_KERNEL_SIZE_zynqmp = "0x1D00000"
+QSPI_RAMDISK_SIZE = "0x4000000"
+QSPI_RAMDISK_SIZE_zynqmpdr = "0x1D00000"
+
+## For versal
+## Load boot.scr at 0x7F80000 -> 127MB of QSPI/NAND Memory
+QSPI_KERNEL_OFFSET_versal = "0xF00000"
+QSPI_RAMDISK_OFFSET_versal = "0x2E00000"
+
+NAND_KERNEL_OFFSET_versal = "0x4100000"
+NAND_RAMDISK_OFFSET_versal = "0x8200000"
+
+QSPI_KERNEL_SIZE_versal = "0x1D00000"
+QSPI_RAMDISK_SIZE_versal = "0x4000000"
+
+QSPI_KERNEL_IMAGE_zynq = "image.ub"
+QSPI_KERNEL_IMAGE_zynqmp = "image.ub"
+QSPI_KERNEL_IMAGE_versal = "image.ub"
+
+NAND_KERNEL_IMAGE = "image.ub"
+
+FIT_IMAGE_LOAD_ADDRESS = "${@append_baseaddr(d,"0x10000000")}"
+
+QSPI_FIT_IMAGE_LOAD_ADDRESS = "${@append_baseaddr(d,"0x10000000")}"
+QSPI_FIT_IMAGE_SIZE = "0x6400000"
+QSPI_FIT_IMAGE_SIZE_zynqmpdr = "0x3F00000"
+QSPI_FIT_IMAGE_SIZE_zynq = "0xF00000"
+
+NAND_FIT_IMAGE_LOAD_ADDRESS = "${@append_baseaddr(d,"0x10000000")}"
+NAND_FIT_IMAGE_SIZE = "0x6400000"
+
+FIT_IMAGE = "image.ub"
+
+python () {
+    baseaddr = d.getVar('DDR_BASEADDR') or "0x0"
+    if baseaddr == "0x0":
+        d.setVar('PRE_BOOTENV','')
+    else:
+        soc_family = d.getVar('SOC_FAMILY') or ""
+        if soc_family == "zynqmp":
+            fdt_high = "0x10000000"
+        elif soc_family == "zynq":
+            fdt_high = "0x20000000"
+        elif soc_family == "versal":
+            fdt_high = "0x70000000"
+
+        if fdt_high:
+            basefdt_high = append_baseaddr(d,fdt_high)
+            bootenv = "setenv fdt_high " + basefdt_high
+            d.setVar('PRE_BOOTENV',bootenv)
+}
+
+def append_baseaddr(d,offset):
+    skip_append = d.getVar('SKIP_APPEND_BASEADDR') or ""
+    if skip_append == "1":
+        return offset
+    import subprocess
+    baseaddr = d.getVar('DDR_BASEADDR') or "0x0"
+    subcmd = "$((%s+%s));" % (baseaddr,offset)
+    cmd = "printf '0x%08x' " + str(subcmd)
+    output = subprocess.check_output(cmd, shell=True).decode("utf-8")
+    return output
+
+do_compile_prepend() {
+	sed -e 's/@@QSPI_KERNEL_OFFSET@@/${QSPI_KERNEL_OFFSET}/' \
+	    -e 's/@@NAND_KERNEL_OFFSET@@/${NAND_KERNEL_OFFSET}/' \
+	    -e 's/@@QSPI_KERNEL_SIZE@@/${QSPI_KERNEL_SIZE}/' \
+	    -e 's/@@NAND_KERNEL_SIZE@@/${NAND_KERNEL_SIZE}/' \
+	    -e 's/@@QSPI_RAMDISK_OFFSET@@/${QSPI_RAMDISK_OFFSET}/' \
+	    -e 's/@@NAND_RAMDISK_OFFSET@@/${NAND_RAMDISK_OFFSET}/' \
+	    -e 's/@@QSPI_RAMDISK_SIZE@@/${QSPI_RAMDISK_SIZE}/' \
+	    -e 's/@@NAND_RAMDISK_SIZE@@/${NAND_RAMDISK_SIZE}/' \
+	    -e 's/@@KERNEL_IMAGE@@/${KERNEL_IMAGE}/' \
+	    -e 's/@@QSPI_KERNEL_IMAGE@@/${QSPI_KERNEL_IMAGE}/' \
+	    -e 's/@@NAND_KERNEL_IMAGE@@/${NAND_KERNEL_IMAGE}/' \
+	    -e 's/@@QSPI_FIT_IMAGE_LOAD_ADDRESS@@/${QSPI_FIT_IMAGE_LOAD_ADDRESS}/' \
+	    -e 's/@@FIT_IMAGE_LOAD_ADDRESS@@/${FIT_IMAGE_LOAD_ADDRESS}/' \
+	    -e 's/@@QSPI_FIT_IMAGE_SIZE@@/${QSPI_FIT_IMAGE_SIZE}/' \
+	    -e 's/@@NAND_FIT_IMAGE_LOAD_ADDRESS@@/${NAND_FIT_IMAGE_LOAD_ADDRESS}/' \
+	    -e 's/@@NAND_FIT_IMAGE_SIZE@@/${NAND_FIT_IMAGE_SIZE}/' \
+	    -e 's/@@FIT_IMAGE@@/${FIT_IMAGE}/' \
+	    -e 's/@@PRE_BOOTENV@@/${PRE_BOOTENV}/' \
+	    "${WORKDIR}/boot.cmd.${BOOTMODE}${BOOTFILE_EXT}" > "${WORKDIR}/boot.cmd.${BOOTMODE}.${SOC_FAMILY}"
+}
--- a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.default
+++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.default
@ -0,0 +1,52 @@
+# This is a boot script for U-Boot
+# Generate boot.scr:
+# mkimage -c none -A arm -T script -d boot.cmd.default boot.scr
+#
+################
+## Please change the kernel_offset and kernel_size if the kernel image size more than
+## the 100MB and BOOT.BIN size more than the 30MB
+## kernel_offset --> is the address of qspi which you want load the kernel image
+## kernel_size --> size of the kernel image in hex
+###############
+fdt_addr=0x1000
+imageub_addr=0x10000000
+kernel_addr=0x80000
+kernel_offset=0x1E00200
+kernel_size=0x7800000
+kernel_type=image.ub
+
+for boot_target in ${boot_targets};
+do
+	if test "${boot_target}" = "jtag" ; then
+		booti ${kernel_addr} - ${fdt_addr};
+		exit;
+	fi
+	if test "${boot_target}" = "mmc0" || test "${boot_target}" = "mmc1" ; then
+		if test -e ${devtype} ${devnum}:${distro_bootpart} /image.ub; then
+			fatload ${devtype} ${devnum}:${distro_bootpart} ${imageub_addr} image.ub;
+			bootm ${imageub_addr};
+			exit;
+		fi
+		if test -e ${devtype} ${devnum}:${distro_bootpart} /Image; then
+			fatload ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr} Image;
+			booti ${kernel_addr} - ${fdt_addr};
+			exit;
+		fi
+		booti ${kernel_addr} - ${fdt_addr};
+		exit;
+	fi
+	if test "${boot_target}" = "xspi0"; then
+		sf probe 0 0 0;
+		if test "${kernel_type}" = "image.ub"; then
+			sf read ${imageub_addr} ${kernel_offset} ${kernel_size};
+			bootm ${imageub_addr};
+			exit;
+		fi
+		if test "${kernel_type}" = "Image"; then
+			sf read ${kernel_addr} ${kernel_offset} ${kernel_size};
+			booti ${kernel_addr} - ${fdt_addr};
+			exit;
+		fi
+		exit;
+	fi
+done
--- a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.default.initrd
+++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.default.initrd
@ -0,0 +1,63 @@
+# This is a boot script for U-Boot
+# Generate boot.scr:
+# mkimage -c none -A arm -T script -d boot.cmd.default boot.scr
+#
+################
+@@PRE_BOOTENV@@
+
+for boot_target in ${boot_targets};
+do
+	if test "${boot_target}" = "jtag" ; then
+		@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@
+		exit;
+	fi
+	if test "${boot_target}" = "mmc0" || test "${boot_target}" = "mmc1" ; then
+		if test -e ${devtype} ${devnum}:${distro_bootpart} /@@FIT_IMAGE@@; then
+			fatload ${devtype} ${devnum}:${distro_bootpart} @@FIT_IMAGE_LOAD_ADDRESS@@ @@FIT_IMAGE@@;
+			bootm @@FIT_IMAGE_LOAD_ADDRESS@@;
+			exit;
+                fi
+		if test -e ${devtype} ${devnum}:${distro_bootpart} /@@KERNEL_IMAGE@@; then
+			fatload ${devtype} ${devnum}:${distro_bootpart} @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGE@@;;
+		fi
+		if test -e ${devtype} ${devnum}:${distro_bootpart} /system.dtb; then
+			fatload ${devtype} ${devnum}:${distro_bootpart} @@DEVICETREE_ADDRESS@@ system.dtb;
+		fi
+		if test -e ${devtype} ${devnum}:${distro_bootpart} /@@RAMDISK_IMAGE@@; then
+			fatload ${devtype} ${devnum}:${distro_bootpart} @@RAMDISK_IMAGE_ADDRESS@@ @@RAMDISK_IMAGE@@;
+			@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@
+			exit;
+		fi
+		@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@
+		exit;
+	fi
+	if test "${boot_target}" = "xspi0" || test "${boot_target}" = "qspi" || test "${boot_target}" = "qspi0"; then
+		sf probe 0 0 0;
+		if test "@@QSPI_KERNEL_IMAGE@@" = "@@FIT_IMAGE@@"; then
+			sf read @@QSPI_FIT_IMAGE_LOAD_ADDRESS@@ @@QSPI_KERNEL_OFFSET@@ @@QSPI_FIT_IMAGE_SIZE@@;
+			bootm @@QSPI_FIT_IMAGE_LOAD_ADDRESS@@;
+			exit;
+		fi
+		if test "@@QSPI_KERNEL_IMAGE@@" = "@@KERNEL_IMAGE@@"; then
+			sf read @@KERNEL_LOAD_ADDRESS@@ @@QSPI_KERNEL_OFFSET@@ @@QSPI_KERNEL_SIZE@@;
+			sf read @@RAMDISK_IMAGE_ADDRESS@@ @@QSPI_RAMDISK_OFFSET@@ @@QSPI_RAMDISK_SIZE@@
+			@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@
+			exit;
+		fi
+		exit;
+	fi
+	if test "${boot_target}" = "nand" || test "${boot_target}" = "nand0"; then
+		nand info
+		if test "@@NAND_KERNEL_IMAGE@@" = "@@FIT_IMAGE@@"; then
+			nand read @@NAND_FIT_IMAGE_LOAD_ADDRESS@@ @@NAND_KERNEL_OFFSET@@ @@NAND_FIT_IMAGE_SIZE@@;
+			bootm @@NAND_FIT_IMAGE_LOAD_ADDRESS@@;
+			exit;
+		fi
+		if test "@@NAND_KERNEL_IMAGE@@" = "@@KERNEL_IMAGE@@"; then
+			nand read @@KERNEL_LOAD_ADDRESS@@ @@NAND_KERNEL_OFFSET@@ @@NAND_KERNEL_SIZE@@;
+			nand read @@RAMDISK_IMAGE_ADDRESS@@ @@NAND_RAMDISK_OFFSET@@  @@NAND_RAMDISK_SIZE@@;
+			@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@
+			exit;
+		fi
+	fi
+done
--- a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.default.ubifs
+++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.default.ubifs
@ -0,0 +1,55 @@
+# This is a boot script for U-Boot
+# Generate boot.scr:
+# mkimage -c none -A arm -T script -d boot.cmd.default boot.scr
+#
+################
+@@PRE_BOOTENV@@
+
+for boot_target in ${boot_targets};
+do
+	if test "${boot_target}" = "xspi0" || test "${boot_target}" = "qspi" || test "${boot_target}" = "qspi0"; then
+		ubifsls @@FIT_IMAGE@@
+		if test $? = 0; then
+			ubifsload @@QSPI_FIT_IMAGE_LOAD_ADDRESS@@ @@FIT_IMAGE@@;
+			bootm @@QSPI_FIT_IMAGE_LOAD_ADDRESS@@;
+			exit;
+		fi
+		ubifsls @@KERNEL_IMAGE@@
+		if test $? = 0; then
+			ubifsload @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGE@@;
+		fi
+		ubifsls system.dtb
+		if test $? = 0; then
+			ubifsload @@DEVICETREE_ADDRESS@@ system.dtb
+		fi
+		ubifsls @@RAMDISK_IMAGE@@
+		if test $? = 0; then
+			ubifsload @@RAMDISK_IMAGE_ADDRESS@@ @@RAMDISK_IMAGE@@
+			@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@
+			exit;
+		fi
+		@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@
+		exit;
+	fi
+	if test "${boot_target}" = "mmc0" || test "${boot_target}" = "mmc1" ; then
+		run bootcmd_${boot_target};
+		if test -e ${devtype} ${devnum}:${distro_bootpart} /@@FIT_IMAGE@@; then
+			ext4load ${devtype} ${devnum}:${distro_bootpart} @@FIT_IMAGE_LOAD_ADDRESS@@ @@FIT_IMAGE@@;
+			bootm @@FIT_IMAGE_LOAD_ADDRESS@@;
+			exit;
+		fi
+		if test -e ${devtype} ${devnum}:${distro_bootpart} /@@KERNEL_IMAGE@@; then
+			ext4load ${devtype} ${devnum}:${distro_bootpart} @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGE@@;
+		fi
+		if test -e ${devtype} ${devnum}:${distro_bootpart} /system.dtb; then
+			ext4load ${devtype} ${devnum}:${distro_bootpart} @@DEVICETREE_ADDRESS@@ system.dtb;
+		fi
+		if test -e ${devtype} ${devnum}:${distro_bootpart} /@@RAMDISK_IMAGE@@; then
+			ext4load ${devtype} ${devnum}:${distro_bootpart} @@RAMDISK_IMAGE_ADDRESS@@ @@RAMDISK_IMAGE@@;
+			@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@
+			exit;
+		fi
+		@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@
+		exit;
+	fi
+done
--- a/Petalinux/project-spec/meta-user/recipes-core/images/petalinux-image-full.bbappend
+++ b/Petalinux/project-spec/meta-user/recipes-core/images/petalinux-image-full.bbappend
@ -0,0 +1,7 @@
+#Note: Mention Each package in individual line
+#      cascaded representation with line breaks are not valid in this file.
+IMAGE_INSTALL_append = " peekpoke"
+IMAGE_INSTALL_append = " gpio-demo"
+
+IMAGE_INSTALL_append = " ethtool"
+IMAGE_INSTALL_append = " iperf3"
--- a/Petalinux/project-spec/meta-user/recipes-core/init-ifupdown/files/myinterfaces
+++ b/Petalinux/project-spec/meta-user/recipes-core/init-ifupdown/files/myinterfaces
@ -0,0 +1,15 @@
+# myinterfaces content
+  
+# /etc/network/interfaces -- configuration file for ifup(8), ifdown(8)
+  
+# The loopback interface
+auto lo
+iface lo inet loopback
+  
+# Wired or wireless interfaces
+auto eth0
+iface eth0 inet dhcp
+  
+# Add auto config for eth1
+auto eth1
+iface eth1 inet dhcp
--- a/Petalinux/project-spec/meta-user/recipes-core/init-ifupdown/init-ifupdown_%.bbappend
+++ b/Petalinux/project-spec/meta-user/recipes-core/init-ifupdown/init-ifupdown_%.bbappend
@ -0,0 +1,12 @@
+# init-ifupdown_%.bbappend content
+  
+SRC_URI += " \
+        file://myinterfaces \
+        "
+  
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+  
+# Overwrite interface file with myinterface file in rootfs
+do_install_append() {
+     install -m 0644 ${WORKDIR}/myinterfaces ${D}${sysconfdir}/network/interfaces
+}
--- a/Petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg
+++ b/Petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg
@ -0,0 +1,3 @@
+CONFIG_XILINX_PHY=y
+# CONFIG_XILINX_DMA is not set
+
--- a/Petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend
+++ b/Petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend
@ -0,0 +1,3 @@
+SRC_URI += "file://bsp.cfg"
+KERNEL_FEATURES_append = " bsp.cfg"
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
--- a/images/BOOT.BIN
+++ b/images/BOOT.BIN
--- a/images/boot.scr
+++ b/images/boot.scr
--- a/images/image.ub
+++ b/images/image.ub
--- a/images/system.dtb
+++ b/images/system.dtb
--- a/results/Results_MTU_9000.png
+++ b/results/Results_MTU_9000.png
--- a/src/constraints/README
+++ b/src/constraints/README
@ -0,0 +1 @@
+Use this directory to track your constraint files
--- a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/gui_handlers.wdf
+++ b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/gui_handlers.wdf
@ -1,46 +1,49 @@
 version:1
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-eof:1898407456
+eof:4213296809
--- a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/java_command_handlers.wdf
+++ b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/java_command_handlers.wdf
@ -1,22 +1,22 @@
 version:1
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-70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:32:00:00
-70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:32:00:00
-70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:33:00:00
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+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:34:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766572736264657369676e:31:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:31:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:31:00:00
-70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:32:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:33:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b72746c616e616c79736973:31:00:00
-eof:503755933
+eof:1813883363
--- a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/project.wpc
+++ b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/project.wpc
@ -1,3 +1,3 @@
 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:4
+6d6f64655f636f756e7465727c4755494d6f6465:6
 eof:
--- a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/synthesis.wdf
+++ b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/synthesis.wdf
@ -1,7 +1,7 @@
 version:1
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:72746c5f31:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78637a753765762d66667663313135362d322d65:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:706c5f6574685f3130675f77726170706572:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
@ -10,7 +10,7 @@ version:1
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:5b7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
@ -36,4 +36,7 @@ version:1
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-eof:3126106825
+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30373a333073:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:343432312e3735304d42:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:333237372e3631374d42:00:00
+eof:3543237790
--- a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/webtalk_pa.xml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/webtalk_pa.xml
@ -3,7 +3,7 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Fri Oct 20 16:41:35 2023">
+<application name="pa" timeStamp="Fri Oct 20 19:58:33 2023">
 <section name="Project Information" visible="false">
 <property name="ProjectID" value="e44f545a56b248f4976b49478b84eb20" type="ProjectID"/>
 <property name="ProjectIteration" value="1" type="ProjectIteration"/>
@ -17,77 +17,80 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
 </item>
 <item name="Java Command Handlers">
-<property name="AutoConnectTarget" value="7" type="JavaHandler"/>
-<property name="CustomizeRSBBlock" value="6" type="JavaHandler"/>
-<property name="ExitApp" value="4" type="JavaHandler"/>
+<property name="AutoConnectTarget" value="8" type="JavaHandler"/>
+<property name="CustomizeRSBBlock" value="14" type="JavaHandler"/>
+<property name="ExitApp" value="5" type="JavaHandler"/>
 <property name="LaunchOpenTarget" value="2" type="JavaHandler"/>
-<property name="LaunchProgramFpga" value="7" type="JavaHandler"/>
-<property name="NewExportHardware" value="2" type="JavaHandler"/>
-<property name="OpenHardwareManager" value="19" type="JavaHandler"/>
+<property name="LaunchProgramFpga" value="8" type="JavaHandler"/>
+<property name="NewExportHardware" value="3" type="JavaHandler"/>
+<property name="OpenHardwareManager" value="22" type="JavaHandler"/>
 <property name="OpenProject" value="1" type="JavaHandler"/>
-<property name="OpenRecentTarget" value="14" type="JavaHandler"/>
-<property name="ProgramDevice" value="9" type="JavaHandler"/>
+<property name="OpenRecentTarget" value="15" type="JavaHandler"/>
+<property name="ProgramDevice" value="10" type="JavaHandler"/>
 <property name="RefreshServer" value="2" type="JavaHandler"/>
 <property name="RefreshTarget" value="1" type="JavaHandler"/>
-<property name="RunBitgen" value="2" type="JavaHandler"/>
-<property name="RunImplementation" value="2" type="JavaHandler"/>
-<property name="RunSynthesis" value="3" type="JavaHandler"/>
+<property name="RunBitgen" value="3" type="JavaHandler"/>
+<property name="RunImplementation" value="3" type="JavaHandler"/>
+<property name="RunSynthesis" value="4" type="JavaHandler"/>
 <property name="SaveRSBDesign" value="1" type="JavaHandler"/>
 <property name="ShowView" value="1" type="JavaHandler"/>
 <property name="ToolsSettings" value="1" type="JavaHandler"/>
-<property name="ViewTaskImplementation" value="2" type="JavaHandler"/>
+<property name="ViewTaskImplementation" value="3" type="JavaHandler"/>
 <property name="ViewTaskRTLAnalysis" value="1" type="JavaHandler"/>
 </item>
 <item name="Gui Handlers">
-<property name="BaseDialog_OK" value="10" type="GuiHandlerData"/>
+<property name="BaseDialog_OK" value="16" type="GuiHandlerData"/>
 <property name="CmdMsgDialog_OK" value="15" type="GuiHandlerData"/>
 <property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="5" type="GuiHandlerData"/>
-<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="3" type="GuiHandlerData"/>
-<property name="ExportPlatformWizard_FIXED_POST_IMPL" value="2" type="GuiHandlerData"/>
-<property name="ExportPlatformWizard_OUTPUT_XSA_NAME" value="1" type="GuiHandlerData"/>
-<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="22" type="GuiHandlerData"/>
-<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="40" type="GuiHandlerData"/>
+<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="4" type="GuiHandlerData"/>
+<property name="ExportPlatformWizard_FIXED_POST_IMPL" value="3" type="GuiHandlerData"/>
+<property name="ExportPlatformWizard_OUTPUT_XSA_NAME" value="2" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="25" type="GuiHandlerData"/>
+<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="43" type="GuiHandlerData"/>
 <property name="HardwareTreePanel_HARDWARE_TREE_TABLE" value="8" type="GuiHandlerData"/>
-<property name="MainMenuMgr_CHECKPOINT" value="3" type="GuiHandlerData"/>
+<property name="MainMenuMgr_CHECKPOINT" value="6" type="GuiHandlerData"/>
 <property name="MainMenuMgr_CONSTRAINTS" value="2" type="GuiHandlerData"/>
-<property name="MainMenuMgr_EXPORT" value="4" type="GuiHandlerData"/>
-<property name="MainMenuMgr_FILE" value="8" type="GuiHandlerData"/>
-<property name="MainMenuMgr_IMPORT" value="2" type="GuiHandlerData"/>
-<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
-<property name="MainMenuMgr_PROJECT" value="4" type="GuiHandlerData"/>
-<property name="MainMenuMgr_TEXT_EDITOR" value="5" type="GuiHandlerData"/>
-<property name="MainToolbarMgr_RUN" value="3" type="GuiHandlerData"/>
-<property name="PACommandNames_AUTO_CONNECT_TARGET" value="7" type="GuiHandlerData"/>
-<property name="PACommandNames_EXPORT_HARDWARE" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_EXPORT" value="6" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FILE" value="10" type="GuiHandlerData"/>
+<property name="MainMenuMgr_IMPORT" value="5" type="GuiHandlerData"/>
+<property name="MainMenuMgr_IP" value="5" type="GuiHandlerData"/>
+<property name="MainMenuMgr_PROJECT" value="5" type="GuiHandlerData"/>
+<property name="MainMenuMgr_TEXT_EDITOR" value="8" type="GuiHandlerData"/>
+<property name="MainToolbarMgr_RUN" value="4" type="GuiHandlerData"/>
+<property name="PACommandNames_AUTO_CONNECT_TARGET" value="8" type="GuiHandlerData"/>
+<property name="PACommandNames_EXPORT_HARDWARE" value="3" type="GuiHandlerData"/>
+<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
 <property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
 <property name="PACommandNames_OPEN_TARGET_WIZARD" value="2" type="GuiHandlerData"/>
 <property name="PACommandNames_REFRESH_SERVER" value="2" type="GuiHandlerData"/>
 <property name="PACommandNames_REFRESH_TARGET" value="1" type="GuiHandlerData"/>
-<property name="PACommandNames_RUN_BITGEN" value="2" type="GuiHandlerData"/>
-<property name="PACommandNames_RUN_SYNTHESIS" value="3" type="GuiHandlerData"/>
+<property name="PACommandNames_RUN_BITGEN" value="3" type="GuiHandlerData"/>
+<property name="PACommandNames_RUN_IMPLEMENTATION" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_RUN_SYNTHESIS" value="4" type="GuiHandlerData"/>
 <property name="PAViews_DASHBOARD" value="1" type="GuiHandlerData"/>
 <property name="PAViews_MIG" value="2" type="GuiHandlerData"/>
-<property name="PAViews_PROJECT_SUMMARY" value="4" type="GuiHandlerData"/>
-<property name="PSSPanelClockingPage_PLL_OPTIONS" value="1" type="GuiHandlerData"/>
-<property name="PSSPanelClockingPage_TABBED_PANE" value="6" type="GuiHandlerData"/>
+<property name="PAViews_PROJECT_SUMMARY" value="5" type="GuiHandlerData"/>
+<property name="PSSPanelClockingPage_PLL_OPTIONS" value="2" type="GuiHandlerData"/>
+<property name="PSSPanelClockingPage_TABBED_PANE" value="11" type="GuiHandlerData"/>
 <property name="PSSPanelDDRPage_OTHER_OPTIONS" value="2" type="GuiHandlerData"/>
 <property name="PSSPanelMainPage_SWITCH_TO_ADVANCED_MODE" value="1" type="GuiHandlerData"/>
-<property name="PSSTreeTablePanelBuilder_ADV_CLK_TREE" value="47" type="GuiHandlerData"/>
-<property name="PSSTreeTablePanelBuilder_CLK_TREE" value="7" type="GuiHandlerData"/>
+<property name="PSSTreeTablePanelBuilder_ADV_CLK_TREE" value="94" type="GuiHandlerData"/>
+<property name="PSSTreeTablePanelBuilder_CLK_TREE" value="9" type="GuiHandlerData"/>
 <property name="PSSTreeTablePanelBuilder_GENERAL_TREE" value="12" type="GuiHandlerData"/>
 <property name="PSSTreeTablePanelBuilder_MIO_TREE" value="8" type="GuiHandlerData"/>
-<property name="ProgramFpgaDialog_PROGRAM" value="7" type="GuiHandlerData"/>
+<property name="ProgramFpgaDialog_PROGRAM" value="8" type="GuiHandlerData"/>
 <property name="RunGadget_SHOW_ERROR_AND_CRITICAL_WARNING_MESSAGES" value="1" type="GuiHandlerData"/>
+<property name="SaveProjectUtils_SAVE" value="1" type="GuiHandlerData"/>
 <property name="SettingsDialog_PROJECT_TREE" value="6" type="GuiHandlerData"/>
-<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="2" type="GuiHandlerData"/>
+<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="3" type="GuiHandlerData"/>
 <property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
 <property name="TclConsoleView_COPY" value="1" type="GuiHandlerData"/>
 <property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="5" type="GuiHandlerData"/>
 </item>
 <item name="Other">
-<property name="GuiMode" value="50" type="GuiMode"/>
+<property name="GuiMode" value="53" type="GuiMode"/>
 <property name="BatchMode" value="0" type="BatchMode"/>
-<property name="TclMode" value="32" type="TclMode"/>
+<property name="TclMode" value="34" type="TclMode"/>
 </item>
 </section>
 </application>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hdl/pl_eth_10g_wrapper.v
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hdl/pl_eth_10g_wrapper.v
@ -1,7 +1,7 @@
 //Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 //--------------------------------------------------------------------------------
 //Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
-//Date        : Fri Oct 20 12:44:41 2023
+//Date        : Fri Oct 20 19:29:21 2023
 //Host        : DESKTOP-5FH9OH3 running 64-bit major release  (build 9200)
 //Command     : generate_target pl_eth_10g_wrapper.bd
 //Design      : pl_eth_10g_wrapper
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g.hwh
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g.hwh
@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Oct 20 12:45:21 2023" VIVADOVERSION="2020.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Oct 20 19:30:01 2023" VIVADOVERSION="2020.2">

  <SYSTEMINFO ARCH="zynquplus" DEVICE="xczu7ev" NAME="pl_eth_10g" PACKAGE="ffvc1156" SPEEDGRADE="-2"/>

@ -9,16 +9,6 @@
        <CONNECTION INSTANCE="sfp_tx_dis" PORT="dout"/>
      </CONNECTIONS>
    </PORT>
-    <PORT DIR="I" NAME="gt_rx_gt_port_0_n" SIGIS="undef" SIGNAME="xxv_ethernet_0_gt_rxn_in_0">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="xxv_ethernet_0" PORT="gt_rxn_in_0"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" NAME="gt_rx_gt_port_0_p" SIGIS="undef" SIGNAME="xxv_ethernet_0_gt_rxp_in_0">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="xxv_ethernet_0" PORT="gt_rxp_in_0"/>
-      </CONNECTIONS>
-    </PORT>
    <PORT DIR="O" NAME="gt_tx_gt_port_0_n" SIGIS="undef" SIGNAME="xxv_ethernet_0_gt_txn_out_0">
      <CONNECTIONS>
        <CONNECTION INSTANCE="xxv_ethernet_0" PORT="gt_txn_out_0"/>
@ -29,6 +19,16 @@
        <CONNECTION INSTANCE="xxv_ethernet_0" PORT="gt_txp_out_0"/>
      </CONNECTIONS>
    </PORT>
+    <PORT DIR="I" NAME="gt_rx_gt_port_0_n" SIGIS="undef" SIGNAME="xxv_ethernet_0_gt_rxn_in_0">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="xxv_ethernet_0" PORT="gt_rxn_in_0"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" NAME="gt_rx_gt_port_0_p" SIGIS="undef" SIGNAME="xxv_ethernet_0_gt_rxp_in_0">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="xxv_ethernet_0" PORT="gt_rxp_in_0"/>
+      </CONNECTIONS>
+    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="I" NAME="gt_ref_clk_clk_n" SIGIS="clk" SIGNAME="xxv_ethernet_0_gt_refclk_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="xxv_ethernet_0" PORT="gt_refclk_n"/>
@ -911,7 +911,7 @@
        <PARAMETER NAME="C_INCLUDE_MM2S_DRE" VALUE="1"/>
        <PARAMETER NAME="C_INCLUDE_S2MM" VALUE="1"/>
        <PARAMETER NAME="C_INCLUDE_S2MM_SF" VALUE="1"/>
-        <PARAMETER NAME="C_S2MM_BURST_SIZE" VALUE="8"/>
+        <PARAMETER NAME="C_S2MM_BURST_SIZE" VALUE="16"/>
        <PARAMETER NAME="C_M_AXI_S2MM_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_S2MM_DATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="C_S_AXIS_S2MM_TDATA_WIDTH" VALUE="64"/>
@ -940,7 +940,7 @@
        <PARAMETER NAME="c_s_axis_s2mm_tdata_width" VALUE="64"/>
        <PARAMETER NAME="c_include_s2mm_dre" VALUE="1"/>
        <PARAMETER NAME="c_include_s2mm_sf" VALUE="1"/>
-        <PARAMETER NAME="c_s2mm_burst_size" VALUE="8"/>
+        <PARAMETER NAME="c_s2mm_burst_size" VALUE="16"/>
        <PARAMETER NAME="c_addr_width" VALUE="32"/>
        <PARAMETER NAME="c_single_interface" VALUE="0"/>
        <PARAMETER NAME="c_increase_throughput" VALUE="0"/>
@ -1603,7 +1603,7 @@
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
-          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="8"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
          <PARAMETER NAME="PHASE" VALUE="0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
@ -10102,155 +10102,6 @@
            <CONNECTION INSTANCE="zups_zynq_ultra_ps_e_0" PORT="saxigp2_rready"/>
          </CONNECTIONS>
        </PORT>
-        <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awaddr">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awaddr"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" LEFT="7" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awlen">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awlen"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awsize">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awsize"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awburst">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awburst"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
-        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awcache">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awcache"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awprot">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awprot"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
-        <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awvalid">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awvalid"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awready">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awready"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wdata">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_wdata"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wstrb">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_wstrb"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wlast">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_wlast"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wvalid">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_wvalid"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wready">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_wready"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_bresp">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_bresp"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_bvalid">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_bvalid"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_bready">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_bready"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_araddr">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_araddr"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arlen">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arlen"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arsize">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arsize"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arburst">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arburst"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
-        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arcache">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arcache"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arprot">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arprot"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
-        <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arvalid">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arvalid"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arready">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arready"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rdata">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_rdata"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rresp">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_rresp"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rlast">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_rlast"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rvalid">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_rvalid"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rready">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_rready"/>
-          </CONNECTIONS>
-        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S02_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awaddr"/>
@ -10400,6 +10251,155 @@
            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
          </CONNECTIONS>
        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
+        <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
+        <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_sg_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_sg_rready"/>
+          </CONNECTIONS>
+        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi_dma_0_M_AXI_SG" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
@ -12915,7 +12915,7 @@
        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1" VALUE="1"/>
-        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0" VALUE="12"/>
+        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0" VALUE="5"/>
        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0" VALUE="7"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1" VALUE="1"/>
@ -13082,7 +13082,7 @@
        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ" VALUE="250"/>
-        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ" VALUE="124.998749"/>
+        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ" VALUE="299.997009"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ" VALUE="187.498123"/>
        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
@ -13109,7 +13109,7 @@
        <PARAMETER NAME="PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
        <PARAMETER NAME="PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ" VALUE="19.999800"/>
-        <PARAMETER NAME="PSU__CRF_APB__ACPU_CTRL__FREQMHZ" VALUE="1200"/>
+        <PARAMETER NAME="PSU__CRF_APB__ACPU_CTRL__FREQMHZ" VALUE="1333.333"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRF_APB__APM_CTRL__FREQMHZ" VALUE="1"/>
@ -13117,7 +13117,7 @@
        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ" VALUE="25"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ" VALUE="27"/>
        <PARAMETER NAME="PSU__CRF_APB__DDR_CTRL__FREQMHZ" VALUE="1067"/>
-        <PARAMETER NAME="PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ" VALUE="500"/>
+        <PARAMETER NAME="PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ" VALUE="600"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ" VALUE="667"/>
@ -13143,7 +13143,7 @@
        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ" VALUE="250"/>
-        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ" VALUE="125"/>
+        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ" VALUE="300"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ" VALUE="100"/>
@ -13155,16 +13155,16 @@
        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ" VALUE="1000"/>
-        <PARAMETER NAME="PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ" VALUE="500"/>
+        <PARAMETER NAME="PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ" VALUE="533.333"/>
        <PARAMETER NAME="PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ" VALUE="500"/>
-        <PARAMETER NAME="PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ" VALUE="250"/>
+        <PARAMETER NAME="PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ" VALUE="267"/>
        <PARAMETER NAME="PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ" VALUE="400"/>
        <PARAMETER NAME="PSU__CRL_APB__PCAP_CTRL__FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ" VALUE="100"/>
-        <PARAMETER NAME="PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ" VALUE="500"/>
+        <PARAMETER NAME="PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ" VALUE="533.333"/>
        <PARAMETER NAME="PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ" VALUE="100"/>
-        <PARAMETER NAME="PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ" VALUE="500"/>
+        <PARAMETER NAME="PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ" VALUE="533.333"/>
        <PARAMETER NAME="PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ" VALUE="1500"/>
        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ" VALUE="50"/>
        <PARAMETER NAME="PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ" VALUE="100"/>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g_bd.tcl
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g_bd.tcl
@ -790,7 +790,7 @@ proc create_hier_cell_zups { parentCell nameHier } {
   CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \
   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
-   CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1333.333} \
   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
   CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
   CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
@ -883,7 +883,7 @@ proc create_hier_cell_zups { parentCell nameHier } {
   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {499.994995} \
   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
-   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {600} \
   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
   CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
@ -915,7 +915,7 @@ proc create_hier_cell_zups { parentCell nameHier } {
   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \
   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
-   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {533.333} \
   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
@ -939,7 +939,7 @@ proc create_hier_cell_zups { parentCell nameHier } {
   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \
   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
-   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {533.333} \
   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
@ -1000,7 +1000,7 @@ proc create_hier_cell_zups { parentCell nameHier } {
   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \
   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
-   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {267} \
   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \
   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
@ -1008,7 +1008,7 @@ proc create_hier_cell_zups { parentCell nameHier } {
   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \
   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
-   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {533.333} \
   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
@ -1043,10 +1043,10 @@ proc create_hier_cell_zups { parentCell nameHier } {
   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
-   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \
-   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {299.997009} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \
   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
-   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {300} \
   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {90} \
@ -1889,7 +1889,7 @@ proc create_root_design { parentCell } {
   CONFIG.c_m_axi_mm2s_data_width {64} \
   CONFIG.c_m_axis_mm2s_tdata_width {64} \
   CONFIG.c_mm2s_burst_size {64} \
-   CONFIG.c_s2mm_burst_size {8} \
+   CONFIG.c_s2mm_burst_size {16} \
   CONFIG.c_sg_include_stscntrl_strm {0} \
   CONFIG.c_sg_length_width {16} \
 ] $axi_dma_0
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0.xml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0.xml
@ -1627,7 +1627,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1658,7 +1658,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1684,7 +1684,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1704,7 +1704,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1732,7 +1732,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1752,7 +1752,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1775,7 +1775,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1.xml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1.xml
@ -583,7 +583,7 @@
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">4</spirit:value>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@ -1233,7 +1233,7 @@
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">4</spirit:value>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@ -1627,7 +1627,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1658,7 +1658,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1684,7 +1684,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1704,11 +1704,11 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:c5200498</spirit:value>
+            <spirit:value>9:ad94d400</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>sim_type</spirit:name>
@ -1732,7 +1732,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1752,11 +1752,11 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:c5200498</spirit:value>
+            <spirit:value>9:ad94d400</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>sim_type</spirit:name>
@ -1775,7 +1775,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.cpp
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.cpp
@ -114,7 +114,7 @@ void pl_eth_10g_auto_cc_1::before_end_of_elaboration()
    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -195,7 +195,7 @@ void pl_eth_10g_auto_cc_1::before_end_of_elaboration()
    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -307,7 +307,7 @@ void pl_eth_10g_auto_cc_1::before_end_of_elaboration()
    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -388,7 +388,7 @@ void pl_eth_10g_auto_cc_1::before_end_of_elaboration()
    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -500,7 +500,7 @@ void pl_eth_10g_auto_cc_1::before_end_of_elaboration()
    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -581,7 +581,7 @@ void pl_eth_10g_auto_cc_1::before_end_of_elaboration()
    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -681,7 +681,7 @@ pl_eth_10g_auto_cc_1::pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm) :
    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -742,7 +742,7 @@ pl_eth_10g_auto_cc_1::pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm) :
    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -868,7 +868,7 @@ pl_eth_10g_auto_cc_1::pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm) :
    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -929,7 +929,7 @@ pl_eth_10g_auto_cc_1::pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm) :
    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.v
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.v
@ -140,7 +140,7 @@ output wire s_axi_wready;
 output wire [1 : 0] s_axi_bresp;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
 output wire s_axi_bvalid;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
 M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
 input wire s_axi_bready;
@ -186,7 +186,7 @@ input wire m_axi_wready;
 input wire [1 : 0] m_axi_bresp;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
 input wire m_axi_bvalid;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
 NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
 output wire m_axi_bready;
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/synth/pl_eth_10g_auto_cc_1.v
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/synth/pl_eth_10g_auto_cc_1.v
@ -142,7 +142,7 @@ output wire s_axi_wready;
 output wire [1 : 0] s_axi_bresp;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
 output wire s_axi_bvalid;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
 M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
 input wire s_axi_bready;
@ -188,7 +188,7 @@ input wire m_axi_wready;
 input wire [1 : 0] m_axi_bresp;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
 input wire m_axi_bvalid;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \
 NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
 output wire m_axi_bready;
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0.xml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0.xml
@ -1519,7 +1519,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1550,7 +1550,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1594,7 +1594,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1614,7 +1614,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1642,7 +1642,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1662,7 +1662,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1685,7 +1685,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1.xml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1.xml
@ -1519,7 +1519,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1550,7 +1550,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1594,7 +1594,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1614,7 +1614,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1642,7 +1642,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1662,7 +1662,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1685,7 +1685,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/pl_eth_10g_auto_pc_0.xml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/pl_eth_10g_auto_pc_0.xml
@ -1511,7 +1511,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1542,7 +1542,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1577,7 +1577,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1597,7 +1597,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1625,7 +1625,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1645,7 +1645,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/pl_eth_10g_auto_pc_1.xml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/pl_eth_10g_auto_pc_1.xml
@ -1511,7 +1511,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1542,7 +1542,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1577,7 +1577,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1597,7 +1597,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1625,7 +1625,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1645,7 +1645,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0.xml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0.xml
@ -1519,7 +1519,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1550,7 +1550,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1594,7 +1594,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1614,7 +1614,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1642,7 +1642,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1662,7 +1662,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1685,7 +1685,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1.xml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1.xml
@ -1519,7 +1519,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1550,7 +1550,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1594,7 +1594,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1614,7 +1614,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1642,7 +1642,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1662,7 +1662,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1685,7 +1685,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2.xml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2.xml
@ -535,7 +535,7 @@
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">8</spirit:value>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">16</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@ -1105,7 +1105,7 @@
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">4</spirit:value>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">8</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@ -1519,7 +1519,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1550,7 +1550,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1594,7 +1594,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1614,11 +1614,11 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:8b059e5b</spirit:value>
+            <spirit:value>9:67119cc3</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>sim_type</spirit:name>
@ -1642,7 +1642,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1662,11 +1662,11 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:8b059e5b</spirit:value>
+            <spirit:value>9:67119cc3</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>sim_type</spirit:name>
@ -1685,7 +1685,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.cpp
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.cpp
@ -112,7 +112,7 @@ void pl_eth_10g_auto_us_2::before_end_of_elaboration()
    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -193,7 +193,7 @@ void pl_eth_10g_auto_us_2::before_end_of_elaboration()
    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -303,7 +303,7 @@ void pl_eth_10g_auto_us_2::before_end_of_elaboration()
    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -384,7 +384,7 @@ void pl_eth_10g_auto_us_2::before_end_of_elaboration()
    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -494,7 +494,7 @@ void pl_eth_10g_auto_us_2::before_end_of_elaboration()
    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -575,7 +575,7 @@ void pl_eth_10g_auto_us_2::before_end_of_elaboration()
    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -673,7 +673,7 @@ pl_eth_10g_auto_us_2::pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm) :
    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -734,7 +734,7 @@ pl_eth_10g_auto_us_2::pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm) :
    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -858,7 +858,7 @@ pl_eth_10g_auto_us_2::pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm) :
    S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
+    S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
    S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
@ -919,7 +919,7 @@ pl_eth_10g_auto_us_2::pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm) :
    M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
    M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
-    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4");
+    M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8");
    M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
    M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
    M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.v
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.v
@ -138,8 +138,8 @@ output wire s_axi_wready;
 output wire [1 : 0] s_axi_bresp;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
 output wire s_axi_bvalid;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NUM\
-_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
+M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
 input wire s_axi_bready;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
@ -178,7 +178,7 @@ input wire m_axi_wready;
 input wire [1 : 0] m_axi_bresp;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
 input wire m_axi_bvalid;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
 M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
 output wire m_axi_bready;
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/synth/pl_eth_10g_auto_us_2.v
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/synth/pl_eth_10g_auto_us_2.v
@ -140,8 +140,8 @@ output wire s_axi_wready;
 output wire [1 : 0] s_axi_bresp;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
 output wire s_axi_bvalid;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NUM\
-_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
+M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
 input wire s_axi_bready;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
@ -180,7 +180,7 @@ input wire m_axi_wready;
 input wire [1 : 0] m_axi_bresp;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
 input wire m_axi_bvalid;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
 M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
 output wire m_axi_bready;
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0.xml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0.xml
@ -2233,7 +2233,7 @@
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.MAX_BURST_LENGTH">8</spirit:value>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_S2MM.MAX_BURST_LENGTH">16</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
@ -5068,7 +5068,7 @@ Note: This value must be greater than or equal to the largest expected packet to
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:de9c90d9</spirit:value>
+            <spirit:value>9:888ce341</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@ -5079,7 +5079,7 @@ Note: This value must be greater than or equal to the largest expected packet to
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:de9c90d9</spirit:value>
+            <spirit:value>9:888ce341</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@ -5095,11 +5095,11 @@ Note: This value must be greater than or equal to the largest expected packet to
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 03:08:17 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:29:22 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:de9c90d9</spirit:value>
+            <spirit:value>9:888ce341</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@ -5140,7 +5140,7 @@ Note: This value must be greater than or equal to the largest expected packet to
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:94903a0b</spirit:value>
+            <spirit:value>9:2a5bc1d6</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@ -5156,11 +5156,11 @@ Note: This value must be greater than or equal to the largest expected packet to
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 03:08:17 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:29:22 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:94903a0b</spirit:value>
+            <spirit:value>9:2a5bc1d6</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@ -7892,7 +7892,7 @@ Note: This value must be greater than or equal to the largest expected packet to
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="INTEGER">
        <spirit:name>C_S2MM_BURST_SIZE</spirit:name>
-        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S2MM_BURST_SIZE" spirit:choiceRef="choice_list_884121e1">8</spirit:value>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S2MM_BURST_SIZE" spirit:choiceRef="choice_list_884121e1">16</spirit:value>
        <spirit:vendorExtensions>
          <xilinx:parameterInfo>
            <xilinx:enablement>
@ -8603,7 +8603,7 @@ Note: This value must be greater than or equal to the largest expected packet to
    <spirit:parameter>
      <spirit:name>c_s2mm_burst_size</spirit:name>
      <spirit:displayName>Max Burst Size</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.c_s2mm_burst_size" spirit:choiceRef="choice_list_425e29a6" spirit:order="3000" spirit:configGroups="1 NoDisplay">8</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.c_s2mm_burst_size" spirit:choiceRef="choice_list_425e29a6" spirit:order="3000" spirit:configGroups="1 NoDisplay">16</spirit:value>
      <spirit:vendorExtensions>
        <xilinx:parameterInfo>
          <xilinx:enablement>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/sim/pl_eth_10g_axi_dma_0_0.vhd
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/sim/pl_eth_10g_axi_dma_0_0.vhd
@ -341,8 +341,8 @@ ARCHITECTURE pl_eth_10g_axi_dma_0_0_arch OF pl_eth_10g_axi_dma_0_0 IS
  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1" & 
-", NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS " & 
+"1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
  ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
  ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
@ -454,7 +454,7 @@ BEGIN
      C_INCLUDE_MM2S_DRE => 1,
      C_INCLUDE_S2MM => 1,
      C_INCLUDE_S2MM_SF => 1,
-      C_S2MM_BURST_SIZE => 8,
+      C_S2MM_BURST_SIZE => 16,
      C_M_AXI_S2MM_ADDR_WIDTH => 32,
      C_M_AXI_S2MM_DATA_WIDTH => 64,
      C_S_AXIS_S2MM_TDATA_WIDTH => 64,
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/synth/pl_eth_10g_axi_dma_0_0.vhd
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/synth/pl_eth_10g_axi_dma_0_0.vhd
@ -318,7 +318,7 @@ ARCHITECTURE pl_eth_10g_axi_dma_0_0_arch OF pl_eth_10g_axi_dma_0_0 IS
  ATTRIBUTE CHECK_LICENSE_TYPE OF pl_eth_10g_axi_dma_0_0_arch : ARCHITECTURE IS "pl_eth_10g_axi_dma_0_0,axi_dma,{}";
  ATTRIBUTE CORE_GENERATION_INFO : STRING;
  ATTRIBUTE CORE_GENERATION_INFO OF pl_eth_10g_axi_dma_0_0_arch: ARCHITECTURE IS "pl_eth_10g_axi_dma_0_0,axi_dma,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=23,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=1,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=16,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=3" & 
-"2,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=64,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=64,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=8,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=64,C_INCLUDE_S2MM_DRE=1,C_INCREASE_THROUGHPUT=0,C_FAMILY=zynquplus}";
+"2,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=64,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=64,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=64,C_INCLUDE_S2MM_DRE=1,C_INCREASE_THROUGHPUT=0,C_FAMILY=zynquplus}";
  ATTRIBUTE X_INTERFACE_INFO : STRING;
  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
  ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_introut: SIGNAL IS "XIL_INTERFACENAME S2MM_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
@ -348,8 +348,8 @@ ARCHITECTURE pl_eth_10g_axi_dma_0_0_arch OF pl_eth_10g_axi_dma_0_0 IS
  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1" & 
-", NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS " & 
+"1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
  ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
  ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
@ -461,7 +461,7 @@ BEGIN
      C_INCLUDE_MM2S_DRE => 1,
      C_INCLUDE_S2MM => 1,
      C_INCLUDE_S2MM_SF => 1,
-      C_S2MM_BURST_SIZE => 8,
+      C_S2MM_BURST_SIZE => 16,
      C_M_AXI_S2MM_ADDR_WIDTH => 32,
      C_M_AXI_S2MM_DATA_WIDTH => 64,
      C_S_AXIS_S2MM_TDATA_WIDTH => 64,
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s00_mmu_0/pl_eth_10g_s00_mmu_0.xml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s00_mmu_0/pl_eth_10g_s00_mmu_0.xml
@ -1419,7 +1419,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1450,7 +1450,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1476,7 +1476,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1496,7 +1496,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s01_mmu_0/pl_eth_10g_s01_mmu_0.xml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s01_mmu_0/pl_eth_10g_s01_mmu_0.xml
@ -1419,7 +1419,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1450,7 +1450,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1476,7 +1476,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1496,7 +1496,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/pl_eth_10g_s02_mmu_0.xml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/pl_eth_10g_s02_mmu_0.xml
@ -567,7 +567,7 @@
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">8</spirit:value>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">16</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
@ -1201,7 +1201,7 @@
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>MAX_BURST_LENGTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">8</spirit:value>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">16</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
@ -1419,7 +1419,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1450,7 +1450,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1476,7 +1476,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
@ -1496,7 +1496,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:20 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:01 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/sim/pl_eth_10g_s02_mmu_0.v
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/sim/pl_eth_10g_s02_mmu_0.v
@ -134,8 +134,8 @@ output wire s_axi_wready;
 output wire [1 : 0] s_axi_bresp;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
 output wire s_axi_bvalid;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NUM\
-_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
+M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
 input wire s_axi_bready;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
@ -172,8 +172,8 @@ input wire m_axi_wready;
 input wire [1 : 0] m_axi_bresp;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
 input wire m_axi_bvalid;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NUM\
-_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
+M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
 output wire m_axi_bready;

--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/synth/pl_eth_10g_s02_mmu_0.v
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/synth/pl_eth_10g_s02_mmu_0.v
@ -136,8 +136,8 @@ output wire s_axi_wready;
 output wire [1 : 0] s_axi_bresp;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
 output wire s_axi_bvalid;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NUM\
-_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
+M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
 input wire s_axi_bready;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
@ -174,8 +174,8 @@ input wire m_axi_wready;
 input wire [1 : 0] m_axi_bresp;
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
 input wire m_axi_bvalid;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NUM\
-_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\
+M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
 output wire m_axi_bready;

--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/hdl/pl_eth_10g_zynq_ultra_ps_e_0_0.hwdef
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/hdl/pl_eth_10g_zynq_ultra_ps_e_0_0.hwdef
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_3.v
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_3.v
@ -76,7 +76,7 @@
 <PLLS><PLL domain={IO} vco={2999.970} /><PLL domain={RPLL} vco={2999.970} /></PLLS>\
 <CSUPMU><Unit name={CSU} usageRate={0.5} clockFreq={500} /><Unit name={PMU} usageRate={0.5} clockFreq={180} /></CSUPMU>\
 <GPIO><Bank ioBank={VCC_PSIO0} number={3} io_standard={LVCMOS 1.8V} /><Bank ioBank={VCC_PSIO1} number={2} io_standard={LVCMOS 1.8V} /><Bank ioBank={VCC_PSIO2} number={0} io_standard={LVCMOS 1.8V} /><Bank ioBank={VCC_PSIO3} number={16} io_standard={LVCMOS 3.3V} /></GPIO>\
-<IOINTERFACES> <IO name={QSPI} io_standard={} ioBank={VCC_PSIO0} clockFreq={124.998749} inputs={0} outputs={5} inouts={8} usageRate={0.5}/><IO name={NAND 3.1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={USB0} io_standard={} ioBank={VCC_PSIO2} clockFreq={249.997498} inputs={3} outputs={1} inouts={8} usageRate={0.5}/><IO name={USB1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GigabitEth0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GigabitEth1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GigabitEth2} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GigabitEth3} io_standard={} ioBank={VCC_PSIO2} clockFreq={124.998749} inputs={6} outputs={6} inouts={0} usageRate={0.5}/><IO name={GPIO 0} io_standard={} ioBank={VCC_PSIO0} clockFreq={1} inputs={0} outputs={0} inouts={3} usageRate={0.5}/><IO name={GPIO 1} io_standard={} ioBank={VCC_PSIO1} clockFreq={1} inputs={0} outputs={0} inouts={2} usageRate={0.5}/><IO name={GPIO 2} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GPIO 3} io_standard={} ioBank={VCC_PSIO3} clockFreq={1} inputs={} outputs={} inouts={16} usageRate={0.5}/><IO name={UART0} io_standard={} ioBank={VCC_PSIO0} clockFreq={99.999001} inputs={1} outputs={1} inouts={0} usageRate={0.5}/><IO name={UART1} io_standard={} ioBank={VCC_PSIO0} clockFreq={99.999001} inputs={1} outputs={1} inouts={0} usageRate={0.5}/><IO name={I2C0} io_standard={} ioBank={VCC_PSIO0} clockFreq={99.999001} inputs={0} outputs={0} inouts={2} usageRate={0.5}/><IO name={I2C1} io_standard={} ioBank={VCC_PSIO0} clockFreq={99.999001} inputs={0} outputs={0} inouts={2} usageRate={0.5}/><IO name={SPI0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={SPI1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={CAN0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={CAN1} io_standard={} ioBank={VCC_PSIO0} clockFreq={99.999001} inputs={1} outputs={1} inouts={0} usageRate={0.5}/><IO name={SD0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={SD1} io_standard={} ioBank={VCC_PSIO1} clockFreq={187.498123} inputs={2} outputs={2} inouts={9} usageRate={0.5}/><IO name={Trace} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={TTC0} io_standard={} ioBank={} clockFreq={100} inputs={0} outputs={0} inouts={0} usageRate={0.5}/><IO name={TTC1} io_standard={} ioBank={} clockFreq={100} inputs={0} outputs={0} inouts={0} usageRate={0.5}/><IO name={TTC2} io_standard={} ioBank={} clockFreq={100} inputs={0} outputs={0} inouts={0} usageRate={0.5}/><IO name={TTC3} io_standard={} ioBank={} clockFreq={100} inputs={0} outputs={0} inouts={0} usageRate={0.5}/><IO name={PJTAG} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={DPAUX} io_standard={} ioBank={VCC_PSIO1} clockFreq={} inputs={2} outputs={2} inouts={0} usageRate={0.5}/><IO name={WDT0} io_standard={} ioBank={} clockFreq={100} inputs={0} outputs={0} inouts={0} usageRate={0.5}/><IO name={WDT1} io_standard={} ioBank={} clockFreq={100} inputs={0} outputs={0} inouts={0} usageRate={0.5}/></IOINTERFACES>\
+<IOINTERFACES> <IO name={QSPI} io_standard={} ioBank={VCC_PSIO0} clockFreq={299.997009} inputs={0} outputs={5} inouts={8} usageRate={0.5}/><IO name={NAND 3.1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={USB0} io_standard={} ioBank={VCC_PSIO2} clockFreq={249.997498} inputs={3} outputs={1} inouts={8} usageRate={0.5}/><IO name={USB1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GigabitEth0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GigabitEth1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GigabitEth2} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GigabitEth3} io_standard={} ioBank={VCC_PSIO2} clockFreq={124.998749} inputs={6} outputs={6} inouts={0} usageRate={0.5}/><IO name={GPIO 0} io_standard={} ioBank={VCC_PSIO0} clockFreq={1} inputs={0} outputs={0} inouts={3} usageRate={0.5}/><IO name={GPIO 1} io_standard={} ioBank={VCC_PSIO1} clockFreq={1} inputs={0} outputs={0} inouts={2} usageRate={0.5}/><IO name={GPIO 2} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={GPIO 3} io_standard={} ioBank={VCC_PSIO3} clockFreq={1} inputs={} outputs={} inouts={16} usageRate={0.5}/><IO name={UART0} io_standard={} ioBank={VCC_PSIO0} clockFreq={99.999001} inputs={1} outputs={1} inouts={0} usageRate={0.5}/><IO name={UART1} io_standard={} ioBank={VCC_PSIO0} clockFreq={99.999001} inputs={1} outputs={1} inouts={0} usageRate={0.5}/><IO name={I2C0} io_standard={} ioBank={VCC_PSIO0} clockFreq={99.999001} inputs={0} outputs={0} inouts={2} usageRate={0.5}/><IO name={I2C1} io_standard={} ioBank={VCC_PSIO0} clockFreq={99.999001} inputs={0} outputs={0} inouts={2} usageRate={0.5}/><IO name={SPI0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={SPI1} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={CAN0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={CAN1} io_standard={} ioBank={VCC_PSIO0} clockFreq={99.999001} inputs={1} outputs={1} inouts={0} usageRate={0.5}/><IO name={SD0} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={SD1} io_standard={} ioBank={VCC_PSIO1} clockFreq={187.498123} inputs={2} outputs={2} inouts={9} usageRate={0.5}/><IO name={Trace} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={TTC0} io_standard={} ioBank={} clockFreq={100} inputs={0} outputs={0} inouts={0} usageRate={0.5}/><IO name={TTC1} io_standard={} ioBank={} clockFreq={100} inputs={0} outputs={0} inouts={0} usageRate={0.5}/><IO name={TTC2} io_standard={} ioBank={} clockFreq={100} inputs={0} outputs={0} inouts={0} usageRate={0.5}/><IO name={TTC3} io_standard={} ioBank={} clockFreq={100} inputs={0} outputs={0} inouts={0} usageRate={0.5}/><IO name={PJTAG} io_standard={} ioBank={} clockFreq={} inputs={} outputs={} inouts={} usageRate={0.5}/><IO name={DPAUX} io_standard={} ioBank={VCC_PSIO1} clockFreq={} inputs={2} outputs={2} inouts={0} usageRate={0.5}/><IO name={WDT0} io_standard={} ioBank={} clockFreq={100} inputs={0} outputs={0} inouts={0} usageRate={0.5}/><IO name={WDT1} io_standard={} ioBank={} clockFreq={100} inputs={0} outputs={0} inouts={0} usageRate={0.5}/></IOINTERFACES>\
 <AFI master={1} slave={0} clockFreq={124.999} usageRate={0.5} />\
 <LPINTERCONNECT clockFreq={499.994995} Bandwidth={High} />\
 </LPD>\
@ -329,12 +329,12 @@ SATA1_MGTRTXP3, , , OUT, PS_MGTRTXP3_505, , , , , ,, \n\
 , PSU__PMU__GPI0__ENABLE=0, PSU__PMU__GPI1__ENABLE=0, PSU__PMU__GPI2__ENABLE=0, PSU__PMU__GPI3__ENABLE=0, PSU__PMU__GPI4__ENABLE=0, PSU__PMU__GPI5__ENABLE=0, PSU__PMU__GPO0__ENABLE=1, PSU__PMU__GPO1__ENABLE=1, PSU__PMU__GPO2__ENABLE=1, PSU__PMU__GPO3__ENABLE=1, PSU__PMU__GPO4__ENABLE=1, PSU__PMU__GPO5__ENABLE=1, PSU__PMU__GPO0__IO=MIO 32, PSU__PMU__GPO1__IO=MIO 33, PSU__PMU__GPO2__IO=MIO 34, PSU__PMU__GPO3__IO=MIO 35, PSU__PMU__GPO4__IO=MIO 36, PSU__PMU__GPO5__IO=MIO 37, PSU__CSU__PERIPHERAL__ENABLE=0, PSU__QSPI__PERIPHERAL__ENABLE=1, PSU__QSPI__PERIPHERAL__IO=MIO 0 .. 12, PSU__QSPI__PERIPHERAL__MODE=Dual Parallel, PSU__QSPI__PERIPHERAL__DATA_MODE=x4, PSU__QSPI__GRP_FBCLK__ENABLE=1, PSU__QSPI__GRP_FBCLK__IO=MIO 6, PSU__SD0__PERIPHERAL__ENABLE=0, PSU__SD0__GRP_CD__ENABLE=0, PSU__SD0__GRP_POW__ENABLE=0, PSU__SD0__GRP_WP__ENABLE=0, PSU__SD1__PERIPHERAL__ENABLE=1, PSU__SD1__PERIPHERAL__IO=MIO 39 .. 51, PSU__SD1__GRP_CD__ENABLE=1, PSU__SD1__GRP_CD__IO=MIO 45, PSU__SD1__GRP_POW__ENABLE=1, PSU__SD1__GRP_POW__IO=MIO 43, PSU__SD1__GRP_WP__ENABLE=1, PSU__SD1__GRP_WP__IO=MIO 44, PSU__SD1__SLOT_TYPE=SD 3.0, PSU__SPI0__PERIPHERAL__ENABLE=0, PSU__SPI0__GRP_SS0__ENABLE=0, PSU__SPI0__GRP_SS1__ENABLE=0, PSU__SPI0__GRP_SS2__ENABLE=0, PSU__SPI1__PERIPHERAL__ENABLE=0, PSU__SPI1__GRP_SS0__ENABLE=0, PSU__SPI1__GRP_SS1__ENABLE=0, PSU__SPI1__GRP_SS2__ENABLE=0, PSU__SPI0_LOOP_SPI1__ENABLE=0, PSU__SWDT0__PERIPHERAL__ENABLE=1, PSU__SWDT0__PERIPHERAL__IO=EMIO, PSU__SWDT1__PERIPHERAL__ENABLE=1\
 , PSU__SWDT1__PERIPHERAL__IO=EMIO, PSU__UART0__BAUD_RATE=115200, PSU__TRACE__PERIPHERAL__ENABLE=0, PSU__TTC0__PERIPHERAL__ENABLE=1, PSU__TTC0__PERIPHERAL__IO=EMIO, PSU__TTC1__PERIPHERAL__ENABLE=1, PSU__TTC1__PERIPHERAL__IO=EMIO, PSU__UART1__BAUD_RATE=115200, PSU__TTC2__PERIPHERAL__ENABLE=1, PSU__TTC2__PERIPHERAL__IO=EMIO, PSU__TTC3__PERIPHERAL__ENABLE=1, PSU__TTC3__PERIPHERAL__IO=EMIO, PSU__DDRC__AL=0, PSU__DDRC__BANK_ADDR_COUNT=2, PSU__DDRC__BUS_WIDTH=64 Bit, PSU__DDRC__CL=15, PSU__DDRC__CLOCK_STOP_EN=0, PSU__DDRC__COL_ADDR_COUNT=10, PSU__DDRC__CWL=14, PSU__DDRC__DEVICE_CAPACITY=8192 MBits, PSU__DDRC__DRAM_WIDTH=16 Bits, PSU__DDRC__ECC=Disabled, PSU__DDRC__ENABLE=1, PSU__DDRC__FREQ_MHZ=1066.50, PSU__DDRC__MEMORY_TYPE=DDR 4, PSU__DDRC__ROW_ADDR_COUNT=16, PSU__DDRC__SPEED_BIN=DDR4_2133P, PSU__DDRC__T_FAW=30.0, PSU__DDRC__T_RAS_MIN=33, PSU__DDRC__T_RC=47.06, PSU__DDRC__T_RCD=15, PSU__DDRC__T_RP=15, PSU__DDRC__TRAIN_DATA_EYE=1, PSU__DDRC__TRAIN_READ_GATE=1, PSU__DDRC__TRAIN_WRITE_LEVEL=1, PSU__FP__POWER__ON=1, PSU__PL__POWER__ON=1, PSU__OCM_BANK0__POWER__ON=1, PSU__OCM_BANK1__POWER__ON=1, PSU__OCM_BANK2__POWER__ON=1, PSU__OCM_BANK3__POWER__ON=1, PSU__TCM0A__POWER__ON=1, PSU__TCM0B__POWER__ON=1, PSU__TCM1A__POWER__ON=1, PSU__TCM1B__POWER__ON=1, PSU__RPU__POWER__ON=1, PSU__L2_BANK0__POWER__ON=1, PSU__GPU_PP0__POWER__ON=1, PSU__GPU_PP1__POWER__ON=1, PSU__ACPU0__POWER__ON=1\
 , PSU__ACPU1__POWER__ON=1, PSU__ACPU2__POWER__ON=1, PSU__ACPU3__POWER__ON=1, PSU__UART0__PERIPHERAL__ENABLE=1, PSU__UART0__PERIPHERAL__IO=MIO 18 .. 19, PSU__UART1__PERIPHERAL__ENABLE=1, PSU__UART1__PERIPHERAL__IO=MIO 20 .. 21, PSU__UART0_LOOP_UART1__ENABLE=0, PSU__UART0__MODEM__ENABLE=0, PSU__UART1__MODEM__ENABLE=0, PSU__USB0__PERIPHERAL__ENABLE=1, PSU__USB0__PERIPHERAL__IO=MIO 52 .. 63, PSU__USB1__PERIPHERAL__ENABLE=0, PSU__CRF_APB__DPLL_CTRL__DIV2=1, PSU__CRF_APB__APLL_CTRL__DIV2=1, PSU__CRL_APB__IOPLL_CTRL__DIV2=1, PSU__CRL_APB__RPLL_CTRL__DIV2=1, PSU__CRF_APB__VPLL_CTRL__DIV2=1, PSU__CRF_APB__APLL_CTRL__FBDIV=72, PSU__CRF_APB__DPLL_CTRL__FBDIV=64, PSU__CRF_APB__VPLL_CTRL__FBDIV=90, PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0=3, PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0=2, PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0=3, PSU__CRF_APB__ACPU_CTRL__DIVISOR0=1, PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0=5, PSU__DISPLAYPORT__PERIPHERAL__ENABLE=1, PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0=2, PSU__CRF_APB__APM_CTRL__DIVISOR0=1, PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0=5, PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1=1, PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0=20, PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1=1, PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0=19, PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1=1, PSU__CRF_APB__DDR_CTRL__DIVISOR0=2, PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0=1, PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI0_REF__ENABLE=0, PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI1_REF__ENABLE=0, PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI2_REF__ENABLE=0, PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI3_REF__ENABLE=0, PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI4_REF__ENABLE=0, PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI5_REF__ENABLE=0, PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0=2\
-, PSU__SATA__PERIPHERAL__ENABLE=1, PSU__SATA__LANE0__ENABLE=0, PSU__SATA__LANE1__ENABLE=1, PSU__SATA__LANE1__IO=GT Lane3, PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0=2, PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0=4, PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0=4, PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0=30, PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0=3, PSU__CRL_APB__AFI6__ENABLE=0, PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0=25, PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1=3, PSU__CRL_APB__USB3__ENABLE=1, PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0=2, PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0=5, PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0=2, PSU__CRL_APB__IOPLL_CTRL__FBDIV=90, PSU__CRL_APB__RPLL_CTRL__FBDIV=90, PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0=3, PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0=3, PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0=6, PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0=6, PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0=6, PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0=7, PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0=8, PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1=1\
+, PSU__SATA__PERIPHERAL__ENABLE=1, PSU__SATA__LANE0__ENABLE=0, PSU__SATA__LANE1__ENABLE=1, PSU__SATA__LANE1__IO=GT Lane3, PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0=2, PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0=4, PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0=4, PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0=30, PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0=3, PSU__CRL_APB__AFI6__ENABLE=0, PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0=25, PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1=3, PSU__CRL_APB__USB3__ENABLE=1, PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0=2, PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0=5, PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0=2, PSU__CRL_APB__IOPLL_CTRL__FBDIV=90, PSU__CRL_APB__RPLL_CTRL__FBDIV=90, PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0=3, PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0=3, PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0=6, PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0=6, PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0=6, PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0=5, PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0=7, PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0=8, PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1=1\
 , PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0=7, PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0=7, PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0=6, PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0=3, PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0=3, PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0=6, PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0=4, PSU__CRL_APB__PCAP_CTRL__DIVISOR0=8, PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0=15, PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0=3, PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0=6, PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0=3, PSU__CRF_APB__APLL_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRF_APB__DPLL_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRF_APB__VPLL_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRF_APB__ACPU_CTRL__SRCSEL=APLL, PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL=IOPLL, PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL=IOPLL, PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL=VPLL, PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL=RPLL, PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL=RPLL, PSU__CRF_APB__DDR_CTRL__SRCSEL=DPLL, PSU__CRF_APB__GPU_REF_CTRL__SRCSEL=IOPLL, PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__SATA_REF_CTRL__SRCSEL=IOPLL, PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__PL0_REF_CTRL__SRCSEL=RPLL, PSU__CRL_APB__PL1_REF_CTRL__SRCSEL=RPLL, PSU__CRL_APB__PL2_REF_CTRL__SRCSEL=RPLL\
 , PSU__CRL_APB__PL3_REF_CTRL__SRCSEL=RPLL, PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL=APLL, PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL=APLL, PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL=DPLL, PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL=IOPLL, PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__IOPLL_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRL_APB__RPLL_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__UART0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__UART1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL=RPLL, PSU__CRL_APB__CPU_R5_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__PCAP_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__NAND_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__DLL_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__AMS_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL=IOPLL, PSU__IOU_SLCR__WDT_CLK_SEL__SELECT=APB, PSU__FPD_SLCR__WDT_CLK_SEL__SELECT=APB, PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL=APB, PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL=APB, PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL=APB, PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL=APB, PSU__CRF_APB__APLL_FRAC_CFG__ENABLED=0, PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED=0\
-, PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED=0, PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED=0, PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED=0, PSU__OVERRIDE__BASIC_CLOCK=0, PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ=1199.988037, PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ=250, PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ=249.997498, PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ=1, PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ=299.997009, PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ=24.999750, PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ=26.315527, PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ=533.328003, PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ=499.994995, PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ=124.998749, PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ=100, PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ=599.994019, PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ=599.994019, PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ=533.328003, PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ=99.999001, PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ=124.998749, PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ=250, PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ=124.998749, PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ=200, PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ=187.498123, PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ=214, PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ=214, PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ=1000, PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ=499.994995\
-, PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ=500, PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ=500, PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ=187.498123, PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ=499.994995, PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ=499.994995, PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ=1499.984985, PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ=49.999500, PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ=500, PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ=19.999800, PSU__CRF_APB__ACPU_CTRL__FREQMHZ=1200, PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ=250, PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ=250, PSU__CRF_APB__APM_CTRL__FREQMHZ=1, PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ=300, PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ=25, PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ=27, PSU__CRF_APB__DDR_CTRL__FREQMHZ=1067, PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ=500, PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ=250, PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ=100, PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ=600, PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ=600, PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ=533.333, PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ=100, PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ=250, PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ=200\
-, PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ=1000, PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ=500, PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ=500, PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ=250, PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ=400, PSU__CRL_APB__PCAP_CTRL__FREQMHZ=200, PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ=100, PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ=500, PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ=250, PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ=500, PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ=1500, PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ=50, PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ=500, PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ=20, PSU__CSU__CSU_TAMPER_0__ENABLE=0, PSU__CSU__CSU_TAMPER_1__ENABLE=0, PSU__CSU__CSU_TAMPER_2__ENABLE=0, PSU__CSU__CSU_TAMPER_3__ENABLE=0, PSU__CSU__CSU_TAMPER_4__ENABLE=0, PSU__CSU__CSU_TAMPER_5__ENABLE=0, PSU__CSU__CSU_TAMPER_6__ENABLE=0, PSU__CSU__CSU_TAMPER_7__ENABLE=0, PSU__CSU__CSU_TAMPER_8__ENABLE=0, PSU__CSU__CSU_TAMPER_9__ENABLE=0, PSU__CSU__CSU_TAMPER_10__ENABLE=0, PSU__CSU__CSU_TAMPER_11__ENABLE=0, PSU__CSU__CSU_TAMPER_12__ENABLE=0, PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM=0\
+, PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED=0, PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED=0, PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED=0, PSU__OVERRIDE__BASIC_CLOCK=0, PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ=1199.988037, PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ=250, PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ=249.997498, PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ=1, PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ=299.997009, PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ=24.999750, PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ=26.315527, PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ=533.328003, PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ=499.994995, PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ=124.998749, PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ=100, PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ=599.994019, PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ=599.994019, PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ=533.328003, PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ=99.999001, PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ=124.998749, PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ=250, PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ=299.997009, PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ=200, PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ=187.498123, PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ=214, PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ=214, PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ=1000, PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ=499.994995\
+, PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ=500, PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ=500, PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ=187.498123, PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ=499.994995, PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ=499.994995, PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ=1499.984985, PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ=49.999500, PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ=500, PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ=19.999800, PSU__CRF_APB__ACPU_CTRL__FREQMHZ=1333.333, PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ=250, PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ=250, PSU__CRF_APB__APM_CTRL__FREQMHZ=1, PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ=300, PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ=25, PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ=27, PSU__CRF_APB__DDR_CTRL__FREQMHZ=1067, PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ=600, PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ=250, PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ=100, PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ=600, PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ=600, PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ=533.333, PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ=100, PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ=250, PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ=300, PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ=200\
+, PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ=1000, PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ=533.333, PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ=500, PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ=267, PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ=400, PSU__CRL_APB__PCAP_CTRL__FREQMHZ=200, PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ=100, PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ=533.333, PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ=250, PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ=533.333, PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ=1500, PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ=50, PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ=500, PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ=20, PSU__CSU__CSU_TAMPER_0__ENABLE=0, PSU__CSU__CSU_TAMPER_1__ENABLE=0, PSU__CSU__CSU_TAMPER_2__ENABLE=0, PSU__CSU__CSU_TAMPER_3__ENABLE=0, PSU__CSU__CSU_TAMPER_4__ENABLE=0, PSU__CSU__CSU_TAMPER_5__ENABLE=0, PSU__CSU__CSU_TAMPER_6__ENABLE=0, PSU__CSU__CSU_TAMPER_7__ENABLE=0, PSU__CSU__CSU_TAMPER_8__ENABLE=0, PSU__CSU__CSU_TAMPER_9__ENABLE=0, PSU__CSU__CSU_TAMPER_10__ENABLE=0, PSU__CSU__CSU_TAMPER_11__ENABLE=0, PSU__CSU__CSU_TAMPER_12__ENABLE=0, PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM=0\
 , PSU__GEN_IPI_0__MASTER=APU, PSU__GEN_IPI_1__MASTER=RPU0, PSU__GEN_IPI_2__MASTER=RPU1, PSU__GEN_IPI_3__MASTER=PMU, PSU__GEN_IPI_4__MASTER=PMU, PSU__GEN_IPI_5__MASTER=PMU, PSU__GEN_IPI_6__MASTER=PMU, PSU__GEN_IPI_7__MASTER=NONE, PSU__GEN_IPI_8__MASTER=NONE, PSU__GEN_IPI_9__MASTER=NONE, PSU__GEN_IPI_10__MASTER=NONE, PSU__PROTECTION__SUBSYSTEMS=PMU Firmware:PMU, PSU__PROTECTION__DDR_SEGMENTS=NONE, PSU__PROTECTION__OCM_SEGMENTS=NONE, PSU__PROTECTION__LPD_SEGMENTS=SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware, PSU__PROTECTION__FPD_SEGMENTS=SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD000000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD020000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD040000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD610000 ;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware   |   SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware, PSU__PROTECTION__DEBUG=0, PSU__PROTECTION__PRESUBSYSTEMS=NONE, PSU__DDR_QOS_ENABLE=0, PSU__DDR_QOS_RD_LPR_THRSHLD=, PSU__DDR_QOS_RD_HPR_THRSHLD=, PSU__DDR_QOS_WR_THRSHLD=, PSU__DDR_QOS_HP0_RDQOS=, PSU__DDR_QOS_HP0_WRQOS=, PSU__DDR_QOS_HP1_RDQOS=, PSU__DDR_QOS_HP1_WRQOS=, PSU__DDR_QOS_HP2_RDQOS=, PSU__DDR_QOS_HP2_WRQOS=, PSU__DDR_QOS_HP3_RDQOS=, PSU__DDR_QOS_HP3_WRQOS= }" *)  
 (* HW_HANDOFF = "pl_eth_10g_zynq_ultra_ps_e_0_0.hwdef" *)  

--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/pl_eth_10g_zynq_ultra_ps_e_0_0.xml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/pl_eth_10g_zynq_ultra_ps_e_0_0.xml
@ -31175,11 +31175,11 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:15 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:29:57 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:a138200d</spirit:value>
+            <spirit:value>9:d6bf550d</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@ -31190,7 +31190,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:a138200d</spirit:value>
+            <spirit:value>9:d6bf550d</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@ -31206,11 +31206,11 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:17 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:29:59 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:a138200d</spirit:value>
+            <spirit:value>9:d6bf550d</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@ -31235,7 +31235,7 @@
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:30caf542</spirit:value>
+            <spirit:value>9:ec384d49</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@ -31251,11 +31251,11 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:18 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:29:59 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:8aa2bfbc</spirit:value>
+            <spirit:value>9:1037eaf7</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>sim_type</spirit:name>
@ -31274,11 +31274,11 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:30caf542</spirit:value>
+            <spirit:value>9:ec384d49</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@ -31294,11 +31294,11 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Oct 20 19:45:19 UTC 2023</spirit:value>
+            <spirit:value>Sat Oct 21 02:30:00 UTC 2023</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:8aa2bfbc</spirit:value>
+            <spirit:value>9:1037eaf7</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>sim_type</spirit:name>
@ -31313,7 +31313,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
-            <spirit:value>9:a138200d</spirit:value>
+            <spirit:value>9:d6bf550d</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@ -77788,7 +77788,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD
    <spirit:parameter>
      <spirit:name>PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0</spirit:name>
      <spirit:displayName>QSPI DIV0</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0" spirit:choiceRef="choice_list_efecb9ff">12</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0" spirit:choiceRef="choice_list_efecb9ff">5</spirit:value>
      <spirit:vendorExtensions>
        <xilinx:parameterInfo>
          <xilinx:enablement>
@ -78918,7 +78918,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD
    <spirit:parameter>
      <spirit:name>PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ</spirit:name>
      <spirit:displayName>ACT QSPI</spirit:displayName>
-      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ" spirit:minimum="-2" spirit:maximum="-1">124.998749</spirit:value>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ" spirit:minimum="-2" spirit:maximum="-1">299.997009</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ</spirit:name>
@ -79053,7 +79053,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD
    <spirit:parameter>
      <spirit:name>PSU__CRF_APB__ACPU_CTRL__FREQMHZ</spirit:name>
      <spirit:displayName>ACPU</spirit:displayName>
-      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRF_APB__ACPU_CTRL__FREQMHZ" spirit:minimum="0.000000" spirit:maximum="1334.000000">1200</spirit:value>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRF_APB__ACPU_CTRL__FREQMHZ" spirit:minimum="0.000000" spirit:maximum="1334.000000">1333.333</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ</spirit:name>
@ -79093,7 +79093,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD
    <spirit:parameter>
      <spirit:name>PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ</spirit:name>
      <spirit:displayName>GPU REF</spirit:displayName>
-      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ" spirit:minimum="0.000000" spirit:maximum="600.000000">500</spirit:value>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ" spirit:minimum="0.000000" spirit:maximum="600.000000">600</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ</spirit:name>
@ -79237,7 +79237,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD
    <spirit:parameter>
      <spirit:name>PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ</spirit:name>
      <spirit:displayName>QSPI</spirit:displayName>
-      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ" spirit:minimum="0.000000" spirit:maximum="300.000000">125</spirit:value>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ" spirit:minimum="0.000000" spirit:maximum="300.000000">300</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ</spirit:name>
@ -79297,7 +79297,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD
    <spirit:parameter>
      <spirit:name>PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ</spirit:name>
      <spirit:displayName>CPU_R5</spirit:displayName>
-      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ" spirit:minimum="0.000000" spirit:maximum="534.000000">500</spirit:value>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ" spirit:minimum="0.000000" spirit:maximum="534.000000">533.333</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ</spirit:name>
@ -79307,7 +79307,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD
    <spirit:parameter>
      <spirit:name>PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ</spirit:name>
      <spirit:displayName>IOU_SWITCH</spirit:displayName>
-      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ" spirit:minimum="0.000000" spirit:maximum="267.000000">250</spirit:value>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ" spirit:minimum="0.000000" spirit:maximum="267.000000">267</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ</spirit:name>
@ -79327,7 +79327,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD
    <spirit:parameter>
      <spirit:name>PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ</spirit:name>
      <spirit:displayName>LPD_SWITCH</spirit:displayName>
-      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ" spirit:minimum="0.000000" spirit:maximum="534.000000">500</spirit:value>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ" spirit:minimum="0.000000" spirit:maximum="534.000000">533.333</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ</spirit:name>
@ -79342,7 +79342,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD
    <spirit:parameter>
      <spirit:name>PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ</spirit:name>
      <spirit:displayName>ADMA_REF</spirit:displayName>
-      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ" spirit:minimum="0.000000" spirit:maximum="534.000000">500</spirit:value>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ" spirit:minimum="0.000000" spirit:maximum="534.000000">533.333</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ</spirit:name>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.c
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.c
@ -960,7 +960,7 @@ unsigned long psu_clock_init_data(void)
    *  PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1                          0x1

    * 6 bit divider
-    *  PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0                          0xc
+    *  PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0                          0x5

    * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
@ -968,10 +968,10 @@ unsigned long psu_clock_init_data(void)
    *  PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL                            0x0

    * This register controls this reference clock
-    * (OFFSET, MASK, VALUE)      (0XFF5E0068, 0x013F3F07U ,0x01010C00U)
+    * (OFFSET, MASK, VALUE)      (0XFF5E0068, 0x013F3F07U ,0x01010500U)
    */
 	PSU_Mask_Write(CRL_APB_QSPI_REF_CTRL_OFFSET,
-		0x013F3F07U, 0x01010C00U);
+		0x013F3F07U, 0x01010500U);
 /*##################################################################### */

    /*
@ -16082,13 +16082,13 @@ unsigned long psu_peripherals_init_data(void)

    * 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa
    * ss the Tap delay on the Rx clock signal of LQSPI
-    *  PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX                     1
+    *  PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX                     0

    * IOU tap delay bypass for the LQSPI and NAND controllers
-    * (OFFSET, MASK, VALUE)      (0XFF180390, 0x00000004U ,0x00000004U)
+    * (OFFSET, MASK, VALUE)      (0XFF180390, 0x00000004U ,0x00000000U)
    */
 	PSU_Mask_Write(IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET,
-		0x00000004U, 0x00000004U);
+		0x00000004U, 0x00000000U);
 /*##################################################################### */

    /*
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.html
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.html
@ -2267,13 +2267,13 @@ IOPLL
 QSPI freq (MHz)
 </TD>
 <TD width=10% BGCOLOR=#FBF5EF>
-125
+300
 </TD>
 <TD width=10% BGCOLOR=#FBF5EF>
 IOPLL
 </TD>
 <TD width=10% BGCOLOR=#FBF5EF>
-124.998749
+299.997009
 </TD>
 </TR>
 <TR valign="top">
@ -2365,7 +2365,7 @@ IOPLL
 CPU_R5 freq (MHz)
 </TD>
 <TD width=10% BGCOLOR=#FBF5EF>
-500
+533.333
 </TD>
 <TD width=10% BGCOLOR=#FBF5EF>
 IOPLL
@ -2379,7 +2379,7 @@ IOPLL
 IOU_SWITCH freq (MHz)
 </TD>
 <TD width=10% BGCOLOR=#FBF5EF>
-250
+267
 </TD>
 <TD width=10% BGCOLOR=#FBF5EF>
 IOPLL
@ -2393,7 +2393,7 @@ IOPLL
 LPD_SWITCH freq (MHz)
 </TD>
 <TD width=10% BGCOLOR=#FBF5EF>
-500
+533.333
 </TD>
 <TD width=10% BGCOLOR=#FBF5EF>
 IOPLL
@ -2491,7 +2491,7 @@ IOPLL
 ADMA freq (MHz)
 </TD>
 <TD width=10% BGCOLOR=#FBF5EF>
-500
+533.333
 </TD>
 <TD width=10% BGCOLOR=#FBF5EF>
 IOPLL
@ -2547,7 +2547,7 @@ IOPLL
 ACPU freq (MHz)
 </TD>
 <TD width=10% BGCOLOR=#FBF5EF>
-1200
+1333.333
 </TD>
 <TD width=10% BGCOLOR=#FBF5EF>
 APLL
@ -2659,7 +2659,7 @@ DPLL
 GPU freq (MHz)
 </TD>
 <TD width=10% BGCOLOR=#FBF5EF>
-500
+600
 </TD>
 <TD width=10% BGCOLOR=#FBF5EF>
 IOPLL
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.tcl
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.tcl
@ -614,7 +614,7 @@ set psu_clock_init_data {
 		# PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1                                              0x1

 		# 6 bit divider
-		# PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0                                              0xc
+		# PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0                                              0x5

 		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
    # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
@ -622,8 +622,8 @@ set psu_clock_init_data {
 		# PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL                                                0x0

 		# This register controls this reference clock
-		#(OFFSET, MASK, VALUE)      (0XFF5E0068, 0x013F3F07U ,0x01010C00U)  */
-    mask_write 0XFF5E0068 0x013F3F07 0x01010C00
+		#(OFFSET, MASK, VALUE)      (0XFF5E0068, 0x013F3F07U ,0x01010500U)  */
+    mask_write 0XFF5E0068 0x013F3F07 0x01010500
 		# Register : SDIO1_REF_CTRL @ 0XFF5E0070</p>

 		# Clock active signal. Switch to 0 to disable the clock
@ -13956,11 +13956,11 @@ set psu_peripherals_init_data {

 		# 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa
    # ss the Tap delay on the Rx clock signal of LQSPI
-		# PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX                                         1
+		# PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX                                         0

 		# IOU tap delay bypass for the LQSPI and NAND controllers
-		#(OFFSET, MASK, VALUE)      (0XFF180390, 0x00000004U ,0x00000004U)  */
-    mask_write 0XFF180390 0x00000004 0x00000004
+		#(OFFSET, MASK, VALUE)      (0XFF180390, 0x00000004U ,0x00000000U)  */
+    mask_write 0XFF180390 0x00000004 0x00000000
 		# : NAND
 		# : USB RESET
 		# Register : RST_LPD_TOP @ 0XFF5E023C</p>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init_gpl.c
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init_gpl.c
@ -969,7 +969,7 @@ unsigned long psu_clock_init_data(void)
    *  PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1                          0x1

    * 6 bit divider
-    *  PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0                          0xc
+    *  PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0                          0x5

    * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
@ -977,10 +977,10 @@ unsigned long psu_clock_init_data(void)
    *  PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL                            0x0

    * This register controls this reference clock
-    * (OFFSET, MASK, VALUE)      (0XFF5E0068, 0x013F3F07U ,0x01010C00U)
+    * (OFFSET, MASK, VALUE)      (0XFF5E0068, 0x013F3F07U ,0x01010500U)
    */
 	PSU_Mask_Write(CRL_APB_QSPI_REF_CTRL_OFFSET,
-		0x013F3F07U, 0x01010C00U);
+		0x013F3F07U, 0x01010500U);
 /*##################################################################### */

    /*
@ -16091,13 +16091,13 @@ unsigned long psu_peripherals_init_data(void)

    * 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa
    * ss the Tap delay on the Rx clock signal of LQSPI
-    *  PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX                     1
+    *  PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX                     0

    * IOU tap delay bypass for the LQSPI and NAND controllers
-    * (OFFSET, MASK, VALUE)      (0XFF180390, 0x00000004U ,0x00000004U)
+    * (OFFSET, MASK, VALUE)      (0XFF180390, 0x00000004U ,0x00000000U)
    */
 	PSU_Mask_Write(IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET,
-		0x00000004U, 0x00000004U);
+		0x00000004U, 0x00000000U);
 /*##################################################################### */

    /*
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/pl_eth_10g.bda
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/pl_eth_10g.bda
@ -21,6 +21,101 @@
  <key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
  <graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
    <node id="n0">
+      <data key="BA">0xC0000000</data>
+      <data key="BP">C_BASEADDR</data>
+      <data key="HA">0xDFFFFFFF</data>
+      <data key="HP">C_HIGHADDR</data>
+      <data key="MA">Data_S2MM</data>
+      <data key="MX">/axi_dma_0</data>
+      <data key="MI">M_AXI_S2MM</data>
+      <data key="MS">SEG_zynq_ultra_ps_e_0_HP0_QSPI</data>
+      <data key="MV">xilinx.com:ip:axi_dma:7.1</data>
+      <data key="TM">both</data>
+      <data key="SX">/zups/zynq_ultra_ps_e_0</data>
+      <data key="SI">S_AXI_HP0_FPD</data>
+      <data key="SS">HP0_QSPI</data>
+      <data key="SV">xilinx.com:ip:zynq_ultra_ps_e:3.3</data>
+      <data key="TU">memory</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n1">
+      <data key="BA">0xE0000000</data>
+      <data key="BP">C_BASEADDR</data>
+      <data key="HA">0xEFFFFFFF</data>
+      <data key="HP">C_HIGHADDR</data>
+      <data key="MA">Data_SG</data>
+      <data key="MX">/axi_dma_0</data>
+      <data key="MI">M_AXI_SG</data>
+      <data key="MS">SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW</data>
+      <data key="MV">xilinx.com:ip:axi_dma:7.1</data>
+      <data key="TM">both</data>
+      <data key="SX">/zups/zynq_ultra_ps_e_0</data>
+      <data key="SI">S_AXI_HP0_FPD</data>
+      <data key="SS">HP0_PCIE_LOW</data>
+      <data key="SV">xilinx.com:ip:zynq_ultra_ps_e:3.3</data>
+      <data key="TU">memory</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n2">
+      <data key="BA">0xC0000000</data>
+      <data key="BP">C_BASEADDR</data>
+      <data key="HA">0xDFFFFFFF</data>
+      <data key="HP">C_HIGHADDR</data>
+      <data key="MA">Data_SG</data>
+      <data key="MX">/axi_dma_0</data>
+      <data key="MI">M_AXI_SG</data>
+      <data key="MS">SEG_zynq_ultra_ps_e_0_HP0_QSPI</data>
+      <data key="MV">xilinx.com:ip:axi_dma:7.1</data>
+      <data key="TM">both</data>
+      <data key="SX">/zups/zynq_ultra_ps_e_0</data>
+      <data key="SI">S_AXI_HP0_FPD</data>
+      <data key="SS">HP0_QSPI</data>
+      <data key="SV">xilinx.com:ip:zynq_ultra_ps_e:3.3</data>
+      <data key="TU">memory</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n3">
+      <data key="BA">0xC0000000</data>
+      <data key="BP">C_BASEADDR</data>
+      <data key="HA">0xDFFFFFFF</data>
+      <data key="HP">C_HIGHADDR</data>
+      <data key="MA">Data_MM2S</data>
+      <data key="MX">/axi_dma_0</data>
+      <data key="MI">M_AXI_MM2S</data>
+      <data key="MS">SEG_zynq_ultra_ps_e_0_HP0_QSPI</data>
+      <data key="MV">xilinx.com:ip:axi_dma:7.1</data>
+      <data key="TM">both</data>
+      <data key="SX">/zups/zynq_ultra_ps_e_0</data>
+      <data key="SI">S_AXI_HP0_FPD</data>
+      <data key="SS">HP0_QSPI</data>
+      <data key="SV">xilinx.com:ip:zynq_ultra_ps_e:3.3</data>
+      <data key="TU">memory</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n4">
+      <data key="VH">2</data>
+      <data key="VM">pl_eth_10g</data>
+      <data key="VT">VR</data>
+    </node>
+    <node id="n5">
+      <data key="BA">0xE0000000</data>
+      <data key="BP">C_BASEADDR</data>
+      <data key="HA">0xEFFFFFFF</data>
+      <data key="HP">C_HIGHADDR</data>
+      <data key="MA">Data_MM2S</data>
+      <data key="MX">/axi_dma_0</data>
+      <data key="MI">M_AXI_MM2S</data>
+      <data key="MS">SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW</data>
+      <data key="MV">xilinx.com:ip:axi_dma:7.1</data>
+      <data key="TM">both</data>
+      <data key="SX">/zups/zynq_ultra_ps_e_0</data>
+      <data key="SI">S_AXI_HP0_FPD</data>
+      <data key="SS">HP0_PCIE_LOW</data>
+      <data key="SV">xilinx.com:ip:zynq_ultra_ps_e:3.3</data>
+      <data key="TU">memory</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n6">
      <data key="BA">0x00000000</data>
      <data key="BP">C_BASEADDR</data>
      <data key="HA">0x7FFFFFFF</data>
@ -38,52 +133,7 @@
      <data key="TU">memory</data>
      <data key="VT">AC</data>
    </node>
-    <node id="n1">
-      <data key="TU">active</data>
-      <data key="VH">2</data>
-      <data key="VT">PM</data>
-    </node>
-    <node id="n2">
-      <data key="VM">pl_eth_10g</data>
-      <data key="VT">BC</data>
-    </node>
-    <node id="n3">
-      <data key="BA">0xE0000000</data>
-      <data key="BP">C_BASEADDR</data>
-      <data key="HA">0xEFFFFFFF</data>
-      <data key="HP">C_HIGHADDR</data>
-      <data key="MA">Data_S2MM</data>
-      <data key="MX">/axi_dma_0</data>
-      <data key="MI">M_AXI_S2MM</data>
-      <data key="MS">SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW</data>
-      <data key="MV">xilinx.com:ip:axi_dma:7.1</data>
-      <data key="TM">both</data>
-      <data key="SX">/zups/zynq_ultra_ps_e_0</data>
-      <data key="SI">S_AXI_HP0_FPD</data>
-      <data key="SS">HP0_PCIE_LOW</data>
-      <data key="SV">xilinx.com:ip:zynq_ultra_ps_e:3.3</data>
-      <data key="TU">memory</data>
-      <data key="VT">AC</data>
-    </node>
-    <node id="n4">
-      <data key="BA">0xE0000000</data>
-      <data key="BP">C_BASEADDR</data>
-      <data key="HA">0xEFFFFFFF</data>
-      <data key="HP">C_HIGHADDR</data>
-      <data key="MA">Data_MM2S</data>
-      <data key="MX">/axi_dma_0</data>
-      <data key="MI">M_AXI_MM2S</data>
-      <data key="MS">SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW</data>
-      <data key="MV">xilinx.com:ip:axi_dma:7.1</data>
-      <data key="TM">both</data>
-      <data key="SX">/zups/zynq_ultra_ps_e_0</data>
-      <data key="SI">S_AXI_HP0_FPD</data>
-      <data key="SS">HP0_PCIE_LOW</data>
-      <data key="SV">xilinx.com:ip:zynq_ultra_ps_e:3.3</data>
-      <data key="TU">memory</data>
-      <data key="VT">AC</data>
-    </node>
-    <node id="n5">
+    <node id="n7">
      <data key="BA">0x0080010000</data>
      <data key="BP">C_BASEADDR</data>
      <data key="HA">0x008001FFFF</data>
@ -101,61 +151,7 @@
      <data key="TU">register</data>
      <data key="VT">AC</data>
    </node>
-    <node id="n6">
-      <data key="BA">0xE0000000</data>
-      <data key="BP">C_BASEADDR</data>
-      <data key="HA">0xEFFFFFFF</data>
-      <data key="HP">C_HIGHADDR</data>
-      <data key="MA">Data_SG</data>
-      <data key="MX">/axi_dma_0</data>
-      <data key="MI">M_AXI_SG</data>
-      <data key="MS">SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW</data>
-      <data key="MV">xilinx.com:ip:axi_dma:7.1</data>
-      <data key="TM">both</data>
-      <data key="SX">/zups/zynq_ultra_ps_e_0</data>
-      <data key="SI">S_AXI_HP0_FPD</data>
-      <data key="SS">HP0_PCIE_LOW</data>
-      <data key="SV">xilinx.com:ip:zynq_ultra_ps_e:3.3</data>
-      <data key="TU">memory</data>
-      <data key="VT">AC</data>
-    </node>
-    <node id="n7">
-      <data key="BA">0xC0000000</data>
-      <data key="BP">C_BASEADDR</data>
-      <data key="HA">0xDFFFFFFF</data>
-      <data key="HP">C_HIGHADDR</data>
-      <data key="MA">Data_SG</data>
-      <data key="MX">/axi_dma_0</data>
-      <data key="MI">M_AXI_SG</data>
-      <data key="MS">SEG_zynq_ultra_ps_e_0_HP0_QSPI</data>
-      <data key="MV">xilinx.com:ip:axi_dma:7.1</data>
-      <data key="TM">both</data>
-      <data key="SX">/zups/zynq_ultra_ps_e_0</data>
-      <data key="SI">S_AXI_HP0_FPD</data>
-      <data key="SS">HP0_QSPI</data>
-      <data key="SV">xilinx.com:ip:zynq_ultra_ps_e:3.3</data>
-      <data key="TU">memory</data>
-      <data key="VT">AC</data>
-    </node>
    <node id="n8">
-      <data key="BA">0xC0000000</data>
-      <data key="BP">C_BASEADDR</data>
-      <data key="HA">0xDFFFFFFF</data>
-      <data key="HP">C_HIGHADDR</data>
-      <data key="MA">Data_MM2S</data>
-      <data key="MX">/axi_dma_0</data>
-      <data key="MI">M_AXI_MM2S</data>
-      <data key="MS">SEG_zynq_ultra_ps_e_0_HP0_QSPI</data>
-      <data key="MV">xilinx.com:ip:axi_dma:7.1</data>
-      <data key="TM">both</data>
-      <data key="SX">/zups/zynq_ultra_ps_e_0</data>
-      <data key="SI">S_AXI_HP0_FPD</data>
-      <data key="SS">HP0_QSPI</data>
-      <data key="SV">xilinx.com:ip:zynq_ultra_ps_e:3.3</data>
-      <data key="TU">memory</data>
-      <data key="VT">AC</data>
-    </node>
-    <node id="n9">
      <data key="BA">0x0080000000</data>
      <data key="BP">C_BASEADDR</data>
      <data key="HA">0x008000FFFF</data>
@ -173,7 +169,7 @@
      <data key="TU">register</data>
      <data key="VT">AC</data>
    </node>
-    <node id="n10">
+    <node id="n9">
      <data key="BA">0x00000000</data>
      <data key="BP">C_BASEADDR</data>
      <data key="HA">0x7FFFFFFF</data>
@ -191,7 +187,7 @@
      <data key="TU">memory</data>
      <data key="VT">AC</data>
    </node>
-    <node id="n11">
+    <node id="n10">
      <data key="BA">0x00000000</data>
      <data key="BP">C_BASEADDR</data>
      <data key="HA">0x7FFFFFFF</data>
@ -209,30 +205,29 @@
      <data key="TU">memory</data>
      <data key="VT">AC</data>
    </node>
+    <node id="n11">
+      <data key="VM">pl_eth_10g</data>
+      <data key="VT">BC</data>
+    </node>
    <node id="n12">
-      <data key="BA">0xC0000000</data>
+      <data key="BA">0xE0000000</data>
      <data key="BP">C_BASEADDR</data>
-      <data key="HA">0xDFFFFFFF</data>
+      <data key="HA">0xEFFFFFFF</data>
      <data key="HP">C_HIGHADDR</data>
      <data key="MA">Data_S2MM</data>
      <data key="MX">/axi_dma_0</data>
      <data key="MI">M_AXI_S2MM</data>
-      <data key="MS">SEG_zynq_ultra_ps_e_0_HP0_QSPI</data>
+      <data key="MS">SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW</data>
      <data key="MV">xilinx.com:ip:axi_dma:7.1</data>
      <data key="TM">both</data>
      <data key="SX">/zups/zynq_ultra_ps_e_0</data>
      <data key="SI">S_AXI_HP0_FPD</data>
-      <data key="SS">HP0_QSPI</data>
+      <data key="SS">HP0_PCIE_LOW</data>
      <data key="SV">xilinx.com:ip:zynq_ultra_ps_e:3.3</data>
      <data key="TU">memory</data>
      <data key="VT">AC</data>
    </node>
    <node id="n13">
-      <data key="VH">2</data>
-      <data key="VM">pl_eth_10g</data>
-      <data key="VT">VR</data>
-    </node>
-    <node id="n14">
      <data key="BA">0xFF000000</data>
      <data key="BP">C_BASEADDR</data>
      <data key="HA">0xFFFFFFFF</data>
@ -250,44 +245,49 @@
      <data key="TU">register</data>
      <data key="VT">AC</data>
    </node>
-    <edge id="e0" source="n2" target="n13">
+    <node id="n14">
+      <data key="TU">active</data>
+      <data key="VH">2</data>
+      <data key="VT">PM</data>
+    </node>
+    <edge id="e0" source="n11" target="n4">
    </edge>
-    <edge id="e1" source="n13" target="n1">
+    <edge id="e1" source="n4" target="n14">
    </edge>
-    <edge id="e2" source="n10" target="n1">
+    <edge id="e2" source="n9" target="n14">
      <data key="EH">2</data>
    </edge>
-    <edge id="e3" source="n6" target="n1">
+    <edge id="e3" source="n1" target="n14">
      <data key="EH">2</data>
    </edge>
-    <edge id="e4" source="n7" target="n1">
+    <edge id="e4" source="n2" target="n14">
      <data key="EH">2</data>
    </edge>
-    <edge id="e5" source="n0" target="n1">
+    <edge id="e5" source="n6" target="n14">
      <data key="EH">2</data>
    </edge>
-    <edge id="e6" source="n4" target="n1">
+    <edge id="e6" source="n5" target="n14">
      <data key="EH">2</data>
    </edge>
-    <edge id="e7" source="n8" target="n1">
+    <edge id="e7" source="n3" target="n14">
      <data key="EH">2</data>
    </edge>
-    <edge id="e8" source="n11" target="n1">
+    <edge id="e8" source="n10" target="n14">
      <data key="EH">2</data>
    </edge>
-    <edge id="e9" source="n14" target="n1">
+    <edge id="e9" source="n13" target="n14">
      <data key="EH">2</data>
    </edge>
-    <edge id="e10" source="n3" target="n1">
+    <edge id="e10" source="n12" target="n14">
      <data key="EH">2</data>
    </edge>
-    <edge id="e11" source="n12" target="n1">
+    <edge id="e11" source="n0" target="n14">
      <data key="EH">2</data>
    </edge>
-    <edge id="e12" source="n9" target="n1">
+    <edge id="e12" source="n8" target="n14">
      <data key="EH">2</data>
    </edge>
-    <edge id="e13" source="n5" target="n1">
+    <edge id="e13" source="n7" target="n14">
      <data key="EH">2</data>
    </edge>
  </graph>
--- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/pl_eth_10g.bxml
+++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/pl_eth_10g.bxml
@ -2,10 +2,10 @@
 <Root MajorVersion="0" MinorVersion="39">
  <CompositeFile CompositeFileTopName="pl_eth_10g" CanBeSetAsTop="true" CanDisplayChildGraph="true">
    <Description>Composite Fileset</Description>
-    <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1697831121"/>
-    <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1697831121"/>
-    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1697831121"/>
-    <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1697831121"/>
+    <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1697855401"/>
+    <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1697855401"/>
+    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1697855401"/>
+    <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1697855401"/>
    <FileCollection Name="SOURCES" Type="SOURCES">
      <File Name="synth\pl_eth_10g.v" Type="Verilog">
        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
--- a/Show More
+++ b/Show More
				`@ -0,0 +1 @@`
				`Use this directory to track your constraint files`