diff --git a/Petalinux/project-spec/attributes b/Petalinux/project-spec/attributes new file mode 100644 index 0000000..b726d37 --- /dev/null +++ b/Petalinux/project-spec/attributes @@ -0,0 +1,11 @@ +#Virtual Providers + + + +#defconfigs + +UBOOT_DEFAULT_DEFCONFIG="xilinx_zynqmp_virt_defconfig" + +#atf + +CONFIG_SUBSYSTEM_PRELOADED_BL33_BASE=0x10080000 diff --git a/Petalinux/project-spec/configs/busybox/inetd.conf b/Petalinux/project-spec/configs/busybox/inetd.conf new file mode 100644 index 0000000..b7c0bbc --- /dev/null +++ b/Petalinux/project-spec/configs/busybox/inetd.conf @@ -0,0 +1,22 @@ +#/etc/inetd.conf: see inetd(8) for further informations. +# +# Internet server configuration database +# +# If you want to disable an entry so it isn't touched during +# package updates just comment it out with a single '#' character. +# +# +# +#:INTERNAL: Internal services +#echo stream tcp nowait root internal +#echo dgram udp wait root internal +#chargen stream tcp nowait root internal +#chargen dgram udp wait root internal +#discard stream tcp nowait root internal +#discard dgram udp wait root internal +#daytime stream tcp nowait root internal +#daytime dgram udp wait root internal +#time stream tcp nowait root internal +#time dgram udp wait root internal +telnet stream tcp nowait root telnetd telnetd -i +ftp stream tcp nowait root ftpd ftpd -w diff --git a/Petalinux/project-spec/configs/config b/Petalinux/project-spec/configs/config new file mode 100644 index 0000000..a001f68 --- /dev/null +++ b/Petalinux/project-spec/configs/config @@ -0,0 +1,304 @@ +# +# Automatically generated file; DO NOT EDIT. +# misc/config System Configuration +# +CONFIG_SUBSYSTEM_TYPE_LINUX=y +CONFIG_SYSTEM_ZYNQMP=y + +# +# Linux Components Selection +# +CONFIG_SUBSYSTEM_COMPONENT_DEVICE__TREE_NAME_DEVICE__TREE__GENERATOR=y +# CONFIG_SUBSYSTEM_COMPONENT_PRE_FSBL is not set +CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_FSBL=y +CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_NAME_ZYNQMP_FSBL=y +CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_PS_INIT=y +CONFIG_SUBSYSTEM_COMPONENT_PMU_FIRMWARE=y +CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_U__BOOT__XLNX=y +# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_REMOTE is not set +# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_EXT__LOCAL__SRC is not set +CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_ARM__TRUSTED__FIRMWARE=y +# CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_REMOTE is not set +# CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_EXT__LOCAL__SRC is not set +CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_LINUX__XLNX=y +# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_REMOTE is not set +# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_EXT__LOCAL__SRC is not set + +# +# Auto Config Settings +# +CONFIG_SUBSYSTEM_AUTOCONFIG_DEVICE__TREE=y +# CONFIG_SUBSYSTEM_DEVICE_TREE_MANUAL_INCLUDE is not set +# CONFIG_SUBSYSTEM_AUTOCONFIG_KERNEL is not set +# CONFIG_SUBSYSTEM_AUTOCONFIG_U__BOOT is not set +CONFIG_SUBSYSTEM_HARDWARE_AUTO=y +CONFIG_SUBSYSTEM_PROCESSOR0_IP_NAME="psu_cortexa53_0" +CONFIG_SUBSYSTEM_PROCESSOR_psu_cortexa53_0_SELECT=y +CONFIG_SUBSYSTEM_ARCH_AARCH64=y + +# +# Memory Settings +# +CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_SELECT=y +# CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_1_BANKLESS_SELECT is not set +# CONFIG_SUBSYSTEM_MEMORY_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_BASEADDR=0x0 +CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_SIZE=0x80000000 +CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_KERNEL_BASEADDR=0x0 +CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_U__BOOT_TEXTBASE_OFFSET=0x100000 +CONFIG_SUBSYSTEM_MEMORY_IP_NAME="PSU_DDR_0" + +# +# Serial Settings +# +# CONFIG_SUBSYSTEM_PMUFW_SERIAL_PSU_UART_1_SELECT is not set +CONFIG_SUBSYSTEM_PMUFW_SERIAL_PSU_UART_0_SELECT=y +# CONFIG_SUBSYSTEM_PMUFW_SERIAL_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_FSBL_SERIAL_PSU_UART_1_SELECT is not set +CONFIG_SUBSYSTEM_FSBL_SERIAL_PSU_UART_0_SELECT=y +# CONFIG_SUBSYSTEM_FSBL_SERIAL_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_ATF_SERIAL_PSU_UART_1_SELECT is not set +CONFIG_SUBSYSTEM_ATF_SERIAL_PSU_UART_0_SELECT=y +# CONFIG_SUBSYSTEM_ATF_SERIAL_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_SELECT is not set +CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_SELECT=y +# CONFIG_SUBSYSTEM_SERIAL_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_9600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_28800 is not set +CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_115200=y +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_230400 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_460800 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_921600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_9600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_28800 is not set +CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_115200=y +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_230400 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_460800 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_921600 is not set +CONFIG_SUBSYSTEM_SERIAL_PMUFW_IP_NAME="psu_uart_0" +CONFIG_SUBSYSTEM_SERIAL_FSBL_IP_NAME="psu_uart_0" +CONFIG_SUBSYSTEM_SERIAL_ATF_IP_NAME="cadence" +CONFIG_SUBSYSTEM_SERIAL_IP_NAME="psu_uart_0" + +# +# Ethernet Settings +# +CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_SELECT=y +# CONFIG_SUBSYSTEM_ETHERNET_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC_AUTO is not set +CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC="00:0a:35:00:22:01" +CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_USE_DHCP=y + +# +# Flash Settings +# +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_SELECT=y +# CONFIG_SUBSYSTEM_FLASH_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_FLASH__ADVANCED_AUTOCONFIG is not set + +# +# partition 0 +# +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_NAME="boot" +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0x01e00000 + +# +# partition 1 +# +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_NAME="bootenv" +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x40000 + +# +# partition 2 +# +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_NAME="kernel" +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x3c00000 + +# +# partition 3 +# +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="" +CONFIG_SUBSYSTEM_FLASH_IP_NAME="psu_qspi_0" + +# +# SD/SDIO Settings +# +CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y +# CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_SD_PSU_SD_1_SELECT=y + +# +# RTC Settings +# +CONFIG_SUBSYSTEM_RTC_PSU_RTC_SELECT=y +# CONFIG_SUBSYSTEM_RTC_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_SATA_PSU_SATA_SELECT=y +CONFIG_SUBSYSTEM_I2C_PSU_I2C_1_SELECT=y +CONFIG_SUBSYSTEM_I2C_PSU_I2C_0_SELECT=y +CONFIG_SUBSYSTEM_USB_PSU_USB_0_SELECT=y +CONFIG_SUBSYSTEM_DP_PSU_DP_SELECT=y +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG=y + +# +# boot image settings +# +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_FLASH_SELECT is not set +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_SD_SELECT=y +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_IMAGE_NAME="BOOT.BIN" + +# +# u-boot env partition settings +# +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_FLASH_SELECT=y +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_SD_SELECT is not set +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_PART_NAME="bootenv" + +# +# kernel image settings +# +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_FLASH_SELECT is not set +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_SD_SELECT=y +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_ETHERNET_SELECT is not set +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_IMAGE_NAME="image.ub" + +# +# jffs2 rootfs image settings +# +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_MEDIA_FLASH_SELECT=y +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_MEDIA_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_PART_NAME="jffs2" +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_IMAGE_NAME="rootfs.jffs2" + +# +# dtb image settings +# +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_BOOTIMAGE_SELECT=y +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_FLASH_SELECT is not set +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_SD_SELECT is not set +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_ETHERNET_SELECT is not set +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_IMAGE_NAME="system.dtb" +CONFIG_SUBSYSTEM_ENDIAN_LITTLE=y + +# +# DTG Settings +# +CONFIG_SUBSYSTEM_MACHINE_NAME="zcu106-reva" +CONFIG_SUBSYSTEM_EXTRA_DT_FILES="" + +# +# Kernel Bootargs +# +CONFIG_SUBSYSTEM_BOOTARGS_AUTO=y +CONFIG_SUBSYSTEM_BOOTARGS_EARLYPRINTK=y +CONFIG_SUBSYSTEM_BOOTARGS_GENERATED=" earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/ram0 rw" +CONFIG_SUBSYSTEM_DEVICETREE_COMPILER_FLAGS="-@" +# CONFIG_SUBSYSTEM_DTB_OVERLAY is not set +# CONFIG_SUBSYSTEM_REMOVE_PL_DTB is not set + +# +# PMUFW Configuration +# +CONFIG_SUBSYSTEM_PMUFW_COMPILER_EXTRA_FLAGS="" + +# +# FSBL Configuration +# +CONFIG_SUBSYSTEM_FSBL_BSPCOMPILER_FLAGS="" +CONFIG_SUBSYSTEM_FSBL_COMPILER_EXTRA_FLAGS="" + +# +# ARM Trusted Firmware Configuration +# +# CONFIG_SUBSYSTEM_ATF_MEMORY_SETTINGS is not set +CONFIG_SUBSYSTEM_ATF_EXTRA_COMPILER_FLAGS="" +CONFIG_SUBSYSTEM_PRELOADED_BL33_BASE=0x10080000 +# CONFIG_SUBSYSTEM_ATF_DEBUG is not set + +# +# FPGA Manager +# +# CONFIG_SUBSYSTEM_FPGA_MANAGER is not set + +# +# u-boot Configuration +# +CONFIG_SUBSYSTEM_UBOOT_CONFIG_TARGET="" +# CONFIG_SUBSYSTEM_UBOOT_EXT_DTB is not set + +# +# Linux Configuration +# +CONFIG_SUBSYSTEM_LINUX_CONFIG_TARGET="" + +# +# Image Packaging Configuration +# +# CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set +CONFIG_SUBSYSTEM_ROOTFS_INITRD=y +# CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set +# CONFIG_SUBSYSTEM_ROOTFS_NFS is not set +# CONFIG_SUBSYSTEM_ROOTFS_EXT4 is not set +# CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set +CONFIG_SUBSYSTEM_INITRD_RAMDISK_LOADADDR=0x0 +CONFIG_SUBSYSTEM_INITRAMFS_IMAGE_NAME="petalinux-image-minimal" +CONFIG_SUBSYSTEM_UIMAGE_NAME="image.ub" +CONFIG_SUBSYSTEM_RFS_FORMATS="cpio cpio.gz cpio.gz.u-boot tar.gz jffs2" +CONFIG_SUBSYSTEM_DTB_PADDING_SIZE=0x1000 +CONFIG_SUBSYSTEM_COPY_TO_TFTPBOOT=y +CONFIG_SUBSYSTEM_TFTPBOOT_DIR="/tftpboot" + +# +# Firmware Version Configuration +# +CONFIG_SUBSYSTEM_HOSTNAME="petalinux-photonic" +CONFIG_SUBSYSTEM_PRODUCT="petalinux-photonic" +CONFIG_SUBSYSTEM_FW_VERSION="1.00" + +# +# Yocto Settings +# +CONFIG_YOCTO_MACHINE_NAME="zynqmp-generic" + +# +# TMPDIR Location +# +CONFIG_TMP_DIR_LOCATION="${PROOT}/build/tmp" + +# +# Devtool Workspace Location +# +CONFIG_DEVTOOL_WORKSPACE_LOCATION="${PROOT}/components/yocto/workspace" + +# +# Parallel thread execution +# +CONFIG_YOCTO_BB_NUMBER_THREADS="" +CONFIG_YOCTO_PARALLEL_MAKE="" + +# +# Add pre-mirror url +# +CONFIG_PRE_MIRROR_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/downloads" + +# +# Local sstate feeds settings +# +CONFIG_YOCTO_LOCAL_SSTATE_FEEDS_URL="" +CONFIG_YOCTO_NETWORK_SSTATE_FEEDS=y + +# +# Network sstate feeds URL +# +CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/aarch64/sstate-cache" +# CONFIG_YOCTO_BB_NO_NETWORK is not set + +# +# User Layers +# +CONFIG_USER_LAYER_0="" diff --git a/Petalinux/project-spec/configs/config.old b/Petalinux/project-spec/configs/config.old new file mode 100644 index 0000000..94faab3 --- /dev/null +++ b/Petalinux/project-spec/configs/config.old @@ -0,0 +1,305 @@ +# +# Automatically generated file; DO NOT EDIT. +# misc/config System Configuration +# +CONFIG_SUBSYSTEM_TYPE_LINUX=y +CONFIG_SYSTEM_ZYNQMP=y + +# +# Linux Components Selection +# +CONFIG_SUBSYSTEM_COMPONENT_DEVICE__TREE_NAME_DEVICE__TREE__GENERATOR=y +# CONFIG_SUBSYSTEM_COMPONENT_PRE_FSBL is not set +CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_FSBL=y +CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_NAME_ZYNQMP_FSBL=y +CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_PS_INIT=y +CONFIG_SUBSYSTEM_COMPONENT_PMU_FIRMWARE=y +CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_U__BOOT__XLNX=y +# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_REMOTE is not set +# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_EXT__LOCAL__SRC is not set +CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_ARM__TRUSTED__FIRMWARE=y +# CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_REMOTE is not set +# CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_EXT__LOCAL__SRC is not set +CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_LINUX__XLNX=y +# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_REMOTE is not set +# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_EXT__LOCAL__SRC is not set + +# +# Auto Config Settings +# +CONFIG_SUBSYSTEM_AUTOCONFIG_DEVICE__TREE=y +# CONFIG_SUBSYSTEM_DEVICE_TREE_MANUAL_INCLUDE is not set +# CONFIG_SUBSYSTEM_AUTOCONFIG_KERNEL is not set +# CONFIG_SUBSYSTEM_AUTOCONFIG_U__BOOT is not set +CONFIG_SUBSYSTEM_HARDWARE_AUTO=y +CONFIG_SUBSYSTEM_PROCESSOR0_IP_NAME="psu_cortexa53_0" +CONFIG_SUBSYSTEM_PROCESSOR_psu_cortexa53_0_SELECT=y +CONFIG_SUBSYSTEM_ARCH_AARCH64=y + +# +# Memory Settings +# +CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_SELECT=y +# CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_1_BANKLESS_SELECT is not set +# CONFIG_SUBSYSTEM_MEMORY_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_BASEADDR=0x0 +CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_SIZE=0x80000000 +CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_KERNEL_BASEADDR=0x0 +CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_U__BOOT_TEXTBASE_OFFSET=0x100000 +CONFIG_SUBSYSTEM_MEMORY_IP_NAME="PSU_DDR_0" + +# +# Serial Settings +# +# CONFIG_SUBSYSTEM_PMUFW_SERIAL_PSU_UART_1_SELECT is not set +CONFIG_SUBSYSTEM_PMUFW_SERIAL_PSU_UART_0_SELECT=y +# CONFIG_SUBSYSTEM_PMUFW_SERIAL_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_FSBL_SERIAL_PSU_UART_1_SELECT is not set +CONFIG_SUBSYSTEM_FSBL_SERIAL_PSU_UART_0_SELECT=y +# CONFIG_SUBSYSTEM_FSBL_SERIAL_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_ATF_SERIAL_PSU_UART_1_SELECT is not set +CONFIG_SUBSYSTEM_ATF_SERIAL_PSU_UART_0_SELECT=y +# CONFIG_SUBSYSTEM_ATF_SERIAL_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_SELECT is not set +CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_SELECT=y +# CONFIG_SUBSYSTEM_SERIAL_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_9600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_28800 is not set +CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_115200=y +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_230400 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_460800 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_921600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_9600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_28800 is not set +CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_115200=y +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_230400 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_460800 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_921600 is not set +CONFIG_SUBSYSTEM_SERIAL_PMUFW_IP_NAME="psu_uart_0" +CONFIG_SUBSYSTEM_SERIAL_FSBL_IP_NAME="psu_uart_0" +CONFIG_SUBSYSTEM_SERIAL_ATF_IP_NAME="cadence" +CONFIG_SUBSYSTEM_SERIAL_IP_NAME="psu_uart_0" + +# +# Ethernet Settings +# +CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_SELECT=y +# CONFIG_SUBSYSTEM_ETHERNET_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC_AUTO is not set +CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC="00:0a:35:00:22:01" +CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_USE_DHCP=y + +# +# Flash Settings +# +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_SELECT=y +# CONFIG_SUBSYSTEM_FLASH_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_FLASH__ADVANCED_AUTOCONFIG is not set + +# +# partition 0 +# +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_NAME="boot" +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0x01e00000 + +# +# partition 1 +# +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_NAME="bootenv" +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x40000 + +# +# partition 2 +# +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_NAME="kernel" +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x3c00000 + +# +# partition 3 +# +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="" +CONFIG_SUBSYSTEM_FLASH_IP_NAME="psu_qspi_0" + +# +# SD/SDIO Settings +# +CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y +# CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_SD_PSU_SD_1_SELECT=y + +# +# RTC Settings +# +CONFIG_SUBSYSTEM_RTC_PSU_RTC_SELECT=y +# CONFIG_SUBSYSTEM_RTC_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_SATA_PSU_SATA_SELECT=y +CONFIG_SUBSYSTEM_I2C_PSU_I2C_1_SELECT=y +CONFIG_SUBSYSTEM_I2C_PSU_I2C_0_SELECT=y +CONFIG_SUBSYSTEM_USB_PSU_USB_0_SELECT=y +CONFIG_SUBSYSTEM_DP_PSU_DP_SELECT=y +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG=y + +# +# boot image settings +# +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_FLASH_SELECT is not set +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_SD_SELECT=y +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_IMAGE_NAME="BOOT.BIN" + +# +# u-boot env partition settings +# +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_FLASH_SELECT=y +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_SD_SELECT is not set +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_PART_NAME="bootenv" + +# +# kernel image settings +# +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_FLASH_SELECT is not set +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_SD_SELECT=y +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_ETHERNET_SELECT is not set +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_IMAGE_NAME="image.ub" + +# +# jffs2 rootfs image settings +# +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_MEDIA_FLASH_SELECT=y +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_MEDIA_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_PART_NAME="jffs2" +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_IMAGE_NAME="rootfs.jffs2" + +# +# dtb image settings +# +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_BOOTIMAGE_SELECT=y +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_FLASH_SELECT is not set +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_SD_SELECT is not set +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_ETHERNET_SELECT is not set +# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_IMAGE_NAME="system.dtb" +CONFIG_SUBSYSTEM_ENDIAN_LITTLE=y + +# +# DTG Settings +# +CONFIG_SUBSYSTEM_MACHINE_NAME="zcu106-reva" +CONFIG_SUBSYSTEM_EXTRA_DT_FILES="" + +# +# Kernel Bootargs +# +CONFIG_SUBSYSTEM_BOOTARGS_AUTO=y +CONFIG_SUBSYSTEM_BOOTARGS_EARLYPRINTK=y + +CONFIG_SUBSYSTEM_DEVICETREE_COMPILER_FLAGS="-@" +# CONFIG_SUBSYSTEM_DTB_OVERLAY is not set +# CONFIG_SUBSYSTEM_REMOVE_PL_DTB is not set + +# +# PMUFW Configuration +# +CONFIG_SUBSYSTEM_PMUFW_COMPILER_EXTRA_FLAGS="" + +# +# FSBL Configuration +# +CONFIG_SUBSYSTEM_FSBL_BSPCOMPILER_FLAGS="" +CONFIG_SUBSYSTEM_FSBL_COMPILER_EXTRA_FLAGS="" + +# +# ARM Trusted Firmware Configuration +# +# CONFIG_SUBSYSTEM_ATF_MEMORY_SETTINGS is not set +CONFIG_SUBSYSTEM_ATF_EXTRA_COMPILER_FLAGS="" +CONFIG_SUBSYSTEM_PRELOADED_BL33_BASE=0x10080000 +# CONFIG_SUBSYSTEM_ATF_DEBUG is not set + +# +# FPGA Manager +# +# CONFIG_SUBSYSTEM_FPGA_MANAGER is not set + +# +# u-boot Configuration +# +CONFIG_SUBSYSTEM_UBOOT_CONFIG_TARGET="" +# CONFIG_SUBSYSTEM_UBOOT_EXT_DTB is not set + +# +# Linux Configuration +# +CONFIG_SUBSYSTEM_LINUX_CONFIG_TARGET="" + +# +# Image Packaging Configuration +# +# CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set +CONFIG_SUBSYSTEM_ROOTFS_INITRD=y +# CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set +# CONFIG_SUBSYSTEM_ROOTFS_NFS is not set +# CONFIG_SUBSYSTEM_ROOTFS_EXT4 is not set +# CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set +CONFIG_SUBSYSTEM_INITRD_RAMDISK_LOADADDR=0x0 +CONFIG_SUBSYSTEM_INITRAMFS_IMAGE_NAME="petalinux-image-minimal" +CONFIG_SUBSYSTEM_UIMAGE_NAME="image.ub" +CONFIG_SUBSYSTEM_RFS_FORMATS="cpio cpio.gz cpio.gz.u-boot tar.gz jffs2" +CONFIG_SUBSYSTEM_DTB_PADDING_SIZE=0x1000 +CONFIG_SUBSYSTEM_COPY_TO_TFTPBOOT=y +CONFIG_SUBSYSTEM_TFTPBOOT_DIR="/tftpboot" + +# +# Firmware Version Configuration +# +CONFIG_SUBSYSTEM_HOSTNAME="petalinux-photonic" +CONFIG_SUBSYSTEM_PRODUCT="petalinux-photonic" +CONFIG_SUBSYSTEM_FW_VERSION="1.00" + +# +# Yocto Settings +# +CONFIG_YOCTO_MACHINE_NAME="zynqmp-generic" + +# +# TMPDIR Location +# +CONFIG_TMP_DIR_LOCATION="${PROOT}/build/tmp" + +# +# Devtool Workspace Location +# +CONFIG_DEVTOOL_WORKSPACE_LOCATION="${PROOT}/components/yocto/workspace" + +# +# Parallel thread execution +# +CONFIG_YOCTO_BB_NUMBER_THREADS="" +CONFIG_YOCTO_PARALLEL_MAKE="" + +# +# Add pre-mirror url +# +CONFIG_PRE_MIRROR_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/downloads" + +# +# Local sstate feeds settings +# +CONFIG_YOCTO_LOCAL_SSTATE_FEEDS_URL="" +CONFIG_YOCTO_NETWORK_SSTATE_FEEDS=y + +# +# Network sstate feeds URL +# +CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/aarch64/sstate-cache" +# CONFIG_YOCTO_BB_NO_NETWORK is not set + +# +# User Layers +# +CONFIG_USER_LAYER_0="" +CONFIG_SUBSYSTEM_BOOTARGS_GENERATED=" earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/ram0 rw" diff --git a/Petalinux/project-spec/configs/init-ifupdown/interfaces b/Petalinux/project-spec/configs/init-ifupdown/interfaces new file mode 100644 index 0000000..0acf4cf --- /dev/null +++ b/Petalinux/project-spec/configs/init-ifupdown/interfaces @@ -0,0 +1,31 @@ +# /etc/network/interfaces -- configuration file for ifup(8), ifdown(8) + +# The loopback interface +auto lo +iface lo inet loopback + +# Wireless interfaces +iface wlan0 inet dhcp + wireless_mode managed + wireless_essid any + wpa-driver wext + wpa-conf /etc/wpa_supplicant.conf + +iface atml0 inet dhcp + +# Wired or wireless interfaces +auto eth0 +iface eth0 inet dhcp +iface eth1 inet dhcp + +# Ethernet/RNDIS gadget (g_ether) +# ... or on host side, usbnet and random hwaddr +iface usb0 inet static + address 192.168.7.2 + netmask 255.255.255.0 + network 192.168.7.0 + gateway 192.168.7.1 + +# Bluetooth networking +iface bnep0 inet dhcp + diff --git a/Petalinux/project-spec/configs/rootfs_config b/Petalinux/project-spec/configs/rootfs_config new file mode 100644 index 0000000..b2c47dc --- /dev/null +++ b/Petalinux/project-spec/configs/rootfs_config @@ -0,0 +1,4256 @@ +# +# Automatically generated file; DO NOT EDIT. +# Configuration +# +CONFIG_system-zynqmp=y + +# +# Filesystem Packages +# + +# +# admin +# + +# +# sudo +# +CONFIG_sudo=y +# CONFIG_sudo-dev is not set +# CONFIG_sudo-dbg is not set + +# +# audio +# + +# +# sox +# +# CONFIG_sox is not set +# CONFIG_sox-dbg is not set +# CONFIG_sox-dev is not set + +# +# base +# + +# +# base-files +# +# CONFIG_base-files is not set +# CONFIG_base-files-dbg is not set +# CONFIG_base-files-dev is not set + +# +# base-passwd +# +# CONFIG_base-passwd is not set +# CONFIG_base-passwd-dev is not set +# CONFIG_base-passwd-dbg is not set +# CONFIG_base-passwd-update is not set + +# +# bc +# +# CONFIG_bc is not set +# CONFIG_bc-dev is not set +# CONFIG_bc-dbg is not set + +# +# busybox +# +# CONFIG_busybox is not set +# CONFIG_busybox-inetd is not set +# CONFIG_busybox-dbg is not set +# CONFIG_busybox-syslog is not set +# CONFIG_busybox-hwclock is not set +# CONFIG_busybox-httpd is not set +# CONFIG_busybox-dev is not set +# CONFIG_busybox-udhcpc is not set +# CONFIG_busybox-udhcpd is not set + +# +# cpio +# +# CONFIG_cpio is not set +# CONFIG_cpio-dbg is not set +# CONFIG_cpio-dev is not set +# CONFIG_cpio-rmt is not set + +# +# dbus +# +# CONFIG_dbus is not set +# CONFIG_dbus-dbg is not set +# CONFIG_dbus-lib is not set +# CONFIG_dbus-dev is not set + +# +# dbus-glib +# +# CONFIG_dbus-glib is not set +# CONFIG_dbus-glib-dev is not set +# CONFIG_dbus-glib-bash-completion is not set +# CONFIG_dbus-glib-tests is not set +# CONFIG_dbus-glib-dbg is not set + +# +# dbus-wait +# +# CONFIG_dbus-wait is not set +# CONFIG_dbus-wait-dbg is not set +# CONFIG_dbus-wait-dev is not set + +# +# diffutils +# +# CONFIG_diffutils is not set +# CONFIG_diffutils-dbg is not set +# CONFIG_diffutils-dev is not set + +# +# dnf +# +# CONFIG_dnf is not set + +# +# e2fsprogs +# +# CONFIG_e2fsprogs is not set +# CONFIG_e2fsprogs-dev is not set +# CONFIG_e2fsprogs-mke2fs is not set +# CONFIG_e2fsprogs-dbg is not set +# CONFIG_e2fsprogs-resize2fs is not set +# CONFIG_e2fsprogs-tune2fs is not set +# CONFIG_libss is not set +# CONFIG_libcomerr is not set +# CONFIG_libext2fs is not set +# CONFIG_libe2p is not set +# CONFIG_e2fsprogs-e2fsck is not set +# CONFIG_e2fsprogs-badblocks is not set + +# +# ed +# +# CONFIG_ed is not set +# CONFIG_ed-dev is not set +# CONFIG_ed-dbg is not set + +# +# elfutils +# +# CONFIG_elfutils is not set +# CONFIG_libdw is not set +# CONFIG_elfutils-dev is not set +# CONFIG_elfutils-binutils is not set +# CONFIG_libelf is not set +# CONFIG_elfutils-dbg is not set +# CONFIG_libasm is not set + +# +# formfactor +# +# CONFIG_formfactor is not set +# CONFIG_formfactor-dbg is not set +# CONFIG_formfactor-dev is not set + +# +# fpga-manager-script +# +CONFIG_fpga-manager-script=y + +# +# haveged +# +CONFIG_haveged=y + +# +# i2c-tools +# +CONFIG_i2c-tools=y +# CONFIG_i2c-tools-dev is not set +# CONFIG_i2c-tools-misc is not set +# CONFIG_i2c-tools-dbg is not set + +# +# init-ifupdown +# +# CONFIG_init-ifupdown is not set +# CONFIG_init-ifupdown-dev is not set +# CONFIG_init-ifupdown-dbg is not set + +# +# initscripts +# +# CONFIG_initscripts is not set +# CONFIG_initscripts-functions is not set +# CONFIG_initscripts-dev is not set +# CONFIG_initscripts-dbg is not set + +# +# iproute2 +# +CONFIG_iproute2=y +# CONFIG_iproute2-ss is not set +# CONFIG_iproute2-dev is not set +# CONFIG_iproute2-dbg is not set +# CONFIG_iproute2-ifstat is not set +# CONFIG_iproute2-nstat is not set +# CONFIG_iproute2-tc is not set +# CONFIG_iproute2-bash-completion is not set +# CONFIG_iproute2-genl is not set +# CONFIG_iproute2-rtacct is not set +# CONFIG_iproute2-lnstat is not set + +# +# kmod +# +# CONFIG_kmod is not set +# CONFIG_kmod-bash-completion is not set +# CONFIG_libkmod is not set +# CONFIG_kmod-dbg is not set +# CONFIG_kmod-dev is not set + +# +# linuxptp +# +# CONFIG_linuxptp is not set +# CONFIG_linuxptp-dev is not set +# CONFIG_linuxptp-dbg is not set + +# +# modutils-initscripts +# +# CONFIG_modutils-initscripts is not set +# CONFIG_modutils-initscripts-dev is not set +# CONFIG_modutils-initscripts-dbg is not set + +# +# mtd-utils +# +CONFIG_mtd-utils=y +# CONFIG_mtd-utils-jffs2 is not set +# CONFIG_mtd-utils-misc is not set +# CONFIG_mtd-utils-dev is not set +# CONFIG_mtd-utils-ubifs is not set +# CONFIG_mtd-utils-dbg is not set + +# +# netbase +# +CONFIG_netbase=y +# CONFIG_netbase-dev is not set +# CONFIG_netbase-dbg is not set + +# +# opkg +# +# CONFIG_opkg is not set +# CONFIG_libopkg is not set +# CONFIG_opkg-dbg is not set +# CONFIG_opkg-dev is not set + +# +# opkg-utils +# +# CONFIG_opkg-utils is not set +# CONFIG_opkg-utils-dbg is not set +# CONFIG_update-alternatives-opkg is not set + +# +# procps +# +# CONFIG_procps is not set +# CONFIG_procps-dev is not set +# CONFIG_procps-dbg is not set + +# +# pseudo +# +# CONFIG_pseudo is not set +# CONFIG_pseudo-dev is not set +# CONFIG_pseudo-dbg is not set + +# +# psplash +# +# CONFIG_psplash is not set +# CONFIG_psplash-dbg is not set +# CONFIG_psplash-default is not set +# CONFIG_psplash-dev is not set + +# +# quota +# +# CONFIG_quota is not set +# CONFIG_quota-dbg is not set +# CONFIG_quota-dev is not set + +# +# shared-mime-info +# +# CONFIG_shared-mime-info is not set +# CONFIG_shared-mime-info-dev is not set +# CONFIG_shared-mime-info-dbg is not set +# CONFIG_shared-mime-info-data is not set + +# +# shell +# + +# +# bash +# +# CONFIG_bash is not set +# CONFIG_bash-dbg is not set +# CONFIG_bash-dev is not set + +# +# sysvinit +# +# CONFIG_sysvinit is not set +# CONFIG_sysvinit-dev is not set +# CONFIG_sysvinit-sulogin is not set +# CONFIG_sysvinit-dbg is not set +# CONFIG_sysvinit-pidof is not set + +# +# tar +# +# CONFIG_tar is not set +# CONFIG_tar-dev is not set +# CONFIG_tar-dbg is not set +# CONFIG_tar-rmt is not set + +# +# tzdata +# +# CONFIG_tzdata is not set +# CONFIG_tzdata-pacific is not set +# CONFIG_tzdata-posix is not set +# CONFIG_tzdata-antarctica is not set +# CONFIG_tzdata-africa is not set +# CONFIG_tzdata-europe is not set +# CONFIG_tzdata-americas is not set +# CONFIG_tzdata-right is not set +# CONFIG_tzdata-atlantic is not set +# CONFIG_tzdata-australia is not set +# CONFIG_tzdata-misc is not set +# CONFIG_tzdata-asia is not set +# CONFIG_tzdata-arctic is not set + +# +# update-rc.d +# +# CONFIG_update-rc.d is not set +# CONFIG_update-rc.d-dbg is not set +# CONFIG_update-rc.d-dev is not set + +# +# usbutils +# +# CONFIG_usbutils is not set +# CONFIG_usbutils-dev is not set +# CONFIG_usbutils-dbg is not set + +# +# util-linux +# +CONFIG_util-linux=y +# CONFIG_util-linux-sulogin is not set +# CONFIG_util-linux-losetup is not set +# CONFIG_util-linux-hwclock is not set +# CONFIG_util-linux-fsck is not set +# CONFIG_util-linux-uuidgen is not set +# CONFIG_util-linux-bash-completion is not set +# CONFIG_util-linux-fstrim is not set +# CONFIG_util-linux-cfdisk is not set +# CONFIG_util-linux-umount is not set +# CONFIG_util-linux-findfs is not set +# CONFIG_util-linux-agetty is not set +# CONFIG_util-linux-mount is not set +# CONFIG_util-linux-sfdisk is not set +# CONFIG_util-linux-swaponoff is not set +# CONFIG_util-linux-fsck.cramfs is not set +# CONFIG_util-linux-prlimit is not set +# CONFIG_util-linux-mcookie is not set +# CONFIG_util-linux-getopt is not set +# CONFIG_util-linux-blkid is not set +# CONFIG_util-linux-dev is not set +# CONFIG_util-linux-partx is not set +# CONFIG_util-linux-mkfs is not set +# CONFIG_util-linux-readprofile is not set +# CONFIG_util-linux-mountpoint is not set +# CONFIG_util-linux-fdisk is not set +# CONFIG_util-linux-lscpu is not set +# CONFIG_util-linux-dbg is not set +# CONFIG_util-linux-uuidd is not set +# CONFIG_util-linux-mkfs.cramfs is not set + +# +# utils +# + +# +# shadow +# +# CONFIG_shadow is not set +# CONFIG_shadow-base is not set +# CONFIG_shadow-dev is not set +# CONFIG_shadow-dbg is not set + +# +# xz +# +# CONFIG_xz is not set +# CONFIG_xz-dev is not set +# CONFIG_xz-dbg is not set +# CONFIG_liblzma is not set + +# +# baseutils +# + +# +# shadow-securetty +# +# CONFIG_shadow-securetty is not set +# CONFIG_shadow-securetty-dev is not set +# CONFIG_shadow-securetty-dbg is not set + +# +# benchmark +# + +# +# tests +# + +# +# dhrystone +# +# CONFIG_dhrystone is not set +# CONFIG_dhrystone-dev is not set +# CONFIG_dhrystone-dbg is not set + +# +# linpack +# +# CONFIG_linpack is not set +# CONFIG_linpack-dbg is not set +# CONFIG_linpack-dev is not set + +# +# whetstone +# +# CONFIG_whetstone is not set +# CONFIG_whetstone-dev is not set +# CONFIG_whetstone-dbg is not set + +# +# bootgen +# +# CONFIG_bootgen is not set +# CONFIG_bootgen-dev is not set +# CONFIG_bootgen-dbg is not set + +# +# bootloader +# + +# +# dtc +# +# CONFIG_dtc is not set +# CONFIG_dtc-dbg is not set +# CONFIG_dtc-misc is not set +# CONFIG_dtc-dev is not set + +# +# console +# + +# +# network +# + +# +# canutils +# +CONFIG_canutils=y +# CONFIG_canutils-dev is not set +# CONFIG_canutils-dbg is not set + +# +# can-utils +# +# CONFIG_can-utils is not set +# CONFIG_can-utils-dbg is not set +# CONFIG_can-utils-dev is not set + +# +# curl +# +# CONFIG_curl is not set +# CONFIG_curl-dbg is not set +# CONFIG_libcurl is not set +# CONFIG_curl-dev is not set + +# +# dropbear +# +# CONFIG_dropbear is not set +# CONFIG_dropbear-dev is not set +# CONFIG_dropbear-dbg is not set + +# +# ethtool +# +CONFIG_ethtool=y +# CONFIG_ethtool-dev is not set +# CONFIG_ethtool-dbg is not set + +# +# lrzsz +# +# CONFIG_lrzsz is not set +# CONFIG_lrzsz-dbg is not set +# CONFIG_lrzsz-dev is not set + +# +# mailx +# +# CONFIG_mailx is not set +# CONFIG_mailx-dbg is not set +# CONFIG_mailx-dev is not set + +# +# minicom +# +CONFIG_minicom=y +# CONFIG_minicom-dev is not set +# CONFIG_minicom-dbg is not set + +# +# nfs-utils +# +# CONFIG_nfs-utils is not set +# CONFIG_nfs-utils-stats is not set +# CONFIG_nfs-utils-dbg is not set +# CONFIG_nfs-utils-dev is not set +# CONFIG_nfs-utils-client is not set + +# +# openssh +# +# CONFIG_openssh is not set +# CONFIG_openssh-ssh is not set +# CONFIG_openssh-sftp is not set +CONFIG_openssh-sftp-server=y +# CONFIG_openssh-keygen is not set +# CONFIG_openssh-dbg is not set +# CONFIG_openssh-dev is not set +# CONFIG_openssh-misc is not set +# CONFIG_openssh-sshd is not set +# CONFIG_openssh-scp is not set + +# +# ppp +# +# CONFIG_ppp is not set +# CONFIG_ppp-dev is not set +# CONFIG_ppp-l2tp is not set +# CONFIG_ppp-minconn is not set +# CONFIG_ppp-winbind is not set +# CONFIG_ppp-dbg is not set +# CONFIG_ppp-oe is not set +# CONFIG_ppp-oa is not set +# CONFIG_ppp-radius is not set +# CONFIG_ppp-tools is not set +# CONFIG_ppp-password is not set + +# +# rpcbind +# +# CONFIG_rpcbind is not set +# CONFIG_rpcbind-dev is not set +# CONFIG_rpcbind-dbg is not set + +# +# rsync +# +# CONFIG_rsync is not set +# CONFIG_rsync-dev is not set +# CONFIG_rsync-dbg is not set + +# +# socat +# +CONFIG_socat=y +# CONFIG_socat-dev is not set +# CONFIG_socat-dbg is not set + +# +# subversion +# +# CONFIG_subversion is not set +# CONFIG_subversion-dev is not set +# CONFIG_subversion-dbg is not set + +# +# tcp-wrappers +# +# CONFIG_tcp-wrappers is not set +# CONFIG_libwrap is not set +# CONFIG_tcp-wrappers-dbg is not set +# CONFIG_libwrap-dev is not set + +# +# wget +# +CONFIG_wget=y +# CONFIG_wget-dev is not set +# CONFIG_wget-dbg is not set + +# +# tools +# + +# +# parted +# +# CONFIG_parted is not set +# CONFIG_parted-dev is not set +# CONFIG_parted-dbg is not set + +# +# xen +# +# CONFIG_xen-libxengnttab-dev is not set +# CONFIG_xen-xenpmd is not set +# CONFIG_xen-libxenstat is not set +# CONFIG_xen-base is not set +# CONFIG_xen-libxenevtchn-dev is not set +# CONFIG_xen-efi is not set +# CONFIG_xen-hypervisor is not set +# CONFIG_xen-xenstat is not set +# CONFIG_xen-xl-examples is not set +# CONFIG_xen-scripts-block is not set +# CONFIG_xen-libxlutil-dev is not set +# CONFIG_xen-libxenstat-dev is not set +# CONFIG_xen-scripts-common is not set +# CONFIG_xen-xenmon is not set +# CONFIG_xen-init-xenstore-dom is not set +# CONFIG_xen-remus is not set +# CONFIG_xen-libxenstore is not set +# CONFIG_xen-libxencall is not set +# CONFIG_xen-xencommons is not set +# CONFIG_xen-libxenstore-dev is not set +# CONFIG_xen-livepatch is not set +# CONFIG_xen-libxenlight-dev is not set +# CONFIG_xen-libxencall-dev is not set +# CONFIG_xen-console is not set +# CONFIG_xen-misc is not set +# CONFIG_xen-libxenvchan is not set +# CONFIG_xen-volatiles is not set +# CONFIG_xen-flask-tools is not set +# CONFIG_xen-dbg is not set +# CONFIG_xen-libxenlight is not set +# CONFIG_xen-libfsimage-dev is not set +# CONFIG_xen-xl is not set +# CONFIG_xen-libxenvchan-dev is not set +# CONFIG_xen-libxentoollog-dev is not set +# CONFIG_xen-fsimage is not set +# CONFIG_xen-libxentoollog is not set +# CONFIG_xen-libxenforeignmemory-dev is not set +# CONFIG_xen-libxengnttab is not set +# CONFIG_xen-xentrace is not set +# CONFIG_xen-libxenctrl is not set +# CONFIG_xen-libfsimage is not set +# CONFIG_xen-libxenforeignmemory is not set +# CONFIG_xen-xendomains is not set +# CONFIG_xen-dev is not set +# CONFIG_xen-xen-watchdog is not set +# CONFIG_xen-libxenguest is not set +# CONFIG_xen-libxlutil is not set +# CONFIG_xen-xenstore is not set +# CONFIG_xen-devd is not set +# CONFIG_xen-libxenevtchn is not set +# CONFIG_xen-libxenctrl-dev is not set +# CONFIG_xen-scripts-network is not set +# CONFIG_xen-libxenguest-dev is not set +# CONFIG_xen-xenstored is not set + +# +# utils +# + +# +# alsa-tools +# +# CONFIG_alsa-tools is not set +# CONFIG_alsa-tools-dbg is not set +# CONFIG_alsa-tools-dev is not set + +# +# alsa-utils +# +# CONFIG_alsa-utils is not set +# CONFIG_alsa-utils-alsatplg is not set +# CONFIG_alsa-utils-midi is not set +# CONFIG_alsa-utils-alsactl is not set +# CONFIG_alsa-utils-alsamixer is not set +# CONFIG_alsa-utils-amixer is not set +# CONFIG_alsa-utils-speakertest is not set +# CONFIG_alsa-utils-aplay is not set +# CONFIG_alsa-utils-dev is not set +# CONFIG_alsa-utils-aconnect is not set +# CONFIG_alsa-utils-alsaloop is not set +# CONFIG_alsa-utils-aseqdump is not set +# CONFIG_alsa-utils-iecset is not set +# CONFIG_alsa-utils-alsaucm is not set +# CONFIG_alsa-utils-dbg is not set +# CONFIG_alsa-utils-aseqnet is not set + +# +# bash-completion +# +# CONFIG_bash-completion is not set +# CONFIG_bash-completion-dbg is not set +# CONFIG_bash-completion-dev is not set +# CONFIG_bash-completion-extra is not set + +# +# bzip2 +# +# CONFIG_bzip2 is not set +# CONFIG_libbz2 is not set +# CONFIG_bzip2-dbg is not set +# CONFIG_bzip2-dev is not set + +# +# file +# +# CONFIG_file is not set +# CONFIG_file-dev is not set +# CONFIG_file-dbg is not set + +# +# findutils +# +# CONFIG_findutils is not set +# CONFIG_findutils-dbg is not set +# CONFIG_findutils-dev is not set + +# +# gawk +# +# CONFIG_gawk is not set +# CONFIG_gawk-dbg is not set +# CONFIG_gawk-dev is not set + +# +# git +# +# CONFIG_git is not set +# CONFIG_git-bash-completion is not set +# CONFIG_git-perltools is not set +# CONFIG_gitweb is not set +# CONFIG_git-dev is not set +# CONFIG_git-dbg is not set + +# +# grep +# +# CONFIG_grep is not set +# CONFIG_grep-dbg is not set +# CONFIG_grep-dev is not set + +# +# groff +# +# CONFIG_groff is not set +# CONFIG_groff-dev is not set +# CONFIG_groff-dbg is not set + +# +# gzip +# +# CONFIG_gzip is not set +# CONFIG_gzip-dev is not set +# CONFIG_gzip-dbg is not set + +# +# hdparm +# +# CONFIG_hdparm is not set +# CONFIG_hdparm-dev is not set +# CONFIG_wiper is not set +# CONFIG_hdparm-dbg is not set + +# +# less +# +# CONFIG_less is not set +# CONFIG_less-dbg is not set +# CONFIG_less-dev is not set + +# +# lmbench +# +# CONFIG_lmbench is not set +# CONFIG_lmbench-dbg is not set +# CONFIG_lmbench-dev is not set + +# +# ltp +# +# CONFIG_ltp is not set +# CONFIG_ltp-dev is not set +# CONFIG_ltp-dbg is not set + +# +# man +# +# CONFIG_man is not set + +# +# man-pages +# +# CONFIG_man-pages is not set +# CONFIG_man-pages-dev is not set +# CONFIG_man-pages-dbg is not set + +# +# mc +# +# CONFIG_mc is not set +# CONFIG_mc-fish is not set +# CONFIG_mc-dev is not set +# CONFIG_mc-dbg is not set +# CONFIG_mc-helpers is not set +# CONFIG_mc-helpers-perl is not set + +# +# pciutils +# +CONFIG_pciutils=y +# CONFIG_pciutils-dbg is not set +# CONFIG_libpci is not set +# CONFIG_pciutils-ids is not set +# CONFIG_pciutils-dev is not set + +# +# pkgconfig +# +# CONFIG_pkgconfig is not set +# CONFIG_pkgconfig-dev is not set +# CONFIG_pkgconfig-dbg is not set + +# +# screen +# +# CONFIG_screen is not set +# CONFIG_screen-dev is not set +# CONFIG_screen-dbg is not set + +# +# sed +# +# CONFIG_sed is not set +# CONFIG_sed-dev is not set +# CONFIG_sed-dbg is not set + +# +# setserial +# +# CONFIG_setserial is not set +# CONFIG_setserial-dbg is not set +# CONFIG_setserial-dev is not set + +# +# smartmontools +# +# CONFIG_smartmontools is not set +# CONFIG_smartmontools-dev is not set +# CONFIG_smartmontools-dbg is not set + +# +# strace +# +# CONFIG_strace is not set +# CONFIG_strace-dev is not set +# CONFIG_strace-dbg is not set + +# +# sysstat +# +# CONFIG_sysstat is not set +# CONFIG_sysstat-dbg is not set +# CONFIG_sysstat-dev is not set + +# +# texinfo +# +# CONFIG_texinfo is not set +# CONFIG_texinfo-dbg is not set +# CONFIG_texinfo-dev is not set +# CONFIG_info is not set + +# +# unzip +# +# CONFIG_unzip is not set +# CONFIG_unzip-dbg is not set +# CONFIG_unzip-dev is not set + +# +# vim +# +# CONFIG_vim is not set +# CONFIG_vim-help is not set +# CONFIG_vim-dbg is not set +# CONFIG_vim-vimrc is not set +# CONFIG_vim-dev is not set +# CONFIG_vim-tutor is not set +# CONFIG_vim-tools is not set +# CONFIG_vim-common is not set +# CONFIG_vim-syntax is not set + +# +# zip +# +# CONFIG_zip is not set +# CONFIG_zip-dev is not set +# CONFIG_zip-dbg is not set + +# +# devel +# + +# +# autoconf +# +# CONFIG_autoconf is not set +# CONFIG_autoconf-dbg is not set +# CONFIG_autoconf-dev is not set + +# +# automake +# +# CONFIG_automake is not set +# CONFIG_automake-dev is not set +# CONFIG_automake-dbg is not set + +# +# binutils +# +# CONFIG_binutils is not set +# CONFIG_binutils-dev is not set +# CONFIG_binutils-dbg is not set + +# +# bison +# +# CONFIG_bison is not set +# CONFIG_bison-dbg is not set +# CONFIG_bison-dev is not set + +# +# ccache +# +# CONFIG_ccache is not set +# CONFIG_ccache-dbg is not set +# CONFIG_ccache-dev is not set + +# +# diffstat +# +# CONFIG_diffstat is not set +# CONFIG_diffstat-dev is not set +# CONFIG_diffstat-dbg is not set + +# +# distcc +# +# CONFIG_distcc is not set +# CONFIG_distcc-dbg is not set +# CONFIG_distcc-dev is not set + +# +# expect +# +# CONFIG_expect is not set +# CONFIG_expect-dev is not set +# CONFIG_expect-dbg is not set + +# +# flex +# +# CONFIG_flex is not set +# CONFIG_flex-dbg is not set +# CONFIG_flex-dev is not set + +# +# gmp +# +# CONFIG_gmp is not set +# CONFIG_libgmpxx is not set +# CONFIG_gmp-dbg is not set +# CONFIG_gmp-dev is not set + +# +# gnu-config +# +# CONFIG_gnu-config is not set + +# +# gnu-efi +# +# CONFIG_gnu-efi is not set +# CONFIG_gnu-efi-dbg is not set +# CONFIG_gnu-efi-dev is not set + +# +# intltool +# +# CONFIG_intltool is not set +# CONFIG_intltool-dev is not set +# CONFIG_intltool-dbg is not set + +# +# libarchive +# +# CONFIG_libarchive is not set +# CONFIG_bsdcpio is not set +# CONFIG_libarchive-dbg is not set +# CONFIG_bsdtar is not set +# CONFIG_libarchive-dev is not set + +# +# libcheck +# +# CONFIG_libcheck is not set +# CONFIG_libcheck-dev is not set +# CONFIG_libcheck-dbg is not set + +# +# libpcre +# +# CONFIG_libpcre is not set +# CONFIG_libpcrecpp is not set +# CONFIG_libpcre-dbg is not set +# CONFIG_libpcreposix is not set +# CONFIG_libpcre-dev is not set +# CONFIG_pcregrep is not set +# CONFIG_pcretest is not set + +# +# lsof +# +# CONFIG_lsof is not set +# CONFIG_lsof-dev is not set +# CONFIG_lsof-dbg is not set + +# +# make +# +# CONFIG_make is not set +# CONFIG_make-dev is not set +# CONFIG_make-dbg is not set + +# +# mpfr +# +# CONFIG_mpfr is not set +# CONFIG_mpfr-dbg is not set +# CONFIG_mpfr-dev is not set + +# +# perl +# +# CONFIG_perl is not set +# CONFIG_perl-misc is not set +# CONFIG_perl-modules is not set +# CONFIG_perl-module-unicore is not set +# CONFIG_perl-dbg is not set +# CONFIG_perl-module-cpan is not set +# CONFIG_perl-pod is not set +# CONFIG_perl-dev is not set + +# +# python +# + +# +# python +# +# CONFIG_python is not set +# CONFIG_python-terminal is not set +# CONFIG_python-mailbox is not set +# CONFIG_python-logging is not set +# CONFIG_python-xml is not set +# CONFIG_python-hotshot is not set +# CONFIG_python-multiprocessing is not set +# CONFIG_python-threading is not set +# CONFIG_python-curses is not set +# CONFIG_python-mime is not set +# CONFIG_python-netclient is not set +# CONFIG_python-netserver is not set +# CONFIG_python-image is not set +# CONFIG_python-unixadmin is not set +# CONFIG_python-sqlite3 is not set +# CONFIG_python-pprint is not set +# CONFIG_python-contextlib is not set +# CONFIG_python-idle is not set +# CONFIG_python-pkgutil is not set +# CONFIG_python-crypt is not set +# CONFIG_python-zlib is not set +# CONFIG_python-fcntl is not set +# CONFIG_python-stringold is not set +# CONFIG_python-dev is not set +# CONFIG_libpython2 is not set +# CONFIG_python-smtpd is not set +# CONFIG_python-core is not set +# CONFIG_python-tkinter is not set +# CONFIG_python-codecs is not set +# CONFIG_python-compression is not set +# CONFIG_python-bsddb is not set +# CONFIG_python-subprocess is not set +# CONFIG_python-io is not set +# CONFIG_python-numbers is not set +# CONFIG_python-unittest is not set +# CONFIG_python-json is not set +# CONFIG_python-html is not set +# CONFIG_python-lang is not set +# CONFIG_python-compiler is not set +# CONFIG_python-shell is not set +# CONFIG_python-datetime is not set +# CONFIG_python-email is not set +# CONFIG_python-misc is not set +# CONFIG_python-resource is not set +# CONFIG_python-distutils is not set +# CONFIG_python-syslog is not set +# CONFIG_python-2to3 is not set +# CONFIG_python-pydoc is not set +# CONFIG_python-tests is not set +# CONFIG_python-modules is not set +# CONFIG_python-db is not set +# CONFIG_python-ctypes is not set +# CONFIG_python-re is not set +# CONFIG_python-audio is not set +# CONFIG_python-profile is not set +# CONFIG_python-dbg is not set +# CONFIG_python-mmap is not set +# CONFIG_python-compile is not set +# CONFIG_python-difflib is not set +# CONFIG_python-xmlrpc is not set +# CONFIG_python-argparse is not set +# CONFIG_python-math is not set +# CONFIG_python-robotparser is not set +# CONFIG_python-pickle is not set +# CONFIG_python-debugger is not set +# CONFIG_python-plistlib is not set +# CONFIG_python-gdbm is not set +# CONFIG_python-textutils is not set + +# +# python3-nose +# +# CONFIG_python3-nose is not set +# CONFIG_python3-nose-dbg is not set +# CONFIG_python3-nose-dev is not set + +# +# python3-numpy +# +# CONFIG_python3-numpy is not set +# CONFIG_python3-numpy-dbg is not set +# CONFIG_python3-numpy-dev is not set + +# +# python3-scons +# +# CONFIG_python3-scons is not set +# CONFIG_python3-scons-dev is not set +# CONFIG_python3-scons-dbg is not set + +# +# python3-dbus +# +# CONFIG_python3-dbus is not set +# CONFIG_python3-dbus-dev is not set +# CONFIG_python3-dbus-dbg is not set + +# +# python3-pygobject +# +# CONFIG_python3-pygobject is not set +# CONFIG_python3-pygobject-dbg is not set +# CONFIG_python3-pygobject-dev is not set + +# +# quilt +# +# CONFIG_quilt is not set +# CONFIG_quilt-dev is not set +# CONFIG_quilt-dbg is not set +# CONFIG_guards is not set + +# +# ruby +# + +# +# ruby +# +# CONFIG_ruby is not set +# CONFIG_ruby-dbg is not set +# CONFIG_ruby-dev is not set +# CONFIG_ruby-rdoc is not set + +# +# run-postinsts +# +CONFIG_run-postinsts=y +# CONFIG_run-postinsts-dbg is not set +# CONFIG_run-postinsts-dev is not set + +# +# swig +# +# CONFIG_swig is not set +# CONFIG_swig-dev is not set +# CONFIG_swig-dbg is not set + +# +# tcltk +# + +# +# tcl +# +# CONFIG_tcl is not set +# CONFIG_tcl-dbg is not set +# CONFIG_tcl-lib is not set +# CONFIG_tcl-dev is not set + +# +# vala +# +# CONFIG_vala is not set +# CONFIG_vala-dbg is not set +# CONFIG_vala-dev is not set + +# +# fonts +# + +# +# cantarell-fonts +# +# CONFIG_cantarell-fonts is not set +# CONFIG_cantarell-fonts-dbg is not set +# CONFIG_cantarell-fonts-dev is not set + +# +# kernel +# + +# +# userland +# + +# +# kexec-tools +# +# CONFIG_kexec-tools is not set +# CONFIG_kexec-tools-dbg is not set +# CONFIG_vmcore-dmesg is not set +# CONFIG_kdump is not set +# CONFIG_kexec is not set +# CONFIG_kexec-tools-dev is not set + +# +# libs +# + +# +# acl +# +# CONFIG_acl is not set +# CONFIG_acl-dev is not set +# CONFIG_libacl is not set +# CONFIG_acl-dbg is not set + +# +# apr +# +# CONFIG_apr is not set +# CONFIG_apr-dev is not set +# CONFIG_apr-dbg is not set + +# +# apr-util +# +# CONFIG_apr-util is not set +# CONFIG_apr-util-dev is not set +# CONFIG_apr-util-dbg is not set + +# +# attr +# +# CONFIG_attr is not set +# CONFIG_libattr is not set +# CONFIG_attr-dbg is not set +# CONFIG_attr-dev is not set + +# +# bluez5 +# +# CONFIG_bluez5 is not set +# CONFIG_bluez5-obex is not set +# CONFIG_bluez5-dev is not set +# CONFIG_bluez5-dbg is not set +# CONFIG_bluez5-noinst-tools is not set +# CONFIG_bluez5-testtools is not set + +# +# cairo +# +# CONFIG_cairo is not set +# CONFIG_cairo-dbg is not set +# CONFIG_cairo-dev is not set +# CONFIG_cairo-script-interpreter is not set +# CONFIG_cairo-perf-utils is not set +# CONFIG_cairo-gobject is not set + +# +# db +# +# CONFIG_db is not set +# CONFIG_db-bin is not set +# CONFIG_db-cxx is not set +# CONFIG_db-dbg is not set +# CONFIG_db-dev is not set + +# +# devel +# + +# +# libyaml +# +# CONFIG_libyaml is not set +# CONFIG_libyaml-dev is not set +# CONFIG_libyaml-dbg is not set + +# +# expat +# +# CONFIG_expat is not set +# CONFIG_expat-dev is not set +# CONFIG_expat-dbg is not set +# CONFIG_expat-bin is not set + +# +# faad2 +# +# CONFIG_faad2 is not set +# CONFIG_faad2-dev is not set +# CONFIG_faad2-dbg is not set + +# +# ffmpeg +# +# CONFIG_ffmpeg is not set +# CONFIG_ffmpeg-dbg is not set +# CONFIG_ffmpeg-dev is not set + +# +# flac +# +# CONFIG_flac is not set +# CONFIG_libflac is not set +# CONFIG_flac-dev is not set +# CONFIG_libflacPLUSPLUS is not set +# CONFIG_flac-dbg is not set + +# +# fontconfig +# +# CONFIG_fontconfig is not set +# CONFIG_fontconfig-utils is not set +# CONFIG_fontconfig-dev is not set +# CONFIG_fontconfig-dbg is not set + +# +# freetype +# +# CONFIG_freetype is not set +# CONFIG_freetype-dbg is not set +# CONFIG_freetype-dev is not set + +# +# gdbm +# +# CONFIG_gdbm is not set +# CONFIG_gdbm-dbg is not set +# CONFIG_gdbm-compat is not set +# CONFIG_gdbm-dev is not set +# CONFIG_gdbm-bin is not set + +# +# gdk-pixbuf +# +# CONFIG_gdk-pixbuf is not set +# CONFIG_gdk-pixbuf-xlib is not set +# CONFIG_gdk-pixbuf-dev is not set +# CONFIG_gdk-pixbuf-dbg is not set + +# +# gettext +# +# CONFIG_gettext is not set +# CONFIG_libgettextsrc is not set +# CONFIG_gettext-dbg is not set +# CONFIG_gettext-runtime is not set +# CONFIG_gettext-dev is not set +# CONFIG_libgettextlib is not set + +# +# glib-networking +# +# CONFIG_glib-networking is not set +# CONFIG_glib-networking-dev is not set +# CONFIG_glib-networking-dbg is not set + +# +# gobject-introspection +# +# CONFIG_gobject-introspection is not set +# CONFIG_gobject-introspection-dbg is not set +# CONFIG_gobject-introspection-dev is not set + +# +# gtk+ +# +# CONFIG_gtkPLUS is not set +# CONFIG_gtkPLUS-dev is not set +# CONFIG_libgail is not set +# CONFIG_gtkPLUS-dbg is not set +# CONFIG_gtk-demo is not set + +# +# gtk+3 +# +# CONFIG_gtkPLUS3 is not set +# CONFIG_gtkPLUS3-dev is not set +# CONFIG_gtkPLUS3-dbg is not set +# CONFIG_gtkPLUS3-demo is not set + +# +# harfbuzz +# +# CONFIG_harfbuzz is not set +# CONFIG_harfbuzz-dev is not set +# CONFIG_harfbuzz-bin is not set +# CONFIG_harfbuzz-icu-dev is not set +# CONFIG_harfbuzz-dbg is not set +# CONFIG_harfbuzz-icu is not set + +# +# libaio +# +# CONFIG_libaio is not set +# CONFIG_libaio-dev is not set +# CONFIG_libaio-dbg is not set + +# +# libcap +# +# CONFIG_libcap is not set +# CONFIG_libcap-bin is not set +# CONFIG_libcap-dbg is not set +# CONFIG_libcap-dev is not set + +# +# libcgroup +# +# CONFIG_libcgroup is not set +# CONFIG_libcgroup-dbg is not set +# CONFIG_libcgroup-dev is not set + +# +# libdaemon +# +# CONFIG_libdaemon is not set +# CONFIG_libdaemon-dbg is not set +# CONFIG_libdaemon-dev is not set + +# +# libdmx +# +# CONFIG_libdmx is not set +# CONFIG_libdmx-dbg is not set +# CONFIG_libdmx-dev is not set + +# +# libeigen +# +# CONFIG_libeigen-dev is not set +# CONFIG_libeigen-dbg is not set + +# +# libepoxy +# +# CONFIG_libepoxy is not set +# CONFIG_libepoxy-dev is not set +# CONFIG_libepoxy-dbg is not set + +# +# libevdev +# +# CONFIG_libevdev is not set +# CONFIG_libevdev-dev is not set +# CONFIG_libevdev-dbg is not set + +# +# libevent +# +# CONFIG_libevent is not set +# CONFIG_libevent-dbg is not set +# CONFIG_libevent-dev is not set + +# +# libexif +# +# CONFIG_libexif is not set +# CONFIG_libexif-dbg is not set +# CONFIG_libexif-dev is not set + +# +# libffi +# +# CONFIG_libffi is not set +# CONFIG_libffi-dbg is not set +# CONFIG_libffi-dev is not set + +# +# libfontenc +# +# CONFIG_libfontenc is not set +# CONFIG_libfontenc-dev is not set +# CONFIG_libfontenc-dbg is not set + +# +# libgcrypt +# +# CONFIG_libgcrypt is not set +# CONFIG_dumpsexp-dev is not set +# CONFIG_libgcrypt-dbg is not set +# CONFIG_libgcrypt-dev is not set + +# +# libgcc +# +# CONFIG_libgcc is not set +# CONFIG_libgcc-dbg is not set +# CONFIG_libgcc-dev is not set + +# +# libgpg-error +# +# CONFIG_libgpg-error is not set +# CONFIG_libgpg-error-dbg is not set +# CONFIG_libgpg-error-dev is not set + +# +# libgphoto2 +# +# CONFIG_libgphoto2 is not set +# CONFIG_libgphoto2-dbg is not set +# CONFIG_libgphoto2-camlibs is not set +# CONFIG_libgphoto2-dev is not set +# CONFIG_libgphoto2-bin is not set +# CONFIG_libgphotoport is not set + +# +# libgpiod +# +# CONFIG_libgpiod is not set +# CONFIG_libgpiod-dev is not set +# CONFIG_libgpiod-dbg is not set + +# +# libgudev +# +# CONFIG_libgudev is not set +# CONFIG_libgudev-dev is not set +# CONFIG_libgudev-dbg is not set + +# +# libhugetlbfs +# +# CONFIG_libhugetlbfs is not set +# CONFIG_libhugetlbfs-tests is not set +# CONFIG_libhugetlbfs-dbg is not set +# CONFIG_libhugetlbfs-dev is not set + +# +# libical +# +# CONFIG_libical is not set +# CONFIG_libical-dev is not set +# CONFIG_libical-dbg is not set + +# +# libice +# +# CONFIG_libice is not set +# CONFIG_libice-dbg is not set +# CONFIG_libice-dev is not set + +# +# libid3tag +# +# CONFIG_libid3tag is not set +# CONFIG_libid3tag-dev is not set +# CONFIG_libid3tag-dbg is not set + +# +# libidn +# +# CONFIG_libidn is not set +# CONFIG_libidn-dbg is not set +# CONFIG_idn is not set +# CONFIG_libidn-dev is not set + +# +# libinput +# +# CONFIG_libinput is not set +# CONFIG_libinput-dev is not set +# CONFIG_libinput-dbg is not set + +# +# libjpeg-turbo +# +# CONFIG_libjpeg-turbo is not set +# CONFIG_jpeg-tools is not set +# CONFIG_libturbojpeg is not set +# CONFIG_libjpeg-turbo-dbg is not set +# CONFIG_libjpeg-turbo-dev is not set + +# +# libmali-xlnx +# +# CONFIG_libmali-xlnx is not set +# CONFIG_libmali-xlnx-dbg is not set +# CONFIG_libmali-xlnx-dev is not set + +# +# libmetal +# +# CONFIG_libmetal is not set +# CONFIG_libmetal-dev is not set +# CONFIG_libmetal-dbg is not set +# CONFIG_libmetal-demos is not set + +# +# libmpc +# +# CONFIG_libmpc is not set +# CONFIG_libmpc-dbg is not set +# CONFIG_libmpc-dev is not set + +# +# libnet +# +# CONFIG_libnet is not set +# CONFIG_libnet-dbg is not set +# CONFIG_libnet-dev is not set + +# +# libnewt +# +# CONFIG_libnewt is not set +# CONFIG_libnewt-dev is not set +# CONFIG_libnewt-dbg is not set +# CONFIG_whiptail is not set + +# +# libnotify +# +# CONFIG_libnotify is not set +# CONFIG_libnotify-dev is not set +# CONFIG_libnotify-dbg is not set + +# +# libnss-mdns +# +# CONFIG_libnss-mdns is not set +# CONFIG_libnss-mdns-dbg is not set +# CONFIG_libnss-mdns-dev is not set + +# +# libogg +# +# CONFIG_libogg is not set +# CONFIG_libogg-dev is not set +# CONFIG_libogg-dbg is not set + +# +# libomxil +# +# CONFIG_libomxil is not set +# CONFIG_libomxil-dev is not set +# CONFIG_libomxil-dbg is not set + +# +# libpciaccess +# +# CONFIG_libpciaccess is not set +# CONFIG_libpciaccess-dev is not set +# CONFIG_libpciaccess-dbg is not set + +# +# libpng +# +# CONFIG_libpng is not set +# CONFIG_libpng-dbg is not set +# CONFIG_libpng-dev is not set +# CONFIG_libpng-tools is not set + +# +# libproxy +# +# CONFIG_libproxy is not set +# CONFIG_libproxy-dbg is not set +# CONFIG_libproxy-dev is not set + +# +# libsamplerate0 +# +# CONFIG_libsamplerate0 is not set +# CONFIG_libsamplerate0-dev is not set +# CONFIG_libsamplerate0-dbg is not set + +# +# libsecret +# +# CONFIG_libsecret is not set +# CONFIG_libsecret-dbg is not set +# CONFIG_libsecret-dev is not set + +# +# libsm +# +# CONFIG_libsm is not set +# CONFIG_libsm-dev is not set +# CONFIG_libsm-dbg is not set + +# +# libtasn1 +# +# CONFIG_libtasn1 is not set +# CONFIG_libtasn1-dbg is not set +# CONFIG_libtasn1-dev is not set +# CONFIG_libtasn1-bin is not set + +# +# libtheora +# +# CONFIG_libtheora is not set +# CONFIG_libtheora-dev is not set +# CONFIG_libtheora-dbg is not set + +# +# libtool +# +# CONFIG_libtool is not set +# CONFIG_libtool-dev is not set +# CONFIG_libltdl is not set +# CONFIG_libtool-dbg is not set + +# +# liburcu +# +# CONFIG_liburcu is not set +# CONFIG_liburcu-dbg is not set +# CONFIG_liburcu-dev is not set + +# +# libusb-compat +# +# CONFIG_libusb-compat is not set +# CONFIG_libusb-compat-dbg is not set +# CONFIG_libusb-compat-dev is not set + +# +# libusb1 +# +# CONFIG_libusb1 is not set +# CONFIG_libusb1-dev is not set +# CONFIG_libusb1-dbg is not set + +# +# libvorbis +# +# CONFIG_libvorbis is not set +# CONFIG_libvorbis-dev is not set +# CONFIG_libvorbis-dbg is not set + +# +# libwebp +# +# CONFIG_libwebp is not set +# CONFIG_libwebp-dbg is not set +# CONFIG_libwebp-bin is not set +# CONFIG_libwebp-dev is not set + +# +# libx11 +# +# CONFIG_libx11 is not set +# CONFIG_libx11-xcb is not set +# CONFIG_libx11-dev is not set +# CONFIG_libx11-dbg is not set + +# +# libxau +# +# CONFIG_libxau is not set +# CONFIG_libxau-dbg is not set +# CONFIG_libxau-dev is not set + +# +# libxcomposite +# +# CONFIG_libxcomposite is not set +# CONFIG_libxcomposite-dbg is not set +# CONFIG_libxcomposite-dev is not set + +# +# libxcursor +# +# CONFIG_libxcursor is not set +# CONFIG_libxcursor-dbg is not set +# CONFIG_libxcursor-dev is not set + +# +# libxdamage +# +# CONFIG_libxdamage is not set +# CONFIG_libxdamage-dbg is not set +# CONFIG_libxdamage-dev is not set + +# +# libxdmcp +# +# CONFIG_libxdmcp is not set +# CONFIG_libxdmcp-dbg is not set +# CONFIG_libxdmcp-dev is not set + +# +# libxext +# +# CONFIG_libxext is not set +# CONFIG_libxext-dev is not set +# CONFIG_libxext-dbg is not set + +# +# libxfixes +# +# CONFIG_libxfixes is not set +# CONFIG_libxfixes-dev is not set +# CONFIG_libxfixes-dbg is not set + +# +# libxfont +# +# CONFIG_libxfont is not set +# CONFIG_libxfont-dev is not set +# CONFIG_libxfont-dbg is not set + +# +# libxft +# +# CONFIG_libxft is not set +# CONFIG_libxft-dbg is not set +# CONFIG_libxft-dev is not set + +# +# libxi +# +# CONFIG_libxi is not set +# CONFIG_libxi-dbg is not set +# CONFIG_libxi-dev is not set + +# +# libxinerama +# +# CONFIG_libxinerama is not set +# CONFIG_libxinerama-dbg is not set +# CONFIG_libxinerama-dev is not set + +# +# libxkbcommon +# +# CONFIG_libxkbcommon is not set +# CONFIG_libxkbcommon-dev is not set +# CONFIG_libxkbcommon-dbg is not set + +# +# libxkbfile +# +# CONFIG_libxkbfile is not set +# CONFIG_libxkbfile-dbg is not set +# CONFIG_libxkbfile-dev is not set + +# +# libxml-parser-perl +# +# CONFIG_libxml-parser-perl is not set +# CONFIG_libxml-parser-perl-dev is not set +# CONFIG_libxml-parser-perl-dbg is not set + +# +# libxml2 +# +# CONFIG_libxml2 is not set +# CONFIG_libxml2-python is not set +# CONFIG_libxml2-dbg is not set +# CONFIG_libxml2-dev is not set + +# +# libxmu +# +# CONFIG_libxmu is not set +# CONFIG_libxmu-dbg is not set +# CONFIG_libxmuu is not set +# CONFIG_libxmu-dev is not set + +# +# libxrandr +# +# CONFIG_libxrandr is not set +# CONFIG_libxrandr-dbg is not set +# CONFIG_libxrandr-dev is not set + +# +# libxrender +# +# CONFIG_libxrender is not set +# CONFIG_libxrender-dev is not set +# CONFIG_libxrender-dbg is not set + +# +# libxres +# +# CONFIG_libxres is not set +# CONFIG_libxres-dbg is not set +# CONFIG_libxres-dev is not set + +# +# libxslt +# +# CONFIG_libxslt is not set +# CONFIG_libxslt-dbg is not set +# CONFIG_libxslt-bin is not set +# CONFIG_libxslt-dev is not set + +# +# libxt +# +# CONFIG_libxt is not set +# CONFIG_libxt-dev is not set +# CONFIG_libxt-dbg is not set + +# +# libxtst +# +# CONFIG_libxtst is not set +# CONFIG_libxtst-dbg is not set +# CONFIG_libxtst-dev is not set + +# +# libxv +# +# CONFIG_libxv is not set +# CONFIG_libxv-dbg is not set +# CONFIG_libxv-dev is not set + +# +# libxxf86vm +# +# CONFIG_libxxf86vm is not set +# CONFIG_libxxf86vm-dbg is not set +# CONFIG_libxxf86vm-dev is not set + +# +# lzo +# +# CONFIG_lzo is not set +# CONFIG_lzo-dbg is not set +# CONFIG_lzo-dev is not set + +# +# mtdev +# +# CONFIG_mtdev is not set +# CONFIG_mtdev-dbg is not set +# CONFIG_mtdev-dev is not set + +# +# multimedia +# + +# +# alsa-lib +# +# CONFIG_alsa-lib is not set +# CONFIG_alsa-server is not set +# CONFIG_libasound is not set +# CONFIG_alsa-conf is not set +# CONFIG_alsa-lib-dbg is not set +# CONFIG_alsa-conf-base is not set +# CONFIG_alsa-lib-dev is not set +# CONFIG_alsa-oss is not set + +# +# libsndfile1 +# +# CONFIG_libsndfile1 is not set +# CONFIG_libsndfile1-dev is not set +# CONFIG_libsndfile1-bin is not set +# CONFIG_libsndfile1-dbg is not set + +# +# pulseaudio +# +# CONFIG_pulseaudio is not set +# CONFIG_pulseaudio-module-console-kit is not set +# CONFIG_pulseaudio-bash-completion is not set +# CONFIG_libpulse is not set +# CONFIG_pulseaudio-misc is not set +# CONFIG_pulseaudio-dev is not set +# CONFIG_libpulse-simple is not set +# CONFIG_pulseaudio-dbg is not set +# CONFIG_libpulsecommon is not set +# CONFIG_pulseaudio-server is not set +# CONFIG_libpulsecore is not set +# CONFIG_libpulse-mainloop-glib is not set + +# +# taglib +# +# CONFIG_taglib is not set +# CONFIG_taglib-dev is not set +# CONFIG_taglib-dbg is not set +# CONFIG_taglib-c is not set + +# +# ncurses +# +# CONFIG_ncurses is not set +# CONFIG_ncurses-terminfo is not set +# CONFIG_ncurses-dev is not set +# CONFIG_ncurses-terminfo-base is not set +# CONFIG_ncurses-tools is not set +# CONFIG_ncurses-dbg is not set + +# +# neon +# +# CONFIG_neon is not set +# CONFIG_neon-dbg is not set +# CONFIG_neon-dev is not set + +# +# nettle +# +# CONFIG_nettle is not set +# CONFIG_nettle-dbg is not set +# CONFIG_nettle-dev is not set + +# +# network +# + +# +# libnl +# +# CONFIG_libnl is not set +# CONFIG_libnl-dbg is not set +# CONFIG_libnl-idiag is not set +# CONFIG_libnl-dev is not set +# CONFIG_libnl-cli is not set +# CONFIG_libnl-nf is not set +# CONFIG_libnl-route is not set +# CONFIG_libnl-xfrm is not set +# CONFIG_libnl-genl is not set + +# +# libpcap +# +# CONFIG_libpcap is not set +# CONFIG_libpcap-dev is not set +# CONFIG_libpcap-dbg is not set + +# +# libsocketcan +# +# CONFIG_libsocketcan is not set +# CONFIG_libsocketcan-dev is not set +# CONFIG_libsocketcan-dbg is not set + +# +# libtirpc +# +# CONFIG_libtirpc is not set +# CONFIG_libtirpc-dbg is not set +# CONFIG_libtirpc-dev is not set + +# +# openssl +# +# CONFIG_openssl is not set +# CONFIG_openssl-bin is not set +# CONFIG_openssl-misc is not set +# CONFIG_openssl-conf is not set +# CONFIG_openssl-dbg is not set +# CONFIG_libcrypto is not set +# CONFIG_openssl-dev is not set +# CONFIG_libssl is not set +# CONFIG_openssl-engines is not set + +# +# open-amp +# +# CONFIG_open-amp is not set +# CONFIG_open-amp-dev is not set +# CONFIG_open-amp-dbg is not set +# CONFIG_open-amp-demos is not set + +# +# opencv +# +# CONFIG_opencv is not set +# CONFIG_opencv-dbg is not set +# CONFIG_opencv-apps is not set +# CONFIG_opencv-dev is not set +# CONFIG_opencv-samples is not set + +# +# pango +# +# CONFIG_pango is not set +# CONFIG_pango-dev is not set +# CONFIG_pango-dbg is not set + +# +# popt +# +# CONFIG_popt is not set +# CONFIG_popt-dev is not set +# CONFIG_popt-dbg is not set + +# +# readline +# +# CONFIG_readline is not set +# CONFIG_readline-dev is not set +# CONFIG_readline-dbg is not set + +# +# sbc +# +# CONFIG_sbc is not set +# CONFIG_sbc-dev is not set +# CONFIG_sbc-dbg is not set + +# +# slang +# +# CONFIG_slang is not set +# CONFIG_slang-dev is not set +# CONFIG_slang-dbg is not set + +# +# speex +# +# CONFIG_speex is not set +# CONFIG_speex-dev is not set +# CONFIG_speex-dbg is not set + +# +# speexdsp +# +# CONFIG_speexdsp is not set +# CONFIG_speexdsp-dev is not set +# CONFIG_speexdsp-dbg is not set + +# +# sqlite3 +# +# CONFIG_sqlite3 is not set +# CONFIG_libsqlite3 is not set +# CONFIG_libsqlite3-dev is not set +# CONFIG_sqlite3-dbg is not set + +# +# startup-notification +# +# CONFIG_startup-notification is not set +# CONFIG_startup-notification-dev is not set +# CONFIG_startup-notification-dbg is not set + +# +# tremor +# +# CONFIG_tremor is not set +# CONFIG_tremor-dbg is not set +# CONFIG_tremor-dev is not set + +# +# which +# +# CONFIG_which is not set +# CONFIG_which-dev is not set +# CONFIG_which-dbg is not set + +# +# xrt +# +# CONFIG_xrt is not set +# CONFIG_xrt-dev is not set +# CONFIG_xrt-dbg is not set + +# +# zocl +# +# CONFIG_zocl is not set +# CONFIG_zocl-dev is not set +# CONFIG_zocl-dbg is not set + +# +# opencl-clhpp +# +# CONFIG_opencl-clhpp is not set + +# +# opencl-headers +# +# CONFIG_opencl-headers is not set + +# +# protobuf +# +# CONFIG_protobuf is not set + +# +# zlib +# +# CONFIG_zlib is not set +# CONFIG_zlib-dev is not set +# CONFIG_zlib-dbg is not set + +# +# misc +# + +# +# alsa-state +# +# CONFIG_alsa-state is not set +# CONFIG_alsa-state-dev is not set +# CONFIG_alsa-states is not set +# CONFIG_alsa-state-dbg is not set + +# +# alsa-utils-scripts +# +# CONFIG_alsa-utils-scripts is not set + +# +# apache2 +# +# CONFIG_apache2 is not set +# CONFIG_apache2-dbg is not set +# CONFIG_apache2-dev is not set + +# +# at-spi2-atk +# +# CONFIG_at-spi2-atk is not set +# CONFIG_at-spi2-atk-dbg is not set +# CONFIG_at-spi2-atk-dev is not set +# CONFIG_at-spi2-atk-gtk2 is not set +# CONFIG_at-spi2-atk-gnome is not set + +# +# at-spi2-core +# +# CONFIG_at-spi2-core is not set +# CONFIG_at-spi2-core-dev is not set +# CONFIG_at-spi2-core-dbg is not set + +# +# babeltrace +# +# CONFIG_babeltrace is not set +# CONFIG_babeltrace-dbg is not set +# CONFIG_babeltrace-dev is not set + +# +# blktool +# +# CONFIG_blktool is not set +# CONFIG_blktool-dbg is not set +# CONFIG_blktool-dev is not set + +# +# blktrace +# +# CONFIG_blktrace is not set +# CONFIG_blktrace-dbg is not set +# CONFIG_blktrace-dev is not set + +# +# ca-certificates +# +# CONFIG_ca-certificates is not set +# CONFIG_ca-certificates-dev is not set +# CONFIG_ca-certificates-dbg is not set + +# +# chkconfig +# +# CONFIG_chkconfig is not set +# CONFIG_chkconfig-alternatives is not set +# CONFIG_chkconfig-dbg is not set +# CONFIG_chkconfig-dev is not set + +# +# chrpath +# +# CONFIG_chrpath is not set +# CONFIG_chrpath-dev is not set +# CONFIG_chrpath-dbg is not set + +# +# connman +# +# CONFIG_connman is not set +# CONFIG_connman-tests is not set +# CONFIG_connman-dbg is not set +# CONFIG_connman-dev is not set +# CONFIG_connman-wait-online is not set +# CONFIG_connman-client is not set +# CONFIG_connman-tools is not set + +# +# connman-conf +# +# CONFIG_connman-conf-dbg is not set + +# +# consolekit +# +# CONFIG_consolekit is not set +# CONFIG_consolekit-dbg is not set +# CONFIG_consolekit-dev is not set + +# +# coreutils +# +# CONFIG_coreutils is not set +# CONFIG_coreutils-dbg is not set +# CONFIG_coreutils-dev is not set + +# +# cpufrequtils +# +# CONFIG_cpufrequtils is not set +# CONFIG_cpufrequtils-dbg is not set +# CONFIG_cpufrequtils-dev is not set + +# +# cryptodev-linux +# +# CONFIG_cryptodev-linux is not set +# CONFIG_cryptodev-linux-dev is not set +# CONFIG_cryptodev-linux-dbg is not set + +# +# dstat +# +# CONFIG_dstat is not set +# CONFIG_dstat-dev is not set +# CONFIG_dstat-dbg is not set + +# +# encodings +# +# CONFIG_encodings is not set +# CONFIG_encodings-dev is not set +# CONFIG_encodings-dbg is not set + +# +# epiphany +# +# CONFIG_epiphany is not set +# CONFIG_epiphany-dev is not set +# CONFIG_epiphany-dbg is not set + +# +# eudev +# +# CONFIG_eudev is not set +# CONFIG_libudev is not set +# CONFIG_eudev-hwdb is not set +# CONFIG_eudev-dev is not set +# CONFIG_eudev-dbg is not set +CONFIG_udev-extraconf=y + +# +# fbset +# +# CONFIG_fbset is not set +# CONFIG_fbset-dev is not set +# CONFIG_fbset-dbg is not set + +# +# fbset-modes +# +# CONFIG_fbset-modes is not set +# CONFIG_fbset-modes-dbg is not set +# CONFIG_fbset-modes-dev is not set + +# +# font-util +# +# CONFIG_font-util is not set +# CONFIG_font-util-dev is not set +# CONFIG_font-util-dbg is not set + +# +# gcc-runtime +# +# CONFIG_libstdcPLUSPLUS-dev is not set +# CONFIG_libstdcPLUSPLUS is not set + +# +# gcr +# +# CONFIG_gcr is not set +# CONFIG_gcr-dev is not set +# CONFIG_gcr-dbg is not set + +# +# gdb +# +# CONFIG_gdb is not set +# CONFIG_gdb-dev is not set +# CONFIG_gdbserver is not set +# CONFIG_gdb-dbg is not set + +# +# glib-2.0 +# +# CONFIG_glib-2.0 is not set +# CONFIG_glib-2.0-dbg is not set +# CONFIG_glib-2.0-dev is not set +# CONFIG_glib-2.0-codegen is not set +# CONFIG_glib-2.0-bash-completion is not set +# CONFIG_glib-2.0-utils is not set + +# +# glibc +# +# CONFIG_glibc is not set +# CONFIG_glibc-dev is not set +# CONFIG_glibc-dbg is not set +# CONFIG_ldd is not set + +# +# gnome-desktop-testing +# +# CONFIG_gnome-desktop-testing is not set +# CONFIG_gnome-desktop-testing-dbg is not set +# CONFIG_gnome-desktop-testing-dev is not set + +# +# gnutls +# +# CONFIG_gnutls is not set +# CONFIG_gnutls-bin is not set +# CONFIG_gnutls-xx is not set +# CONFIG_gnutls-dbg is not set +# CONFIG_gnutls-openssl is not set +# CONFIG_gnutls-dev is not set + +# +# gsettings-desktop-schemas +# +# CONFIG_gsettings-desktop-schemas is not set +# CONFIG_gsettings-desktop-schemas-dev is not set +# CONFIG_gsettings-desktop-schemas-dbg is not set + +# +# gst-player +# +# CONFIG_gst-player is not set + +# +# gstreamer1.0-meta-base +# +# CONFIG_gstreamer1.0-meta-base is not set +# CONFIG_gstreamer1.0-meta-video is not set +# CONFIG_gstreamer1.0-meta-video-dbg is not set +# CONFIG_gstreamer1.0-meta-debug-dev is not set +# CONFIG_gstreamer1.0-meta-x11-base-dev is not set +# CONFIG_gstreamer1.0-meta-audio-dbg is not set +# CONFIG_gstreamer1.0-meta-audio is not set +# CONFIG_gstreamer1.0-meta-x11-base is not set +# CONFIG_gstreamer1.0-meta-video-dev is not set +# CONFIG_gstreamer1.0-meta-x11-base-dbg is not set +# CONFIG_gstreamer1.0-meta-base-dev is not set +# CONFIG_gstreamer1.0-meta-base-dbg is not set +# CONFIG_gstreamer1.0-meta-debug is not set +# CONFIG_gstreamer1.0-meta-audio-dev is not set +# CONFIG_gstreamer1.0-meta-debug-dbg is not set + +# +# gstreamer1.0-plugins-bad +# +# CONFIG_gstreamer1.0-plugins-bad is not set +# CONFIG_gstreamer1.0-plugins-bad-meta is not set +# CONFIG_gstreamer1.0-plugins-bad-dev is not set +# CONFIG_gstreamer1.0-plugins-bad-dbg is not set + +# +# gstreamer1.0-plugins-base +# +# CONFIG_gstreamer1.0-plugins-base is not set +# CONFIG_gstreamer1.0-plugins-base-apps is not set +# CONFIG_gstreamer1.0-plugins-base-dev is not set +# CONFIG_gstreamer1.0-plugins-base-dbg is not set +# CONFIG_gstreamer1.0-plugins-base-meta is not set + +# +# gstreamer1.0-plugins-good +# +# CONFIG_gstreamer1.0-plugins-good is not set +# CONFIG_gstreamer1.0-plugins-good-dev is not set +# CONFIG_gstreamer1.0-plugins-good-dbg is not set +# CONFIG_gstreamer1.0-plugins-good-meta is not set + +# +# hicolor-icon-theme +# +# CONFIG_hicolor-icon-theme is not set +# CONFIG_hicolor-icon-theme-dev is not set +# CONFIG_hicolor-icon-theme-dbg is not set + +# +# hdmi-module +# +# CONFIG_kernel-module-hdmi is not set + +# +# icu +# +# CONFIG_icu is not set +# CONFIG_icu-dbg is not set +# CONFIG_icu-dev is not set +# CONFIG_libicudata is not set +# CONFIG_libicuio is not set +# CONFIG_libicui18n is not set +# CONFIG_libicuuc is not set +# CONFIG_libicutu is not set + +# +# iotop +# +# CONFIG_iotop is not set +# CONFIG_iotop-dev is not set +# CONFIG_iotop-dbg is not set + +# +# iptables +# +# CONFIG_iptables is not set +# CONFIG_iptables-dev is not set +# CONFIG_iptables-dbg is not set + +# +# iptraf +# +# CONFIG_iptraf is not set + +# +# iso-codes +# +# CONFIG_iso-codes is not set +# CONFIG_iso-codes-dbg is not set +# CONFIG_iso-codes-dev is not set + +# +# json-c +# +# CONFIG_json-c is not set +# CONFIG_json-c-dev is not set +# CONFIG_json-c-dbg is not set + +# +# l3afpad +# +# CONFIG_l3afpad is not set +# CONFIG_l3afpad-dev is not set +# CONFIG_l3afpad-dbg is not set + +# +# lttng-ust +# +# CONFIG_lttng-ust is not set +# CONFIG_lttng-ust-dev is not set +# CONFIG_lttng-ust-dbg is not set +# CONFIG_lttng-ust-bin is not set + +# +# m4 +# +# CONFIG_m4 is not set +# CONFIG_m4-dev is not set +# CONFIG_m4-dbg is not set + +# +# matchbox-config-gtk +# +# CONFIG_matchbox-config-gtk is not set +# CONFIG_matchbox-config-gtk-dbg is not set +# CONFIG_matchbox-config-gtk-dev is not set + +# +# matchbox-panel-2 +# +# CONFIG_matchbox-panel-2 is not set +# CONFIG_matchbox-panel-2-dbg is not set +# CONFIG_matchbox-panel-2-dev is not set + +# +# mdadm +# +# CONFIG_mdadm is not set +# CONFIG_mdadm-dbg is not set +# CONFIG_mdadm-dev is not set + +# +# mesa-gl +# +# CONFIG_mesa-gl-dev is not set +# CONFIG_libgl-mesa is not set +# CONFIG_mesa-megadriver is not set +# CONFIG_libglapi-dev is not set +# CONFIG_libglapi is not set +# CONFIG_libgl-mesa-dev is not set +# CONFIG_mesa-gl-dbg is not set + +# +# mkfontdir +# +# CONFIG_mkfontdir is not set +# CONFIG_mkfontdir-dbg is not set +# CONFIG_mkfontdir-dev is not set + +# +# mkfontscale +# +# CONFIG_mkfontscale is not set +# CONFIG_mkfontscale-dbg is not set +# CONFIG_mkfontscale-dev is not set + +# +# net-tools +# +# CONFIG_net-tools is not set +# CONFIG_net-tools-dbg is not set +# CONFIG_net-tools-dev is not set + +# +# nicstat +# +# CONFIG_nicstat is not set +# CONFIG_nicstat-dbg is not set +# CONFIG_nicstat-dev is not set + +# +# ofono +# +# CONFIG_ofono is not set +# CONFIG_ofono-dbg is not set +# CONFIG_ofono-dev is not set +# CONFIG_ofono-tests is not set + +# +# openamp-fw-echo-testd +# +# CONFIG_openamp-fw-echo-testd is not set +# CONFIG_openamp-fw-echo-testd-dev is not set +# CONFIG_openamp-fw-echo-testd-dbg is not set + +# +# openamp-fw-mat-muld +# +# CONFIG_openamp-fw-mat-muld is not set +# CONFIG_openamp-fw-mat-muld-dev is not set +# CONFIG_openamp-fw-mat-muld-dbg is not set + +# +# openamp-fw-rpc-demo +# +# CONFIG_openamp-fw-rpc-demo is not set +# CONFIG_openamp-fw-rpc-demo-dbg is not set +# CONFIG_openamp-fw-rpc-demo-dev is not set + +# +# opkg-arch-config +# +# CONFIG_opkg-arch-config is not set +# CONFIG_opkg-arch-config-dbg is not set +# CONFIG_opkg-arch-config-dev is not set + +# +# orc +# +# CONFIG_orc is not set +# CONFIG_orc-dbg is not set +# CONFIG_orc-dev is not set + +# +# p11-kit +# +# CONFIG_p11-kit is not set +# CONFIG_p11-kit-dbg is not set +# CONFIG_p11-kit-dev is not set + +# +# packagegroup-core-boot +# +CONFIG_packagegroup-core-boot=y +# CONFIG_packagegroup-core-boot-dev is not set +# CONFIG_packagegroup-core-boot-dbg is not set + +# +# packagegroup-core-buildessential +# +# CONFIG_packagegroup-core-buildessential is not set +# CONFIG_packagegroup-core-buildessential-dbg is not set +# CONFIG_packagegroup-core-buildessential-dev is not set + +# +# packagegroup-core-sdk +# +# CONFIG_packagegroup-core-sdk is not set +# CONFIG_packagegroup-core-sdk-dbg is not set +# CONFIG_packagegroup-core-sdk-dev is not set + +# +# packagegroup-core-ssh-dropbear +# +CONFIG_packagegroup-core-ssh-dropbear=y +# CONFIG_packagegroup-core-ssh-dropbear-dev is not set +# CONFIG_packagegroup-core-ssh-dropbear-dbg is not set + +# +# packagegroup-core-standalone-sdk-target +# +# CONFIG_packagegroup-core-standalone-sdk-target is not set +# CONFIG_packagegroup-core-standalone-sdk-target-dbg is not set +# CONFIG_packagegroup-core-standalone-sdk-target-dev is not set + +# +# packagegroup-core-tools-debug +# +# CONFIG_packagegroup-core-tools-debug is not set +# CONFIG_packagegroup-core-tools-debug-dev is not set +# CONFIG_packagegroup-core-tools-debug-dbg is not set + +# +# packagegroup-core-tools-profile +# +# CONFIG_packagegroup-core-tools-profile is not set +# CONFIG_packagegroup-core-tools-profile-dev is not set +# CONFIG_packagegroup-core-tools-profile-dbg is not set + +# +# packagegroup-core-tools-testapps +# +# CONFIG_packagegroup-core-tools-testapps is not set +# CONFIG_packagegroup-core-tools-testapps-dev is not set +# CONFIG_packagegroup-core-tools-testapps-dbg is not set + +# +# packagegroup-core-x11 +# +# CONFIG_packagegroup-core-x11 is not set +# CONFIG_packagegroup-core-x11-utils-dbg is not set +# CONFIG_packagegroup-core-x11-utils is not set +# CONFIG_packagegroup-core-x11-utils-dev is not set +# CONFIG_packagegroup-core-x11-dev is not set +# CONFIG_packagegroup-core-x11-dbg is not set + +# +# packagegroup-core-x11-base +# +# CONFIG_packagegroup-core-x11-base is not set +# CONFIG_packagegroup-core-x11-base-dev is not set +# CONFIG_packagegroup-core-x11-base-dbg is not set + +# +# packagegroup-core-x11-xserver +# +# CONFIG_packagegroup-core-x11-xserver is not set +# CONFIG_packagegroup-core-x11-xserver-dev is not set +# CONFIG_packagegroup-core-x11-xserver-dbg is not set + +# +# packagegroup-self-hosted +# +# CONFIG_packagegroup-self-hosted is not set +# CONFIG_packagegroup-self-hosted-debug-dbg is not set +# CONFIG_packagegroup-self-hosted-dev is not set +# CONFIG_packagegroup-self-hosted-debug is not set +# CONFIG_packagegroup-self-hosted-sdk is not set +# CONFIG_packagegroup-self-hosted-extended-dbg is not set +# CONFIG_packagegroup-self-hosted-graphics-dbg is not set +# CONFIG_packagegroup-self-hosted-extended is not set +# CONFIG_packagegroup-self-hosted-host-tools-dev is not set +# CONFIG_packagegroup-self-hosted-debug-dev is not set +# CONFIG_packagegroup-self-hosted-sdk-dbg is not set +# CONFIG_packagegroup-self-hosted-sdk-dev is not set +# CONFIG_packagegroup-self-hosted-extended-dev is not set +# CONFIG_packagegroup-self-hosted-graphics is not set +# CONFIG_packagegroup-self-hosted-host-tools-dbg is not set +# CONFIG_packagegroup-self-hosted-dbg is not set +# CONFIG_packagegroup-self-hosted-host-tools is not set +# CONFIG_packagegroup-self-hosted-graphics-dev is not set + +# +# perf +# +# CONFIG_perf is not set +# CONFIG_perf-python is not set +# CONFIG_perf-dbg is not set +# CONFIG_perf-dev is not set +# CONFIG_perf-tests is not set + +# +# pixman +# +# CONFIG_pixman is not set +# CONFIG_pixman-dbg is not set +# CONFIG_pixman-dev is not set + +# +# powertop +# +# CONFIG_powertop is not set +# CONFIG_powertop-dbg is not set +# CONFIG_powertop-dev is not set + +# +# ptest-runner +# +# CONFIG_ptest-runner is not set +# CONFIG_ptest-runner-dev is not set +# CONFIG_ptest-runner-dbg is not set + +# +# python3 +# +# CONFIG_python3 is not set +# CONFIG_python3-crypt is not set +# CONFIG_python3-unixadmin is not set +# CONFIG_python3-io is not set +# CONFIG_python3-pydoc is not set +# CONFIG_python3-codecs is not set +# CONFIG_python3-pprint is not set +# CONFIG_python3-datetime is not set +# CONFIG_python3-2to3 is not set +# CONFIG_python3-modules is not set +# CONFIG_python3-xml is not set +# CONFIG_python3-numbers is not set +# CONFIG_python3-pyvenv is not set +# CONFIG_python3-tests is not set +# CONFIG_python3-netclient is not set +# CONFIG_python3-netserver is not set +# CONFIG_python3-math is not set +# CONFIG_python3-asyncio is not set +# CONFIG_python3-tkinter is not set +# CONFIG_python3-compression is not set +# CONFIG_python3-gdbm is not set +# CONFIG_python3-idle is not set +# CONFIG_python3-core is not set +# CONFIG_python3-smtpd is not set +# CONFIG_python3-resource is not set +# CONFIG_python3-terminal is not set +# CONFIG_python3-shell is not set +# CONFIG_python3-db is not set +# CONFIG_python3-threading is not set +# CONFIG_python3-email is not set +# CONFIG_python3-stringold is not set +# CONFIG_python3-unittest is not set +# CONFIG_python3-misc is not set +# CONFIG_python3-mailbox is not set +# CONFIG_python3-pkgutil is not set +# CONFIG_python3-mmap is not set +# CONFIG_python3-json is not set +# CONFIG_python3-audio is not set +# CONFIG_python3-distutils is not set +# CONFIG_python3-mime is not set +# CONFIG_python3-multiprocessing is not set +# CONFIG_python3-html is not set +# CONFIG_python3-image is not set +# CONFIG_python3-difflib is not set +# CONFIG_python3-dev is not set +# CONFIG_python3-syslog is not set +# CONFIG_python3-curses is not set +# CONFIG_libpython3 is not set +# CONFIG_python3-logging is not set +# CONFIG_python3-profile is not set +# CONFIG_python3-xmlrpc is not set +# CONFIG_python3-ctypes is not set +# CONFIG_python3-sqlite3 is not set +# CONFIG_python3-fcntl is not set +# CONFIG_python3-compile is not set +# CONFIG_python3-pickle is not set +# CONFIG_python3-dbg is not set +# CONFIG_python3-debugger is not set + +# +# python3-async +# +# CONFIG_python3-async is not set +# CONFIG_python3-async-dbg is not set +# CONFIG_python3-async-dev is not set + +# +# python3-git +# +# CONFIG_python3-git is not set +# CONFIG_python3-git-dev is not set +# CONFIG_python3-git-dbg is not set + +# +# python3-gitdb +# +# CONFIG_python3-gitdb is not set +# CONFIG_python3-gitdb-dev is not set +# CONFIG_python3-gitdb-dbg is not set + +# +# python3-setuptools +# +# CONFIG_python3-setuptools is not set +# CONFIG_python3-setuptools-dbg is not set +# CONFIG_python3-setuptools-dev is not set + +# +# python3-smmap +# +# CONFIG_python3-smmap is not set +# CONFIG_python3-smmap-dev is not set +# CONFIG_python3-smmap-dbg is not set + +# +# qemu +# +# CONFIG_qemu is not set +# CONFIG_qemu-dev is not set +# CONFIG_qemu-dbg is not set + +# +# qtbase +# +# CONFIG_qtbase is not set +# CONFIG_qtbase-plugins is not set +# CONFIG_qtbase-dev is not set +# CONFIG_qtbase-dbg is not set +# CONFIG_qtbase-tools is not set +# CONFIG_qtbase-examples is not set +# CONFIG_qtbase-mkspecs is not set + +# +# qtcharts +# +# CONFIG_qtcharts is not set +# CONFIG_qtcharts-qmlplugins is not set +# CONFIG_qtcharts-mkspecs is not set +# CONFIG_qtcharts-dbg is not set +# CONFIG_qtcharts-examples is not set +# CONFIG_qtcharts-dev is not set +# CONFIG_qtcharts-qmldesigner is not set + +# +# qtconnectivity +# +# CONFIG_qtconnectivity is not set +# CONFIG_qtconnectivity-qmlplugins is not set +# CONFIG_qtconnectivity-tools is not set +# CONFIG_qtconnectivity-mkspecs is not set +# CONFIG_qtconnectivity-examples is not set +# CONFIG_qtconnectivity-dev is not set +# CONFIG_qtconnectivity-dbg is not set + +# +# qtdeclarative +# +# CONFIG_qtdeclarative is not set +# CONFIG_qtdeclarative-tools is not set +# CONFIG_qtdeclarative-examples is not set +# CONFIG_qtdeclarative-mkspecs is not set +# CONFIG_qtdeclarative-dbg is not set +# CONFIG_qtdeclarative-qmlplugins is not set +# CONFIG_qtdeclarative-dev is not set + +# +# qtenginio +# +# CONFIG_qtenginio is not set +# CONFIG_qtenginio-qmlplugins is not set +# CONFIG_qtenginio-dev is not set +# CONFIG_qtenginio-dbg is not set +# CONFIG_qtenginio-examples is not set +# CONFIG_qtenginio-mkspecs is not set + +# +# qtimageformats +# +# CONFIG_qtimageformats is not set +# CONFIG_qtimageformats-dev is not set +# CONFIG_qtimageformats-dbg is not set +# CONFIG_qtimageformats-plugins is not set + +# +# qtlocation +# +# CONFIG_qtlocation is not set +# CONFIG_qtlocation-qmlplugins is not set +# CONFIG_qtlocation-examples is not set +# CONFIG_qtlocation-mkspecs is not set +# CONFIG_qtlocation-dev is not set +# CONFIG_qtlocation-plugins is not set +# CONFIG_qtlocation-dbg is not set + +# +# qtmultimedia +# +# CONFIG_qtmultimedia is not set +# CONFIG_qtmultimedia-dbg is not set +# CONFIG_qtmultimedia-plugins is not set +# CONFIG_qtmultimedia-mkspecs is not set +# CONFIG_qtmultimedia-dev is not set +# CONFIG_qtmultimedia-examples is not set +# CONFIG_qtmultimedia-qmlplugins is not set + +# +# qtquickcontrols +# +# CONFIG_qtquickcontrols is not set +# CONFIG_qtquickcontrols-dev is not set +# CONFIG_qtquickcontrols-examples is not set +# CONFIG_qtquickcontrols-qmldesigner is not set +# CONFIG_qtquickcontrols-qmlplugins is not set +# CONFIG_qtquickcontrols-dbg is not set + +# +# qtscript +# +# CONFIG_qtscript is not set +# CONFIG_qtscript-dbg is not set +# CONFIG_qtscript-mkspecs is not set +# CONFIG_qtscript-dev is not set +# CONFIG_qtscript-examples is not set + +# +# qtsensors +# +# CONFIG_qtsensors is not set +# CONFIG_qtsensors-examples is not set +# CONFIG_qtsensors-qmlplugins is not set +# CONFIG_qtsensors-mkspecs is not set +# CONFIG_qtsensors-plugins is not set +# CONFIG_qtsensors-dbg is not set +# CONFIG_qtsensors-dev is not set + +# +# qtserialport +# +# CONFIG_qtserialport is not set +# CONFIG_qtserialport-mkspecs is not set +# CONFIG_qtserialport-dev is not set +# CONFIG_qtserialport-dbg is not set +# CONFIG_qtserialport-examples is not set + +# +# qtsvg +# +# CONFIG_qtsvg is not set +# CONFIG_qtsvg-dev is not set +# CONFIG_qtsvg-dbg is not set +# CONFIG_qtsvg-examples is not set +# CONFIG_qtsvg-mkspecs is not set +# CONFIG_qtsvg-plugins is not set + +# +# qtsystems +# +# CONFIG_qtsystems is not set +# CONFIG_qtsystems-dev is not set +# CONFIG_qtsystems-mkspecs is not set +# CONFIG_qtsystems-qmlplugins is not set +# CONFIG_qtsystems-dbg is not set +# CONFIG_qtsystems-tools is not set +# CONFIG_qtsystems-examples is not set + +# +# qttools +# +# CONFIG_qttools is not set +# CONFIG_qttools-dbg is not set +# CONFIG_qttools-dev is not set +# CONFIG_qttools-examples is not set +# CONFIG_qttools-tools is not set +# CONFIG_qttools-mkspecs is not set +# CONFIG_qttools-plugins is not set + +# +# qttranslations +# +# CONFIG_qttranslations is not set +# CONFIG_qttranslations-qtwebengine is not set +# CONFIG_qttranslations-qthelp is not set +# CONFIG_qttranslations-qtbase is not set +# CONFIG_qttranslations-dbg is not set +# CONFIG_qttranslations-dev is not set +# CONFIG_qttranslations-qtscript is not set +# CONFIG_qttranslations-qtdeclarative is not set +# CONFIG_qttranslations-assistant is not set +# CONFIG_qttranslations-qtwebsockets is not set +# CONFIG_qttranslations-linguist is not set +# CONFIG_qttranslations-qtserialport is not set +# CONFIG_qttranslations-qtmultimedia is not set +# CONFIG_qttranslations-qtconnectivity is not set +# CONFIG_qttranslations-qtlocation is not set +# CONFIG_qttranslations-qtxmlpatterns is not set +# CONFIG_qttranslations-qtquickcontrols is not set +# CONFIG_qttranslations-designer is not set +# CONFIG_qttranslations-qtquickcontrols2 is not set + +# +# qtwebchannel +# +# CONFIG_qtwebchannel is not set +# CONFIG_qtwebchannel-mkspecs is not set +# CONFIG_qtwebchannel-dbg is not set +# CONFIG_qtwebchannel-examples is not set +# CONFIG_qtwebchannel-qmlplugins is not set +# CONFIG_qtwebchannel-dev is not set + +# +# qtwebkit +# +# CONFIG_qtwebkit is not set +# CONFIG_qtwebkit-qmlplugins is not set +# CONFIG_qtwebkit-mkspecs is not set +# CONFIG_qtwebkit-dbg is not set +# CONFIG_qtwebkit-dev is not set + +# +# qtwebsockets +# +# CONFIG_qtwebsockets is not set +# CONFIG_qtwebsockets-examples is not set +# CONFIG_qtwebsockets-qmlplugins is not set +# CONFIG_qtwebsockets-dbg is not set +# CONFIG_qtwebsockets-dev is not set +# CONFIG_qtwebsockets-mkspecs is not set + +# +# qtxmlpatterns +# +# CONFIG_qtxmlpatterns is not set +# CONFIG_qtxmlpatterns-dev is not set +# CONFIG_qtxmlpatterns-mkspecs is not set +# CONFIG_qtxmlpatterns-examples is not set +# CONFIG_qtxmlpatterns-dbg is not set +# CONFIG_qtxmlpatterns-tools is not set + +# +# rgb +# +# CONFIG_rgb is not set +# CONFIG_rgb-dev is not set +# CONFIG_rgb-dbg is not set + +# +# rpm +# +# CONFIG_rpm is not set +# CONFIG_rpm-build is not set +# CONFIG_rpm-dbg is not set +# CONFIG_rpm-dev is not set + +# +# rpmsg-echo-test +# +# CONFIG_rpmsg-echo-test is not set +# CONFIG_rpmsg-echo-test-dbg is not set +# CONFIG_rpmsg-echo-test-dev is not set + +# +# rpmsg-mat-mul +# +# CONFIG_rpmsg-mat-mul is not set +# CONFIG_rpmsg-mat-mul-dev is not set +# CONFIG_rpmsg-mat-mul-dbg is not set + +# +# rpmsg-proxy-app +# +# CONFIG_rpmsg-proxy-app is not set +# CONFIG_rpmsg-proxy-app-dbg is not set +# CONFIG_rpmsg-proxy-app-dev is not set + +# +# serf +# +# CONFIG_serf is not set +# CONFIG_serf-dev is not set +# CONFIG_serf-dbg is not set + +# +# sysfsutils +# +# CONFIG_sysfsutils is not set +# CONFIG_libsysfs is not set +# CONFIG_sysfsutils-dbg is not set +# CONFIG_sysfsutils-dev is not set + +# +# sysvinit-inittab +# +# CONFIG_sysvinit-inittab is not set +# CONFIG_sysvinit-inittab-dev is not set +# CONFIG_sysvinit-inittab-dbg is not set + +# +# tbb +# +# CONFIG_tbb is not set +# CONFIG_tbb-dbg is not set +# CONFIG_tbb-dev is not set + +# +# tcf-agent +# +CONFIG_tcf-agent=y +# CONFIG_tcf-agent-dev is not set +# CONFIG_tcf-agent-dbg is not set + +# +# texi2html +# +# CONFIG_texi2html is not set +# CONFIG_texi2html-dev is not set +# CONFIG_texi2html-dbg is not set + +# +# tiff +# +# CONFIG_tiff is not set +# CONFIG_tiffxx is not set +# CONFIG_tiff-dbg is not set +# CONFIG_tiff-utils is not set +# CONFIG_tiff-dev is not set + +# +# util-macros +# +# CONFIG_util-macros is not set +# CONFIG_util-macros-dbg is not set +# CONFIG_util-macros-dev is not set + +# +# v4l-utils +# +# CONFIG_v4l-utils is not set +# CONFIG_libv4l is not set +# CONFIG_ir-keytable is not set +# CONFIG_media-ctl is not set +# CONFIG_v4l-utils-dbg is not set +# CONFIG_rc-keymaps is not set +# CONFIG_v4l-utils-dev is not set +# CONFIG_libv4l-dev is not set + +# +# valgrind +# +# CONFIG_valgrind is not set +# CONFIG_valgrind-dbg is not set +# CONFIG_valgrind-dev is not set + +# +# vte +# +# CONFIG_vte is not set +# CONFIG_vte-dbg is not set +# CONFIG_vte-dev is not set +# CONFIG_libvte is not set + +# +# watchdog +# +# CONFIG_watchdog is not set +# CONFIG_watchdog-dbg is not set +# CONFIG_watchdog-dev is not set +# CONFIG_watchdog-keepalive is not set + +# +# watchdog-config +# +# CONFIG_watchdog-config is not set +# CONFIG_watchdog-config-dbg is not set +# CONFIG_watchdog-config-dev is not set + +# +# watchdog-init +# +CONFIG_watchdog-init=y + +# +# webkitgtk +# +# CONFIG_webkitgtk is not set +# CONFIG_webkitgtk-dbg is not set +# CONFIG_webkitgtk-dev is not set + +# +# x11perf +# +# CONFIG_x11perf is not set +# CONFIG_x11perf-dev is not set +# CONFIG_x11perf-dbg is not set + +# +# x264 +# +# CONFIG_x264 is not set +# CONFIG_x264-dev is not set +# CONFIG_x264-dbg is not set +# CONFIG_x264-bin is not set + +# +# xauth +# +# CONFIG_xauth is not set +# CONFIG_xauth-dbg is not set +# CONFIG_xauth-dev is not set + +# +# xcb-util-image +# +# CONFIG_xcb-util-image is not set +# CONFIG_xcb-util-image-dbg is not set +# CONFIG_xcb-util-image-dev is not set + +# +# xcb-util-keysyms +# +# CONFIG_xcb-util-keysyms is not set +# CONFIG_xcb-util-keysyms-dev is not set +# CONFIG_xcb-util-keysyms-dbg is not set + +# +# xcb-util-renderutil +# +# CONFIG_xcb-util-renderutil is not set +# CONFIG_xcb-util-renderutil-dev is not set +# CONFIG_xcb-util-renderutil-dbg is not set + +# +# xcb-util-wm +# +# CONFIG_xcb-util-wm is not set +# CONFIG_xcb-util-wm-dbg is not set +# CONFIG_xcb-util-wm-dev is not set + +# +# xdg-utils +# +# CONFIG_xdg-utils is not set +# CONFIG_xdg-utils-dev is not set +# CONFIG_xdg-utils-dbg is not set + +# +# xdpyinfo +# +# CONFIG_xdpyinfo is not set +# CONFIG_xdpyinfo-dev is not set +# CONFIG_xdpyinfo-dbg is not set + +# +# xf86-input-evdev +# +# CONFIG_xf86-input-evdev is not set +# CONFIG_xf86-input-evdev-dbg is not set +# CONFIG_xf86-input-evdev-dev is not set + +# +# xf86-input-keyboard +# +# CONFIG_xf86-input-keyboard is not set +# CONFIG_xf86-input-keyboard-dev is not set +# CONFIG_xf86-input-keyboard-dbg is not set + +# +# xf86-input-mouse +# +# CONFIG_xf86-input-mouse is not set +# CONFIG_xf86-input-mouse-dbg is not set +# CONFIG_xf86-input-mouse-dev is not set + +# +# xf86-video-armsoc +# +# CONFIG_xf86-video-armsoc is not set +# CONFIG_xf86-video-armsoc-dbg is not set +# CONFIG_xf86-video-armsoc-dev is not set + +# +# xf86-video-fbdev +# +# CONFIG_xf86-video-fbdev is not set +# CONFIG_xf86-video-fbdev-dbg is not set +# CONFIG_xf86-video-fbdev-dev is not set + +# +# xhost +# +# CONFIG_xhost is not set +# CONFIG_xhost-dbg is not set +# CONFIG_xhost-dev is not set + +# +# xinetd +# +# CONFIG_xinetd is not set +# CONFIG_xinetd-dbg is not set +# CONFIG_xinetd-dev is not set + +# +# xinit +# +# CONFIG_xinit is not set +# CONFIG_xinit-dbg is not set +# CONFIG_xinit-dev is not set + +# +# xinput +# +# CONFIG_xinput is not set +# CONFIG_xinput-dev is not set +# CONFIG_xinput-dbg is not set + +# +# xinput-calibrator +# +# CONFIG_xinput-calibrator is not set +# CONFIG_xinput-calibrator-dev is not set +# CONFIG_xinput-calibrator-dbg is not set + +# +# xkbcomp +# +# CONFIG_xkbcomp is not set +# CONFIG_xkbcomp-dbg is not set +# CONFIG_xkbcomp-dev is not set + +# +# xmodmap +# +# CONFIG_xmodmap is not set +# CONFIG_xmodmap-dbg is not set +# CONFIG_xmodmap-dev is not set + +# +# xprop +# +# CONFIG_xprop is not set +# CONFIG_xprop-dbg is not set +# CONFIG_xprop-dev is not set + +# +# xrandr +# +# CONFIG_xrandr is not set +# CONFIG_xrandr-dbg is not set +# CONFIG_xrandr-dev is not set + +# +# xserver-common +# +# CONFIG_xserver-common is not set +# CONFIG_xserver-common-dbg is not set +# CONFIG_xserver-common-dev is not set + +# +# xset +# +# CONFIG_xset is not set +# CONFIG_xset-dev is not set +# CONFIG_xset-dbg is not set + +# +# xtrans +# +# CONFIG_xtrans-dev is not set +# CONFIG_xtrans-dbg is not set + +# +# xwininfo +# +# CONFIG_xwininfo is not set +# CONFIG_xwininfo-dev is not set +# CONFIG_xwininfo-dbg is not set + +# +# yajl +# +# CONFIG_yajl is not set +# CONFIG_yajl-dev is not set +# CONFIG_yajl-dbg is not set +# CONFIG_yajl-bin is not set + +# +# yavta +# +# CONFIG_yavta is not set +# CONFIG_yavta-dbg is not set +# CONFIG_yavta-dev is not set + +# +# multimedia +# + +# +# alsa-plugins +# +# CONFIG_alsa-plugins is not set +# CONFIG_alsa-plugins-dbg is not set +# CONFIG_alsa-plugins-dev is not set +# CONFIG_alsa-plugins-pulseaudio-conf is not set + +# +# gstreamer1.0 +# +# CONFIG_gstreamer1.0 is not set +# CONFIG_gstreamer1.0-dev is not set +# CONFIG_gstreamer1.0-bash-completion is not set +# CONFIG_gstreamer1.0-dbg is not set + +# +# gstreamer1.0-omx +# +# CONFIG_gstreamer1.0-omx is not set +# CONFIG_gstreamer1.0-omx-dbg is not set +# CONFIG_gstreamer1.0-omx-dev is not set + +# +# gstreamer1.0-rtsp-server +# +# CONFIG_gstreamer1.0-rtsp-server is not set +# CONFIG_gstreamer1.0-rtsp-server-dbg is not set +# CONFIG_gstreamer1.0-rtsp-server-dev is not set +# CONFIG_gstreamer1.0-rtsp-server-meta is not set + +# +# net +# + +# +# bridge-utils +# +CONFIG_bridge-utils=y +# CONFIG_bridge-utils-dbg is not set +# CONFIG_bridge-utils-dev is not set + +# +# net-snmp +# +# CONFIG_net-snmp is not set +# CONFIG_net-snmp-server-snmptrapd is not set +# CONFIG_net-snmp-libs is not set +# CONFIG_net-snmp-dev is not set +# CONFIG_net-snmp-client is not set +# CONFIG_net-snmp-mibs is not set +# CONFIG_net-snmp-dbg is not set +# CONFIG_net-snmp-server-snmpd is not set +# CONFIG_net-snmp-server is not set + +# +# netcat +# +CONFIG_netcat=y +# CONFIG_netcat-dbg is not set +# CONFIG_netcat-dev is not set + +# +# tcpdump +# +CONFIG_tcpdump=y +# CONFIG_tcpdump-dev is not set +# CONFIG_tcpdump-dbg is not set + +# +# network +# + +# +# avahi +# +# CONFIG_libavahi-client is not set +# CONFIG_libavahi-glib is not set +# CONFIG_avahi-utils is not set +# CONFIG_libavahi-common is not set +# CONFIG_avahi-dnsconfd is not set +# CONFIG_avahi-daemon is not set +# CONFIG_avahi-autoipd is not set +# CONFIG_libavahi-gobject is not set +# CONFIG_libavahi-core is not set +# CONFIG_avahi-dbg is not set +# CONFIG_avahi-dev is not set + +# +# mobile-broadband-provider-info +# +# CONFIG_mobile-broadband-provider-info is not set +# CONFIG_mobile-broadband-provider-info-dbg is not set +# CONFIG_mobile-broadband-provider-info-dev is not set + +# +# wpa-supplicant +# +# CONFIG_wpa-supplicant is not set +# CONFIG_wpa-supplicant-passphrase is not set +# CONFIG_wpa-supplicant-dev is not set +# CONFIG_wpa-supplicant-dbg is not set +# CONFIG_wpa-supplicant-cli is not set + +# +# optional +# + +# +# libatomic-ops +# +# CONFIG_libatomic-ops is not set +# CONFIG_libatomic-ops-dev is not set +# CONFIG_libatomic-ops-dbg is not set + +# +# mtools +# +# CONFIG_mtools is not set +# CONFIG_mtools-dev is not set +# CONFIG_mtools-dbg is not set + +# +# power management +# +CONFIG_hellopm=y + +# +# utils +# + +# +# dosfstools +# +# CONFIG_dosfstools is not set +# CONFIG_dosfstools-dev is not set +# CONFIG_dosfstools-dbg is not set + +# +# patch +# +# CONFIG_patch is not set +# CONFIG_patch-dbg is not set +# CONFIG_patch-dev is not set + +# +# resize-part +# +# CONFIG_resize-part is not set +# CONFIG_resize-part-dbg is not set +# CONFIG_resize-part-dev is not set + +# +# x11 +# + +# +# base +# + +# +# libdrm +# +# CONFIG_libdrm is not set +# CONFIG_libdrm-tests is not set +# CONFIG_libdrm-drivers is not set +# CONFIG_libdrm-amdgpu is not set +# CONFIG_libdrm-nouveau is not set +# CONFIG_libdrm-dev is not set +# CONFIG_libdrm-freedreno is not set +# CONFIG_libdrm-radeon is not set +# CONFIG_libdrm-kms is not set +# CONFIG_libdrm-dbg is not set +# CONFIG_libdrm-omap is not set + +# +# xcursor-transparent-theme +# +# CONFIG_xcursor-transparent-theme is not set +# CONFIG_xcursor-transparent-theme-dev is not set +# CONFIG_xcursor-transparent-theme-dbg is not set + +# +# xserver-xf86-config +# +# CONFIG_xserver-xf86-config is not set +# CONFIG_xserver-xf86-config-dev is not set +# CONFIG_xserver-xf86-config-dbg is not set + +# +# xserver-xorg +# +# CONFIG_xserver-xorg is not set +# CONFIG_xserver-xorg-module-exa is not set +# CONFIG_xserver-xorg-module-libint10 is not set +# CONFIG_xserver-xorg-extension-record is not set +# CONFIG_xserver-xorg-dev is not set +# CONFIG_xserver-xorg-extension-dri2 is not set +# CONFIG_xserver-xorg-extension-dri is not set +# CONFIG_xserver-xorg-module-libwfb is not set +# CONFIG_xf86-video-modesetting is not set +# CONFIG_xserver-xorg-extension-dbe is not set +# CONFIG_xserver-xorg-extension-glx is not set +# CONFIG_xserver-xorg-xvfb is not set +# CONFIG_xserver-xorg-utils is not set +# CONFIG_xserver-xorg-dbg is not set +# CONFIG_xserver-xorg-extension-extmod is not set + +# +# builder +# +# CONFIG_builder is not set +# CONFIG_builder-dbg is not set +# CONFIG_builder-dev is not set + +# +# fonts +# + +# +# liberation-fonts +# +# CONFIG_liberation-fonts is not set + +# +# glew +# +# CONFIG_glew is not set +# CONFIG_glew-bin is not set +# CONFIG_glew-dev is not set +# CONFIG_glew-dbg is not set + +# +# gnome +# + +# +# adwaita-icon-theme +# +# CONFIG_adwaita-icon-theme is not set +# CONFIG_adwaita-icon-theme-hires is not set +# CONFIG_adwaita-icon-theme-symbolic is not set +# CONFIG_adwaita-icon-theme-cursors is not set +# CONFIG_adwaita-icon-theme-symbolic-hires is not set + +# +# gconf +# +# CONFIG_gconf is not set +# CONFIG_gconf-dev is not set +# CONFIG_gconf-dbg is not set + +# +# gnome-common +# +# CONFIG_gnome-common is not set +# CONFIG_gnome-common-dev is not set +# CONFIG_gnome-common-dbg is not set + +# +# gnome-desktop3 +# +# CONFIG_gnome-desktop3 is not set +# CONFIG_gnome-desktop3-dbg is not set +# CONFIG_gnome-desktop3-dev is not set +# CONFIG_libgnome-desktop3 is not set + +# +# gnome-themes-standard +# +# CONFIG_gnome-themes-standard-dev is not set +# CONFIG_gnome-themes-standard-dbg is not set +# CONFIG_gnome-theme-adwaita is not set + +# +# libsoup-2.4 +# +# CONFIG_libsoup-2.4 is not set +# CONFIG_libsoup-2.4-dev is not set +# CONFIG_libsoup-2.4-dbg is not set + +# +# libglu +# +# CONFIG_libglu is not set +# CONFIG_libglu-dev is not set +# CONFIG_libglu-dbg is not set + +# +# libs +# + +# +# atk +# +# CONFIG_atk is not set +# CONFIG_atk-dev is not set +# CONFIG_atk-dbg is not set + +# +# libfm +# +# CONFIG_libfm is not set +# CONFIG_libfm-mime is not set +# CONFIG_libfm-dev is not set +# CONFIG_libfm-dbg is not set + +# +# libfm-extra +# +# CONFIG_libfm-extra is not set +# CONFIG_libfm-extra-dev is not set +# CONFIG_libfm-extra-dbg is not set + +# +# libmatchbox +# +# CONFIG_libmatchbox is not set +# CONFIG_libmatchbox-dev is not set +# CONFIG_libmatchbox-dbg is not set + +# +# libpthread-stubs +# +# CONFIG_libpthread-stubs-dbg is not set +# CONFIG_libpthread-stubs-dev is not set + +# +# libwnck3 +# +# CONFIG_libwnck3 is not set +# CONFIG_libwnck3-dev is not set +# CONFIG_libwnck3-dbg is not set + +# +# libxcb +# +# CONFIG_libxcb is not set +# CONFIG_libxcb-dev is not set +# CONFIG_libxcb-dbg is not set + +# +# menu-cache +# +# CONFIG_menu-cache is not set +# CONFIG_menu-cache-dbg is not set +# CONFIG_menu-cache-dev is not set + +# +# xcb-proto +# +# CONFIG_python-xcbgen is not set +# CONFIG_xcb-proto-dev is not set +# CONFIG_xcb-proto-dbg is not set + +# +# xcb-util +# +# CONFIG_xcb-util is not set +# CONFIG_xcb-util-dbg is not set +# CONFIG_xcb-util-dev is not set + +# +# xkeyboard-config +# +# CONFIG_xkeyboard-config is not set +# CONFIG_xkeyboard-config-dev is not set +# CONFIG_xkeyboard-config-dbg is not set + +# +# matchbox-keyboard +# +# CONFIG_matchbox-keyboard is not set +# CONFIG_matchbox-keyboard-im is not set +# CONFIG_matchbox-keyboard-dev is not set +# CONFIG_matchbox-keyboard-applet is not set +# CONFIG_matchbox-keyboard-dbg is not set + +# +# matchbox-session +# +# CONFIG_matchbox-session is not set +# CONFIG_matchbox-session-dev is not set +# CONFIG_matchbox-session-dbg is not set + +# +# matchbox-session-sato +# +# CONFIG_matchbox-session-sato is not set +# CONFIG_matchbox-session-sato-dev is not set +# CONFIG_matchbox-session-sato-dbg is not set + +# +# mesa-demos +# +# CONFIG_mesa-demos is not set +# CONFIG_mesa-demos-dbg is not set +# CONFIG_mesa-demos-dev is not set + +# +# mini-x-session +# +# CONFIG_mini-x-session is not set +# CONFIG_mini-x-session-dev is not set +# CONFIG_mini-x-session-dbg is not set + +# +# pcmanfm +# +# CONFIG_pcmanfm is not set +# CONFIG_pcmanfm-dbg is not set +# CONFIG_pcmanfm-dev is not set + +# +# settings-daemon +# +# CONFIG_settings-daemon is not set +# CONFIG_settings-daemon-dev is not set +# CONFIG_settings-daemon-dbg is not set + +# +# utils +# + +# +# libcroco +# +# CONFIG_libcroco is not set +# CONFIG_libcroco-dbg is not set +# CONFIG_libcroco-dev is not set + +# +# librsvg +# +# CONFIG_librsvg is not set +# CONFIG_librsvg-gtk is not set +# CONFIG_rsvg is not set +# CONFIG_librsvg-dev is not set +# CONFIG_librsvg-dbg is not set + +# +# matchbox-terminal +# +# CONFIG_matchbox-terminal is not set +# CONFIG_matchbox-terminal-dev is not set +# CONFIG_matchbox-terminal-dbg is not set + +# +# xrestop +# +# CONFIG_xrestop is not set +# CONFIG_xrestop-dev is not set +# CONFIG_xrestop-dbg is not set + +# +# wm +# + +# +# libfakekey +# +# CONFIG_libfakekey is not set +# CONFIG_libfakekey-dev is not set +# CONFIG_libfakekey-dbg is not set + +# +# matchbox-desktop +# +# CONFIG_matchbox-desktop is not set +# CONFIG_matchbox-desktop-dbg is not set +# CONFIG_matchbox-desktop-dev is not set + +# +# matchbox-theme-sato +# +# CONFIG_matchbox-theme-sato is not set +# CONFIG_matchbox-theme-sato-dbg is not set +# CONFIG_matchbox-theme-sato-dev is not set + +# +# matchbox-wm +# +# CONFIG_matchbox-wm is not set +# CONFIG_matchbox-wm-dev is not set +# CONFIG_matchbox-wm-dbg is not set + +# +# xserver-nodm-init +# +# CONFIG_xserver-nodm-init is not set +# CONFIG_xserver-nodm-init-dbg is not set +# CONFIG_xserver-nodm-init-dev is not set + +# +# Petalinux Package Groups +# + +# +# packagegroup-petalinux +# +# CONFIG_packagegroup-petalinux is not set +# CONFIG_packagegroup-petalinux-dbg is not set +# CONFIG_packagegroup-petalinux-dev is not set + +# +# packagegroup-petalinux-audio +# +# CONFIG_packagegroup-petalinux-audio is not set +# CONFIG_packagegroup-petalinux-audio-dbg is not set +# CONFIG_packagegroup-petalinux-audio-dev is not set + +# +# packagegroup-petalinux-benchmarks +# +# CONFIG_packagegroup-petalinux-benchmarks is not set +# CONFIG_packagegroup-petalinux-benchmarks-dbg is not set +# CONFIG_packagegroup-petalinux-benchmarks-dev is not set + +# +# packagegroup-petalinux-display-debug +# +# CONFIG_packagegroup-petalinux-display-debug is not set +# CONFIG_packagegroup-petalinux-display-debug-dbg is not set +# CONFIG_packagegroup-petalinux-display-debug-dev is not set + +# +# packagegroup-petalinux-gstreamer +# +# CONFIG_packagegroup-petalinux-gstreamer is not set +# CONFIG_packagegroup-petalinux-gstreamer-dev is not set +# CONFIG_packagegroup-petalinux-gstreamer-dbg is not set + +# +# packagegroup-petalinux-lmsensors +# +# CONFIG_packagegroup-petalinux-lmsensors is not set +# CONFIG_packagegroup-petalinux-lmsensors-dbg is not set +# CONFIG_packagegroup-petalinux-lmsensors-dev is not set + +# +# packagegroup-petalinux-matchbox +# +# CONFIG_packagegroup-petalinux-matchbox is not set +# CONFIG_packagegroup-petalinux-matchbox-dbg is not set +# CONFIG_packagegroup-petalinux-matchbox-dev is not set + +# +# packagegroup-petalinux-mraa +# +# CONFIG_packagegroup-petalinux-mraa is not set +# CONFIG_packagegroup-petalinux-mraa-dbg is not set +# CONFIG_packagegroup-petalinux-mraa-dev is not set + +# +# packagegroup-petalinux-multimedia +# +# CONFIG_packagegroup-petalinux-multimedia is not set +# CONFIG_packagegroup-petalinux-multimedia-dbg is not set +# CONFIG_packagegroup-petalinux-multimedia-dev is not set + +# +# packagegroup-petalinux-networking-debug +# +CONFIG_packagegroup-petalinux-networking-debug=y +# CONFIG_packagegroup-petalinux-networking-debug-dbg is not set +# CONFIG_packagegroup-petalinux-networking-debug-dev is not set + +# +# packagegroup-petalinux-networking-stack +# +CONFIG_packagegroup-petalinux-networking-stack=y +# CONFIG_packagegroup-petalinux-networking-stack-dbg is not set +# CONFIG_packagegroup-petalinux-networking-stack-dev is not set + +# +# packagegroup-petalinux-ocicontainers +# +# CONFIG_packagegroup-petalinux-ocicontainers is not set +# CONFIG_packagegroup-petalinux-ocicontainers-dev is not set +# CONFIG_packagegroup-petalinux-ocicontainers-dbg is not set + +# +# packagegroup-petalinux-openamp +# +# CONFIG_packagegroup-petalinux-openamp is not set +# CONFIG_packagegroup-petalinux-openamp-dev is not set +# CONFIG_packagegroup-petalinux-openamp-dbg is not set + +# +# packagegroup-petalinux-opencv +# +# CONFIG_packagegroup-petalinux-opencv is not set +# CONFIG_packagegroup-petalinux-opencv-dev is not set +# CONFIG_packagegroup-petalinux-opencv-dbg is not set + +# +# packagegroup-petalinux-python-modules +# +# CONFIG_packagegroup-petalinux-python-modules is not set +# CONFIG_packagegroup-petalinux-python-modules-dbg is not set +# CONFIG_packagegroup-petalinux-python-modules-dev is not set + +# +# packagegroup-petalinux-qt +# +# CONFIG_packagegroup-petalinux-qt is not set +# CONFIG_packagegroup-petalinux-qt-dev is not set +# CONFIG_packagegroup-petalinux-qt-dbg is not set +# CONFIG_imageclass-populate-sdk-qt5 is not set + +# +# packagegroup-petalinux-qt-extended +# +# CONFIG_packagegroup-petalinux-qt-extended is not set +# CONFIG_packagegroup-petalinux-qt-extended-dbg is not set +# CONFIG_packagegroup-petalinux-qt-extended-dev is not set + +# +# packagegroup-petalinux-self-hosted +# +# CONFIG_packagegroup-petalinux-self-hosted is not set +# CONFIG_packagegroup-petalinux-self-hosted-dbg is not set +# CONFIG_packagegroup-petalinux-self-hosted-dev is not set + +# +# packagegroup-petalinux-updateboot +# +# CONFIG_packagegroup-petalinux-updateboot is not set +# CONFIG_packagegroup-petalinux-updateboot-dbg is not set +# CONFIG_packagegroup-petalinux-updateboot-dev is not set + +# +# packagegroup-petalinux-utils +# +# CONFIG_packagegroup-petalinux-utils is not set +# CONFIG_packagegroup-petalinux-utils-dbg is not set +# CONFIG_packagegroup-petalinux-utils-dev is not set + +# +# packagegroup-petalinux-v4lutils +# +# CONFIG_packagegroup-petalinux-v4lutils is not set +# CONFIG_packagegroup-petalinux-v4lutils-dbg is not set +# CONFIG_packagegroup-petalinux-v4lutils-dev is not set + +# +# packagegroup-petalinux-vitisai +# +# CONFIG_packagegroup-petalinux-vitisai is not set +# CONFIG_packagegroup-petalinux-vitisai-dbg is not set +# CONFIG_packagegroup-petalinux-vitisai-dev is not set + +# +# packagegroup-petalinux-weston +# +# CONFIG_packagegroup-petalinux-weston is not set +# CONFIG_packagegroup-petalinux-weston-dbg is not set +# CONFIG_packagegroup-petalinux-weston-dev is not set + +# +# packagegroup-petalinux-x11 +# +# CONFIG_packagegroup-petalinux-x11 is not set +# CONFIG_packagegroup-petalinux-x11-dev is not set +# CONFIG_packagegroup-petalinux-x11-dbg is not set + +# +# packagegroup-petalinux-xen +# +# CONFIG_packagegroup-petalinux-xen is not set +# CONFIG_packagegroup-petalinux-xen-dev is not set +# CONFIG_packagegroup-petalinux-xen-dbg is not set + +# +# packagegroup-petalinux-xrt +# +# CONFIG_packagegroup-petalinux-xrt is not set +# CONFIG_packagegroup-petalinux-xrt-dev is not set +# CONFIG_packagegroup-petalinux-xrt-dbg is not set + +# +# Image Features +# +CONFIG_imagefeature-ssh-server-dropbear=y +# CONFIG_imagefeature-ssh-server-openssh is not set +CONFIG_imagefeature-hwcodecs=y +# CONFIG_imagefeature-package-management is not set +CONFIG_imagefeature-debug-tweaks=y +CONFIG_auto-login=y + +# +# apps +# +CONFIG_gpio-demo=y +CONFIG_myapp-init=y +CONFIG_peekpoke=y + +# +# user packages +# +CONFIG_iperf3=y +CONFIG_phytool=y + +# +# PetaLinux RootFS Settings +# +CONFIG_ROOTFS_ROOT_PASSWD="root" +CONFIG_ADD_EXTRA_USERS="pinky" diff --git a/Petalinux/project-spec/configs/rootfs_config.old b/Petalinux/project-spec/configs/rootfs_config.old new file mode 100644 index 0000000..8acdd8e --- /dev/null +++ b/Petalinux/project-spec/configs/rootfs_config.old @@ -0,0 +1,4256 @@ +# +# Automatically generated file; DO NOT EDIT. +# Configuration +# +CONFIG_system-zynqmp=y + +# +# Filesystem Packages +# + +# +# admin +# + +# +# sudo +# +CONFIG_sudo=y +# CONFIG_sudo-dev is not set +# CONFIG_sudo-dbg is not set + +# +# audio +# + +# +# sox +# +# CONFIG_sox is not set +# CONFIG_sox-dbg is not set +# CONFIG_sox-dev is not set + +# +# base +# + +# +# base-files +# +# CONFIG_base-files is not set +# CONFIG_base-files-dbg is not set +# CONFIG_base-files-dev is not set + +# +# base-passwd +# +# CONFIG_base-passwd is not set +# CONFIG_base-passwd-dev is not set +# CONFIG_base-passwd-dbg is not set +# CONFIG_base-passwd-update is not set + +# +# bc +# +# CONFIG_bc is not set +# CONFIG_bc-dev is not set +# CONFIG_bc-dbg is not set + +# +# busybox +# +# CONFIG_busybox is not set +# CONFIG_busybox-inetd is not set +# CONFIG_busybox-dbg is not set +# CONFIG_busybox-syslog is not set +# CONFIG_busybox-hwclock is not set +# CONFIG_busybox-httpd is not set +# CONFIG_busybox-dev is not set +# CONFIG_busybox-udhcpc is not set +# CONFIG_busybox-udhcpd is not set + +# +# cpio +# +# CONFIG_cpio is not set +# CONFIG_cpio-dbg is not set +# CONFIG_cpio-dev is not set +# CONFIG_cpio-rmt is not set + +# +# dbus +# +# CONFIG_dbus is not set +# CONFIG_dbus-dbg is not set +# CONFIG_dbus-lib is not set +# CONFIG_dbus-dev is not set + +# +# dbus-glib +# +# CONFIG_dbus-glib is not set +# CONFIG_dbus-glib-dev is not set +# CONFIG_dbus-glib-bash-completion is not set +# CONFIG_dbus-glib-tests is not set +# CONFIG_dbus-glib-dbg is not set + +# +# dbus-wait +# +# CONFIG_dbus-wait is not set +# CONFIG_dbus-wait-dbg is not set +# CONFIG_dbus-wait-dev is not set + +# +# diffutils +# +# CONFIG_diffutils is not set +# CONFIG_diffutils-dbg is not set +# CONFIG_diffutils-dev is not set + +# +# dnf +# +# CONFIG_dnf is not set + +# +# e2fsprogs +# +# CONFIG_e2fsprogs is not set +# CONFIG_e2fsprogs-dev is not set +# CONFIG_e2fsprogs-mke2fs is not set +# CONFIG_e2fsprogs-dbg is not set +# CONFIG_e2fsprogs-resize2fs is not set +# CONFIG_e2fsprogs-tune2fs is not set +# CONFIG_libss is not set +# CONFIG_libcomerr is not set +# CONFIG_libext2fs is not set +# CONFIG_libe2p is not set +# CONFIG_e2fsprogs-e2fsck is not set +# CONFIG_e2fsprogs-badblocks is not set + +# +# ed +# +# CONFIG_ed is not set +# CONFIG_ed-dev is not set +# CONFIG_ed-dbg is not set + +# +# elfutils +# +# CONFIG_elfutils is not set +# CONFIG_libdw is not set +# CONFIG_elfutils-dev is not set +# CONFIG_elfutils-binutils is not set +# CONFIG_libelf is not set +# CONFIG_elfutils-dbg is not set +# CONFIG_libasm is not set + +# +# formfactor +# +# CONFIG_formfactor is not set +# CONFIG_formfactor-dbg is not set +# CONFIG_formfactor-dev is not set + +# +# fpga-manager-script +# +CONFIG_fpga-manager-script=y + +# +# haveged +# +CONFIG_haveged=y + +# +# i2c-tools +# +CONFIG_i2c-tools=y +# CONFIG_i2c-tools-dev is not set +# CONFIG_i2c-tools-misc is not set +# CONFIG_i2c-tools-dbg is not set + +# +# init-ifupdown +# +# CONFIG_init-ifupdown is not set +# CONFIG_init-ifupdown-dev is not set +# CONFIG_init-ifupdown-dbg is not set + +# +# initscripts +# +# CONFIG_initscripts is not set +# CONFIG_initscripts-functions is not set +# CONFIG_initscripts-dev is not set +# CONFIG_initscripts-dbg is not set + +# +# iproute2 +# +CONFIG_iproute2=y +# CONFIG_iproute2-ss is not set +# CONFIG_iproute2-dev is not set +# CONFIG_iproute2-dbg is not set +# CONFIG_iproute2-ifstat is not set +# CONFIG_iproute2-nstat is not set +# CONFIG_iproute2-tc is not set +# CONFIG_iproute2-bash-completion is not set +# CONFIG_iproute2-genl is not set +# CONFIG_iproute2-rtacct is not set +# CONFIG_iproute2-lnstat is not set + +# +# kmod +# +# CONFIG_kmod is not set +# CONFIG_kmod-bash-completion is not set +# CONFIG_libkmod is not set +# CONFIG_kmod-dbg is not set +# CONFIG_kmod-dev is not set + +# +# linuxptp +# +# CONFIG_linuxptp is not set +# CONFIG_linuxptp-dev is not set +# CONFIG_linuxptp-dbg is not set + +# +# modutils-initscripts +# +# CONFIG_modutils-initscripts is not set +# CONFIG_modutils-initscripts-dev is not set +# CONFIG_modutils-initscripts-dbg is not set + +# +# mtd-utils +# +CONFIG_mtd-utils=y +# CONFIG_mtd-utils-jffs2 is not set +# CONFIG_mtd-utils-misc is not set +# CONFIG_mtd-utils-dev is not set +# CONFIG_mtd-utils-ubifs is not set +# CONFIG_mtd-utils-dbg is not set + +# +# netbase +# +CONFIG_netbase=y +# CONFIG_netbase-dev is not set +# CONFIG_netbase-dbg is not set + +# +# opkg +# +# CONFIG_opkg is not set +# CONFIG_libopkg is not set +# CONFIG_opkg-dbg is not set +# CONFIG_opkg-dev is not set + +# +# opkg-utils +# +# CONFIG_opkg-utils is not set +# CONFIG_opkg-utils-dbg is not set +# CONFIG_update-alternatives-opkg is not set + +# +# procps +# +# CONFIG_procps is not set +# CONFIG_procps-dev is not set +# CONFIG_procps-dbg is not set + +# +# pseudo +# +# CONFIG_pseudo is not set +# CONFIG_pseudo-dev is not set +# CONFIG_pseudo-dbg is not set + +# +# psplash +# +# CONFIG_psplash is not set +# CONFIG_psplash-dbg is not set +# CONFIG_psplash-default is not set +# CONFIG_psplash-dev is not set + +# +# quota +# +# CONFIG_quota is not set +# CONFIG_quota-dbg is not set +# CONFIG_quota-dev is not set + +# +# shared-mime-info +# +# CONFIG_shared-mime-info is not set +# CONFIG_shared-mime-info-dev is not set +# CONFIG_shared-mime-info-dbg is not set +# CONFIG_shared-mime-info-data is not set + +# +# shell +# + +# +# bash +# +# CONFIG_bash is not set +# CONFIG_bash-dbg is not set +# CONFIG_bash-dev is not set + +# +# sysvinit +# +# CONFIG_sysvinit is not set +# CONFIG_sysvinit-dev is not set +# CONFIG_sysvinit-sulogin is not set +# CONFIG_sysvinit-dbg is not set +# CONFIG_sysvinit-pidof is not set + +# +# tar +# +# CONFIG_tar is not set +# CONFIG_tar-dev is not set +# CONFIG_tar-dbg is not set +# CONFIG_tar-rmt is not set + +# +# tzdata +# +# CONFIG_tzdata is not set +# CONFIG_tzdata-pacific is not set +# CONFIG_tzdata-posix is not set +# CONFIG_tzdata-antarctica is not set +# CONFIG_tzdata-africa is not set +# CONFIG_tzdata-europe is not set +# CONFIG_tzdata-americas is not set +# CONFIG_tzdata-right is not set +# CONFIG_tzdata-atlantic is not set +# CONFIG_tzdata-australia is not set +# CONFIG_tzdata-misc is not set +# CONFIG_tzdata-asia is not set +# CONFIG_tzdata-arctic is not set + +# +# update-rc.d +# +# CONFIG_update-rc.d is not set +# CONFIG_update-rc.d-dbg is not set +# CONFIG_update-rc.d-dev is not set + +# +# usbutils +# +# CONFIG_usbutils is not set +# CONFIG_usbutils-dev is not set +# CONFIG_usbutils-dbg is not set + +# +# util-linux +# +CONFIG_util-linux=y +# CONFIG_util-linux-sulogin is not set +# CONFIG_util-linux-losetup is not set +# CONFIG_util-linux-hwclock is not set +# CONFIG_util-linux-fsck is not set +# CONFIG_util-linux-uuidgen is not set +# CONFIG_util-linux-bash-completion is not set +# CONFIG_util-linux-fstrim is not set +# CONFIG_util-linux-cfdisk is not set +# CONFIG_util-linux-umount is not set +# CONFIG_util-linux-findfs is not set +# CONFIG_util-linux-agetty is not set +# CONFIG_util-linux-mount is not set +# CONFIG_util-linux-sfdisk is not set +# CONFIG_util-linux-swaponoff is not set +# CONFIG_util-linux-fsck.cramfs is not set +# CONFIG_util-linux-prlimit is not set +# CONFIG_util-linux-mcookie is not set +# CONFIG_util-linux-getopt is not set +# CONFIG_util-linux-blkid is not set +# CONFIG_util-linux-dev is not set +# CONFIG_util-linux-partx is not set +# CONFIG_util-linux-mkfs is not set +# CONFIG_util-linux-readprofile is not set +# CONFIG_util-linux-mountpoint is not set +# CONFIG_util-linux-fdisk is not set +# CONFIG_util-linux-lscpu is not set +# CONFIG_util-linux-dbg is not set +# CONFIG_util-linux-uuidd is not set +# CONFIG_util-linux-mkfs.cramfs is not set + +# +# utils +# + +# +# shadow +# +# CONFIG_shadow is not set +# CONFIG_shadow-base is not set +# CONFIG_shadow-dev is not set +# CONFIG_shadow-dbg is not set + +# +# xz +# +# CONFIG_xz is not set +# CONFIG_xz-dev is not set +# CONFIG_xz-dbg is not set +# CONFIG_liblzma is not set + +# +# baseutils +# + +# +# shadow-securetty +# +# CONFIG_shadow-securetty is not set +# CONFIG_shadow-securetty-dev is not set +# CONFIG_shadow-securetty-dbg is not set + +# +# benchmark +# + +# +# tests +# + +# +# dhrystone +# +# CONFIG_dhrystone is not set +# CONFIG_dhrystone-dev is not set +# CONFIG_dhrystone-dbg is not set + +# +# linpack +# +# CONFIG_linpack is not set +# CONFIG_linpack-dbg is not set +# CONFIG_linpack-dev is not set + +# +# whetstone +# +# CONFIG_whetstone is not set +# CONFIG_whetstone-dev is not set +# CONFIG_whetstone-dbg is not set + +# +# bootgen +# +# CONFIG_bootgen is not set +# CONFIG_bootgen-dev is not set +# CONFIG_bootgen-dbg is not set + +# +# bootloader +# + +# +# dtc +# +# CONFIG_dtc is not set +# CONFIG_dtc-dbg is not set +# CONFIG_dtc-misc is not set +# CONFIG_dtc-dev is not set + +# +# console +# + +# +# network +# + +# +# canutils +# +CONFIG_canutils=y +# CONFIG_canutils-dev is not set +# CONFIG_canutils-dbg is not set + +# +# can-utils +# +# CONFIG_can-utils is not set +# CONFIG_can-utils-dbg is not set +# CONFIG_can-utils-dev is not set + +# +# curl +# +# CONFIG_curl is not set +# CONFIG_curl-dbg is not set +# CONFIG_libcurl is not set +# CONFIG_curl-dev is not set + +# +# dropbear +# +# CONFIG_dropbear is not set +# CONFIG_dropbear-dev is not set +# CONFIG_dropbear-dbg is not set + +# +# ethtool +# +CONFIG_ethtool=y +# CONFIG_ethtool-dev is not set +# CONFIG_ethtool-dbg is not set + +# +# lrzsz +# +# CONFIG_lrzsz is not set +# CONFIG_lrzsz-dbg is not set +# CONFIG_lrzsz-dev is not set + +# +# mailx +# +# CONFIG_mailx is not set +# CONFIG_mailx-dbg is not set +# CONFIG_mailx-dev is not set + +# +# minicom +# +# CONFIG_minicom is not set +# CONFIG_minicom-dev is not set +# CONFIG_minicom-dbg is not set + +# +# nfs-utils +# +# CONFIG_nfs-utils is not set +# CONFIG_nfs-utils-stats is not set +# CONFIG_nfs-utils-dbg is not set +# CONFIG_nfs-utils-dev is not set +# CONFIG_nfs-utils-client is not set + +# +# openssh +# +# CONFIG_openssh is not set +# CONFIG_openssh-ssh is not set +# CONFIG_openssh-sftp is not set +CONFIG_openssh-sftp-server=y +# CONFIG_openssh-keygen is not set +# CONFIG_openssh-dbg is not set +# CONFIG_openssh-dev is not set +# CONFIG_openssh-misc is not set +# CONFIG_openssh-sshd is not set +# CONFIG_openssh-scp is not set + +# +# ppp +# +# CONFIG_ppp is not set +# CONFIG_ppp-dev is not set +# CONFIG_ppp-l2tp is not set +# CONFIG_ppp-minconn is not set +# CONFIG_ppp-winbind is not set +# CONFIG_ppp-dbg is not set +# CONFIG_ppp-oe is not set +# CONFIG_ppp-oa is not set +# CONFIG_ppp-radius is not set +# CONFIG_ppp-tools is not set +# CONFIG_ppp-password is not set + +# +# rpcbind +# +# CONFIG_rpcbind is not set +# CONFIG_rpcbind-dev is not set +# CONFIG_rpcbind-dbg is not set + +# +# rsync +# +# CONFIG_rsync is not set +# CONFIG_rsync-dev is not set +# CONFIG_rsync-dbg is not set + +# +# socat +# +CONFIG_socat=y +# CONFIG_socat-dev is not set +# CONFIG_socat-dbg is not set + +# +# subversion +# +# CONFIG_subversion is not set +# CONFIG_subversion-dev is not set +# CONFIG_subversion-dbg is not set + +# +# tcp-wrappers +# +# CONFIG_tcp-wrappers is not set +# CONFIG_libwrap is not set +# CONFIG_tcp-wrappers-dbg is not set +# CONFIG_libwrap-dev is not set + +# +# wget +# +CONFIG_wget=y +# CONFIG_wget-dev is not set +# CONFIG_wget-dbg is not set + +# +# tools +# + +# +# parted +# +# CONFIG_parted is not set +# CONFIG_parted-dev is not set +# CONFIG_parted-dbg is not set + +# +# xen +# +# CONFIG_xen-libxengnttab-dev is not set +# CONFIG_xen-xenpmd is not set +# CONFIG_xen-libxenstat is not set +# CONFIG_xen-base is not set +# CONFIG_xen-libxenevtchn-dev is not set +# CONFIG_xen-efi is not set +# CONFIG_xen-hypervisor is not set +# CONFIG_xen-xenstat is not set +# CONFIG_xen-xl-examples is not set +# CONFIG_xen-scripts-block is not set +# CONFIG_xen-libxlutil-dev is not set +# CONFIG_xen-libxenstat-dev is not set +# CONFIG_xen-scripts-common is not set +# CONFIG_xen-xenmon is not set +# CONFIG_xen-init-xenstore-dom is not set +# CONFIG_xen-remus is not set +# CONFIG_xen-libxenstore is not set +# CONFIG_xen-libxencall is not set +# CONFIG_xen-xencommons is not set +# CONFIG_xen-libxenstore-dev is not set +# CONFIG_xen-livepatch is not set +# CONFIG_xen-libxenlight-dev is not set +# CONFIG_xen-libxencall-dev is not set +# CONFIG_xen-console is not set +# CONFIG_xen-misc is not set +# CONFIG_xen-libxenvchan is not set +# CONFIG_xen-volatiles is not set +# CONFIG_xen-flask-tools is not set +# CONFIG_xen-dbg is not set +# CONFIG_xen-libxenlight is not set +# CONFIG_xen-libfsimage-dev is not set +# CONFIG_xen-xl is not set +# CONFIG_xen-libxenvchan-dev is not set +# CONFIG_xen-libxentoollog-dev is not set +# CONFIG_xen-fsimage is not set +# CONFIG_xen-libxentoollog is not set +# CONFIG_xen-libxenforeignmemory-dev is not set +# CONFIG_xen-libxengnttab is not set +# CONFIG_xen-xentrace is not set +# CONFIG_xen-libxenctrl is not set +# CONFIG_xen-libfsimage is not set +# CONFIG_xen-libxenforeignmemory is not set +# CONFIG_xen-xendomains is not set +# CONFIG_xen-dev is not set +# CONFIG_xen-xen-watchdog is not set +# CONFIG_xen-libxenguest is not set +# CONFIG_xen-libxlutil is not set +# CONFIG_xen-xenstore is not set +# CONFIG_xen-devd is not set +# CONFIG_xen-libxenevtchn is not set +# CONFIG_xen-libxenctrl-dev is not set +# CONFIG_xen-scripts-network is not set +# CONFIG_xen-libxenguest-dev is not set +# CONFIG_xen-xenstored is not set + +# +# utils +# + +# +# alsa-tools +# +# CONFIG_alsa-tools is not set +# CONFIG_alsa-tools-dbg is not set +# CONFIG_alsa-tools-dev is not set + +# +# alsa-utils +# +# CONFIG_alsa-utils is not set +# CONFIG_alsa-utils-alsatplg is not set +# CONFIG_alsa-utils-midi is not set +# CONFIG_alsa-utils-alsactl is not set +# CONFIG_alsa-utils-alsamixer is not set +# CONFIG_alsa-utils-amixer is not set +# CONFIG_alsa-utils-speakertest is not set +# CONFIG_alsa-utils-aplay is not set +# CONFIG_alsa-utils-dev is not set +# CONFIG_alsa-utils-aconnect is not set +# CONFIG_alsa-utils-alsaloop is not set +# CONFIG_alsa-utils-aseqdump is not set +# CONFIG_alsa-utils-iecset is not set +# CONFIG_alsa-utils-alsaucm is not set +# CONFIG_alsa-utils-dbg is not set +# CONFIG_alsa-utils-aseqnet is not set + +# +# bash-completion +# +# CONFIG_bash-completion is not set +# CONFIG_bash-completion-dbg is not set +# CONFIG_bash-completion-dev is not set +# CONFIG_bash-completion-extra is not set + +# +# bzip2 +# +# CONFIG_bzip2 is not set +# CONFIG_libbz2 is not set +# CONFIG_bzip2-dbg is not set +# CONFIG_bzip2-dev is not set + +# +# file +# +# CONFIG_file is not set +# CONFIG_file-dev is not set +# CONFIG_file-dbg is not set + +# +# findutils +# +# CONFIG_findutils is not set +# CONFIG_findutils-dbg is not set +# CONFIG_findutils-dev is not set + +# +# gawk +# +# CONFIG_gawk is not set +# CONFIG_gawk-dbg is not set +# CONFIG_gawk-dev is not set + +# +# git +# +# CONFIG_git is not set +# CONFIG_git-bash-completion is not set +# CONFIG_git-perltools is not set +# CONFIG_gitweb is not set +# CONFIG_git-dev is not set +# CONFIG_git-dbg is not set + +# +# grep +# +# CONFIG_grep is not set +# CONFIG_grep-dbg is not set +# CONFIG_grep-dev is not set + +# +# groff +# +# CONFIG_groff is not set +# CONFIG_groff-dev is not set +# CONFIG_groff-dbg is not set + +# +# gzip +# +# CONFIG_gzip is not set +# CONFIG_gzip-dev is not set +# CONFIG_gzip-dbg is not set + +# +# hdparm +# +# CONFIG_hdparm is not set +# CONFIG_hdparm-dev is not set +# CONFIG_wiper is not set +# CONFIG_hdparm-dbg is not set + +# +# less +# +# CONFIG_less is not set +# CONFIG_less-dbg is not set +# CONFIG_less-dev is not set + +# +# lmbench +# +# CONFIG_lmbench is not set +# CONFIG_lmbench-dbg is not set +# CONFIG_lmbench-dev is not set + +# +# ltp +# +# CONFIG_ltp is not set +# CONFIG_ltp-dev is not set +# CONFIG_ltp-dbg is not set + +# +# man +# +# CONFIG_man is not set + +# +# man-pages +# +# CONFIG_man-pages is not set +# CONFIG_man-pages-dev is not set +# CONFIG_man-pages-dbg is not set + +# +# mc +# +# CONFIG_mc is not set +# CONFIG_mc-fish is not set +# CONFIG_mc-dev is not set +# CONFIG_mc-dbg is not set +# CONFIG_mc-helpers is not set +# CONFIG_mc-helpers-perl is not set + +# +# pciutils +# +CONFIG_pciutils=y +# CONFIG_pciutils-dbg is not set +# CONFIG_libpci is not set +# CONFIG_pciutils-ids is not set +# CONFIG_pciutils-dev is not set + +# +# pkgconfig +# +# CONFIG_pkgconfig is not set +# CONFIG_pkgconfig-dev is not set +# CONFIG_pkgconfig-dbg is not set + +# +# screen +# +# CONFIG_screen is not set +# CONFIG_screen-dev is not set +# CONFIG_screen-dbg is not set + +# +# sed +# +# CONFIG_sed is not set +# CONFIG_sed-dev is not set +# CONFIG_sed-dbg is not set + +# +# setserial +# +# CONFIG_setserial is not set +# CONFIG_setserial-dbg is not set +# CONFIG_setserial-dev is not set + +# +# smartmontools +# +# CONFIG_smartmontools is not set +# CONFIG_smartmontools-dev is not set +# CONFIG_smartmontools-dbg is not set + +# +# strace +# +# CONFIG_strace is not set +# CONFIG_strace-dev is not set +# CONFIG_strace-dbg is not set + +# +# sysstat +# +# CONFIG_sysstat is not set +# CONFIG_sysstat-dbg is not set +# CONFIG_sysstat-dev is not set + +# +# texinfo +# +# CONFIG_texinfo is not set +# CONFIG_texinfo-dbg is not set +# CONFIG_texinfo-dev is not set +# CONFIG_info is not set + +# +# unzip +# +# CONFIG_unzip is not set +# CONFIG_unzip-dbg is not set +# CONFIG_unzip-dev is not set + +# +# vim +# +# CONFIG_vim is not set +# CONFIG_vim-help is not set +# CONFIG_vim-dbg is not set +# CONFIG_vim-vimrc is not set +# CONFIG_vim-dev is not set +# CONFIG_vim-tutor is not set +# CONFIG_vim-tools is not set +# CONFIG_vim-common is not set +# CONFIG_vim-syntax is not set + +# +# zip +# +# CONFIG_zip is not set +# CONFIG_zip-dev is not set +# CONFIG_zip-dbg is not set + +# +# devel +# + +# +# autoconf +# +# CONFIG_autoconf is not set +# CONFIG_autoconf-dbg is not set +# CONFIG_autoconf-dev is not set + +# +# automake +# +# CONFIG_automake is not set +# CONFIG_automake-dev is not set +# CONFIG_automake-dbg is not set + +# +# binutils +# +# CONFIG_binutils is not set +# CONFIG_binutils-dev is not set +# CONFIG_binutils-dbg is not set + +# +# bison +# +# CONFIG_bison is not set +# CONFIG_bison-dbg is not set +# CONFIG_bison-dev is not set + +# +# ccache +# +# CONFIG_ccache is not set +# CONFIG_ccache-dbg is not set +# CONFIG_ccache-dev is not set + +# +# diffstat +# +# CONFIG_diffstat is not set +# CONFIG_diffstat-dev is not set +# CONFIG_diffstat-dbg is not set + +# +# distcc +# +# CONFIG_distcc is not set +# CONFIG_distcc-dbg is not set +# CONFIG_distcc-dev is not set + +# +# expect +# +# CONFIG_expect is not set +# CONFIG_expect-dev is not set +# CONFIG_expect-dbg is not set + +# +# flex +# +# CONFIG_flex is not set +# CONFIG_flex-dbg is not set +# CONFIG_flex-dev is not set + +# +# gmp +# +# CONFIG_gmp is not set +# CONFIG_libgmpxx is not set +# CONFIG_gmp-dbg is not set +# CONFIG_gmp-dev is not set + +# +# gnu-config +# +# CONFIG_gnu-config is not set + +# +# gnu-efi +# +# CONFIG_gnu-efi is not set +# CONFIG_gnu-efi-dbg is not set +# CONFIG_gnu-efi-dev is not set + +# +# intltool +# +# CONFIG_intltool is not set +# CONFIG_intltool-dev is not set +# CONFIG_intltool-dbg is not set + +# +# libarchive +# +# CONFIG_libarchive is not set +# CONFIG_bsdcpio is not set +# CONFIG_libarchive-dbg is not set +# CONFIG_bsdtar is not set +# CONFIG_libarchive-dev is not set + +# +# libcheck +# +# CONFIG_libcheck is not set +# CONFIG_libcheck-dev is not set +# CONFIG_libcheck-dbg is not set + +# +# libpcre +# +# CONFIG_libpcre is not set +# CONFIG_libpcrecpp is not set +# CONFIG_libpcre-dbg is not set +# CONFIG_libpcreposix is not set +# CONFIG_libpcre-dev is not set +# CONFIG_pcregrep is not set +# CONFIG_pcretest is not set + +# +# lsof +# +# CONFIG_lsof is not set +# CONFIG_lsof-dev is not set +# CONFIG_lsof-dbg is not set + +# +# make +# +# CONFIG_make is not set +# CONFIG_make-dev is not set +# CONFIG_make-dbg is not set + +# +# mpfr +# +# CONFIG_mpfr is not set +# CONFIG_mpfr-dbg is not set +# CONFIG_mpfr-dev is not set + +# +# perl +# +# CONFIG_perl is not set +# CONFIG_perl-misc is not set +# CONFIG_perl-modules is not set +# CONFIG_perl-module-unicore is not set +# CONFIG_perl-dbg is not set +# CONFIG_perl-module-cpan is not set +# CONFIG_perl-pod is not set +# CONFIG_perl-dev is not set + +# +# python +# + +# +# python +# +# CONFIG_python is not set +# CONFIG_python-terminal is not set +# CONFIG_python-mailbox is not set +# CONFIG_python-logging is not set +# CONFIG_python-xml is not set +# CONFIG_python-hotshot is not set +# CONFIG_python-multiprocessing is not set +# CONFIG_python-threading is not set +# CONFIG_python-curses is not set +# CONFIG_python-mime is not set +# CONFIG_python-netclient is not set +# CONFIG_python-netserver is not set +# CONFIG_python-image is not set +# CONFIG_python-unixadmin is not set +# CONFIG_python-sqlite3 is not set +# CONFIG_python-pprint is not set +# CONFIG_python-contextlib is not set +# CONFIG_python-idle is not set +# CONFIG_python-pkgutil is not set +# CONFIG_python-crypt is not set +# CONFIG_python-zlib is not set +# CONFIG_python-fcntl is not set +# CONFIG_python-stringold is not set +# CONFIG_python-dev is not set +# CONFIG_libpython2 is not set +# CONFIG_python-smtpd is not set +# CONFIG_python-core is not set +# CONFIG_python-tkinter is not set +# CONFIG_python-codecs is not set +# CONFIG_python-compression is not set +# CONFIG_python-bsddb is not set +# CONFIG_python-subprocess is not set +# CONFIG_python-io is not set +# CONFIG_python-numbers is not set +# CONFIG_python-unittest is not set +# CONFIG_python-json is not set +# CONFIG_python-html is not set +# CONFIG_python-lang is not set +# CONFIG_python-compiler is not set +# CONFIG_python-shell is not set +# CONFIG_python-datetime is not set +# CONFIG_python-email is not set +# CONFIG_python-misc is not set +# CONFIG_python-resource is not set +# CONFIG_python-distutils is not set +# CONFIG_python-syslog is not set +# CONFIG_python-2to3 is not set +# CONFIG_python-pydoc is not set +# CONFIG_python-tests is not set +# CONFIG_python-modules is not set +# CONFIG_python-db is not set +# CONFIG_python-ctypes is not set +# CONFIG_python-re is not set +# CONFIG_python-audio is not set +# CONFIG_python-profile is not set +# CONFIG_python-dbg is not set +# CONFIG_python-mmap is not set +# CONFIG_python-compile is not set +# CONFIG_python-difflib is not set +# CONFIG_python-xmlrpc is not set +# CONFIG_python-argparse is not set +# CONFIG_python-math is not set +# CONFIG_python-robotparser is not set +# CONFIG_python-pickle is not set +# CONFIG_python-debugger is not set +# CONFIG_python-plistlib is not set +# CONFIG_python-gdbm is not set +# CONFIG_python-textutils is not set + +# +# python3-nose +# +# CONFIG_python3-nose is not set +# CONFIG_python3-nose-dbg is not set +# CONFIG_python3-nose-dev is not set + +# +# python3-numpy +# +# CONFIG_python3-numpy is not set +# CONFIG_python3-numpy-dbg is not set +# CONFIG_python3-numpy-dev is not set + +# +# python3-scons +# +# CONFIG_python3-scons is not set +# CONFIG_python3-scons-dev is not set +# CONFIG_python3-scons-dbg is not set + +# +# python3-dbus +# +# CONFIG_python3-dbus is not set +# CONFIG_python3-dbus-dev is not set +# CONFIG_python3-dbus-dbg is not set + +# +# python3-pygobject +# +# CONFIG_python3-pygobject is not set +# CONFIG_python3-pygobject-dbg is not set +# CONFIG_python3-pygobject-dev is not set + +# +# quilt +# +# CONFIG_quilt is not set +# CONFIG_quilt-dev is not set +# CONFIG_quilt-dbg is not set +# CONFIG_guards is not set + +# +# ruby +# + +# +# ruby +# +# CONFIG_ruby is not set +# CONFIG_ruby-dbg is not set +# CONFIG_ruby-dev is not set +# CONFIG_ruby-rdoc is not set + +# +# run-postinsts +# +CONFIG_run-postinsts=y +# CONFIG_run-postinsts-dbg is not set +# CONFIG_run-postinsts-dev is not set + +# +# swig +# +# CONFIG_swig is not set +# CONFIG_swig-dev is not set +# CONFIG_swig-dbg is not set + +# +# tcltk +# + +# +# tcl +# +# CONFIG_tcl is not set +# CONFIG_tcl-dbg is not set +# CONFIG_tcl-lib is not set +# CONFIG_tcl-dev is not set + +# +# vala +# +# CONFIG_vala is not set +# CONFIG_vala-dbg is not set +# CONFIG_vala-dev is not set + +# +# fonts +# + +# +# cantarell-fonts +# +# CONFIG_cantarell-fonts is not set +# CONFIG_cantarell-fonts-dbg is not set +# CONFIG_cantarell-fonts-dev is not set + +# +# kernel +# + +# +# userland +# + +# +# kexec-tools +# +# CONFIG_kexec-tools is not set +# CONFIG_kexec-tools-dbg is not set +# CONFIG_vmcore-dmesg is not set +# CONFIG_kdump is not set +# CONFIG_kexec is not set +# CONFIG_kexec-tools-dev is not set + +# +# libs +# + +# +# acl +# +# CONFIG_acl is not set +# CONFIG_acl-dev is not set +# CONFIG_libacl is not set +# CONFIG_acl-dbg is not set + +# +# apr +# +# CONFIG_apr is not set +# CONFIG_apr-dev is not set +# CONFIG_apr-dbg is not set + +# +# apr-util +# +# CONFIG_apr-util is not set +# CONFIG_apr-util-dev is not set +# CONFIG_apr-util-dbg is not set + +# +# attr +# +# CONFIG_attr is not set +# CONFIG_libattr is not set +# CONFIG_attr-dbg is not set +# CONFIG_attr-dev is not set + +# +# bluez5 +# +# CONFIG_bluez5 is not set +# CONFIG_bluez5-obex is not set +# CONFIG_bluez5-dev is not set +# CONFIG_bluez5-dbg is not set +# CONFIG_bluez5-noinst-tools is not set +# CONFIG_bluez5-testtools is not set + +# +# cairo +# +# CONFIG_cairo is not set +# CONFIG_cairo-dbg is not set +# CONFIG_cairo-dev is not set +# CONFIG_cairo-script-interpreter is not set +# CONFIG_cairo-perf-utils is not set +# CONFIG_cairo-gobject is not set + +# +# db +# +# CONFIG_db is not set +# CONFIG_db-bin is not set +# CONFIG_db-cxx is not set +# CONFIG_db-dbg is not set +# CONFIG_db-dev is not set + +# +# devel +# + +# +# libyaml +# +# CONFIG_libyaml is not set +# CONFIG_libyaml-dev is not set +# CONFIG_libyaml-dbg is not set + +# +# expat +# +# CONFIG_expat is not set +# CONFIG_expat-dev is not set +# CONFIG_expat-dbg is not set +# CONFIG_expat-bin is not set + +# +# faad2 +# +# CONFIG_faad2 is not set +# CONFIG_faad2-dev is not set +# CONFIG_faad2-dbg is not set + +# +# ffmpeg +# +# CONFIG_ffmpeg is not set +# CONFIG_ffmpeg-dbg is not set +# CONFIG_ffmpeg-dev is not set + +# +# flac +# +# CONFIG_flac is not set +# CONFIG_libflac is not set +# CONFIG_flac-dev is not set +# CONFIG_libflacPLUSPLUS is not set +# CONFIG_flac-dbg is not set + +# +# fontconfig +# +# CONFIG_fontconfig is not set +# CONFIG_fontconfig-utils is not set +# CONFIG_fontconfig-dev is not set +# CONFIG_fontconfig-dbg is not set + +# +# freetype +# +# CONFIG_freetype is not set +# CONFIG_freetype-dbg is not set +# CONFIG_freetype-dev is not set + +# +# gdbm +# +# CONFIG_gdbm is not set +# CONFIG_gdbm-dbg is not set +# CONFIG_gdbm-compat is not set +# CONFIG_gdbm-dev is not set +# CONFIG_gdbm-bin is not set + +# +# gdk-pixbuf +# +# CONFIG_gdk-pixbuf is not set +# CONFIG_gdk-pixbuf-xlib is not set +# CONFIG_gdk-pixbuf-dev is not set +# CONFIG_gdk-pixbuf-dbg is not set + +# +# gettext +# +# CONFIG_gettext is not set +# CONFIG_libgettextsrc is not set +# CONFIG_gettext-dbg is not set +# CONFIG_gettext-runtime is not set +# CONFIG_gettext-dev is not set +# CONFIG_libgettextlib is not set + +# +# glib-networking +# +# CONFIG_glib-networking is not set +# CONFIG_glib-networking-dev is not set +# CONFIG_glib-networking-dbg is not set + +# +# gobject-introspection +# +# CONFIG_gobject-introspection is not set +# CONFIG_gobject-introspection-dbg is not set +# CONFIG_gobject-introspection-dev is not set + +# +# gtk+ +# +# CONFIG_gtkPLUS is not set +# CONFIG_gtkPLUS-dev is not set +# CONFIG_libgail is not set +# CONFIG_gtkPLUS-dbg is not set +# CONFIG_gtk-demo is not set + +# +# gtk+3 +# +# CONFIG_gtkPLUS3 is not set +# CONFIG_gtkPLUS3-dev is not set +# CONFIG_gtkPLUS3-dbg is not set +# CONFIG_gtkPLUS3-demo is not set + +# +# harfbuzz +# +# CONFIG_harfbuzz is not set +# CONFIG_harfbuzz-dev is not set +# CONFIG_harfbuzz-bin is not set +# CONFIG_harfbuzz-icu-dev is not set +# CONFIG_harfbuzz-dbg is not set +# CONFIG_harfbuzz-icu is not set + +# +# libaio +# +# CONFIG_libaio is not set +# CONFIG_libaio-dev is not set +# CONFIG_libaio-dbg is not set + +# +# libcap +# +# CONFIG_libcap is not set +# CONFIG_libcap-bin is not set +# CONFIG_libcap-dbg is not set +# CONFIG_libcap-dev is not set + +# +# libcgroup +# +# CONFIG_libcgroup is not set +# CONFIG_libcgroup-dbg is not set +# CONFIG_libcgroup-dev is not set + +# +# libdaemon +# +# CONFIG_libdaemon is not set +# CONFIG_libdaemon-dbg is not set +# CONFIG_libdaemon-dev is not set + +# +# libdmx +# +# CONFIG_libdmx is not set +# CONFIG_libdmx-dbg is not set +# CONFIG_libdmx-dev is not set + +# +# libeigen +# +# CONFIG_libeigen-dev is not set +# CONFIG_libeigen-dbg is not set + +# +# libepoxy +# +# CONFIG_libepoxy is not set +# CONFIG_libepoxy-dev is not set +# CONFIG_libepoxy-dbg is not set + +# +# libevdev +# +# CONFIG_libevdev is not set +# CONFIG_libevdev-dev is not set +# CONFIG_libevdev-dbg is not set + +# +# libevent +# +# CONFIG_libevent is not set +# CONFIG_libevent-dbg is not set +# CONFIG_libevent-dev is not set + +# +# libexif +# +# CONFIG_libexif is not set +# CONFIG_libexif-dbg is not set +# CONFIG_libexif-dev is not set + +# +# libffi +# +# CONFIG_libffi is not set +# CONFIG_libffi-dbg is not set +# CONFIG_libffi-dev is not set + +# +# libfontenc +# +# CONFIG_libfontenc is not set +# CONFIG_libfontenc-dev is not set +# CONFIG_libfontenc-dbg is not set + +# +# libgcrypt +# +# CONFIG_libgcrypt is not set +# CONFIG_dumpsexp-dev is not set +# CONFIG_libgcrypt-dbg is not set +# CONFIG_libgcrypt-dev is not set + +# +# libgcc +# +# CONFIG_libgcc is not set +# CONFIG_libgcc-dbg is not set +# CONFIG_libgcc-dev is not set + +# +# libgpg-error +# +# CONFIG_libgpg-error is not set +# CONFIG_libgpg-error-dbg is not set +# CONFIG_libgpg-error-dev is not set + +# +# libgphoto2 +# +# CONFIG_libgphoto2 is not set +# CONFIG_libgphoto2-dbg is not set +# CONFIG_libgphoto2-camlibs is not set +# CONFIG_libgphoto2-dev is not set +# CONFIG_libgphoto2-bin is not set +# CONFIG_libgphotoport is not set + +# +# libgpiod +# +# CONFIG_libgpiod is not set +# CONFIG_libgpiod-dev is not set +# CONFIG_libgpiod-dbg is not set + +# +# libgudev +# +# CONFIG_libgudev is not set +# CONFIG_libgudev-dev is not set +# CONFIG_libgudev-dbg is not set + +# +# libhugetlbfs +# +# CONFIG_libhugetlbfs is not set +# CONFIG_libhugetlbfs-tests is not set +# CONFIG_libhugetlbfs-dbg is not set +# CONFIG_libhugetlbfs-dev is not set + +# +# libical +# +# CONFIG_libical is not set +# CONFIG_libical-dev is not set +# CONFIG_libical-dbg is not set + +# +# libice +# +# CONFIG_libice is not set +# CONFIG_libice-dbg is not set +# CONFIG_libice-dev is not set + +# +# libid3tag +# +# CONFIG_libid3tag is not set +# CONFIG_libid3tag-dev is not set +# CONFIG_libid3tag-dbg is not set + +# +# libidn +# +# CONFIG_libidn is not set +# CONFIG_libidn-dbg is not set +# CONFIG_idn is not set +# CONFIG_libidn-dev is not set + +# +# libinput +# +# CONFIG_libinput is not set +# CONFIG_libinput-dev is not set +# CONFIG_libinput-dbg is not set + +# +# libjpeg-turbo +# +# CONFIG_libjpeg-turbo is not set +# CONFIG_jpeg-tools is not set +# CONFIG_libturbojpeg is not set +# CONFIG_libjpeg-turbo-dbg is not set +# CONFIG_libjpeg-turbo-dev is not set + +# +# libmali-xlnx +# +# CONFIG_libmali-xlnx is not set +# CONFIG_libmali-xlnx-dbg is not set +# CONFIG_libmali-xlnx-dev is not set + +# +# libmetal +# +# CONFIG_libmetal is not set +# CONFIG_libmetal-dev is not set +# CONFIG_libmetal-dbg is not set +# CONFIG_libmetal-demos is not set + +# +# libmpc +# +# CONFIG_libmpc is not set +# CONFIG_libmpc-dbg is not set +# CONFIG_libmpc-dev is not set + +# +# libnet +# +# CONFIG_libnet is not set +# CONFIG_libnet-dbg is not set +# CONFIG_libnet-dev is not set + +# +# libnewt +# +# CONFIG_libnewt is not set +# CONFIG_libnewt-dev is not set +# CONFIG_libnewt-dbg is not set +# CONFIG_whiptail is not set + +# +# libnotify +# +# CONFIG_libnotify is not set +# CONFIG_libnotify-dev is not set +# CONFIG_libnotify-dbg is not set + +# +# libnss-mdns +# +# CONFIG_libnss-mdns is not set +# CONFIG_libnss-mdns-dbg is not set +# CONFIG_libnss-mdns-dev is not set + +# +# libogg +# +# CONFIG_libogg is not set +# CONFIG_libogg-dev is not set +# CONFIG_libogg-dbg is not set + +# +# libomxil +# +# CONFIG_libomxil is not set +# CONFIG_libomxil-dev is not set +# CONFIG_libomxil-dbg is not set + +# +# libpciaccess +# +# CONFIG_libpciaccess is not set +# CONFIG_libpciaccess-dev is not set +# CONFIG_libpciaccess-dbg is not set + +# +# libpng +# +# CONFIG_libpng is not set +# CONFIG_libpng-dbg is not set +# CONFIG_libpng-dev is not set +# CONFIG_libpng-tools is not set + +# +# libproxy +# +# CONFIG_libproxy is not set +# CONFIG_libproxy-dbg is not set +# CONFIG_libproxy-dev is not set + +# +# libsamplerate0 +# +# CONFIG_libsamplerate0 is not set +# CONFIG_libsamplerate0-dev is not set +# CONFIG_libsamplerate0-dbg is not set + +# +# libsecret +# +# CONFIG_libsecret is not set +# CONFIG_libsecret-dbg is not set +# CONFIG_libsecret-dev is not set + +# +# libsm +# +# CONFIG_libsm is not set +# CONFIG_libsm-dev is not set +# CONFIG_libsm-dbg is not set + +# +# libtasn1 +# +# CONFIG_libtasn1 is not set +# CONFIG_libtasn1-dbg is not set +# CONFIG_libtasn1-dev is not set +# CONFIG_libtasn1-bin is not set + +# +# libtheora +# +# CONFIG_libtheora is not set +# CONFIG_libtheora-dev is not set +# CONFIG_libtheora-dbg is not set + +# +# libtool +# +# CONFIG_libtool is not set +# CONFIG_libtool-dev is not set +# CONFIG_libltdl is not set +# CONFIG_libtool-dbg is not set + +# +# liburcu +# +# CONFIG_liburcu is not set +# CONFIG_liburcu-dbg is not set +# CONFIG_liburcu-dev is not set + +# +# libusb-compat +# +# CONFIG_libusb-compat is not set +# CONFIG_libusb-compat-dbg is not set +# CONFIG_libusb-compat-dev is not set + +# +# libusb1 +# +# CONFIG_libusb1 is not set +# CONFIG_libusb1-dev is not set +# CONFIG_libusb1-dbg is not set + +# +# libvorbis +# +# CONFIG_libvorbis is not set +# CONFIG_libvorbis-dev is not set +# CONFIG_libvorbis-dbg is not set + +# +# libwebp +# +# CONFIG_libwebp is not set +# CONFIG_libwebp-dbg is not set +# CONFIG_libwebp-bin is not set +# CONFIG_libwebp-dev is not set + +# +# libx11 +# +# CONFIG_libx11 is not set +# CONFIG_libx11-xcb is not set +# CONFIG_libx11-dev is not set +# CONFIG_libx11-dbg is not set + +# +# libxau +# +# CONFIG_libxau is not set +# CONFIG_libxau-dbg is not set +# CONFIG_libxau-dev is not set + +# +# libxcomposite +# +# CONFIG_libxcomposite is not set +# CONFIG_libxcomposite-dbg is not set +# CONFIG_libxcomposite-dev is not set + +# +# libxcursor +# +# CONFIG_libxcursor is not set +# CONFIG_libxcursor-dbg is not set +# CONFIG_libxcursor-dev is not set + +# +# libxdamage +# +# CONFIG_libxdamage is not set +# CONFIG_libxdamage-dbg is not set +# CONFIG_libxdamage-dev is not set + +# +# libxdmcp +# +# CONFIG_libxdmcp is not set +# CONFIG_libxdmcp-dbg is not set +# CONFIG_libxdmcp-dev is not set + +# +# libxext +# +# CONFIG_libxext is not set +# CONFIG_libxext-dev is not set +# CONFIG_libxext-dbg is not set + +# +# libxfixes +# +# CONFIG_libxfixes is not set +# CONFIG_libxfixes-dev is not set +# CONFIG_libxfixes-dbg is not set + +# +# libxfont +# +# CONFIG_libxfont is not set +# CONFIG_libxfont-dev is not set +# CONFIG_libxfont-dbg is not set + +# +# libxft +# +# CONFIG_libxft is not set +# CONFIG_libxft-dbg is not set +# CONFIG_libxft-dev is not set + +# +# libxi +# +# CONFIG_libxi is not set +# CONFIG_libxi-dbg is not set +# CONFIG_libxi-dev is not set + +# +# libxinerama +# +# CONFIG_libxinerama is not set +# CONFIG_libxinerama-dbg is not set +# CONFIG_libxinerama-dev is not set + +# +# libxkbcommon +# +# CONFIG_libxkbcommon is not set +# CONFIG_libxkbcommon-dev is not set +# CONFIG_libxkbcommon-dbg is not set + +# +# libxkbfile +# +# CONFIG_libxkbfile is not set +# CONFIG_libxkbfile-dbg is not set +# CONFIG_libxkbfile-dev is not set + +# +# libxml-parser-perl +# +# CONFIG_libxml-parser-perl is not set +# CONFIG_libxml-parser-perl-dev is not set +# CONFIG_libxml-parser-perl-dbg is not set + +# +# libxml2 +# +# CONFIG_libxml2 is not set +# CONFIG_libxml2-python is not set +# CONFIG_libxml2-dbg is not set +# CONFIG_libxml2-dev is not set + +# +# libxmu +# +# CONFIG_libxmu is not set +# CONFIG_libxmu-dbg is not set +# CONFIG_libxmuu is not set +# CONFIG_libxmu-dev is not set + +# +# libxrandr +# +# CONFIG_libxrandr is not set +# CONFIG_libxrandr-dbg is not set +# CONFIG_libxrandr-dev is not set + +# +# libxrender +# +# CONFIG_libxrender is not set +# CONFIG_libxrender-dev is not set +# CONFIG_libxrender-dbg is not set + +# +# libxres +# +# CONFIG_libxres is not set +# CONFIG_libxres-dbg is not set +# CONFIG_libxres-dev is not set + +# +# libxslt +# +# CONFIG_libxslt is not set +# CONFIG_libxslt-dbg is not set +# CONFIG_libxslt-bin is not set +# CONFIG_libxslt-dev is not set + +# +# libxt +# +# CONFIG_libxt is not set +# CONFIG_libxt-dev is not set +# CONFIG_libxt-dbg is not set + +# +# libxtst +# +# CONFIG_libxtst is not set +# CONFIG_libxtst-dbg is not set +# CONFIG_libxtst-dev is not set + +# +# libxv +# +# CONFIG_libxv is not set +# CONFIG_libxv-dbg is not set +# CONFIG_libxv-dev is not set + +# +# libxxf86vm +# +# CONFIG_libxxf86vm is not set +# CONFIG_libxxf86vm-dbg is not set +# CONFIG_libxxf86vm-dev is not set + +# +# lzo +# +# CONFIG_lzo is not set +# CONFIG_lzo-dbg is not set +# CONFIG_lzo-dev is not set + +# +# mtdev +# +# CONFIG_mtdev is not set +# CONFIG_mtdev-dbg is not set +# CONFIG_mtdev-dev is not set + +# +# multimedia +# + +# +# alsa-lib +# +# CONFIG_alsa-lib is not set +# CONFIG_alsa-server is not set +# CONFIG_libasound is not set +# CONFIG_alsa-conf is not set +# CONFIG_alsa-lib-dbg is not set +# CONFIG_alsa-conf-base is not set +# CONFIG_alsa-lib-dev is not set +# CONFIG_alsa-oss is not set + +# +# libsndfile1 +# +# CONFIG_libsndfile1 is not set +# CONFIG_libsndfile1-dev is not set +# CONFIG_libsndfile1-bin is not set +# CONFIG_libsndfile1-dbg is not set + +# +# pulseaudio +# +# CONFIG_pulseaudio is not set +# CONFIG_pulseaudio-module-console-kit is not set +# CONFIG_pulseaudio-bash-completion is not set +# CONFIG_libpulse is not set +# CONFIG_pulseaudio-misc is not set +# CONFIG_pulseaudio-dev is not set +# CONFIG_libpulse-simple is not set +# CONFIG_pulseaudio-dbg is not set +# CONFIG_libpulsecommon is not set +# CONFIG_pulseaudio-server is not set +# CONFIG_libpulsecore is not set +# CONFIG_libpulse-mainloop-glib is not set + +# +# taglib +# +# CONFIG_taglib is not set +# CONFIG_taglib-dev is not set +# CONFIG_taglib-dbg is not set +# CONFIG_taglib-c is not set + +# +# ncurses +# +# CONFIG_ncurses is not set +# CONFIG_ncurses-terminfo is not set +# CONFIG_ncurses-dev is not set +# CONFIG_ncurses-terminfo-base is not set +# CONFIG_ncurses-tools is not set +# CONFIG_ncurses-dbg is not set + +# +# neon +# +# CONFIG_neon is not set +# CONFIG_neon-dbg is not set +# CONFIG_neon-dev is not set + +# +# nettle +# +# CONFIG_nettle is not set +# CONFIG_nettle-dbg is not set +# CONFIG_nettle-dev is not set + +# +# network +# + +# +# libnl +# +# CONFIG_libnl is not set +# CONFIG_libnl-dbg is not set +# CONFIG_libnl-idiag is not set +# CONFIG_libnl-dev is not set +# CONFIG_libnl-cli is not set +# CONFIG_libnl-nf is not set +# CONFIG_libnl-route is not set +# CONFIG_libnl-xfrm is not set +# CONFIG_libnl-genl is not set + +# +# libpcap +# +# CONFIG_libpcap is not set +# CONFIG_libpcap-dev is not set +# CONFIG_libpcap-dbg is not set + +# +# libsocketcan +# +# CONFIG_libsocketcan is not set +# CONFIG_libsocketcan-dev is not set +# CONFIG_libsocketcan-dbg is not set + +# +# libtirpc +# +# CONFIG_libtirpc is not set +# CONFIG_libtirpc-dbg is not set +# CONFIG_libtirpc-dev is not set + +# +# openssl +# +# CONFIG_openssl is not set +# CONFIG_openssl-bin is not set +# CONFIG_openssl-misc is not set +# CONFIG_openssl-conf is not set +# CONFIG_openssl-dbg is not set +# CONFIG_libcrypto is not set +# CONFIG_openssl-dev is not set +# CONFIG_libssl is not set +# CONFIG_openssl-engines is not set + +# +# open-amp +# +# CONFIG_open-amp is not set +# CONFIG_open-amp-dev is not set +# CONFIG_open-amp-dbg is not set +# CONFIG_open-amp-demos is not set + +# +# opencv +# +# CONFIG_opencv is not set +# CONFIG_opencv-dbg is not set +# CONFIG_opencv-apps is not set +# CONFIG_opencv-dev is not set +# CONFIG_opencv-samples is not set + +# +# pango +# +# CONFIG_pango is not set +# CONFIG_pango-dev is not set +# CONFIG_pango-dbg is not set + +# +# popt +# +# CONFIG_popt is not set +# CONFIG_popt-dev is not set +# CONFIG_popt-dbg is not set + +# +# readline +# +# CONFIG_readline is not set +# CONFIG_readline-dev is not set +# CONFIG_readline-dbg is not set + +# +# sbc +# +# CONFIG_sbc is not set +# CONFIG_sbc-dev is not set +# CONFIG_sbc-dbg is not set + +# +# slang +# +# CONFIG_slang is not set +# CONFIG_slang-dev is not set +# CONFIG_slang-dbg is not set + +# +# speex +# +# CONFIG_speex is not set +# CONFIG_speex-dev is not set +# CONFIG_speex-dbg is not set + +# +# speexdsp +# +# CONFIG_speexdsp is not set +# CONFIG_speexdsp-dev is not set +# CONFIG_speexdsp-dbg is not set + +# +# sqlite3 +# +# CONFIG_sqlite3 is not set +# CONFIG_libsqlite3 is not set +# CONFIG_libsqlite3-dev is not set +# CONFIG_sqlite3-dbg is not set + +# +# startup-notification +# +# CONFIG_startup-notification is not set +# CONFIG_startup-notification-dev is not set +# CONFIG_startup-notification-dbg is not set + +# +# tremor +# +# CONFIG_tremor is not set +# CONFIG_tremor-dbg is not set +# CONFIG_tremor-dev is not set + +# +# which +# +# CONFIG_which is not set +# CONFIG_which-dev is not set +# CONFIG_which-dbg is not set + +# +# xrt +# +# CONFIG_xrt is not set +# CONFIG_xrt-dev is not set +# CONFIG_xrt-dbg is not set + +# +# zocl +# +# CONFIG_zocl is not set +# CONFIG_zocl-dev is not set +# CONFIG_zocl-dbg is not set + +# +# opencl-clhpp +# +# CONFIG_opencl-clhpp is not set + +# +# opencl-headers +# +# CONFIG_opencl-headers is not set + +# +# protobuf +# +# CONFIG_protobuf is not set + +# +# zlib +# +# CONFIG_zlib is not set +# CONFIG_zlib-dev is not set +# CONFIG_zlib-dbg is not set + +# +# misc +# + +# +# alsa-state +# +# CONFIG_alsa-state is not set +# CONFIG_alsa-state-dev is not set +# CONFIG_alsa-states is not set +# CONFIG_alsa-state-dbg is not set + +# +# alsa-utils-scripts +# +# CONFIG_alsa-utils-scripts is not set + +# +# apache2 +# +# CONFIG_apache2 is not set +# CONFIG_apache2-dbg is not set +# CONFIG_apache2-dev is not set + +# +# at-spi2-atk +# +# CONFIG_at-spi2-atk is not set +# CONFIG_at-spi2-atk-dbg is not set +# CONFIG_at-spi2-atk-dev is not set +# CONFIG_at-spi2-atk-gtk2 is not set +# CONFIG_at-spi2-atk-gnome is not set + +# +# at-spi2-core +# +# CONFIG_at-spi2-core is not set +# CONFIG_at-spi2-core-dev is not set +# CONFIG_at-spi2-core-dbg is not set + +# +# babeltrace +# +# CONFIG_babeltrace is not set +# CONFIG_babeltrace-dbg is not set +# CONFIG_babeltrace-dev is not set + +# +# blktool +# +# CONFIG_blktool is not set +# CONFIG_blktool-dbg is not set +# CONFIG_blktool-dev is not set + +# +# blktrace +# +# CONFIG_blktrace is not set +# CONFIG_blktrace-dbg is not set +# CONFIG_blktrace-dev is not set + +# +# ca-certificates +# +# CONFIG_ca-certificates is not set +# CONFIG_ca-certificates-dev is not set +# CONFIG_ca-certificates-dbg is not set + +# +# chkconfig +# +# CONFIG_chkconfig is not set +# CONFIG_chkconfig-alternatives is not set +# CONFIG_chkconfig-dbg is not set +# CONFIG_chkconfig-dev is not set + +# +# chrpath +# +# CONFIG_chrpath is not set +# CONFIG_chrpath-dev is not set +# CONFIG_chrpath-dbg is not set + +# +# connman +# +# CONFIG_connman is not set +# CONFIG_connman-tests is not set +# CONFIG_connman-dbg is not set +# CONFIG_connman-dev is not set +# CONFIG_connman-wait-online is not set +# CONFIG_connman-client is not set +# CONFIG_connman-tools is not set + +# +# connman-conf +# +# CONFIG_connman-conf-dbg is not set + +# +# consolekit +# +# CONFIG_consolekit is not set +# CONFIG_consolekit-dbg is not set +# CONFIG_consolekit-dev is not set + +# +# coreutils +# +# CONFIG_coreutils is not set +# CONFIG_coreutils-dbg is not set +# CONFIG_coreutils-dev is not set + +# +# cpufrequtils +# +# CONFIG_cpufrequtils is not set +# CONFIG_cpufrequtils-dbg is not set +# CONFIG_cpufrequtils-dev is not set + +# +# cryptodev-linux +# +# CONFIG_cryptodev-linux is not set +# CONFIG_cryptodev-linux-dev is not set +# CONFIG_cryptodev-linux-dbg is not set + +# +# dstat +# +# CONFIG_dstat is not set +# CONFIG_dstat-dev is not set +# CONFIG_dstat-dbg is not set + +# +# encodings +# +# CONFIG_encodings is not set +# CONFIG_encodings-dev is not set +# CONFIG_encodings-dbg is not set + +# +# epiphany +# +# CONFIG_epiphany is not set +# CONFIG_epiphany-dev is not set +# CONFIG_epiphany-dbg is not set + +# +# eudev +# +# CONFIG_eudev is not set +# CONFIG_libudev is not set +# CONFIG_eudev-hwdb is not set +# CONFIG_eudev-dev is not set +# CONFIG_eudev-dbg is not set +CONFIG_udev-extraconf=y + +# +# fbset +# +# CONFIG_fbset is not set +# CONFIG_fbset-dev is not set +# CONFIG_fbset-dbg is not set + +# +# fbset-modes +# +# CONFIG_fbset-modes is not set +# CONFIG_fbset-modes-dbg is not set +# CONFIG_fbset-modes-dev is not set + +# +# font-util +# +# CONFIG_font-util is not set +# CONFIG_font-util-dev is not set +# CONFIG_font-util-dbg is not set + +# +# gcc-runtime +# +# CONFIG_libstdcPLUSPLUS-dev is not set +# CONFIG_libstdcPLUSPLUS is not set + +# +# gcr +# +# CONFIG_gcr is not set +# CONFIG_gcr-dev is not set +# CONFIG_gcr-dbg is not set + +# +# gdb +# +# CONFIG_gdb is not set +# CONFIG_gdb-dev is not set +# CONFIG_gdbserver is not set +# CONFIG_gdb-dbg is not set + +# +# glib-2.0 +# +# CONFIG_glib-2.0 is not set +# CONFIG_glib-2.0-dbg is not set +# CONFIG_glib-2.0-dev is not set +# CONFIG_glib-2.0-codegen is not set +# CONFIG_glib-2.0-bash-completion is not set +# CONFIG_glib-2.0-utils is not set + +# +# glibc +# +# CONFIG_glibc is not set +# CONFIG_glibc-dev is not set +# CONFIG_glibc-dbg is not set +# CONFIG_ldd is not set + +# +# gnome-desktop-testing +# +# CONFIG_gnome-desktop-testing is not set +# CONFIG_gnome-desktop-testing-dbg is not set +# CONFIG_gnome-desktop-testing-dev is not set + +# +# gnutls +# +# CONFIG_gnutls is not set +# CONFIG_gnutls-bin is not set +# CONFIG_gnutls-xx is not set +# CONFIG_gnutls-dbg is not set +# CONFIG_gnutls-openssl is not set +# CONFIG_gnutls-dev is not set + +# +# gsettings-desktop-schemas +# +# CONFIG_gsettings-desktop-schemas is not set +# CONFIG_gsettings-desktop-schemas-dev is not set +# CONFIG_gsettings-desktop-schemas-dbg is not set + +# +# gst-player +# +# CONFIG_gst-player is not set + +# +# gstreamer1.0-meta-base +# +# CONFIG_gstreamer1.0-meta-base is not set +# CONFIG_gstreamer1.0-meta-video is not set +# CONFIG_gstreamer1.0-meta-video-dbg is not set +# CONFIG_gstreamer1.0-meta-debug-dev is not set +# CONFIG_gstreamer1.0-meta-x11-base-dev is not set +# CONFIG_gstreamer1.0-meta-audio-dbg is not set +# CONFIG_gstreamer1.0-meta-audio is not set +# CONFIG_gstreamer1.0-meta-x11-base is not set +# CONFIG_gstreamer1.0-meta-video-dev is not set +# CONFIG_gstreamer1.0-meta-x11-base-dbg is not set +# CONFIG_gstreamer1.0-meta-base-dev is not set +# CONFIG_gstreamer1.0-meta-base-dbg is not set +# CONFIG_gstreamer1.0-meta-debug is not set +# CONFIG_gstreamer1.0-meta-audio-dev is not set +# CONFIG_gstreamer1.0-meta-debug-dbg is not set + +# +# gstreamer1.0-plugins-bad +# +# CONFIG_gstreamer1.0-plugins-bad is not set +# CONFIG_gstreamer1.0-plugins-bad-meta is not set +# CONFIG_gstreamer1.0-plugins-bad-dev is not set +# CONFIG_gstreamer1.0-plugins-bad-dbg is not set + +# +# gstreamer1.0-plugins-base +# +# CONFIG_gstreamer1.0-plugins-base is not set +# CONFIG_gstreamer1.0-plugins-base-apps is not set +# CONFIG_gstreamer1.0-plugins-base-dev is not set +# CONFIG_gstreamer1.0-plugins-base-dbg is not set +# CONFIG_gstreamer1.0-plugins-base-meta is not set + +# +# gstreamer1.0-plugins-good +# +# CONFIG_gstreamer1.0-plugins-good is not set +# CONFIG_gstreamer1.0-plugins-good-dev is not set +# CONFIG_gstreamer1.0-plugins-good-dbg is not set +# CONFIG_gstreamer1.0-plugins-good-meta is not set + +# +# hicolor-icon-theme +# +# CONFIG_hicolor-icon-theme is not set +# CONFIG_hicolor-icon-theme-dev is not set +# CONFIG_hicolor-icon-theme-dbg is not set + +# +# hdmi-module +# +# CONFIG_kernel-module-hdmi is not set + +# +# icu +# +# CONFIG_icu is not set +# CONFIG_icu-dbg is not set +# CONFIG_icu-dev is not set +# CONFIG_libicudata is not set +# CONFIG_libicuio is not set +# CONFIG_libicui18n is not set +# CONFIG_libicuuc is not set +# CONFIG_libicutu is not set + +# +# iotop +# +# CONFIG_iotop is not set +# CONFIG_iotop-dev is not set +# CONFIG_iotop-dbg is not set + +# +# iptables +# +# CONFIG_iptables is not set +# CONFIG_iptables-dev is not set +# CONFIG_iptables-dbg is not set + +# +# iptraf +# +# CONFIG_iptraf is not set + +# +# iso-codes +# +# CONFIG_iso-codes is not set +# CONFIG_iso-codes-dbg is not set +# CONFIG_iso-codes-dev is not set + +# +# json-c +# +# CONFIG_json-c is not set +# CONFIG_json-c-dev is not set +# CONFIG_json-c-dbg is not set + +# +# l3afpad +# +# CONFIG_l3afpad is not set +# CONFIG_l3afpad-dev is not set +# CONFIG_l3afpad-dbg is not set + +# +# lttng-ust +# +# CONFIG_lttng-ust is not set +# CONFIG_lttng-ust-dev is not set +# CONFIG_lttng-ust-dbg is not set +# CONFIG_lttng-ust-bin is not set + +# +# m4 +# +# CONFIG_m4 is not set +# CONFIG_m4-dev is not set +# CONFIG_m4-dbg is not set + +# +# matchbox-config-gtk +# +# CONFIG_matchbox-config-gtk is not set +# CONFIG_matchbox-config-gtk-dbg is not set +# CONFIG_matchbox-config-gtk-dev is not set + +# +# matchbox-panel-2 +# +# CONFIG_matchbox-panel-2 is not set +# CONFIG_matchbox-panel-2-dbg is not set +# CONFIG_matchbox-panel-2-dev is not set + +# +# mdadm +# +# CONFIG_mdadm is not set +# CONFIG_mdadm-dbg is not set +# CONFIG_mdadm-dev is not set + +# +# mesa-gl +# +# CONFIG_mesa-gl-dev is not set +# CONFIG_libgl-mesa is not set +# CONFIG_mesa-megadriver is not set +# CONFIG_libglapi-dev is not set +# CONFIG_libglapi is not set +# CONFIG_libgl-mesa-dev is not set +# CONFIG_mesa-gl-dbg is not set + +# +# mkfontdir +# +# CONFIG_mkfontdir is not set +# CONFIG_mkfontdir-dbg is not set +# CONFIG_mkfontdir-dev is not set + +# +# mkfontscale +# +# CONFIG_mkfontscale is not set +# CONFIG_mkfontscale-dbg is not set +# CONFIG_mkfontscale-dev is not set + +# +# net-tools +# +# CONFIG_net-tools is not set +# CONFIG_net-tools-dbg is not set +# CONFIG_net-tools-dev is not set + +# +# nicstat +# +# CONFIG_nicstat is not set +# CONFIG_nicstat-dbg is not set +# CONFIG_nicstat-dev is not set + +# +# ofono +# +# CONFIG_ofono is not set +# CONFIG_ofono-dbg is not set +# CONFIG_ofono-dev is not set +# CONFIG_ofono-tests is not set + +# +# openamp-fw-echo-testd +# +# CONFIG_openamp-fw-echo-testd is not set +# CONFIG_openamp-fw-echo-testd-dev is not set +# CONFIG_openamp-fw-echo-testd-dbg is not set + +# +# openamp-fw-mat-muld +# +# CONFIG_openamp-fw-mat-muld is not set +# CONFIG_openamp-fw-mat-muld-dev is not set +# CONFIG_openamp-fw-mat-muld-dbg is not set + +# +# openamp-fw-rpc-demo +# +# CONFIG_openamp-fw-rpc-demo is not set +# CONFIG_openamp-fw-rpc-demo-dbg is not set +# CONFIG_openamp-fw-rpc-demo-dev is not set + +# +# opkg-arch-config +# +# CONFIG_opkg-arch-config is not set +# CONFIG_opkg-arch-config-dbg is not set +# CONFIG_opkg-arch-config-dev is not set + +# +# orc +# +# CONFIG_orc is not set +# CONFIG_orc-dbg is not set +# CONFIG_orc-dev is not set + +# +# p11-kit +# +# CONFIG_p11-kit is not set +# CONFIG_p11-kit-dbg is not set +# CONFIG_p11-kit-dev is not set + +# +# packagegroup-core-boot +# +CONFIG_packagegroup-core-boot=y +# CONFIG_packagegroup-core-boot-dev is not set +# CONFIG_packagegroup-core-boot-dbg is not set + +# +# packagegroup-core-buildessential +# +# CONFIG_packagegroup-core-buildessential is not set +# CONFIG_packagegroup-core-buildessential-dbg is not set +# CONFIG_packagegroup-core-buildessential-dev is not set + +# +# packagegroup-core-sdk +# +# CONFIG_packagegroup-core-sdk is not set +# CONFIG_packagegroup-core-sdk-dbg is not set +# CONFIG_packagegroup-core-sdk-dev is not set + +# +# packagegroup-core-ssh-dropbear +# +CONFIG_packagegroup-core-ssh-dropbear=y +# CONFIG_packagegroup-core-ssh-dropbear-dev is not set +# CONFIG_packagegroup-core-ssh-dropbear-dbg is not set + +# +# packagegroup-core-standalone-sdk-target +# +# CONFIG_packagegroup-core-standalone-sdk-target is not set +# CONFIG_packagegroup-core-standalone-sdk-target-dbg is not set +# CONFIG_packagegroup-core-standalone-sdk-target-dev is not set + +# +# packagegroup-core-tools-debug +# +# CONFIG_packagegroup-core-tools-debug is not set +# CONFIG_packagegroup-core-tools-debug-dev is not set +# CONFIG_packagegroup-core-tools-debug-dbg is not set + +# +# packagegroup-core-tools-profile +# +# CONFIG_packagegroup-core-tools-profile is not set +# CONFIG_packagegroup-core-tools-profile-dev is not set +# CONFIG_packagegroup-core-tools-profile-dbg is not set + +# +# packagegroup-core-tools-testapps +# +# CONFIG_packagegroup-core-tools-testapps is not set +# CONFIG_packagegroup-core-tools-testapps-dev is not set +# CONFIG_packagegroup-core-tools-testapps-dbg is not set + +# +# packagegroup-core-x11 +# +# CONFIG_packagegroup-core-x11 is not set +# CONFIG_packagegroup-core-x11-utils-dbg is not set +# CONFIG_packagegroup-core-x11-utils is not set +# CONFIG_packagegroup-core-x11-utils-dev is not set +# CONFIG_packagegroup-core-x11-dev is not set +# CONFIG_packagegroup-core-x11-dbg is not set + +# +# packagegroup-core-x11-base +# +# CONFIG_packagegroup-core-x11-base is not set +# CONFIG_packagegroup-core-x11-base-dev is not set +# CONFIG_packagegroup-core-x11-base-dbg is not set + +# +# packagegroup-core-x11-xserver +# +# CONFIG_packagegroup-core-x11-xserver is not set +# CONFIG_packagegroup-core-x11-xserver-dev is not set +# CONFIG_packagegroup-core-x11-xserver-dbg is not set + +# +# packagegroup-self-hosted +# +# CONFIG_packagegroup-self-hosted is not set +# CONFIG_packagegroup-self-hosted-debug-dbg is not set +# CONFIG_packagegroup-self-hosted-dev is not set +# CONFIG_packagegroup-self-hosted-debug is not set +# CONFIG_packagegroup-self-hosted-sdk is not set +# CONFIG_packagegroup-self-hosted-extended-dbg is not set +# CONFIG_packagegroup-self-hosted-graphics-dbg is not set +# CONFIG_packagegroup-self-hosted-extended is not set +# CONFIG_packagegroup-self-hosted-host-tools-dev is not set +# CONFIG_packagegroup-self-hosted-debug-dev is not set +# CONFIG_packagegroup-self-hosted-sdk-dbg is not set +# CONFIG_packagegroup-self-hosted-sdk-dev is not set +# CONFIG_packagegroup-self-hosted-extended-dev is not set +# CONFIG_packagegroup-self-hosted-graphics is not set +# CONFIG_packagegroup-self-hosted-host-tools-dbg is not set +# CONFIG_packagegroup-self-hosted-dbg is not set +# CONFIG_packagegroup-self-hosted-host-tools is not set +# CONFIG_packagegroup-self-hosted-graphics-dev is not set + +# +# perf +# +# CONFIG_perf is not set +# CONFIG_perf-python is not set +# CONFIG_perf-dbg is not set +# CONFIG_perf-dev is not set +# CONFIG_perf-tests is not set + +# +# pixman +# +# CONFIG_pixman is not set +# CONFIG_pixman-dbg is not set +# CONFIG_pixman-dev is not set + +# +# powertop +# +# CONFIG_powertop is not set +# CONFIG_powertop-dbg is not set +# CONFIG_powertop-dev is not set + +# +# ptest-runner +# +# CONFIG_ptest-runner is not set +# CONFIG_ptest-runner-dev is not set +# CONFIG_ptest-runner-dbg is not set + +# +# python3 +# +# CONFIG_python3 is not set +# CONFIG_python3-crypt is not set +# CONFIG_python3-unixadmin is not set +# CONFIG_python3-io is not set +# CONFIG_python3-pydoc is not set +# CONFIG_python3-codecs is not set +# CONFIG_python3-pprint is not set +# CONFIG_python3-datetime is not set +# CONFIG_python3-2to3 is not set +# CONFIG_python3-modules is not set +# CONFIG_python3-xml is not set +# CONFIG_python3-numbers is not set +# CONFIG_python3-pyvenv is not set +# CONFIG_python3-tests is not set +# CONFIG_python3-netclient is not set +# CONFIG_python3-netserver is not set +# CONFIG_python3-math is not set +# CONFIG_python3-asyncio is not set +# CONFIG_python3-tkinter is not set +# CONFIG_python3-compression is not set +# CONFIG_python3-gdbm is not set +# CONFIG_python3-idle is not set +# CONFIG_python3-core is not set +# CONFIG_python3-smtpd is not set +# CONFIG_python3-resource is not set +# CONFIG_python3-terminal is not set +# CONFIG_python3-shell is not set +# CONFIG_python3-db is not set +# CONFIG_python3-threading is not set +# CONFIG_python3-email is not set +# CONFIG_python3-stringold is not set +# CONFIG_python3-unittest is not set +# CONFIG_python3-misc is not set +# CONFIG_python3-mailbox is not set +# CONFIG_python3-pkgutil is not set +# CONFIG_python3-mmap is not set +# CONFIG_python3-json is not set +# CONFIG_python3-audio is not set +# CONFIG_python3-distutils is not set +# CONFIG_python3-mime is not set +# CONFIG_python3-multiprocessing is not set +# CONFIG_python3-html is not set +# CONFIG_python3-image is not set +# CONFIG_python3-difflib is not set +# CONFIG_python3-dev is not set +# CONFIG_python3-syslog is not set +# CONFIG_python3-curses is not set +# CONFIG_libpython3 is not set +# CONFIG_python3-logging is not set +# CONFIG_python3-profile is not set +# CONFIG_python3-xmlrpc is not set +# CONFIG_python3-ctypes is not set +# CONFIG_python3-sqlite3 is not set +# CONFIG_python3-fcntl is not set +# CONFIG_python3-compile is not set +# CONFIG_python3-pickle is not set +# CONFIG_python3-dbg is not set +# CONFIG_python3-debugger is not set + +# +# python3-async +# +# CONFIG_python3-async is not set +# CONFIG_python3-async-dbg is not set +# CONFIG_python3-async-dev is not set + +# +# python3-git +# +# CONFIG_python3-git is not set +# CONFIG_python3-git-dev is not set +# CONFIG_python3-git-dbg is not set + +# +# python3-gitdb +# +# CONFIG_python3-gitdb is not set +# CONFIG_python3-gitdb-dev is not set +# CONFIG_python3-gitdb-dbg is not set + +# +# python3-setuptools +# +# CONFIG_python3-setuptools is not set +# CONFIG_python3-setuptools-dbg is not set +# CONFIG_python3-setuptools-dev is not set + +# +# python3-smmap +# +# CONFIG_python3-smmap is not set +# CONFIG_python3-smmap-dev is not set +# CONFIG_python3-smmap-dbg is not set + +# +# qemu +# +# CONFIG_qemu is not set +# CONFIG_qemu-dev is not set +# CONFIG_qemu-dbg is not set + +# +# qtbase +# +# CONFIG_qtbase is not set +# CONFIG_qtbase-plugins is not set +# CONFIG_qtbase-dev is not set +# CONFIG_qtbase-dbg is not set +# CONFIG_qtbase-tools is not set +# CONFIG_qtbase-examples is not set +# CONFIG_qtbase-mkspecs is not set + +# +# qtcharts +# +# CONFIG_qtcharts is not set +# CONFIG_qtcharts-qmlplugins is not set +# CONFIG_qtcharts-mkspecs is not set +# CONFIG_qtcharts-dbg is not set +# CONFIG_qtcharts-examples is not set +# CONFIG_qtcharts-dev is not set +# CONFIG_qtcharts-qmldesigner is not set + +# +# qtconnectivity +# +# CONFIG_qtconnectivity is not set +# CONFIG_qtconnectivity-qmlplugins is not set +# CONFIG_qtconnectivity-tools is not set +# CONFIG_qtconnectivity-mkspecs is not set +# CONFIG_qtconnectivity-examples is not set +# CONFIG_qtconnectivity-dev is not set +# CONFIG_qtconnectivity-dbg is not set + +# +# qtdeclarative +# +# CONFIG_qtdeclarative is not set +# CONFIG_qtdeclarative-tools is not set +# CONFIG_qtdeclarative-examples is not set +# CONFIG_qtdeclarative-mkspecs is not set +# CONFIG_qtdeclarative-dbg is not set +# CONFIG_qtdeclarative-qmlplugins is not set +# CONFIG_qtdeclarative-dev is not set + +# +# qtenginio +# +# CONFIG_qtenginio is not set +# CONFIG_qtenginio-qmlplugins is not set +# CONFIG_qtenginio-dev is not set +# CONFIG_qtenginio-dbg is not set +# CONFIG_qtenginio-examples is not set +# CONFIG_qtenginio-mkspecs is not set + +# +# qtimageformats +# +# CONFIG_qtimageformats is not set +# CONFIG_qtimageformats-dev is not set +# CONFIG_qtimageformats-dbg is not set +# CONFIG_qtimageformats-plugins is not set + +# +# qtlocation +# +# CONFIG_qtlocation is not set +# CONFIG_qtlocation-qmlplugins is not set +# CONFIG_qtlocation-examples is not set +# CONFIG_qtlocation-mkspecs is not set +# CONFIG_qtlocation-dev is not set +# CONFIG_qtlocation-plugins is not set +# CONFIG_qtlocation-dbg is not set + +# +# qtmultimedia +# +# CONFIG_qtmultimedia is not set +# CONFIG_qtmultimedia-dbg is not set +# CONFIG_qtmultimedia-plugins is not set +# CONFIG_qtmultimedia-mkspecs is not set +# CONFIG_qtmultimedia-dev is not set +# CONFIG_qtmultimedia-examples is not set +# CONFIG_qtmultimedia-qmlplugins is not set + +# +# qtquickcontrols +# +# CONFIG_qtquickcontrols is not set +# CONFIG_qtquickcontrols-dev is not set +# CONFIG_qtquickcontrols-examples is not set +# CONFIG_qtquickcontrols-qmldesigner is not set +# CONFIG_qtquickcontrols-qmlplugins is not set +# CONFIG_qtquickcontrols-dbg is not set + +# +# qtscript +# +# CONFIG_qtscript is not set +# CONFIG_qtscript-dbg is not set +# CONFIG_qtscript-mkspecs is not set +# CONFIG_qtscript-dev is not set +# CONFIG_qtscript-examples is not set + +# +# qtsensors +# +# CONFIG_qtsensors is not set +# CONFIG_qtsensors-examples is not set +# CONFIG_qtsensors-qmlplugins is not set +# CONFIG_qtsensors-mkspecs is not set +# CONFIG_qtsensors-plugins is not set +# CONFIG_qtsensors-dbg is not set +# CONFIG_qtsensors-dev is not set + +# +# qtserialport +# +# CONFIG_qtserialport is not set +# CONFIG_qtserialport-mkspecs is not set +# CONFIG_qtserialport-dev is not set +# CONFIG_qtserialport-dbg is not set +# CONFIG_qtserialport-examples is not set + +# +# qtsvg +# +# CONFIG_qtsvg is not set +# CONFIG_qtsvg-dev is not set +# CONFIG_qtsvg-dbg is not set +# CONFIG_qtsvg-examples is not set +# CONFIG_qtsvg-mkspecs is not set +# CONFIG_qtsvg-plugins is not set + +# +# qtsystems +# +# CONFIG_qtsystems is not set +# CONFIG_qtsystems-dev is not set +# CONFIG_qtsystems-mkspecs is not set +# CONFIG_qtsystems-qmlplugins is not set +# CONFIG_qtsystems-dbg is not set +# CONFIG_qtsystems-tools is not set +# CONFIG_qtsystems-examples is not set + +# +# qttools +# +# CONFIG_qttools is not set +# CONFIG_qttools-dbg is not set +# CONFIG_qttools-dev is not set +# CONFIG_qttools-examples is not set +# CONFIG_qttools-tools is not set +# CONFIG_qttools-mkspecs is not set +# CONFIG_qttools-plugins is not set + +# +# qttranslations +# +# CONFIG_qttranslations is not set +# CONFIG_qttranslations-qtwebengine is not set +# CONFIG_qttranslations-qthelp is not set +# CONFIG_qttranslations-qtbase is not set +# CONFIG_qttranslations-dbg is not set +# CONFIG_qttranslations-dev is not set +# CONFIG_qttranslations-qtscript is not set +# CONFIG_qttranslations-qtdeclarative is not set +# CONFIG_qttranslations-assistant is not set +# CONFIG_qttranslations-qtwebsockets is not set +# CONFIG_qttranslations-linguist is not set +# CONFIG_qttranslations-qtserialport is not set +# CONFIG_qttranslations-qtmultimedia is not set +# CONFIG_qttranslations-qtconnectivity is not set +# CONFIG_qttranslations-qtlocation is not set +# CONFIG_qttranslations-qtxmlpatterns is not set +# CONFIG_qttranslations-qtquickcontrols is not set +# CONFIG_qttranslations-designer is not set +# CONFIG_qttranslations-qtquickcontrols2 is not set + +# +# qtwebchannel +# +# CONFIG_qtwebchannel is not set +# CONFIG_qtwebchannel-mkspecs is not set +# CONFIG_qtwebchannel-dbg is not set +# CONFIG_qtwebchannel-examples is not set +# CONFIG_qtwebchannel-qmlplugins is not set +# CONFIG_qtwebchannel-dev is not set + +# +# qtwebkit +# +# CONFIG_qtwebkit is not set +# CONFIG_qtwebkit-qmlplugins is not set +# CONFIG_qtwebkit-mkspecs is not set +# CONFIG_qtwebkit-dbg is not set +# CONFIG_qtwebkit-dev is not set + +# +# qtwebsockets +# +# CONFIG_qtwebsockets is not set +# CONFIG_qtwebsockets-examples is not set +# CONFIG_qtwebsockets-qmlplugins is not set +# CONFIG_qtwebsockets-dbg is not set +# CONFIG_qtwebsockets-dev is not set +# CONFIG_qtwebsockets-mkspecs is not set + +# +# qtxmlpatterns +# +# CONFIG_qtxmlpatterns is not set +# CONFIG_qtxmlpatterns-dev is not set +# CONFIG_qtxmlpatterns-mkspecs is not set +# CONFIG_qtxmlpatterns-examples is not set +# CONFIG_qtxmlpatterns-dbg is not set +# CONFIG_qtxmlpatterns-tools is not set + +# +# rgb +# +# CONFIG_rgb is not set +# CONFIG_rgb-dev is not set +# CONFIG_rgb-dbg is not set + +# +# rpm +# +# CONFIG_rpm is not set +# CONFIG_rpm-build is not set +# CONFIG_rpm-dbg is not set +# CONFIG_rpm-dev is not set + +# +# rpmsg-echo-test +# +# CONFIG_rpmsg-echo-test is not set +# CONFIG_rpmsg-echo-test-dbg is not set +# CONFIG_rpmsg-echo-test-dev is not set + +# +# rpmsg-mat-mul +# +# CONFIG_rpmsg-mat-mul is not set +# CONFIG_rpmsg-mat-mul-dev is not set +# CONFIG_rpmsg-mat-mul-dbg is not set + +# +# rpmsg-proxy-app +# +# CONFIG_rpmsg-proxy-app is not set +# CONFIG_rpmsg-proxy-app-dbg is not set +# CONFIG_rpmsg-proxy-app-dev is not set + +# +# serf +# +# CONFIG_serf is not set +# CONFIG_serf-dev is not set +# CONFIG_serf-dbg is not set + +# +# sysfsutils +# +# CONFIG_sysfsutils is not set +# CONFIG_libsysfs is not set +# CONFIG_sysfsutils-dbg is not set +# CONFIG_sysfsutils-dev is not set + +# +# sysvinit-inittab +# +# CONFIG_sysvinit-inittab is not set +# CONFIG_sysvinit-inittab-dev is not set +# CONFIG_sysvinit-inittab-dbg is not set + +# +# tbb +# +# CONFIG_tbb is not set +# CONFIG_tbb-dbg is not set +# CONFIG_tbb-dev is not set + +# +# tcf-agent +# +CONFIG_tcf-agent=y +# CONFIG_tcf-agent-dev is not set +# CONFIG_tcf-agent-dbg is not set + +# +# texi2html +# +# CONFIG_texi2html is not set +# CONFIG_texi2html-dev is not set +# CONFIG_texi2html-dbg is not set + +# +# tiff +# +# CONFIG_tiff is not set +# CONFIG_tiffxx is not set +# CONFIG_tiff-dbg is not set +# CONFIG_tiff-utils is not set +# CONFIG_tiff-dev is not set + +# +# util-macros +# +# CONFIG_util-macros is not set +# CONFIG_util-macros-dbg is not set +# CONFIG_util-macros-dev is not set + +# +# v4l-utils +# +# CONFIG_v4l-utils is not set +# CONFIG_libv4l is not set +# CONFIG_ir-keytable is not set +# CONFIG_media-ctl is not set +# CONFIG_v4l-utils-dbg is not set +# CONFIG_rc-keymaps is not set +# CONFIG_v4l-utils-dev is not set +# CONFIG_libv4l-dev is not set + +# +# valgrind +# +# CONFIG_valgrind is not set +# CONFIG_valgrind-dbg is not set +# CONFIG_valgrind-dev is not set + +# +# vte +# +# CONFIG_vte is not set +# CONFIG_vte-dbg is not set +# CONFIG_vte-dev is not set +# CONFIG_libvte is not set + +# +# watchdog +# +# CONFIG_watchdog is not set +# CONFIG_watchdog-dbg is not set +# CONFIG_watchdog-dev is not set +# CONFIG_watchdog-keepalive is not set + +# +# watchdog-config +# +# CONFIG_watchdog-config is not set +# CONFIG_watchdog-config-dbg is not set +# CONFIG_watchdog-config-dev is not set + +# +# watchdog-init +# +CONFIG_watchdog-init=y + +# +# webkitgtk +# +# CONFIG_webkitgtk is not set +# CONFIG_webkitgtk-dbg is not set +# CONFIG_webkitgtk-dev is not set + +# +# x11perf +# +# CONFIG_x11perf is not set +# CONFIG_x11perf-dev is not set +# CONFIG_x11perf-dbg is not set + +# +# x264 +# +# CONFIG_x264 is not set +# CONFIG_x264-dev is not set +# CONFIG_x264-dbg is not set +# CONFIG_x264-bin is not set + +# +# xauth +# +# CONFIG_xauth is not set +# CONFIG_xauth-dbg is not set +# CONFIG_xauth-dev is not set + +# +# xcb-util-image +# +# CONFIG_xcb-util-image is not set +# CONFIG_xcb-util-image-dbg is not set +# CONFIG_xcb-util-image-dev is not set + +# +# xcb-util-keysyms +# +# CONFIG_xcb-util-keysyms is not set +# CONFIG_xcb-util-keysyms-dev is not set +# CONFIG_xcb-util-keysyms-dbg is not set + +# +# xcb-util-renderutil +# +# CONFIG_xcb-util-renderutil is not set +# CONFIG_xcb-util-renderutil-dev is not set +# CONFIG_xcb-util-renderutil-dbg is not set + +# +# xcb-util-wm +# +# CONFIG_xcb-util-wm is not set +# CONFIG_xcb-util-wm-dbg is not set +# CONFIG_xcb-util-wm-dev is not set + +# +# xdg-utils +# +# CONFIG_xdg-utils is not set +# CONFIG_xdg-utils-dev is not set +# CONFIG_xdg-utils-dbg is not set + +# +# xdpyinfo +# +# CONFIG_xdpyinfo is not set +# CONFIG_xdpyinfo-dev is not set +# CONFIG_xdpyinfo-dbg is not set + +# +# xf86-input-evdev +# +# CONFIG_xf86-input-evdev is not set +# CONFIG_xf86-input-evdev-dbg is not set +# CONFIG_xf86-input-evdev-dev is not set + +# +# xf86-input-keyboard +# +# CONFIG_xf86-input-keyboard is not set +# CONFIG_xf86-input-keyboard-dev is not set +# CONFIG_xf86-input-keyboard-dbg is not set + +# +# xf86-input-mouse +# +# CONFIG_xf86-input-mouse is not set +# CONFIG_xf86-input-mouse-dbg is not set +# CONFIG_xf86-input-mouse-dev is not set + +# +# xf86-video-armsoc +# +# CONFIG_xf86-video-armsoc is not set +# CONFIG_xf86-video-armsoc-dbg is not set +# CONFIG_xf86-video-armsoc-dev is not set + +# +# xf86-video-fbdev +# +# CONFIG_xf86-video-fbdev is not set +# CONFIG_xf86-video-fbdev-dbg is not set +# CONFIG_xf86-video-fbdev-dev is not set + +# +# xhost +# +# CONFIG_xhost is not set +# CONFIG_xhost-dbg is not set +# CONFIG_xhost-dev is not set + +# +# xinetd +# +# CONFIG_xinetd is not set +# CONFIG_xinetd-dbg is not set +# CONFIG_xinetd-dev is not set + +# +# xinit +# +# CONFIG_xinit is not set +# CONFIG_xinit-dbg is not set +# CONFIG_xinit-dev is not set + +# +# xinput +# +# CONFIG_xinput is not set +# CONFIG_xinput-dev is not set +# CONFIG_xinput-dbg is not set + +# +# xinput-calibrator +# +# CONFIG_xinput-calibrator is not set +# CONFIG_xinput-calibrator-dev is not set +# CONFIG_xinput-calibrator-dbg is not set + +# +# xkbcomp +# +# CONFIG_xkbcomp is not set +# CONFIG_xkbcomp-dbg is not set +# CONFIG_xkbcomp-dev is not set + +# +# xmodmap +# +# CONFIG_xmodmap is not set +# CONFIG_xmodmap-dbg is not set +# CONFIG_xmodmap-dev is not set + +# +# xprop +# +# CONFIG_xprop is not set +# CONFIG_xprop-dbg is not set +# CONFIG_xprop-dev is not set + +# +# xrandr +# +# CONFIG_xrandr is not set +# CONFIG_xrandr-dbg is not set +# CONFIG_xrandr-dev is not set + +# +# xserver-common +# +# CONFIG_xserver-common is not set +# CONFIG_xserver-common-dbg is not set +# CONFIG_xserver-common-dev is not set + +# +# xset +# +# CONFIG_xset is not set +# CONFIG_xset-dev is not set +# CONFIG_xset-dbg is not set + +# +# xtrans +# +# CONFIG_xtrans-dev is not set +# CONFIG_xtrans-dbg is not set + +# +# xwininfo +# +# CONFIG_xwininfo is not set +# CONFIG_xwininfo-dev is not set +# CONFIG_xwininfo-dbg is not set + +# +# yajl +# +# CONFIG_yajl is not set +# CONFIG_yajl-dev is not set +# CONFIG_yajl-dbg is not set +# CONFIG_yajl-bin is not set + +# +# yavta +# +# CONFIG_yavta is not set +# CONFIG_yavta-dbg is not set +# CONFIG_yavta-dev is not set + +# +# multimedia +# + +# +# alsa-plugins +# +# CONFIG_alsa-plugins is not set +# CONFIG_alsa-plugins-dbg is not set +# CONFIG_alsa-plugins-dev is not set +# CONFIG_alsa-plugins-pulseaudio-conf is not set + +# +# gstreamer1.0 +# +# CONFIG_gstreamer1.0 is not set +# CONFIG_gstreamer1.0-dev is not set +# CONFIG_gstreamer1.0-bash-completion is not set +# CONFIG_gstreamer1.0-dbg is not set + +# +# gstreamer1.0-omx +# +# CONFIG_gstreamer1.0-omx is not set +# CONFIG_gstreamer1.0-omx-dbg is not set +# CONFIG_gstreamer1.0-omx-dev is not set + +# +# gstreamer1.0-rtsp-server +# +# CONFIG_gstreamer1.0-rtsp-server is not set +# CONFIG_gstreamer1.0-rtsp-server-dbg is not set +# CONFIG_gstreamer1.0-rtsp-server-dev is not set +# CONFIG_gstreamer1.0-rtsp-server-meta is not set + +# +# net +# + +# +# bridge-utils +# +CONFIG_bridge-utils=y +# CONFIG_bridge-utils-dbg is not set +# CONFIG_bridge-utils-dev is not set + +# +# net-snmp +# +# CONFIG_net-snmp is not set +# CONFIG_net-snmp-server-snmptrapd is not set +# CONFIG_net-snmp-libs is not set +# CONFIG_net-snmp-dev is not set +# CONFIG_net-snmp-client is not set +# CONFIG_net-snmp-mibs is not set +# CONFIG_net-snmp-dbg is not set +# CONFIG_net-snmp-server-snmpd is not set +# CONFIG_net-snmp-server is not set + +# +# netcat +# +CONFIG_netcat=y +# CONFIG_netcat-dbg is not set +# CONFIG_netcat-dev is not set + +# +# tcpdump +# +CONFIG_tcpdump=y +# CONFIG_tcpdump-dev is not set +# CONFIG_tcpdump-dbg is not set + +# +# network +# + +# +# avahi +# +# CONFIG_libavahi-client is not set +# CONFIG_libavahi-glib is not set +# CONFIG_avahi-utils is not set +# CONFIG_libavahi-common is not set +# CONFIG_avahi-dnsconfd is not set +# CONFIG_avahi-daemon is not set +# CONFIG_avahi-autoipd is not set +# CONFIG_libavahi-gobject is not set +# CONFIG_libavahi-core is not set +# CONFIG_avahi-dbg is not set +# CONFIG_avahi-dev is not set + +# +# mobile-broadband-provider-info +# +# CONFIG_mobile-broadband-provider-info is not set +# CONFIG_mobile-broadband-provider-info-dbg is not set +# CONFIG_mobile-broadband-provider-info-dev is not set + +# +# wpa-supplicant +# +# CONFIG_wpa-supplicant is not set +# CONFIG_wpa-supplicant-passphrase is not set +# CONFIG_wpa-supplicant-dev is not set +# CONFIG_wpa-supplicant-dbg is not set +# CONFIG_wpa-supplicant-cli is not set + +# +# optional +# + +# +# libatomic-ops +# +# CONFIG_libatomic-ops is not set +# CONFIG_libatomic-ops-dev is not set +# CONFIG_libatomic-ops-dbg is not set + +# +# mtools +# +# CONFIG_mtools is not set +# CONFIG_mtools-dev is not set +# CONFIG_mtools-dbg is not set + +# +# power management +# +CONFIG_hellopm=y + +# +# utils +# + +# +# dosfstools +# +# CONFIG_dosfstools is not set +# CONFIG_dosfstools-dev is not set +# CONFIG_dosfstools-dbg is not set + +# +# patch +# +# CONFIG_patch is not set +# CONFIG_patch-dbg is not set +# CONFIG_patch-dev is not set + +# +# resize-part +# +# CONFIG_resize-part is not set +# CONFIG_resize-part-dbg is not set +# CONFIG_resize-part-dev is not set + +# +# x11 +# + +# +# base +# + +# +# libdrm +# +# CONFIG_libdrm is not set +# CONFIG_libdrm-tests is not set +# CONFIG_libdrm-drivers is not set +# CONFIG_libdrm-amdgpu is not set +# CONFIG_libdrm-nouveau is not set +# CONFIG_libdrm-dev is not set +# CONFIG_libdrm-freedreno is not set +# CONFIG_libdrm-radeon is not set +# CONFIG_libdrm-kms is not set +# CONFIG_libdrm-dbg is not set +# CONFIG_libdrm-omap is not set + +# +# xcursor-transparent-theme +# +# CONFIG_xcursor-transparent-theme is not set +# CONFIG_xcursor-transparent-theme-dev is not set +# CONFIG_xcursor-transparent-theme-dbg is not set + +# +# xserver-xf86-config +# +# CONFIG_xserver-xf86-config is not set +# CONFIG_xserver-xf86-config-dev is not set +# CONFIG_xserver-xf86-config-dbg is not set + +# +# xserver-xorg +# +# CONFIG_xserver-xorg is not set +# CONFIG_xserver-xorg-module-exa is not set +# CONFIG_xserver-xorg-module-libint10 is not set +# CONFIG_xserver-xorg-extension-record is not set +# CONFIG_xserver-xorg-dev is not set +# CONFIG_xserver-xorg-extension-dri2 is not set +# CONFIG_xserver-xorg-extension-dri is not set +# CONFIG_xserver-xorg-module-libwfb is not set +# CONFIG_xf86-video-modesetting is not set +# CONFIG_xserver-xorg-extension-dbe is not set +# CONFIG_xserver-xorg-extension-glx is not set +# CONFIG_xserver-xorg-xvfb is not set +# CONFIG_xserver-xorg-utils is not set +# CONFIG_xserver-xorg-dbg is not set +# CONFIG_xserver-xorg-extension-extmod is not set + +# +# builder +# +# CONFIG_builder is not set +# CONFIG_builder-dbg is not set +# CONFIG_builder-dev is not set + +# +# fonts +# + +# +# liberation-fonts +# +# CONFIG_liberation-fonts is not set + +# +# glew +# +# CONFIG_glew is not set +# CONFIG_glew-bin is not set +# CONFIG_glew-dev is not set +# CONFIG_glew-dbg is not set + +# +# gnome +# + +# +# adwaita-icon-theme +# +# CONFIG_adwaita-icon-theme is not set +# CONFIG_adwaita-icon-theme-hires is not set +# CONFIG_adwaita-icon-theme-symbolic is not set +# CONFIG_adwaita-icon-theme-cursors is not set +# CONFIG_adwaita-icon-theme-symbolic-hires is not set + +# +# gconf +# +# CONFIG_gconf is not set +# CONFIG_gconf-dev is not set +# CONFIG_gconf-dbg is not set + +# +# gnome-common +# +# CONFIG_gnome-common is not set +# CONFIG_gnome-common-dev is not set +# CONFIG_gnome-common-dbg is not set + +# +# gnome-desktop3 +# +# CONFIG_gnome-desktop3 is not set +# CONFIG_gnome-desktop3-dbg is not set +# CONFIG_gnome-desktop3-dev is not set +# CONFIG_libgnome-desktop3 is not set + +# +# gnome-themes-standard +# +# CONFIG_gnome-themes-standard-dev is not set +# CONFIG_gnome-themes-standard-dbg is not set +# CONFIG_gnome-theme-adwaita is not set + +# +# libsoup-2.4 +# +# CONFIG_libsoup-2.4 is not set +# CONFIG_libsoup-2.4-dev is not set +# CONFIG_libsoup-2.4-dbg is not set + +# +# libglu +# +# CONFIG_libglu is not set +# CONFIG_libglu-dev is not set +# CONFIG_libglu-dbg is not set + +# +# libs +# + +# +# atk +# +# CONFIG_atk is not set +# CONFIG_atk-dev is not set +# CONFIG_atk-dbg is not set + +# +# libfm +# +# CONFIG_libfm is not set +# CONFIG_libfm-mime is not set +# CONFIG_libfm-dev is not set +# CONFIG_libfm-dbg is not set + +# +# libfm-extra +# +# CONFIG_libfm-extra is not set +# CONFIG_libfm-extra-dev is not set +# CONFIG_libfm-extra-dbg is not set + +# +# libmatchbox +# +# CONFIG_libmatchbox is not set +# CONFIG_libmatchbox-dev is not set +# CONFIG_libmatchbox-dbg is not set + +# +# libpthread-stubs +# +# CONFIG_libpthread-stubs-dbg is not set +# CONFIG_libpthread-stubs-dev is not set + +# +# libwnck3 +# +# CONFIG_libwnck3 is not set +# CONFIG_libwnck3-dev is not set +# CONFIG_libwnck3-dbg is not set + +# +# libxcb +# +# CONFIG_libxcb is not set +# CONFIG_libxcb-dev is not set +# CONFIG_libxcb-dbg is not set + +# +# menu-cache +# +# CONFIG_menu-cache is not set +# CONFIG_menu-cache-dbg is not set +# CONFIG_menu-cache-dev is not set + +# +# xcb-proto +# +# CONFIG_python-xcbgen is not set +# CONFIG_xcb-proto-dev is not set +# CONFIG_xcb-proto-dbg is not set + +# +# xcb-util +# +# CONFIG_xcb-util is not set +# CONFIG_xcb-util-dbg is not set +# CONFIG_xcb-util-dev is not set + +# +# xkeyboard-config +# +# CONFIG_xkeyboard-config is not set +# CONFIG_xkeyboard-config-dev is not set +# CONFIG_xkeyboard-config-dbg is not set + +# +# matchbox-keyboard +# +# CONFIG_matchbox-keyboard is not set +# CONFIG_matchbox-keyboard-im is not set +# CONFIG_matchbox-keyboard-dev is not set +# CONFIG_matchbox-keyboard-applet is not set +# CONFIG_matchbox-keyboard-dbg is not set + +# +# matchbox-session +# +# CONFIG_matchbox-session is not set +# CONFIG_matchbox-session-dev is not set +# CONFIG_matchbox-session-dbg is not set + +# +# matchbox-session-sato +# +# CONFIG_matchbox-session-sato is not set +# CONFIG_matchbox-session-sato-dev is not set +# CONFIG_matchbox-session-sato-dbg is not set + +# +# mesa-demos +# +# CONFIG_mesa-demos is not set +# CONFIG_mesa-demos-dbg is not set +# CONFIG_mesa-demos-dev is not set + +# +# mini-x-session +# +# CONFIG_mini-x-session is not set +# CONFIG_mini-x-session-dev is not set +# CONFIG_mini-x-session-dbg is not set + +# +# pcmanfm +# +# CONFIG_pcmanfm is not set +# CONFIG_pcmanfm-dbg is not set +# CONFIG_pcmanfm-dev is not set + +# +# settings-daemon +# +# CONFIG_settings-daemon is not set +# CONFIG_settings-daemon-dev is not set +# CONFIG_settings-daemon-dbg is not set + +# +# utils +# + +# +# libcroco +# +# CONFIG_libcroco is not set +# CONFIG_libcroco-dbg is not set +# CONFIG_libcroco-dev is not set + +# +# librsvg +# +# CONFIG_librsvg is not set +# CONFIG_librsvg-gtk is not set +# CONFIG_rsvg is not set +# CONFIG_librsvg-dev is not set +# CONFIG_librsvg-dbg is not set + +# +# matchbox-terminal +# +# CONFIG_matchbox-terminal is not set +# CONFIG_matchbox-terminal-dev is not set +# CONFIG_matchbox-terminal-dbg is not set + +# +# xrestop +# +# CONFIG_xrestop is not set +# CONFIG_xrestop-dev is not set +# CONFIG_xrestop-dbg is not set + +# +# wm +# + +# +# libfakekey +# +# CONFIG_libfakekey is not set +# CONFIG_libfakekey-dev is not set +# CONFIG_libfakekey-dbg is not set + +# +# matchbox-desktop +# +# CONFIG_matchbox-desktop is not set +# CONFIG_matchbox-desktop-dbg is not set +# CONFIG_matchbox-desktop-dev is not set + +# +# matchbox-theme-sato +# +# CONFIG_matchbox-theme-sato is not set +# CONFIG_matchbox-theme-sato-dbg is not set +# CONFIG_matchbox-theme-sato-dev is not set + +# +# matchbox-wm +# +# CONFIG_matchbox-wm is not set +# CONFIG_matchbox-wm-dev is not set +# CONFIG_matchbox-wm-dbg is not set + +# +# xserver-nodm-init +# +# CONFIG_xserver-nodm-init is not set +# CONFIG_xserver-nodm-init-dbg is not set +# CONFIG_xserver-nodm-init-dev is not set + +# +# Petalinux Package Groups +# + +# +# packagegroup-petalinux +# +# CONFIG_packagegroup-petalinux is not set +# CONFIG_packagegroup-petalinux-dbg is not set +# CONFIG_packagegroup-petalinux-dev is not set + +# +# packagegroup-petalinux-audio +# +# CONFIG_packagegroup-petalinux-audio is not set +# CONFIG_packagegroup-petalinux-audio-dbg is not set +# CONFIG_packagegroup-petalinux-audio-dev is not set + +# +# packagegroup-petalinux-benchmarks +# +# CONFIG_packagegroup-petalinux-benchmarks is not set +# CONFIG_packagegroup-petalinux-benchmarks-dbg is not set +# CONFIG_packagegroup-petalinux-benchmarks-dev is not set + +# +# packagegroup-petalinux-display-debug +# +# CONFIG_packagegroup-petalinux-display-debug is not set +# CONFIG_packagegroup-petalinux-display-debug-dbg is not set +# CONFIG_packagegroup-petalinux-display-debug-dev is not set + +# +# packagegroup-petalinux-gstreamer +# +# CONFIG_packagegroup-petalinux-gstreamer is not set +# CONFIG_packagegroup-petalinux-gstreamer-dev is not set +# CONFIG_packagegroup-petalinux-gstreamer-dbg is not set + +# +# packagegroup-petalinux-lmsensors +# +# CONFIG_packagegroup-petalinux-lmsensors is not set +# CONFIG_packagegroup-petalinux-lmsensors-dbg is not set +# CONFIG_packagegroup-petalinux-lmsensors-dev is not set + +# +# packagegroup-petalinux-matchbox +# +# CONFIG_packagegroup-petalinux-matchbox is not set +# CONFIG_packagegroup-petalinux-matchbox-dbg is not set +# CONFIG_packagegroup-petalinux-matchbox-dev is not set + +# +# packagegroup-petalinux-mraa +# +# CONFIG_packagegroup-petalinux-mraa is not set +# CONFIG_packagegroup-petalinux-mraa-dbg is not set +# CONFIG_packagegroup-petalinux-mraa-dev is not set + +# +# packagegroup-petalinux-multimedia +# +# CONFIG_packagegroup-petalinux-multimedia is not set +# CONFIG_packagegroup-petalinux-multimedia-dbg is not set +# CONFIG_packagegroup-petalinux-multimedia-dev is not set + +# +# packagegroup-petalinux-networking-debug +# +CONFIG_packagegroup-petalinux-networking-debug=y +# CONFIG_packagegroup-petalinux-networking-debug-dbg is not set +# CONFIG_packagegroup-petalinux-networking-debug-dev is not set + +# +# packagegroup-petalinux-networking-stack +# +CONFIG_packagegroup-petalinux-networking-stack=y +# CONFIG_packagegroup-petalinux-networking-stack-dbg is not set +# CONFIG_packagegroup-petalinux-networking-stack-dev is not set + +# +# packagegroup-petalinux-ocicontainers +# +# CONFIG_packagegroup-petalinux-ocicontainers is not set +# CONFIG_packagegroup-petalinux-ocicontainers-dev is not set +# CONFIG_packagegroup-petalinux-ocicontainers-dbg is not set + +# +# packagegroup-petalinux-openamp +# +# CONFIG_packagegroup-petalinux-openamp is not set +# CONFIG_packagegroup-petalinux-openamp-dev is not set +# CONFIG_packagegroup-petalinux-openamp-dbg is not set + +# +# packagegroup-petalinux-opencv +# +# CONFIG_packagegroup-petalinux-opencv is not set +# CONFIG_packagegroup-petalinux-opencv-dev is not set +# CONFIG_packagegroup-petalinux-opencv-dbg is not set + +# +# packagegroup-petalinux-python-modules +# +# CONFIG_packagegroup-petalinux-python-modules is not set +# CONFIG_packagegroup-petalinux-python-modules-dbg is not set +# CONFIG_packagegroup-petalinux-python-modules-dev is not set + +# +# packagegroup-petalinux-qt +# +# CONFIG_packagegroup-petalinux-qt is not set +# CONFIG_packagegroup-petalinux-qt-dev is not set +# CONFIG_packagegroup-petalinux-qt-dbg is not set +# CONFIG_imageclass-populate-sdk-qt5 is not set + +# +# packagegroup-petalinux-qt-extended +# +# CONFIG_packagegroup-petalinux-qt-extended is not set +# CONFIG_packagegroup-petalinux-qt-extended-dbg is not set +# CONFIG_packagegroup-petalinux-qt-extended-dev is not set + +# +# packagegroup-petalinux-self-hosted +# +# CONFIG_packagegroup-petalinux-self-hosted is not set +# CONFIG_packagegroup-petalinux-self-hosted-dbg is not set +# CONFIG_packagegroup-petalinux-self-hosted-dev is not set + +# +# packagegroup-petalinux-updateboot +# +# CONFIG_packagegroup-petalinux-updateboot is not set +# CONFIG_packagegroup-petalinux-updateboot-dbg is not set +# CONFIG_packagegroup-petalinux-updateboot-dev is not set + +# +# packagegroup-petalinux-utils +# +# CONFIG_packagegroup-petalinux-utils is not set +# CONFIG_packagegroup-petalinux-utils-dbg is not set +# CONFIG_packagegroup-petalinux-utils-dev is not set + +# +# packagegroup-petalinux-v4lutils +# +# CONFIG_packagegroup-petalinux-v4lutils is not set +# CONFIG_packagegroup-petalinux-v4lutils-dbg is not set +# CONFIG_packagegroup-petalinux-v4lutils-dev is not set + +# +# packagegroup-petalinux-vitisai +# +# CONFIG_packagegroup-petalinux-vitisai is not set +# CONFIG_packagegroup-petalinux-vitisai-dbg is not set +# CONFIG_packagegroup-petalinux-vitisai-dev is not set + +# +# packagegroup-petalinux-weston +# +# CONFIG_packagegroup-petalinux-weston is not set +# CONFIG_packagegroup-petalinux-weston-dbg is not set +# CONFIG_packagegroup-petalinux-weston-dev is not set + +# +# packagegroup-petalinux-x11 +# +# CONFIG_packagegroup-petalinux-x11 is not set +# CONFIG_packagegroup-petalinux-x11-dev is not set +# CONFIG_packagegroup-petalinux-x11-dbg is not set + +# +# packagegroup-petalinux-xen +# +# CONFIG_packagegroup-petalinux-xen is not set +# CONFIG_packagegroup-petalinux-xen-dev is not set +# CONFIG_packagegroup-petalinux-xen-dbg is not set + +# +# packagegroup-petalinux-xrt +# +# CONFIG_packagegroup-petalinux-xrt is not set +# CONFIG_packagegroup-petalinux-xrt-dev is not set +# CONFIG_packagegroup-petalinux-xrt-dbg is not set + +# +# Image Features +# +CONFIG_imagefeature-ssh-server-dropbear=y +# CONFIG_imagefeature-ssh-server-openssh is not set +CONFIG_imagefeature-hwcodecs=y +# CONFIG_imagefeature-package-management is not set +# CONFIG_imagefeature-debug-tweaks is not set +# CONFIG_auto-login is not set + +# +# apps +# +CONFIG_gpio-demo=y +CONFIG_myapp-init=y +CONFIG_peekpoke=y + +# +# user packages +# +CONFIG_iperf3=y +CONFIG_phytool=y + +# +# PetaLinux RootFS Settings +# +CONFIG_ROOTFS_ROOT_PASSWD="root" +CONFIG_ADD_EXTRA_USERS="pinky" diff --git a/Petalinux/project-spec/hw-description/metadata b/Petalinux/project-spec/hw-description/metadata new file mode 100644 index 0000000..e69de29 diff --git a/Petalinux/project-spec/hw-description/pl_eth_10g_wrapper2.bit b/Petalinux/project-spec/hw-description/pl_eth_10g_wrapper2.bit new file mode 100644 index 0000000..a509357 Binary files /dev/null and b/Petalinux/project-spec/hw-description/pl_eth_10g_wrapper2.bit differ diff --git a/Petalinux/project-spec/hw-description/psu_init.c b/Petalinux/project-spec/hw-description/psu_init.c new file mode 100644 index 0000000..4076d69 --- /dev/null +++ b/Petalinux/project-spec/hw-description/psu_init.c @@ -0,0 +1,23824 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file psu_init.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include +#include +#include "psu_init.h" +#define DPLL_CFG_LOCK_DLY 63 +#define DPLL_CFG_LOCK_CNT 625 +#define DPLL_CFG_LFHF 3 +#define DPLL_CFG_CP 3 +#define DPLL_CFG_RES 2 + +static int mask_pollOnValue(u32 add, u32 mask, u32 value); + +static int mask_poll(u32 add, u32 mask); + +static void mask_delay(u32 delay); + +static u32 mask_read(u32 add, u32 mask); + +static int serdes_rst_seq (u32 lane3_protocol, u32 lane3_rate, u32 lane2_protocol, u32 lane2_rate, u32 lane1_protocol, u32 lane1_rate, u32 lane0_protocol, u32 lane0_rate); + +static int serdes_bist_static_settings(u32 lane_active); + +static int serdes_bist_run(u32 lane_active); + +static int serdes_bist_result(u32 lane_active); + +static int serdes_illcalib_pcie_gen1 (u32 lane3_protocol, u32 lane3_rate, u32 lane2_protocol, u32 lane2_rate, u32 lane1_protocol, u32 lane1_rate, u32 lane0_protocol, u32 lane0_rate, u32 gen2_calib); + +static int serdes_illcalib (u32 lane3_protocol, u32 lane3_rate, u32 lane2_protocol, u32 lane2_rate, u32 lane1_protocol, u32 lane1_rate, u32 lane0_protocol, u32 lane0_rate); + +static +void PSU_Mask_Write(unsigned long offset, unsigned long mask, + unsigned long val) +{ + unsigned long RegVal = 0x0; + + RegVal = Xil_In32(offset); + RegVal &= ~(mask); + RegVal |= (val & mask); + Xil_Out32(offset, RegVal); +} + + void prog_reg(unsigned long addr, unsigned long mask, + unsigned long shift, unsigned long value) { + int rdata = 0; + + rdata = Xil_In32(addr); + rdata = rdata & (~mask); + rdata = rdata | (value << shift); + Xil_Out32(addr, rdata); + } + +unsigned long psu_pll_init_data(void) +{ + /* + * RPLL INIT + */ + /* + * Register : RPLL_CFG @ 0XFF5E0034 + + * PLL loop filter resistor control + * PSU_CRL_APB_RPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRL_APB_RPLL_CFG_CP 0x4 + + * PLL loop filter high frequency capacitor control + * PSU_CRL_APB_RPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C82U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRL_APB_RPLL_CTRL_FBDIV 0x5a + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRL_APB_RPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00015A00U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_RPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_RPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_RPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFF5E0040 + + * RPLL is locked + * PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U) + */ + mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000002U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_RPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048 + + * Divisor value for this clock. + * PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the LPD, but used in the F + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRL_APB_RPLL_TO_FPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * RPLL FRAC CFG + */ + /* + * SYSMON CLOCK PRESET TO RPLL AGAIN TO AVOID GLITCH WHEN NEXT IOPLL WILL B + * E PUT IN BYPASS MODE + */ + /* + * Register : AMS_REF_CTRL @ 0XFF5E0108 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 1 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 35 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_AMS_REF_CTRL_CLKACT 1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01012300U) + */ + PSU_Mask_Write(CRL_APB_AMS_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01012300U); +/*##################################################################### */ + + /* + * IOPLL INIT + */ + /* + * Register : IOPLL_CFG @ 0XFF5E0024 + + * PLL loop filter resistor control + * PSU_CRL_APB_IOPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRL_APB_IOPLL_CFG_CP 0x4 + + * PLL loop filter high frequency capacitor control + * PSU_CRL_APB_IOPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E4B0C82U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x5a + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRL_APB_IOPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00015A00U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_IOPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_IOPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_IOPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFF5E0040 + + * IOPLL is locked + * PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000001U ,0x00000001U) + */ + mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000001U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_IOPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044 + + * Divisor value for this clock. + * PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the LPD, but used in the F + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * IOPLL FRAC CFG + */ + /* + * APU_PLL INIT + */ + /* + * Register : APLL_CFG @ 0XFD1A0024 + + * PLL loop filter resistor control + * PSU_CRF_APB_APLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_APLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_APLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U) + */ + PSU_Mask_Write(CRF_APB_APLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_APLL_CTRL_FBDIV 0x48 + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_APLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014800U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00717F00U, 0x00014800U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_APLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_APLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_APLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * APLL is locked + * PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000001U ,0x00000001U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000001U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_APLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : APLL_TO_LPD_CTRL @ 0XFD1A0048 + + * Divisor value for this clock. + * PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRF_APB_APLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * APLL FRAC CFG + */ + /* + * DDR_PLL INIT + */ + /* + * Register : DPLL_CFG @ 0XFD1A0030 + + * PLL loop filter resistor control + * PSU_CRF_APB_DPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_DPLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_DPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40 + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_DPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00717F00U, 0x00014000U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_DPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_DPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_DPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * DPLL is locked + * PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000002U ,0x00000002U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000002U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_DPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C + + * Divisor value for this clock. + * PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x2 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DPLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000200U); +/*##################################################################### */ + + /* + * DPLL FRAC CFG + */ + /* + * VIDEO_PLL INIT + */ + /* + * Register : VPLL_CFG @ 0XFD1A003C + + * PLL loop filter resistor control + * PSU_CRF_APB_VPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_VPLL_CFG_CP 0x4 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_VPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E4B0C82U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_VPLL_CTRL_FBDIV 0x5a + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_VPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00015A00U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_VPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_VPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_VPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * VPLL is locked + * PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000004U ,0x00000004U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000004U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_VPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050 + + * Divisor value for this clock. + * PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRF_APB_VPLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * VIDEO FRAC CFG + */ + + return 1; +} +unsigned long psu_clock_init_data(void) +{ + /* + * CLOCK CONTROL SLCR REGISTER + */ + /* + * Register : GEM3_REF_CTRL @ 0XFF5E005C + + * Clock active for the RX channel + * PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) + */ + PSU_Mask_Write(CRL_APB_GEM3_REF_CTRL_OFFSET, + 0x063F3F07U, 0x06010C00U); +/*##################################################################### */ + + /* + * Register : GEM_TSU_REF_CTRL @ 0XFF5E0100 + + * 6 bit divider + * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x0 + + * 6 bit divider + * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010600U) + */ + PSU_Mask_Write(CRL_APB_GEM_TSU_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010600U); +/*##################################################################### */ + + /* + * Register : USB0_BUS_REF_CTRL @ 0XFF5E0060 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U) + */ + PSU_Mask_Write(CRL_APB_USB0_BUS_REF_CTRL_OFFSET, + 0x023F3F07U, 0x02010600U); +/*##################################################################### */ + + /* + * Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0x3 + + * 6 bit divider + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x19 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x02031900U) + */ + PSU_Mask_Write(CRL_APB_USB3_DUAL_REF_CTRL_OFFSET, + 0x023F3F07U, 0x02031900U); +/*##################################################################### */ + + /* + * Register : QSPI_REF_CTRL @ 0XFF5E0068 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0x5 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010500U) + */ + PSU_Mask_Write(CRL_APB_QSPI_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010500U); +/*##################################################################### */ + + /* + * Register : SDIO1_REF_CTRL @ 0XFF5E0070 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x8 + + * 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010800U) + */ + PSU_Mask_Write(CRL_APB_SDIO1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010800U); +/*##################################################################### */ + + /* + * Register : SDIO_CLK_CTRL @ 0XFF18030C + + * MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO + * [51] 1: MIO [76] + * PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0 + + * SoC Debug Clock Control + * (OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_SDIO_CLK_CTRL_OFFSET, + 0x00020000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : UART0_REF_CTRL @ 0XFF5E0074 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_UART0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : UART1_REF_CTRL @ 0XFF5E0078 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_UART1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : I2C0_REF_CTRL @ 0XFF5E0120 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_I2C0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : I2C1_REF_CTRL @ 0XFF5E0124 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_I2C1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : CAN1_REF_CTRL @ 0XFF5E0088 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_CAN1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : CPU_R5_CTRL @ 0XFF5E0090 + + * Turing this off will shut down the OCM, some parts of the APM, and preve + * nt transactions going from the FPD to the LPD and could lead to system h + * ang + * PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_CPU_R5_CTRL_OFFSET, 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : IOU_SWITCH_CTRL @ 0XFF5E009C + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U) + */ + PSU_Mask_Write(CRL_APB_IOU_SWITCH_CTRL_OFFSET, + 0x01003F07U, 0x01000602U); +/*##################################################################### */ + + /* + * Register : PCAP_CTRL @ 0XFF5E00A4 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x8 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000800U) + */ + PSU_Mask_Write(CRL_APB_PCAP_CTRL_OFFSET, 0x01003F07U, 0x01000800U); +/*##################################################################### */ + + /* + * Register : LPD_SWITCH_CTRL @ 0XFF5E00A8 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_LPD_SWITCH_CTRL_OFFSET, + 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : LPD_LSBUS_CTRL @ 0XFF5E00AC + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U) + */ + PSU_Mask_Write(CRL_APB_LPD_LSBUS_CTRL_OFFSET, + 0x01003F07U, 0x01000F02U); +/*##################################################################### */ + + /* + * Register : DBG_LPD_CTRL @ 0XFF5E00B0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U) + */ + PSU_Mask_Write(CRL_APB_DBG_LPD_CTRL_OFFSET, + 0x01003F07U, 0x01000602U); +/*##################################################################### */ + + /* + * Register : ADMA_REF_CTRL @ 0XFF5E00B8 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_ADMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : PL0_REF_CTRL @ 0XFF5E00C0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xc + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010C02U) + */ + PSU_Mask_Write(CRL_APB_PL0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010C02U); +/*##################################################################### */ + + /* + * Register : PL1_REF_CTRL @ 0XFF5E00C4 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_PL1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_PL1_REF_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00C4, 0x013F3F07U ,0x01010F02U) + */ + PSU_Mask_Write(CRL_APB_PL1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F02U); +/*##################################################################### */ + + /* + * Register : AMS_REF_CTRL @ 0XFF5E0108 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1e + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011E02U) + */ + PSU_Mask_Write(CRL_APB_AMS_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01011E02U); +/*##################################################################### */ + + /* + * Register : DLL_REF_CTRL @ 0XFF5E0104 + + * 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an + * issue, but designers must be aware.) + * PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_DLL_REF_CTRL_OFFSET, + 0x00000007U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128 + + * 6 bit divider + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf + + * 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may + * only be toggled after 4 cycles of the old clock and 4 cycles of the new + * clock. This is not usually an issue, but designers must be aware.) + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U) + */ + PSU_Mask_Write(CRL_APB_TIMESTAMP_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000F00U); +/*##################################################################### */ + + /* + * Register : SATA_REF_CTRL @ 0XFD1A00A0 + + * 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_SATA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : PCIE_REF_CTRL @ 0XFD1A00B4 + + * 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only + * be toggled after 4 cycles of the old clock and 4 cycles of the new cloc + * k. This is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_PCIE_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070 + + * 6 bit divider + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x5 + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010500U) + */ + PSU_Mask_Write(CRF_APB_DP_VIDEO_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010500U); +/*##################################################################### */ + + /* + * Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074 + + * 6 bit divider + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0x14 + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01011403U) + */ + PSU_Mask_Write(CRF_APB_DP_AUDIO_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01011403U); +/*##################################################################### */ + + /* + * Register : DP_STC_REF_CTRL @ 0XFD1A007C + + * 6 bit divider + * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0x13 + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg + * led after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01011303U) + */ + PSU_Mask_Write(CRF_APB_DP_STC_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01011303U); +/*##################################################################### */ + + /* + * Register : ACPU_CTRL @ 0XFD1A0060 + + * 6 bit divider + * PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1 + + * 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock. For the half spee + * d APU Clock + * PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1 + + * Clock active signal. Switch to 0 to disable the clock. For the full spee + * d ACPUX Clock. This will shut off the high speed clock to the entire APU + * PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U) + */ + PSU_Mask_Write(CRF_APB_ACPU_CTRL_OFFSET, 0x03003F07U, 0x03000100U); +/*##################################################################### */ + + /* + * Register : DBG_FPD_CTRL @ 0XFD1A0068 + + * 6 bit divider + * PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2 + + * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_DBG_FPD_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DDR_CTRL @ 0XFD1A0080 + + * 6 bit divider + * PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2 + + * 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an i + * ssue, but designers must be aware.) + * PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DDR_CTRL_OFFSET, 0x00003F07U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : GPU_REF_CTRL @ 0XFD1A0084 + + * 6 bit divider + * PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1 + + * 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock, which will stop c + * lock for GPU (and both Pixel Processors). + * PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1 + + * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor + * PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1 + + * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor + * PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U) + */ + PSU_Mask_Write(CRF_APB_GPU_REF_CTRL_OFFSET, + 0x07003F07U, 0x07000100U); +/*##################################################################### */ + + /* + * Register : GDMA_REF_CTRL @ 0XFD1A00B8 + + * 6 bit divider + * PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_GDMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DPDMA_REF_CTRL @ 0XFD1A00BC + + * 6 bit divider + * PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_DPDMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0 + + * 6 bit divider + * PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000203U) + */ + PSU_Mask_Write(CRF_APB_TOPSW_MAIN_CTRL_OFFSET, + 0x01003F07U, 0x01000203U); +/*##################################################################### */ + + /* + * Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4 + + * 6 bit divider + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5 + + * 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U) + */ + PSU_Mask_Write(CRF_APB_TOPSW_LSBUS_CTRL_OFFSET, + 0x01003F07U, 0x01000502U); +/*##################################################################### */ + + /* + * Register : DBG_TSTMP_CTRL @ 0XFD1A00F8 + + * 6 bit divider + * PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2 + + * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DBG_TSTMP_CTRL_OFFSET, + 0x00003F07U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : IOU_TTC_APB_CLK @ 0XFF180380 + + * 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se + * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5 + * clock for the APB interface of TTC0 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se + * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5 + * clock for the APB interface of TTC1 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se + * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5 + * clock for the APB interface of TTC2 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se + * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5 + * clock for the APB interface of TTC3 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0 + + * TTC APB clock select + * (OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_IOU_TTC_APB_CLK_OFFSET, + 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : WDT_CLK_SEL @ 0XFD610100 + + * System watchdog timer clock source selection: 0: Internal APB clock 1: E + * xternal (PL clock via EMIO or Pinout clock via MIO) + * PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(FPD_SLCR_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : WDT_CLK_SEL @ 0XFF180300 + + * System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock from PL via EMIO, or from pinout via MIO + * PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050 + + * System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock pss_ref_clk + * PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_ddr_init_data(void) +{ + /* + * DDR INITIALIZATION + */ + /* + * DDR CONTROLLER RESET + */ + /* + * Register : RST_DDR_SS @ 0XFD1A0108 + + * DDR block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1 + + * DDR sub system block level reset + * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MSTR @ 0XFD070000 + + * Indicates the configuration of the device used in the system. - 00 - x4 + * device - 01 - x8 device - 10 - x16 device - 11 - x32 device + * PSU_DDRC_MSTR_DEVICE_CONFIG 0x2 + + * Choose which registers are used. - 0 - Original registers - 1 - Shadow r + * egisters + * PSU_DDRC_MSTR_FREQUENCY_MODE 0x0 + + * Only present for multi-rank configurations. Each bit represents one rank + * . For two-rank configurations, only bits[25:24] are present. - 1 - popul + * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow + * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others - + * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran + * k - 0011 - Two ranks - 1111 - Four ranks + * PSU_DDRC_MSTR_ACTIVE_RANKS 0x1 + + * SDRAM burst length used: - 0001 - Burst length of 2 (only supported for + * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur + * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other + * values are reserved. This controls the burst size used to access the SDR + * AM. This must match the burst length mode register setting in the SDRAM. + * (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) + * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH + * is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 + * PSU_DDRC_MSTR_BURST_RDWR 0x4 + + * Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low + * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for + * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC + * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi + * s bit must be set to '0'. + * PSU_DDRC_MSTR_DLL_OFF_MODE 0x0 + + * Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full + * DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter + * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is + * only supported when the SDRAM bus width is a multiple of 16, and quarter + * bus width mode is only supported when the SDRAM bus width is a multiple + * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid + * th refers to DQ bus width (excluding any ECC width). + * PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0 + + * 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D + * RAM in normal mode (1N). This register can be changed, only when the Con + * troller is in self-refresh mode. This signal must be set the same value + * as MR3 bit A3. Note: Geardown mode is not supported if the configuration + * parameter MEMC_CMD_RTN2IDLE is set + * PSU_DDRC_MSTR_GEARDOWN_MODE 0x0 + + * If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin + * g, all command signals (except chip select) are held for 2 clocks on the + * SDRAM bus. Chip select is asserted on the second cycle of the command N + * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti + * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i + * s set Note: 2T timing is not supported in DDR4 geardown mode. + * PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0 + + * When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci + * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full + * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer + * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is + * disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl + * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported + * , and this bit must be set to '0' + * PSU_DDRC_MSTR_BURSTCHOP 0x0 + + * Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d + * evice in use Present only in designs configured to support LPDDR4. + * PSU_DDRC_MSTR_LPDDR4 0x0 + + * Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device + * in use Present only in designs configured to support DDR4. + * PSU_DDRC_MSTR_DDR4 0x1 + + * Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d + * evice in use Present only in designs configured to support LPDDR3. + * PSU_DDRC_MSTR_LPDDR3 0x0 + + * Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d + * evice in use Present only in designs configured to support LPDDR2. + * PSU_DDRC_MSTR_LPDDR2 0x0 + + * Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de + * vice in use Only present in designs that support DDR3. + * PSU_DDRC_MSTR_DDR3 0x0 + + * Master Register + * (OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x81040010U) + */ + PSU_Mask_Write(DDRC_MSTR_OFFSET, 0xE30FBE3DU, 0x81040010U); +/*##################################################################### */ + + /* + * Register : MRCTRL0 @ 0XFD070010 + + * Setting this register bit to 1 triggers a mode register read or write op + * eration. When the MR operation is complete, the uMCTL2 automatically cle + * ars this bit. The other register fields of this register must be written + * in a separate APB transaction, before setting this mr_wr bit. It is rec + * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper + * ating modes. + * PSU_DDRC_MRCTRL0_MR_WR 0x0 + + * Address of the mode register that is to be written to. - 0000 - MR0 - 00 + * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR + * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data + * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als + * o used for writing to control words of RDIMMs. In that case, it correspo + * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[ + * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a + * s the bit[2:0] must be set to an appropriate value which is considered b + * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R + * DIMMs. + * PSU_DDRC_MRCTRL0_MR_ADDR 0x0 + + * Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire + * d to access all ranks, so all bits should be set to 1. However, for mult + * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess + * ary to access ranks individually. Examples (assume uMCTL2 is configured + * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x + * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran + * ks 0, 1, 2 and 3 + * PSU_DDRC_MRCTRL0_MR_RANK 0x3 + + * Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b + * efore automatic SDRAM initialization routine or not. For DDR4, this bit + * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init + * ialization. For LPDDR4, this bit can be used to program additional mode + * registers before automatic SDRAM initialization if necessary. Note: This + * must be cleared to 0 after completing Software operation. Otherwise, SD + * RAM initialization routine will not re-start. - 0 - Software interventio + * n is not allowed - 1 - Software intervention is allowed + * PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0 + + * Indicates whether the mode register operation is MRS in PDA mode or not + * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode + * PSU_DDRC_MRCTRL0_PDA_EN 0x0 + + * Indicates whether the mode register operation is MRS or WR/RD for MPR (o + * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR + * PSU_DDRC_MRCTRL0_MPR_EN 0x0 + + * Indicates whether the mode register operation is read or write. Only use + * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read + * PSU_DDRC_MRCTRL0_MR_TYPE 0x0 + + * Mode Register Read/Write Control Register 0. Note: Do not enable more th + * an one of the following fields simultaneously: - sw_init_int - pda_en - + * mpr_en + * (OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U) + */ + PSU_Mask_Write(DDRC_MRCTRL0_OFFSET, 0x8000F03FU, 0x00000030U); +/*##################################################################### */ + + /* + * Register : DERATEEN @ 0XFD070020 + + * Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us + * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d + * esigns configured to support LPDDR4. The required number of cycles for d + * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p + * eriod, and rounding up the next integer. + * PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x2 + + * Derate byte Present only in designs configured to support LPDDR2/LPDDR3/ + * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma + * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. + * PSU_DDRC_DERATEEN_DERATE_BYTE 0x0 + + * Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl + * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all + * LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ + * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8 + * 75 ns is less than a core_ddrc_core_clk period or not. + * PSU_DDRC_DERATEEN_DERATE_VALUE 0x0 + + * Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin + * g parameter derating is enabled using MR4 read value. Present only in de + * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set + * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. + * PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0 + + * Temperature Derate Enable Register + * (OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000200U) + */ + PSU_Mask_Write(DDRC_DERATEEN_OFFSET, 0x000003F3U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : DERATEINT @ 0XFD070024 + + * Interval between two MR4 reads, used to derate the timing parameters. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r + * egister must not be set to zero + * PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000 + + * Temperature Derate Interval Register + * (OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U) + */ + PSU_Mask_Write(DDRC_DERATEINT_OFFSET, 0xFFFFFFFFU, 0x00800000U); +/*##################################################################### */ + + /* + * Register : PWRCTL @ 0XFD070030 + + * Self refresh state is an intermediate state to enter to Self refresh pow + * er down state or exit Self refresh power down state for LPDDR4. This reg + * ister controls transition from the Self refresh state. - 1 - Prohibit tr + * ansition from Self refresh state - 0 - Allow transition from Self refres + * h state + * PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0 + + * A value of 1 to this register causes system to move to Self Refresh stat + * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa + * re Entry to Self Refresh - 0 - Software Exit from Self Refresh + * PSU_DDRC_PWRCTL_SELFREF_SW 0x0 + + * When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode + * when the transaction store is empty. This register must be reset to '0' + * to bring uMCTL2 out of maximum power saving mode. Present only in desig + * ns configured to support DDR4. For non-DDR4, this register should not be + * set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if + * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r + * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRCTL_MPSM_EN 0x0 + + * Enable the assertion of dfi_dram_clk_disable whenever a clock is not req + * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. + * Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only + * be asserted in Self Refresh. In DDR4, can be asserted in following: - i + * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca + * n be asserted in following: - in Self Refresh - in Power Down - in Deep + * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse + * rted in following: - in Self Refresh Power Down - in Power Down - during + * Normal operation (Clock Stop) + * PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0 + + * When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the + * transaction store is empty. This register must be reset to '0' to bring + * uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM + * initialization on deep power-down exit. Present only in designs configu + * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD + * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0 + + * If true then the uMCTL2 goes into power-down after a programmable number + * of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_ + * x32). This register bit may be re-programmed during the course of normal + * operation. + * PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0 + + * If true then the uMCTL2 puts the SDRAM into Self Refresh after a program + * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG. + * selfref_to_x32)'. This register bit may be re-programmed during the cour + * se of normal operation. + * PSU_DDRC_PWRCTL_SELFREF_EN 0x0 + + * Low Power Control Register + * (OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PWRCTL_OFFSET, 0x0000007FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PWRTMG @ 0XFD070034 + + * After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_ + * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40 + + * Minimum deep power-down time. For mDDR, value from the JEDEC specificati + * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL + * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE + * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i + * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + * ONLY. + * PSU_DDRC_PWRTMG_T_DPD_X4096 0x84 + + * After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_ + * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10 + + * Low Power Timing Register + * (OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U) + */ + PSU_Mask_Write(DDRC_PWRTMG_OFFSET, 0x00FFFF1FU, 0x00408410U); +/*##################################################################### */ + + /* + * Register : RFSHCTL0 @ 0XFD070050 + + * Threshold value in number of clock cycles before the critical refresh or + * page timer expires. A critical refresh is to be issued before this thre + * shold is reached. It is recommended that this not be changed from the de + * fault value, currently shown as 0x2. It must always be less than interna + * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u + * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i + * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n + * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo + * cks. + * PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2 + + * If the refresh timer (tRFCnom, also known as tREFI) has expired at least + * once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then + * a speculative refresh may be performed. A speculative refresh is a refr + * esh performed at a time when refresh would be useful, but before it is a + * bsolutely required. When the SDRAM bus is idle for a period of time dete + * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired + * at least once since the last refresh, then a speculative refresh is per + * formed. Speculative refreshes continues successively until there are no + * refreshes pending or until new reads or writes are issued to the uMCTL2. + * FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10 + + * The programmed value + 1 is the number of refresh timeouts that is allow + * ed to accumulate before traffic is blocked and the refreshes are forced + * to execute. Closing pages to perform a refresh is a one-time penalty tha + * t must be paid for each group of refreshes. Therefore, performing refres + * hes in a burst reduces the per-refresh penalty of these page closings. H + * igher numbers for RFSHCTL.refresh_burst slightly increases utilization; + * lower numbers decreases the worst-case latency associated with refreshes + * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh + * For information on burst refresh feature refer to section 3.9 of DDR2 J + * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe + * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF + * I cycles using the burst refresh feature. In DDR4 mode, according to Fin + * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre + * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda + * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens + * ure that tRFCmax is not violated due to a PHY-initiated update occurring + * shortly before a refresh burst was due. In this situation, the refresh + * burst will be delayed until the PHY-initiated update is complete. + * PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0 + + * - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + * traffic to flow to other banks. Per bank refresh is not supported by all + * LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4 + * PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0 + + * Refresh Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U) + */ + PSU_Mask_Write(DDRC_RFSHCTL0_OFFSET, 0x00F1F1F4U, 0x00210000U); +/*##################################################################### */ + + /* + * Register : RFSHCTL1 @ 0XFD070054 + + * Refresh timer start for rank 1 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32 0x0 + + * Refresh timer start for rank 0 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32 0x0 + + * Refresh Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD070054, 0x0FFF0FFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_RFSHCTL1_OFFSET, 0x0FFF0FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RFSHCTL3 @ 0XFD070060 + + * Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix + * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11 + * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No + * te: The on-the-fly modes is not supported in this version of the uMCTL2. + * Note: This must be set up while the Controller is in reset or while the + * Controller is in self-refresh mode. Changing this during normal operati + * on is not allowed. Making this a dynamic register will be supported in f + * uture version of the uMCTL2. + * PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0 + + * Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + * the refresh register(s) have been updated. The value is automatically up + * dated when exiting reset, so it does not need to be toggled initially. + * PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0 + + * When '1', disable auto-refresh generated by the uMCTL2. When auto-refres + * h is disabled, the SoC core must generate refreshes using the registers + * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a + * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1 + * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 + * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d + * isable auto-refresh is not supported, and this bit must be set to '0'. T + * his register field is changeable on the fly. + * PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1 + + * Refresh Control Register 3 + * (OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_RFSHCTL3_OFFSET, 0x00000073U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : RFSHTMG @ 0XFD070064 + + * tREFI: Average time interval between refreshes per rank (Specification: + * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, + * LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre + * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE + * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + * register should be set to tREFIpb For configurations with MEMC_FREQ_RAT + * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val + * ue is different depending on the refresh mode. The user should program t + * he appropriate value from the spec based on the value programmed in the + * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea + * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th + * an 0x1. Unit: Multiples of 32 clocks. + * PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x81 + + * Used only when LPDDR3 memory type is connected. Should only be changed w + * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r + * equired by some LPDDR3 devices which comply with earlier versions of the + * LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 + * - tREFBW parameter used + * PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1 + + * tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F + * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t + * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro + * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using + * all-bank refreshes, the tRFCmin value in the above equations is equal to + * tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq + * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above + * equations is different depending on the refresh mode (fixed 1X,2X,4X) an + * d the device density. The user should program the appropriate value from + * the spec based on the 'refresh_mode' and the device density that is use + * d. Unit: Clocks. + * PSU_DDRC_RFSHTMG_T_RFC_MIN 0xbb + + * Refresh Timing Register + * (OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x008180BBU) + */ + PSU_Mask_Write(DDRC_RFSHTMG_OFFSET, 0x0FFF83FFU, 0x008180BBU); +/*##################################################################### */ + + /* + * Register : ECCCFG0 @ 0XFD070070 + + * Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U + * SE_RMW is defined + * PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1 + + * ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov + * er 1 beat - all other settings are reserved for future use + * PSU_DDRC_ECCCFG0_ECC_MODE 0x0 + + * ECC Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U) + */ + PSU_Mask_Write(DDRC_ECCCFG0_OFFSET, 0x00000017U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : ECCCFG1 @ 0XFD070074 + + * Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da + * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat + * a_poison_en=1 + * PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0 + + * Enable ECC data poisoning - introduces ECC errors on writes to address s + * pecified by the ECCPOISONADDR0/1 registers + * PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0 + + * ECC Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_ECCCFG1_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CRCPARCTL1 @ 0XFD0700C4 + + * The maximum number of DFI PHY clock cycles allowed from the assertion of + * the dfi_rddata_en signal to the assertion of each of the corresponding + * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing + * parameter tphy_rdlat. Refer to PHY specification for correct value. This + * value it only used for detecting read data timeout when DDR4 retry is e + * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: + * - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r + * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 + * : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d + * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ + * rdlat < 'd114 Unit: DFI Clocks + * PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10 + + * After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa + * re has an option to read the mode registers in the DRAM before the hardw + * are begins the retry process - 1: Wait for software to read/write the mo + * de registers before hardware begins the retry. After software is done wi + * th its operations, it will clear the alert interrupt register bit - 0: H + * ardware can begin the retry right away after the dfi_alert_n pulse goes + * away. The value on this register is valid only when retry is enabled (PA + * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t + * he software doesn't clear the interrupt register after handling the pari + * ty/CRC error, then the hardware will not begin the retry process and the + * system will hang. In the case of Parity/CRC error, there are two possib + * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten + * t parity' mode register bit is NOT set: the commands sent during retry a + * nd normal operation are executed without parity checking. The value in t + * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent + * parity' mode register bit is SET: Parity checking is done for commands s + * ent during retry and normal operation. If multiple errors occur before M + * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don' + * t care'. + * PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1 + + * - 1: Enable command retry mechanism in case of C/A Parity or CRC error - + * 0: Disable command retry mechanism when C/A Parity or CRC features are + * enabled. Note that retry functionality is not supported if burst chop is + * enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF + * SHCTL3.dis_auto_refresh = 1) + * PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0 + + * CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no + * t includes DM signal Present only in designs configured to support DDR4. + * PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0 + + * CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio + * n of CRC The setting of this register should match the CRC mode register + * setting in the DRAM. + * PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0 + + * C/A Parity enable register - 1: Enable generation of C/A parity and dete + * ction of C/A parity error - 0: Disable generation of C/A parity and disa + * ble detection of C/A parity error If RCD's parity error detection or SDR + * AM's parity detection is enabled, this register should be 1. + * PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0 + + * CRC Parity Control Register1 + * (OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U) + */ + PSU_Mask_Write(DDRC_CRCPARCTL1_OFFSET, 0x3F000391U, 0x10000200U); +/*##################################################################### */ + + /* + * Register : CRCPARCTL2 @ 0XFD0700C8 + + * Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M + * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT + * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i + * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. + * PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40 + + * Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX + * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW + * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille + * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. + * PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5 + + * Indicates the maximum duration in number of DRAM clock cycles for which + * a command should be held in the Command Retry FIFO before it is popped o + * ut. Every location in the Command Retry FIFO has an associated down coun + * ting timer that will use this register as the start value. The down coun + * ting starts when a command is loaded into the FIFO. The timer counts dow + * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe + * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err + * or occurs before the counter reaches zero. The counter is reset to 0, af + * ter all the commands in the FIFO are retried. Recommended(minimum) value + * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten + * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable + * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R + * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be + * in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n + * ) should be considered. Note 3: Use the worst case(longer) value for PHY + * Latencies/Board delay Note 4: The Recommended values are minimum value + * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max + * value can be set to this register is defined below: - MEMC_BURST_LENGTH + * == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 + * Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b + * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod + * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C + * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC= + * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 + * Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full + * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod + * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC + * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF + * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma + * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal + * . + * PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f + + * CRC Parity Control Register2 + * (OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU) + */ + PSU_Mask_Write(DDRC_CRCPARCTL2_OFFSET, 0x01FF1F3FU, 0x0040051FU); +/*##################################################################### */ + + /* + * Register : INIT0 @ 0XFD0700D0 + + * If lower bit is enabled the SDRAM initialization routine is skipped. The + * upper bit decides what state the controller starts up in when reset is + * removed - 00 - SDRAM Intialization routine is run after power-up - 01 - + * SDRAM Intialization routine is skipped after power-up. Controller starts + * up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p + * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ + * ation routine is run after power-up. Note: The only 2'b00 is supported f + * or LPDDR4 in this version of the uMCTL2. + * PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0 + + * Cycles to wait after driving CKE high to start the SDRAM initialization + * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req + * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD + * R3 typically requires this to be programmed for a delay of 200 us. LPDDR + * 4 typically requires this to be programmed for a delay of 2 us. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi + * ded by 2, and round it up to next integer value. + * PSU_DDRC_INIT0_POST_CKE_X1024 0x2 + + * Cycles to wait after reset before driving CKE high to start the SDRAM in + * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi + * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD + * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati + * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by + * 2, and round it up to next integer value. + * PSU_DDRC_INIT0_PRE_CKE_X1024 0x106 + + * SDRAM Initialization Register 0 + * (OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U) + */ + PSU_Mask_Write(DDRC_INIT0_OFFSET, 0xC3FF0FFFU, 0x00020106U); +/*##################################################################### */ + + /* + * Register : INIT1 @ 0XFD0700D4 + + * Number of cycles to assert SDRAM reset signal during init sequence. This + * is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo + * r use with a DDR PHY, this should be set to a minimum of 1 + * PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2 + + * Cycles to wait after completing the SDRAM initialization sequence before + * starting the dynamic scheduler. Unit: Counts of a global timer that pul + * ses every 32 clock cycles. There is no known specific requirement for th + * is; it may be set to zero. + * PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0 + + * Wait period before driving the OCD complete command to SDRAM. Unit: Coun + * ts of a global timer that pulses every 32 clock cycles. There is no know + * n specific requirement for this; it may be set to zero. + * PSU_DDRC_INIT1_PRE_OCD_X32 0x0 + + * SDRAM Initialization Register 1 + * (OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U) + */ + PSU_Mask_Write(DDRC_INIT1_OFFSET, 0x01FF7F0FU, 0x00020000U); +/*##################################################################### */ + + /* + * Register : INIT2 @ 0XFD0700D8 + + * Idle time after the reset command, tINIT4. Present only in designs confi + * gured to support LPDDR2. Unit: 32 clock cycles. + * PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23 + + * Time to wait after the first CKE high, tINIT2. Present only in designs c + * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t + * ypically requires 5 x tCK delay. + * PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5 + + * SDRAM Initialization Register 2 + * (OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U) + */ + PSU_Mask_Write(DDRC_INIT2_OFFSET, 0x0000FF0FU, 0x00002305U); +/*##################################################################### */ + + /* + * Register : INIT3 @ 0XFD0700DC + + * DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he + * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value + * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP + * DDR3/LPDDR4 - Value to write to MR1 register + * PSU_DDRC_INIT3_MR 0x730 + + * DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti + * ng in this register is ignored. The uMCTL2 sets those bits appropriately + * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu + * ation mode training is enabled, this bit is set appropriately by the uMC + * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/ + * LPDDR3/LPDDR4 - Value to write to MR2 register + * PSU_DDRC_INIT3_EMR 0x301 + + * SDRAM Initialization Register 3 + * (OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x07300301U) + */ + PSU_Mask_Write(DDRC_INIT3_OFFSET, 0xFFFFFFFFU, 0x07300301U); +/*##################################################################### */ + + /* + * Register : INIT4 @ 0XFD0700E0 + + * DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 + * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus + * ed + * PSU_DDRC_INIT4_EMR2 0x20 + + * DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 + * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis + * ter + * PSU_DDRC_INIT4_EMR3 0x200 + + * SDRAM Initialization Register 4 + * (OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U) + */ + PSU_Mask_Write(DDRC_INIT4_OFFSET, 0xFFFFFFFFU, 0x00200200U); +/*##################################################################### */ + + /* + * Register : INIT5 @ 0XFD0700E4 + + * ZQ initial calibration, tZQINIT. Present only in designs configured to s + * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica + * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir + * es 1 us. + * PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21 + + * Maximum duration of the auto initialization, tINIT5. Present only in des + * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir + * es 10 us. + * PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4 + + * SDRAM Initialization Register 5 + * (OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U) + */ + PSU_Mask_Write(DDRC_INIT5_OFFSET, 0x00FF03FFU, 0x00210004U); +/*##################################################################### */ + + /* + * Register : INIT6 @ 0XFD0700E8 + + * DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT6_MR4 0x0 + + * DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT6_MR5 0x6c0 + + * SDRAM Initialization Register 6 + * (OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U) + */ + PSU_Mask_Write(DDRC_INIT6_OFFSET, 0xFFFFFFFFU, 0x000006C0U); +/*##################################################################### */ + + /* + * Register : INIT7 @ 0XFD0700EC + + * DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT7_MR6 0x819 + + * SDRAM Initialization Register 7 + * (OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U) + */ + PSU_Mask_Write(DDRC_INIT7_OFFSET, 0xFFFF0000U, 0x08190000U); +/*##################################################################### */ + + /* + * Register : DIMMCTL @ 0XFD0700F0 + + * Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r + * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp + * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. + * PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0 + + * Enable for BG1 bit of MRS command. BG1 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have BG1 are attached and + * both the CA parity and the Output Inversion are enabled, this must be s + * et to 0, so that the calculation of CA parity will not include BG1 bit. + * Note: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. If address mirroring is enab + * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En + * abled - 0 - Disabled + * PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1 + + * Enable for A17 bit of MRS command. A17 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have A17 are attached and + * the Output Inversion are enabled, this must be set to 0, so that the ca + * lculation of CA parity will not include A17 bit. Note: This has no effec + * t on the address of any other memory accesses, or of software-driven mod + * e register accesses. - 1 - Enabled - 0 - Disabled + * PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0 + + * Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM + * M implements the Output Inversion feature by default, which means that t + * he following address, bank address and bank group bits of B-side DRAMs a + * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en + * sures that, for mode register accesses generated by the uMCTL2 during th + * e automatic initialization routine and enabling of a particular DDR4 fea + * ture, separate A-side and B-side mode register accesses are generated. F + * or B-side mode register accesses, these bits are inverted within the uMC + * TL2 to compensate for this RDIMM inversion. Note: This has no effect on + * the address of any other memory accesses, or of software-driven mode reg + * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - + * Do not implement output inversion for B-side DRAMs. + * PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0 + + * Address Mirroring Enable (for multi-rank UDIMM implementations and multi + * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement + * address mirroring for odd ranks, which means that the following address + * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, + * A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t + * his bit ensures that, for mode register accesses during the automatic in + * itialization routine, these bits are swapped within the uMCTL2 to compen + * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial + * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th + * e automatic MRS access to enable/disable of a particular DDR4 feature. N + * ote: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. This is not supported for mDD + * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 + * output of MRS for the odd ranks is same as BG0 because BG1 is invalid, + * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran + * ks, implement address mirroring for MRS commands to during initializatio + * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp + * lements address mirroring) - 0 - Do not implement address mirroring + * PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0 + + * Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM + * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 + * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of + * software driven MR commands (via MRCTRL0/MRCTRL1), where software is re + * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se + * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma + * nds to even and odd ranks seperately - 0 - Do not stagger accesses + * PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0 + + * DIMM Control Register + * (OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U) + */ + PSU_Mask_Write(DDRC_DIMMCTL_OFFSET, 0x0000003FU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : RANKCTL @ 0XFD0700F4 + + * Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive writes to differ + * ent ranks. This is used to switch the delays in the PHY to match the ran + * k requirements. This value should consider both PHY requirement and ODT + * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v + * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by + * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas + * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc + * reased by 1. - ODT requirement: The value programmed in this register ta + * kes care of the ODT switch off timing requirement when switching ranks d + * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 + * For configurations with MEMC_FREQ_RATIO=1, program this to the larger o + * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_ + * RATIO=2, program this to the larger value divided by two and round it up + * to the next integer. + * PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6 + + * Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive reads to differe + * nt ranks. This is used to switch the delays in the PHY to match the rank + * requirements. This value should consider both PHY requirement and ODT r + * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va + * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), + * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only + * ), should be increased by 1. - ODT requirement: The value programmed in + * this register takes care of the ODT switch off timing requirement when s + * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, + * program this to the larger of PHY requirement or ODT requirement. For co + * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di + * vided by two and round it up to the next integer. + * PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6 + + * Only present for multi-rank configurations. Background: Reads to the sam + * e rank can be performed back-to-back. Reads to different ranks require a + * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is + * to avoid possible data bus contention as well as to give PHY enough tim + * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus + * access on a cycle-by-cycle basis; therefore after a read is scheduled, + * there are few clock cycles (determined by the value on RANKCTL.diff_rank + * _rd_gap register) in which only reads from the same rank are eligible to + * be scheduled. This prevents reads from other ranks from having fair acc + * ess to the data bus. This parameter represents the maximum number of rea + * ds that can be scheduled consecutively to the same rank. After this numb + * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by + * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig + * her numbers increase bandwidth utilization, lower numbers increase fairn + * ess. This feature can be DISABLED by setting this register to 0. When se + * t to 0, the Controller will stay on the same rank as long as commands ar + * e available for it. Minimum programmable value is 0 (feature disabled) a + * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY. + * PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf + + * Rank Control Register + * (OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU) + */ + PSU_Mask_Write(DDRC_RANKCTL_OFFSET, 0x00000FFFU, 0x0000066FU); +/*##################################################################### */ + + /* + * Register : DRAMTMG0 @ 0XFD070100 + + * Minimum time between write and precharge to same bank. Unit: Clocks Spec + * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks + * @400MHz and less for lower frequencies where: - WL = write latency - BL + * = burst length. This must match the value programmed in the BL bit of t + * he mode register to the SDRAM. BST (burst terminate) is not supported at + * present. - tWR = Write recovery time. This comes directly from the SDRA + * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p + * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the + * above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT + * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u + * p to the next integer value. + * PSU_DDRC_DRAMTMG0_WR2PRE 0x11 + + * tFAW Valid only when 8 or more banks(or banks x bank groups) are present + * . In 8-bank design, at most 4 banks must be activated in a rolling windo + * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se + * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + * Unit: Clocks + * PSU_DDRC_DRAMTMG0_T_FAW 0x10 + + * tRAS(max): Maximum time between activate and precharge to same bank. Thi + * s is the maximum time that a page can be kept open Minimum value of this + * register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO + * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of + * 1024 clocks. + * PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24 + + * tRAS(min): Minimum time between activate and precharge to the same bank. + * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA + * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T + * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th + * e next integer value. Unit: Clocks + * PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12 + + * SDRAM Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x11102412U) + */ + PSU_Mask_Write(DDRC_DRAMTMG0_OFFSET, 0x7F3F7F3FU, 0x11102412U); +/*##################################################################### */ + + /* + * Register : DRAMTMG1 @ 0XFD070104 + + * tXP: Minimum time after power-down exit to any operation. For DDR3, this + * should be programmed to tXPDLL if slow powerdown exit is selected in MR + * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it + * up to the next integer value. Units: Clocks + * PSU_DDRC_DRAMTMG1_T_XP 0x4 + + * tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL + * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi + * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 + * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t + * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) + * - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_ + * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi + * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo + * ve value by 2 and round it up to the next integer value. Unit: Clocks. + * PSU_DDRC_DRAMTMG1_RD2PRE 0x4 + + * tRC: Minimum time between activates to same bank. For configurations wit + * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege + * r value. Unit: Clocks. + * PSU_DDRC_DRAMTMG1_T_RC 0x1a + + * SDRAM Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x0004041AU) + */ + PSU_Mask_Write(DDRC_DRAMTMG1_OFFSET, 0x001F1F7FU, 0x0004041AU); +/*##################################################################### */ + + /* + * Register : DRAMTMG2 @ 0XFD070108 + + * Set to WL Time from write command to write data on SDRAM interface. This + * must be set to WL. For mDDR, it should normally be set to 1. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use a valu + * e of WL + 1 to compensate for the extra cycle of latency through the RDI + * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate + * d using the above equation by 2, and round it up to next integer. This r + * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING + * is set), as the DFI read and write latencies defined in DFITMG0 and DFI + * TMG1 are sufficient for those protocols Unit: clocks + * PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7 + + * Set to RL Time from read command to read data on SDRAM interface. This m + * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma + * t be necessary to use a value of RL + 1 to compensate for the extra cycl + * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2 + * , divide the value calculated using the above equation by 2, and round i + * t up to next integer. This register field is not required for DDR2 and D + * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie + * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit + * : clocks + * PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8 + + * DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L + * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di + * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL + * LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL + * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write + * command. Include time for bus turnaround and all per-bank, per-rank, an + * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b + * urst length. This must match the value programmed in the BL bit of the m + * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL + * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = + * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d + * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should + * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal + * culated using the above equation by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG2_RD2WR 0x6 + + * DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu + * m time from write command to read command for same bank group. In others + * , minimum time from write command to read command. Includes time for bus + * turnaround, recovery times, and all per-bank, per-rank, and global cons + * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la + * tency - BL = burst length. This must match the value programmed in the B + * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea + * d command delay for same bank group. This comes directly from the SDRAM + * specification. - tWTR = internal write to read command delay. This comes + * directly from the SDRAM specification. Add one extra cycle for LPDDR2/L + * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid + * e the value calculated using the above equation by 2, and round it up to + * next integer. + * PSU_DDRC_DRAMTMG2_WR2RD 0xd + + * SDRAM Timing Register 2 + * (OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060DU) + */ + PSU_Mask_Write(DDRC_DRAMTMG2_OFFSET, 0x3F3F3F3FU, 0x0708060DU); +/*##################################################################### */ + + /* + * Register : DRAMTMG3 @ 0XFD07010C + + * Time to wait after a mode register write or read (MRW or MRR). Present o + * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty + * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD + * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist + * er is used for the time from a MRW/MRR to all other commands. For LDPDR3 + * , this register is used for the time from a MRW/MRR to a MRW/MRR. + * PSU_DDRC_DRAMTMG3_T_MRW 0x5 + + * tMRD: Cycles to wait after a mode register write or read. Depending on t + * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com + * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim + * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2, + * program this to (tMRD/2) and round it up to the next integer value. If + * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. + * PSU_DDRC_DRAMTMG3_T_MRD 0x4 + + * tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com + * mand and following non-load mode command. If C/A parity for DDR4 is used + * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or + * tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if + * using RDIMM, depending on the PHY, it may be necessary to use a value of + * tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a + * pplied to mode register writes by the RDIMM chip. + * PSU_DDRC_DRAMTMG3_T_MOD 0xc + + * SDRAM Timing Register 3 + * (OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU) + */ + PSU_Mask_Write(DDRC_DRAMTMG3_OFFSET, 0x3FF3F3FFU, 0x0050400CU); +/*##################################################################### */ + + /* + * Register : DRAMTMG4 @ 0XFD070110 + + * tRCD - tAL: Minimum time from activate to read or write command to same + * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD + * - tAL)/2) and round it up to the next integer value. Minimum value allow + * ed for this register is 1, which implies minimum (tRCD - tAL) value to b + * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. + * PSU_DDRC_DRAMTMG4_T_RCD 0x8 + + * DDR4: tCCD_L: This is the minimum time between two reads or two writes f + * or same bank group. Others: tCCD: This is the minimum time between two r + * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t + * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U + * nit: clocks. + * PSU_DDRC_DRAMTMG4_T_CCD 0x3 + + * DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f + * or same bank group. Others: tRRD: Minimum time between activates from ba + * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni + * t: Clocks. + * PSU_DDRC_DRAMTMG4_T_RRD 0x4 + + * tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ + * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM + * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t + * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho + * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. + * PSU_DDRC_DRAMTMG4_T_RP 0x9 + + * SDRAM Timing Register 4 + * (OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030409U) + */ + PSU_Mask_Write(DDRC_DRAMTMG4_OFFSET, 0x1F0F0F1FU, 0x08030409U); +/*##################################################################### */ + + /* + * Register : DRAMTMG5 @ 0XFD070114 + + * This is the time before Self Refresh Exit that CK is maintained as a val + * id clock before issuing SRX. Specifies the clock stable time before SRX. + * Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK + * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKSRX 0x6 + + * This is the time after Self Refresh Down Entry that CK is maintained as + * a valid clock. Specifies the clock disable delay after SRE. Recommended + * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 + * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations + * with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw + * o and round it up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKSRE 0x6 + + * Minimum CKE low width for Self refresh or Self refresh power down entry + * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF + * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: + * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ + * _RATIO=2, program this to recommended value divided by two and round it + * up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKESR 0x4 + + * Minimum number of cycles of CKE HIGH/LOW during power-down and self refr + * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP + * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/ + * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration + * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and + * round it up to the next integer value. Unit: Clocks. + * PSU_DDRC_DRAMTMG5_T_CKE 0x3 + + * SDRAM Timing Register 5 + * (OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U) + */ + PSU_Mask_Write(DDRC_DRAMTMG5_OFFSET, 0x0F0F3F1FU, 0x06060403U); +/*##################################################################### */ + + /* + * Register : DRAMTMG6 @ 0XFD070118 + + * This is the time after Deep Power Down Entry that CK is maintained as a + * valid clock. Specifies the clock disable delay after DPDE. Recommended s + * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. This is only present for designs supporting mDDR + * or LPDDR2/LPDDR3 devices. + * PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1 + + * This is the time before Deep Power Down Exit that CK is maintained as a + * valid clock before issuing DPDX. Specifies the clock stable time before + * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config + * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid + * ed by two and round it up to next integer. This is only present for desi + * gns supporting mDDR or LPDDR2 devices. + * PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1 + + * This is the time before Clock Stop Exit that CK is maintained as a valid + * clock before issuing Clock Stop Exit. Specifies the clock stable time b + * efore next command after Clock Stop Exit. Recommended settings: - mDDR: + * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio + * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by + * two and round it up to next integer. This is only present for designs su + * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG6_T_CKCSX 0x4 + + * SDRAM Timing Register 6 + * (OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U) + */ + PSU_Mask_Write(DDRC_DRAMTMG6_OFFSET, 0x0F0F000FU, 0x01010004U); +/*##################################################################### */ + + /* + * Register : DRAMTMG7 @ 0XFD07011C + + * This is the time after Power Down Entry that CK is maintained as a valid + * clock. Specifies the clock disable delay after PDE. Recommended setting + * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration + * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t + * wo and round it up to next integer. This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG7_T_CKPDE 0x6 + + * This is the time before Power Down Exit that CK is maintained as a valid + * clock before issuing PDX. Specifies the clock stable time before PDX. R + * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c + * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value + * divided by two and round it up to next integer. This is only present for + * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG7_T_CKPDX 0x6 + + * SDRAM Timing Register 7 + * (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U) + */ + PSU_Mask_Write(DDRC_DRAMTMG7_OFFSET, 0x00000F0FU, 0x00000606U); +/*##################################################################### */ + + /* + * Register : DRAMTMG8 @ 0XFD070120 + + * tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and + * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this + * to the above value divided by 2 and round up to next integer value. Unit + * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com + * mands. Note: Ensure this is less than or equal to t_xs_x32. + * PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x4 + + * tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S + * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th + * is to the above value divided by 2 and round up to next integer value. U + * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to + * t_xs_x32. + * PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x4 + + * tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config + * urations with MEMC_FREQ_RATIO=2, program this to the above value divided + * by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + * PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd + + * tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi + * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide + * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + * PSU_DDRC_DRAMTMG8_T_XS_X32 0x7 + + * SDRAM Timing Register 8 + * (OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x04040D07U) + */ + PSU_Mask_Write(DDRC_DRAMTMG8_OFFSET, 0x7F7F7F7FU, 0x04040D07U); +/*##################################################################### */ + + /* + * Register : DRAMTMG9 @ 0XFD070124 + + * DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o + * nly with MEMC_FREQ_RATIO=2 + * PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0 + + * tCCD_S: This is the minimum time between two reads or two writes for dif + * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m + * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2 + * , program this to (tCCD_S/2) and round it up to the next integer value. + * Present only in designs configured to support DDR4. Unit: clocks. + * PSU_DDRC_DRAMTMG9_T_CCD_S 0x2 + + * tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif + * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th + * is to (tRRD_S/2) and round it up to the next integer value. Present only + * in designs configured to support DDR4. Unit: Clocks. + * PSU_DDRC_DRAMTMG9_T_RRD_S 0x3 + + * CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command + * for different bank group. Includes time for bus turnaround, recovery ti + * mes, and all per-bank, per-rank, and global constraints. Present only in + * designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr + * ite latency - PL = Parity latency - BL = burst length. This must match t + * he value programmed in the BL bit of the mode register to the SDRAM - tW + * TR_S = internal write to read command delay for different bank group. Th + * is comes directly from the SDRAM specification. For configurations with + * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation + * by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG9_WR2RD_S 0xb + + * SDRAM Timing Register 9 + * (OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002030BU) + */ + PSU_Mask_Write(DDRC_DRAMTMG9_OFFSET, 0x40070F3FU, 0x0002030BU); +/*##################################################################### */ + + /* + * Register : DRAMTMG11 @ 0XFD07012C + + * tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL + * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2 + * ) and round it up to the next integer value. Present only in designs con + * figured to support DDR4. Unit: Multiples of 32 clocks. + * PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x12 + + * tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For + * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2 + * )+1. Present only in designs configured to support DDR4. Unit: clocks. + * PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7 + + * tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_ + * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int + * eger value. Present only in designs configured to support DDR4. Unit: Cl + * ocks. + * PSU_DDRC_DRAMTMG11_T_MPX_S 0x1 + + * tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i + * n designs configured to support DDR4. Unit: Clocks. For configurations w + * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat + * ion by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG11_T_CKMPE 0xe + + * SDRAM Timing Register 11 + * (OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x1207010EU) + */ + PSU_Mask_Write(DDRC_DRAMTMG11_OFFSET, 0x7F1F031FU, 0x1207010EU); +/*##################################################################### */ + + /* + * Register : DRAMTMG12 @ 0XFD070130 + + * tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg + * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr + * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu + * e. + * PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2 + + * tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat + * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u + * p to next integer value. + * PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6 + + * tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2) + * and round it up to next integer value. + * PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8 + + * SDRAM Timing Register 12 + * (OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U) + */ + PSU_Mask_Write(DDRC_DRAMTMG12_OFFSET, 0x00030F1FU, 0x00020608U); +/*##################################################################### */ + + /* + * Register : ZQCTL0 @ 0XFD070180 + + * - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg + * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration + * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati + * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre + * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1 + + * - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres + * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 + * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio + * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i + * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present + * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0 + + * - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC + * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co + * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share + * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR + * 3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0 + + * - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. + * Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com + * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4 + * mode. This is only present for designs supporting DDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0 + + * tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe + * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St + * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO + * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int + * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th + * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t + * o the next integer value. Unit: Clock cycles. This is only present for d + * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100 + + * tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of + * NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command + * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t + * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy + * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP + * DDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40 + + * ZQ Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U) + */ + PSU_Mask_Write(DDRC_ZQCTL0_OFFSET, 0xF7FF03FFU, 0x81000040U); +/*##################################################################### */ + + /* + * Register : ZQCTL1 @ 0XFD070184 + + * tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati + * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_ + * RATIO=2, program this to tZQReset/2 and round it up to the next integer + * value. Unit: Clock cycles. This is only present for designs supporting L + * PDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20 + + * Average interval to wait between automatically issuing ZQCS (ZQ calibrat + * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR + * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles + * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 + * /LPDDR4 devices. + * PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x196e5 + + * ZQ Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x020196E5U) + */ + PSU_Mask_Write(DDRC_ZQCTL1_OFFSET, 0x3FFFFFFFU, 0x020196E5U); +/*##################################################################### */ + + /* + * Register : DFITMG0 @ 0XFD070190 + + * Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. + * PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4 + + * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. + * PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1 + + * Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks + * PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb + + * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. + * PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1 + + * Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks + * PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2 + + * Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. + * PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb + + * DFI Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU) + */ + PSU_Mask_Write(DDRC_DFITMG0_OFFSET, 0x1FBFBF3FU, 0x048B820BU); +/*##################################################################### */ + + /* + * Register : DFITMG1 @ 0XFD070194 + + * Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated command is driven. This field is used + * for CAL mode, should be set to '0' or the value which matches the CAL mo + * de register setting in the DRAM. If the PHY can add the latency for CAL + * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 + * PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0 + + * Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated dfi_parity_in signal is driven. + * PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0 + + * Specifies the number of DFI clocks between when the dfi_wrdata_en signal + * is asserted and when the corresponding write data transfer is completed + * on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d + * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set + * to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI + * 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va + * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_ + * RATIO=2, divide PHY's value by 2 and round up to next integer. If using + * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks + * PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3 + + * Specifies the number of DFI clock cycles from the assertion of the dfi_d + * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev + * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock + * and the memory clock are not phase aligned, this timing parameter should + * be rounded up to the next integer value. + * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3 + + * Specifies the number of DFI clock cycles from the de-assertion of the df + * i_dram_clk_disable signal on the DFI until the first valid rising edge o + * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the + * DFI clock and the memory clock are not phase aligned, this timing param + * eter should be rounded up to the next integer value. + * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4 + + * DFI Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U) + */ + PSU_Mask_Write(DDRC_DFITMG1_OFFSET, 0xF31F0F0FU, 0x00030304U); +/*##################################################################### */ + + /* + * Register : DFILPCFG0 @ 0XFD070198 + + * Setting for DFI's tlp_resp time. Same value is used for both Power Down, + * Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s + * pecification onwards, recommends using a fixed value of 7 always. + * PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7 + + * Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente + * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 + * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5 + * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - + * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553 + * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T + * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices + * . + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0 + + * Enables DFI Low Power interface handshaking during Deep Power Down Entry + * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3 devices. + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0 + + * Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered + * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc + * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 + * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 + * - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c + * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0 + + * Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex + * it. - 0 - Disabled - 1 - Enabled + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1 + + * Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle + * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy + * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - + * 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc + * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0 + + * Enables DFI Low Power interface handshaking during Power Down Entry/Exit + * . - 0 - Disabled - 1 - Enabled + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1 + + * DFI Low Power Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U) + */ + PSU_Mask_Write(DDRC_DFILPCFG0_OFFSET, 0x0FF1F1F1U, 0x07000101U); +/*##################################################################### */ + + /* + * Register : DFILPCFG1 @ 0XFD07019C + + * Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is + * entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 + * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x + * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl + * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - + * 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi + * ted This is only present for designs supporting DDR4 devices. + * PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2 + + * Enables DFI Low Power interface handshaking during Maximum Power Saving + * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d + * esigns supporting DDR4 devices. + * PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1 + + * DFI Low Power Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U) + */ + PSU_Mask_Write(DDRC_DFILPCFG1_OFFSET, 0x000000F1U, 0x00000021U); +/*##################################################################### */ + + /* + * Register : DFIUPD0 @ 0XFD0701A0 + + * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc + * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. + * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD 0x0 + + * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * following a self-refresh exit. The core must issue the dfi_ctrlupd_req + * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct + * rlupd_req after exiting self-refresh. + * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX 0x0 + + * Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si + * gnal can assert. Lowest value to assign to this variable is 0x40. Unit: + * Clocks + * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MAX 0x40 + + * Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si + * gnal must be asserted. The uMCTL2 expects the PHY to respond within this + * time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup + * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this + * variable is 0x3. Unit: Clocks + * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MIN 0x3 + + * DFI Update Register 0 + * (OFFSET, MASK, VALUE) (0XFD0701A0, 0xC3FF03FFU ,0x00400003U) + */ + PSU_Mask_Write(DDRC_DFIUPD0_OFFSET, 0xC3FF03FFU, 0x00400003U); +/*##################################################################### */ + + /* + * Register : DFIUPD1 @ 0XFD0701A4 + + * This is the minimum amount of time between uMCTL2 initiated DFI update r + * equests (which is executed whenever the uMCTL2 is idle). Set this number + * higher to reduce the frequency of update requests, which can have a sma + * ll impact on the latency of the first read request when the uMCTL2 is id + * le. Unit: 1024 clocks + * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0xc8 + + * This is the maximum amount of time between uMCTL2 initiated DFI update r + * equests. This timer resets with each update request; when the timer expi + * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd + * _ackx is received. PHY can use this idle time to recalibrate the delay l + * ines to the DLLs. The DFI controller update is also used to reset PHY FI + * FO pointers in case of data capture errors. Updates are required to main + * tain calibration over PVT, but frequent updates may impact performance. + * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must + * be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl + * ocks + * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xff + + * DFI Update Register 1 + * (OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x00C800FFU) + */ + PSU_Mask_Write(DDRC_DFIUPD1_OFFSET, 0x00FF00FFU, 0x00C800FFU); +/*##################################################################### */ + + /* + * Register : DFIMISC @ 0XFD0701B0 + + * Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal + * s are active low - 1: Signals are active high + * PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0 + + * DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. + * - 1 - PHY implements DBI functionality. Present only in designs configu + * red to support DDR4 and LPDDR4. + * PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0 + + * PHY initialization complete enable signal. When asserted the dfi_init_co + * mplete signal can be used to trigger SDRAM initialisation + * PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0 + + * DFI Miscellaneous Control Register + * (OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DFIMISC_OFFSET, 0x00000007U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DFITMG2 @ 0XFD0701B4 + + * >Number of clocks between when a read command is sent on the DFI control + * interface and when the associated dfi_rddata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe + * cification for correct value. + * PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9 + + * Number of clocks between when a write command is sent on the DFI control + * interface and when the associated dfi_wrdata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe + * cification for correct value. + * PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x9 + + * DFI Timing Register 2 + * (OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000909U) + */ + PSU_Mask_Write(DDRC_DFITMG2_OFFSET, 0x00003F3FU, 0x00000909U); +/*##################################################################### */ + + /* + * Register : DBICTL @ 0XFD0701C0 + + * Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D + * BI is enabled. This signal must be set the same value as DRAM's mode reg + * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b + * e set to 0. - LPDDR4: MR3[6] + * PSU_DDRC_DBICTL_RD_DBI_EN 0x0 + + * Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ + * e DBI is enabled. This signal must be set the same value as DRAM's mode + * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus + * t be set to 0. - LPDDR4: MR3[7] + * PSU_DDRC_DBICTL_WR_DBI_EN 0x0 + + * DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi + * s signal must be set the same logical value as DRAM's mode register. - D + * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th + * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13 + * [5] which is opposite polarity from this signal + * PSU_DDRC_DBICTL_DM_EN 0x1 + + * DM/DBI Control Register + * (OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_DBICTL_OFFSET, 0x00000007U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : ADDRMAP0 @ 0XFD070200 + + * Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t + * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, r + * ank address bit 0 is set to 0. + * PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f + + * Address Map Register 0 + * (OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP0_OFFSET, 0x0000001FU, 0x0000001FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP1 @ 0XFD070204 + + * Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t + * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, ba + * nk address bit 2 is set to 0. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f + + * Selects the HIF address bits used as bank address bit 1. Valid Range: 0 + * to 30 Internal Base: 3 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0x9 + + * Selects the HIF address bits used as bank address bit 0. Valid Range: 0 + * to 30 Internal Base: 2 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0x9 + + * Address Map Register 1 + * (OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0909U) + */ + PSU_Mask_Write(DDRC_ADDRMAP1_OFFSET, 0x001F1F1FU, 0x001F0909U); +/*##################################################################### */ + + /* + * Register : ADDRMAP2 @ 0XFD070208 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base + * : 5 The selected HIF address bit is determined by adding the internal ba + * se to the value of this field. If set to 15, this column address bit is + * set to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x1 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: + * 4 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x1 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1 + * 6, it is required to program this to 0, hence register does not exist in + * this case. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x1 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 + * or 16, it is required to program this to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0 + + * Address Map Register 2 + * (OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x01010100U) + */ + PSU_Mask_Write(DDRC_ADDRMAP2_OFFSET, 0x0F0F0F0FU, 0x01010100U); +/*##################################################################### */ + + /* + * Register : ADDRMAP3 @ 0XFD07020C + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: + * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/ + * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + * HIF address bit is determined by adding the internal base to the value o + * f this field. If set to 15, this column address bit is set to 0. Note: P + * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo + * r indicating auto-precharge, and hence no source address bit can be mapp + * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit + * for auto-precharge in the CA bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x1 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 + * to 7, and 15 Internal Base: 8 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi + * cation, column address bit 10 is reserved for indicating auto-precharge, + * and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA + * bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x1 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: + * 7 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x1 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: + * 6 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x1 + + * Address Map Register 3 + * (OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x01010101U) + */ + PSU_Mask_Write(DDRC_ADDRMAP3_OFFSET, 0x0F0F0F0FU, 0x01010101U); +/*##################################################################### */ + + /* + * Register : ADDRMAP4 @ 0XFD070210 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m + * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un + * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, + * and 15 Internal Base: 11 The selected HIF address bit is determined by + * adding the internal base to the value of this field. If set to 15, this + * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio + * n, column address bit 10 is reserved for indicating auto-precharge, and + * hence no source address bit can be mapped to column address bit 10. In L + * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus + * and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the + * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) + * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied + * to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + * address bit is determined by adding the internal base to the value of t + * his field. If set to 15, this column address bit is set to 0. Note: Per + * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i + * ndicating auto-precharge, and hence no source address bit can be mapped + * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + * auto-precharge in the CA bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf + + * Address Map Register 4 + * (OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP4_OFFSET, 0x00000F0FU, 0x00000F0FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP5 @ 0XFD070214 + + * Selects the HIF address bit used as row address bit 11. Valid Range: 0 t + * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 11 is set to 0. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x7 + + * Selects the HIF address bits used as row address bits 2 to 10. Valid Ran + * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row + * address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro + * w address bit 10) The selected HIF address bit for each of the row addre + * ss bits is determined by adding the internal base to the value of this f + * ield. When value 15 is used the values of row address bits 2 to 10 are d + * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf + + * Selects the HIF address bits used as row address bit 1. Valid Range: 0 t + * o 11 Internal Base: 7 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x7 + + * Selects the HIF address bits used as row address bit 0. Valid Range: 0 t + * o 11 Internal Base: 6 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x7 + + * Address Map Register 5 + * (OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x070F0707U) + */ + PSU_Mask_Write(DDRC_ADDRMAP5_OFFSET, 0x0F0F0F0FU, 0x070F0707U); +/*##################################################################### */ + + /* + * Register : ADDRMAP6 @ 0XFD070218 + + * Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 + * - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]= + * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. + * All addresses are valid Present only in designs configured to support L + * PDDR3. + * PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0 + + * Selects the HIF address bit used as row address bit 15. Valid Range: 0 t + * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 15 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0x7 + + * Selects the HIF address bit used as row address bit 14. Valid Range: 0 t + * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 14 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x7 + + * Selects the HIF address bit used as row address bit 13. Valid Range: 0 t + * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 13 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x7 + + * Selects the HIF address bit used as row address bit 12. Valid Range: 0 t + * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 12 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x7 + + * Address Map Register 6 + * (OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x07070707U) + */ + PSU_Mask_Write(DDRC_ADDRMAP6_OFFSET, 0x8F0F0F0FU, 0x07070707U); +/*##################################################################### */ + + /* + * Register : ADDRMAP7 @ 0XFD07021C + + * Selects the HIF address bit used as row address bit 17. Valid Range: 0 t + * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 17 is set to 0. + * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf + + * Selects the HIF address bit used as row address bit 16. Valid Range: 0 t + * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 16 is set to 0. + * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf + + * Address Map Register 7 + * (OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP7_OFFSET, 0x00000F0FU, 0x00000F0FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP8 @ 0XFD070220 + + * Selects the HIF address bits used as bank group address bit 1. Valid Ran + * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea + * ch of the bank group address bits is determined by adding the internal b + * ase to the value of this field. If set to 31, bank group address bit 1 i + * s set to 0. + * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x1f + + * Selects the HIF address bits used as bank group address bit 0. Valid Ran + * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th + * e bank group address bits is determined by adding the internal base to t + * he value of this field. + * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x1 + + * Address Map Register 8 + * (OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00001F01U) + */ + PSU_Mask_Write(DDRC_ADDRMAP8_OFFSET, 0x00001F1FU, 0x00001F01U); +/*##################################################################### */ + + /* + * Register : ADDRMAP9 @ 0XFD070224 + + * Selects the HIF address bits used as row address bit 5. Valid Range: 0 t + * o 11 Internal Base: 11 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x7 + + * Selects the HIF address bits used as row address bit 4. Valid Range: 0 t + * o 11 Internal Base: 10 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x7 + + * Selects the HIF address bits used as row address bit 3. Valid Range: 0 t + * o 11 Internal Base: 9 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x7 + + * Selects the HIF address bits used as row address bit 2. Valid Range: 0 t + * o 11 Internal Base: 8 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x7 + + * Address Map Register 9 + * (OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x07070707U) + */ + PSU_Mask_Write(DDRC_ADDRMAP9_OFFSET, 0x0F0F0F0FU, 0x07070707U); +/*##################################################################### */ + + /* + * Register : ADDRMAP10 @ 0XFD070228 + + * Selects the HIF address bits used as row address bit 9. Valid Range: 0 t + * o 11 Internal Base: 15 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x7 + + * Selects the HIF address bits used as row address bit 8. Valid Range: 0 t + * o 11 Internal Base: 14 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x7 + + * Selects the HIF address bits used as row address bit 7. Valid Range: 0 t + * o 11 Internal Base: 13 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x7 + + * Selects the HIF address bits used as row address bit 6. Valid Range: 0 t + * o 11 Internal Base: 12 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x7 + + * Address Map Register 10 + * (OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x07070707U) + */ + PSU_Mask_Write(DDRC_ADDRMAP10_OFFSET, 0x0F0F0F0FU, 0x07070707U); +/*##################################################################### */ + + /* + * Register : ADDRMAP11 @ 0XFD07022C + + * Selects the HIF address bits used as row address bit 10. Valid Range: 0 + * to 11 Internal Base: 16 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of + * this field. This register field is used only when ADDRMAP5.addrmap_row_b + * 2_10 is set to value 15. + * PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x7 + + * Address Map Register 11 + * (OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000007U) + */ + PSU_Mask_Write(DDRC_ADDRMAP11_OFFSET, 0x0000000FU, 0x00000007U); +/*##################################################################### */ + + /* + * Register : ODTCFG @ 0XFD070240 + + * Cycles to hold ODT for a write command. The minimum supported value is 2 + * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800 + * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D + * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR + * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 ( + * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6 + + * The delay, in clock cycles, from issuing a write command to setting ODT + * values associated with that command. ODT setting must remain constant fo + * r the entire time that DQS is driven by the uMCTL2. Recommended values: + * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + + * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo + * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust + * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) + * PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0 + + * Cycles to hold ODT for a read command. The minimum supported value is 2. + * Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - + * BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 + * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p + * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + + * RU(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6 + + * The delay, in clock cycles, from issuing a read command to setting ODT v + * alues associated with that command. ODT setting must remain constant for + * the entire time that DQS is driven by the uMCTL2. Recommended values: D + * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL + * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C + * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat + * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK + * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre + * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su + * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R + * U(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0 + + * ODT Configuration Register + * (OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U) + */ + PSU_Mask_Write(DDRC_ODTCFG_OFFSET, 0x0F1F0F7CU, 0x06000600U); +/*##################################################################### */ + + /* + * Register : ODTMAP @ 0XFD070244 + + * Indicates which remote ODTs must be turned on during a read from rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. Present only in configurations that have 2 or more + * ranks + * PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a write to rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. Present only in configurations that have 2 or more r + * anks + * PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a read from rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. + * PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a write to rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. + * PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1 + + * ODT/Rank Map Register + * (OFFSET, MASK, VALUE) (0XFD070244, 0x00003333U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_ODTMAP_OFFSET, 0x00003333U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : SCHED @ 0XFD070250 + + * When the preferred transaction store is empty for these many clock cycle + * s, switch to the alternate transaction store if it is non-empty. The rea + * d transaction store (both high and low priority) is the default preferre + * d transaction store and the write transaction store is the alternative s + * tore. When prefer write over read is set this is reversed. 0x0 is a lega + * l value for this register. When set to 0x0, the transaction store switch + * ing will happen immediately when the switching conditions become true. F + * OR PERFORMANCE ONLY + * PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1 + + * UNUSED + * PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0 + + * Number of entries in the low priority transaction store is this value + + * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent + * ries available for the high priority transaction store. Setting this to + * maximum value allocates all entries to low priority transaction store. S + * etting this to 0 allocates 1 entry to low priority transaction store and + * the rest to high priority transaction store. Note: In ECC configuration + * s, the numbers of write and low priority read credits issued is one less + * than in the non-ECC case. One entry each is reserved in the write and l + * ow-priority read CAMs for storing the RMW requests arising out of single + * bit error correction RMW operation. + * PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20 + + * If true, bank is kept open only while there are page hit transactions av + * ailable in the CAM to that bank. The last read or write command in the C + * AM with a bank and page hit will be executed with auto-precharge if SCHE + * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos + * e_timer is set to 0, explicit precharge (and not auto-precharge) may be + * issued in some cases where there is a mode switch between Write and Read + * or between LPR and HPR. The Read and Write commands that are executed a + * s part of the ECC scrub requests are also executed without auto-precharg + * e. If false, the bank remains open until there is a need to close it (to + * open a different page, or for page timeout or refresh timeout) - also k + * nown as open page policy. The open page policy can be overridden by sett + * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + * The pageclose feature provids a midway between Open and Close page polic + * ies. FOR PERFORMANCE ONLY. + * PSU_DDRC_SCHED_PAGECLOSE 0x0 + + * If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. + * PSU_DDRC_SCHED_PREFER_WRITE 0x0 + + * Active low signal. When asserted ('0'), all incoming transactions are fo + * rced to low priority. This implies that all High Priority Read (HPR) and + * Variable Priority Read commands (VPR) will be treated as Low Priority R + * ead (LPR) commands. On the write side, all Variable Priority Write (VPW) + * commands will be treated as Normal Priority Write (NPW) commands. Forci + * ng the incoming transactions to low priority implicitly turns off Bypass + * path for read commands. FOR PERFORMANCE ONLY. + * PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1 + + * Scheduler Control Register + * (OFFSET, MASK, VALUE) (0XFD070250, 0x7FFF3F07U ,0x01002001U) + */ + PSU_Mask_Write(DDRC_SCHED_OFFSET, 0x7FFF3F07U, 0x01002001U); +/*##################################################################### */ + + /* + * Register : PERFLPR1 @ 0XFD070264 + + * Number of transactions that are serviced once the LPR queue goes critica + * l is the smaller of: - (a) This number - (b) Number of transactions avai + * lable. Unit: Transaction. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8 + + * Number of clocks that the LPR queue can be starved before it goes critic + * al. The minimum valid functional value for this register is 0x1. Program + * ming it to 0x0 will disable the starvation functionality; during normal + * operation, this function should not be disabled as it will cause excessi + * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40 + + * Low Priority Read CAM Register 1 + * (OFFSET, MASK, VALUE) (0XFD070264, 0xFF00FFFFU ,0x08000040U) + */ + PSU_Mask_Write(DDRC_PERFLPR1_OFFSET, 0xFF00FFFFU, 0x08000040U); +/*##################################################################### */ + + /* + * Register : PERFWR1 @ 0XFD07026C + + * Number of transactions that are serviced once the WR queue goes critical + * is the smaller of: - (a) This number - (b) Number of transactions avail + * able. Unit: Transaction. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8 + + * Number of clocks that the WR queue can be starved before it goes critica + * l. The minimum valid functional value for this register is 0x1. Programm + * ing it to 0x0 will disable the starvation functionality; during normal o + * peration, this function should not be disabled as it will cause excessiv + * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40 + + * Write CAM Register 1 + * (OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U) + */ + PSU_Mask_Write(DDRC_PERFWR1_OFFSET, 0xFF00FFFFU, 0x08000040U); +/*##################################################################### */ + + /* + * Register : DQMAP0 @ 0XFD070280 + + * DQ nibble map for DQ bits [12-15] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15 0x0 + + * DQ nibble map for DQ bits [8-11] Present only in designs configured to s + * upport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11 0x0 + + * DQ nibble map for DQ bits [4-7] Present only in designs configured to su + * pport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7 0x0 + + * DQ nibble map for DQ bits [0-3] Present only in designs configured to su + * pport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3 0x0 + + * DQ Map Register 0 + * (OFFSET, MASK, VALUE) (0XFD070280, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP0_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP1 @ 0XFD070284 + + * DQ nibble map for DQ bits [28-31] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31 0x0 + + * DQ nibble map for DQ bits [24-27] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27 0x0 + + * DQ nibble map for DQ bits [20-23] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23 0x0 + + * DQ nibble map for DQ bits [16-19] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19 0x0 + + * DQ Map Register 1 + * (OFFSET, MASK, VALUE) (0XFD070284, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP1_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP2 @ 0XFD070288 + + * DQ nibble map for DQ bits [44-47] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47 0x0 + + * DQ nibble map for DQ bits [40-43] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43 0x0 + + * DQ nibble map for DQ bits [36-39] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39 0x0 + + * DQ nibble map for DQ bits [32-35] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35 0x0 + + * DQ Map Register 2 + * (OFFSET, MASK, VALUE) (0XFD070288, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP3 @ 0XFD07028C + + * DQ nibble map for DQ bits [60-63] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63 0x0 + + * DQ nibble map for DQ bits [56-59] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59 0x0 + + * DQ nibble map for DQ bits [52-55] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55 0x0 + + * DQ nibble map for DQ bits [48-51] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51 0x0 + + * DQ Map Register 3 + * (OFFSET, MASK, VALUE) (0XFD07028C, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP3_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP4 @ 0XFD070290 + + * DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf + * igured to support DDR4. + * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7 0x0 + + * DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf + * igured to support DDR4. + * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3 0x0 + + * DQ Map Register 4 + * (OFFSET, MASK, VALUE) (0XFD070290, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP4_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP5 @ 0XFD070294 + + * All even ranks have the same DQ mapping controled by DQMAP0-4 register a + * s rank 0. This register provides DQ swap function for all odd ranks to s + * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b + * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba + * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs + * configured to support DDR4. + * PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1 + + * DQ Map Register 5 + * (OFFSET, MASK, VALUE) (0XFD070294, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_DQMAP5_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : DBG0 @ 0XFD070300 + + * When this is set to '0', auto-precharge is disabled for the flushed comm + * and in a collision case. Collision cases are write followed by read to s + * ame address, read followed by write to same address, or write followed b + * y write to same address with DBG0.dis_wc bit = 1 (where same address com + * parisons exclude the two address bits representing critical word). FOR D + * EBUG ONLY. + * PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0 + + * When 1, disable write combine. FOR DEBUG ONLY + * PSU_DDRC_DBG0_DIS_WC 0x0 + + * Debug Register 0 + * (OFFSET, MASK, VALUE) (0XFD070300, 0x00000011U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DBG0_OFFSET, 0x00000011U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DBGCMD @ 0XFD07030C + + * Setting this register bit to 1 allows refresh and ZQCS commands to be tr + * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD. + * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore + * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and + * ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor + * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no + * function, and are ignored by the uMCTL2 logic. This register is static, + * and may only be changed when the DDRC reset signal, core_ddrc_rstn, is + * asserted (0). + * PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct + * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit + * is automatically cleared. This operation must only be performed when DF + * IUPD0.dis_auto_ctrlupd=1. + * PSU_DDRC_DBGCMD_CTRLUPD 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS ( + * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi + * s request is stored in the uMCTL2, the bit is automatically cleared. Thi + * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom + * mended NOT to set this register bit if in Init operating mode. This regi + * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown + * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo + * de. + * PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be + * set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. + * PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be + * set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. + * PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0 + + * Command Debug Register + * (OFFSET, MASK, VALUE) (0XFD07030C, 0x80000033U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DBGCMD_OFFSET, 0x80000033U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SWCTL @ 0XFD070320 + + * Enable quasi-dynamic register programming outside reset. Program registe + * r to 0 to enable quasi-dynamic programming. Set back register to 1 once + * programming is done. + * PSU_DDRC_SWCTL_SW_DONE 0x0 + + * Software register programming control enable + * (OFFSET, MASK, VALUE) (0XFD070320, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SWCTL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCCFG @ 0XFD070400 + + * Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand + * s every AXI burst into multiple HIF commands, using the memory burst len + * gth as a unit. If set to 1, then XPI will use half of the memory burst l + * ength as a unit. This applies to both reads and writes. When MSTR.data_b + * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i + * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d + * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd + * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali + * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT + * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an + * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST + * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs + * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR + * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared + * -AC is enabled + * PSU_DDRC_PCCFG_BL_EXP_MODE 0x0 + + * Page match four limit. If set to 1, limits the number of consecutive sam + * e page DDRC transactions that can be granted by the Port Arbiter to four + * when Page Match feature is enabled. If set to 0, there is no limit impo + * sed on number of consecutive same page DDRC transactions. + * PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0 + + * If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l + * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw + * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_ + * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a + * t DDRC are driven to 1b'0. + * PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1 + + * Port Common Configuration Register + * (OFFSET, MASK, VALUE) (0XFD070400, 0x00000111U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCCFG_OFFSET, 0x00000111U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGR_0 @ 0XFD070404 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070404, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_0_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_0 @ 0XFD070408 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_0_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_0 @ 0XFD070490 + + * Enables port n. + * PSU_DDRC_PCTRL_0_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070490, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_0_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_0 @ 0XFD070494 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070494, 0x0033000FU ,0x0020000BU) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_0_OFFSET, 0x0033000FU, 0x0020000BU); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_0 @ 0XFD070498 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070498, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_0_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_1 @ 0XFD0704B4 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD0704B4, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_1_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_1 @ 0XFD0704B8 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_1_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_1 @ 0XFD070540 + + * Enables port n. + * PSU_DDRC_PCTRL_1_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070540, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_1_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_1 @ 0XFD070544 + + * This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0 + + * Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070544, 0x03330F0FU ,0x02000B03U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_1_OFFSET, 0x03330F0FU, 0x02000B03U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_1 @ 0XFD070548 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070548, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_1_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_2 @ 0XFD070564 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070564, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_2_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_2 @ 0XFD070568 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_2_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_2 @ 0XFD0705F0 + + * Enables port n. + * PSU_DDRC_PCTRL_2_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD0705F0, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_2_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_2 @ 0XFD0705F4 + + * This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0 + + * Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0705F4, 0x03330F0FU ,0x02000B03U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_2_OFFSET, 0x03330F0FU, 0x02000B03U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_2 @ 0XFD0705F8 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0705F8, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_2_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_3 @ 0XFD070614 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070614, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_3_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_3 @ 0XFD070618 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_3_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_3 @ 0XFD0706A0 + + * Enables port n. + * PSU_DDRC_PCTRL_3_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD0706A0, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_3_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_3 @ 0XFD0706A4 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0706A4, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_3_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_3 @ 0XFD0706A8 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0706A8, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_3_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_3 @ 0XFD0706AC + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0706AC, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_3_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_3 @ 0XFD0706B0 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0706B0, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_3_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGR_4 @ 0XFD0706C4 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_4_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_4 @ 0XFD0706C8 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_4_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_4 @ 0XFD070750 + + * Enables port n. + * PSU_DDRC_PCTRL_4_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070750, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_4_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_4 @ 0XFD070754 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070754, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_4_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_4 @ 0XFD070758 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070758, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_4_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_4 @ 0XFD07075C + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD07075C, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_4_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_4 @ 0XFD070760 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070760, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_4_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGR_5 @ 0XFD070774 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070774, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_5_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_5 @ 0XFD070778 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_5_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_5 @ 0XFD070800 + + * Enables port n. + * PSU_DDRC_PCTRL_5_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070800, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_5_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_5 @ 0XFD070804 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070804, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_5_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_5 @ 0XFD070808 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070808, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_5_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_5 @ 0XFD07080C + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD07080C, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_5_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_5 @ 0XFD070810 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070810, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_5_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : SARBASE0 @ 0XFD070F04 + + * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + * PSU_DDRC_SARBASE0_BASE_ADDR 0x0 + + * SAR Base Address Register n + * (OFFSET, MASK, VALUE) (0XFD070F04, 0x000001FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SARBASE0_OFFSET, 0x000001FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SARSIZE0 @ 0XFD070F08 + + * Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. + * PSU_DDRC_SARSIZE0_NBLOCKS 0x0 + + * SAR Size Register n + * (OFFSET, MASK, VALUE) (0XFD070F08, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SARSIZE0_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SARBASE1 @ 0XFD070F0C + + * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + * PSU_DDRC_SARBASE1_BASE_ADDR 0x10 + + * SAR Base Address Register n + * (OFFSET, MASK, VALUE) (0XFD070F0C, 0x000001FFU ,0x00000010U) + */ + PSU_Mask_Write(DDRC_SARBASE1_OFFSET, 0x000001FFU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : SARSIZE1 @ 0XFD070F10 + + * Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. + * PSU_DDRC_SARSIZE1_NBLOCKS 0xf + + * SAR Size Register n + * (OFFSET, MASK, VALUE) (0XFD070F10, 0x000000FFU ,0x0000000FU) + */ + PSU_Mask_Write(DDRC_SARSIZE1_OFFSET, 0x000000FFU, 0x0000000FU); +/*##################################################################### */ + + /* + * Register : DFITMG0_SHADOW @ 0XFD072190 + + * Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. + * PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7 + + * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. + * PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1 + + * Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks + * PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2 + + * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. + * PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1 + + * Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks + * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0 + + * Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. + * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2 + + * DFI Timing Shadow Register 0 + * (OFFSET, MASK, VALUE) (0XFD072190, 0x1FBFBF3FU ,0x07828002U) + */ + PSU_Mask_Write(DDRC_DFITMG0_SHADOW_OFFSET, 0x1FBFBF3FU, 0x07828002U); +/*##################################################################### */ + + /* + * DDR CONTROLLER RESET + */ + /* + * Register : RST_DDR_SS @ 0XFD1A0108 + + * DDR block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0 + + * APM block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_APM_RESET 0X0 + + * DDR sub system block level reset + * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x0000000CU ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x0000000CU, 0x00000000U); +/*##################################################################### */ + + /* + * DDR PHY + */ + /* + * Register : PGCR0 @ 0XFD080010 + + * Address Copy + * PSU_DDR_PHY_PGCR0_ADCP 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_30_27 0x0 + + * PHY FIFO Reset + * PSU_DDR_PHY_PGCR0_PHYFRST 0x1 + + * Oscillator Mode Address/Command Delay Line Select + * PSU_DDR_PHY_PGCR0_OSCACDL 0x3 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_23_19 0x0 + + * Digital Test Output Select + * PSU_DDR_PHY_PGCR0_DTOSEL 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_13 0x0 + + * Oscillator Mode Division + * PSU_DDR_PHY_PGCR0_OSCDIV 0xf + + * Oscillator Enable + * PSU_DDR_PHY_PGCR0_OSCEN 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_7_0 0x0 + + * PHY General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080010, 0xFFFFFFFFU ,0x07001E00U) + */ + PSU_Mask_Write(DDR_PHY_PGCR0_OFFSET, 0xFFFFFFFFU, 0x07001E00U); +/*##################################################################### */ + + /* + * Register : PGCR2 @ 0XFD080018 + + * Clear Training Status Registers + * PSU_DDR_PHY_PGCR2_CLRTSTAT 0x0 + + * Clear Impedance Calibration + * PSU_DDR_PHY_PGCR2_CLRZCAL 0x0 + + * Clear Parity Error + * PSU_DDR_PHY_PGCR2_CLRPERR 0x0 + + * Initialization Complete Pin Configuration + * PSU_DDR_PHY_PGCR2_ICPC 0x0 + + * Data Training PUB Mode Exit Timer + * PSU_DDR_PHY_PGCR2_DTPMXTMR 0xf + + * Initialization Bypass + * PSU_DDR_PHY_PGCR2_INITFSMBYP 0x0 + + * PLL FSM Bypass + * PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0 + + * Refresh Period + * PSU_DDR_PHY_PGCR2_TREFPRD 0x10010 + + * PHY General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10010U) + */ + PSU_Mask_Write(DDR_PHY_PGCR2_OFFSET, 0xFFFFFFFFU, 0x00F10010U); +/*##################################################################### */ + + /* + * Register : PGCR3 @ 0XFD08001C + + * CKN Enable + * PSU_DDR_PHY_PGCR3_CKNEN 0x55 + + * CK Enable + * PSU_DDR_PHY_PGCR3_CKEN 0xaa + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR3_RESERVED_15 0x0 + + * Enable Clock Gating for AC [0] ctl_rd_clk + * PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2 + + * Enable Clock Gating for AC [0] ddr_clk + * PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2 + + * Enable Clock Gating for AC [0] ctl_clk + * PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR3_RESERVED_8 0x0 + + * Controls DDL Bypass Modes + * PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2 + + * IO Loop-Back Select + * PSU_DDR_PHY_PGCR3_IOLB 0x0 + + * AC Receive FIFO Read Mode + * PSU_DDR_PHY_PGCR3_RDMODE 0x0 + + * Read FIFO Reset Disable + * PSU_DDR_PHY_PGCR3_DISRST 0x0 + + * Clock Level when Clock Gating + * PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0 + + * PHY General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U) + */ + PSU_Mask_Write(DDR_PHY_PGCR3_OFFSET, 0xFFFFFFFFU, 0x55AA5480U); +/*##################################################################### */ + + /* + * Register : PGCR5 @ 0XFD080024 + + * Frequency B Ratio Term + * PSU_DDR_PHY_PGCR5_FRQBT 0x1 + + * Frequency A Ratio Term + * PSU_DDR_PHY_PGCR5_FRQAT 0x1 + + * DFI Disconnect Time Period + * PSU_DDR_PHY_PGCR5_DISCNPERIOD 0x0 + + * Receiver bias core side control + * PSU_DDR_PHY_PGCR5_VREF_RBCTRL 0xf + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR5_RESERVED_3 0x0 + + * Internal VREF generator REFSEL ragne select + * PSU_DDR_PHY_PGCR5_DXREFISELRANGE 0x1 + + * DDL Page Read Write select + * PSU_DDR_PHY_PGCR5_DDLPGACT 0x0 + + * DDL Page Read Write select + * PSU_DDR_PHY_PGCR5_DDLPGRW 0x0 + + * PHY General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080024, 0xFFFFFFFFU ,0x010100F4U) + */ + PSU_Mask_Write(DDR_PHY_PGCR5_OFFSET, 0xFFFFFFFFU, 0x010100F4U); +/*##################################################################### */ + + /* + * Register : PTR0 @ 0XFD080040 + + * PLL Power-Down Time + * PSU_DDR_PHY_PTR0_TPLLPD 0x216 + + * PLL Gear Shift Time + * PSU_DDR_PHY_PTR0_TPLLGS 0x856 + + * PHY Reset Time + * PSU_DDR_PHY_PTR0_TPHYRST 0x10 + + * PHY Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x42C21590U) + */ + PSU_Mask_Write(DDR_PHY_PTR0_OFFSET, 0xFFFFFFFFU, 0x42C21590U); +/*##################################################################### */ + + /* + * Register : PTR1 @ 0XFD080044 + + * PLL Lock Time + * PSU_DDR_PHY_PTR1_TPLLLOCK 0xd055 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0 + + * PLL Reset Time + * PSU_DDR_PHY_PTR1_TPLLRST 0x12c0 + + * PHY Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0xD05512C0U) + */ + PSU_Mask_Write(DDR_PHY_PTR1_OFFSET, 0xFFFFFFFFU, 0xD05512C0U); +/*##################################################################### */ + + /* + * Register : PLLCR0 @ 0XFD080068 + + * PLL Bypass + * PSU_DDR_PHY_PLLCR0_PLLBYP 0x0 + + * PLL Reset + * PSU_DDR_PHY_PLLCR0_PLLRST 0x0 + + * PLL Power Down + * PSU_DDR_PHY_PLLCR0_PLLPD 0x0 + + * Reference Stop Mode + * PSU_DDR_PHY_PLLCR0_RSTOPM 0x0 + + * PLL Frequency Select + * PSU_DDR_PHY_PLLCR0_FRQSEL 0x1 + + * Relock Mode + * PSU_DDR_PHY_PLLCR0_RLOCKM 0x0 + + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_PLLCR0_CPPC 0x8 + + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_PLLCR0_CPIC 0x0 + + * Gear Shift + * PSU_DDR_PHY_PLLCR0_GSHIFT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PLLCR0_RESERVED_11_9 0x0 + + * Analog Test Enable + * PSU_DDR_PHY_PLLCR0_ATOEN 0x0 + + * Analog Test Control + * PSU_DDR_PHY_PLLCR0_ATC 0x0 + + * Digital Test Control + * PSU_DDR_PHY_PLLCR0_DTC 0x0 + + * PLL Control Register 0 (Type B PLL Only) + * (OFFSET, MASK, VALUE) (0XFD080068, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_PLLCR0_OFFSET, 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ + + /* + * Register : DSGCR @ 0XFD080090 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0 + + * When RDBI enabled, this bit is used to select RDBI CL calculation, if it + * is 1b1, calculation will use RDBICL, otherwise use default calculation. + * PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0 + + * When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v + * alue. + * PSU_DDR_PHY_DSGCR_RDBICL 0x2 + + * PHY Impedance Update Enable + * PSU_DDR_PHY_DSGCR_PHYZUEN 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_22 0x0 + + * SDRAM Reset Output Enable + * PSU_DDR_PHY_DSGCR_RSTOE 0x1 + + * Single Data Rate Mode + * PSU_DDR_PHY_DSGCR_SDRMODE 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_18 0x0 + + * ATO Analog Test Enable + * PSU_DDR_PHY_DSGCR_ATOAE 0x0 + + * DTO Output Enable + * PSU_DDR_PHY_DSGCR_DTOOE 0x0 + + * DTO I/O Mode + * PSU_DDR_PHY_DSGCR_DTOIOM 0x0 + + * DTO Power Down Receiver + * PSU_DDR_PHY_DSGCR_DTOPDR 0x1 + + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_13 0x0 + + * DTO On-Die Termination + * PSU_DDR_PHY_DSGCR_DTOODT 0x0 + + * PHY Update Acknowledge Delay + * PSU_DDR_PHY_DSGCR_PUAD 0x5 + + * Controller Update Acknowledge Enable + * PSU_DDR_PHY_DSGCR_CUAEN 0x1 + + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_4_3 0x0 + + * Controller Impedance Update Enable + * PSU_DDR_PHY_DSGCR_CTLZUEN 0x0 + + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_1 0x0 + + * PHY Update Request Enable + * PSU_DDR_PHY_DSGCR_PUREN 0x1 + + * DDR System General Configuration Register + * (OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04161U) + */ + PSU_Mask_Write(DDR_PHY_DSGCR_OFFSET, 0xFFFFFFFFU, 0x02A04161U); +/*##################################################################### */ + + /* + * Register : GPR0 @ 0XFD0800C0 + + * General Purpose Register 0 + * PSU_DDR_PHY_GPR0_GPR0 0x0 + + * General Purpose Register 0 + * (OFFSET, MASK, VALUE) (0XFD0800C0, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_GPR0_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : GPR1 @ 0XFD0800C4 + + * General Purpose Register 1 + * PSU_DDR_PHY_GPR1_GPR1 0xe3 + + * General Purpose Register 1 + * (OFFSET, MASK, VALUE) (0XFD0800C4, 0xFFFFFFFFU ,0x000000E3U) + */ + PSU_Mask_Write(DDR_PHY_GPR1_OFFSET, 0xFFFFFFFFU, 0x000000E3U); +/*##################################################################### */ + + /* + * Register : DCR @ 0XFD080100 + + * DDR4 Gear Down Timing. + * PSU_DDR_PHY_DCR_GEARDN 0x0 + + * Un-used Bank Group + * PSU_DDR_PHY_DCR_UBG 0x0 + + * Un-buffered DIMM Address Mirroring + * PSU_DDR_PHY_DCR_UDIMM 0x0 + + * DDR 2T Timing + * PSU_DDR_PHY_DCR_DDR2T 0x0 + + * No Simultaneous Rank Access + * PSU_DDR_PHY_DCR_NOSRA 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DCR_RESERVED_26_18 0x0 + + * Byte Mask + * PSU_DDR_PHY_DCR_BYTEMASK 0x1 + + * DDR Type + * PSU_DDR_PHY_DCR_DDRTYPE 0x0 + + * Multi-Purpose Register (MPR) DQ (DDR3 Only) + * PSU_DDR_PHY_DCR_MPRDQ 0x0 + + * Primary DQ (DDR3 Only) + * PSU_DDR_PHY_DCR_PDQ 0x0 + + * DDR 8-Bank + * PSU_DDR_PHY_DCR_DDR8BNK 0x1 + + * DDR Mode + * PSU_DDR_PHY_DCR_DDRMD 0x4 + + * DRAM Configuration Register + * (OFFSET, MASK, VALUE) (0XFD080100, 0xFFFFFFFFU ,0x0800040CU) + */ + PSU_Mask_Write(DDR_PHY_DCR_OFFSET, 0xFFFFFFFFU, 0x0800040CU); +/*##################################################################### */ + + /* + * Register : DTPR0 @ 0XFD080110 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_31_29 0x0 + + * Activate to activate command delay (different banks) + * PSU_DDR_PHY_DTPR0_TRRD 0x7 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_23 0x0 + + * Activate to precharge command delay + * PSU_DDR_PHY_DTPR0_TRAS 0x24 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_15 0x0 + + * Precharge command period + * PSU_DDR_PHY_DTPR0_TRP 0xf + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0 + + * Internal read to precharge command delay + * PSU_DDR_PHY_DTPR0_TRTP 0x8 + + * DRAM Timing Parameters Register 0 + * (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x07240F08U) + */ + PSU_Mask_Write(DDR_PHY_DTPR0_OFFSET, 0xFFFFFFFFU, 0x07240F08U); +/*##################################################################### */ + + /* + * Register : DTPR1 @ 0XFD080114 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_31 0x0 + + * Minimum delay from when write leveling mode is programmed to the first D + * QS/DQS# rising edge. + * PSU_DDR_PHY_DTPR1_TWLMRD 0x28 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_23 0x0 + + * 4-bank activate period + * PSU_DDR_PHY_DTPR1_TFAW 0x20 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0 + + * Load mode update delay (DDR4 and DDR3 only) + * PSU_DDR_PHY_DTPR1_TMOD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0 + + * Load mode cycle time + * PSU_DDR_PHY_DTPR1_TMRD 0x8 + + * DRAM Timing Parameters Register 1 + * (OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28200008U) + */ + PSU_Mask_Write(DDR_PHY_DTPR1_OFFSET, 0xFFFFFFFFU, 0x28200008U); +/*##################################################################### */ + + /* + * Register : DTPR2 @ 0XFD080118 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_31_29 0x0 + + * Read to Write command delay. Valid values are + * PSU_DDR_PHY_DTPR2_TRTW 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_27_25 0x0 + + * Read to ODT delay (DDR3 only) + * PSU_DDR_PHY_DTPR2_TRTODT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0 + + * CKE minimum pulse width + * PSU_DDR_PHY_DTPR2_TCKE 0xf + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0 + + * Self refresh exit delay + * PSU_DDR_PHY_DTPR2_TXS 0x300 + + * DRAM Timing Parameters Register 2 + * (OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x000F0300U) + */ + PSU_Mask_Write(DDR_PHY_DTPR2_OFFSET, 0xFFFFFFFFU, 0x000F0300U); +/*##################################################################### */ + + /* + * Register : DTPR3 @ 0XFD08011C + + * ODT turn-off delay extension + * PSU_DDR_PHY_DTPR3_TOFDX 0x4 + + * Read to read and write to write command delay + * PSU_DDR_PHY_DTPR3_TCCD 0x0 + + * DLL locking time + * PSU_DDR_PHY_DTPR3_TDLLK 0x300 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR3_RESERVED_15_12 0x0 + + * Maximum DQS output access time from CK/CK# (LPDDR2/3 only) + * PSU_DDR_PHY_DTPR3_TDQSCKMAX 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0 + + * DQS output access time from CK/CK# (LPDDR2/3 only) + * PSU_DDR_PHY_DTPR3_TDQSCK 0x0 + + * DRAM Timing Parameters Register 3 + * (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U) + */ + PSU_Mask_Write(DDR_PHY_DTPR3_OFFSET, 0xFFFFFFFFU, 0x83000800U); +/*##################################################################### */ + + /* + * Register : DTPR4 @ 0XFD080120 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_31_30 0x0 + + * ODT turn-on/turn-off delays (DDR2 only) + * PSU_DDR_PHY_DTPR4_TAOND_TAOFD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_27_26 0x0 + + * Refresh-to-Refresh + * PSU_DDR_PHY_DTPR4_TRFC 0x176 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_15_14 0x0 + + * Write leveling output delay + * PSU_DDR_PHY_DTPR4_TWLO 0x2b + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0 + + * Power down exit delay + * PSU_DDR_PHY_DTPR4_TXP 0x7 + + * DRAM Timing Parameters Register 4 + * (OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01762B07U) + */ + PSU_Mask_Write(DDR_PHY_DTPR4_OFFSET, 0xFFFFFFFFU, 0x01762B07U); +/*##################################################################### */ + + /* + * Register : DTPR5 @ 0XFD080124 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0 + + * Activate to activate command delay (same bank) + * PSU_DDR_PHY_DTPR5_TRC 0x33 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_15 0x0 + + * Activate to read or write delay + * PSU_DDR_PHY_DTPR5_TRCD 0xf + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0 + + * Internal write to read command delay + * PSU_DDR_PHY_DTPR5_TWTR 0x8 + + * DRAM Timing Parameters Register 5 + * (OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00330F08U) + */ + PSU_Mask_Write(DDR_PHY_DTPR5_OFFSET, 0xFFFFFFFFU, 0x00330F08U); +/*##################################################################### */ + + /* + * Register : DTPR6 @ 0XFD080128 + + * PUB Write Latency Enable + * PSU_DDR_PHY_DTPR6_PUBWLEN 0x0 + + * PUB Read Latency Enable + * PSU_DDR_PHY_DTPR6_PUBRLEN 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR6_RESERVED_29_14 0x0 + + * Write Latency + * PSU_DDR_PHY_DTPR6_PUBWL 0xe + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR6_RESERVED_7_6 0x0 + + * Read Latency + * PSU_DDR_PHY_DTPR6_PUBRL 0xf + + * DRAM Timing Parameters Register 6 + * (OFFSET, MASK, VALUE) (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU) + */ + PSU_Mask_Write(DDR_PHY_DTPR6_OFFSET, 0xFFFFFFFFU, 0x00000E0FU); +/*##################################################################### */ + + /* + * Register : RDIMMGCR0 @ 0XFD080140 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_31 0x0 + + * RDMIMM Quad CS Enable + * PSU_DDR_PHY_RDIMMGCR0_QCSEN 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28 0x0 + + * RDIMM Outputs I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24 0x0 + + * ERROUT# Output Enable + * PSU_DDR_PHY_RDIMMGCR0_ERROUTOE 0x0 + + * ERROUT# I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM 0x1 + + * ERROUT# Power Down Receiver + * PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_20 0x0 + + * ERROUT# On-Die Termination + * PSU_DDR_PHY_RDIMMGCR0_ERROUTODT 0x0 + + * Load Reduced DIMM + * PSU_DDR_PHY_RDIMMGCR0_LRDIMM 0x0 + + * PAR_IN I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_PARINIOM 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD 0x0 + + * Rank Mirror Enable. + * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN 0x2 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_3 0x0 + + * Stop on Parity Error + * PSU_DDR_PHY_RDIMMGCR0_SOPERR 0x0 + + * Parity Error No Registering + * PSU_DDR_PHY_RDIMMGCR0_ERRNOREG 0x0 + + * Registered DIMM + * PSU_DDR_PHY_RDIMMGCR0_RDIMM 0x0 + + * RDIMM General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080140, 0xFFFFFFFFU ,0x08400020U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMGCR0_OFFSET, 0xFFFFFFFFU, 0x08400020U); +/*##################################################################### */ + + /* + * Register : RDIMMGCR1 @ 0XFD080144 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29 0x0 + + * Address [17] B-side Inversion Disable + * PSU_DDR_PHY_RDIMMGCR1_A17BID 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_27 0x0 + + * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_23 0x0 + + * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_19 0x0 + + * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14 0x0 + + * Stabilization time + * PSU_DDR_PHY_RDIMMGCR1_TBCSTAB 0xc80 + + * RDIMM General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMGCR1_OFFSET, 0xFFFFFFFFU, 0x00000C80U); +/*##################################################################### */ + + /* + * Register : RDIMMCR0 @ 0XFD080150 + + * DDR4/DDR3 Control Word 7 + * PSU_DDR_PHY_RDIMMCR0_RC7 0x0 + + * DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR0_RC6 0x0 + + * DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC5 0x0 + + * DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control + * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont + * rol Word) + * PSU_DDR_PHY_RDIMMCR0_RC4 0x0 + + * DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo + * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri + * cs Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC3 0x0 + + * DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 + * (Timing Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC2 0x0 + + * DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC1 0x0 + + * DDR4/DDR3 Control Word 0 (Global Features Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC0 0x0 + + * RDIMM Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMCR0_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RDIMMCR1 @ 0XFD080154 + + * Control Word 15 + * PSU_DDR_PHY_RDIMMCR1_RC15 0x0 + + * DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC14 0x0 + + * DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC13 0x0 + + * DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC12 0x0 + + * DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo + * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC11 0x0 + + * DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC10 0x2 + + * DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC9 0x0 + + * DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con + * trol Word 8 (Additional Input Bus Termination Setting Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC8 0x0 + + * RDIMM Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD080154, 0xFFFFFFFFU ,0x00000200U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMCR1_OFFSET, 0xFFFFFFFFU, 0x00000200U); +/*##################################################################### */ + + /* + * Register : MR0 @ 0XFD080180 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR0_RESERVED_31_8 0x6 + + * CA Terminating Rank + * PSU_DDR_PHY_MR0_CATR 0x0 + + * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. + * PSU_DDR_PHY_MR0_RSVD_6_5 0x1 + + * Built-in Self-Test for RZQ + * PSU_DDR_PHY_MR0_RZQI 0x2 + + * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. + * PSU_DDR_PHY_MR0_RSVD_2_0 0x0 + + * LPDDR4 Mode Register 0 + * (OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000630U) + */ + PSU_Mask_Write(DDR_PHY_MR0_OFFSET, 0xFFFFFFFFU, 0x00000630U); +/*##################################################################### */ + + /* + * Register : MR1 @ 0XFD080184 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR1_RESERVED_31_8 0x3 + + * Read Postamble Length + * PSU_DDR_PHY_MR1_RDPST 0x0 + + * Write-recovery for auto-precharge command + * PSU_DDR_PHY_MR1_NWR 0x0 + + * Read Preamble Length + * PSU_DDR_PHY_MR1_RDPRE 0x0 + + * Write Preamble Length + * PSU_DDR_PHY_MR1_WRPRE 0x0 + + * Burst Length + * PSU_DDR_PHY_MR1_BL 0x1 + + * LPDDR4 Mode Register 1 + * (OFFSET, MASK, VALUE) (0XFD080184, 0xFFFFFFFFU ,0x00000301U) + */ + PSU_Mask_Write(DDR_PHY_MR1_OFFSET, 0xFFFFFFFFU, 0x00000301U); +/*##################################################################### */ + + /* + * Register : MR2 @ 0XFD080188 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR2_RESERVED_31_8 0x0 + + * Write Leveling + * PSU_DDR_PHY_MR2_WRL 0x0 + + * Write Latency Set + * PSU_DDR_PHY_MR2_WLS 0x0 + + * Write Latency + * PSU_DDR_PHY_MR2_WL 0x4 + + * Read Latency + * PSU_DDR_PHY_MR2_RL 0x0 + + * LPDDR4 Mode Register 2 + * (OFFSET, MASK, VALUE) (0XFD080188, 0xFFFFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(DDR_PHY_MR2_OFFSET, 0xFFFFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MR3 @ 0XFD08018C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR3_RESERVED_31_8 0x2 + + * DBI-Write Enable + * PSU_DDR_PHY_MR3_DBIWR 0x0 + + * DBI-Read Enable + * PSU_DDR_PHY_MR3_DBIRD 0x0 + + * Pull-down Drive Strength + * PSU_DDR_PHY_MR3_PDDS 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR3_RSVD 0x0 + + * Write Postamble Length + * PSU_DDR_PHY_MR3_WRPST 0x0 + + * Pull-up Calibration Point + * PSU_DDR_PHY_MR3_PUCAL 0x0 + + * LPDDR4 Mode Register 3 + * (OFFSET, MASK, VALUE) (0XFD08018C, 0xFFFFFFFFU ,0x00000200U) + */ + PSU_Mask_Write(DDR_PHY_MR3_OFFSET, 0xFFFFFFFFU, 0x00000200U); +/*##################################################################### */ + + /* + * Register : MR4 @ 0XFD080190 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR4_RESERVED_31_16 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR4_RSVD_15_13 0x0 + + * Write Preamble + * PSU_DDR_PHY_MR4_WRP 0x0 + + * Read Preamble + * PSU_DDR_PHY_MR4_RDP 0x0 + + * Read Preamble Training Mode + * PSU_DDR_PHY_MR4_RPTM 0x0 + + * Self Refresh Abort + * PSU_DDR_PHY_MR4_SRA 0x0 + + * CS to Command Latency Mode + * PSU_DDR_PHY_MR4_CS2CMDL 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR4_RSVD1 0x0 + + * Internal VREF Monitor + * PSU_DDR_PHY_MR4_IVM 0x0 + + * Temperature Controlled Refresh Mode + * PSU_DDR_PHY_MR4_TCRM 0x0 + + * Temperature Controlled Refresh Range + * PSU_DDR_PHY_MR4_TCRR 0x0 + + * Maximum Power Down Mode + * PSU_DDR_PHY_MR4_MPDM 0x0 + + * This is a JEDEC reserved bit and is recommended by JEDEC to be programme + * d to 0x0. + * PSU_DDR_PHY_MR4_RSVD_0 0x0 + + * DDR4 Mode Register 4 + * (OFFSET, MASK, VALUE) (0XFD080190, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR4_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MR5 @ 0XFD080194 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR5_RESERVED_31_16 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR5_RSVD 0x0 + + * Read DBI + * PSU_DDR_PHY_MR5_RDBI 0x0 + + * Write DBI + * PSU_DDR_PHY_MR5_WDBI 0x0 + + * Data Mask + * PSU_DDR_PHY_MR5_DM 0x1 + + * CA Parity Persistent Error + * PSU_DDR_PHY_MR5_CAPPE 0x1 + + * RTT_PARK + * PSU_DDR_PHY_MR5_RTTPARK 0x3 + + * ODT Input Buffer during Power Down mode + * PSU_DDR_PHY_MR5_ODTIBPD 0x0 + + * C/A Parity Error Status + * PSU_DDR_PHY_MR5_CAPES 0x0 + + * CRC Error Clear + * PSU_DDR_PHY_MR5_CRCEC 0x0 + + * C/A Parity Latency Mode + * PSU_DDR_PHY_MR5_CAPM 0x0 + + * DDR4 Mode Register 5 + * (OFFSET, MASK, VALUE) (0XFD080194, 0xFFFFFFFFU ,0x000006C0U) + */ + PSU_Mask_Write(DDR_PHY_MR5_OFFSET, 0xFFFFFFFFU, 0x000006C0U); +/*##################################################################### */ + + /* + * Register : MR6 @ 0XFD080198 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR6_RESERVED_31_16 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR6_RSVD_15_13 0x0 + + * CAS_n to CAS_n command delay for same bank group (tCCD_L) + * PSU_DDR_PHY_MR6_TCCDL 0x2 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR6_RSVD_9_8 0x0 + + * VrefDQ Training Enable + * PSU_DDR_PHY_MR6_VDDQTEN 0x0 + + * VrefDQ Training Range + * PSU_DDR_PHY_MR6_VDQTRG 0x0 + + * VrefDQ Training Values + * PSU_DDR_PHY_MR6_VDQTVAL 0x19 + + * DDR4 Mode Register 6 + * (OFFSET, MASK, VALUE) (0XFD080198, 0xFFFFFFFFU ,0x00000819U) + */ + PSU_Mask_Write(DDR_PHY_MR6_OFFSET, 0xFFFFFFFFU, 0x00000819U); +/*##################################################################### */ + + /* + * Register : MR11 @ 0XFD0801AC + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR11_RESERVED_31_8 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR11_RSVD 0x0 + + * Power Down Control + * PSU_DDR_PHY_MR11_PDCTL 0x0 + + * DQ Bus Receiver On-Die-Termination + * PSU_DDR_PHY_MR11_DQODT 0x0 + + * LPDDR4 Mode Register 11 + * (OFFSET, MASK, VALUE) (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR11_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MR12 @ 0XFD0801B0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR12_RESERVED_31_8 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR12_RSVD 0x0 + + * VREF_CA Range Select. + * PSU_DDR_PHY_MR12_VR_CA 0x1 + + * Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. + * PSU_DDR_PHY_MR12_VREF_CA 0xd + + * LPDDR4 Mode Register 12 + * (OFFSET, MASK, VALUE) (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU) + */ + PSU_Mask_Write(DDR_PHY_MR12_OFFSET, 0xFFFFFFFFU, 0x0000004DU); +/*##################################################################### */ + + /* + * Register : MR13 @ 0XFD0801B4 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR13_RESERVED_31_8 0x0 + + * Frequency Set Point Operation Mode + * PSU_DDR_PHY_MR13_FSPOP 0x0 + + * Frequency Set Point Write Enable + * PSU_DDR_PHY_MR13_FSPWR 0x0 + + * Data Mask Enable + * PSU_DDR_PHY_MR13_DMD 0x0 + + * Refresh Rate Option + * PSU_DDR_PHY_MR13_RRO 0x0 + + * VREF Current Generator + * PSU_DDR_PHY_MR13_VRCG 0x1 + + * VREF Output + * PSU_DDR_PHY_MR13_VRO 0x0 + + * Read Preamble Training Mode + * PSU_DDR_PHY_MR13_RPT 0x0 + + * Command Bus Training + * PSU_DDR_PHY_MR13_CBT 0x0 + + * LPDDR4 Mode Register 13 + * (OFFSET, MASK, VALUE) (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U) + */ + PSU_Mask_Write(DDR_PHY_MR13_OFFSET, 0xFFFFFFFFU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MR14 @ 0XFD0801B8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR14_RESERVED_31_8 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR14_RSVD 0x0 + + * VREFDQ Range Selects. + * PSU_DDR_PHY_MR14_VR_DQ 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR14_VREF_DQ 0xd + + * LPDDR4 Mode Register 14 + * (OFFSET, MASK, VALUE) (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU) + */ + PSU_Mask_Write(DDR_PHY_MR14_OFFSET, 0xFFFFFFFFU, 0x0000004DU); +/*##################################################################### */ + + /* + * Register : MR22 @ 0XFD0801D8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR22_RESERVED_31_8 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR22_RSVD 0x0 + + * CA ODT termination disable. + * PSU_DDR_PHY_MR22_ODTD_CA 0x0 + + * ODT CS override. + * PSU_DDR_PHY_MR22_ODTE_CS 0x0 + + * ODT CK override. + * PSU_DDR_PHY_MR22_ODTE_CK 0x0 + + * Controller ODT value for VOH calibration. + * PSU_DDR_PHY_MR22_CODT 0x0 + + * LPDDR4 Mode Register 22 + * (OFFSET, MASK, VALUE) (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR22_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DTCR0 @ 0XFD080200 + + * Refresh During Training + * PSU_DDR_PHY_DTCR0_RFSHDT 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0 + + * Data Training Debug Rank Select + * PSU_DDR_PHY_DTCR0_DTDRS 0x0 + + * Data Training with Early/Extended Gate + * PSU_DDR_PHY_DTCR0_DTEXG 0x0 + + * Data Training Extended Write DQS + * PSU_DDR_PHY_DTCR0_DTEXD 0x0 + + * Data Training Debug Step + * PSU_DDR_PHY_DTCR0_DTDSTP 0x0 + + * Data Training Debug Enable + * PSU_DDR_PHY_DTCR0_DTDEN 0x0 + + * Data Training Debug Byte Select + * PSU_DDR_PHY_DTCR0_DTDBS 0x0 + + * Data Training read DBI deskewing configuration + * PSU_DDR_PHY_DTCR0_DTRDBITR 0x2 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_13 0x0 + + * Data Training Write Bit Deskew Data Mask + * PSU_DDR_PHY_DTCR0_DTWBDDM 0x1 + + * Refreshes Issued During Entry to Training + * PSU_DDR_PHY_DTCR0_RFSHEN 0x1 + + * Data Training Compare Data + * PSU_DDR_PHY_DTCR0_DTCMPD 0x1 + + * Data Training Using MPR + * PSU_DDR_PHY_DTCR0_DTMPR 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_5_4 0x0 + + * Data Training Repeat Number + * PSU_DDR_PHY_DTCR0_DTRPTN 0x7 + + * Data Training Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U) + */ + PSU_Mask_Write(DDR_PHY_DTCR0_OFFSET, 0xFFFFFFFFU, 0x800091C7U); +/*##################################################################### */ + + /* + * Register : DTCR1 @ 0XFD080204 + + * Rank Enable. + * PSU_DDR_PHY_DTCR1_RANKEN_RSVD 0x0 + + * Rank Enable. + * PSU_DDR_PHY_DTCR1_RANKEN 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_15_14 0x0 + + * Data Training Rank + * PSU_DDR_PHY_DTCR1_DTRANK 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_11 0x0 + + * Read Leveling Gate Sampling Difference + * PSU_DDR_PHY_DTCR1_RDLVLGDIFF 0x2 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_7 0x0 + + * Read Leveling Gate Shift + * PSU_DDR_PHY_DTCR1_RDLVLGS 0x3 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_3 0x0 + + * Read Preamble Training enable + * PSU_DDR_PHY_DTCR1_RDPRMVL_TRN 0x1 + + * Read Leveling Enable + * PSU_DDR_PHY_DTCR1_RDLVLEN 0x1 + + * Basic Gate Training Enable + * PSU_DDR_PHY_DTCR1_BSTEN 0x0 + + * Data Training Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080204, 0xFFFFFFFFU ,0x00010236U) + */ + PSU_Mask_Write(DDR_PHY_DTCR1_OFFSET, 0xFFFFFFFFU, 0x00010236U); +/*##################################################################### */ + + /* + * Register : CATR0 @ 0XFD080240 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0 + + * Minimum time (in terms of number of dram clocks) between two consectuve + * CA calibration command + * PSU_DDR_PHY_CATR0_CACD 0x14 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0 + + * Minimum time (in terms of number of dram clocks) PUB should wait before + * sampling the CA response after Calibration command has been sent to the + * memory + * PSU_DDR_PHY_CATR0_CAADR 0x10 + + * CA_1 Response Byte Lane 1 + * PSU_DDR_PHY_CATR0_CA1BYTE1 0x5 + + * CA_1 Response Byte Lane 0 + * PSU_DDR_PHY_CATR0_CA1BYTE0 0x4 + + * CA Training Register 0 + * (OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) + */ + PSU_Mask_Write(DDR_PHY_CATR0_OFFSET, 0xFFFFFFFFU, 0x00141054U); +/*##################################################################### */ + + /* + * Register : DQSDR0 @ 0XFD080250 + + * Number of delay taps by which the DQS gate LCDL will be updated when DQS + * drift is detected + * PSU_DDR_PHY_DQSDR0_DFTDLY 0x0 + + * Drift Impedance Update + * PSU_DDR_PHY_DQSDR0_DFTZQUP 0x0 + + * Drift DDL Update + * PSU_DDR_PHY_DQSDR0_DFTDDLUP 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DQSDR0_RESERVED_25_22 0x0 + + * Drift Read Spacing + * PSU_DDR_PHY_DQSDR0_DFTRDSPC 0x0 + + * Drift Back-to-Back Reads + * PSU_DDR_PHY_DQSDR0_DFTB2BRD 0x8 + + * Drift Idle Reads + * PSU_DDR_PHY_DQSDR0_DFTIDLRD 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DQSDR0_RESERVED_11_8 0x0 + + * Gate Pulse Enable + * PSU_DDR_PHY_DQSDR0_DFTGPULSE 0x0 + + * DQS Drift Update Mode + * PSU_DDR_PHY_DQSDR0_DFTUPMODE 0x0 + + * DQS Drift Detection Mode + * PSU_DDR_PHY_DQSDR0_DFTDTMODE 0x0 + + * DQS Drift Detection Enable + * PSU_DDR_PHY_DQSDR0_DFTDTEN 0x0 + + * DQS Drift Register 0 + * (OFFSET, MASK, VALUE) (0XFD080250, 0xFFFFFFFFU ,0x00088000U) + */ + PSU_Mask_Write(DDR_PHY_DQSDR0_OFFSET, 0xFFFFFFFFU, 0x00088000U); +/*##################################################################### */ + + /* + * Register : BISTLSR @ 0XFD080414 + + * LFSR seed for pseudo-random BIST patterns + * PSU_DDR_PHY_BISTLSR_SEED 0x12341000 + + * BIST LFSR Seed Register + * (OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U) + */ + PSU_Mask_Write(DDR_PHY_BISTLSR_OFFSET, 0xFFFFFFFFU, 0x12341000U); +/*##################################################################### */ + + /* + * Register : RIOCR5 @ 0XFD0804F4 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RIOCR5_RESERVED_31_16 0x0 + + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD 0x0 + + * SDRAM On-die Termination Output Enable (OE) Mode Selection. + * PSU_DDR_PHY_RIOCR5_ODTOEMODE 0x5 + + * Rank I/O Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U) + */ + PSU_Mask_Write(DDR_PHY_RIOCR5_OFFSET, 0xFFFFFFFFU, 0x00000005U); +/*##################################################################### */ + + /* + * Register : ACIOCR0 @ 0XFD080500 + + * Address/Command Slew Rate (D3F I/O Only) + * PSU_DDR_PHY_ACIOCR0_ACSR 0x0 + + * SDRAM Reset I/O Mode + * PSU_DDR_PHY_ACIOCR0_RSTIOM 0x1 + + * SDRAM Reset Power Down Receiver + * PSU_DDR_PHY_ACIOCR0_RSTPDR 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_27 0x0 + + * SDRAM Reset On-Die Termination + * PSU_DDR_PHY_ACIOCR0_RSTODT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_25_10 0x0 + + * CK Duty Cycle Correction + * PSU_DDR_PHY_ACIOCR0_CKDCC 0x0 + + * AC Power Down Receiver Mode + * PSU_DDR_PHY_ACIOCR0_ACPDRMODE 0x2 + + * AC On-die Termination Mode + * PSU_DDR_PHY_ACIOCR0_ACODTMODE 0x2 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_1 0x0 + + * Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. + * PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL 0x0 + + * AC I/O Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080500, 0xFFFFFFFFU ,0x30000028U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR0_OFFSET, 0xFFFFFFFFU, 0x30000028U); +/*##################################################################### */ + + /* + * Register : ACIOCR2 @ 0XFD080508 + + * Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL + * slice + * PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0 + + * Clock gating for Output Enable D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0 0x0 + + * Clock gating for Power Down Receiver D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0 0x0 + + * Clock gating for Termination Enable D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0 0x0 + + * Clock gating for CK# D slices [1:0] + * PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0 0x2 + + * Clock gating for CK D slices [1:0] + * PSU_DDR_PHY_ACIOCR2_CKCLKGATE0 0x2 + + * Clock gating for AC D slices [23:0] + * PSU_DDR_PHY_ACIOCR2_ACCLKGATE0 0x0 + + * AC I/O Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080508, 0xFFFFFFFFU ,0x0A000000U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR2_OFFSET, 0xFFFFFFFFU, 0x0A000000U); +/*##################################################################### */ + + /* + * Register : ACIOCR3 @ 0XFD08050C + + * SDRAM Parity Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_PAROEMODE 0x0 + + * SDRAM Bank Group Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_BGOEMODE 0x0 + + * SDRAM Bank Address Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_BAOEMODE 0x0 + + * SDRAM A[17] Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_A17OEMODE 0x0 + + * SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_A16OEMODE 0x0 + + * SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) + * PSU_DDR_PHY_ACIOCR3_ACTOEMODE 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR3_RESERVED_15_8 0x0 + + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD 0x0 + + * SDRAM CK Output Enable (OE) Mode Selection. + * PSU_DDR_PHY_ACIOCR3_CKOEMODE 0x9 + + * AC I/O Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08050C, 0xFFFFFFFFU ,0x00000009U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR3_OFFSET, 0xFFFFFFFFU, 0x00000009U); +/*##################################################################### */ + + /* + * Register : ACIOCR4 @ 0XFD080510 + + * Clock gating for AC LB slices and loopback read valid slices + * PSU_DDR_PHY_ACIOCR4_LBCLKGATE 0x0 + + * Clock gating for Output Enable D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1 0x0 + + * Clock gating for Power Down Receiver D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1 0x0 + + * Clock gating for Termination Enable D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1 0x0 + + * Clock gating for CK# D slices [3:2] + * PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1 0x2 + + * Clock gating for CK D slices [3:2] + * PSU_DDR_PHY_ACIOCR4_CKCLKGATE1 0x2 + + * Clock gating for AC D slices [47:24] + * PSU_DDR_PHY_ACIOCR4_ACCLKGATE1 0x0 + + * AC I/O Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080510, 0xFFFFFFFFU ,0x0A000000U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR4_OFFSET, 0xFFFFFFFFU, 0x0A000000U); +/*##################################################################### */ + + /* + * Register : IOVCR0 @ 0XFD080520 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_IOVCR0_RESERVED_31_29 0x0 + + * Address/command lane VREF Pad Enable + * PSU_DDR_PHY_IOVCR0_ACREFPEN 0x0 + + * Address/command lane Internal VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFEEN 0x0 + + * Address/command lane Single-End VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFSEN 0x1 + + * Address/command lane Internal VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFIEN 0x1 + + * External VREF generato REFSEL range select + * PSU_DDR_PHY_IOVCR0_ACREFESELRANGE 0x0 + + * Address/command lane External VREF Select + * PSU_DDR_PHY_IOVCR0_ACREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE 0x1 + + * Address/command lane Single-End VREF Select + * PSU_DDR_PHY_IOVCR0_ACREFSSEL 0x30 + + * Internal VREF generator REFSEL ragne select + * PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1 + + * REFSEL Control for internal AC IOs + * PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x4e + + * IO VREF Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0CEU) + */ + PSU_Mask_Write(DDR_PHY_IOVCR0_OFFSET, 0xFFFFFFFFU, 0x0300B0CEU); +/*##################################################################### */ + + /* + * Register : VTCR0 @ 0XFD080528 + + * Number of ctl_clk required to meet (> 150ns) timing requirements during + * DRAM DQ VREF training + * PSU_DDR_PHY_VTCR0_TVREF 0x7 + + * DRM DQ VREF training Enable + * PSU_DDR_PHY_VTCR0_DVEN 0x1 + + * Per Device Addressability Enable + * PSU_DDR_PHY_VTCR0_PDAEN 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR0_RESERVED_26 0x0 + + * VREF Word Count + * PSU_DDR_PHY_VTCR0_VWCR 0x4 + + * DRAM DQ VREF step size used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVSS 0x0 + + * Maximum VREF limit value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVMAX 0x32 + + * Minimum VREF limit value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVMIN 0x0 + + * Initial DRAM DQ VREF value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVINIT 0x19 + + * VREF Training Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080528, 0xFFFFFFFFU ,0xF9032019U) + */ + PSU_Mask_Write(DDR_PHY_VTCR0_OFFSET, 0xFFFFFFFFU, 0xF9032019U); +/*##################################################################### */ + + /* + * Register : VTCR1 @ 0XFD08052C + + * Host VREF step size used during VREF training. The register value of N i + * ndicates step size of (N+1) + * PSU_DDR_PHY_VTCR1_HVSS 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_27 0x0 + + * Maximum VREF limit value used during DRAM VREF training. + * PSU_DDR_PHY_VTCR1_HVMAX 0x7f + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_19 0x0 + + * Minimum VREF limit value used during DRAM VREF training. + * PSU_DDR_PHY_VTCR1_HVMIN 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_11 0x0 + + * Static Host Vref Rank Value + * PSU_DDR_PHY_VTCR1_SHRNK 0x0 + + * Static Host Vref Rank Enable + * PSU_DDR_PHY_VTCR1_SHREN 0x1 + + * Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir + * ements during Host IO VREF training + * PSU_DDR_PHY_VTCR1_TVREFIO 0x7 + + * Eye LCDL Offset value for VREF training + * PSU_DDR_PHY_VTCR1_EOFF 0x0 + + * Number of LCDL Eye points for which VREF training is repeated + * PSU_DDR_PHY_VTCR1_ENUM 0x0 + + * HOST (IO) internal VREF training Enable + * PSU_DDR_PHY_VTCR1_HVEN 0x1 + + * Host IO Type Control + * PSU_DDR_PHY_VTCR1_HVIO 0x1 + + * VREF Training Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U) + */ + PSU_Mask_Write(DDR_PHY_VTCR1_OFFSET, 0xFFFFFFFFU, 0x07F001E3U); +/*##################################################################### */ + + /* + * Register : ACBDLR1 @ 0XFD080544 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0 + + * Delay select for the BDL on Parity. + * PSU_DDR_PHY_ACBDLR1_PARBD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0 + + * Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn + * ected to WE. + * PSU_DDR_PHY_ACBDLR1_A16BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0 + + * Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi + * s pin is connected to CAS. + * PSU_DDR_PHY_ACBDLR1_A17BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0 + + * Delay select for the BDL on ACTN. + * PSU_DDR_PHY_ACBDLR1_ACTBD 0x0 + + * AC Bit Delay Line Register 1 + * (OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR1_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ACBDLR2 @ 0XFD080548 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0 + + * Delay select for the BDL on BG[1]. + * PSU_DDR_PHY_ACBDLR2_BG1BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0 + + * Delay select for the BDL on BG[0]. + * PSU_DDR_PHY_ACBDLR2_BG0BD 0x0 + + * Reser.ved Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0 + + * Delay select for the BDL on BA[1]. + * PSU_DDR_PHY_ACBDLR2_BA1BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0 + + * Delay select for the BDL on BA[0]. + * PSU_DDR_PHY_ACBDLR2_BA0BD 0x0 + + * AC Bit Delay Line Register 2 + * (OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ACBDLR6 @ 0XFD080558 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0 + + * Delay select for the BDL on Address A[3]. + * PSU_DDR_PHY_ACBDLR6_A03BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0 + + * Delay select for the BDL on Address A[2]. + * PSU_DDR_PHY_ACBDLR6_A02BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0 + + * Delay select for the BDL on Address A[1]. + * PSU_DDR_PHY_ACBDLR6_A01BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0 + + * Delay select for the BDL on Address A[0]. + * PSU_DDR_PHY_ACBDLR6_A00BD 0x0 + + * AC Bit Delay Line Register 6 + * (OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR6_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ACBDLR7 @ 0XFD08055C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0 + + * Delay select for the BDL on Address A[7]. + * PSU_DDR_PHY_ACBDLR7_A07BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0 + + * Delay select for the BDL on Address A[6]. + * PSU_DDR_PHY_ACBDLR7_A06BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_15_14 0x0 + + * Delay select for the BDL on Address A[5]. + * PSU_DDR_PHY_ACBDLR7_A05BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_7_6 0x0 + + * Delay select for the BDL on Address A[4]. + * PSU_DDR_PHY_ACBDLR7_A04BD 0x0 + + * AC Bit Delay Line Register 7 + * (OFFSET, MASK, VALUE) (0XFD08055C, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR7_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ACBDLR8 @ 0XFD080560 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_31_30 0x0 + + * Delay select for the BDL on Address A[11]. + * PSU_DDR_PHY_ACBDLR8_A11BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_23_22 0x0 + + * Delay select for the BDL on Address A[10]. + * PSU_DDR_PHY_ACBDLR8_A10BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_15_14 0x0 + + * Delay select for the BDL on Address A[9]. + * PSU_DDR_PHY_ACBDLR8_A09BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_7_6 0x0 + + * Delay select for the BDL on Address A[8]. + * PSU_DDR_PHY_ACBDLR8_A08BD 0x0 + + * AC Bit Delay Line Register 8 + * (OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR8_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ACBDLR9 @ 0XFD080564 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0 + + * Delay select for the BDL on Address A[15]. + * PSU_DDR_PHY_ACBDLR9_A15BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0 + + * Delay select for the BDL on Address A[14]. + * PSU_DDR_PHY_ACBDLR9_A14BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0 + + * Delay select for the BDL on Address A[13]. + * PSU_DDR_PHY_ACBDLR9_A13BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0 + + * Delay select for the BDL on Address A[12]. + * PSU_DDR_PHY_ACBDLR9_A12BD 0x0 + + * AC Bit Delay Line Register 9 + * (OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR9_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ZQCR @ 0XFD080680 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0 + + * ZQ VREF Range + * PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0 + + * Programmable Wait for Frequency B + * PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11 + + * Programmable Wait for Frequency A + * PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x15 + + * ZQ VREF Pad Enable + * PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0 + + * ZQ Internal VREF Enable + * PSU_DDR_PHY_ZQCR_ZQREFIEN 0x1 + + * Choice of termination mode + * PSU_DDR_PHY_ZQCR_ODT_MODE 0x1 + + * Force ZCAL VT update + * PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE 0x0 + + * IO VT Drift Limit + * PSU_DDR_PHY_ZQCR_IODLMT 0x2 + + * Averaging algorithm enable, if set, enables averaging algorithm + * PSU_DDR_PHY_ZQCR_AVGEN 0x1 + + * Maximum number of averaging rounds to be used by averaging algorithm + * PSU_DDR_PHY_ZQCR_AVGMAX 0x2 + + * ZQ Calibration Type + * PSU_DDR_PHY_ZQCR_ZCALT 0x0 + + * ZQ Power Down + * PSU_DDR_PHY_ZQCR_ZQPD 0x0 + + * ZQ Impedance Control Register + * (OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008AAA58U) + */ + PSU_Mask_Write(DDR_PHY_ZQCR_OFFSET, 0xFFFFFFFFU, 0x008AAA58U); +/*##################################################################### */ + + /* + * Register : ZQ0PR0 @ 0XFD080684 + + * Pull-down drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN 0x0 + + * Pull-up drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN 0x0 + + * Pull-down termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN 0x0 + + * Pull-up termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN 0x0 + + * Calibration segment bypass + * PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0 + + * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB + * PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0 + + * Termination adjustment + * PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST 0x0 + + * Pulldown drive strength adjustment + * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST 0x0 + + * Pullup drive strength adjustment + * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST 0x0 + + * DRAM Impedance Divide Ratio + * PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7 + + * HOST Impedance Divide Ratio + * PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x9 + + * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) + * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd + + * Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) + * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd + + * ZQ n Impedance Control Program Register 0 + * (OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000079DDU) + */ + PSU_Mask_Write(DDR_PHY_ZQ0PR0_OFFSET, 0xFFFFFFFFU, 0x000079DDU); +/*##################################################################### */ + + /* + * Register : ZQ0OR0 @ 0XFD080694 + + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26 0x0 + + * Override value for the pull-up output impedance + * PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD 0x1e1 + + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10 0x0 + + * Override value for the pull-down output impedance + * PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD 0x210 + + * ZQ n Impedance Control Override Data Register 0 + * (OFFSET, MASK, VALUE) (0XFD080694, 0xFFFFFFFFU ,0x01E10210U) + */ + PSU_Mask_Write(DDR_PHY_ZQ0OR0_OFFSET, 0xFFFFFFFFU, 0x01E10210U); +/*##################################################################### */ + + /* + * Register : ZQ0OR1 @ 0XFD080698 + + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26 0x0 + + * Override value for the pull-up termination + * PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD 0x1e1 + + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10 0x0 + + * Override value for the pull-down termination + * PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD 0x0 + + * ZQ n Impedance Control Override Data Register 1 + * (OFFSET, MASK, VALUE) (0XFD080698, 0xFFFFFFFFU ,0x01E10000U) + */ + PSU_Mask_Write(DDR_PHY_ZQ0OR1_OFFSET, 0xFFFFFFFFU, 0x01E10000U); +/*##################################################################### */ + + /* + * Register : ZQ1PR0 @ 0XFD0806A4 + + * Pull-down drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN 0x0 + + * Pull-up drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN 0x0 + + * Pull-down termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN 0x0 + + * Pull-up termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN 0x0 + + * Calibration segment bypass + * PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0 + + * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB + * PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0 + + * Termination adjustment + * PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST 0x0 + + * Pulldown drive strength adjustment + * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST 0x1 + + * Pullup drive strength adjustment + * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST 0x0 + + * DRAM Impedance Divide Ratio + * PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT 0x7 + + * HOST Impedance Divide Ratio + * PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb + + * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) + * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd + + * Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) + * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb + + * ZQ n Impedance Control Program Register 0 + * (OFFSET, MASK, VALUE) (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU) + */ + PSU_Mask_Write(DDR_PHY_ZQ1PR0_OFFSET, 0xFFFFFFFFU, 0x00087BDBU); +/*##################################################################### */ + + /* + * Register : DX0GCR0 @ 0XFD080700 + + * Calibration Bypass + * PSU_DDR_PHY_DX0GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX0GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX0GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX0GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX0GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX0GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX0GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX0GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX0GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX0GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080700, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX0GCR1 @ 0XFD080704 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX0GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX0GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX0GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX0GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX0GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX0GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX0GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX0GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX0GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX0GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080704, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX0GCR3 @ 0XFD08070C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX0GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX0GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX0GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX0GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX0GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX0GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX0GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX0GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX0GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX0GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX0GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX0GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX0GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX0GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX0GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX0GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX0GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX0GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08070C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX0GCR4 @ 0XFD080710 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX0GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX0GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX0GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX0GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX0GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX0GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX0GCR4_DXREFIEN 0xf + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX0GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ + + /* + * Register : DX0GCR5 @ 0XFD080714 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX0GCR6 @ 0XFD080718 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX1GCR0 @ 0XFD080800 + + * Calibration Bypass + * PSU_DDR_PHY_DX1GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX1GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX1GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX1GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX1GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX1GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX1GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX1GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX1GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX1GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080800, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX1GCR1 @ 0XFD080804 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX1GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX1GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX1GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX1GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX1GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX1GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX1GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX1GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX1GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX1GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080804, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX1GCR3 @ 0XFD08080C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX1GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX1GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX1GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX1GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX1GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX1GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX1GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX1GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX1GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX1GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX1GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX1GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX1GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX1GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX1GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX1GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX1GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX1GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08080C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX1GCR4 @ 0XFD080810 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX1GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX1GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX1GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX1GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX1GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX1GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX1GCR4_DXREFIEN 0xf + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX1GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ + + /* + * Register : DX1GCR5 @ 0XFD080814 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX1GCR6 @ 0XFD080818 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX2GCR0 @ 0XFD080900 + + * Calibration Bypass + * PSU_DDR_PHY_DX2GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX2GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX2GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX2GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX2GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX2GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX2GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX2GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX2GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX2GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080900, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX2GCR1 @ 0XFD080904 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX2GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX2GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX2GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX2GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX2GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX2GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX2GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX2GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX2GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX2GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX2GCR3 @ 0XFD08090C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX2GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX2GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX2GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX2GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX2GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX2GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX2GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX2GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX2GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX2GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX2GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX2GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX2GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX2GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX2GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX2GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX2GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX2GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08090C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX2GCR4 @ 0XFD080910 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX2GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX2GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX2GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX2GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX2GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX2GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX2GCR4_DXREFIEN 0x1 + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX2GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080910, 0xFFFFFFFFU ,0x0E00B004U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B004U); +/*##################################################################### */ + + /* + * Register : DX2GCR5 @ 0XFD080914 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX2GCR6 @ 0XFD080918 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX3GCR0 @ 0XFD080A00 + + * Calibration Bypass + * PSU_DDR_PHY_DX3GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX3GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX3GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX3GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX3GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX3GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX3GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX3GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX3GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX3GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080A00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX3GCR1 @ 0XFD080A04 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX3GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX3GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX3GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX3GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX3GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX3GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX3GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX3GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX3GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX3GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX3GCR3 @ 0XFD080A0C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX3GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX3GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX3GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX3GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX3GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX3GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX3GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX3GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX3GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX3GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX3GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX3GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX3GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX3GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX3GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX3GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX3GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX3GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD080A0C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX3GCR4 @ 0XFD080A10 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX3GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX3GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX3GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX3GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX3GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX3GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX3GCR4_DXREFIEN 0x1 + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX3GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080A10, 0xFFFFFFFFU ,0x0E00B004U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B004U); +/*##################################################################### */ + + /* + * Register : DX3GCR5 @ 0XFD080A14 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX3GCR6 @ 0XFD080A18 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX4GCR0 @ 0XFD080B00 + + * Calibration Bypass + * PSU_DDR_PHY_DX4GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX4GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX4GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX4GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX4GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX4GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX4GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX4GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX4GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX4GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080B00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX4GCR1 @ 0XFD080B04 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX4GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX4GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX4GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX4GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX4GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX4GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX4GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX4GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX4GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX4GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX4GCR2 @ 0XFD080B08 + + * Enables the OE mode values for DQ[7:0] + * PSU_DDR_PHY_DX4GCR2_DXOEMODE 0x0 + + * Enables the TE (ODT) mode values for DQ[7:0] + * PSU_DDR_PHY_DX4GCR2_DXTEMODE 0x0 + + * DATX8 n General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080B08, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DX4GCR3 @ 0XFD080B0C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX4GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX4GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX4GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX4GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX4GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX4GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX4GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX4GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX4GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX4GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX4GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX4GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX4GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX4GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX4GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX4GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX4GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX4GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD080B0C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX4GCR4 @ 0XFD080B10 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX4GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX4GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX4GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX4GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX4GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX4GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX4GCR4_DXREFIEN 0x1 + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX4GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080B10, 0xFFFFFFFFU ,0x0E00B004U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B004U); +/*##################################################################### */ + + /* + * Register : DX4GCR5 @ 0XFD080B14 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX4GCR6 @ 0XFD080B18 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX5GCR0 @ 0XFD080C00 + + * Calibration Bypass + * PSU_DDR_PHY_DX5GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX5GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX5GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX5GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX5GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX5GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX5GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX5GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX5GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX5GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080C00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX5GCR1 @ 0XFD080C04 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX5GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX5GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX5GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX5GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX5GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX5GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX5GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX5GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX5GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX5GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX5GCR2 @ 0XFD080C08 + + * Enables the OE mode values for DQ[7:0] + * PSU_DDR_PHY_DX5GCR2_DXOEMODE 0x0 + + * Enables the TE (ODT) mode values for DQ[7:0] + * PSU_DDR_PHY_DX5GCR2_DXTEMODE 0x0 + + * DATX8 n General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080C08, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DX5GCR3 @ 0XFD080C0C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX5GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX5GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX5GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX5GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX5GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX5GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX5GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX5GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX5GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX5GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX5GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX5GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX5GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX5GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX5GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX5GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX5GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX5GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD080C0C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX5GCR4 @ 0XFD080C10 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX5GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX5GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX5GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX5GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX5GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX5GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX5GCR4_DXREFIEN 0xf + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX5GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ + + /* + * Register : DX5GCR5 @ 0XFD080C14 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX5GCR6 @ 0XFD080C18 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX6GCR0 @ 0XFD080D00 + + * Calibration Bypass + * PSU_DDR_PHY_DX6GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX6GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX6GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX6GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX6GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX6GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX6GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX6GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX6GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX6GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080D00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX6GCR1 @ 0XFD080D04 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX6GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX6GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX6GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX6GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX6GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX6GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX6GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX6GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX6GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX6GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX6GCR2 @ 0XFD080D08 + + * Enables the OE mode values for DQ[7:0] + * PSU_DDR_PHY_DX6GCR2_DXOEMODE 0x0 + + * Enables the TE (ODT) mode values for DQ[7:0] + * PSU_DDR_PHY_DX6GCR2_DXTEMODE 0x0 + + * DATX8 n General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080D08, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DX6GCR3 @ 0XFD080D0C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX6GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX6GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX6GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX6GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX6GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX6GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX6GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX6GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX6GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX6GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX6GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX6GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX6GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX6GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX6GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX6GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX6GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX6GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD080D0C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX6GCR4 @ 0XFD080D10 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX6GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX6GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX6GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX6GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX6GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX6GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX6GCR4_DXREFIEN 0x1 + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX6GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080D10, 0xFFFFFFFFU ,0x0E00B004U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B004U); +/*##################################################################### */ + + /* + * Register : DX6GCR5 @ 0XFD080D14 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX6GCR6 @ 0XFD080D18 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX7GCR0 @ 0XFD080E00 + + * Calibration Bypass + * PSU_DDR_PHY_DX7GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX7GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX7GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX7GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX7GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX7GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX7GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX7GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX7GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX7GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080E00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX7GCR1 @ 0XFD080E04 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX7GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX7GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX7GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX7GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX7GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX7GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX7GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX7GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX7GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX7GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX7GCR2 @ 0XFD080E08 + + * Enables the OE mode values for DQ[7:0] + * PSU_DDR_PHY_DX7GCR2_DXOEMODE 0x0 + + * Enables the TE (ODT) mode values for DQ[7:0] + * PSU_DDR_PHY_DX7GCR2_DXTEMODE 0x0 + + * DATX8 n General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080E08, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DX7GCR3 @ 0XFD080E0C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX7GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX7GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX7GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX7GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX7GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX7GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX7GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX7GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX7GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX7GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX7GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX7GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX7GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX7GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX7GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX7GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX7GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX7GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD080E0C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX7GCR4 @ 0XFD080E10 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX7GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX7GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX7GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX7GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX7GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX7GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX7GCR4_DXREFIEN 0xf + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX7GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ + + /* + * Register : DX7GCR5 @ 0XFD080E14 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX7GCR6 @ 0XFD080E18 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX8GCR0 @ 0XFD080F00 + + * Calibration Bypass + * PSU_DDR_PHY_DX8GCR0_CALBYP 0x1 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX8GCR0_MDLEN 0x0 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX8GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX8GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSNSEPDR 0x1 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSSEPDR 0x1 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX8GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX8GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX8GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX8GCR0_DQSRPD 0x1 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSGPDR 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX8GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX8GCR0_DQSGOE 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080F00, 0xFFFFFFFFU ,0x80803660U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR0_OFFSET, 0xFFFFFFFFU, 0x80803660U); +/*##################################################################### */ + + /* + * Register : DX8GCR1 @ 0XFD080F04 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX8GCR1_DXPDRMODE 0x5555 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX8GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX8GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX8GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX8GCR1_OEEN 0x0 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX8GCR1_PDREN 0x0 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX8GCR1_TEEN 0x0 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX8GCR1_DSEN 0x0 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX8GCR1_DMEN 0x0 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX8GCR1_DQEN 0x0 + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080F04, 0xFFFFFFFFU ,0x55556000U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR1_OFFSET, 0xFFFFFFFFU, 0x55556000U); +/*##################################################################### */ + + /* + * Register : DX8GCR2 @ 0XFD080F08 + + * Enables the OE mode values for DQ[7:0] + * PSU_DDR_PHY_DX8GCR2_DXOEMODE 0xaaaa + + * Enables the TE (ODT) mode values for DQ[7:0] + * PSU_DDR_PHY_DX8GCR2_DXTEMODE 0xaaaa + + * DATX8 n General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080F08, 0xFFFFFFFFU ,0xAAAAAAAAU) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR2_OFFSET, 0xFFFFFFFFU, 0xAAAAAAAAU); +/*##################################################################### */ + + /* + * Register : DX8GCR3 @ 0XFD080F0C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX8GCR3_RDBVT 0x0 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX8GCR3_WDBVT 0x0 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX8GCR3_RGLVT 0x0 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX8GCR3_RDLVT 0x0 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX8GCR3_WDLVT 0x0 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX8GCR3_WLLVT 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX8GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX8GCR3_DSNOEMODE 0x2 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX8GCR3_DSNTEMODE 0x2 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX8GCR3_DSNPDRMODE 0x1 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX8GCR3_DMOEMODE 0x2 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX8GCR3_DMTEMODE 0x2 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX8GCR3_DMPDRMODE 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX8GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX8GCR3_DSOEMODE 0x2 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX8GCR3_DSTEMODE 0x2 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX8GCR3_DSPDRMODE 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX8GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD080F0C, 0xFFFFFFFFU ,0x0029A4A4U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR3_OFFSET, 0xFFFFFFFFU, 0x0029A4A4U); +/*##################################################################### */ + + /* + * Register : DX8GCR4 @ 0XFD080F10 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX8GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX8GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX8GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX8GCR4_DXREFSEN 0x0 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX8GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX8GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX8GCR4_DXREFIEN 0x0 + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX8GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080F10, 0xFFFFFFFFU ,0x0C00B000U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR4_OFFSET, 0xFFFFFFFFU, 0x0C00B000U); +/*##################################################################### */ + + /* + * Register : DX8GCR5 @ 0XFD080F14 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX8GCR6 @ 0XFD080F18 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX8SL0OSC @ 0XFD081400 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0 + + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2 + + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2 + + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2 + + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0 + + * Loopback Mode + * PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0 + + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0 + + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0 + + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0 + + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1 + + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1 + + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0 + + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3 + + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3 + + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3 + + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf + + * Oscillator Enable + * PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0 + + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ + + /* + * Register : DX8SL0PLLCR0 @ 0XFD081404 + + * PLL Bypass + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLBYP 0x0 + + * PLL Reset + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLRST 0x0 + + * PLL Power Down + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLPD 0x0 + + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL0PLLCR0_RSTOPM 0x0 + + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL0PLLCR0_FRQSEL 0x1 + + * Relock Mode + * PSU_DDR_PHY_DX8SL0PLLCR0_RLOCKM 0x0 + + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL0PLLCR0_CPPC 0x8 + + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL0PLLCR0_CPIC 0x0 + + * Gear Shift + * PSU_DDR_PHY_DX8SL0PLLCR0_GSHIFT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9 0x0 + + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL0PLLCR0_ATOEN 0x0 + + * Analog Test Control + * PSU_DDR_PHY_DX8SL0PLLCR0_ATC 0x0 + + * Digital Test Control + * PSU_DDR_PHY_DX8SL0PLLCR0_DTC 0x0 + + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081404, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ + + /* + * Register : DX8SL0DQSCTL @ 0XFD08141C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25 0x0 + + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22 0x0 + + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE 0x1 + + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX 0x0 + + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD 0x1 + + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15 0x0 + + * QS Counter Enable + * PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN 0x1 + + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10 0x0 + + * Data Slew Rate + * PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3 + + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0 + + * DQS Resistor + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0 + + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ + + /* + * Register : DX8SL0DXCTL2 @ 0XFD08142C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24 0x0 + + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN 0x0 + + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0 + + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0 + + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL0DXCTL2_IOAG 0x0 + + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL0DXCTL2_IOLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13 0x0 + + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH 0xc + + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_RDBI 0x0 + + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_WDBI 0x0 + + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP 0x0 + + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE 0x0 + + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL0DXCTL2_DISRST 0x0 + + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0 + + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ + + /* + * Register : DX8SL0IOCR @ 0XFD081430 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31 0x0 + + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE 0x7 + + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM 0x0 + + * DX IO Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXIOM 0x2 + + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXTXM 0x0 + + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXRXM 0x0 + + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ + + /* + * Register : DX8SL1OSC @ 0XFD081440 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0 + + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2 + + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2 + + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2 + + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0 + + * Loopback Mode + * PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0 + + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0 + + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0 + + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0 + + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1 + + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1 + + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0 + + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3 + + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3 + + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3 + + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf + + * Oscillator Enable + * PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0 + + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ + + /* + * Register : DX8SL1PLLCR0 @ 0XFD081444 + + * PLL Bypass + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLBYP 0x0 + + * PLL Reset + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLRST 0x0 + + * PLL Power Down + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLPD 0x0 + + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL1PLLCR0_RSTOPM 0x0 + + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL1PLLCR0_FRQSEL 0x1 + + * Relock Mode + * PSU_DDR_PHY_DX8SL1PLLCR0_RLOCKM 0x0 + + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL1PLLCR0_CPPC 0x8 + + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL1PLLCR0_CPIC 0x0 + + * Gear Shift + * PSU_DDR_PHY_DX8SL1PLLCR0_GSHIFT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9 0x0 + + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL1PLLCR0_ATOEN 0x0 + + * Analog Test Control + * PSU_DDR_PHY_DX8SL1PLLCR0_ATC 0x0 + + * Digital Test Control + * PSU_DDR_PHY_DX8SL1PLLCR0_DTC 0x0 + + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081444, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ + + /* + * Register : DX8SL1DQSCTL @ 0XFD08145C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25 0x0 + + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22 0x0 + + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE 0x1 + + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX 0x0 + + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD 0x1 + + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15 0x0 + + * QS Counter Enable + * PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN 0x1 + + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10 0x0 + + * Data Slew Rate + * PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3 + + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0 + + * DQS Resistor + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0 + + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ + + /* + * Register : DX8SL1DXCTL2 @ 0XFD08146C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24 0x0 + + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN 0x0 + + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0 + + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0 + + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL1DXCTL2_IOAG 0x0 + + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL1DXCTL2_IOLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13 0x0 + + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH 0xc + + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_RDBI 0x0 + + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_WDBI 0x0 + + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP 0x0 + + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE 0x0 + + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL1DXCTL2_DISRST 0x0 + + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0 + + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ + + /* + * Register : DX8SL1IOCR @ 0XFD081470 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31 0x0 + + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE 0x7 + + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM 0x0 + + * DX IO Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXIOM 0x2 + + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXTXM 0x0 + + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXRXM 0x0 + + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ + + /* + * Register : DX8SL2OSC @ 0XFD081480 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0 + + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2 + + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2 + + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2 + + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0 + + * Loopback Mode + * PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0 + + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0 + + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0 + + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0 + + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1 + + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1 + + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0 + + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3 + + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3 + + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3 + + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf + + * Oscillator Enable + * PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0 + + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ + + /* + * Register : DX8SL2PLLCR0 @ 0XFD081484 + + * PLL Bypass + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLBYP 0x0 + + * PLL Reset + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLRST 0x0 + + * PLL Power Down + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLPD 0x0 + + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL2PLLCR0_RSTOPM 0x0 + + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL2PLLCR0_FRQSEL 0x1 + + * Relock Mode + * PSU_DDR_PHY_DX8SL2PLLCR0_RLOCKM 0x0 + + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL2PLLCR0_CPPC 0x8 + + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL2PLLCR0_CPIC 0x0 + + * Gear Shift + * PSU_DDR_PHY_DX8SL2PLLCR0_GSHIFT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9 0x0 + + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL2PLLCR0_ATOEN 0x0 + + * Analog Test Control + * PSU_DDR_PHY_DX8SL2PLLCR0_ATC 0x0 + + * Digital Test Control + * PSU_DDR_PHY_DX8SL2PLLCR0_DTC 0x0 + + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081484, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ + + /* + * Register : DX8SL2DQSCTL @ 0XFD08149C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0 + + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0 + + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1 + + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX 0x0 + + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD 0x1 + + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15 0x0 + + * QS Counter Enable + * PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN 0x1 + + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10 0x0 + + * Data Slew Rate + * PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3 + + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0 + + * DQS Resistor + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0 + + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ + + /* + * Register : DX8SL2DXCTL2 @ 0XFD0814AC + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24 0x0 + + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN 0x0 + + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0 + + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0 + + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL2DXCTL2_IOAG 0x0 + + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL2DXCTL2_IOLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13 0x0 + + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH 0xc + + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_RDBI 0x0 + + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_WDBI 0x0 + + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP 0x0 + + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE 0x0 + + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL2DXCTL2_DISRST 0x0 + + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0 + + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ + + /* + * Register : DX8SL2IOCR @ 0XFD0814B0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31 0x0 + + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE 0x7 + + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM 0x0 + + * DX IO Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXIOM 0x2 + + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXTXM 0x0 + + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXRXM 0x0 + + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ + + /* + * Register : DX8SL3OSC @ 0XFD0814C0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0 + + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2 + + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2 + + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2 + + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0 + + * Loopback Mode + * PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0 + + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0 + + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0 + + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0 + + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1 + + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1 + + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0 + + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3 + + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3 + + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3 + + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf + + * Oscillator Enable + * PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0 + + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ + + /* + * Register : DX8SL3PLLCR0 @ 0XFD0814C4 + + * PLL Bypass + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLBYP 0x0 + + * PLL Reset + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLRST 0x0 + + * PLL Power Down + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLPD 0x0 + + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL3PLLCR0_RSTOPM 0x0 + + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL3PLLCR0_FRQSEL 0x1 + + * Relock Mode + * PSU_DDR_PHY_DX8SL3PLLCR0_RLOCKM 0x0 + + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL3PLLCR0_CPPC 0x8 + + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL3PLLCR0_CPIC 0x0 + + * Gear Shift + * PSU_DDR_PHY_DX8SL3PLLCR0_GSHIFT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9 0x0 + + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL3PLLCR0_ATOEN 0x0 + + * Analog Test Control + * PSU_DDR_PHY_DX8SL3PLLCR0_ATC 0x0 + + * Digital Test Control + * PSU_DDR_PHY_DX8SL3PLLCR0_DTC 0x0 + + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD0814C4, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ + + /* + * Register : DX8SL3DQSCTL @ 0XFD0814DC + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25 0x0 + + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22 0x0 + + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE 0x1 + + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX 0x0 + + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD 0x1 + + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15 0x0 + + * QS Counter Enable + * PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN 0x1 + + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10 0x0 + + * Data Slew Rate + * PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3 + + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0 + + * DQS Resistor + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0 + + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ + + /* + * Register : DX8SL3DXCTL2 @ 0XFD0814EC + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24 0x0 + + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN 0x0 + + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0 + + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0 + + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL3DXCTL2_IOAG 0x0 + + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL3DXCTL2_IOLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13 0x0 + + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH 0xc + + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_RDBI 0x0 + + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_WDBI 0x0 + + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP 0x0 + + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE 0x0 + + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL3DXCTL2_DISRST 0x0 + + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0 + + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ + + /* + * Register : DX8SL3IOCR @ 0XFD0814F0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31 0x0 + + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE 0x7 + + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM 0x0 + + * DX IO Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXIOM 0x2 + + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXTXM 0x0 + + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXRXM 0x0 + + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ + + /* + * Register : DX8SL4OSC @ 0XFD081500 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0 + + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x1 + + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x1 + + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x1 + + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0 + + * Loopback Mode + * PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0 + + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0 + + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0 + + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0 + + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1 + + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1 + + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0 + + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3 + + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3 + + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3 + + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf + + * Oscillator Enable + * PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0 + + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x15019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4OSC_OFFSET, 0xFFFFFFFFU, 0x15019FFEU); +/*##################################################################### */ + + /* + * Register : DX8SL4PLLCR0 @ 0XFD081504 + + * PLL Bypass + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLBYP 0x0 + + * PLL Reset + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLRST 0x0 + + * PLL Power Down + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLPD 0x1 + + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL4PLLCR0_RSTOPM 0x0 + + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL4PLLCR0_FRQSEL 0x1 + + * Relock Mode + * PSU_DDR_PHY_DX8SL4PLLCR0_RLOCKM 0x0 + + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL4PLLCR0_CPPC 0x8 + + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL4PLLCR0_CPIC 0x0 + + * Gear Shift + * PSU_DDR_PHY_DX8SL4PLLCR0_GSHIFT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9 0x0 + + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL4PLLCR0_ATOEN 0x0 + + * Analog Test Control + * PSU_DDR_PHY_DX8SL4PLLCR0_ATC 0x0 + + * Digital Test Control + * PSU_DDR_PHY_DX8SL4PLLCR0_DTC 0x0 + + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081504, 0xFFFFFFFFU ,0x21100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x21100000U); +/*##################################################################### */ + + /* + * Register : DX8SL4DQSCTL @ 0XFD08151C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25 0x0 + + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22 0x0 + + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE 0x1 + + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX 0x0 + + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD 0x1 + + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15 0x0 + + * QS Counter Enable + * PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN 0x1 + + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10 0x0 + + * Data Slew Rate + * PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3 + + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0 + + * DQS Resistor + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0 + + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01266300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01266300U); +/*##################################################################### */ + + /* + * Register : DX8SL4DXCTL2 @ 0XFD08152C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24 0x0 + + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN 0x0 + + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0 + + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0 + + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL4DXCTL2_IOAG 0x0 + + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL4DXCTL2_IOLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13 0x0 + + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH 0xc + + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_RDBI 0x0 + + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_WDBI 0x0 + + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP 0x0 + + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE 0x0 + + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL4DXCTL2_DISRST 0x0 + + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0 + + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ + + /* + * Register : DX8SL4IOCR @ 0XFD081530 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31 0x0 + + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE 0x7 + + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM 0x0 + + * DX IO Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXIOM 0x1 + + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXTXM 0x0 + + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXRXM 0x0 + + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70400000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4IOCR_OFFSET, 0xFFFFFFFFU, 0x70400000U); +/*##################################################################### */ + + /* + * Register : DX8SLbDQSCTL @ 0XFD0817DC + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25 0x0 + + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22 0x0 + + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE 0x1 + + * DQS Gate Extension + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX 0x0 + + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD 0x1 + + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15 0x0 + + * QS Counter Enable + * PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN 0x1 + + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10 0x0 + + * Data Slew Rate + * PSU_DDR_PHY_DX8SLBDQSCTL_DXSR 0x3 + + * DQS# Resistor + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES 0xc + + * DQS Resistor + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES 0x4 + + * DATX8 0-8 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U) + */ + PSU_Mask_Write(DDR_PHY_DX8SLBDQSCTL_OFFSET, + 0xFFFFFFFFU, 0x012643C4U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_ddr_qos_init_data(void) +{ + /* + * AFI INTERCONNECT QOS CONFIGURATION + */ + /* + * Register : AFIFM_RDQoS @ 0XFD360008 + + * Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM0_AFIFM_RDQOS_VALUE 0 + + * QoS Read Channel Register + * (OFFSET, MASK, VALUE) (0XFD360008, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM0_AFIFM_RDQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRQoS @ 0XFD36001C + + * Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM0_AFIFM_WRQOS_VALUE 0 + + * QoS Write Channel Register + * (OFFSET, MASK, VALUE) (0XFD36001C, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM0_AFIFM_WRQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_RDQoS @ 0XFD370008 + + * Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM1_AFIFM_RDQOS_VALUE 0 + + * QoS Read Channel Register + * (OFFSET, MASK, VALUE) (0XFD370008, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM1_AFIFM_RDQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRQoS @ 0XFD37001C + + * Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM1_AFIFM_WRQOS_VALUE 0 + + * QoS Write Channel Register + * (OFFSET, MASK, VALUE) (0XFD37001C, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM1_AFIFM_WRQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_RDQoS @ 0XFD380008 + + * Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM2_AFIFM_RDQOS_VALUE 0 + + * QoS Read Channel Register + * (OFFSET, MASK, VALUE) (0XFD380008, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM2_AFIFM_RDQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRQoS @ 0XFD38001C + + * Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM2_AFIFM_WRQOS_VALUE 0 + + * QoS Write Channel Register + * (OFFSET, MASK, VALUE) (0XFD38001C, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM2_AFIFM_WRQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_RDQoS @ 0XFD390008 + + * Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM3_AFIFM_RDQOS_VALUE 0 + + * QoS Read Channel Register + * (OFFSET, MASK, VALUE) (0XFD390008, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM3_AFIFM_RDQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRQoS @ 0XFD39001C + + * Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM3_AFIFM_WRQOS_VALUE 0 + + * QoS Write Channel Register + * (OFFSET, MASK, VALUE) (0XFD39001C, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM3_AFIFM_WRQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_RDQoS @ 0XFD3A0008 + + * Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM4_AFIFM_RDQOS_VALUE 0 + + * QoS Read Channel Register + * (OFFSET, MASK, VALUE) (0XFD3A0008, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM4_AFIFM_RDQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRQoS @ 0XFD3A001C + + * Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM4_AFIFM_WRQOS_VALUE 0 + + * QoS Write Channel Register + * (OFFSET, MASK, VALUE) (0XFD3A001C, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM4_AFIFM_WRQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_RDQoS @ 0XFD3B0008 + + * Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM5_AFIFM_RDQOS_VALUE 0 + + * QoS Read Channel Register + * (OFFSET, MASK, VALUE) (0XFD3B0008, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM5_AFIFM_RDQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRQoS @ 0XFD3B001C + + * Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM5_AFIFM_WRQOS_VALUE 0 + + * QoS Write Channel Register + * (OFFSET, MASK, VALUE) (0XFD3B001C, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM5_AFIFM_WRQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_RDQoS @ 0XFF9B0008 + + * Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM6_AFIFM_RDQOS_VALUE 0 + + * QoS Read Channel Register + * (OFFSET, MASK, VALUE) (0XFF9B0008, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM6_AFIFM_RDQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRQoS @ 0XFF9B001C + + * Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM6_AFIFM_WRQOS_VALUE 0 + + * QoS Write Channel Register + * (OFFSET, MASK, VALUE) (0XFF9B001C, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM6_AFIFM_WRQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_mio_init_data(void) +{ + /* + * MIO PROGRAMMING + */ + /* + * Register : MIO_PIN_0 @ 0XFF180000 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- + * (QSPI Clock) + * PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0 + + * Configures MIO Pin 0 peripheral interface mapping. S + * (OFFSET, MASK, VALUE) (0XFF180000, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_0_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_1 @ 0XFF180004 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q + * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou + * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) + * PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0 + + * Configures MIO Pin 1 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180004, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_1_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_2 @ 0XFF180008 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI + * Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I + * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0 + + * Configures MIO Pin 2 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180008, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_2_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_3 @ 0XFF18000C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI + * Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0 + + * Configures MIO Pin 3 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18000C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_3_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_4 @ 0XFF180010 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- ( + * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0 + + * Configures MIO Pin 4 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180010, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_4_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_5 @ 0XFF180014 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- + * (QSPI Slave Select) + * PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0 + + * Configures MIO Pin 5 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180014, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_5_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_6 @ 0XFF180018 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l + * pbk- (QSPI Clock to be fed-back) + * PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s + * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT + * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, + * Output, tracedq[4]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0 + + * Configures MIO Pin 6 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180018, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_6_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_7 @ 0XFF18001C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_ + * upper- (QSPI Slave Select upper) + * PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma + * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua + * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t + * racedq[5]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0 + + * Configures MIO Pin 7 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18001C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_7_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_8 @ 0XFF180020 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste + * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_ + * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra + * ce Port Databus) + * PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0 + + * Configures MIO Pin 8 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180020, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_8_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_9 @ 0XFF180024 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S + * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, + * Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA + * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data + * bus) + * PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0 + + * Configures MIO Pin 9 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180024, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_9_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_10 @ 0XFF180028 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 10]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0 + + * Configures MIO Pin 10 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180028, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_10_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_11 @ 0XFF18002C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 11]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0 + + * Configures MIO Pin 11 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18002C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_11_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_12 @ 0XFF180030 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_ + * upper- (QSPI Upper Clock) + * PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) + * PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 12]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT + * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_ + * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O + * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace + * dq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0 + + * Configures MIO Pin 12 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180030, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_12_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_13 @ 0XFF180034 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, + * test_scan_out[13]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA + * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, + * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR + * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data + * bus) + * PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0 + + * Configures MIO Pin 13 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180034, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_13_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_14 @ 0XFF180038 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND + * Command Latch Enable) + * PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, + * test_scan_out[14]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT + * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, + * Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver + * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2 + + * Configures MIO Pin 14 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180038, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_14_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_15 @ 0XFF18003C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND + * Address Latch Enable) + * PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, + * test_scan_out[15]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT + * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp + * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou + * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria + * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2 + + * Configures MIO Pin 15 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18003C, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_15_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_16 @ 0XFF180040 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, + * test_scan_out[16]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2 + + * Configures MIO Pin 16 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180040, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_16_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_17 @ 0XFF180044 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, + * test_scan_out[17]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2 + + * Configures MIO Pin 17 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180044, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_17_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_18 @ 0XFF180048 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, + * test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6 + + * Configures MIO Pin 18 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180048, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_18_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_19 @ 0XFF18004C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, + * test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6 + + * Configures MIO Pin 19 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18004C, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_19_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_20 @ 0XFF180050 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, + * test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua + * 1_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6 + + * Configures MIO Pin 20 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180050, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_20_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_21 @ 0XFF180054 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes + * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t + * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E + * xt Tamper) + * PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc + * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- ( + * UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6 + + * Configures MIO Pin 21 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180054, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_21_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_22 @ 0XFF180058 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN + * D Write Enable) + * PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = + * test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c + * su_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed + * PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0 + + * Configures MIO Pin 22 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180058, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_22_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_23 @ 0XFF18005C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po + * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp + * ut, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0 + + * Configures MIO Pin 23 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18005C, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_23_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_24 @ 0XFF180060 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test + * Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= + * csu, Input, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N + * ot Used + * PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1 + + * Configures MIO Pin 24 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180060, 0x000000FEU ,0x00000020U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_24_OFFSET, 0x000000FEU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_25 @ 0XFF180064 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN + * D Read Enable) + * PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]- + * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port + * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou + * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in + * put) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1 + + * Configures MIO Pin 25 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180064, 0x000000FEU ,0x00000020U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_25_OFFSET, 0x000000FEU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_26 @ 0XFF180068 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0 + + * Configures MIO Pin 26 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_26_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_27 @ 0XFF18006C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0 + + * Configures MIO Pin 27 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_27_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_28 @ 0XFF180070 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0 + + * Configures MIO Pin 28 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_28_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_29 @ 0XFF180074 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, + * spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0 + + * Configures MIO Pin 29 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_29_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_30 @ 0XFF180078 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0 + * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock + * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, + * tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0 + + * Configures MIO Pin 30 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_30_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_31 @ 0XFF18007C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT + * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp + * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0 + + * Configures MIO Pin 31 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18007C, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_31_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_32 @ 0XFF180080 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) + * PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t + * race, Output, tracedq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0 + + * Configures MIO Pin 32 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180080, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_32_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_33 @ 0XFF180084 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas + * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1 + * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq + * [11]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0 + + * Configures MIO Pin 33 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180084, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_33_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_38 @ 0XFF180098 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA + * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s + * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In + * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- + * (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0 + + * Configures MIO Pin 38 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180098, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_38_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_39 @ 0XFF18009C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b + * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT + * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, + * Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U + * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port + * Control Signal) + * PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0 + + * Configures MIO Pin 39 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_39_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_40 @ 0XFF1800A0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1 + * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[ + * 5]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ + * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3 + * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi + * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0 + + * Configures MIO Pin 40 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_40_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_41 @ 0XFF1800A4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[6]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA + * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu + * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out + * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp + * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0 + + * Configures MIO Pin 41 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_41_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_42 @ 0XFF1800A8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[7]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp + * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0 + + * Configures MIO Pin 42 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_42_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_43 @ 0XFF1800AC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) + * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0 + + * Configures MIO Pin 43 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_43_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_44 @ 0XFF1800B0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4 + * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0 + + * Configures MIO Pin 44 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_44_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_45 @ 0XFF1800B4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0 + + * Configures MIO Pin 45 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_45_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_46 @ 0XFF1800B8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0 + + * Configures MIO Pin 46 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_46_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_47 @ 0XFF1800BC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste + * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt + * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0 + + * Configures MIO Pin 47 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800BC, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_47_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_48 @ 0XFF1800C0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us + * ed + * PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0 + + * Configures MIO Pin 48 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_48_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_49 @ 0XFF1800C4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd + * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0 + + * Configures MIO Pin 49 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_49_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_50 @ 0XFF1800C8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) + * PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind + * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= + * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece + * iver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0 + + * Configures MIO Pin 50 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_50_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_51 @ 0XFF1800CC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) + * PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi + * o1_clk_out- (SDSDIO clock) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat + * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa + * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter + * serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0 + + * Configures MIO Pin 51 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800CC, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_51_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_52 @ 0XFF1800D0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i + * n- (ULPI Clock) + * PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0 + + * Configures MIO Pin 52 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_52_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_53 @ 0XFF1800D4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- + * (Data bus direction control) + * PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou + * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) + * PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0 + + * Configures MIO Pin 53 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_53_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_54 @ 0XFF1800D8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I + * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0 + + * Configures MIO Pin 54 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_54_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_55 @ 0XFF1800DC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- + * (Data flow control signal from the PHY) + * PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0 + + * Configures MIO Pin 55 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_55_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_56 @ 0XFF1800E0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0 + + * Configures MIO Pin 56 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_56_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_57 @ 0XFF1800E4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0 + + * Configures MIO Pin 57 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_57_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_58 @ 0XFF1800E8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- + * (Asserted to end or interrupt transfers) + * PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0 + + * Configures MIO Pin 58 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_58_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_59 @ 0XFF1800EC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0 + + * Configures MIO Pin 59 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_59_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_60 @ 0XFF1800F0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0 + + * Configures MIO Pin 60 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_60_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_61 @ 0XFF1800F4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, + * spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0 + + * Configures MIO Pin 61 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_61_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_62 @ 0XFF1800F8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0 + + * Configures MIO Pin 62 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_62_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_63 @ 0XFF1800FC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0 + + * Configures MIO Pin 63 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_63_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_64 @ 0XFF180100 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i + * n- (ULPI Clock) + * PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4 + * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * trace, Output, tracedq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0 + + * Configures MIO Pin 64 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180100, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_64_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_65 @ 0XFF180104 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- + * (Data bus direction control) + * PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace + * dq[11]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0 + + * Configures MIO Pin 65 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180104, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_65_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_66 @ 0XFF180108 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not + * Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace + * Port Databus) + * PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0 + + * Configures MIO Pin 66 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180108, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_66_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_67 @ 0XFF18010C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- + * (Data flow control signal from the PHY) + * PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N + * ot Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste + * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt + * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace + * Port Databus) + * PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0 + + * Configures MIO Pin 67 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18010C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_67_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_68 @ 0XFF180110 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N + * ot Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0 + + * Configures MIO Pin 68 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180110, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_68_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_69 @ 0XFF180114 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0 + + * Configures MIO Pin 69 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180114, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_69_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_70 @ 0XFF180118 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- + * (Asserted to end or interrupt transfers) + * PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed + * PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0 + + * Configures MIO Pin 70 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180118, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_70_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_71 @ 0XFF18011C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0 + + * Configures MIO Pin 71 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18011C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_71_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_72 @ 0XFF180120 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri + * al output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0 + + * Configures MIO Pin 72 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180120, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_72_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_73 @ 0XFF180124 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not + * Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0 + + * Configures MIO Pin 73 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180124, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_73_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_74 @ 0XFF180128 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[3]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- ( + * UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0 + + * Configures MIO Pin 74 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180128, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_74_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_75 @ 0XFF18012C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1 + * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t + * xd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0 + + * Configures MIO Pin 75 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18012C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_75_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_76 @ 0XFF180130 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO + * clock) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI + * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2 + * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6 + + * Configures MIO Pin 76 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180130, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_76_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_77 @ 0XFF180134 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio + * 1_cd_n- (SD card detect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M + * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, + * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5 + * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou + * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp + * ut, gem3_mdio_out- (MDIO Data) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6 + + * Configures MIO Pin 77 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180134, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_77_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_MST_TRI0 @ 0XFF180204 + + * Master Tri-state Enable for pin 0, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI 0 + + * Master Tri-state Enable for pin 1, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI 0 + + * Master Tri-state Enable for pin 2, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI 0 + + * Master Tri-state Enable for pin 3, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI 0 + + * Master Tri-state Enable for pin 4, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI 0 + + * Master Tri-state Enable for pin 5, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI 0 + + * Master Tri-state Enable for pin 6, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI 0 + + * Master Tri-state Enable for pin 7, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI 0 + + * Master Tri-state Enable for pin 8, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI 0 + + * Master Tri-state Enable for pin 9, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI 0 + + * Master Tri-state Enable for pin 10, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI 0 + + * Master Tri-state Enable for pin 11, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI 0 + + * Master Tri-state Enable for pin 12, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI 0 + + * Master Tri-state Enable for pin 13, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI 0 + + * Master Tri-state Enable for pin 14, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI 0 + + * Master Tri-state Enable for pin 15, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI 0 + + * Master Tri-state Enable for pin 16, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI 0 + + * Master Tri-state Enable for pin 17, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI 0 + + * Master Tri-state Enable for pin 18, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI 1 + + * Master Tri-state Enable for pin 19, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI 0 + + * Master Tri-state Enable for pin 20, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI 0 + + * Master Tri-state Enable for pin 21, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI 1 + + * Master Tri-state Enable for pin 22, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI 0 + + * Master Tri-state Enable for pin 23, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI 0 + + * Master Tri-state Enable for pin 24, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI 0 + + * Master Tri-state Enable for pin 25, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1 + + * Master Tri-state Enable for pin 26, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0 + + * Master Tri-state Enable for pin 27, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0 + + * Master Tri-state Enable for pin 28, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1 + + * Master Tri-state Enable for pin 29, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0 + + * Master Tri-state Enable for pin 30, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1 + + * Master Tri-state Enable for pin 31, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0 + + * MIO pin Tri-state Enables, 31:0 + * (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI0_OFFSET, + 0xFFFFFFFFU, 0x52240000U); +/*##################################################################### */ + + /* + * Register : MIO_MST_TRI1 @ 0XFF180208 + + * Master Tri-state Enable for pin 32, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI 0 + + * Master Tri-state Enable for pin 33, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI 0 + + * Master Tri-state Enable for pin 34, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI 0 + + * Master Tri-state Enable for pin 35, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI 0 + + * Master Tri-state Enable for pin 36, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI 0 + + * Master Tri-state Enable for pin 37, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI 0 + + * Master Tri-state Enable for pin 38, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI 0 + + * Master Tri-state Enable for pin 39, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI 0 + + * Master Tri-state Enable for pin 40, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI 0 + + * Master Tri-state Enable for pin 41, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI 0 + + * Master Tri-state Enable for pin 42, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI 0 + + * Master Tri-state Enable for pin 43, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI 0 + + * Master Tri-state Enable for pin 44, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI 1 + + * Master Tri-state Enable for pin 45, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI 1 + + * Master Tri-state Enable for pin 46, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI 0 + + * Master Tri-state Enable for pin 47, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI 0 + + * Master Tri-state Enable for pin 48, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI 0 + + * Master Tri-state Enable for pin 49, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI 0 + + * Master Tri-state Enable for pin 50, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI 0 + + * Master Tri-state Enable for pin 51, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0 + + * Master Tri-state Enable for pin 52, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 1 + + * Master Tri-state Enable for pin 53, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 1 + + * Master Tri-state Enable for pin 54, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0 + + * Master Tri-state Enable for pin 55, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 1 + + * Master Tri-state Enable for pin 56, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0 + + * Master Tri-state Enable for pin 57, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0 + + * Master Tri-state Enable for pin 58, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0 + + * Master Tri-state Enable for pin 59, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0 + + * Master Tri-state Enable for pin 60, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0 + + * Master Tri-state Enable for pin 61, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0 + + * Master Tri-state Enable for pin 62, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0 + + * Master Tri-state Enable for pin 63, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0 + + * MIO pin Tri-state Enables, 63:32 + * (OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00B03000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI1_OFFSET, + 0xFFFFFFFFU, 0x00B03000U); +/*##################################################################### */ + + /* + * Register : MIO_MST_TRI2 @ 0XFF18020C + + * Master Tri-state Enable for pin 64, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI 0 + + * Master Tri-state Enable for pin 65, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI 0 + + * Master Tri-state Enable for pin 66, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI 0 + + * Master Tri-state Enable for pin 67, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI 0 + + * Master Tri-state Enable for pin 68, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI 0 + + * Master Tri-state Enable for pin 69, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI 0 + + * Master Tri-state Enable for pin 70, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI 1 + + * Master Tri-state Enable for pin 71, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI 1 + + * Master Tri-state Enable for pin 72, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI 1 + + * Master Tri-state Enable for pin 73, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI 1 + + * Master Tri-state Enable for pin 74, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI 1 + + * Master Tri-state Enable for pin 75, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI 1 + + * Master Tri-state Enable for pin 76, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI 0 + + * Master Tri-state Enable for pin 77, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI 0 + + * MIO pin Tri-state Enables, 77:64 + * (OFFSET, MASK, VALUE) (0XFF18020C, 0x00003FFFU ,0x00000FC0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI2_OFFSET, + 0x00003FFFU, 0x00000FC0U); +/*##################################################################### */ + + /* + * Register : bank0_ctrl0 @ 0XFF180138 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25 1 + + * Drive0 control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl1 @ 0XFF18013C + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl3 @ 0XFF180140 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25 1 + + * Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180140, 0x03FFFFFFU ,0x02E7EF1EU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL3_OFFSET, + 0x03FFFFFFU, 0x02E7EF1EU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl4 @ 0XFF180144 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank0_pull_enable is set, this selects pull up or pull down for + * MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl5 @ 0XFF180148 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank0_pullupdown to selects pull up or pull d + * own for MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl6 @ 0XFF18014C + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 + + * Slew rate control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF18014C, 0x03FFFFFFU ,0x01DBFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL6_OFFSET, + 0x03FFFFFFU, 0x01DBFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl0 @ 0XFF180154 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25 1 + + * Drive0 control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl1 @ 0XFF180158 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl3 @ 0XFF18015C + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25 0 + + * Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF18015C, 0x03FFFFFFU ,0x01FDF015U) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL3_OFFSET, + 0x03FFFFFFU, 0x01FDF015U); +/*##################################################################### */ + + /* + * Register : bank1_ctrl4 @ 0XFF180160 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank1_pull_enable is set, this selects pull up or pull down for + * MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl5 @ 0XFF180164 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank1_pullupdown to selects pull up or pull d + * own for MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl6 @ 0XFF180168 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25 1 + + * Slew rate control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180168, 0x03FFFFFFU ,0x03F3FFEBU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL6_OFFSET, + 0x03FFFFFFU, 0x03F3FFEBU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl0 @ 0XFF180170 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25 1 + + * Drive0 control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl1 @ 0XFF180174 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl3 @ 0XFF180178 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25 1 + + * Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180178, 0x03FFFFFFU ,0x02FC0FBFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL3_OFFSET, + 0x03FFFFFFU, 0x02FC0FBFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl4 @ 0XFF18017C + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank2_pull_enable is set, this selects pull up or pull down for + * MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl5 @ 0XFF180180 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank2_pullupdown to selects pull up or pull d + * own for MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl6 @ 0XFF180184 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25 1 + + * Slew rate control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180184, 0x03FFFFFFU ,0x0303FFF4U) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL6_OFFSET, + 0x03FFFFFFU, 0x0303FFF4U); +/*##################################################################### */ + + /* + * LOOPBACK + */ + /* + * Register : MIO_LOOPBACK @ 0XFF180200 + + * I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 + * = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs + * . + * PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0 + + * CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 + * = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. + * PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0 + + * UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. + * 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 + * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD + * and RI not used. + * PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0 + + * SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 + * = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs + * . The other SPI core will appear on the LS Slave Select. + * PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0 + + * Loopback function within MIO + * (OFFSET, MASK, VALUE) (0XFF180200, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_LOOPBACK_OFFSET, + 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_peripherals_pre_init_data(void) +{ + /* + * SYSMON CLOCK PRESET TO IOPLL AT 1500 MHZ FROM PBR TO MAKE AMS CLOCK UNDE + * R RANGE + */ + /* + * Register : AMS_REF_CTRL @ 0XFF5E0108 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 1 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 35 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 2 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_AMS_REF_CTRL_CLKACT 1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01012302U) + */ + PSU_Mask_Write(CRL_APB_AMS_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01012302U); +/*##################################################################### */ + + /* + * PUT QSPI IN RESET STATE + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 1 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_peripherals_init_data(void) +{ + /* + * COHERENCY + */ + /* + * FPD RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0 + + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0 + + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0 + + * FPD WDT reset + * PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET 0 + + * GDMA block level reset + * PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET 0 + + * Pixel Processor (submodule of GPU) block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET 0 + + * Pixel Processor (submodule of GPU) block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET 0 + + * GPU block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_RESET 0 + + * GT block level reset + * PSU_CRF_APB_RST_FPD_TOP_GT_RESET 0 + + * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000F807EU, 0x00000000U); +/*##################################################################### */ + + /* + * RESET BLOCKS + */ + /* + * TIMESTAMP + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_IOU_CC_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_ADMA_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x001A0000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x001A0000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * Reset entire full power domain. + * PSU_CRL_APB_RST_LPD_TOP_FPD_RESET 0 + + * LPD SWDT + * PSU_CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET 0 + + * Sysmonitor reset + * PSU_CRL_APB_RST_LPD_TOP_SYSMON_RESET 0 + + * Real Time Clock reset + * PSU_CRL_APB_RST_LPD_TOP_RTC_RESET 0 + + * APM reset + * PSU_CRL_APB_RST_LPD_TOP_APM_RESET 0 + + * IPI reset + * PSU_CRL_APB_RST_LPD_TOP_IPI_RESET 0 + + * reset entire RPU power island + * PSU_CRL_APB_RST_LPD_TOP_RPU_PGE_RESET 0 + + * reset ocm + * PSU_CRL_APB_RST_LPD_TOP_OCM_RESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x0093C018U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x0093C018U, 0x00000000U); +/*##################################################################### */ + + /* + * ENET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 + + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0 + + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * QSPI + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * QSPI TAP DELAY + */ + /* + * Register : IOU_TAPDLY_BYPASS @ 0XFF180390 + + * 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa + * ss the Tap delay on the Rx clock signal of LQSPI + * PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 0 + + * IOU tap delay bypass for the LQSPI and NAND controllers + * (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET, + 0x00000004U, 0x00000000U); +/*##################################################################### */ + + /* + * NAND + */ + /* + * USB RESET + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000400U, 0x00000000U); +/*##################################################################### */ + + /* + * SD + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000040U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CTRL_REG_SD @ 0XFF180310 + + * SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled + * PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL 0 + + * SD eMMC selection + * (OFFSET, MASK, VALUE) (0XFF180310, 0x00008000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_CTRL_REG_SD_OFFSET, + 0x00008000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SD_CONFIG_REG2 @ 0XFF180320 + + * Should be set based on the final product usage 00 - Removable SCard Slot + * 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0 + + * 8-bit Support for Embedded Device 1: The Core supports 8-bit Interface 0 + * : Supports only 4-bit SD Interface + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_8BIT 1 + + * 1.8V Support 1: 1.8V supported 0: 1.8V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 1 + + * 3.0V Support 1: 3.0V supported 0: 3.0V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0 + + * 3.3V Support 1: 3.3V supported 0: 3.3V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1 + + * SD Config Register 2 + * (OFFSET, MASK, VALUE) (0XFF180320, 0x33840000U ,0x02840000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG2_OFFSET, + 0x33840000U, 0x02840000U); +/*##################################################################### */ + + /* + * SD1 BASE CLOCK + */ + /* + * Register : SD_CONFIG_REG1 @ 0XFF18031C + + * Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. + * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc8 + + * Configures the Number of Taps (Phases) of the rxclk_in that is supported + * . + * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT 0x28 + + * SD Config Register 1 + * (OFFSET, MASK, VALUE) (0XFF18031C, 0x7FFE0000U ,0x64500000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG1_OFFSET, + 0x7FFE0000U, 0x64500000U); +/*##################################################################### */ + + /* + * Register : SD_DLL_CTRL @ 0XFF180358 + + * Reserved. + * PSU_IOU_SLCR_SD_DLL_CTRL_RESERVED 1 + + * SDIO status register + * (OFFSET, MASK, VALUE) (0XFF180358, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_SD_DLL_CTRL_OFFSET, + 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * SD1 RETUNER + */ + /* + * Register : SD_CONFIG_REG3 @ 0XFF180324 + + * This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S + * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other + * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n + * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved + * PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0 + + * SD Config Register 3 + * (OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG3_OFFSET, + 0x03C00000U, 0x00000000U); +/*##################################################################### */ + + /* + * CAN + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000100U, 0x00000000U); +/*##################################################################### */ + + /* + * I2C + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000600U, 0x00000000U); +/*##################################################################### */ + + /* + * SWDT + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00008000U, 0x00000000U); +/*##################################################################### */ + + /* + * SPI + */ + /* + * TTC + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00007800U, 0x00000000U); +/*##################################################################### */ + + /* + * UART + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000006U, 0x00000000U); +/*##################################################################### */ + + /* + * UART BAUD RATE + */ + /* + * Register : Baud_rate_divider_reg0 @ 0XFF000034 + + * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate + * PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV 0x6 + + * Baud Rate Divider Register + * (OFFSET, MASK, VALUE) (0XFF000034, 0x000000FFU ,0x00000006U) + */ + PSU_Mask_Write(UART0_BAUD_RATE_DIVIDER_REG0_OFFSET, + 0x000000FFU, 0x00000006U); +/*##################################################################### */ + + /* + * Register : Baud_rate_gen_reg0 @ 0XFF000018 + + * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + * PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x7c + + * Baud Rate Generator Register. + * (OFFSET, MASK, VALUE) (0XFF000018, 0x0000FFFFU ,0x0000007CU) + */ + PSU_Mask_Write(UART0_BAUD_RATE_GEN_REG0_OFFSET, + 0x0000FFFFU, 0x0000007CU); +/*##################################################################### */ + + /* + * Register : Control_reg0 @ 0XFF000000 + + * Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. + * PSU_UART0_CONTROL_REG0_STPBRK 0x0 + + * Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. + * PSU_UART0_CONTROL_REG0_STTBRK 0x0 + + * Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. + * PSU_UART0_CONTROL_REG0_RSTTO 0x0 + + * Transmit disable: 0: enable transmitter 1: disable transmitter + * PSU_UART0_CONTROL_REG0_TXDIS 0x0 + + * Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. + * PSU_UART0_CONTROL_REG0_TXEN 0x1 + + * Receive disable: 0: enable 1: disable, regardless of the value of RXEN + * PSU_UART0_CONTROL_REG0_RXDIS 0x0 + + * Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. + * PSU_UART0_CONTROL_REG0_RXEN 0x1 + + * Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. + * PSU_UART0_CONTROL_REG0_TXRES 0x1 + + * Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. + * PSU_UART0_CONTROL_REG0_RXRES 0x1 + + * UART Control Register + * (OFFSET, MASK, VALUE) (0XFF000000, 0x000001FFU ,0x00000017U) + */ + PSU_Mask_Write(UART0_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U); +/*##################################################################### */ + + /* + * Register : mode_reg0 @ 0XFF000004 + + * Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback + * PSU_UART0_MODE_REG0_CHMODE 0x0 + + * Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved + * PSU_UART0_MODE_REG0_NBSTOP 0x0 + + * Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty + * PSU_UART0_MODE_REG0_PAR 0x4 + + * Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits + * PSU_UART0_MODE_REG0_CHRL 0x0 + + * Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 + * PSU_UART0_MODE_REG0_CLKS 0x0 + + * UART Mode Register + * (OFFSET, MASK, VALUE) (0XFF000004, 0x000003FFU ,0x00000020U) + */ + PSU_Mask_Write(UART0_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : Baud_rate_divider_reg0 @ 0XFF010034 + + * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate + * PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV 0x6 + + * Baud Rate Divider Register + * (OFFSET, MASK, VALUE) (0XFF010034, 0x000000FFU ,0x00000006U) + */ + PSU_Mask_Write(UART1_BAUD_RATE_DIVIDER_REG0_OFFSET, + 0x000000FFU, 0x00000006U); +/*##################################################################### */ + + /* + * Register : Baud_rate_gen_reg0 @ 0XFF010018 + + * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + * PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x7c + + * Baud Rate Generator Register. + * (OFFSET, MASK, VALUE) (0XFF010018, 0x0000FFFFU ,0x0000007CU) + */ + PSU_Mask_Write(UART1_BAUD_RATE_GEN_REG0_OFFSET, + 0x0000FFFFU, 0x0000007CU); +/*##################################################################### */ + + /* + * Register : Control_reg0 @ 0XFF010000 + + * Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. + * PSU_UART1_CONTROL_REG0_STPBRK 0x0 + + * Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. + * PSU_UART1_CONTROL_REG0_STTBRK 0x0 + + * Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. + * PSU_UART1_CONTROL_REG0_RSTTO 0x0 + + * Transmit disable: 0: enable transmitter 1: disable transmitter + * PSU_UART1_CONTROL_REG0_TXDIS 0x0 + + * Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. + * PSU_UART1_CONTROL_REG0_TXEN 0x1 + + * Receive disable: 0: enable 1: disable, regardless of the value of RXEN + * PSU_UART1_CONTROL_REG0_RXDIS 0x0 + + * Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. + * PSU_UART1_CONTROL_REG0_RXEN 0x1 + + * Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. + * PSU_UART1_CONTROL_REG0_TXRES 0x1 + + * Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. + * PSU_UART1_CONTROL_REG0_RXRES 0x1 + + * UART Control Register + * (OFFSET, MASK, VALUE) (0XFF010000, 0x000001FFU ,0x00000017U) + */ + PSU_Mask_Write(UART1_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U); +/*##################################################################### */ + + /* + * Register : mode_reg0 @ 0XFF010004 + + * Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback + * PSU_UART1_MODE_REG0_CHMODE 0x0 + + * Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved + * PSU_UART1_MODE_REG0_NBSTOP 0x0 + + * Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty + * PSU_UART1_MODE_REG0_PAR 0x4 + + * Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits + * PSU_UART1_MODE_REG0_CHRL 0x0 + + * Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 + * PSU_UART1_MODE_REG0_CLKS 0x0 + + * UART Mode Register + * (OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U) + */ + PSU_Mask_Write(UART1_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U); +/*##################################################################### */ + + /* + * GPIO + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_GPIO_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00040000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00040000U, 0x00000000U); +/*##################################################################### */ + + /* + * ADMA TZ + */ + /* + * Register : slcr_adma @ 0XFF4B0024 + + * TrustZone Classification for ADMA + * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0XFF + + * RPU TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * CSU TAMPERING + */ + /* + * CSU TAMPER STATUS + */ + /* + * Register : tamper_status @ 0XFFCA5000 + + * CSU regsiter + * PSU_CSU_TAMPER_STATUS_TAMPER_0 0 + + * External MIO + * PSU_CSU_TAMPER_STATUS_TAMPER_1 0 + + * JTAG toggle detect + * PSU_CSU_TAMPER_STATUS_TAMPER_2 0 + + * PL SEU error + * PSU_CSU_TAMPER_STATUS_TAMPER_3 0 + + * AMS over temperature alarm for LPD + * PSU_CSU_TAMPER_STATUS_TAMPER_4 0 + + * AMS over temperature alarm for APU + * PSU_CSU_TAMPER_STATUS_TAMPER_5 0 + + * AMS voltage alarm for VCCPINT_FPD + * PSU_CSU_TAMPER_STATUS_TAMPER_6 0 + + * AMS voltage alarm for VCCPINT_LPD + * PSU_CSU_TAMPER_STATUS_TAMPER_7 0 + + * AMS voltage alarm for VCCPAUX + * PSU_CSU_TAMPER_STATUS_TAMPER_8 0 + + * AMS voltage alarm for DDRPHY + * PSU_CSU_TAMPER_STATUS_TAMPER_9 0 + + * AMS voltage alarm for PSIO bank 0/1/2 + * PSU_CSU_TAMPER_STATUS_TAMPER_10 0 + + * AMS voltage alarm for PSIO bank 3 (dedicated pins) + * PSU_CSU_TAMPER_STATUS_TAMPER_11 0 + + * AMS voltaage alarm for GT + * PSU_CSU_TAMPER_STATUS_TAMPER_12 0 + + * Tamper Response Status + * (OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U) + */ + PSU_Mask_Write(CSU_TAMPER_STATUS_OFFSET, 0x00001FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * CSU TAMPER RESPONSE + */ + /* + * CPU QOS DEFAULT + */ + /* + * Register : ACE_CTRL @ 0XFD5C0060 + + * Set ACE outgoing AWQOS value + * PSU_APU_ACE_CTRL_AWQOS 0X0 + + * Set ACE outgoing ARQOS value + * PSU_APU_ACE_CTRL_ARQOS 0X0 + + * ACE Control Register + * (OFFSET, MASK, VALUE) (0XFD5C0060, 0x000F000FU ,0x00000000U) + */ + PSU_Mask_Write(APU_ACE_CTRL_OFFSET, 0x000F000FU, 0x00000000U); +/*##################################################################### */ + + /* + * ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE + */ + /* + * Register : CONTROL @ 0XFFA60040 + + * Enables the RTC. By writing a 0 to this bit, RTC will be powered off and + * the only module that potentially draws current from the battery will be + * BBRAM. The value read through this bit does not necessarily reflect whe + * ther RTC is enabled or not. It is expected that RTC is enabled every tim + * e it is being configured. If RTC is not used in the design, FSBL will di + * sable it by writing a 0 to this bit. + * PSU_RTC_CONTROL_BATTERY_DISABLE 0X1 + + * This register controls various functionalities within the RTC + * (OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U) + */ + PSU_Mask_Write(RTC_CONTROL_OFFSET, 0x80000000U, 0x80000000U); +/*##################################################################### */ + + /* + * TIMESTAMP COUNTER + */ + /* + * Register : base_frequency_ID_register @ 0XFF260020 + + * Frequency in number of ticks per second. Valid range from 10 MHz to 100 + * MHz. + * PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5dd18 + + * Program this register to match the clock frequency of the timestamp gene + * rator, in ticks per second. For example, for a 50 MHz clock, program 0x0 + * 2FAF080. This register is not accessible to the read-only programming in + * terface. + * (OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5DD18U) + */ + PSU_Mask_Write(IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET, + 0xFFFFFFFFU, 0x05F5DD18U); +/*##################################################################### */ + + /* + * Register : counter_control_register @ 0XFF260000 + + * Enable 0: The counter is disabled and not incrementing. 1: The counter i + * s enabled and is incrementing. + * PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1 + + * Controls the counter increments. This register is not accessible to the + * read-only programming interface. + * (OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * TTC SRC SELECT + */ + /* + * USB RESET + */ + /* + * USB RESET WITH BOOT PIN MODE + */ + /* + * BOOT PIN HIGH + */ + /* + * Register : BOOT_PIN_CTRL @ 0XFF5E0250 + + * Value driven onto the mode pins, when out_en = 1 + * PSU_CRL_APB_BOOT_PIN_CTRL_OUT_VAL 0X2 + + * When 0, the pins will be inputs from the board to the PS. When 1, the PS + * will drive these pins + * PSU_CRL_APB_BOOT_PIN_CTRL_OUT_EN 0X2 + + * Used to control the mode pins after boot. + * (OFFSET, MASK, VALUE) (0XFF5E0250, 0x00000F0FU ,0x00000202U) + */ + PSU_Mask_Write(CRL_APB_BOOT_PIN_CTRL_OFFSET, + 0x00000F0FU, 0x00000202U); +/*##################################################################### */ + + /* + * ADD 1US DELAY + */ + mask_delay(1); + +/*##################################################################### */ + + /* + * BOOT PIN LOW + */ + /* + * Register : BOOT_PIN_CTRL @ 0XFF5E0250 + + * Value driven onto the mode pins, when out_en = 1 + * PSU_CRL_APB_BOOT_PIN_CTRL_OUT_VAL 0X0 + + * When 0, the pins will be inputs from the board to the PS. When 1, the PS + * will drive these pins + * PSU_CRL_APB_BOOT_PIN_CTRL_OUT_EN 0X2 + + * Used to control the mode pins after boot. + * (OFFSET, MASK, VALUE) (0XFF5E0250, 0x00000F0FU ,0x00000002U) + */ + PSU_Mask_Write(CRL_APB_BOOT_PIN_CTRL_OFFSET, + 0x00000F0FU, 0x00000002U); +/*##################################################################### */ + + /* + * ADD 5US DELAY + */ + mask_delay(5); + +/*##################################################################### */ + + /* + * BOOT PIN HIGH + */ + /* + * Register : BOOT_PIN_CTRL @ 0XFF5E0250 + + * Value driven onto the mode pins, when out_en = 1 + * PSU_CRL_APB_BOOT_PIN_CTRL_OUT_VAL 0X2 + + * When 0, the pins will be inputs from the board to the PS. When 1, the PS + * will drive these pins + * PSU_CRL_APB_BOOT_PIN_CTRL_OUT_EN 0X2 + + * Used to control the mode pins after boot. + * (OFFSET, MASK, VALUE) (0XFF5E0250, 0x00000F0FU ,0x00000202U) + */ + PSU_Mask_Write(CRL_APB_BOOT_PIN_CTRL_OFFSET, + 0x00000F0FU, 0x00000202U); +/*##################################################################### */ + + /* + * PCIE RESET + */ + /* + * DIR MODE BANK 0 + */ + /* + * DIR MODE BANK 1 + */ + /* + * Register : DIRM_1 @ 0XFF0A0244 + + * Operation is the same as DIRM_0[DIRECTION_0] + * PSU_GPIO_DIRM_1_DIRECTION_1 0x20 + + * Direction mode (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0244, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_DIRM_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * DIR MODE BANK 2 + */ + /* + * OUTPUT ENABLE BANK 0 + */ + /* + * OUTPUT ENABLE BANK 1 + */ + /* + * Register : OEN_1 @ 0XFF0A0248 + + * Operation is the same as OEN_0[OP_ENABLE_0] + * PSU_GPIO_OEN_1_OP_ENABLE_1 0x20 + + * Output enable (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0248, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_OEN_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * OUTPUT ENABLE BANK 2 + */ + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0020U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * ADD 1US DELAY + */ + mask_delay(1); + +/*##################################################################### */ + + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x0 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0000U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0000U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * ADD 5US DELAY + */ + mask_delay(5); + +/*##################################################################### */ + + /* + * GPIO POLARITY INITIALIZATION + */ + /* + * Register : DIRM_1 @ 0XFF0A0244 + + * Operation is the same as DIRM_0[DIRECTION_0] + * PSU_GPIO_DIRM_1_DIRECTION_1 0x20 + + * Direction mode (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0244, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_DIRM_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : OEN_1 @ 0XFF0A0248 + + * Operation is the same as OEN_0[OP_ENABLE_0] + * PSU_GPIO_OEN_1_OP_ENABLE_1 0x20 + + * Output enable (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0248, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_OEN_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x0 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0000U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0000U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_post_config_data(void) +{ + /* + * POST_CONFIG + */ + + return 1; +} +unsigned long psu_peripherals_powerdwn_data(void) +{ + /* + * POWER DOWN REQUEST INTERRUPT ENABLE + */ + /* + * POWER DOWN TRIGGER + */ + + return 1; +} +unsigned long psu_lpd_xppu_data(void) +{ + /* + * MASTER ID LIST + */ + /* + * APERTURE PERMISIION LIST + */ + /* + * APERTURE NAME: UART0, START ADDRESS: FF000000, END ADDRESS: FF00FFFF + */ + /* + * APERTURE NAME: UART1, START ADDRESS: FF010000, END ADDRESS: FF01FFFF + */ + /* + * APERTURE NAME: I2C0, START ADDRESS: FF020000, END ADDRESS: FF02FFFF + */ + /* + * APERTURE NAME: I2C1, START ADDRESS: FF030000, END ADDRESS: FF03FFFF + */ + /* + * APERTURE NAME: SPI0, START ADDRESS: FF040000, END ADDRESS: FF04FFFF + */ + /* + * APERTURE NAME: SPI1, START ADDRESS: FF050000, END ADDRESS: FF05FFFF + */ + /* + * APERTURE NAME: CAN0, START ADDRESS: FF060000, END ADDRESS: FF06FFFF + */ + /* + * APERTURE NAME: CAN1, START ADDRESS: FF070000, END ADDRESS: FF07FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09 + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09 + * FFFF + */ + /* + * APERTURE NAME: GPIO, START ADDRESS: FF0A0000, END ADDRESS: FF0AFFFF + */ + /* + * APERTURE NAME: GEM0, START ADDRESS: FF0B0000, END ADDRESS: FF0BFFFF + */ + /* + * APERTURE NAME: GEM1, START ADDRESS: FF0C0000, END ADDRESS: FF0CFFFF + */ + /* + * APERTURE NAME: GEM2, START ADDRESS: FF0D0000, END ADDRESS: FF0DFFFF + */ + /* + * APERTURE NAME: GEM3, START ADDRESS: FF0E0000, END ADDRESS: FF0EFFFF + */ + /* + * APERTURE NAME: QSPI, START ADDRESS: FF0F0000, END ADDRESS: FF0FFFFF + */ + /* + * APERTURE NAME: NAND, START ADDRESS: FF100000, END ADDRESS: FF10FFFF + */ + /* + * APERTURE NAME: TTC0, START ADDRESS: FF110000, END ADDRESS: FF11FFFF + */ + /* + * APERTURE NAME: TTC1, START ADDRESS: FF120000, END ADDRESS: FF12FFFF + */ + /* + * APERTURE NAME: TTC2, START ADDRESS: FF130000, END ADDRESS: FF13FFFF + */ + /* + * APERTURE NAME: TTC3, START ADDRESS: FF140000, END ADDRESS: FF14FFFF + */ + /* + * APERTURE NAME: SWDT, START ADDRESS: FF150000, END ADDRESS: FF15FFFF + */ + /* + * APERTURE NAME: SD0, START ADDRESS: FF160000, END ADDRESS: FF16FFFF + */ + /* + * APERTURE NAME: SD1, START ADDRESS: FF170000, END ADDRESS: FF17FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SECURE_SLCR, START ADDRESS: FF240000, END ADDRESS: FF + * 24FFFF + */ + /* + * APERTURE NAME: IOU_SCNTR, START ADDRESS: FF250000, END ADDRESS: FF25FFFF + */ + /* + * APERTURE NAME: IOU_SCNTRS, START ADDRESS: FF260000, END ADDRESS: FF26FFF + * F + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_1, START ADDRESS: FF400000, END ADDRESS: FF40F + * FFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: OCM_SLCR, START ADDRESS: FF960000, END ADDRESS: FF96FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_4, START ADDRESS: FF970000, END ADDRESS: FF97F + * FFF + */ + /* + * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + */ + /* + * APERTURE NAME: RPU, START ADDRESS: FF9A0000, END ADDRESS: FF9AFFFF + */ + /* + * APERTURE NAME: AFIFM6, START ADDRESS: FF9B0000, END ADDRESS: FF9BFFFF + */ + /* + * APERTURE NAME: LPD_XPPU_SINK, START ADDRESS: FF9C0000, END ADDRESS: FF9C + * FFFF + */ + /* + * APERTURE NAME: USB3_0, START ADDRESS: FF9D0000, END ADDRESS: FF9DFFFF + */ + /* + * APERTURE NAME: USB3_1, START ADDRESS: FF9E0000, END ADDRESS: FF9EFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_5, START ADDRESS: FF9F0000, END ADDRESS: FF9FF + * FFF + */ + /* + * APERTURE NAME: APM0, START ADDRESS: FFA00000, END ADDRESS: FFA0FFFF + */ + /* + * APERTURE NAME: APM1, START ADDRESS: FFA10000, END ADDRESS: FFA1FFFF + */ + /* + * APERTURE NAME: APM_INTC_IOU, START ADDRESS: FFA20000, END ADDRESS: FFA2F + * FFF + */ + /* + * APERTURE NAME: APM_FPD_LPD, START ADDRESS: FFA30000, END ADDRESS: FFA3FF + * FF + */ + /* + * APERTURE NAME: LPD_UNUSED_6, START ADDRESS: FFA40000, END ADDRESS: FFA4F + * FFF + */ + /* + * APERTURE NAME: AMS, START ADDRESS: FFA50000, END ADDRESS: FFA5FFFF + */ + /* + * APERTURE NAME: RTC, START ADDRESS: FFA60000, END ADDRESS: FFA6FFFF + */ + /* + * APERTURE NAME: OCM_XMPU_CFG, START ADDRESS: FFA70000, END ADDRESS: FFA7F + * FFF + */ + /* + * APERTURE NAME: ADMA_0, START ADDRESS: FFA80000, END ADDRESS: FFA8FFFF + */ + /* + * APERTURE NAME: ADMA_1, START ADDRESS: FFA90000, END ADDRESS: FFA9FFFF + */ + /* + * APERTURE NAME: ADMA_2, START ADDRESS: FFAA0000, END ADDRESS: FFAAFFFF + */ + /* + * APERTURE NAME: ADMA_3, START ADDRESS: FFAB0000, END ADDRESS: FFABFFFF + */ + /* + * APERTURE NAME: ADMA_4, START ADDRESS: FFAC0000, END ADDRESS: FFACFFFF + */ + /* + * APERTURE NAME: ADMA_5, START ADDRESS: FFAD0000, END ADDRESS: FFADFFFF + */ + /* + * APERTURE NAME: ADMA_6, START ADDRESS: FFAE0000, END ADDRESS: FFAEFFFF + */ + /* + * APERTURE NAME: ADMA_7, START ADDRESS: FFAF0000, END ADDRESS: FFAFFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + */ + /* + * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + */ + /* + * APERTURE NAME: CSU_LOCAL, START ADDRESS: FFC20000, END ADDRESS: FFC2FFFF + */ + /* + * APERTURE NAME: PUF, START ADDRESS: FFC30000, END ADDRESS: FFC3FFFF + */ + /* + * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + */ + /* + * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + */ + /* + * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F + * FFF + */ + /* + * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F + * FFF + */ + /* + * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + */ + /* + * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + */ + /* + * APERTURE NAME: CSU, START ADDRESS: FFCA0000, END ADDRESS: FFCAFFFF + */ + /* + * APERTURE NAME: CSU_WDT, START ADDRESS: FFCB0000, END ADDRESS: FFCBFFFF + */ + /* + * APERTURE NAME: EFUSE, START ADDRESS: FFCC0000, END ADDRESS: FFCCFFFF + */ + /* + * APERTURE NAME: BBRAM, START ADDRESS: FFCD0000, END ADDRESS: FFCDFFFF + */ + /* + * APERTURE NAME: RSA_CORE, START ADDRESS: FFCE0000, END ADDRESS: FFCEFFFF + */ + /* + * APERTURE NAME: MBISTJTAG, START ADDRESS: FFCF0000, END ADDRESS: FFCFFFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F + * FFF + */ + /* + * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F + * FFF + */ + /* + * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + */ + /* + * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: R5_0_ATCM, START ADDRESS: FFE00000, END ADDRESS: FFE0FFFF + */ + /* + * APERTURE NAME: R5_0_ATCM_LOCKSTEP, START ADDRESS: FFE10000, END ADDRESS: + * FFE1FFFF + */ + /* + * APERTURE NAME: R5_0_BTCM, START ADDRESS: FFE20000, END ADDRESS: FFE2FFFF + */ + /* + * APERTURE NAME: R5_0_BTCM_LOCKSTEP, START ADDRESS: FFE30000, END ADDRESS: + * FFE3FFFF + */ + /* + * APERTURE NAME: R5_0_INSTRUCTION_CACHE, START ADDRESS: FFE40000, END ADDR + * ESS: FFE4FFFF + */ + /* + * APERTURE NAME: R5_0_DATA_CACHE, START ADDRESS: FFE50000, END ADDRESS: FF + * E5FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: R5_1_ATCM_, START ADDRESS: FFE90000, END ADDRESS: FFE9FFF + * F + */ + /* + * APERTURE NAME: RPU_UNUSED_10, START ADDRESS: FFEA0000, END ADDRESS: FFEA + * FFFF + */ + /* + * APERTURE NAME: R5_1_BTCM_, START ADDRESS: FFEB0000, END ADDRESS: FFEBFFF + * F + */ + /* + * APERTURE NAME: R5_1_INSTRUCTION_CACHE, START ADDRESS: FFEC0000, END ADDR + * ESS: FFECFFFF + */ + /* + * APERTURE NAME: R5_1_DATA_CACHE, START ADDRESS: FFED0000, END ADDRESS: FF + * EDFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IOU_GPV, START ADDRESS: FE000000, END ADDRESS: FE0FFFFF + */ + /* + * APERTURE NAME: LPD_GPV, START ADDRESS: FE100000, END ADDRESS: FE1FFFFF + */ + /* + * APERTURE NAME: USB3_0_XHCI, START ADDRESS: FE200000, END ADDRESS: FE2FFF + * FF + */ + /* + * APERTURE NAME: USB3_1_XHCI, START ADDRESS: FE300000, END ADDRESS: FE3FFF + * FF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: QSPI_LINEAR_ADDRESS, START ADDRESS: C0000000, END ADDRESS + * : DFFFFFFF + */ + /* + * XPPU CONTROL + */ + + return 1; +} +unsigned long psu_ddr_xmpu0_data(void) +{ + /* + * DDR XMPU0 + */ + + return 1; +} +unsigned long psu_ddr_xmpu1_data(void) +{ + /* + * DDR XMPU1 + */ + + return 1; +} +unsigned long psu_ddr_xmpu2_data(void) +{ + /* + * DDR XMPU2 + */ + + return 1; +} +unsigned long psu_ddr_xmpu3_data(void) +{ + /* + * DDR XMPU3 + */ + + return 1; +} +unsigned long psu_ddr_xmpu4_data(void) +{ + /* + * DDR XMPU4 + */ + + return 1; +} +unsigned long psu_ddr_xmpu5_data(void) +{ + /* + * DDR XMPU5 + */ + + return 1; +} +unsigned long psu_ocm_xmpu_data(void) +{ + /* + * OCM XMPU + */ + + return 1; +} +unsigned long psu_fpd_xmpu_data(void) +{ + /* + * FPD XMPU + */ + + return 1; +} +unsigned long psu_protection_lock_data(void) +{ + /* + * LOCKING PROTECTION MODULE + */ + /* + * XPPU LOCK + */ + /* + * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + */ + /* + * XMPU LOCK + */ + /* + * LOCK OCM XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK FPD XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + + return 1; +} +unsigned long psu_apply_master_tz(void) +{ + /* + * RPU + */ + /* + * DP TZ + */ + /* + * Register : slcr_dpdma @ 0XFD690040 + + * TrustZone classification for DisplayPort DMA + * PSU_FPD_SLCR_SECURE_SLCR_DPDMA_TZ 1 + + * DPDMA TrustZone Settings + * (OFFSET, MASK, VALUE) (0XFD690040, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * SATA TZ + */ + /* + * PCIE TZ + */ + /* + * Register : slcr_pcie @ 0XFD690030 + + * TrustZone classification for DMA Channel 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0 1 + + * TrustZone classification for DMA Channel 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1 1 + + * TrustZone classification for DMA Channel 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2 1 + + * TrustZone classification for DMA Channel 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3 1 + + * TrustZone classification for Ingress Address Translation 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0 1 + + * TrustZone classification for Ingress Address Translation 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1 1 + + * TrustZone classification for Ingress Address Translation 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2 1 + + * TrustZone classification for Ingress Address Translation 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3 1 + + * TrustZone classification for Ingress Address Translation 4 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4 1 + + * TrustZone classification for Ingress Address Translation 5 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5 1 + + * TrustZone classification for Ingress Address Translation 6 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6 1 + + * TrustZone classification for Ingress Address Translation 7 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7 1 + + * TrustZone classification for Egress Address Translation 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0 1 + + * TrustZone classification for Egress Address Translation 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1 1 + + * TrustZone classification for Egress Address Translation 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2 1 + + * TrustZone classification for Egress Address Translation 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3 1 + + * TrustZone classification for Egress Address Translation 4 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4 1 + + * TrustZone classification for Egress Address Translation 5 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5 1 + + * TrustZone classification for Egress Address Translation 6 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6 1 + + * TrustZone classification for Egress Address Translation 7 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7 1 + + * TrustZone classification for DMA Registers + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS 1 + + * TrustZone classification for MSIx Table + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE 1 + + * TrustZone classification for MSIx PBA + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA 1 + + * TrustZone classification for ECAM + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM 1 + + * TrustZone classification for Bridge Common Registers + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS 1 + + * PCIe TrustZone settings. This register may only be modified during bootu + * p (while PCIe block is disabled) + * (OFFSET, MASK, VALUE) (0XFD690030, 0x01FFFFFFU ,0x01FFFFFFU) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_PCIE_OFFSET, + 0x01FFFFFFU, 0x01FFFFFFU); +/*##################################################################### */ + + /* + * USB TZ + */ + /* + * Register : slcr_usb @ 0XFF4B0034 + + * TrustZone Classification for USB3_0 + * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0 1 + + * TrustZone Classification for USB3_1 + * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1 1 + + * USB3 TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0034, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_USB_OFFSET, + 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * SD TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x003F0000U ,0x00120000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x003F0000U, 0x00120000U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x003F0000U ,0x00120000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x003F0000U, 0x00120000U); +/*##################################################################### */ + + /* + * GEM TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x00000FFFU ,0x00000492U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x00000FFFU, 0x00000492U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x00000FFFU ,0x00000492U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x00000FFFU, 0x00000492U); +/*##################################################################### */ + + /* + * QSPI TZ + */ + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x0E000000U ,0x04000000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x0E000000U, 0x04000000U); +/*##################################################################### */ + + /* + * NAND TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x01C00000U ,0x00800000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x01C00000U, 0x00800000U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x01C00000U ,0x00800000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x01C00000U, 0x00800000U); +/*##################################################################### */ + + /* + * DMA TZ + */ + /* + * Register : slcr_adma @ 0XFF4B0024 + + * TrustZone Classification for ADMA + * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0xFF + + * RPU TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : slcr_gdma @ 0XFD690050 + + * TrustZone Classification for GDMA + * PSU_FPD_SLCR_SECURE_SLCR_GDMA_TZ 0xFF + + * GDMA Trustzone Settings + * (OFFSET, MASK, VALUE) (0XFD690050, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_GDMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_serdes_init_data(void) +{ + /* + * SERDES INITIALIZATION + */ + /* + * GT REFERENCE CLOCK SOURCE SELECTION + */ + /* + * Register : PLL_REF_SEL0 @ 0XFD410000 + + * PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD + + * PLL0 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL0_OFFSET, 0x0000001FU, 0x0000000DU); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL1 @ 0XFD410004 + + * PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9 + + * PLL1 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL1_OFFSET, 0x0000001FU, 0x00000009U); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL2 @ 0XFD410008 + + * PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8 + + * PLL2 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL2_OFFSET, 0x0000001FU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL3 @ 0XFD41000C + + * PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF + + * PLL3 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL3_OFFSET, 0x0000001FU, 0x0000000FU); +/*##################################################################### */ + + /* + * GT REFERENCE CLOCK FREQUENCY SELECTION + */ + /* + * Register : L0_L0_REF_CLK_SEL @ 0XFD402860 + + * Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp + * ut. Set to 0 to select lane0 ref clock mux output. + * PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1 + + * Lane0 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_L0_REF_CLK_SEL_OFFSET, + 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_L1_REF_CLK_SEL @ 0XFD402864 + + * Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane1 ref clock mux output. + * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0 + + * Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli + * cer output from ref clock network + * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1 + + * Lane1 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U) + */ + PSU_Mask_Write(SERDES_L0_L1_REF_CLK_SEL_OFFSET, + 0x00000088U, 0x00000008U); +/*##################################################################### */ + + /* + * Register : L0_L2_REF_CLK_SEL @ 0XFD402868 + + * Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane2 ref clock mux output. + * PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1 + + * Lane2 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_L2_REF_CLK_SEL_OFFSET, + 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_L3_REF_CLK_SEL @ 0XFD40286C + + * Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp + * ut. Set to 0 to select lane3 ref clock mux output. + * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0 + + * Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli + * cer output from ref clock network + * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1 + + * Lane3 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L0_L3_REF_CLK_SEL_OFFSET, + 0x00000082U, 0x00000002U); +/*##################################################################### */ + + /* + * ENABLE SPREAD SPECTRUM + */ + /* + * Register : L2_TM_PLL_DIG_37 @ 0XFD40A094 + + * Enable/Disable coarse code satureation limiting logic + * PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1 + + * Test mode register 37 + * (OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_PLL_DIG_37_OFFSET, + 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x00000038U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x000000E0U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x00000058U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x0000007CU); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374 + + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33 + + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x00000033U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378 + + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 + + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C + + * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 + + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x00000033U, 0x00000030U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4 + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x000000F4U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374 + + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31 + + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x00000031U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378 + + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 + + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C + + * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 + + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x00000033U, 0x00000030U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9 + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x000000C9U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374 + + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2 + + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x000000D2U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378 + + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1 + + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C + + * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 + + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable test mode forcing on enable Spread Spectrum + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1 + + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x000000B3U, 0x000000B0U); +/*##################################################################### */ + + /* + * Register : L2_TM_DIG_6 @ 0XFD40906C + + * Bypass Descrambler + * PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1 + + * Enable Bypass for <1> TM_DIG_CTRL_6 + * PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 + + * Data path test modes in decoder and descram + * (OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_6_OFFSET, 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L2_TX_DIG_TM_61 @ 0XFD4080F4 + + * Bypass scrambler signal + * PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1 + + * Enable/disable scrambler bypass signal + * PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 + + * MPHY PLL Gear and bypass scrambler + * (OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_TX_DIG_TM_61_OFFSET, + 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360 + + * Enable test mode force on fractional mode enable + * PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1 + + * Fractional feedback division control and fractional value for feedback d + * ivision bits 26:24 + * (OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L3_TM_DIG_6 @ 0XFD40D06C + + * Bypass 8b10b decoder + * PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1 + + * Enable Bypass for <3> TM_DIG_CTRL_6 + * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1 + + * Bypass Descrambler + * PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1 + + * Enable Bypass for <1> TM_DIG_CTRL_6 + * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 + + * Data path test modes in decoder and descram + * (OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_6_OFFSET, 0x0000000FU, 0x0000000FU); +/*##################################################################### */ + + /* + * Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4 + + * Enable/disable encoder bypass signal + * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1 + + * Bypass scrambler signal + * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1 + + * Enable/disable scrambler bypass signal + * PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 + + * MPHY PLL Gear and bypass scrambler + * (OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU) + */ + PSU_Mask_Write(SERDES_L3_TX_DIG_TM_61_OFFSET, + 0x0000000BU, 0x0000000BU); +/*##################################################################### */ + + /* + * ENABLE CHICKEN BIT FOR PCIE AND USB + */ + /* + * Register : L0_TM_AUX_0 @ 0XFD4010CC + + * Spare- not used + * PSU_SERDES_L0_TM_AUX_0_BIT_2 1 + + * Spare registers + * (OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L0_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L2_TM_AUX_0 @ 0XFD4090CC + + * Spare- not used + * PSU_SERDES_L2_TM_AUX_0_BIT_2 1 + + * Spare registers + * (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L2_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * ENABLING EYE SURF + */ + /* + * Register : L0_TM_DIG_8 @ 0XFD401074 + + * Enable Eye Surf + * PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L0_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L1_TM_DIG_8 @ 0XFD405074 + + * Enable Eye Surf + * PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L1_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_DIG_8 @ 0XFD409074 + + * Enable Eye Surf + * PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L3_TM_DIG_8 @ 0XFD40D074 + + * Enable Eye Surf + * PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * ILL SETTINGS FOR GAIN AND LOCK SETTINGS + */ + /* + * Register : L0_TM_MISC2 @ 0XFD40189C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL1 @ 0XFD4018F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL2 @ 0XFD4018FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL12 @ 0XFD401990 + + * G1A pll ctr bypass value + * PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL12_OFFSET, 0x000000FFU, 0x00000011U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL1 @ 0XFD401924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL1_OFFSET, 0x000000FFU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL2 @ 0XFD401928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL2_OFFSET, 0x000000FFU, 0x000000FEU); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL3 @ 0XFD401900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL3 @ 0XFD40192C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL8 @ 0XFD401980 + + * ILL calibration code change wait time + * PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL8 @ 0XFD401914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL9 @ 0XFD401918 + + * bypass IQ polytrim + * PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL8 @ 0XFD401940 + + * E ILL polytrim bypass value + * PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL9 @ 0XFD401944 + + * bypass E polytrim + * PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL13 @ 0XFD401994 + + * ILL cal idle val refcnt + * PSU_SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD401994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L1_TM_ILL13 @ 0XFD405994 + + * ILL cal idle val refcnt + * PSU_SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD405994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L1_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L2_TM_MISC2 @ 0XFD40989C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L2_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL1 @ 0XFD4098F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL2 @ 0XFD4098FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL12 @ 0XFD409990 + + * G1A pll ctr bypass value + * PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL12_OFFSET, 0x000000FFU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL1 @ 0XFD409924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL1_OFFSET, 0x000000FFU, 0x000000FEU); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL2 @ 0XFD409928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL3 @ 0XFD409900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL3 @ 0XFD40992C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL8 @ 0XFD409980 + + * ILL calibration code change wait time + * PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL8 @ 0XFD409914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL9 @ 0XFD409918 + + * bypass IQ polytrim + * PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL8 @ 0XFD409940 + + * E ILL polytrim bypass value + * PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL9 @ 0XFD409944 + + * bypass E polytrim + * PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL13 @ 0XFD409994 + + * ILL cal idle val refcnt + * PSU_SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD409994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L3_TM_MISC2 @ 0XFD40D89C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L3_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL12 @ 0XFD40D990 + + * G1A pll ctr bypass value + * PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL12_OFFSET, 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL1 @ 0XFD40D924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL1_OFFSET, 0x000000FFU, 0x0000009CU); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL2 @ 0XFD40D928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000039U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL11 @ 0XFD40D98C + + * G2A_PCIe1 PLL ctr bypass value + * PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL11_OFFSET, 0x000000F0U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL3 @ 0XFD40D900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL3 @ 0XFD40D92C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL8 @ 0XFD40D980 + + * ILL calibration code change wait time + * PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL8 @ 0XFD40D914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL9 @ 0XFD40D918 + + * bypass IQ polytrim + * PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL8 @ 0XFD40D940 + + * E ILL polytrim bypass value + * PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL9 @ 0XFD40D944 + + * bypass E polytrim + * PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL13 @ 0XFD40D994 + + * ILL cal idle val refcnt + * PSU_SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD40D994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * SYMBOL LOCK AND WAIT + */ + /* + * Register : L0_TM_DIG_10 @ 0XFD40107C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L1_TM_DIG_10 @ 0XFD40507C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40507C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L1_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_DIG_10 @ 0XFD40907C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40907C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_DIG_10 @ 0XFD40D07C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40D07C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG + */ + /* + * Register : L0_TM_RST_DLY @ 0XFD4019A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L0_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L0_TM_ANA_BYP_15 @ 0XFD401038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L0_TM_ANA_BYP_12 @ 0XFD40102C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L1_TM_RST_DLY @ 0XFD4059A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L1_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L1_TM_ANA_BYP_15 @ 0XFD405038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L1_TM_ANA_BYP_12 @ 0XFD40502C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L2_TM_RST_DLY @ 0XFD4099A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L2_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L2_TM_ANA_BYP_15 @ 0XFD409038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L2_TM_ANA_BYP_12 @ 0XFD40902C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L3_TM_RST_DLY @ 0XFD40D9A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L3_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L3_TM_ANA_BYP_15 @ 0XFD40D038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * DISABLE FPL/FFL + */ + /* + * Register : L0_TM_MISC3 @ 0XFD4019AC + + * CDR fast phase lock control + * PSU_SERDES_L0_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L0_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4019AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L0_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L1_TM_MISC3 @ 0XFD4059AC + + * CDR fast phase lock control + * PSU_SERDES_L1_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L1_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4059AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_MISC3 @ 0XFD4099AC + + * CDR fast phase lock control + * PSU_SERDES_L2_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L2_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4099AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L3_TM_MISC3 @ 0XFD40D9AC + + * CDR fast phase lock control + * PSU_SERDES_L3_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L3_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD40D9AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L3_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * DISABLE DYNAMIC OFFSET CALIBRATION + */ + /* + * Register : L0_TM_EQ11 @ 0XFD401978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD401978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L0_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L1_TM_EQ11 @ 0XFD405978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD405978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L1_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_EQ11 @ 0XFD409978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD409978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ11 @ 0XFD40D978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD40D978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * SERDES ILL CALIB + */ + serdes_illcalib(2,3,3,0,4,0,1,1); + +/*##################################################################### */ + + /* + * DISABLE ECO FOR PCIE + */ + /* + * Register : eco_0 @ 0XFD3D001C + + * For future use + * PSU_SIOU_ECO_0_FIELD 0x1 + + * ECO Register for future use + * (OFFSET, MASK, VALUE) (0XFD3D001C, 0xFFFFFFFFU ,0x00000001U) + */ + PSU_Mask_Write(SIOU_ECO_0_OFFSET, 0xFFFFFFFFU, 0x00000001U); +/*##################################################################### */ + + /* + * GT LANE SETTINGS + */ + /* + * Register : ICM_CFG0 @ 0XFD410010 + + * Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1 + + * Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4 + + * ICM Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U) + */ + PSU_Mask_Write(SERDES_ICM_CFG0_OFFSET, 0x00000077U, 0x00000041U); +/*##################################################################### */ + + /* + * Register : ICM_CFG1 @ 0XFD410014 + + * Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3 + + * Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, + * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2 + + * ICM Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U) + */ + PSU_Mask_Write(SERDES_ICM_CFG1_OFFSET, 0x00000077U, 0x00000023U); +/*##################################################################### */ + + /* + * CHECKING PLL LOCK + */ + /* + * ENABLE SERIAL DATA MUX DEEMPH + */ + /* + * Register : L1_TXPMD_TM_45 @ 0XFD404CB4 + + * Enable/disable DP post2 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1 + + * Override enable/disable of DP post2 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1 + + * Override enable/disable of DP post1 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1 + + * Enable/disable DP main path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1 + + * Override enable/disable of DP main path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1 + + * Post or pre or main DP path selection + * (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U) + */ + PSU_Mask_Write(SERDES_L1_TXPMD_TM_45_OFFSET, + 0x00000037U, 0x00000037U); +/*##################################################################### */ + + /* + * Register : L1_TX_ANA_TM_118 @ 0XFD4041D8 + + * Test register force for enabling/disablign TX deemphasis bits <17:0> + * PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 + + * Enable Override of TX deemphasis + * (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L1_TX_ANA_TM_118_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8 + + * Test register force for enabling/disablign TX deemphasis bits <17:0> + * PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 + + * Enable Override of TX deemphasis + * (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TX_ANA_TM_118_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * CDR AND RX EQUALIZATION SETTINGS + */ + /* + * Register : L3_TM_CDR5 @ 0XFD40DC14 + + * FPHL FSM accumulate cycles + * PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7 + + * FFL Phase0 int gain aka 2ol SD update rate + * PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6 + + * Fast phase lock controls -- FSM accumulator cycle control and phase 0 in + * t gain control. + * (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U) + */ + PSU_Mask_Write(SERDES_L3_TM_CDR5_OFFSET, 0x000000FFU, 0x000000E6U); +/*##################################################################### */ + + /* + * Register : L3_TM_CDR16 @ 0XFD40DC40 + + * FFL Phase0 prop gain aka 1ol SD update rate + * PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC + + * Fast phase lock controls -- phase 0 prop gain + * (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU) + */ + PSU_Mask_Write(SERDES_L3_TM_CDR16_OFFSET, 0x0000001FU, 0x0000000CU); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ0 @ 0XFD40D94C + + * EQ stg 2 controls BYPASSED + * PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1 + + * eq stg1 and stg2 controls + * (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ1 @ 0XFD40D950 + + * EQ STG2 RL PROG + * PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2 + + * EQ stg 2 preamp mode val + * PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1 + + * eq stg1 and stg2 controls + * (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ1_OFFSET, 0x00000007U, 0x00000006U); +/*##################################################################### */ + + /* + * GEM SERDES SETTINGS + */ + /* + * ENABLE PRE EMPHAIS AND VOLTAGE SWING + */ + /* + * Register : L1_TXPMD_TM_48 @ 0XFD404CC0 + + * Margining factor value + * PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0 + + * Margining factor + * (OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TXPMD_TM_48_OFFSET, + 0x0000001FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L1_TX_ANA_TM_18 @ 0XFD404048 + + * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved + * PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0 + + * Override for PIPE TX de-emphasis + * (OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TX_ANA_TM_18_OFFSET, + 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L3_TX_ANA_TM_18 @ 0XFD40C048 + + * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved + * PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1 + + * Override for PIPE TX de-emphasis + * (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TX_ANA_TM_18_OFFSET, + 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_resetout_init_data(void) +{ + /* + * TAKING SERDES PERIPHERAL OUT OF RESET RESET + */ + /* + * PUTTING USB0 IN RESET + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000400U, 0x00000000U); +/*##################################################################### */ + + /* + * USB0 PIPE POWER PRESENT + */ + /* + * Register : fpd_power_prsnt @ 0XFF9D0080 + + * This bit is used to choose between PIPE power present and 1'b1 + * PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1 + + * fpd_power_prsnt + * (OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(USB3_0_FPD_POWER_PRSNT_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : fpd_pipe_clk @ 0XFF9D007C + + * This bit is used to choose between PIPE clock coming from SerDes and the + * suspend clk + * PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0 + + * fpd_pipe_clk + * (OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(USB3_0_FPD_PIPE_CLK_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * HIBERREST + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0 + + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000140U, 0x00000000U); +/*##################################################################### */ + + /* + * PUTTING GEM0 IN RESET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 + + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0 + + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * PUTTING SATA IN RESET + */ + /* + * Register : sata_misc_ctrl @ 0XFD3D0100 + + * Sata PM clock control select + * PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3 + + * Misc Contorls for SATA.This register may only be modified during bootup + * (while SATA block is disabled) + * (OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SIOU_SATA_MISC_CTRL_OFFSET, 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ + + /* + * PUTTING PCIE CFG AND BRIDGE IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0 + + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000C0000U, 0x00000000U); +/*##################################################################### */ + + /* + * PUTTING DP IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DP_PHY_RESET @ 0XFD4A0200 + + * Set to '1' to hold the GT in reset. Clear to release. + * PSU_DP_DP_PHY_RESET_GT_RESET 0X0 + + * Reset the transmitter PHY. + * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238 + + * Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 + * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0 + + * Control PHY Power down + * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET, + 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * USB0 GFLADJ + */ + /* + * Register : GUSB2PHYCFG @ 0XFE20C200 + + * USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc + * ks. Specifies the response time for a MAC request to the Packet FIFO Con + * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th + * e required values for the minimum SoC bus frequency of 60 MHz. USB turna + * round time is a critical certification criteria when using long cables a + * nd five hub levels. The required values for this field: - 4'h5: When the + * MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit + * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim + * e is not critical, this field can be set to a larger value. Note: This f + * ield is valid only in device mode. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9 + + * Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP + * I Transceiver Select signal (for HS) and the assertion of the TxValid si + * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima + * tely 2.5 us) is introduced from the time when the Transceiver Select is + * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the + * chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you + * enable the hibernation feature when the device core comes out of power- + * off, you must re-initialize this bit with the appropriate value because + * the core does not save and restore this bit value during hibernation. - + * This bit is valid only in device mode. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0 + + * Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use + * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th + * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert + * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s + * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t + * he external PHY. Note: This bit must be set high for Port0 if PHY is use + * d. Note: In Device mode - Before issuing any device endpoint command whe + * n operating in 2.0 speeds, disable this bit and enable it after the comm + * and completes. Without disabling this bit, if a command is issued when t + * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of + * f, the command will not get completed. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0 + + * USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T + * he application uses this bit to select a high-speed PHY or a full-speed + * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a + * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans + * ceiver. This bit is always 1, with Write Only access. If both interface + * types are selected in coreConsultant (that is, parameters' values are no + * t zero), the application uses this bit to select the active interface is + * active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv + * er is not supported. This bit always reads as 1'b0. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0 + + * Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend + * mode if Suspend conditions are valid. For DRD/OTG configurations, it is + * recommended that this bit is set to 0 during coreConsultant configurati + * on. If it is set to 1, then the application must clear this bit after po + * wer-on reset. Application needs to set it to 1 after the core initializa + * tion completes. For all other configurations, this bit can be set to 1 d + * uring core configuration. Note: - In host mode, on reset, this bit is se + * t to 1. Software can override this bit after reset. - In device mode, be + * fore issuing any device endpoint command when operating in 2.0 speeds, d + * isable this bit and enable it after the command completes. If you issue + * a command without disabling this bit when the device is in L2 state and + * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c + * ompleted. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0x1 + + * Full-Speed Serial Interface Select (FSIntf) The application uses this bi + * t to select a unidirectional or bidirectional USB 1.1 full-speed serial + * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in + * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir + * ectional full-speed serial interface. This bit is set to 0 with Read Onl + * y access. Note: USB 1.1 full-speed serial interface is not supported. Th + * is bit always reads as 1'b0. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0 + + * ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se + * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int + * erface This bit is writable only if UTMI+ and ULPI is specified for High + * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_ + * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o + * n the interface selected through DWC_USB3_HSPHY_INTERFACE. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1 + + * PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi + * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte + * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en + * abled 2.0 ports must have the same clock frequency as Port0 clock freque + * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge + * ther for different ports at the same time (that is, all the ports must b + * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If + * any of the USB 2.0 ports is selected as ULPI port for operation, then a + * ll the USB 2.0 ports must be operating at 60 MHz. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0 + + * HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat + * ed by the application in this field, is multiplied by a bit-time factor; + * this factor is added to the high-speed/full-speed interpacket timeout d + * uration in the core to account for additional delays introduced by the P + * HY. This may be required, since the delay introduced by the PHY in gener + * ating the linestate condition may vary among PHYs. The USB standard time + * out value for high-speed operation is 736 to 816 (inclusive) bit times. + * The USB standard timeout value for full-speed operation is 16 to 18 (inc + * lusive) bit times. The application must program this field based on the + * speed of connection. The number of bit times added per PHY clock are: Hi + * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P + * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0. + * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc + * k = 0.25 bit times + * PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7 + + * ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive + * 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char + * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl + * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3) + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV 0x1 + + * Global USB2 PHY Configuration Register The application must program this + * register before starting any transactions on either the SoC bus or the + * USB. In Device-only configurations, only one register is needed. In Host + * mode, per-port registers are implemented. + * (OFFSET, MASK, VALUE) (0XFE20C200, 0x00023FFFU ,0x00022457U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUSB2PHYCFG_OFFSET, + 0x00023FFFU, 0x00022457U); +/*##################################################################### */ + + /* + * Register : GFLADJ @ 0XFE20C630 + + * This field indicates the frame length adjustment to be applied when SOF/ + * ITP counter is running on the ref_clk. This register value is used to ad + * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i + * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must + * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t + * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows: + * FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe + * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege + * r value of the ref_clk period got by truncating the decimal (fractional) + * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c + * lk_period is the ref_clk period including the fractional value. Examples + * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA + * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin + * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE + * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2 + * 0.8333 = 5208 (ignoring the fractional value) + * PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0 + + * Global Frame Length Adjustment Register This register provides options f + * or the software to control the core behavior with respect to SOF (Start + * of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer + * functionality. It provides an option to override the fladj_30mhz_reg sid + * eband signal. In addition, it enables running SOF or ITP frame timer cou + * nters completely from the ref_clk. This facilitates hardware LPM in host + * mode with the SOF or ITP counters being run from the ref_clk signal. + * (OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) + */ + PSU_Mask_Write(USB3_0_XHCI_GFLADJ_OFFSET, 0x003FFF00U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : GUCTL1 @ 0XFE20C11C + + * When this bit is set to '0', termsel, xcvrsel will become 0 during end o + * f resume while the opmode will become 0 once controller completes end of + * resume and enters U0 state (2 separate commandswill be issued). When th + * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during + * end of resume itself (only 1 command will be issued) + * PSU_USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY 0x1 + + * Reserved + * PSU_USB3_0_XHCI_GUCTL1_RESERVED_9 0x1 + + * Global User Control Register 1 + * (OFFSET, MASK, VALUE) (0XFE20C11C, 0x00000600U ,0x00000600U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUCTL1_OFFSET, 0x00000600U, 0x00000600U); +/*##################################################################### */ + + /* + * Register : GUCTL @ 0XFE20C12C + + * Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th + * e Auto Retry feature. For IN transfers (non-isochronous) that encounter + * data packets with CRC errors or internal overrun scenarios, the auto ret + * ry feature causes the Host core to reply to the device with a non-termin + * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N + * umP != 0). If the Auto Retry feature is disabled (default), the core wil + * l respond with a terminating retry ACK (that is, an ACK transaction pack + * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut + * o Retry Enabled Note: This bit is also applicable to the device mode. + * PSU_USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN 0x1 + + * Global User Control Register: This register provides a few options for t + * he software to control the core behavior in the Host mode. Most of the o + * ptions are used to improve host inter-operability with different devices + * . + * (OFFSET, MASK, VALUE) (0XFE20C12C, 0x00004000U ,0x00004000U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUCTL_OFFSET, 0x00004000U, 0x00004000U); +/*##################################################################### */ + + /* + * UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCO + * RRECT RESET VALUES IN SILICON. + */ + /* + * Register : ATTR_25 @ 0XFD480064 + + * If TRUE Completion Timeout Disable is supported. This is required to be + * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi + * ce Capability 2 [4]; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1 + + * ATTR_25 + * (OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x00000200U, 0x00000200U); +/*##################################################################### */ + + /* + * PCIE SETTINGS + */ + /* + * Register : ATTR_7 @ 0XFD48001C + + * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0x0004; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0 + + * ATTR_7 + * (OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_7_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_8 @ 0XFD480020 + + * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0xFFF0; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0 + + * ATTR_8 + * (OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_8_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_9 @ 0XFD480024 + + * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0 + + * ATTR_9 + * (OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_9_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_10 @ 0XFD480028 + + * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0 + + * ATTR_10 + * (OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_10_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_11 @ 0XFD48002C + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFFF + * PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF + + * ATTR_11 + * (OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_11_OFFSET, 0x0000FFFFU, 0x0000FFFFU); +/*##################################################################### */ + + /* + * Register : ATTR_12 @ 0XFD480030 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0x00FF + * PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF + + * ATTR_12 + * (OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_12_OFFSET, 0x0000FFFFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : ATTR_13 @ 0XFD480034 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0 + + * ATTR_13 + * (OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_13_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_14 @ 0XFD480038 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0xFFFF + * PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF + + * ATTR_14 + * (OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_14_OFFSET, 0x0000FFFFU, 0x0000FFFFU); +/*##################################################################### */ + + /* + * Register : ATTR_15 @ 0XFD48003C + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFF0 + * PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0 + + * ATTR_15 + * (OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_15_OFFSET, 0x0000FFFFU, 0x0000FFF0U); +/*##################################################################### */ + + /* + * Register : ATTR_16 @ 0XFD480040 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0xFFF0 + * PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0 + + * ATTR_16 + * (OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_16_OFFSET, 0x0000FFFFU, 0x0000FFF0U); +/*##################################################################### */ + + /* + * Register : ATTR_17 @ 0XFD480044 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 + * PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1 + + * ATTR_17 + * (OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_17_OFFSET, 0x0000FFFFU, 0x0000FFF1U); +/*##################################################################### */ + + /* + * Register : ATTR_18 @ 0XFD480048 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 + * PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1 + + * ATTR_18 + * (OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_18_OFFSET, 0x0000FFFFU, 0x0000FFF1U); +/*##################################################################### */ + + /* + * Register : ATTR_27 @ 0XFD48006C + + * Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1 + * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa + * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo + * rted; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1 + + * Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca + * n withstand on transitions from L1 state to L0 (if L1 state supported). + * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to + * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For + * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0 + + * ATTR_27 + * (OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_27_OFFSET, 0x00000738U, 0x00000100U); +/*##################################################################### */ + + /* + * Register : ATTR_50 @ 0XFD4800C8 + + * Identifies the type of device/port as follows: 0000b PCI Express Endpoin + * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P + * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110 + * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X + * Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre + * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM + * _FACING settings.; EP=0x0000; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4 + + * PCIe Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x009C; + * RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0 + + * ATTR_50 + * (OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_50_OFFSET, 0x0000FFF0U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : ATTR_105 @ 0XFD4801A4 + + * Number of credits that should be advertised for Completion data received + * on Virtual Channel 0. The bytes advertised must be less than or equal t + * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD + * PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD + + * ATTR_105 + * (OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_105_OFFSET, + 0x000007FFU, 0x000000CDU); +/*##################################################################### */ + + /* + * Register : ATTR_106 @ 0XFD4801A8 + + * Number of credits that should be advertised for Completion headers recei + * ved on Virtual Channel 0. The sum of the posted, non posted, and complet + * ion header credits must be <= 80; EP=0x0048; RP=0x0024 + * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24 + + * Number of credits that should be advertised for Non-Posted headers recei + * ved on Virtual Channel 0. The number of non posted data credits advertis + * ed by the block is equal to the number of non posted header credits. The + * sum of the posted, non posted, and completion header credits must be <= + * 80; EP=0x0004; RP=0x000C + * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC + + * ATTR_106 + * (OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_106_OFFSET, + 0x00003FFFU, 0x00000624U); +/*##################################################################### */ + + /* + * Register : ATTR_107 @ 0XFD4801AC + + * Number of credits that should be advertised for Non-Posted data received + * on Virtual Channel 0. The number of non posted data credits advertised + * by the block is equal to two times the number of non posted header credi + * ts if atomic operations are supported or is equal to the number of non p + * osted header credits if atomic operations are not supported. The bytes a + * dvertised must be less than or equal to the bram bytes available. See VC + * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 + * PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18 + + * ATTR_107 + * (OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_107_OFFSET, + 0x000007FFU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : ATTR_108 @ 0XFD4801B0 + + * Number of credits that should be advertised for Posted data received on + * Virtual Channel 0. The bytes advertised must be less than or equal to th + * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 + * PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5 + + * ATTR_108 + * (OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_108_OFFSET, + 0x000007FFU, 0x000000B5U); +/*##################################################################### */ + + /* + * Register : ATTR_109 @ 0XFD4801B4 + + * Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_ + * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0 + + * Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim + * TRUE == trim.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1 + + * Enables ECRC check on received TLP's 0 == don't check 1 == always check + * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP= + * 0x0003; RP=0x0003 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3 + + * Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). + * Calculated from max payload size supported and the number of brams conf + * igured for transmit; EP=0x001C; RP=0x001C + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c + + * Number of credits that should be advertised for Posted headers received + * on Virtual Channel 0. The sum of the posted, non posted, and completion + * header credits must be <= 80; EP=0x0004; RP=0x0020 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20 + + * ATTR_109 + * (OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_109_OFFSET, + 0x0000FFFFU, 0x00007E20U); +/*##################################################################### */ + + /* + * Register : ATTR_34 @ 0XFD480088 + + * Specifies values to be transferred to Header Type register. Bit 7 should + * be set to '0' indicating single-function device. Bit 0 identifies heade + * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; + * RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1 + + * ATTR_34 + * (OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_34_OFFSET, 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : ATTR_53 @ 0XFD4800D4 + + * PM Capability's Next Capability Offset pointer to the next item in the c + * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP + * =0x0060 + * PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60 + + * ATTR_53 + * (OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_53_OFFSET, 0x000000FFU, 0x00000060U); +/*##################################################################### */ + + /* + * Register : ATTR_41 @ 0XFD4800A4 + + * MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont + * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure; + * EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0 + + * Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 + + * MSI Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x0060; R + * P=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0 + + * Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 + + * ATTR_41 + * (OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_41_OFFSET, 0x000003FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_97 @ 0XFD480184 + + * Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b + * x4, 001000b x8.; EP=0x0004; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1 + + * Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1 + * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1 + + * ATTR_97 + * (OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_97_OFFSET, 0x00000FFFU, 0x00000041U); +/*##################################################################### */ + + /* + * Register : ATTR_100 @ 0XFD480190 + + * TRUE specifies upstream-facing port. FALSE specifies downstream-facing p + * ort.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0 + + * ATTR_100 + * (OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_100_OFFSET, + 0x00000040U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_101 @ 0XFD480194 + + * Enable the routing of message TLPs to the user through the TRN RX interf + * ace. A bit value of 1 enables routing of the message TLP to the user. Me + * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 + * - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I + * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit + * 10 PME_Turn_Off; EP=0x0000; RP=0x07FF + * PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF + + * Disable BAR filtering. Does not change the behavior of the bar hit outpu + * ts; EP=0x0000; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1 + + * ATTR_101 + * (OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_101_OFFSET, + 0x0000FFE2U, 0x0000FFE2U); +/*##################################################################### */ + + /* + * Register : ATTR_37 @ 0XFD480094 + + * Link Bandwidth notification capability. Indicates support for the link b + * andwidth notification status and interrupt mechanism. Required for Root. + * ; EP=0x0000; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1 + + * Maximum Link Speed. Valid settings are: 0001b [2.5 GT/s], 0010b [5.0 GT/ + * s and 2.5 GT/s].; EP=0x0002; RP=0x0002 + * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_MAX_LINK_SPEED 0x2 + + * Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op + * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001 + * ; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1 + + * ATTR_37 + * (OFFSET, MASK, VALUE) (0XFD480094, 0x00007E00U ,0x00004A00U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_37_OFFSET, 0x00007E00U, 0x00004A00U); +/*##################################################################### */ + + /* + * Register : ATTR_93 @ 0XFD480174 + + * Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value + * (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU + * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1 + + * Sets a user-defined timeout for the Replay Timer to force cause the retr + * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_ + * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att + * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.; + * EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000 + + * ATTR_93 + * (OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_93_OFFSET, 0x0000FFFFU, 0x00009000U); +/*##################################################################### */ + + /* + * Register : ID @ 0XFD480200 + + * Device ID for the the PCIe Cap Structure Device ID field + * PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd011 + + * Vendor ID for the PCIe Cap Structure Vendor ID field + * PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee + + * ID + * (OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED011U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ID_OFFSET, 0xFFFFFFFFU, 0x10EED011U); +/*##################################################################### */ + + /* + * Register : SUBSYS_ID @ 0XFD480204 + + * Subsystem ID for the the PCIe Cap Structure Subsystem ID field + * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7 + + * Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field + * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee + + * SUBSYS_ID + * (OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U) + */ + PSU_Mask_Write(PCIE_ATTRIB_SUBSYS_ID_OFFSET, + 0xFFFFFFFFU, 0x10EE0007U); +/*##################################################################### */ + + /* + * Register : REV_ID @ 0XFD480208 + + * Revision ID for the the PCIe Cap Structure + * PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0 + + * REV_ID + * (OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_REV_ID_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_24 @ 0XFD480060 + + * Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000 + * PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x8000 + + * ATTR_24 + * (OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00008000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_24_OFFSET, 0x0000FFFFU, 0x00008000U); +/*##################################################################### */ + + /* + * Register : ATTR_25 @ 0XFD480064 + + * Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6 + + * INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] + * to be hardwired to 0.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0 + + * ATTR_25 + * (OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x000001FFU, 0x00000006U); +/*##################################################################### */ + + /* + * Register : ATTR_4 @ 0XFD480010 + + * Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 + + * Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 + + * ATTR_4 + * (OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_4_OFFSET, 0x00001000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_89 @ 0XFD480164 + + * VSEC's Next Capability Offset pointer to the next item in the capabiliti + * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140 + * PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0 + + * ATTR_89 + * (OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_89_OFFSET, 0x00001FFEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_79 @ 0XFD48013C + + * CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the + * Root Capabilities register.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1 + + * ATTR_79 + * (OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_79_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : ATTR_43 @ 0XFD4800AC + + * Indicates that the MSIX structures exists. If this is FALSE, then the MS + * IX structure cannot be accessed via either the link or the management po + * rt.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0 + + * ATTR_43 + * (OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_43_OFFSET, 0x00000100U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_48 @ 0XFD4800C0 + + * MSI-X Table Size. This value is transferred to the MSI-X Message Control + * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does + * not implement the table; that must be implemented in user logic.; EP=0x0 + * 003; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0 + + * ATTR_48 + * (OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_48_OFFSET, 0x000007FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_46 @ 0XFD4800B8 + + * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0 + + * ATTR_46 + * (OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_46_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_47 @ 0XFD4800BC + + * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0 + + * ATTR_47 + * (OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_47_OFFSET, 0x00001FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_44 @ 0XFD4800B0 + + * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0 + + * ATTR_44 + * (OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_44_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_45 @ 0XFD4800B4 + + * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0 + + * ATTR_45 + * (OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_45_OFFSET, 0x0000FFF8U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CB @ 0XFD48031C + + * DT837748 Enable + * PSU_PCIE_ATTRIB_CB_CB1 0x0 + + * ECO Register 1 + * (OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_CB_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_35 @ 0XFD48008C + + * Active State PM Support. Indicates the level of active state power manag + * ement supported by the selected PCI Express Link, encoded as follows: 0 + * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte + * d.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0 + + * Data Link Layer Link Active status notification is supported. This is op + * tional for Upstream ports.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP 1 + + * ATTR_35 + * (OFFSET, MASK, VALUE) (0XFD48008C, 0x0000B000U ,0x00008000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_35_OFFSET, 0x0000B000U, 0x00008000U); +/*##################################################################### */ + + /* + * PUTTING PCIE CONTROL IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00020000U, 0x00000000U); +/*##################################################################### */ + + /* + * PCIE GPIO RESET + */ + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0020U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * CHECK PLL LOCK FOR LANE0 + */ + /* + * Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE1 + */ + /* + * Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE2 + */ + /* + * Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE3 + */ + /* + * Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * SATA AHCI VENDOR SETTING + */ + /* + * Register : PP2C @ 0XFD0C00AC + + * CIBGMN: COMINIT Burst Gap Minimum. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18 + + * CIBGMX: COMINIT Burst Gap Maximum. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40 + + * CIBGN: COMINIT Burst Gap Nominal. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18 + + * CINMP: COMINIT Negate Minimum Period. + * PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28 + + * PP2C - Port Phy2Cfg Register. This register controls the configuration o + * f the Phy Control OOB timing for the COMINIT parameters for either Port + * 0 or Port 1. The Port configured is controlled by the value programmed i + * nto the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP2C_OFFSET, + 0xFFFFFFFFU, 0x28184018U); +/*##################################################################### */ + + /* + * Register : PP3C @ 0XFD0C00B0 + + * CWBGMN: COMWAKE Burst Gap Minimum. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06 + + * CWBGMX: COMWAKE Burst Gap Maximum. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14 + + * CWBGN: COMWAKE Burst Gap Nominal. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08 + + * CWNMP: COMWAKE Negate Minimum Period. + * PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E + + * PP3C - Port Phy3CfgRegister. This register controls the configuration of + * the Phy Control OOB timing for the COMWAKE parameters for either Port 0 + * or Port 1. The Port configured is controlled by the value programmed in + * to the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP3C_OFFSET, + 0xFFFFFFFFU, 0x0E081406U); +/*##################################################################### */ + + /* + * Register : PP4C @ 0XFD0C00B4 + + * BMX: COM Burst Maximum. + * PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13 + + * BNM: COM Burst Nominal. + * PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08 + + * SFD: Signal Failure Detection, if the signal detection de-asserts for a + * time greater than this then the OOB detector will determine this is a li + * ne idle and cause the PhyInit state machine to exit the Phy Ready State. + * A value of zero disables the Signal Failure Detector. The value is base + * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving + * a nominal time of 500ns based on a 150MHz PMCLK. + * PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A + + * PTST: Partial to Slumber timer value, specific delay the controller shou + * ld apply while in partial before entering slumber. The value is bases on + * the system clock divided by 128, total delay = (Sys Clock Period) * PTS + * T * 128 + * PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06 + + * PP4C - Port Phy4Cfg Register. This register controls the configuration o + * f the Phy Control Burst timing for the COM parameters for either Port 0 + * or Port 1. The Port configured is controlled by the value programmed int + * o the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP4C_OFFSET, + 0xFFFFFFFFU, 0x064A0813U); +/*##################################################################### */ + + /* + * Register : PP5C @ 0XFD0C00B8 + + * RIT: Retry Interval Timer. The calculated value divided by two, the lowe + * r digit of precision is not needed. + * PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4 + + * RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev + * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a + * fast SERDES it is suggested that this value be 54.2us / 4 + * PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF + + * PP5C - Port Phy5Cfg Register. This register controls the configuration o + * f the Phy Control Retry Interval timing for either Port 0 or Port 1. The + * Port configured is controlled by the value programmed into the Port Con + * fig Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP5C_OFFSET, + 0xFFFFFFFFU, 0x3FFC96A4U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_resetin_init_data(void) +{ + /* + * PUTTING SERDES PERIPHERAL IN RESET + */ + /* + * PUTTING USB0 IN RESET + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X1 + + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X1 + + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X1 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000540U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000540U, 0x00000540U); +/*##################################################################### */ + + /* + * PUTTING GEM0 IN RESET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 + + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X1 + + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * PUTTING SATA IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X1 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000002U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000002U); +/*##################################################################### */ + + /* + * PUTTING PCIE IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1 + + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000E0000U, 0x000E0000U); +/*##################################################################### */ + + /* + * PUTTING DP IN RESET + */ + /* + * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238 + + * Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 + * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA + + * Control PHY Power down + * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x0000000AU) + */ + PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET, + 0x0000000FU, 0x0000000AU); +/*##################################################################### */ + + /* + * Register : DP_PHY_RESET @ 0XFD4A0200 + + * Set to '1' to hold the GT in reset. Clear to release. + * PSU_DP_DP_PHY_RESET_GT_RESET 0X1 + + * Reset the transmitter PHY. + * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000002U) + */ + PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000002U); +/*##################################################################### */ + + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X1 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00010000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00010000U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_ps_pl_isolation_removal_data(void) +{ + /* + * PS-PL POWER UP REQUEST + */ + /* + * Register : REQ_PWRUP_INT_EN @ 0XFFD80118 + + * Power-up Request Interrupt Enable for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1 + + * Power-up Request Interrupt Enable Register. Writing a 1 to this location + * will unmask the interrupt. + * (OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U) + */ + PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET, + 0x00800000U, 0x00800000U); +/*##################################################################### */ + + /* + * Register : REQ_PWRUP_TRIG @ 0XFFD80120 + + * Power-up Request Trigger for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1 + + * Power-up Request Trigger Register. A write of one to this location will + * generate a power-up request to the PMU. + * (OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U) + */ + PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET, + 0x00800000U, 0x00800000U); +/*##################################################################### */ + + /* + * POLL ON PL POWER STATUS + */ + /* + * Register : REQ_PWRUP_STATUS @ 0XFFD80110 + + * Power-up Request Status for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL 1 + * (OFFSET, MASK, VALUE) (0XFFD80110, 0x00800000U ,0x00000000U) + */ + mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET, + 0x00800000U, 0x00000000U); + +/*##################################################################### */ + + + return 1; +} +unsigned long psu_afi_config(void) +{ + /* + * AFI RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * AF_FM0 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM0_RESET 0 + + * AF_FM1 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM1_RESET 0 + + * AF_FM2 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM2_RESET 0 + + * AF_FM3 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM3_RESET 0 + + * AF_FM4 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM4_RESET 0 + + * AF_FM5 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM5_RESET 0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00001F80U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00001F80U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * AFI FM 6 + * PSU_CRL_APB_RST_LPD_TOP_AFI_FM6_RESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00080000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00080000U, 0x00000000U); +/*##################################################################### */ + + /* + * AFIFM INTERFACE WIDTH + */ + /* + * Register : afi_fs @ 0XFF419000 + + * Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved + * PSU_LPD_SLCR_AFI_FS_DW_SS2_SEL 0x2 + + * afi fs SLCR control register. Do not change the bits durin + * (OFFSET, MASK, VALUE) (0XFF419000, 0x00000300U ,0x00000200U) + */ + PSU_Mask_Write(LPD_SLCR_AFI_FS_OFFSET, 0x00000300U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : AFIFM_RDCTRL @ 0XFD380000 + + * Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b + * 10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128-bit enabled + * PSU_AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH 0x0 + + * Read Channel Control Register + * (OFFSET, MASK, VALUE) (0XFD380000, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(AFIFM2_AFIFM_RDCTRL_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRCTRL @ 0XFD380014 + + * Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2' + * b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128-bit enabled + * PSU_AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH 0x0 + + * Write Channel Control Register + * (OFFSET, MASK, VALUE) (0XFD380014, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(AFIFM2_AFIFM_WRCTRL_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_ps_pl_reset_config_data(void) +{ + /* + * PS PL RESET SEQUENCE + */ + /* + * FABRIC RESET USING EMIO + */ + /* + * Register : MASK_DATA_5_MSW @ 0XFF0A002C + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW 0x8000 + + * Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A002C, 0xFFFF0000U ,0x80000000U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_5_MSW_OFFSET, + 0xFFFF0000U, 0x80000000U); +/*##################################################################### */ + + /* + * Register : DIRM_5 @ 0XFF0A0344 + + * Operation is the same as DIRM_0[DIRECTION_0] + * PSU_GPIO_DIRM_5_DIRECTION_5 0x80000000 + + * Direction mode (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DIRM_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + /* + * Register : OEN_5 @ 0XFF0A0348 + + * Operation is the same as OEN_0[OP_ENABLE_0] + * PSU_GPIO_OEN_5_OP_ENABLE_5 0x80000000 + + * Output enable (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_OEN_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + /* + * Register : DATA_5 @ 0XFF0A0054 + + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0x80000000 + + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + mask_delay(1); + +/*##################################################################### */ + + /* + * FABRIC RESET USING DATA_5 TOGGLE + */ + /* + * Register : DATA_5 @ 0XFF0A0054 + + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0X00000000 + + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + mask_delay(1); + +/*##################################################################### */ + + /* + * FABRIC RESET USING DATA_5 TOGGLE + */ + /* + * Register : DATA_5 @ 0XFF0A0054 + + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0x80000000 + + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + + return 1; +} + +unsigned long psu_ddr_phybringup_data(void) +{ + + + unsigned int regval = 0; + + unsigned int pll_retry = 10; + + unsigned int pll_locked = 0; + + + while ((pll_retry > 0) && (!pll_locked)) { + + Xil_Out32(0xFD080004, 0x00040010);/*PIR*/ + Xil_Out32(0xFD080004, 0x00040011);/*PIR*/ + + while ((Xil_In32(0xFD080030) & 0x1) != 1) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31;/*PGSR0*/ + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16;/*DX0GSR0*/ + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16 ; /*DX2GSR0*/ + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16;/*DX4GSR0*/ + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16;/*DX6GSR0*/ + pll_retry--; + } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | + (pll_retry << 16));/*GPR0*/ + if(!pll_locked) + return(0); + + Xil_Out32(0xFD080004U, 0x00040063U); + /* PHY BRINGUP SEQ */ + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + /* poll for PHY initialization to complete */ + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >>18); + if(regval != 0) { + return(0); + } + +/* Run Vref training in static read mode*/ + Xil_Out32(0xFD080200U, 0x100091C7U); + int cur_R006_tREFPRD; + + cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + + Xil_Out32(0xFD080004, 0x00060001); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while ((regval & 0x80004001) != 0x80004001) { + /*PUB_PGSR0*/ + regval = Xil_In32(0xFD080030); + } + +/* Vref training is complete*/ +/* Check if any training errors then exit*/ + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >>18); + if(regval != 0) { + return(0); + } + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); +/*Vref training is complete, disabling static read mode*/ + Xil_Out32(0xFD080200U, 0x800091C7U); + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + + + Xil_Out32(0xFD080004, 0x0000C001); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while ((regval & 0x80000C01) != 0x80000C01) { + /*PUB_PGSR0*/ + regval = Xil_In32(0xFD080030); + } + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + +return 1; +} + +/** + * CRL_APB Base Address + */ +#define CRL_APB_BASEADDR 0XFF5E0000U +#define CRL_APB_RST_LPD_IOU0 ((CRL_APB_BASEADDR) + 0X00000230U) +#define CRL_APB_RST_LPD_IOU1 ((CRL_APB_BASEADDR) + 0X00000234U) +#define CRL_APB_RST_LPD_IOU2 ((CRL_APB_BASEADDR) + 0X00000238U) +#define CRL_APB_RST_LPD_TOP ((CRL_APB_BASEADDR) + 0X0000023CU) +#define CRL_APB_IOU_SWITCH_CTRL ((CRL_APB_BASEADDR) + 0X0000009CU) + +/** + * CRF_APB Base Address + */ +#define CRF_APB_BASEADDR 0XFD1A0000U + +#define CRF_APB_RST_FPD_TOP ((CRF_APB_BASEADDR) + 0X00000100U) +#define CRF_APB_GPU_REF_CTRL ((CRF_APB_BASEADDR) + 0X00000084U) +#define CRF_APB_RST_DDR_SS ((CRF_APB_BASEADDR) + 0X00000108U) +#define PSU_MASK_POLL_TIME 1100000 + +/** + * * Register: CRF_APB_DPLL_CTRL + */ +#define CRF_APB_DPLL_CTRL ((CRF_APB_BASEADDR) + 0X0000002C) + + +#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_DPLL_CTRL_DIV2_WIDTH 1 + +#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_DPLL_CTRL_FBDIV_WIDTH 7 + +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_WIDTH 1 + +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_WIDTH 1 + +/** + * * Register: CRF_APB_DPLL_CFG + */ +#define CRF_APB_DPLL_CFG ((CRF_APB_BASEADDR) + 0X00000030) + +#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_DPLL_CFG_LOCK_DLY_WIDTH 7 + +#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_DPLL_CFG_LOCK_CNT_WIDTH 10 + +#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_DPLL_CFG_LFHF_WIDTH 2 + +#define CRF_APB_DPLL_CFG_CP_SHIFT 5 +#define CRF_APB_DPLL_CFG_CP_WIDTH 4 + +#define CRF_APB_DPLL_CFG_RES_SHIFT 0 +#define CRF_APB_DPLL_CFG_RES_WIDTH 4 + +/** + * Register: CRF_APB_PLL_STATUS + */ +#define CRF_APB_PLL_STATUS ((CRF_APB_BASEADDR) + 0X00000044) + + +static int mask_pollOnValue(u32 add, u32 mask, u32 value) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; + int i = 0; + + while ((*addr & mask) != value) { + if (i == PSU_MASK_POLL_TIME) + return 0; + i++; + } + return 1; +} + +static int mask_poll(u32 add, u32 mask) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; + int i = 0; + + while (!(*addr & mask)) { + if (i == PSU_MASK_POLL_TIME) + return 0; + i++; + } + return 1; +} + +static void mask_delay(u32 delay) +{ + usleep(delay); +} + +static u32 mask_read(u32 add, u32 mask) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; + u32 val = (*addr & mask); + return val; +} + +//Kishore -- ILL calibration code begins +//ILL calibration code begins +#define SERDES_L0_TM_PLL_DIG_33 0XFD402084 +#define SERDES_L1_TM_PLL_DIG_33 0XFD406084 +#define SERDES_L2_TM_PLL_DIG_33 0XFD40A084 +#define SERDES_L3_TM_PLL_DIG_33 0XFD40E084 + +#define SERDES_L0_TM_ANA_BYP_4 0XFD401010 +#define SERDES_L1_TM_ANA_BYP_4 0XFD405010 +#define SERDES_L2_TM_ANA_BYP_4 0XFD409010 +#define SERDES_L3_TM_ANA_BYP_4 0XFD40D010 + +#define SERDES_L0_TM_ANA_BYP_7 0XFD401018 +#define SERDES_L1_TM_ANA_BYP_7 0XFD405018 +#define SERDES_L2_TM_ANA_BYP_7 0XFD409018 +#define SERDES_L3_TM_ANA_BYP_7 0XFD40D018 + +#define SERDES_L0_TM_E_ILL7 0XFD40193C +#define SERDES_L1_TM_E_ILL7 0XFD40593C +#define SERDES_L2_TM_E_ILL7 0XFD40993C +#define SERDES_L3_TM_E_ILL7 0XFD40D93C + +#define SERDES_L0_TM_IQ_ILL7 0XFD401910 +#define SERDES_L1_TM_IQ_ILL7 0XFD405910 +#define SERDES_L2_TM_IQ_ILL7 0XFD409910 +#define SERDES_L3_TM_IQ_ILL7 0XFD40D910 + +#define SERDES_L0_TX_DIG_TM_61 0XFD4000F4 +#define SERDES_L1_TX_DIG_TM_61 0XFD4040F4 +#define SERDES_L2_TX_DIG_TM_61 0XFD4080F4 +#define SERDES_L3_TX_DIG_TM_61 0XFD40C0F4 + +#define SERDES_L0_TM_DIG_6 0XFD40106C +#define SERDES_L1_TM_DIG_6 0XFD40506C +#define SERDES_L2_TM_DIG_6 0XFD40906C +#define SERDES_L3_TM_DIG_6 0XFD40D06C + +#define SERDES_L0_TM_IQ_ILL1 0XFD4018F8 +#define SERDES_L0_TM_IQ_ILL2 0XFD4018FC +#define SERDES_L0_TM_ILL11 0XFD40198C +#define SERDES_L0_TM_ILL12 0XFD401990 +#define SERDES_L0_TM_E_ILL1 0XFD401924 +#define SERDES_L0_TM_E_ILL2 0XFD401928 +#define SERDES_L0_TM_IQ_ILL3 0XFD401900 +#define SERDES_L0_TM_E_ILL3 0XFD40192C +#define SERDES_L0_TM_ILL8 0XFD401980 +#define SERDES_L0_TM_IQ_ILL8 0XFD401914 +#define SERDES_L0_TM_IQ_ILL9 0XFD401918 +#define SERDES_L0_TM_E_ILL8 0XFD401940 +#define SERDES_L0_TM_E_ILL9 0XFD401944 +#define SERDES_L0_TM_ILL13 0XFD401994 +#define SERDES_L1_TM_MISC2 0XFD40589C +#define SERDES_L1_TM_IQ_ILL1 0XFD4058F8 +#define SERDES_L1_TM_IQ_ILL2 0XFD4058FC +#define SERDES_L1_TM_ILL11 0XFD40598C +#define SERDES_L1_TM_ILL12 0XFD405990 +#define SERDES_L1_TM_E_ILL1 0XFD405924 +#define SERDES_L1_TM_E_ILL2 0XFD405928 +#define SERDES_L1_TM_IQ_ILL3 0XFD405900 +#define SERDES_L1_TM_E_ILL3 0XFD40592C +#define SERDES_L1_TM_ILL8 0XFD405980 +#define SERDES_L1_TM_IQ_ILL8 0XFD405914 +#define SERDES_L1_TM_IQ_ILL9 0XFD405918 +#define SERDES_L1_TM_E_ILL8 0XFD405940 +#define SERDES_L1_TM_E_ILL9 0XFD405944 +#define SERDES_L1_TM_ILL13 0XFD405994 +#define SERDES_L2_TM_MISC2 0XFD40989C +#define SERDES_L2_TM_IQ_ILL1 0XFD4098F8 +#define SERDES_L2_TM_IQ_ILL2 0XFD4098FC +#define SERDES_L2_TM_ILL11 0XFD40998C +#define SERDES_L2_TM_ILL12 0XFD409990 +#define SERDES_L2_TM_E_ILL1 0XFD409924 +#define SERDES_L2_TM_E_ILL2 0XFD409928 +#define SERDES_L2_TM_IQ_ILL3 0XFD409900 +#define SERDES_L2_TM_E_ILL3 0XFD40992C +#define SERDES_L2_TM_ILL8 0XFD409980 +#define SERDES_L2_TM_IQ_ILL8 0XFD409914 +#define SERDES_L2_TM_IQ_ILL9 0XFD409918 +#define SERDES_L2_TM_E_ILL8 0XFD409940 +#define SERDES_L2_TM_E_ILL9 0XFD409944 +#define SERDES_L2_TM_ILL13 0XFD409994 +#define SERDES_L3_TM_MISC2 0XFD40D89C +#define SERDES_L3_TM_IQ_ILL1 0XFD40D8F8 +#define SERDES_L3_TM_IQ_ILL2 0XFD40D8FC +#define SERDES_L3_TM_ILL11 0XFD40D98C +#define SERDES_L3_TM_ILL12 0XFD40D990 +#define SERDES_L3_TM_E_ILL1 0XFD40D924 +#define SERDES_L3_TM_E_ILL2 0XFD40D928 +#define SERDES_L3_TM_IQ_ILL3 0XFD40D900 +#define SERDES_L3_TM_E_ILL3 0XFD40D92C +#define SERDES_L3_TM_ILL8 0XFD40D980 +#define SERDES_L3_TM_IQ_ILL8 0XFD40D914 +#define SERDES_L3_TM_IQ_ILL9 0XFD40D918 +#define SERDES_L3_TM_E_ILL8 0XFD40D940 +#define SERDES_L3_TM_E_ILL9 0XFD40D944 +#define SERDES_L3_TM_ILL13 0XFD40D994 +#undef SERDES_UPHY_SPARE0 +#define SERDES_UPHY_SPARE0 0XFD410098 +#undef SERDES_UPHY_SPARE1 +#define SERDES_UPHY_SPARE1 0XFD41009C +#undef SERDES_UPHY_SPARE2 +#define SERDES_UPHY_SPARE2 0XFD4100A0 +#undef SERDES_UPHY_SPARE3 +#define SERDES_UPHY_SPARE3 0XFD4100A4 + +#define SERDES_L0_PLL_FBDIV_FRAC_3_MSB 0xFD402360 +#define SERDES_L1_PLL_FBDIV_FRAC_3_MSB 0xFD406360 +#define SERDES_L2_PLL_FBDIV_FRAC_3_MSB 0xFD40A360 +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB 0xFD40E360 + +#define SERDES_L0_PLL_STATUS_READ_1 0XFD4023E4 +#define SERDES_L0_TM_MISC_ST_0 0XFD401AC8 +#define SERDES_L1_PLL_STATUS_READ_1 0XFD4063E4 +#define SERDES_L1_TM_MISC_ST_0 0XFD405AC8 +#define SERDES_L2_PLL_STATUS_READ_1 0XFD40A3E4 +#define SERDES_L2_TM_MISC_ST_0 0XFD409AC8 +#define SERDES_L3_PLL_STATUS_READ_1 0XFD40E3E4 +#define SERDES_L3_TM_MISC_ST_0 0XFD40DAC8 + +#define SERDES_L0_BIST_CTRL_1 0xFD403004 +#define SERDES_L0_BIST_CTRL_2 0xFD403008 +#define SERDES_L0_BIST_RUN_LEN_L 0xFD40300C +#define SERDES_L0_BIST_ERR_INJ_POINT_L 0xFD403010 +#define SERDES_L0_BIST_RUNLEN_ERR_INJ_H 0xFD403014 +#define SERDES_L0_BIST_IDLE_TIME 0xFD403018 +#define SERDES_L0_BIST_MARKER_L 0xFD40301C +#define SERDES_L0_BIST_IDLE_CHAR_L 0xFD403020 +#define SERDES_L0_BIST_MARKER_IDLE_H 0xFD403024 +#define SERDES_L0_BIST_LOW_PULSE_TIME 0xFD403028 +#define SERDES_L0_BIST_TOTAL_PULSE_TIME 0xFD40302C +#define SERDES_L0_BIST_TEST_PAT_1 0xFD403030 +#define SERDES_L0_BIST_TEST_PAT_2 0xFD403034 +#define SERDES_L0_BIST_TEST_PAT_3 0xFD403038 +#define SERDES_L0_BIST_TEST_PAT_4 0xFD40303C +#define SERDES_L0_BIST_TEST_PAT_MSBS 0xFD403040 +#define SERDES_L0_BIST_PKT_NUM 0xFD403044 +#define SERDES_L0_BIST_FRM_IDLE_TIME 0xFD403048 +#define SERDES_L0_BIST_PKT_CTR_L 0xFD40304C +#define SERDES_L0_BIST_PKT_CTR_H 0xFD403050 +#define SERDES_L0_BIST_ERR_CTR_L 0xFD403054 +#define SERDES_L0_BIST_ERR_CTR_H 0xFD403058 +#define SERDES_L0_BIST_FILLER_OUT 0xFD403068 +#define SERDES_L0_BIST_FORCE_MK_RST 0xFD40306C + +#define SERDES_L1_BIST_CTRL_1 0xFD407004 +#define SERDES_L1_BIST_CTRL_2 0xFD407008 +#define SERDES_L1_BIST_RUN_LEN_L 0xFD40700C +#define SERDES_L1_BIST_ERR_INJ_POINT_L 0xFD407010 +#define SERDES_L1_BIST_RUNLEN_ERR_INJ_H 0xFD407014 +#define SERDES_L1_BIST_IDLE_TIME 0xFD407018 +#define SERDES_L1_BIST_MARKER_L 0xFD40701C +#define SERDES_L1_BIST_IDLE_CHAR_L 0xFD407020 +#define SERDES_L1_BIST_MARKER_IDLE_H 0xFD407024 +#define SERDES_L1_BIST_LOW_PULSE_TIME 0xFD407028 +#define SERDES_L1_BIST_TOTAL_PULSE_TIME 0xFD40702C +#define SERDES_L1_BIST_TEST_PAT_1 0xFD407030 +#define SERDES_L1_BIST_TEST_PAT_2 0xFD407034 +#define SERDES_L1_BIST_TEST_PAT_3 0xFD407038 +#define SERDES_L1_BIST_TEST_PAT_4 0xFD40703C +#define SERDES_L1_BIST_TEST_PAT_MSBS 0xFD407040 +#define SERDES_L1_BIST_PKT_NUM 0xFD407044 +#define SERDES_L1_BIST_FRM_IDLE_TIME 0xFD407048 +#define SERDES_L1_BIST_PKT_CTR_L 0xFD40704C +#define SERDES_L1_BIST_PKT_CTR_H 0xFD407050 +#define SERDES_L1_BIST_ERR_CTR_L 0xFD407054 +#define SERDES_L1_BIST_ERR_CTR_H 0xFD407058 +#define SERDES_L1_BIST_FILLER_OUT 0xFD407068 +#define SERDES_L1_BIST_FORCE_MK_RST 0xFD40706C + +#define SERDES_L2_BIST_CTRL_1 0xFD40B004 +#define SERDES_L2_BIST_CTRL_2 0xFD40B008 +#define SERDES_L2_BIST_RUN_LEN_L 0xFD40B00C +#define SERDES_L2_BIST_ERR_INJ_POINT_L 0xFD40B010 +#define SERDES_L2_BIST_RUNLEN_ERR_INJ_H 0xFD40B014 +#define SERDES_L2_BIST_IDLE_TIME 0xFD40B018 +#define SERDES_L2_BIST_MARKER_L 0xFD40B01C +#define SERDES_L2_BIST_IDLE_CHAR_L 0xFD40B020 +#define SERDES_L2_BIST_MARKER_IDLE_H 0xFD40B024 +#define SERDES_L2_BIST_LOW_PULSE_TIME 0xFD40B028 +#define SERDES_L2_BIST_TOTAL_PULSE_TIME 0xFD40B02C +#define SERDES_L2_BIST_TEST_PAT_1 0xFD40B030 +#define SERDES_L2_BIST_TEST_PAT_2 0xFD40B034 +#define SERDES_L2_BIST_TEST_PAT_3 0xFD40B038 +#define SERDES_L2_BIST_TEST_PAT_4 0xFD40B03C +#define SERDES_L2_BIST_TEST_PAT_MSBS 0xFD40B040 +#define SERDES_L2_BIST_PKT_NUM 0xFD40B044 +#define SERDES_L2_BIST_FRM_IDLE_TIME 0xFD40B048 +#define SERDES_L2_BIST_PKT_CTR_L 0xFD40B04C +#define SERDES_L2_BIST_PKT_CTR_H 0xFD40B050 +#define SERDES_L2_BIST_ERR_CTR_L 0xFD40B054 +#define SERDES_L2_BIST_ERR_CTR_H 0xFD40B058 +#define SERDES_L2_BIST_FILLER_OUT 0xFD40B068 +#define SERDES_L2_BIST_FORCE_MK_RST 0xFD40B06C + +#define SERDES_L3_BIST_CTRL_1 0xFD40F004 +#define SERDES_L3_BIST_CTRL_2 0xFD40F008 +#define SERDES_L3_BIST_RUN_LEN_L 0xFD40F00C +#define SERDES_L3_BIST_ERR_INJ_POINT_L 0xFD40F010 +#define SERDES_L3_BIST_RUNLEN_ERR_INJ_H 0xFD40F014 +#define SERDES_L3_BIST_IDLE_TIME 0xFD40F018 +#define SERDES_L3_BIST_MARKER_L 0xFD40F01C +#define SERDES_L3_BIST_IDLE_CHAR_L 0xFD40F020 +#define SERDES_L3_BIST_MARKER_IDLE_H 0xFD40F024 +#define SERDES_L3_BIST_LOW_PULSE_TIME 0xFD40F028 +#define SERDES_L3_BIST_TOTAL_PULSE_TIME 0xFD40F02C +#define SERDES_L3_BIST_TEST_PAT_1 0xFD40F030 +#define SERDES_L3_BIST_TEST_PAT_2 0xFD40F034 +#define SERDES_L3_BIST_TEST_PAT_3 0xFD40F038 +#define SERDES_L3_BIST_TEST_PAT_4 0xFD40F03C +#define SERDES_L3_BIST_TEST_PAT_MSBS 0xFD40F040 +#define SERDES_L3_BIST_PKT_NUM 0xFD40F044 +#define SERDES_L3_BIST_FRM_IDLE_TIME 0xFD40F048 +#define SERDES_L3_BIST_PKT_CTR_L 0xFD40F04C +#define SERDES_L3_BIST_PKT_CTR_H 0xFD40F050 +#define SERDES_L3_BIST_ERR_CTR_L 0xFD40F054 +#define SERDES_L3_BIST_ERR_CTR_H 0xFD40F058 +#define SERDES_L3_BIST_FILLER_OUT 0xFD40F068 +#define SERDES_L3_BIST_FORCE_MK_RST 0xFD40F06C + +#define SERDES_TX_PROT_BUS_WIDTH 0xFD410040 +#define SERDES_RX_PROT_BUS_WIDTH 0xFD410044 +#define SERDES_LPBK_CTRL0 0xFD410038 +#define SERDES_LPBK_CTRL1 0xFD41003C +#define SERDES_L0_TM_DIG_22 0xFD4010AC +#define SERDES_L1_TM_DIG_22 0xFD4050AC +#define SERDES_L2_TM_DIG_22 0xFD4090AC +#define SERDES_L3_TM_DIG_22 0xFD40D0AC +#define SERDES_L0_DATA_BUS_WID 0xFD403060 +#define SERDES_L1_DATA_BUS_WID 0xFD407060 +#define SERDES_L2_DATA_BUS_WID 0xFD40B060 +#define SERDES_L3_DATA_BUS_WID 0xFD40F060 +#define SERDES_L0_TX_ANA_TM_3 0XFD40000C +#define SERDES_L1_TX_ANA_TM_3 0XFD40400C +#define SERDES_L2_TX_ANA_TM_3 0XFD40800C +#define SERDES_L3_TX_ANA_TM_3 0XFD40C00C + +#undef SERDES_PLL_REF_SEL0_OFFSET +#define SERDES_PLL_REF_SEL0_OFFSET 0xFD410000 +#undef SERDES_PLL_REF_SEL1_OFFSET +#define SERDES_PLL_REF_SEL1_OFFSET 0xFD410004 +#undef SERDES_PLL_REF_SEL2_OFFSET +#define SERDES_PLL_REF_SEL2_OFFSET 0xFD410008 +#undef SERDES_PLL_REF_SEL3_OFFSET +#define SERDES_PLL_REF_SEL3_OFFSET 0xFD41000C +#undef SERDES_ICM_CFG0_OFFSET +#define SERDES_ICM_CFG0_OFFSET 0xFD410010 +#undef SERDES_ICM_CFG1_OFFSET +#define SERDES_ICM_CFG1_OFFSET 0xFD410014 + +static int serdes_rst_seq (u32 lane3_protocol, u32 lane3_rate, u32 lane2_protocol, u32 lane2_rate, u32 lane1_protocol, u32 lane1_rate, u32 lane0_protocol, u32 lane0_rate) +{ + Xil_Out32(SERDES_UPHY_SPARE0, 0x00000000); + Xil_Out32(SERDES_L0_TM_ANA_BYP_4, 0x00000040); + Xil_Out32(SERDES_L1_TM_ANA_BYP_4, 0x00000040); + Xil_Out32(SERDES_L2_TM_ANA_BYP_4, 0x00000040); + Xil_Out32(SERDES_L3_TM_ANA_BYP_4, 0x00000040); + Xil_Out32(SERDES_L0_TM_PLL_DIG_33, 0x00000080); + Xil_Out32(SERDES_L1_TM_PLL_DIG_33, 0x00000080); + Xil_Out32(SERDES_L2_TM_PLL_DIG_33, 0x00000080); + Xil_Out32(SERDES_L3_TM_PLL_DIG_33, 0x00000080); + Xil_Out32(SERDES_UPHY_SPARE0, 0x00000004); + mask_delay(50); + if (lane0_rate == 1) Xil_Out32(SERDES_UPHY_SPARE0, 0x0000000E); + Xil_Out32(SERDES_UPHY_SPARE0, 0x00000006); + if (lane0_rate == 1) { + Xil_Out32(SERDES_L0_TX_ANA_TM_3, 0x00000004); + Xil_Out32(SERDES_L1_TX_ANA_TM_3, 0x00000004); + Xil_Out32(SERDES_L2_TX_ANA_TM_3, 0x00000004); + Xil_Out32(SERDES_L3_TX_ANA_TM_3, 0x00000004); + Xil_Out32(SERDES_UPHY_SPARE0, 0x00000007); + mask_delay (400); + Xil_Out32(SERDES_L0_TX_ANA_TM_3, 0x0000000C); + Xil_Out32(SERDES_L1_TX_ANA_TM_3, 0x0000000C); + Xil_Out32(SERDES_L2_TX_ANA_TM_3, 0x0000000C); + Xil_Out32(SERDES_L3_TX_ANA_TM_3, 0x0000000C); + mask_delay (15); + Xil_Out32(SERDES_UPHY_SPARE0, 0x0000000F); + mask_delay (100); + } + if (lane0_protocol != 0) mask_poll(SERDES_L0_PLL_STATUS_READ_1, 0x00000010U); + if (lane1_protocol != 0) mask_poll(SERDES_L1_PLL_STATUS_READ_1, 0x00000010U); + if (lane2_protocol != 0) mask_poll(SERDES_L2_PLL_STATUS_READ_1, 0x00000010U); + if (lane3_protocol != 0) mask_poll(SERDES_L3_PLL_STATUS_READ_1, 0x00000010U); + mask_delay(50); + Xil_Out32(SERDES_L0_TM_ANA_BYP_4, 0x000000C0); + Xil_Out32(SERDES_L1_TM_ANA_BYP_4, 0x000000C0); + Xil_Out32(SERDES_L2_TM_ANA_BYP_4, 0x000000C0); + Xil_Out32(SERDES_L3_TM_ANA_BYP_4, 0x000000C0); + Xil_Out32(SERDES_L0_TM_ANA_BYP_4, 0x00000080); + Xil_Out32(SERDES_L1_TM_ANA_BYP_4, 0x00000080); + Xil_Out32(SERDES_L2_TM_ANA_BYP_4, 0x00000080); + Xil_Out32(SERDES_L3_TM_ANA_BYP_4, 0x00000080); + + Xil_Out32(SERDES_L0_TM_PLL_DIG_33 , 0x000000C0); + Xil_Out32(SERDES_L1_TM_PLL_DIG_33 , 0x000000C0); + Xil_Out32(SERDES_L2_TM_PLL_DIG_33 , 0x000000C0); + Xil_Out32(SERDES_L3_TM_PLL_DIG_33 , 0x000000C0); + mask_delay(50); + Xil_Out32(SERDES_L0_TM_PLL_DIG_33 , 0x00000080); + Xil_Out32(SERDES_L1_TM_PLL_DIG_33 , 0x00000080); + Xil_Out32(SERDES_L2_TM_PLL_DIG_33 , 0x00000080); + Xil_Out32(SERDES_L3_TM_PLL_DIG_33 , 0x00000080); + mask_delay(50); + Xil_Out32(SERDES_L0_TM_ANA_BYP_4, 0x00000000); + Xil_Out32(SERDES_L1_TM_ANA_BYP_4, 0x00000000); + Xil_Out32(SERDES_L2_TM_ANA_BYP_4, 0x00000000); + Xil_Out32(SERDES_L3_TM_ANA_BYP_4, 0x00000000); + Xil_Out32(SERDES_L0_TM_PLL_DIG_33 , 0x00000000); + Xil_Out32(SERDES_L1_TM_PLL_DIG_33 , 0x00000000); + Xil_Out32(SERDES_L2_TM_PLL_DIG_33 , 0x00000000); + Xil_Out32(SERDES_L3_TM_PLL_DIG_33 , 0x00000000); + mask_delay(500); + return 1; +} + + +static int serdes_bist_static_settings(u32 lane_active) +{ + if (lane_active == 0) + { + Xil_Out32(SERDES_L0_BIST_CTRL_1, (Xil_In32(SERDES_L0_BIST_CTRL_1) & 0xFFFFFF1F)); + Xil_Out32(SERDES_L0_BIST_FILLER_OUT, 0x1 ); + Xil_Out32(SERDES_L0_BIST_FORCE_MK_RST, 0x1 ); + Xil_Out32(SERDES_L0_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L0_BIST_CTRL_2, 0x0); + Xil_Out32(SERDES_L0_BIST_RUN_LEN_L, 0xF4); + Xil_Out32(SERDES_L0_BIST_ERR_INJ_POINT_L, 0x0); + Xil_Out32(SERDES_L0_BIST_RUNLEN_ERR_INJ_H, 0x0); + Xil_Out32(SERDES_L0_BIST_IDLE_TIME,0x00); + Xil_Out32(SERDES_L0_BIST_MARKER_L, 0xFB); + Xil_Out32(SERDES_L0_BIST_IDLE_CHAR_L, 0xFF); + Xil_Out32(SERDES_L0_BIST_MARKER_IDLE_H, 0x0); + Xil_Out32(SERDES_L0_BIST_LOW_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L0_BIST_TOTAL_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_1, 0x4A); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_2, 0x4A); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_3, 0x4A); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_4, 0x4A); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_MSBS, 0x0); + Xil_Out32(SERDES_L0_BIST_PKT_NUM, 0x14); + Xil_Out32(SERDES_L0_BIST_FRM_IDLE_TIME,0x02); + Xil_Out32(SERDES_L0_BIST_CTRL_1, (Xil_In32(SERDES_L0_BIST_CTRL_1) & 0xFFFFFF1F)); + } + if (lane_active == 1) + { + Xil_Out32(SERDES_L1_BIST_CTRL_1, (Xil_In32(SERDES_L1_BIST_CTRL_1) & 0xFFFFFF1F)); + Xil_Out32(SERDES_L1_BIST_FILLER_OUT, 0x1 ); + Xil_Out32(SERDES_L1_BIST_FORCE_MK_RST, 0x1 ); + Xil_Out32(SERDES_L1_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L1_BIST_CTRL_2, 0x0); + Xil_Out32(SERDES_L1_BIST_RUN_LEN_L, 0xF4); + Xil_Out32(SERDES_L1_BIST_ERR_INJ_POINT_L, 0x0); + Xil_Out32(SERDES_L1_BIST_RUNLEN_ERR_INJ_H, 0x0); + Xil_Out32(SERDES_L1_BIST_IDLE_TIME,0x00); + Xil_Out32(SERDES_L1_BIST_MARKER_L, 0xFB); + Xil_Out32(SERDES_L1_BIST_IDLE_CHAR_L, 0xFF); + Xil_Out32(SERDES_L1_BIST_MARKER_IDLE_H, 0x0); + Xil_Out32(SERDES_L1_BIST_LOW_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L1_BIST_TOTAL_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_1, 0x4A); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_2, 0x4A); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_3, 0x4A); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_4, 0x4A); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_MSBS, 0x0); + Xil_Out32(SERDES_L1_BIST_PKT_NUM, 0x14); + Xil_Out32(SERDES_L1_BIST_FRM_IDLE_TIME,0x02); + Xil_Out32(SERDES_L1_BIST_CTRL_1, (Xil_In32(SERDES_L1_BIST_CTRL_1) & 0xFFFFFF1F)); + } + + if (lane_active == 2) + { + Xil_Out32(SERDES_L2_BIST_CTRL_1, (Xil_In32(SERDES_L2_BIST_CTRL_1) & 0xFFFFFF1F)); + Xil_Out32(SERDES_L2_BIST_FILLER_OUT, 0x1 ); + Xil_Out32(SERDES_L2_BIST_FORCE_MK_RST, 0x1 ); + Xil_Out32(SERDES_L2_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L2_BIST_CTRL_2, 0x0); + Xil_Out32(SERDES_L2_BIST_RUN_LEN_L, 0xF4); + Xil_Out32(SERDES_L2_BIST_ERR_INJ_POINT_L, 0x0); + Xil_Out32(SERDES_L2_BIST_RUNLEN_ERR_INJ_H, 0x0); + Xil_Out32(SERDES_L2_BIST_IDLE_TIME,0x00); + Xil_Out32(SERDES_L2_BIST_MARKER_L, 0xFB); + Xil_Out32(SERDES_L2_BIST_IDLE_CHAR_L, 0xFF); + Xil_Out32(SERDES_L2_BIST_MARKER_IDLE_H, 0x0); + Xil_Out32(SERDES_L2_BIST_LOW_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L2_BIST_TOTAL_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_1, 0x4A); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_2, 0x4A); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_3, 0x4A); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_4, 0x4A); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_MSBS, 0x0); + Xil_Out32(SERDES_L2_BIST_PKT_NUM, 0x14); + Xil_Out32(SERDES_L2_BIST_FRM_IDLE_TIME,0x02); + Xil_Out32(SERDES_L2_BIST_CTRL_1, (Xil_In32(SERDES_L2_BIST_CTRL_1) & 0xFFFFFF1F)); + } + + if (lane_active == 3) + { + Xil_Out32(SERDES_L3_BIST_CTRL_1, (Xil_In32(SERDES_L3_BIST_CTRL_1) & 0xFFFFFF1F)); + Xil_Out32(SERDES_L3_BIST_FILLER_OUT, 0x1 ); + Xil_Out32(SERDES_L3_BIST_FORCE_MK_RST, 0x1 ); + Xil_Out32(SERDES_L3_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L3_BIST_CTRL_2, 0x0); + Xil_Out32(SERDES_L3_BIST_RUN_LEN_L, 0xF4); + Xil_Out32(SERDES_L3_BIST_ERR_INJ_POINT_L, 0x0); + Xil_Out32(SERDES_L3_BIST_RUNLEN_ERR_INJ_H, 0x0); + Xil_Out32(SERDES_L3_BIST_IDLE_TIME,0x00); + Xil_Out32(SERDES_L3_BIST_MARKER_L, 0xFB); + Xil_Out32(SERDES_L3_BIST_IDLE_CHAR_L, 0xFF); + Xil_Out32(SERDES_L3_BIST_MARKER_IDLE_H, 0x0); + Xil_Out32(SERDES_L3_BIST_LOW_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L3_BIST_TOTAL_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_1, 0x4A); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_2, 0x4A); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_3, 0x4A); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_4, 0x4A); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_MSBS, 0x0); + Xil_Out32(SERDES_L3_BIST_PKT_NUM, 0x14); + Xil_Out32(SERDES_L3_BIST_FRM_IDLE_TIME,0x02); + Xil_Out32(SERDES_L3_BIST_CTRL_1, (Xil_In32(SERDES_L3_BIST_CTRL_1) & 0xFFFFFF1F)); + } + return (1); +} + +static int serdes_bist_run(u32 lane_active) +{ + if (lane_active == 0) { + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x00000003U, 0x00000000U); + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x00000003U, 0x00000000U); + PSU_Mask_Write(SERDES_LPBK_CTRL0, 0x00000007U, 0x00000001U); + Xil_Out32(SERDES_L0_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L0_BIST_CTRL_1,(Xil_In32(SERDES_L0_BIST_CTRL_1) | 0x1)); + } + if (lane_active == 1) { + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x0000000CU, 0x00000000U); + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x0000000CU, 0x00000000U); + PSU_Mask_Write(SERDES_LPBK_CTRL0, 0x00000070U, 0x00000010U); + Xil_Out32(SERDES_L1_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L1_BIST_CTRL_1,(Xil_In32(SERDES_L1_BIST_CTRL_1) | 0x1)); + } + if (lane_active == 2) { + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x00000030U, 0x00000000U); + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x00000030U, 0x00000000U); + PSU_Mask_Write(SERDES_LPBK_CTRL1, 0x00000007U, 0x00000001U); + Xil_Out32(SERDES_L2_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L2_BIST_CTRL_1,(Xil_In32(SERDES_L2_BIST_CTRL_1) | 0x1)); + } + if (lane_active == 3) { + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x000000C0U, 0x00000000U); + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x000000C0U, 0x00000000U); + PSU_Mask_Write(SERDES_LPBK_CTRL1, 0x00000070U, 0x00000010U); + Xil_Out32(SERDES_L3_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L3_BIST_CTRL_1,(Xil_In32(SERDES_L3_BIST_CTRL_1) | 0x1)); + } + mask_delay(100); + return (1); +} + +static int serdes_bist_result(u32 lane_active) +{ + u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0; + if (lane_active == 0) { + pkt_cnt_l0 = Xil_In32(SERDES_L0_BIST_PKT_CTR_L); + pkt_cnt_h0 = Xil_In32(SERDES_L0_BIST_PKT_CTR_H); + err_cnt_l0 = Xil_In32(SERDES_L0_BIST_ERR_CTR_L); + err_cnt_h0 = Xil_In32(SERDES_L0_BIST_ERR_CTR_H); + } + if (lane_active == 1) { + pkt_cnt_l0 = Xil_In32(SERDES_L1_BIST_PKT_CTR_L); + pkt_cnt_h0 = Xil_In32(SERDES_L1_BIST_PKT_CTR_H); + err_cnt_l0 = Xil_In32(SERDES_L1_BIST_ERR_CTR_L); + err_cnt_h0 = Xil_In32(SERDES_L1_BIST_ERR_CTR_H); + } + if (lane_active == 2) { + pkt_cnt_l0 = Xil_In32(SERDES_L2_BIST_PKT_CTR_L); + pkt_cnt_h0 = Xil_In32(SERDES_L2_BIST_PKT_CTR_H); + err_cnt_l0 = Xil_In32(SERDES_L2_BIST_ERR_CTR_L); + err_cnt_h0 = Xil_In32(SERDES_L2_BIST_ERR_CTR_H); + } + if (lane_active == 3) { + pkt_cnt_l0 = Xil_In32(SERDES_L3_BIST_PKT_CTR_L); + pkt_cnt_h0 = Xil_In32(SERDES_L3_BIST_PKT_CTR_H); + err_cnt_l0 = Xil_In32(SERDES_L3_BIST_ERR_CTR_L); + err_cnt_h0 = Xil_In32(SERDES_L3_BIST_ERR_CTR_H); + } + if (lane_active == 0) Xil_Out32(SERDES_L0_BIST_CTRL_1,0x0); + if (lane_active == 1) Xil_Out32(SERDES_L1_BIST_CTRL_1,0x0); + if (lane_active == 2) Xil_Out32(SERDES_L2_BIST_CTRL_1,0x0); + if (lane_active == 3) Xil_Out32(SERDES_L3_BIST_CTRL_1,0x0); + if((err_cnt_l0 > 0) || (err_cnt_h0 > 0) || ((pkt_cnt_l0 == 0) && (pkt_cnt_h0 == 0))) + return (0); + return (1); +} + +static int serdes_illcalib_pcie_gen1 (u32 lane3_protocol, u32 lane3_rate, u32 lane2_protocol, u32 lane2_rate, u32 lane1_protocol, u32 lane1_rate, u32 lane0_protocol, u32 lane0_rate, u32 gen2_calib) +{ + u64 tempbistresult; + u32 currbistresult[4]; + u32 prevbistresult[4]; + u32 itercount = 0; + u32 ill12_val[4], ill1_val[4]; + u32 loop=0; + u32 iterresult[8]; + u32 meancount[4]; + u32 bistpasscount[4]; + u32 meancountalt[4]; + u32 meancountalt_bistpasscount[4]; + u32 lane0_active; + u32 lane1_active; + u32 lane2_active; + u32 lane3_active; + + lane0_active = (lane0_protocol == 1); + lane1_active = (lane1_protocol == 1); + lane2_active = (lane2_protocol == 1); + lane3_active = (lane3_protocol == 1); + for (loop=0; loop<=3; loop++) + { + iterresult[loop] = 0; + iterresult[loop+4] = 0; + meancountalt[loop] = 0; + meancountalt_bistpasscount[loop]=0; + meancount[loop] = 0; + prevbistresult[loop] = 0; + bistpasscount[loop] = 0; + } + itercount = 0; + if (lane0_active) serdes_bist_static_settings(0); + if (lane1_active) serdes_bist_static_settings(1); + if (lane2_active) serdes_bist_static_settings(2); + if (lane3_active) serdes_bist_static_settings(3); + do + { + if (gen2_calib != 1) + { + if (lane0_active == 1) ill1_val[0] = ((0x04 + itercount*8) % 0x100); + if (lane0_active == 1) ill12_val[0] = ((0x04 + itercount*8) >= 0x100) ? 0x10 : 0x00; + if (lane1_active == 1) ill1_val[1] = ((0x04 + itercount*8) % 0x100); + if (lane1_active == 1) ill12_val[1] = ((0x04 + itercount*8) >= 0x100) ? 0x10 : 0x00; + if (lane2_active == 1) ill1_val[2] = ((0x04 + itercount*8) % 0x100); + if (lane2_active == 1) ill12_val[2] = ((0x04 + itercount*8) >= 0x100) ? 0x10 : 0x00; + if (lane3_active == 1) ill1_val[3] = ((0x04 + itercount*8) % 0x100); + if (lane3_active == 1) ill12_val[3] = ((0x04 + itercount*8) >= 0x100) ? 0x10 : 0x00; + + if (lane0_active == 1) Xil_Out32(SERDES_L0_TM_E_ILL1,ill1_val[0]); + if (lane0_active == 1) PSU_Mask_Write(SERDES_L0_TM_ILL12, 0x000000F0U, ill12_val[0]); + if (lane1_active == 1) Xil_Out32(SERDES_L1_TM_E_ILL1,ill1_val[1]); + if (lane1_active == 1) PSU_Mask_Write(SERDES_L1_TM_ILL12, 0x000000F0U, ill12_val[1]); + if (lane2_active == 1) Xil_Out32(SERDES_L2_TM_E_ILL1,ill1_val[2]); + if (lane2_active == 1) PSU_Mask_Write(SERDES_L2_TM_ILL12, 0x000000F0U, ill12_val[2]); + if (lane3_active == 1) Xil_Out32(SERDES_L3_TM_E_ILL1,ill1_val[3]); + if (lane3_active == 1) PSU_Mask_Write(SERDES_L3_TM_ILL12, 0x000000F0U, ill12_val[3]); + } + if (gen2_calib == 1) + { + if (lane0_active == 1) ill1_val[0] = ((0x104 + itercount*8) % 0x100); + if (lane0_active == 1) ill12_val[0] = ((0x104 + itercount*8) >= 0x200) ? 0x02 : 0x01; + if (lane1_active == 1) ill1_val[1] = ((0x104 + itercount*8) % 0x100); + if (lane1_active == 1) ill12_val[1] = ((0x104 + itercount*8) >= 0x200) ? 0x02 : 0x01; + if (lane2_active == 1) ill1_val[2] = ((0x104 + itercount*8) % 0x100); + if (lane2_active == 1) ill12_val[2] = ((0x104 + itercount*8) >= 0x200) ? 0x02 : 0x01; + if (lane3_active == 1) ill1_val[3] = ((0x104 + itercount*8) % 0x100); + if (lane3_active == 1) ill12_val[3] = ((0x104 + itercount*8) >= 0x200) ? 0x02 : 0x01; + + if (lane0_active == 1) Xil_Out32(SERDES_L0_TM_E_ILL2,ill1_val[0]); + if (lane0_active == 1) PSU_Mask_Write(SERDES_L0_TM_ILL12, 0x0000000FU, ill12_val[0]); + if (lane1_active == 1) Xil_Out32(SERDES_L1_TM_E_ILL2,ill1_val[1]); + if (lane1_active == 1) PSU_Mask_Write(SERDES_L1_TM_ILL12, 0x0000000FU, ill12_val[1]); + if (lane2_active == 1) Xil_Out32(SERDES_L2_TM_E_ILL2,ill1_val[2]); + if (lane2_active == 1) PSU_Mask_Write(SERDES_L2_TM_ILL12, 0x0000000FU, ill12_val[2]); + if (lane3_active == 1) Xil_Out32(SERDES_L3_TM_E_ILL2,ill1_val[3]); + if (lane3_active == 1) PSU_Mask_Write(SERDES_L3_TM_ILL12, 0x0000000FU, ill12_val[3]); + } + + if (lane0_active == 1) PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_7, 0x00000030U, 0x00000010U); + if (lane1_active == 1) PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_7, 0x00000030U, 0x00000010U); + if (lane2_active == 1) PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_7, 0x00000030U, 0x00000010U); + if (lane3_active == 1) PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_7, 0x00000030U, 0x00000010U); + if (lane0_active == 1) currbistresult[0] = 0; + if (lane1_active == 1) currbistresult[1] = 0; + if (lane2_active == 1) currbistresult[2] = 0; + if (lane3_active == 1) currbistresult[3] = 0; + serdes_rst_seq (lane3_protocol, lane3_rate, lane2_protocol, lane2_rate, lane1_protocol, lane1_rate, lane0_protocol, lane0_rate); + if (lane3_active == 1) serdes_bist_run(3); + if (lane2_active == 1) serdes_bist_run(2); + if (lane1_active == 1) serdes_bist_run(1); + if (lane0_active == 1) serdes_bist_run(0); + tempbistresult = 0; + if (lane3_active == 1) tempbistresult = tempbistresult | serdes_bist_result(3); + tempbistresult = tempbistresult << 1; + if (lane2_active == 1) tempbistresult = tempbistresult | serdes_bist_result(2); + tempbistresult = tempbistresult << 1; + if (lane1_active == 1) tempbistresult = tempbistresult | serdes_bist_result(1); + tempbistresult = tempbistresult << 1; + if (lane0_active == 1) tempbistresult = tempbistresult | serdes_bist_result(0); + Xil_Out32(SERDES_UPHY_SPARE0, 0x0); + Xil_Out32(SERDES_UPHY_SPARE0, 0x2); + + if (itercount < 32) { + iterresult[0] = ((iterresult[0]<<1) | ((tempbistresult&0x1)==0x1)); + iterresult[1] = ((iterresult[1]<<1) | ((tempbistresult&0x2)==0x2)); + iterresult[2] = ((iterresult[2]<<1) | ((tempbistresult&0x4)==0x4)); + iterresult[3] = ((iterresult[3]<<1) | ((tempbistresult&0x8)==0x8)); + } else { + iterresult[4] = ((iterresult[4]<<1) | ((tempbistresult&0x1)==0x1)); + iterresult[5] = ((iterresult[5]<<1) | ((tempbistresult&0x2)==0x2)); + iterresult[6] = ((iterresult[6]<<1) | ((tempbistresult&0x4)==0x4)); + iterresult[7] = ((iterresult[7]<<1) | ((tempbistresult&0x8)==0x8)); + } + currbistresult[0] = currbistresult[0] | ((tempbistresult&0x1)==1); + currbistresult[1] = currbistresult[1] | ((tempbistresult&0x2)==0x2); + currbistresult[2] = currbistresult[2] | ((tempbistresult&0x4)==0x4); + currbistresult[3] = currbistresult[3] | ((tempbistresult&0x8)==0x8); + + for (loop=0; loop<=3; loop++) + { + if ((currbistresult[loop]==1) && (prevbistresult[loop]==1)) + bistpasscount[loop] = bistpasscount[loop]+1; + if ((bistpasscount[loop]<4) && (currbistresult[loop]==0) && (itercount>2)) + { + if (meancountalt_bistpasscount[loop] < bistpasscount[loop]) + { + meancountalt_bistpasscount[loop] = bistpasscount[loop]; + meancountalt[loop] = ((itercount-1)-((bistpasscount[loop]+1)/2)); + } + bistpasscount[loop] = 0; + } + if ((meancount[loop]==0) && (bistpasscount[loop]>=4) && ((currbistresult[loop]==0)||(itercount == 63)) && (prevbistresult[loop]==1)) + meancount[loop] = (itercount-1)-((bistpasscount[loop]+1)/2); + prevbistresult[loop] = currbistresult[loop]; + } + }while(++itercount<64); + + for (loop=0; loop<=3; loop++) + { + if ((lane0_active == 0) && (loop == 0)) continue; + if ((lane1_active == 0) && (loop == 1)) continue; + if ((lane2_active == 0) && (loop == 2)) continue; + if ((lane3_active == 0) && (loop == 3)) continue; + + if (meancount[loop] == 0) + meancount[loop] = meancountalt[loop]; + + + if (gen2_calib != 1) + { + ill1_val[loop] = ((0x04 + meancount[loop]*8) % 0x100); + ill12_val[loop] = ((0x04 + meancount[loop]*8) >= 0x100) ? 0x10 : 0x00; + /*Xil_Out32(0xFFFE0000+loop*4,iterresult[loop]); + Xil_Out32(0xFFFE0010+loop*4,iterresult[loop+4]); + Xil_Out32(0xFFFE0020+loop*4,bistpasscount[loop]); + Xil_Out32(0xFFFE0030+loop*4,meancount[loop]);*/ + } + if (gen2_calib == 1) + { + ill1_val[loop] = ((0x104 + meancount[loop]*8) % 0x100); + ill12_val[loop] = ((0x104 + meancount[loop]*8) >= 0x200) ? 0x02 : 0x01; + /*Xil_Out32(0xFFFE0040+loop*4,iterresult[loop]); + Xil_Out32(0xFFFE0050+loop*4,iterresult[loop+4]); + Xil_Out32(0xFFFE0060+loop*4,bistpasscount[loop]); + Xil_Out32(0xFFFE0070+loop*4,meancount[loop]);*/ + } + } + if (gen2_calib != 1) + { + if (lane0_active == 1) Xil_Out32(SERDES_L0_TM_E_ILL1,ill1_val[0]); + if (lane0_active == 1) PSU_Mask_Write(SERDES_L0_TM_ILL12, 0x000000F0U, ill12_val[0]); + if (lane1_active == 1) Xil_Out32(SERDES_L1_TM_E_ILL1,ill1_val[1]); + if (lane1_active == 1) PSU_Mask_Write(SERDES_L1_TM_ILL12, 0x000000F0U, ill12_val[1]); + if (lane2_active == 1) Xil_Out32(SERDES_L2_TM_E_ILL1,ill1_val[2]); + if (lane2_active == 1) PSU_Mask_Write(SERDES_L2_TM_ILL12, 0x000000F0U, ill12_val[2]); + if (lane3_active == 1) Xil_Out32(SERDES_L3_TM_E_ILL1,ill1_val[3]); + if (lane3_active == 1) PSU_Mask_Write(SERDES_L3_TM_ILL12, 0x000000F0U, ill12_val[3]); + } + if (gen2_calib == 1) + { + if (lane0_active == 1) Xil_Out32(SERDES_L0_TM_E_ILL2,ill1_val[0]); + if (lane0_active == 1) PSU_Mask_Write(SERDES_L0_TM_ILL12, 0x0000000FU, ill12_val[0]); + if (lane1_active == 1) Xil_Out32(SERDES_L1_TM_E_ILL2,ill1_val[1]); + if (lane1_active == 1) PSU_Mask_Write(SERDES_L1_TM_ILL12, 0x0000000FU, ill12_val[1]); + if (lane2_active == 1) Xil_Out32(SERDES_L2_TM_E_ILL2,ill1_val[2]); + if (lane2_active == 1) PSU_Mask_Write(SERDES_L2_TM_ILL12, 0x0000000FU, ill12_val[2]); + if (lane3_active == 1) Xil_Out32(SERDES_L3_TM_E_ILL2,ill1_val[3]); + if (lane3_active == 1) PSU_Mask_Write(SERDES_L3_TM_ILL12, 0x0000000FU, ill12_val[3]); + } + + + if (lane0_active == 1) PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_7, 0x00000030U, 0x00000000U); + if (lane1_active == 1) PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_7, 0x00000030U, 0x00000000U); + if (lane2_active == 1) PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_7, 0x00000030U, 0x00000000U); + if (lane3_active == 1) PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_7, 0x00000030U, 0x00000000U); + + Xil_Out32(SERDES_UPHY_SPARE0,0); + if (lane0_active == 1) + { + Xil_Out32(SERDES_L0_BIST_CTRL_1,0); + Xil_Out32(SERDES_L0_BIST_CTRL_2,0); + Xil_Out32(SERDES_L0_BIST_RUN_LEN_L,0); + Xil_Out32(SERDES_L0_BIST_ERR_INJ_POINT_L,0); + Xil_Out32(SERDES_L0_BIST_RUNLEN_ERR_INJ_H,0); + Xil_Out32(SERDES_L0_BIST_IDLE_TIME,0); + Xil_Out32(SERDES_L0_BIST_MARKER_L,0); + Xil_Out32(SERDES_L0_BIST_IDLE_CHAR_L,0); + Xil_Out32(SERDES_L0_BIST_MARKER_IDLE_H,0); + Xil_Out32(SERDES_L0_BIST_LOW_PULSE_TIME,0); + Xil_Out32(SERDES_L0_BIST_TOTAL_PULSE_TIME,0); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_1,0); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_2,0); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_3,0); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_4,0); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_MSBS,0); + Xil_Out32(SERDES_L0_BIST_PKT_NUM,0); + Xil_Out32(SERDES_L0_BIST_FRM_IDLE_TIME,0); + Xil_Out32(SERDES_L0_BIST_PKT_CTR_L,0); + Xil_Out32(SERDES_L0_BIST_PKT_CTR_H,0); + Xil_Out32(SERDES_L0_BIST_ERR_CTR_L,0); + Xil_Out32(SERDES_L0_BIST_ERR_CTR_H,0); + Xil_Out32(SERDES_L0_BIST_FILLER_OUT,1); + Xil_Out32(SERDES_L0_BIST_FORCE_MK_RST,0); + Xil_Out32(SERDES_L0_TM_DIG_22,0); + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x00000003U, 0x00000001U); + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x00000003U, 0x00000001U); + PSU_Mask_Write(SERDES_LPBK_CTRL0, 0x00000007U, 0x00000000U); + } + if (lane1_active == 1) + { + Xil_Out32(SERDES_L1_BIST_CTRL_1,0); + Xil_Out32(SERDES_L1_BIST_CTRL_2,0); + Xil_Out32(SERDES_L1_BIST_RUN_LEN_L,0); + Xil_Out32(SERDES_L1_BIST_ERR_INJ_POINT_L,0); + Xil_Out32(SERDES_L1_BIST_RUNLEN_ERR_INJ_H,0); + Xil_Out32(SERDES_L1_BIST_IDLE_TIME,0); + Xil_Out32(SERDES_L1_BIST_MARKER_L,0); + Xil_Out32(SERDES_L1_BIST_IDLE_CHAR_L,0); + Xil_Out32(SERDES_L1_BIST_MARKER_IDLE_H,0); + Xil_Out32(SERDES_L1_BIST_LOW_PULSE_TIME,0); + Xil_Out32(SERDES_L1_BIST_TOTAL_PULSE_TIME,0); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_1,0); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_2,0); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_3,0); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_4,0); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_MSBS,0); + Xil_Out32(SERDES_L1_BIST_PKT_NUM,0); + Xil_Out32(SERDES_L1_BIST_FRM_IDLE_TIME,0); + Xil_Out32(SERDES_L1_BIST_PKT_CTR_L,0); + Xil_Out32(SERDES_L1_BIST_PKT_CTR_H,0); + Xil_Out32(SERDES_L1_BIST_ERR_CTR_L,0); + Xil_Out32(SERDES_L1_BIST_ERR_CTR_H,0); + Xil_Out32(SERDES_L1_BIST_FILLER_OUT,1); + Xil_Out32(SERDES_L1_BIST_FORCE_MK_RST,0); + Xil_Out32(SERDES_L1_TM_DIG_22,0); + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x0000000CU, 0x00000004U); + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x0000000CU, 0x00000004U); + PSU_Mask_Write(SERDES_LPBK_CTRL0, 0x00000070U, 0x00000000U); + } + if (lane2_active == 1) + { + Xil_Out32(SERDES_L2_BIST_CTRL_1,0); + Xil_Out32(SERDES_L2_BIST_CTRL_2,0); + Xil_Out32(SERDES_L2_BIST_RUN_LEN_L,0); + Xil_Out32(SERDES_L2_BIST_ERR_INJ_POINT_L,0); + Xil_Out32(SERDES_L2_BIST_RUNLEN_ERR_INJ_H,0); + Xil_Out32(SERDES_L2_BIST_IDLE_TIME,0); + Xil_Out32(SERDES_L2_BIST_MARKER_L,0); + Xil_Out32(SERDES_L2_BIST_IDLE_CHAR_L,0); + Xil_Out32(SERDES_L2_BIST_MARKER_IDLE_H,0); + Xil_Out32(SERDES_L2_BIST_LOW_PULSE_TIME,0); + Xil_Out32(SERDES_L2_BIST_TOTAL_PULSE_TIME,0); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_1,0); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_2,0); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_3,0); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_4,0); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_MSBS,0); + Xil_Out32(SERDES_L2_BIST_PKT_NUM,0); + Xil_Out32(SERDES_L2_BIST_FRM_IDLE_TIME,0); + Xil_Out32(SERDES_L2_BIST_PKT_CTR_L,0); + Xil_Out32(SERDES_L2_BIST_PKT_CTR_H,0); + Xil_Out32(SERDES_L2_BIST_ERR_CTR_L,0); + Xil_Out32(SERDES_L2_BIST_ERR_CTR_H,0); + Xil_Out32(SERDES_L2_BIST_FILLER_OUT,1); + Xil_Out32(SERDES_L2_BIST_FORCE_MK_RST,0); + Xil_Out32(SERDES_L2_TM_DIG_22,0); + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x00000030U, 0x00000010U); + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x00000030U, 0x00000010U); + PSU_Mask_Write(SERDES_LPBK_CTRL1, 0x00000007U, 0x00000000U); + } + if (lane3_active == 1) + { + Xil_Out32(SERDES_L3_BIST_CTRL_1,0); + Xil_Out32(SERDES_L3_BIST_CTRL_2,0); + Xil_Out32(SERDES_L3_BIST_RUN_LEN_L,0); + Xil_Out32(SERDES_L3_BIST_ERR_INJ_POINT_L,0); + Xil_Out32(SERDES_L3_BIST_RUNLEN_ERR_INJ_H,0); + Xil_Out32(SERDES_L3_BIST_IDLE_TIME,0); + Xil_Out32(SERDES_L3_BIST_MARKER_L,0); + Xil_Out32(SERDES_L3_BIST_IDLE_CHAR_L,0); + Xil_Out32(SERDES_L3_BIST_MARKER_IDLE_H,0); + Xil_Out32(SERDES_L3_BIST_LOW_PULSE_TIME,0); + Xil_Out32(SERDES_L3_BIST_TOTAL_PULSE_TIME,0); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_1,0); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_2,0); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_3,0); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_4,0); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_MSBS,0); + Xil_Out32(SERDES_L3_BIST_PKT_NUM,0); + Xil_Out32(SERDES_L3_BIST_FRM_IDLE_TIME,0); + Xil_Out32(SERDES_L3_BIST_PKT_CTR_L,0); + Xil_Out32(SERDES_L3_BIST_PKT_CTR_H,0); + Xil_Out32(SERDES_L3_BIST_ERR_CTR_L,0); + Xil_Out32(SERDES_L3_BIST_ERR_CTR_H,0); + Xil_Out32(SERDES_L3_BIST_FILLER_OUT,1); + Xil_Out32(SERDES_L3_BIST_FORCE_MK_RST,0); + Xil_Out32(SERDES_L3_TM_DIG_22,0); + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x000000C0U, 0x00000040U); + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x000000C0U, 0x00000040U); + PSU_Mask_Write(SERDES_LPBK_CTRL1, 0x00000070U, 0x00000000U); + } + return 1; +} + +static int serdes_illcalib (u32 lane3_protocol, u32 lane3_rate, u32 lane2_protocol, u32 lane2_rate, u32 lane1_protocol, u32 lane1_rate, u32 lane0_protocol, u32 lane0_rate) +//Protocol values +//pcie = 1; sata = 2; usb = 3; dp = 4; sgmii = 5 +//Rate values +//pcie_gen1 = 0; pcie_gen2 = 1; +//sata_gen1 = 1; sata_gen2 = 2; sata_gen3 = 3; +//usb = 0; sgmii = 0; DP = 0; +{ + unsigned int rdata=0; + unsigned int sata_gen2=1; + unsigned int temp_ill12=0; + unsigned int temp_PLL_REF_SEL_OFFSET; + unsigned int temp_TM_IQ_ILL1; + unsigned int temp_TM_E_ILL1; + unsigned int temp_tx_dig_tm_61; + unsigned int temp_tm_dig_6; + unsigned int temp_pll_fbdiv_frac_3_msb_offset; + + if ((lane0_protocol == 2)||(lane0_protocol == 1)) + { + Xil_Out32(SERDES_L0_TM_IQ_ILL7, 0xF3); + Xil_Out32(SERDES_L0_TM_E_ILL7, 0xF3); + Xil_Out32(SERDES_L0_TM_IQ_ILL8,0xF3); + Xil_Out32(SERDES_L0_TM_E_ILL8,0xF3); + } + if ((lane1_protocol == 2)||(lane1_protocol == 1)) + { + Xil_Out32(SERDES_L1_TM_IQ_ILL7, 0xF3); + Xil_Out32(SERDES_L1_TM_E_ILL7, 0xF3); + Xil_Out32(SERDES_L1_TM_IQ_ILL8,0xF3); + Xil_Out32(SERDES_L1_TM_E_ILL8,0xF3); + } + if ((lane2_protocol == 2)||(lane2_protocol == 1)) + { + Xil_Out32(SERDES_L2_TM_IQ_ILL7, 0xF3); + Xil_Out32(SERDES_L2_TM_E_ILL7, 0xF3); + Xil_Out32(SERDES_L2_TM_IQ_ILL8,0xF3); + Xil_Out32(SERDES_L2_TM_E_ILL8,0xF3); + } + if ((lane3_protocol == 2)||(lane3_protocol == 1)) + { + Xil_Out32(SERDES_L3_TM_IQ_ILL7, 0xF3); + Xil_Out32(SERDES_L3_TM_E_ILL7, 0xF3); + Xil_Out32(SERDES_L3_TM_IQ_ILL8,0xF3); + Xil_Out32(SERDES_L3_TM_E_ILL8,0xF3); + } + + if (sata_gen2 == 1) + { + if (lane0_protocol == 2) + { + temp_pll_fbdiv_frac_3_msb_offset=Xil_In32(SERDES_L0_PLL_FBDIV_FRAC_3_MSB); + Xil_Out32(SERDES_L0_PLL_FBDIV_FRAC_3_MSB,0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(SERDES_PLL_REF_SEL0_OFFSET); + PSU_Mask_Write(SERDES_PLL_REF_SEL0_OFFSET, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(SERDES_L0_TM_IQ_ILL1); + temp_TM_E_ILL1 = Xil_In32(SERDES_L0_TM_E_ILL1); + Xil_Out32(SERDES_L0_TM_IQ_ILL1,0x78); + temp_tx_dig_tm_61 = Xil_In32(SERDES_L0_TX_DIG_TM_61); + temp_tm_dig_6 = Xil_In32(SERDES_L0_TM_DIG_6); + PSU_Mask_Write(SERDES_L0_TX_DIG_TM_61, 0x0000000BU, 0x00000000U); + PSU_Mask_Write(SERDES_L0_TM_DIG_6, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(SERDES_L0_TM_ILL12) & 0xF0; + + serdes_illcalib_pcie_gen1 (0, 0, 0, 0, 0, 0, 1, 0, 0); + + Xil_Out32(SERDES_L0_PLL_FBDIV_FRAC_3_MSB,temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(SERDES_PLL_REF_SEL3_OFFSET, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(SERDES_L0_TM_IQ_ILL1,temp_TM_IQ_ILL1); + Xil_Out32(SERDES_L0_TX_DIG_TM_61, temp_tx_dig_tm_61); + Xil_Out32(SERDES_L0_TM_DIG_6, temp_tm_dig_6); + Xil_Out32(SERDES_L0_TM_E_ILL2, Xil_In32(SERDES_L0_TM_E_ILL1)); + temp_ill12 = temp_ill12 | (Xil_In32(SERDES_L0_TM_ILL12)>>4 & 0xF); + Xil_Out32(SERDES_L0_TM_ILL12, temp_ill12); + Xil_Out32(SERDES_L0_TM_E_ILL1, temp_TM_E_ILL1); + } + if (lane1_protocol == 2) + { + temp_pll_fbdiv_frac_3_msb_offset=Xil_In32(SERDES_L1_PLL_FBDIV_FRAC_3_MSB); + Xil_Out32(SERDES_L1_PLL_FBDIV_FRAC_3_MSB,0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(SERDES_PLL_REF_SEL1_OFFSET); + PSU_Mask_Write(SERDES_PLL_REF_SEL1_OFFSET, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(SERDES_L1_TM_IQ_ILL1); + temp_TM_E_ILL1 = Xil_In32(SERDES_L1_TM_E_ILL1); + Xil_Out32(SERDES_L1_TM_IQ_ILL1,0x78); + temp_tx_dig_tm_61 = Xil_In32(SERDES_L1_TX_DIG_TM_61); + temp_tm_dig_6 = Xil_In32(SERDES_L1_TM_DIG_6); + PSU_Mask_Write(SERDES_L1_TX_DIG_TM_61, 0x0000000BU, 0x00000000U); + PSU_Mask_Write(SERDES_L1_TM_DIG_6, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(SERDES_L1_TM_ILL12) & 0xF0; + + serdes_illcalib_pcie_gen1 (0, 0, 0, 0, 1, 0, 0, 0, 0); + + Xil_Out32(SERDES_L1_PLL_FBDIV_FRAC_3_MSB,temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(SERDES_PLL_REF_SEL3_OFFSET, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(SERDES_L1_TM_IQ_ILL1,temp_TM_IQ_ILL1); + Xil_Out32(SERDES_L1_TX_DIG_TM_61, temp_tx_dig_tm_61); + Xil_Out32(SERDES_L1_TM_DIG_6, temp_tm_dig_6); + Xil_Out32(SERDES_L1_TM_E_ILL2, Xil_In32(SERDES_L1_TM_E_ILL1)); + temp_ill12 = temp_ill12 | (Xil_In32(SERDES_L1_TM_ILL12)>>4 & 0xF); + Xil_Out32(SERDES_L1_TM_ILL12, temp_ill12); + Xil_Out32(SERDES_L1_TM_E_ILL1, temp_TM_E_ILL1); + } + if (lane2_protocol == 2) + { + temp_pll_fbdiv_frac_3_msb_offset=Xil_In32(SERDES_L2_PLL_FBDIV_FRAC_3_MSB); + Xil_Out32(SERDES_L2_PLL_FBDIV_FRAC_3_MSB,0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(SERDES_PLL_REF_SEL2_OFFSET); + PSU_Mask_Write(SERDES_PLL_REF_SEL2_OFFSET, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(SERDES_L2_TM_IQ_ILL1); + temp_TM_E_ILL1 = Xil_In32(SERDES_L2_TM_E_ILL1); + Xil_Out32(SERDES_L2_TM_IQ_ILL1,0x78); + temp_tx_dig_tm_61 = Xil_In32(SERDES_L2_TX_DIG_TM_61); + temp_tm_dig_6 = Xil_In32(SERDES_L2_TM_DIG_6); + PSU_Mask_Write(SERDES_L2_TX_DIG_TM_61, 0x0000000BU, 0x00000000U); + PSU_Mask_Write(SERDES_L2_TM_DIG_6, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(SERDES_L2_TM_ILL12) & 0xF0; + + serdes_illcalib_pcie_gen1 (0, 0, 1, 0, 0, 0, 0, 0, 0); + + Xil_Out32(SERDES_L2_PLL_FBDIV_FRAC_3_MSB,temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(SERDES_PLL_REF_SEL3_OFFSET, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(SERDES_L2_TM_IQ_ILL1,temp_TM_IQ_ILL1); + Xil_Out32(SERDES_L2_TX_DIG_TM_61, temp_tx_dig_tm_61); + Xil_Out32(SERDES_L2_TM_DIG_6, temp_tm_dig_6); + Xil_Out32(SERDES_L2_TM_E_ILL2, Xil_In32(SERDES_L2_TM_E_ILL1)); + temp_ill12 = temp_ill12 | (Xil_In32(SERDES_L2_TM_ILL12)>>4 & 0xF); + Xil_Out32(SERDES_L2_TM_ILL12, temp_ill12); + Xil_Out32(SERDES_L2_TM_E_ILL1, temp_TM_E_ILL1); + } + if (lane3_protocol == 2) + { + temp_pll_fbdiv_frac_3_msb_offset=Xil_In32(SERDES_L3_PLL_FBDIV_FRAC_3_MSB); + Xil_Out32(SERDES_L3_PLL_FBDIV_FRAC_3_MSB,0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(SERDES_PLL_REF_SEL3_OFFSET); + PSU_Mask_Write(SERDES_PLL_REF_SEL3_OFFSET, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(SERDES_L3_TM_IQ_ILL1); + temp_TM_E_ILL1 = Xil_In32(SERDES_L3_TM_E_ILL1); + Xil_Out32(SERDES_L3_TM_IQ_ILL1,0x78); + temp_tx_dig_tm_61 = Xil_In32(SERDES_L3_TX_DIG_TM_61); + temp_tm_dig_6 = Xil_In32(SERDES_L3_TM_DIG_6); + PSU_Mask_Write(SERDES_L3_TX_DIG_TM_61, 0x0000000BU, 0x00000000U); + PSU_Mask_Write(SERDES_L3_TM_DIG_6, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(SERDES_L3_TM_ILL12) & 0xF0; + + serdes_illcalib_pcie_gen1 (1, 0, 0, 0, 0, 0, 0, 0, 0); + + Xil_Out32(SERDES_L3_PLL_FBDIV_FRAC_3_MSB,temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(SERDES_PLL_REF_SEL3_OFFSET, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(SERDES_L3_TM_IQ_ILL1,temp_TM_IQ_ILL1); + Xil_Out32(SERDES_L3_TX_DIG_TM_61, temp_tx_dig_tm_61); + Xil_Out32(SERDES_L3_TM_DIG_6, temp_tm_dig_6); + Xil_Out32(SERDES_L3_TM_E_ILL2, Xil_In32(SERDES_L3_TM_E_ILL1)); + temp_ill12 = temp_ill12 | (Xil_In32(SERDES_L3_TM_ILL12)>>4 & 0xF); + Xil_Out32(SERDES_L3_TM_ILL12, temp_ill12); + Xil_Out32(SERDES_L3_TM_E_ILL1, temp_TM_E_ILL1); + } + rdata = Xil_In32(SERDES_UPHY_SPARE0); + rdata = (rdata & 0xDF); + Xil_Out32(SERDES_UPHY_SPARE0,rdata); + } + + if ((lane0_protocol == 2)&&(lane0_rate == 3)) + { + PSU_Mask_Write(SERDES_L0_TM_ILL11, 0x000000F0U, 0x00000020U); + PSU_Mask_Write(SERDES_L0_TM_E_ILL3, 0x000000FFU, 0x00000094U); + } + if ((lane1_protocol == 2)&&(lane1_rate == 3)) + { + PSU_Mask_Write(SERDES_L1_TM_ILL11, 0x000000F0U, 0x00000020U); + PSU_Mask_Write(SERDES_L1_TM_E_ILL3, 0x000000FFU, 0x00000094U); + } + if ((lane2_protocol == 2)&&(lane2_rate == 3)) + { + PSU_Mask_Write(SERDES_L2_TM_ILL11, 0x000000F0U, 0x00000020U); + PSU_Mask_Write(SERDES_L2_TM_E_ILL3, 0x000000FFU, 0x00000094U); + } + if ((lane3_protocol == 2)&&(lane3_rate == 3)) + { + PSU_Mask_Write(SERDES_L3_TM_ILL11, 0x000000F0U, 0x00000020U); + PSU_Mask_Write(SERDES_L3_TM_E_ILL3, 0x000000FFU, 0x00000094U); + } + + //PCIe settings + //If lane-0 is PCIe, we need to run pcie dynamic search on all active pcie lanes + //and reset sequence on all active lanes + if (lane0_protocol == 1) + { + if (lane0_rate == 0) + { + serdes_illcalib_pcie_gen1 (lane3_protocol, lane3_rate, lane2_protocol, lane2_rate, lane1_protocol, lane1_rate, lane0_protocol, 0, 0); + } + else + { + serdes_illcalib_pcie_gen1 (lane3_protocol, lane3_rate, lane2_protocol, lane2_rate, lane1_protocol, lane1_rate, lane0_protocol, 0, 0); + serdes_illcalib_pcie_gen1 (lane3_protocol, lane3_rate, lane2_protocol, lane2_rate, lane1_protocol, lane1_rate, lane0_protocol, lane0_rate, 1); + } + } + + //USB3 settings + if (lane0_protocol == 3) Xil_Out32(SERDES_L0_TM_IQ_ILL8,0xF3); + if (lane0_protocol == 3) Xil_Out32(SERDES_L0_TM_E_ILL8,0xF3); + if (lane0_protocol == 3) Xil_Out32(SERDES_L0_TM_ILL12,0x20); + if (lane0_protocol == 3) Xil_Out32(SERDES_L0_TM_E_ILL1,0x37); + + if (lane1_protocol == 3) Xil_Out32(SERDES_L1_TM_IQ_ILL8,0xF3); + if (lane1_protocol == 3) Xil_Out32(SERDES_L1_TM_E_ILL8,0xF3); + if (lane1_protocol == 3) Xil_Out32(SERDES_L1_TM_ILL12,0x20); + if (lane1_protocol == 3) Xil_Out32(SERDES_L1_TM_E_ILL1,0x37); + + if (lane2_protocol == 3) Xil_Out32(SERDES_L2_TM_IQ_ILL8,0xF3); + if (lane2_protocol == 3) Xil_Out32(SERDES_L2_TM_E_ILL8,0xF3); + if (lane2_protocol == 3) Xil_Out32(SERDES_L2_TM_ILL12,0x20); + if (lane2_protocol == 3) Xil_Out32(SERDES_L2_TM_E_ILL1,0x37); + + if (lane3_protocol == 3) Xil_Out32(SERDES_L3_TM_IQ_ILL8,0xF3); + if (lane3_protocol == 3) Xil_Out32(SERDES_L3_TM_E_ILL8,0xF3); + if (lane3_protocol == 3) Xil_Out32(SERDES_L3_TM_ILL12,0x20); + if (lane3_protocol == 3) Xil_Out32(SERDES_L3_TM_E_ILL1,0x37); + + return 1; +} + + +//Kishore -- ILL calibration code ends + +/*Following SERDES programming sequences that a user need to follow to work + * around the known limitation with SERDES. These sequences should done + * before STEP 1 and STEP 2 as described in previous section. These + * programming steps are *required for current silicon version and are + * likely to undergo further changes with subsequent silicon versions. + */ + + +static int serdes_enb_coarse_saturation(void) +{ + /*Enable PLL Coarse Code saturation Logic*/ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +int serdes_fixcal_code(void) +{ + int MaskStatus = 1; + + unsigned int rdata = 0; + + /*The valid codes are from 0x26 to 0x3C. + *There are 23 valid codes in total. + */ + /*Each element of array stands for count of occurence of valid code.*/ + unsigned int match_pmos_code[23]; + /*Each element of array stands for count of occurence of valid code.*/ + /*The valid codes are from 0xC to 0x12. + *There are 7 valid codes in total. + */ + unsigned int match_nmos_code[23]; + /*Each element of array stands for count of occurence of valid code.*/ + /*The valid codes are from 0x6 to 0xC. + * There are 7 valid codes in total. + */ + unsigned int match_ical_code[7]; + /*Each element of array stands for count of occurence of valid code.*/ + unsigned int match_rcal_code[7]; + + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + + int i = 0; + + rdata = Xil_In32(0XFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0XFD40289C, rdata); + // check supply good status before starting AFE sequencing + int count = 0; + do + { + if (count == PSU_MASK_POLL_TIME) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + }while((rdata&0x0000000E) !=0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + + do { + /*Clear ICM_CFG value*/ + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + /*Set ICM_CFG value*/ + /*This will trigger recalibration of all stages*/ + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + /*is calibration done? polling on L3_CALIB_DONE_STATUS*/ + MaskStatus = mask_poll(0xFD40EF14, 0x2); + if (MaskStatus == 0) { + /*failure here is because of calibration done timeout*/ + xil_printf("#SERDES initialization timed out\n\r"); + return MaskStatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);/*PMOS code*/ + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);/*NMOS code*/ + /*m_code = mask_read(0xFD40EF20, 0xFFFFFFFF)*/;/*MPHY code*/ + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);/*ICAL code*/ + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);/*RX code*/ + /*u_code = mask_read(0xFD40EF2C, 0xFFFFFFFF)*/;/*USB2 code*/ + + /*PMOS code in acceptable range*/ + if ((p_code >= 0x26) && (p_code <= 0x3C)) + match_pmos_code[p_code - 0x26] += 1; + + /*NMOS code in acceptable range*/ + if ((n_code >= 0x26) && (n_code <= 0x3C)) + match_nmos_code[n_code - 0x26] += 1; + + /*PMOS code in acceptable range*/ + if ((i_code >= 0xC) && (i_code <= 0x12)) + match_ical_code[i_code - 0xC] += 1; + + /*NMOS code in acceptable range*/ + if ((r_code >= 0x6) && (r_code <= 0xC)) + match_rcal_code[r_code - 0x6] += 1; + + + } while (repeat_count++ < 10); + + /*find the valid code which resulted in maximum times in 10 iterations*/ + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + /*L3_TM_CALIB_DIG20[3] PSW MSB Override*/ + /*L3_TM_CALIB_DIG20[2:0] PSW Code [4:2]*/ + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);/*read DIG20*/ + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + + /*L3_TM_CALIB_DIG19[7:6] PSW Code [1:0]*/ + /*L3_TM_CALIB_DIG19[5] PSW Override*/ + /*L3_TM_CALIB_DIG19[2] NSW MSB Override*/ + /*L3_TM_CALIB_DIG19[1:0] NSW Code [4:3]*/ + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);/*read DIG19*/ + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + /*L3_TM_CALIB_DIG18[7:5] NSW Code [2:0]*/ + /*L3_TM_CALIB_DIG18[4] NSW Override*/ + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);/*read DIG18*/ + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + + /*L3_TM_CALIB_DIG16[2:0] RX Code [3:1]*/ + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);/*read DIG16*/ + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + /*L3_TM_CALIB_DIG15[7] RX Code [0]*/ + /*L3_TM_CALIB_DIG15[6] RX CODE Override*/ + /*L3_TM_CALIB_DIG15[3] ICAL MSB Override*/ + /*L3_TM_CALIB_DIG15[2:0] ICAL Code [3:1]*/ + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);/*read DIG15*/ + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + /*L3_TM_CALIB_DIG14[7] ICAL Code [0]*/ + /*L3_TM_CALIB_DIG14[6] ICAL Override*/ + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);/*read DIG14*/ + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + /*Forces the calibration values*/ + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return MaskStatus; + +} +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + + +static void init_peripheral(void) +{ +/*SMMU_REG Interrrupt Enable: Followig register need to be written all the time to properly catch SMMU messages.*/ + PSU_Mask_Write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +static int psu_init_xppu_aper_ram(void) +{ + + return 0; +} + +int psu_lpd_protection(void) +{ + psu_init_xppu_aper_ram(); + return 0; +} + +int psu_ddr_protection(void) +{ + psu_ddr_xmpu0_data(); + psu_ddr_xmpu1_data(); + psu_ddr_xmpu2_data(); + psu_ddr_xmpu3_data(); + psu_ddr_xmpu4_data(); + psu_ddr_xmpu5_data(); + return 0; +} +int psu_ocm_protection(void) +{ + psu_ocm_xmpu_data(); + return 0; +} + +int psu_fpd_protection(void) +{ + psu_fpd_xmpu_data(); + return 0; +} + +int psu_protection_lock(void) +{ + psu_protection_lock_data(); + return 0; +} + +int psu_protection(void) +{ + psu_apply_master_tz(); + psu_ddr_protection(); + psu_ocm_protection(); + psu_fpd_protection(); + psu_lpd_protection(); + return 0; +} + +int +psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_peripherals_pre_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_peripherals_powerdwn_data(); + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) + return 1; + return 0; +} + +int psu_init_ddr_self_refresh(void) { + + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_peripherals_pre_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_peripherals_powerdwn_data(); + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) + return 1; + return 0; + + +} + + diff --git a/Petalinux/project-spec/hw-description/psu_init.h b/Petalinux/project-spec/hw-description/psu_init.h new file mode 100644 index 0000000..9e00ce5 --- /dev/null +++ b/Petalinux/project-spec/hw-description/psu_init.h @@ -0,0 +1,38619 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file psu_init.h +* +* This file is automatically generated +* +*****************************************************************************/ + + +#undef CRL_APB_RPLL_CFG_OFFSET +#define CRL_APB_RPLL_CFG_OFFSET 0XFF5E0034 +#undef CRL_APB_RPLL_CTRL_OFFSET +#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 +#undef CRL_APB_RPLL_CTRL_OFFSET +#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 +#undef CRL_APB_RPLL_CTRL_OFFSET +#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 +#undef CRL_APB_RPLL_CTRL_OFFSET +#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 +#undef CRL_APB_RPLL_CTRL_OFFSET +#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 +#undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET +#define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 0XFF5E0048 +#undef CRL_APB_AMS_REF_CTRL_OFFSET +#define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108 +#undef CRL_APB_IOPLL_CFG_OFFSET +#define CRL_APB_IOPLL_CFG_OFFSET 0XFF5E0024 +#undef CRL_APB_IOPLL_CTRL_OFFSET +#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 +#undef CRL_APB_IOPLL_CTRL_OFFSET +#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 +#undef CRL_APB_IOPLL_CTRL_OFFSET +#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 +#undef CRL_APB_IOPLL_CTRL_OFFSET +#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 +#undef CRL_APB_IOPLL_CTRL_OFFSET +#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 +#undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET +#define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 0XFF5E0044 +#undef CRF_APB_APLL_CFG_OFFSET +#define CRF_APB_APLL_CFG_OFFSET 0XFD1A0024 +#undef CRF_APB_APLL_CTRL_OFFSET +#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 +#undef CRF_APB_APLL_CTRL_OFFSET +#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 +#undef CRF_APB_APLL_CTRL_OFFSET +#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 +#undef CRF_APB_APLL_CTRL_OFFSET +#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 +#undef CRF_APB_APLL_CTRL_OFFSET +#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 +#undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET +#define CRF_APB_APLL_TO_LPD_CTRL_OFFSET 0XFD1A0048 +#undef CRF_APB_DPLL_CFG_OFFSET +#define CRF_APB_DPLL_CFG_OFFSET 0XFD1A0030 +#undef CRF_APB_DPLL_CTRL_OFFSET +#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C +#undef CRF_APB_DPLL_CTRL_OFFSET +#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C +#undef CRF_APB_DPLL_CTRL_OFFSET +#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C +#undef CRF_APB_DPLL_CTRL_OFFSET +#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C +#undef CRF_APB_DPLL_CTRL_OFFSET +#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C +#undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET +#define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 0XFD1A004C +#undef CRF_APB_VPLL_CFG_OFFSET +#define CRF_APB_VPLL_CFG_OFFSET 0XFD1A003C +#undef CRF_APB_VPLL_CTRL_OFFSET +#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 +#undef CRF_APB_VPLL_CTRL_OFFSET +#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 +#undef CRF_APB_VPLL_CTRL_OFFSET +#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 +#undef CRF_APB_VPLL_CTRL_OFFSET +#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 +#undef CRF_APB_VPLL_CTRL_OFFSET +#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 +#undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET +#define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 0XFD1A0050 + +/* +* PLL loop filter resistor control +*/ +#undef CRL_APB_RPLL_CFG_RES_DEFVAL +#undef CRL_APB_RPLL_CFG_RES_SHIFT +#undef CRL_APB_RPLL_CFG_RES_MASK +#define CRL_APB_RPLL_CFG_RES_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_RES_SHIFT 0 +#define CRL_APB_RPLL_CFG_RES_MASK 0x0000000FU + +/* +* PLL charge pump control +*/ +#undef CRL_APB_RPLL_CFG_CP_DEFVAL +#undef CRL_APB_RPLL_CFG_CP_SHIFT +#undef CRL_APB_RPLL_CFG_CP_MASK +#define CRL_APB_RPLL_CFG_CP_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_CP_SHIFT 5 +#define CRL_APB_RPLL_CFG_CP_MASK 0x000001E0U + +/* +* PLL loop filter high frequency capacitor control +*/ +#undef CRL_APB_RPLL_CFG_LFHF_DEFVAL +#undef CRL_APB_RPLL_CFG_LFHF_SHIFT +#undef CRL_APB_RPLL_CFG_LFHF_MASK +#define CRL_APB_RPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LFHF_SHIFT 10 +#define CRL_APB_RPLL_CFG_LFHF_MASK 0x00000C00U + +/* +* Lock circuit counter setting +*/ +#undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL +#undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT +#undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK +#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK 0x007FE000U + +/* +* Lock circuit configuration settings for lock windowsize +*/ +#undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL +#undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT +#undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK +#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK 0xFE000000U + +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ +#undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL +#undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT +#undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK +#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK 0x00700000U + +/* +* The integer portion of the feedback divider to the PLL +*/ +#undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL +#undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT +#undef CRL_APB_RPLL_CTRL_FBDIV_MASK +#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8 +#define CRL_APB_RPLL_CTRL_FBDIV_MASK 0x00007F00U + +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ +#undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL +#undef CRL_APB_RPLL_CTRL_DIV2_SHIFT +#undef CRL_APB_RPLL_CTRL_DIV2_MASK +#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16 +#define CRL_APB_RPLL_CTRL_DIV2_MASK 0x00010000U + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL +#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT +#undef CRL_APB_RPLL_CTRL_BYPASS_MASK +#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL +#undef CRL_APB_RPLL_CTRL_RESET_SHIFT +#undef CRL_APB_RPLL_CTRL_RESET_MASK +#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL +#undef CRL_APB_RPLL_CTRL_RESET_SHIFT +#undef CRL_APB_RPLL_CTRL_RESET_MASK +#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U + +/* +* RPLL is locked +*/ +#undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL +#undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT +#undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK +#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 0x00000018 +#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1 +#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 0x00000002U +#define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040 + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL +#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT +#undef CRL_APB_RPLL_CTRL_BYPASS_MASK +#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Divisor value for this clock. +*/ +#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 6 bit divider +*/ +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK +#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK +#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* PLL loop filter resistor control +*/ +#undef CRL_APB_IOPLL_CFG_RES_DEFVAL +#undef CRL_APB_IOPLL_CFG_RES_SHIFT +#undef CRL_APB_IOPLL_CFG_RES_MASK +#define CRL_APB_IOPLL_CFG_RES_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_RES_SHIFT 0 +#define CRL_APB_IOPLL_CFG_RES_MASK 0x0000000FU + +/* +* PLL charge pump control +*/ +#undef CRL_APB_IOPLL_CFG_CP_DEFVAL +#undef CRL_APB_IOPLL_CFG_CP_SHIFT +#undef CRL_APB_IOPLL_CFG_CP_MASK +#define CRL_APB_IOPLL_CFG_CP_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_CP_SHIFT 5 +#define CRL_APB_IOPLL_CFG_CP_MASK 0x000001E0U + +/* +* PLL loop filter high frequency capacitor control +*/ +#undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL +#undef CRL_APB_IOPLL_CFG_LFHF_SHIFT +#undef CRL_APB_IOPLL_CFG_LFHF_MASK +#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10 +#define CRL_APB_IOPLL_CFG_LFHF_MASK 0x00000C00U + +/* +* Lock circuit counter setting +*/ +#undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL +#undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT +#undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK +#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 0x007FE000U + +/* +* Lock circuit configuration settings for lock windowsize +*/ +#undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL +#undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT +#undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK +#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 0xFE000000U + +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ +#undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL +#undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT +#undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK +#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 0x00700000U + +/* +* The integer portion of the feedback divider to the PLL +*/ +#undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL +#undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT +#undef CRL_APB_IOPLL_CTRL_FBDIV_MASK +#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8 +#define CRL_APB_IOPLL_CTRL_FBDIV_MASK 0x00007F00U + +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ +#undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL +#undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT +#undef CRL_APB_IOPLL_CTRL_DIV2_MASK +#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16 +#define CRL_APB_IOPLL_CTRL_DIV2_MASK 0x00010000U + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL +#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT +#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK +#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL +#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT +#undef CRL_APB_IOPLL_CTRL_RESET_MASK +#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL +#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT +#undef CRL_APB_IOPLL_CTRL_RESET_MASK +#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U + +/* +* IOPLL is locked +*/ +#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL +#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT +#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 0x00000018 +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0 +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 0x00000001U +#define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040 + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL +#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT +#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK +#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Divisor value for this clock. +*/ +#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* PLL loop filter resistor control +*/ +#undef CRF_APB_APLL_CFG_RES_DEFVAL +#undef CRF_APB_APLL_CFG_RES_SHIFT +#undef CRF_APB_APLL_CFG_RES_MASK +#define CRF_APB_APLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_RES_SHIFT 0 +#define CRF_APB_APLL_CFG_RES_MASK 0x0000000FU + +/* +* PLL charge pump control +*/ +#undef CRF_APB_APLL_CFG_CP_DEFVAL +#undef CRF_APB_APLL_CFG_CP_SHIFT +#undef CRF_APB_APLL_CFG_CP_MASK +#define CRF_APB_APLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_CP_SHIFT 5 +#define CRF_APB_APLL_CFG_CP_MASK 0x000001E0U + +/* +* PLL loop filter high frequency capacitor control +*/ +#undef CRF_APB_APLL_CFG_LFHF_DEFVAL +#undef CRF_APB_APLL_CFG_LFHF_SHIFT +#undef CRF_APB_APLL_CFG_LFHF_MASK +#define CRF_APB_APLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_APLL_CFG_LFHF_MASK 0x00000C00U + +/* +* Lock circuit counter setting +*/ +#undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL +#undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT +#undef CRF_APB_APLL_CFG_LOCK_CNT_MASK +#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_APLL_CFG_LOCK_CNT_MASK 0x007FE000U + +/* +* Lock circuit configuration settings for lock windowsize +*/ +#undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL +#undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT +#undef CRF_APB_APLL_CFG_LOCK_DLY_MASK +#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_APLL_CFG_LOCK_DLY_MASK 0xFE000000U + +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ +#undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL +#undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT +#undef CRF_APB_APLL_CTRL_PRE_SRC_MASK +#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_APLL_CTRL_PRE_SRC_MASK 0x00700000U + +/* +* The integer portion of the feedback divider to the PLL +*/ +#undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL +#undef CRF_APB_APLL_CTRL_FBDIV_SHIFT +#undef CRF_APB_APLL_CTRL_FBDIV_MASK +#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_APLL_CTRL_FBDIV_MASK 0x00007F00U + +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ +#undef CRF_APB_APLL_CTRL_DIV2_DEFVAL +#undef CRF_APB_APLL_CTRL_DIV2_SHIFT +#undef CRF_APB_APLL_CTRL_DIV2_MASK +#define CRF_APB_APLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_APLL_CTRL_DIV2_MASK 0x00010000U + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL +#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT +#undef CRF_APB_APLL_CTRL_BYPASS_MASK +#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRF_APB_APLL_CTRL_RESET_DEFVAL +#undef CRF_APB_APLL_CTRL_RESET_SHIFT +#undef CRF_APB_APLL_CTRL_RESET_MASK +#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRF_APB_APLL_CTRL_RESET_DEFVAL +#undef CRF_APB_APLL_CTRL_RESET_SHIFT +#undef CRF_APB_APLL_CTRL_RESET_MASK +#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U + +/* +* APLL is locked +*/ +#undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL +#undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT +#undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK +#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0 +#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK 0x00000001U +#define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL +#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT +#undef CRF_APB_APLL_CTRL_BYPASS_MASK +#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Divisor value for this clock. +*/ +#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* PLL loop filter resistor control +*/ +#undef CRF_APB_DPLL_CFG_RES_DEFVAL +#undef CRF_APB_DPLL_CFG_RES_SHIFT +#undef CRF_APB_DPLL_CFG_RES_MASK +#define CRF_APB_DPLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_RES_SHIFT 0 +#define CRF_APB_DPLL_CFG_RES_MASK 0x0000000FU + +/* +* PLL charge pump control +*/ +#undef CRF_APB_DPLL_CFG_CP_DEFVAL +#undef CRF_APB_DPLL_CFG_CP_SHIFT +#undef CRF_APB_DPLL_CFG_CP_MASK +#define CRF_APB_DPLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_CP_SHIFT 5 +#define CRF_APB_DPLL_CFG_CP_MASK 0x000001E0U + +/* +* PLL loop filter high frequency capacitor control +*/ +#undef CRF_APB_DPLL_CFG_LFHF_DEFVAL +#undef CRF_APB_DPLL_CFG_LFHF_SHIFT +#undef CRF_APB_DPLL_CFG_LFHF_MASK +#define CRF_APB_DPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_DPLL_CFG_LFHF_MASK 0x00000C00U + +/* +* Lock circuit counter setting +*/ +#undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL +#undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT +#undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK +#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK 0x007FE000U + +/* +* Lock circuit configuration settings for lock windowsize +*/ +#undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL +#undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT +#undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK +#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK 0xFE000000U + +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ +#undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL +#undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT +#undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK +#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK 0x00700000U + +/* +* The integer portion of the feedback divider to the PLL +*/ +#undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL +#undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT +#undef CRF_APB_DPLL_CTRL_FBDIV_MASK +#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_DPLL_CTRL_FBDIV_MASK 0x00007F00U + +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ +#undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL +#undef CRF_APB_DPLL_CTRL_DIV2_SHIFT +#undef CRF_APB_DPLL_CTRL_DIV2_MASK +#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_DPLL_CTRL_DIV2_MASK 0x00010000U + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL +#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT +#undef CRF_APB_DPLL_CTRL_BYPASS_MASK +#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL +#undef CRF_APB_DPLL_CTRL_RESET_SHIFT +#undef CRF_APB_DPLL_CTRL_RESET_MASK +#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL +#undef CRF_APB_DPLL_CTRL_RESET_SHIFT +#undef CRF_APB_DPLL_CTRL_RESET_MASK +#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U + +/* +* DPLL is locked +*/ +#undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL +#undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT +#undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK +#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1 +#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 0x00000002U +#define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL +#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT +#undef CRF_APB_DPLL_CTRL_BYPASS_MASK +#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Divisor value for this clock. +*/ +#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* PLL loop filter resistor control +*/ +#undef CRF_APB_VPLL_CFG_RES_DEFVAL +#undef CRF_APB_VPLL_CFG_RES_SHIFT +#undef CRF_APB_VPLL_CFG_RES_MASK +#define CRF_APB_VPLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_RES_SHIFT 0 +#define CRF_APB_VPLL_CFG_RES_MASK 0x0000000FU + +/* +* PLL charge pump control +*/ +#undef CRF_APB_VPLL_CFG_CP_DEFVAL +#undef CRF_APB_VPLL_CFG_CP_SHIFT +#undef CRF_APB_VPLL_CFG_CP_MASK +#define CRF_APB_VPLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_CP_SHIFT 5 +#define CRF_APB_VPLL_CFG_CP_MASK 0x000001E0U + +/* +* PLL loop filter high frequency capacitor control +*/ +#undef CRF_APB_VPLL_CFG_LFHF_DEFVAL +#undef CRF_APB_VPLL_CFG_LFHF_SHIFT +#undef CRF_APB_VPLL_CFG_LFHF_MASK +#define CRF_APB_VPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_VPLL_CFG_LFHF_MASK 0x00000C00U + +/* +* Lock circuit counter setting +*/ +#undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL +#undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT +#undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK +#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK 0x007FE000U + +/* +* Lock circuit configuration settings for lock windowsize +*/ +#undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL +#undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT +#undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK +#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK 0xFE000000U + +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ +#undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL +#undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT +#undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK +#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK 0x00700000U + +/* +* The integer portion of the feedback divider to the PLL +*/ +#undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL +#undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT +#undef CRF_APB_VPLL_CTRL_FBDIV_MASK +#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_VPLL_CTRL_FBDIV_MASK 0x00007F00U + +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ +#undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL +#undef CRF_APB_VPLL_CTRL_DIV2_SHIFT +#undef CRF_APB_VPLL_CTRL_DIV2_MASK +#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_VPLL_CTRL_DIV2_MASK 0x00010000U + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL +#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT +#undef CRF_APB_VPLL_CTRL_BYPASS_MASK +#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL +#undef CRF_APB_VPLL_CTRL_RESET_SHIFT +#undef CRF_APB_VPLL_CTRL_RESET_MASK +#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL +#undef CRF_APB_VPLL_CTRL_RESET_SHIFT +#undef CRF_APB_VPLL_CTRL_RESET_MASK +#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U + +/* +* VPLL is locked +*/ +#undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL +#undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT +#undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK +#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2 +#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 0x00000004U +#define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL +#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT +#undef CRF_APB_VPLL_CTRL_BYPASS_MASK +#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Divisor value for this clock. +*/ +#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U +#undef CRL_APB_GEM3_REF_CTRL_OFFSET +#define CRL_APB_GEM3_REF_CTRL_OFFSET 0XFF5E005C +#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET +#define CRL_APB_GEM_TSU_REF_CTRL_OFFSET 0XFF5E0100 +#undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET +#define CRL_APB_USB0_BUS_REF_CTRL_OFFSET 0XFF5E0060 +#undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET +#define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 0XFF5E004C +#undef CRL_APB_QSPI_REF_CTRL_OFFSET +#define CRL_APB_QSPI_REF_CTRL_OFFSET 0XFF5E0068 +#undef CRL_APB_SDIO1_REF_CTRL_OFFSET +#define CRL_APB_SDIO1_REF_CTRL_OFFSET 0XFF5E0070 +#undef IOU_SLCR_SDIO_CLK_CTRL_OFFSET +#define IOU_SLCR_SDIO_CLK_CTRL_OFFSET 0XFF18030C +#undef CRL_APB_UART0_REF_CTRL_OFFSET +#define CRL_APB_UART0_REF_CTRL_OFFSET 0XFF5E0074 +#undef CRL_APB_UART1_REF_CTRL_OFFSET +#define CRL_APB_UART1_REF_CTRL_OFFSET 0XFF5E0078 +#undef CRL_APB_I2C0_REF_CTRL_OFFSET +#define CRL_APB_I2C0_REF_CTRL_OFFSET 0XFF5E0120 +#undef CRL_APB_I2C1_REF_CTRL_OFFSET +#define CRL_APB_I2C1_REF_CTRL_OFFSET 0XFF5E0124 +#undef CRL_APB_CAN1_REF_CTRL_OFFSET +#define CRL_APB_CAN1_REF_CTRL_OFFSET 0XFF5E0088 +#undef CRL_APB_CPU_R5_CTRL_OFFSET +#define CRL_APB_CPU_R5_CTRL_OFFSET 0XFF5E0090 +#undef CRL_APB_IOU_SWITCH_CTRL_OFFSET +#define CRL_APB_IOU_SWITCH_CTRL_OFFSET 0XFF5E009C +#undef CRL_APB_PCAP_CTRL_OFFSET +#define CRL_APB_PCAP_CTRL_OFFSET 0XFF5E00A4 +#undef CRL_APB_LPD_SWITCH_CTRL_OFFSET +#define CRL_APB_LPD_SWITCH_CTRL_OFFSET 0XFF5E00A8 +#undef CRL_APB_LPD_LSBUS_CTRL_OFFSET +#define CRL_APB_LPD_LSBUS_CTRL_OFFSET 0XFF5E00AC +#undef CRL_APB_DBG_LPD_CTRL_OFFSET +#define CRL_APB_DBG_LPD_CTRL_OFFSET 0XFF5E00B0 +#undef CRL_APB_ADMA_REF_CTRL_OFFSET +#define CRL_APB_ADMA_REF_CTRL_OFFSET 0XFF5E00B8 +#undef CRL_APB_PL0_REF_CTRL_OFFSET +#define CRL_APB_PL0_REF_CTRL_OFFSET 0XFF5E00C0 +#undef CRL_APB_PL1_REF_CTRL_OFFSET +#define CRL_APB_PL1_REF_CTRL_OFFSET 0XFF5E00C4 +#undef CRL_APB_AMS_REF_CTRL_OFFSET +#define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108 +#undef CRL_APB_DLL_REF_CTRL_OFFSET +#define CRL_APB_DLL_REF_CTRL_OFFSET 0XFF5E0104 +#undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET +#define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 0XFF5E0128 +#undef CRF_APB_SATA_REF_CTRL_OFFSET +#define CRF_APB_SATA_REF_CTRL_OFFSET 0XFD1A00A0 +#undef CRF_APB_PCIE_REF_CTRL_OFFSET +#define CRF_APB_PCIE_REF_CTRL_OFFSET 0XFD1A00B4 +#undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET +#define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 0XFD1A0070 +#undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET +#define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET 0XFD1A0074 +#undef CRF_APB_DP_STC_REF_CTRL_OFFSET +#define CRF_APB_DP_STC_REF_CTRL_OFFSET 0XFD1A007C +#undef CRF_APB_ACPU_CTRL_OFFSET +#define CRF_APB_ACPU_CTRL_OFFSET 0XFD1A0060 +#undef CRF_APB_DBG_FPD_CTRL_OFFSET +#define CRF_APB_DBG_FPD_CTRL_OFFSET 0XFD1A0068 +#undef CRF_APB_DDR_CTRL_OFFSET +#define CRF_APB_DDR_CTRL_OFFSET 0XFD1A0080 +#undef CRF_APB_GPU_REF_CTRL_OFFSET +#define CRF_APB_GPU_REF_CTRL_OFFSET 0XFD1A0084 +#undef CRF_APB_GDMA_REF_CTRL_OFFSET +#define CRF_APB_GDMA_REF_CTRL_OFFSET 0XFD1A00B8 +#undef CRF_APB_DPDMA_REF_CTRL_OFFSET +#define CRF_APB_DPDMA_REF_CTRL_OFFSET 0XFD1A00BC +#undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET +#define CRF_APB_TOPSW_MAIN_CTRL_OFFSET 0XFD1A00C0 +#undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET +#define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 0XFD1A00C4 +#undef CRF_APB_DBG_TSTMP_CTRL_OFFSET +#define CRF_APB_DBG_TSTMP_CTRL_OFFSET 0XFD1A00F8 +#undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET +#define IOU_SLCR_IOU_TTC_APB_CLK_OFFSET 0XFF180380 +#undef FPD_SLCR_WDT_CLK_SEL_OFFSET +#define FPD_SLCR_WDT_CLK_SEL_OFFSET 0XFD610100 +#undef IOU_SLCR_WDT_CLK_SEL_OFFSET +#define IOU_SLCR_WDT_CLK_SEL_OFFSET 0XFF180300 +#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 0XFF410050 + +/* +* Clock active for the RX channel +*/ +#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL +#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT +#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26 +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 0x04000000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK +#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 0x02000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 0x02000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 0x02000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK +#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO + * [51] 1: MIO [76] +*/ +#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL +#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT +#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17 +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK +#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK +#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK +#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK +#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK +#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK +#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK +#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Turing this off will shut down the OCM, some parts of the APM, and preve + * nt transactions going from the FPD to the LPD and could lead to system h + * ang +*/ +#undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL +#undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT +#undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK +#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT +#undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK +#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL +#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT +#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT +#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL +#undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT +#undef CRL_APB_PCAP_CTRL_CLKACT_MASK +#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PCAP_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK +#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT +#undef CRL_APB_PCAP_CTRL_SRCSEL_MASK +#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PCAP_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL +#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT +#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT +#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL +#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT +#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT +#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL +#undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT +#undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK +#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT +#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK +#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK +#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK +#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_PL1_REF_CTRL_CLKACT_MASK +#define CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PL1_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_PL1_REF_CTRL_SRCSEL_MASK +#define CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 6 bit divider +*/ +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK +#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK +#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an + * issue, but designers must be aware.) +*/ +#undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK +#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 0x00000000 +#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 6 bit divider +*/ +#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may + * only be toggled after 4 cycles of the old clock and 4 cycles of the new + * clock. This is not usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK +#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK +#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only + * be toggled after 4 cycles of the old clock and 4 cycles of the new cloc + * k. This is not usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK +#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL +#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT +#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) +*/ +#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL +#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT +#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) +*/ +#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL +#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT +#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg + * led after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK +#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT +#undef CRF_APB_ACPU_CTRL_SRCSEL_MASK +#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_ACPU_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock. For the half spee + * d APU Clock +*/ +#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL +#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT +#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25 +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 0x02000000U + +/* +* Clock active signal. Switch to 0 to disable the clock. For the full spee + * d ACPUX Clock. This will shut off the high speed clock to the entire APU +*/ +#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL +#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT +#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24 +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT +#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL +#undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT +#undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK +#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DDR_CTRL_DIVISOR0_MASK +#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DDR_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an i + * ssue, but designers must be aware.) +*/ +#undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT +#undef CRF_APB_DDR_CTRL_SRCSEL_MASK +#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DDR_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 6 bit divider +*/ +#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK +#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock, which will stop c + * lock for GPU (and both Pixel Processors). +*/ +#undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK +#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor +*/ +#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL +#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT +#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25 +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 0x02000000U + +/* +* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor +*/ +#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL +#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT +#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26 +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 0x04000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK +#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT +#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL +#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT +#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT +#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL +#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT +#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 0x00000A00 +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT +#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 0x00000A00 +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se + * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5 + * clock for the APB interface of TTC0 +*/ +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 0 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003U + +/* +* 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se + * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5 + * clock for the APB interface of TTC1 +*/ +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 2 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000CU + +/* +* 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se + * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5 + * clock for the APB interface of TTC2 +*/ +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 4 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030U + +/* +* 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se + * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5 + * clock for the APB interface of TTC3 +*/ +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 6 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 0x000000C0U + +/* +* System watchdog timer clock source selection: 0: Internal APB clock 1: E + * xternal (PL clock via EMIO or Pinout clock via MIO) +*/ +#undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL +#undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT +#undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK +#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 +#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U + +/* +* System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock from PL via EMIO, or from pinout via MIO +*/ +#undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL +#undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT +#undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK +#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 +#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U + +/* +* System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock pss_ref_clk +*/ +#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL +#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT +#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0 +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 0x00000001U +#undef CRF_APB_RST_DDR_SS_OFFSET +#define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108 +#undef DDRC_MSTR_OFFSET +#define DDRC_MSTR_OFFSET 0XFD070000 +#undef DDRC_MRCTRL0_OFFSET +#define DDRC_MRCTRL0_OFFSET 0XFD070010 +#undef DDRC_DERATEEN_OFFSET +#define DDRC_DERATEEN_OFFSET 0XFD070020 +#undef DDRC_DERATEINT_OFFSET +#define DDRC_DERATEINT_OFFSET 0XFD070024 +#undef DDRC_PWRCTL_OFFSET +#define DDRC_PWRCTL_OFFSET 0XFD070030 +#undef DDRC_PWRTMG_OFFSET +#define DDRC_PWRTMG_OFFSET 0XFD070034 +#undef DDRC_RFSHCTL0_OFFSET +#define DDRC_RFSHCTL0_OFFSET 0XFD070050 +#undef DDRC_RFSHCTL1_OFFSET +#define DDRC_RFSHCTL1_OFFSET 0XFD070054 +#undef DDRC_RFSHCTL3_OFFSET +#define DDRC_RFSHCTL3_OFFSET 0XFD070060 +#undef DDRC_RFSHTMG_OFFSET +#define DDRC_RFSHTMG_OFFSET 0XFD070064 +#undef DDRC_ECCCFG0_OFFSET +#define DDRC_ECCCFG0_OFFSET 0XFD070070 +#undef DDRC_ECCCFG1_OFFSET +#define DDRC_ECCCFG1_OFFSET 0XFD070074 +#undef DDRC_CRCPARCTL1_OFFSET +#define DDRC_CRCPARCTL1_OFFSET 0XFD0700C4 +#undef DDRC_CRCPARCTL2_OFFSET +#define DDRC_CRCPARCTL2_OFFSET 0XFD0700C8 +#undef DDRC_INIT0_OFFSET +#define DDRC_INIT0_OFFSET 0XFD0700D0 +#undef DDRC_INIT1_OFFSET +#define DDRC_INIT1_OFFSET 0XFD0700D4 +#undef DDRC_INIT2_OFFSET +#define DDRC_INIT2_OFFSET 0XFD0700D8 +#undef DDRC_INIT3_OFFSET +#define DDRC_INIT3_OFFSET 0XFD0700DC +#undef DDRC_INIT4_OFFSET +#define DDRC_INIT4_OFFSET 0XFD0700E0 +#undef DDRC_INIT5_OFFSET +#define DDRC_INIT5_OFFSET 0XFD0700E4 +#undef DDRC_INIT6_OFFSET +#define DDRC_INIT6_OFFSET 0XFD0700E8 +#undef DDRC_INIT7_OFFSET +#define DDRC_INIT7_OFFSET 0XFD0700EC +#undef DDRC_DIMMCTL_OFFSET +#define DDRC_DIMMCTL_OFFSET 0XFD0700F0 +#undef DDRC_RANKCTL_OFFSET +#define DDRC_RANKCTL_OFFSET 0XFD0700F4 +#undef DDRC_DRAMTMG0_OFFSET +#define DDRC_DRAMTMG0_OFFSET 0XFD070100 +#undef DDRC_DRAMTMG1_OFFSET +#define DDRC_DRAMTMG1_OFFSET 0XFD070104 +#undef DDRC_DRAMTMG2_OFFSET +#define DDRC_DRAMTMG2_OFFSET 0XFD070108 +#undef DDRC_DRAMTMG3_OFFSET +#define DDRC_DRAMTMG3_OFFSET 0XFD07010C +#undef DDRC_DRAMTMG4_OFFSET +#define DDRC_DRAMTMG4_OFFSET 0XFD070110 +#undef DDRC_DRAMTMG5_OFFSET +#define DDRC_DRAMTMG5_OFFSET 0XFD070114 +#undef DDRC_DRAMTMG6_OFFSET +#define DDRC_DRAMTMG6_OFFSET 0XFD070118 +#undef DDRC_DRAMTMG7_OFFSET +#define DDRC_DRAMTMG7_OFFSET 0XFD07011C +#undef DDRC_DRAMTMG8_OFFSET +#define DDRC_DRAMTMG8_OFFSET 0XFD070120 +#undef DDRC_DRAMTMG9_OFFSET +#define DDRC_DRAMTMG9_OFFSET 0XFD070124 +#undef DDRC_DRAMTMG11_OFFSET +#define DDRC_DRAMTMG11_OFFSET 0XFD07012C +#undef DDRC_DRAMTMG12_OFFSET +#define DDRC_DRAMTMG12_OFFSET 0XFD070130 +#undef DDRC_ZQCTL0_OFFSET +#define DDRC_ZQCTL0_OFFSET 0XFD070180 +#undef DDRC_ZQCTL1_OFFSET +#define DDRC_ZQCTL1_OFFSET 0XFD070184 +#undef DDRC_DFITMG0_OFFSET +#define DDRC_DFITMG0_OFFSET 0XFD070190 +#undef DDRC_DFITMG1_OFFSET +#define DDRC_DFITMG1_OFFSET 0XFD070194 +#undef DDRC_DFILPCFG0_OFFSET +#define DDRC_DFILPCFG0_OFFSET 0XFD070198 +#undef DDRC_DFILPCFG1_OFFSET +#define DDRC_DFILPCFG1_OFFSET 0XFD07019C +#undef DDRC_DFIUPD0_OFFSET +#define DDRC_DFIUPD0_OFFSET 0XFD0701A0 +#undef DDRC_DFIUPD1_OFFSET +#define DDRC_DFIUPD1_OFFSET 0XFD0701A4 +#undef DDRC_DFIMISC_OFFSET +#define DDRC_DFIMISC_OFFSET 0XFD0701B0 +#undef DDRC_DFITMG2_OFFSET +#define DDRC_DFITMG2_OFFSET 0XFD0701B4 +#undef DDRC_DBICTL_OFFSET +#define DDRC_DBICTL_OFFSET 0XFD0701C0 +#undef DDRC_ADDRMAP0_OFFSET +#define DDRC_ADDRMAP0_OFFSET 0XFD070200 +#undef DDRC_ADDRMAP1_OFFSET +#define DDRC_ADDRMAP1_OFFSET 0XFD070204 +#undef DDRC_ADDRMAP2_OFFSET +#define DDRC_ADDRMAP2_OFFSET 0XFD070208 +#undef DDRC_ADDRMAP3_OFFSET +#define DDRC_ADDRMAP3_OFFSET 0XFD07020C +#undef DDRC_ADDRMAP4_OFFSET +#define DDRC_ADDRMAP4_OFFSET 0XFD070210 +#undef DDRC_ADDRMAP5_OFFSET +#define DDRC_ADDRMAP5_OFFSET 0XFD070214 +#undef DDRC_ADDRMAP6_OFFSET +#define DDRC_ADDRMAP6_OFFSET 0XFD070218 +#undef DDRC_ADDRMAP7_OFFSET +#define DDRC_ADDRMAP7_OFFSET 0XFD07021C +#undef DDRC_ADDRMAP8_OFFSET +#define DDRC_ADDRMAP8_OFFSET 0XFD070220 +#undef DDRC_ADDRMAP9_OFFSET +#define DDRC_ADDRMAP9_OFFSET 0XFD070224 +#undef DDRC_ADDRMAP10_OFFSET +#define DDRC_ADDRMAP10_OFFSET 0XFD070228 +#undef DDRC_ADDRMAP11_OFFSET +#define DDRC_ADDRMAP11_OFFSET 0XFD07022C +#undef DDRC_ODTCFG_OFFSET +#define DDRC_ODTCFG_OFFSET 0XFD070240 +#undef DDRC_ODTMAP_OFFSET +#define DDRC_ODTMAP_OFFSET 0XFD070244 +#undef DDRC_SCHED_OFFSET +#define DDRC_SCHED_OFFSET 0XFD070250 +#undef DDRC_PERFLPR1_OFFSET +#define DDRC_PERFLPR1_OFFSET 0XFD070264 +#undef DDRC_PERFWR1_OFFSET +#define DDRC_PERFWR1_OFFSET 0XFD07026C +#undef DDRC_DQMAP0_OFFSET +#define DDRC_DQMAP0_OFFSET 0XFD070280 +#undef DDRC_DQMAP1_OFFSET +#define DDRC_DQMAP1_OFFSET 0XFD070284 +#undef DDRC_DQMAP2_OFFSET +#define DDRC_DQMAP2_OFFSET 0XFD070288 +#undef DDRC_DQMAP3_OFFSET +#define DDRC_DQMAP3_OFFSET 0XFD07028C +#undef DDRC_DQMAP4_OFFSET +#define DDRC_DQMAP4_OFFSET 0XFD070290 +#undef DDRC_DQMAP5_OFFSET +#define DDRC_DQMAP5_OFFSET 0XFD070294 +#undef DDRC_DBG0_OFFSET +#define DDRC_DBG0_OFFSET 0XFD070300 +#undef DDRC_DBGCMD_OFFSET +#define DDRC_DBGCMD_OFFSET 0XFD07030C +#undef DDRC_SWCTL_OFFSET +#define DDRC_SWCTL_OFFSET 0XFD070320 +#undef DDRC_PCCFG_OFFSET +#define DDRC_PCCFG_OFFSET 0XFD070400 +#undef DDRC_PCFGR_0_OFFSET +#define DDRC_PCFGR_0_OFFSET 0XFD070404 +#undef DDRC_PCFGW_0_OFFSET +#define DDRC_PCFGW_0_OFFSET 0XFD070408 +#undef DDRC_PCTRL_0_OFFSET +#define DDRC_PCTRL_0_OFFSET 0XFD070490 +#undef DDRC_PCFGQOS0_0_OFFSET +#define DDRC_PCFGQOS0_0_OFFSET 0XFD070494 +#undef DDRC_PCFGQOS1_0_OFFSET +#define DDRC_PCFGQOS1_0_OFFSET 0XFD070498 +#undef DDRC_PCFGR_1_OFFSET +#define DDRC_PCFGR_1_OFFSET 0XFD0704B4 +#undef DDRC_PCFGW_1_OFFSET +#define DDRC_PCFGW_1_OFFSET 0XFD0704B8 +#undef DDRC_PCTRL_1_OFFSET +#define DDRC_PCTRL_1_OFFSET 0XFD070540 +#undef DDRC_PCFGQOS0_1_OFFSET +#define DDRC_PCFGQOS0_1_OFFSET 0XFD070544 +#undef DDRC_PCFGQOS1_1_OFFSET +#define DDRC_PCFGQOS1_1_OFFSET 0XFD070548 +#undef DDRC_PCFGR_2_OFFSET +#define DDRC_PCFGR_2_OFFSET 0XFD070564 +#undef DDRC_PCFGW_2_OFFSET +#define DDRC_PCFGW_2_OFFSET 0XFD070568 +#undef DDRC_PCTRL_2_OFFSET +#define DDRC_PCTRL_2_OFFSET 0XFD0705F0 +#undef DDRC_PCFGQOS0_2_OFFSET +#define DDRC_PCFGQOS0_2_OFFSET 0XFD0705F4 +#undef DDRC_PCFGQOS1_2_OFFSET +#define DDRC_PCFGQOS1_2_OFFSET 0XFD0705F8 +#undef DDRC_PCFGR_3_OFFSET +#define DDRC_PCFGR_3_OFFSET 0XFD070614 +#undef DDRC_PCFGW_3_OFFSET +#define DDRC_PCFGW_3_OFFSET 0XFD070618 +#undef DDRC_PCTRL_3_OFFSET +#define DDRC_PCTRL_3_OFFSET 0XFD0706A0 +#undef DDRC_PCFGQOS0_3_OFFSET +#define DDRC_PCFGQOS0_3_OFFSET 0XFD0706A4 +#undef DDRC_PCFGQOS1_3_OFFSET +#define DDRC_PCFGQOS1_3_OFFSET 0XFD0706A8 +#undef DDRC_PCFGWQOS0_3_OFFSET +#define DDRC_PCFGWQOS0_3_OFFSET 0XFD0706AC +#undef DDRC_PCFGWQOS1_3_OFFSET +#define DDRC_PCFGWQOS1_3_OFFSET 0XFD0706B0 +#undef DDRC_PCFGR_4_OFFSET +#define DDRC_PCFGR_4_OFFSET 0XFD0706C4 +#undef DDRC_PCFGW_4_OFFSET +#define DDRC_PCFGW_4_OFFSET 0XFD0706C8 +#undef DDRC_PCTRL_4_OFFSET +#define DDRC_PCTRL_4_OFFSET 0XFD070750 +#undef DDRC_PCFGQOS0_4_OFFSET +#define DDRC_PCFGQOS0_4_OFFSET 0XFD070754 +#undef DDRC_PCFGQOS1_4_OFFSET +#define DDRC_PCFGQOS1_4_OFFSET 0XFD070758 +#undef DDRC_PCFGWQOS0_4_OFFSET +#define DDRC_PCFGWQOS0_4_OFFSET 0XFD07075C +#undef DDRC_PCFGWQOS1_4_OFFSET +#define DDRC_PCFGWQOS1_4_OFFSET 0XFD070760 +#undef DDRC_PCFGR_5_OFFSET +#define DDRC_PCFGR_5_OFFSET 0XFD070774 +#undef DDRC_PCFGW_5_OFFSET +#define DDRC_PCFGW_5_OFFSET 0XFD070778 +#undef DDRC_PCTRL_5_OFFSET +#define DDRC_PCTRL_5_OFFSET 0XFD070800 +#undef DDRC_PCFGQOS0_5_OFFSET +#define DDRC_PCFGQOS0_5_OFFSET 0XFD070804 +#undef DDRC_PCFGQOS1_5_OFFSET +#define DDRC_PCFGQOS1_5_OFFSET 0XFD070808 +#undef DDRC_PCFGWQOS0_5_OFFSET +#define DDRC_PCFGWQOS0_5_OFFSET 0XFD07080C +#undef DDRC_PCFGWQOS1_5_OFFSET +#define DDRC_PCFGWQOS1_5_OFFSET 0XFD070810 +#undef DDRC_SARBASE0_OFFSET +#define DDRC_SARBASE0_OFFSET 0XFD070F04 +#undef DDRC_SARSIZE0_OFFSET +#define DDRC_SARSIZE0_OFFSET 0XFD070F08 +#undef DDRC_SARBASE1_OFFSET +#define DDRC_SARBASE1_OFFSET 0XFD070F0C +#undef DDRC_SARSIZE1_OFFSET +#define DDRC_SARSIZE1_OFFSET 0XFD070F10 +#undef DDRC_DFITMG0_SHADOW_OFFSET +#define DDRC_DFITMG0_SHADOW_OFFSET 0XFD072190 +#undef CRF_APB_RST_DDR_SS_OFFSET +#define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108 +#undef DDR_PHY_PGCR0_OFFSET +#define DDR_PHY_PGCR0_OFFSET 0XFD080010 +#undef DDR_PHY_PGCR2_OFFSET +#define DDR_PHY_PGCR2_OFFSET 0XFD080018 +#undef DDR_PHY_PGCR3_OFFSET +#define DDR_PHY_PGCR3_OFFSET 0XFD08001C +#undef DDR_PHY_PGCR5_OFFSET +#define DDR_PHY_PGCR5_OFFSET 0XFD080024 +#undef DDR_PHY_PTR0_OFFSET +#define DDR_PHY_PTR0_OFFSET 0XFD080040 +#undef DDR_PHY_PTR1_OFFSET +#define DDR_PHY_PTR1_OFFSET 0XFD080044 +#undef DDR_PHY_PLLCR0_OFFSET +#define DDR_PHY_PLLCR0_OFFSET 0XFD080068 +#undef DDR_PHY_DSGCR_OFFSET +#define DDR_PHY_DSGCR_OFFSET 0XFD080090 +#undef DDR_PHY_GPR0_OFFSET +#define DDR_PHY_GPR0_OFFSET 0XFD0800C0 +#undef DDR_PHY_GPR1_OFFSET +#define DDR_PHY_GPR1_OFFSET 0XFD0800C4 +#undef DDR_PHY_DCR_OFFSET +#define DDR_PHY_DCR_OFFSET 0XFD080100 +#undef DDR_PHY_DTPR0_OFFSET +#define DDR_PHY_DTPR0_OFFSET 0XFD080110 +#undef DDR_PHY_DTPR1_OFFSET +#define DDR_PHY_DTPR1_OFFSET 0XFD080114 +#undef DDR_PHY_DTPR2_OFFSET +#define DDR_PHY_DTPR2_OFFSET 0XFD080118 +#undef DDR_PHY_DTPR3_OFFSET +#define DDR_PHY_DTPR3_OFFSET 0XFD08011C +#undef DDR_PHY_DTPR4_OFFSET +#define DDR_PHY_DTPR4_OFFSET 0XFD080120 +#undef DDR_PHY_DTPR5_OFFSET +#define DDR_PHY_DTPR5_OFFSET 0XFD080124 +#undef DDR_PHY_DTPR6_OFFSET +#define DDR_PHY_DTPR6_OFFSET 0XFD080128 +#undef DDR_PHY_RDIMMGCR0_OFFSET +#define DDR_PHY_RDIMMGCR0_OFFSET 0XFD080140 +#undef DDR_PHY_RDIMMGCR1_OFFSET +#define DDR_PHY_RDIMMGCR1_OFFSET 0XFD080144 +#undef DDR_PHY_RDIMMCR0_OFFSET +#define DDR_PHY_RDIMMCR0_OFFSET 0XFD080150 +#undef DDR_PHY_RDIMMCR1_OFFSET +#define DDR_PHY_RDIMMCR1_OFFSET 0XFD080154 +#undef DDR_PHY_MR0_OFFSET +#define DDR_PHY_MR0_OFFSET 0XFD080180 +#undef DDR_PHY_MR1_OFFSET +#define DDR_PHY_MR1_OFFSET 0XFD080184 +#undef DDR_PHY_MR2_OFFSET +#define DDR_PHY_MR2_OFFSET 0XFD080188 +#undef DDR_PHY_MR3_OFFSET +#define DDR_PHY_MR3_OFFSET 0XFD08018C +#undef DDR_PHY_MR4_OFFSET +#define DDR_PHY_MR4_OFFSET 0XFD080190 +#undef DDR_PHY_MR5_OFFSET +#define DDR_PHY_MR5_OFFSET 0XFD080194 +#undef DDR_PHY_MR6_OFFSET +#define DDR_PHY_MR6_OFFSET 0XFD080198 +#undef DDR_PHY_MR11_OFFSET +#define DDR_PHY_MR11_OFFSET 0XFD0801AC +#undef DDR_PHY_MR12_OFFSET +#define DDR_PHY_MR12_OFFSET 0XFD0801B0 +#undef DDR_PHY_MR13_OFFSET +#define DDR_PHY_MR13_OFFSET 0XFD0801B4 +#undef DDR_PHY_MR14_OFFSET +#define DDR_PHY_MR14_OFFSET 0XFD0801B8 +#undef DDR_PHY_MR22_OFFSET +#define DDR_PHY_MR22_OFFSET 0XFD0801D8 +#undef DDR_PHY_DTCR0_OFFSET +#define DDR_PHY_DTCR0_OFFSET 0XFD080200 +#undef DDR_PHY_DTCR1_OFFSET +#define DDR_PHY_DTCR1_OFFSET 0XFD080204 +#undef DDR_PHY_CATR0_OFFSET +#define DDR_PHY_CATR0_OFFSET 0XFD080240 +#undef DDR_PHY_DQSDR0_OFFSET +#define DDR_PHY_DQSDR0_OFFSET 0XFD080250 +#undef DDR_PHY_BISTLSR_OFFSET +#define DDR_PHY_BISTLSR_OFFSET 0XFD080414 +#undef DDR_PHY_RIOCR5_OFFSET +#define DDR_PHY_RIOCR5_OFFSET 0XFD0804F4 +#undef DDR_PHY_ACIOCR0_OFFSET +#define DDR_PHY_ACIOCR0_OFFSET 0XFD080500 +#undef DDR_PHY_ACIOCR2_OFFSET +#define DDR_PHY_ACIOCR2_OFFSET 0XFD080508 +#undef DDR_PHY_ACIOCR3_OFFSET +#define DDR_PHY_ACIOCR3_OFFSET 0XFD08050C +#undef DDR_PHY_ACIOCR4_OFFSET +#define DDR_PHY_ACIOCR4_OFFSET 0XFD080510 +#undef DDR_PHY_IOVCR0_OFFSET +#define DDR_PHY_IOVCR0_OFFSET 0XFD080520 +#undef DDR_PHY_VTCR0_OFFSET +#define DDR_PHY_VTCR0_OFFSET 0XFD080528 +#undef DDR_PHY_VTCR1_OFFSET +#define DDR_PHY_VTCR1_OFFSET 0XFD08052C +#undef DDR_PHY_ACBDLR1_OFFSET +#define DDR_PHY_ACBDLR1_OFFSET 0XFD080544 +#undef DDR_PHY_ACBDLR2_OFFSET +#define DDR_PHY_ACBDLR2_OFFSET 0XFD080548 +#undef DDR_PHY_ACBDLR6_OFFSET +#define DDR_PHY_ACBDLR6_OFFSET 0XFD080558 +#undef DDR_PHY_ACBDLR7_OFFSET +#define DDR_PHY_ACBDLR7_OFFSET 0XFD08055C +#undef DDR_PHY_ACBDLR8_OFFSET +#define DDR_PHY_ACBDLR8_OFFSET 0XFD080560 +#undef DDR_PHY_ACBDLR9_OFFSET +#define DDR_PHY_ACBDLR9_OFFSET 0XFD080564 +#undef DDR_PHY_ZQCR_OFFSET +#define DDR_PHY_ZQCR_OFFSET 0XFD080680 +#undef DDR_PHY_ZQ0PR0_OFFSET +#define DDR_PHY_ZQ0PR0_OFFSET 0XFD080684 +#undef DDR_PHY_ZQ0OR0_OFFSET +#define DDR_PHY_ZQ0OR0_OFFSET 0XFD080694 +#undef DDR_PHY_ZQ0OR1_OFFSET +#define DDR_PHY_ZQ0OR1_OFFSET 0XFD080698 +#undef DDR_PHY_ZQ1PR0_OFFSET +#define DDR_PHY_ZQ1PR0_OFFSET 0XFD0806A4 +#undef DDR_PHY_DX0GCR0_OFFSET +#define DDR_PHY_DX0GCR0_OFFSET 0XFD080700 +#undef DDR_PHY_DX0GCR1_OFFSET +#define DDR_PHY_DX0GCR1_OFFSET 0XFD080704 +#undef DDR_PHY_DX0GCR3_OFFSET +#define DDR_PHY_DX0GCR3_OFFSET 0XFD08070C +#undef DDR_PHY_DX0GCR4_OFFSET +#define DDR_PHY_DX0GCR4_OFFSET 0XFD080710 +#undef DDR_PHY_DX0GCR5_OFFSET +#define DDR_PHY_DX0GCR5_OFFSET 0XFD080714 +#undef DDR_PHY_DX0GCR6_OFFSET +#define DDR_PHY_DX0GCR6_OFFSET 0XFD080718 +#undef DDR_PHY_DX1GCR0_OFFSET +#define DDR_PHY_DX1GCR0_OFFSET 0XFD080800 +#undef DDR_PHY_DX1GCR1_OFFSET +#define DDR_PHY_DX1GCR1_OFFSET 0XFD080804 +#undef DDR_PHY_DX1GCR3_OFFSET +#define DDR_PHY_DX1GCR3_OFFSET 0XFD08080C +#undef DDR_PHY_DX1GCR4_OFFSET +#define DDR_PHY_DX1GCR4_OFFSET 0XFD080810 +#undef DDR_PHY_DX1GCR5_OFFSET +#define DDR_PHY_DX1GCR5_OFFSET 0XFD080814 +#undef DDR_PHY_DX1GCR6_OFFSET +#define DDR_PHY_DX1GCR6_OFFSET 0XFD080818 +#undef DDR_PHY_DX2GCR0_OFFSET +#define DDR_PHY_DX2GCR0_OFFSET 0XFD080900 +#undef DDR_PHY_DX2GCR1_OFFSET +#define DDR_PHY_DX2GCR1_OFFSET 0XFD080904 +#undef DDR_PHY_DX2GCR3_OFFSET +#define DDR_PHY_DX2GCR3_OFFSET 0XFD08090C +#undef DDR_PHY_DX2GCR4_OFFSET +#define DDR_PHY_DX2GCR4_OFFSET 0XFD080910 +#undef DDR_PHY_DX2GCR5_OFFSET +#define DDR_PHY_DX2GCR5_OFFSET 0XFD080914 +#undef DDR_PHY_DX2GCR6_OFFSET +#define DDR_PHY_DX2GCR6_OFFSET 0XFD080918 +#undef DDR_PHY_DX3GCR0_OFFSET +#define DDR_PHY_DX3GCR0_OFFSET 0XFD080A00 +#undef DDR_PHY_DX3GCR1_OFFSET +#define DDR_PHY_DX3GCR1_OFFSET 0XFD080A04 +#undef DDR_PHY_DX3GCR3_OFFSET +#define DDR_PHY_DX3GCR3_OFFSET 0XFD080A0C +#undef DDR_PHY_DX3GCR4_OFFSET +#define DDR_PHY_DX3GCR4_OFFSET 0XFD080A10 +#undef DDR_PHY_DX3GCR5_OFFSET +#define DDR_PHY_DX3GCR5_OFFSET 0XFD080A14 +#undef DDR_PHY_DX3GCR6_OFFSET +#define DDR_PHY_DX3GCR6_OFFSET 0XFD080A18 +#undef DDR_PHY_DX4GCR0_OFFSET +#define DDR_PHY_DX4GCR0_OFFSET 0XFD080B00 +#undef DDR_PHY_DX4GCR1_OFFSET +#define DDR_PHY_DX4GCR1_OFFSET 0XFD080B04 +#undef DDR_PHY_DX4GCR2_OFFSET +#define DDR_PHY_DX4GCR2_OFFSET 0XFD080B08 +#undef DDR_PHY_DX4GCR3_OFFSET +#define DDR_PHY_DX4GCR3_OFFSET 0XFD080B0C +#undef DDR_PHY_DX4GCR4_OFFSET +#define DDR_PHY_DX4GCR4_OFFSET 0XFD080B10 +#undef DDR_PHY_DX4GCR5_OFFSET +#define DDR_PHY_DX4GCR5_OFFSET 0XFD080B14 +#undef DDR_PHY_DX4GCR6_OFFSET +#define DDR_PHY_DX4GCR6_OFFSET 0XFD080B18 +#undef DDR_PHY_DX5GCR0_OFFSET +#define DDR_PHY_DX5GCR0_OFFSET 0XFD080C00 +#undef DDR_PHY_DX5GCR1_OFFSET +#define DDR_PHY_DX5GCR1_OFFSET 0XFD080C04 +#undef DDR_PHY_DX5GCR2_OFFSET +#define DDR_PHY_DX5GCR2_OFFSET 0XFD080C08 +#undef DDR_PHY_DX5GCR3_OFFSET +#define DDR_PHY_DX5GCR3_OFFSET 0XFD080C0C +#undef DDR_PHY_DX5GCR4_OFFSET +#define DDR_PHY_DX5GCR4_OFFSET 0XFD080C10 +#undef DDR_PHY_DX5GCR5_OFFSET +#define DDR_PHY_DX5GCR5_OFFSET 0XFD080C14 +#undef DDR_PHY_DX5GCR6_OFFSET +#define DDR_PHY_DX5GCR6_OFFSET 0XFD080C18 +#undef DDR_PHY_DX6GCR0_OFFSET +#define DDR_PHY_DX6GCR0_OFFSET 0XFD080D00 +#undef DDR_PHY_DX6GCR1_OFFSET +#define DDR_PHY_DX6GCR1_OFFSET 0XFD080D04 +#undef DDR_PHY_DX6GCR2_OFFSET +#define DDR_PHY_DX6GCR2_OFFSET 0XFD080D08 +#undef DDR_PHY_DX6GCR3_OFFSET +#define DDR_PHY_DX6GCR3_OFFSET 0XFD080D0C +#undef DDR_PHY_DX6GCR4_OFFSET +#define DDR_PHY_DX6GCR4_OFFSET 0XFD080D10 +#undef DDR_PHY_DX6GCR5_OFFSET +#define DDR_PHY_DX6GCR5_OFFSET 0XFD080D14 +#undef DDR_PHY_DX6GCR6_OFFSET +#define DDR_PHY_DX6GCR6_OFFSET 0XFD080D18 +#undef DDR_PHY_DX7GCR0_OFFSET +#define DDR_PHY_DX7GCR0_OFFSET 0XFD080E00 +#undef DDR_PHY_DX7GCR1_OFFSET +#define DDR_PHY_DX7GCR1_OFFSET 0XFD080E04 +#undef DDR_PHY_DX7GCR2_OFFSET +#define DDR_PHY_DX7GCR2_OFFSET 0XFD080E08 +#undef DDR_PHY_DX7GCR3_OFFSET +#define DDR_PHY_DX7GCR3_OFFSET 0XFD080E0C +#undef DDR_PHY_DX7GCR4_OFFSET +#define DDR_PHY_DX7GCR4_OFFSET 0XFD080E10 +#undef DDR_PHY_DX7GCR5_OFFSET +#define DDR_PHY_DX7GCR5_OFFSET 0XFD080E14 +#undef DDR_PHY_DX7GCR6_OFFSET +#define DDR_PHY_DX7GCR6_OFFSET 0XFD080E18 +#undef DDR_PHY_DX8GCR0_OFFSET +#define DDR_PHY_DX8GCR0_OFFSET 0XFD080F00 +#undef DDR_PHY_DX8GCR1_OFFSET +#define DDR_PHY_DX8GCR1_OFFSET 0XFD080F04 +#undef DDR_PHY_DX8GCR2_OFFSET +#define DDR_PHY_DX8GCR2_OFFSET 0XFD080F08 +#undef DDR_PHY_DX8GCR3_OFFSET +#define DDR_PHY_DX8GCR3_OFFSET 0XFD080F0C +#undef DDR_PHY_DX8GCR4_OFFSET +#define DDR_PHY_DX8GCR4_OFFSET 0XFD080F10 +#undef DDR_PHY_DX8GCR5_OFFSET +#define DDR_PHY_DX8GCR5_OFFSET 0XFD080F14 +#undef DDR_PHY_DX8GCR6_OFFSET +#define DDR_PHY_DX8GCR6_OFFSET 0XFD080F18 +#undef DDR_PHY_DX8SL0OSC_OFFSET +#define DDR_PHY_DX8SL0OSC_OFFSET 0XFD081400 +#undef DDR_PHY_DX8SL0PLLCR0_OFFSET +#define DDR_PHY_DX8SL0PLLCR0_OFFSET 0XFD081404 +#undef DDR_PHY_DX8SL0DQSCTL_OFFSET +#define DDR_PHY_DX8SL0DQSCTL_OFFSET 0XFD08141C +#undef DDR_PHY_DX8SL0DXCTL2_OFFSET +#define DDR_PHY_DX8SL0DXCTL2_OFFSET 0XFD08142C +#undef DDR_PHY_DX8SL0IOCR_OFFSET +#define DDR_PHY_DX8SL0IOCR_OFFSET 0XFD081430 +#undef DDR_PHY_DX8SL1OSC_OFFSET +#define DDR_PHY_DX8SL1OSC_OFFSET 0XFD081440 +#undef DDR_PHY_DX8SL1PLLCR0_OFFSET +#define DDR_PHY_DX8SL1PLLCR0_OFFSET 0XFD081444 +#undef DDR_PHY_DX8SL1DQSCTL_OFFSET +#define DDR_PHY_DX8SL1DQSCTL_OFFSET 0XFD08145C +#undef DDR_PHY_DX8SL1DXCTL2_OFFSET +#define DDR_PHY_DX8SL1DXCTL2_OFFSET 0XFD08146C +#undef DDR_PHY_DX8SL1IOCR_OFFSET +#define DDR_PHY_DX8SL1IOCR_OFFSET 0XFD081470 +#undef DDR_PHY_DX8SL2OSC_OFFSET +#define DDR_PHY_DX8SL2OSC_OFFSET 0XFD081480 +#undef DDR_PHY_DX8SL2PLLCR0_OFFSET +#define DDR_PHY_DX8SL2PLLCR0_OFFSET 0XFD081484 +#undef DDR_PHY_DX8SL2DQSCTL_OFFSET +#define DDR_PHY_DX8SL2DQSCTL_OFFSET 0XFD08149C +#undef DDR_PHY_DX8SL2DXCTL2_OFFSET +#define DDR_PHY_DX8SL2DXCTL2_OFFSET 0XFD0814AC +#undef DDR_PHY_DX8SL2IOCR_OFFSET +#define DDR_PHY_DX8SL2IOCR_OFFSET 0XFD0814B0 +#undef DDR_PHY_DX8SL3OSC_OFFSET +#define DDR_PHY_DX8SL3OSC_OFFSET 0XFD0814C0 +#undef DDR_PHY_DX8SL3PLLCR0_OFFSET +#define DDR_PHY_DX8SL3PLLCR0_OFFSET 0XFD0814C4 +#undef DDR_PHY_DX8SL3DQSCTL_OFFSET +#define DDR_PHY_DX8SL3DQSCTL_OFFSET 0XFD0814DC +#undef DDR_PHY_DX8SL3DXCTL2_OFFSET +#define DDR_PHY_DX8SL3DXCTL2_OFFSET 0XFD0814EC +#undef DDR_PHY_DX8SL3IOCR_OFFSET +#define DDR_PHY_DX8SL3IOCR_OFFSET 0XFD0814F0 +#undef DDR_PHY_DX8SL4OSC_OFFSET +#define DDR_PHY_DX8SL4OSC_OFFSET 0XFD081500 +#undef DDR_PHY_DX8SL4PLLCR0_OFFSET +#define DDR_PHY_DX8SL4PLLCR0_OFFSET 0XFD081504 +#undef DDR_PHY_DX8SL4DQSCTL_OFFSET +#define DDR_PHY_DX8SL4DQSCTL_OFFSET 0XFD08151C +#undef DDR_PHY_DX8SL4DXCTL2_OFFSET +#define DDR_PHY_DX8SL4DXCTL2_OFFSET 0XFD08152C +#undef DDR_PHY_DX8SL4IOCR_OFFSET +#define DDR_PHY_DX8SL4IOCR_OFFSET 0XFD081530 +#undef DDR_PHY_DX8SLBDQSCTL_OFFSET +#define DDR_PHY_DX8SLBDQSCTL_OFFSET 0XFD0817DC + +/* +* DDR block level reset inside of the DDR Sub System +*/ +#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL +#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT +#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK +#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 +#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U + +/* +* Indicates the configuration of the device used in the system. - 00 - x4 + * device - 01 - x8 device - 10 - x16 device - 11 - x32 device +*/ +#undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL +#undef DDRC_MSTR_DEVICE_CONFIG_SHIFT +#undef DDRC_MSTR_DEVICE_CONFIG_MASK +#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL 0x03040001 +#define DDRC_MSTR_DEVICE_CONFIG_SHIFT 30 +#define DDRC_MSTR_DEVICE_CONFIG_MASK 0xC0000000U + +/* +* Choose which registers are used. - 0 - Original registers - 1 - Shadow r + * egisters +*/ +#undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL +#undef DDRC_MSTR_FREQUENCY_MODE_SHIFT +#undef DDRC_MSTR_FREQUENCY_MODE_MASK +#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_FREQUENCY_MODE_SHIFT 29 +#define DDRC_MSTR_FREQUENCY_MODE_MASK 0x20000000U + +/* +* Only present for multi-rank configurations. Each bit represents one rank + * . For two-rank configurations, only bits[25:24] are present. - 1 - popul + * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow + * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others - + * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran + * k - 0011 - Two ranks - 1111 - Four ranks +*/ +#undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL +#undef DDRC_MSTR_ACTIVE_RANKS_SHIFT +#undef DDRC_MSTR_ACTIVE_RANKS_MASK +#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL 0x03040001 +#define DDRC_MSTR_ACTIVE_RANKS_SHIFT 24 +#define DDRC_MSTR_ACTIVE_RANKS_MASK 0x03000000U + +/* +* SDRAM burst length used: - 0001 - Burst length of 2 (only supported for + * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur + * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other + * values are reserved. This controls the burst size used to access the SDR + * AM. This must match the burst length mode register setting in the SDRAM. + * (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) + * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH + * is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 +*/ +#undef DDRC_MSTR_BURST_RDWR_DEFVAL +#undef DDRC_MSTR_BURST_RDWR_SHIFT +#undef DDRC_MSTR_BURST_RDWR_MASK +#define DDRC_MSTR_BURST_RDWR_DEFVAL 0x03040001 +#define DDRC_MSTR_BURST_RDWR_SHIFT 16 +#define DDRC_MSTR_BURST_RDWR_MASK 0x000F0000U + +/* +* Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low + * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for + * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC + * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi + * s bit must be set to '0'. +*/ +#undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL +#undef DDRC_MSTR_DLL_OFF_MODE_SHIFT +#undef DDRC_MSTR_DLL_OFF_MODE_MASK +#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_DLL_OFF_MODE_SHIFT 15 +#define DDRC_MSTR_DLL_OFF_MODE_MASK 0x00008000U + +/* +* Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full + * DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter + * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is + * only supported when the SDRAM bus width is a multiple of 16, and quarter + * bus width mode is only supported when the SDRAM bus width is a multiple + * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid + * th refers to DQ bus width (excluding any ECC width). +*/ +#undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL +#undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT +#undef DDRC_MSTR_DATA_BUS_WIDTH_MASK +#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 0x03040001 +#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12 +#define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x00003000U + +/* +* 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D + * RAM in normal mode (1N). This register can be changed, only when the Con + * troller is in self-refresh mode. This signal must be set the same value + * as MR3 bit A3. Note: Geardown mode is not supported if the configuration + * parameter MEMC_CMD_RTN2IDLE is set +*/ +#undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL +#undef DDRC_MSTR_GEARDOWN_MODE_SHIFT +#undef DDRC_MSTR_GEARDOWN_MODE_MASK +#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_GEARDOWN_MODE_SHIFT 11 +#define DDRC_MSTR_GEARDOWN_MODE_MASK 0x00000800U + +/* +* If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin + * g, all command signals (except chip select) are held for 2 clocks on the + * SDRAM bus. Chip select is asserted on the second cycle of the command N + * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti + * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i + * s set Note: 2T timing is not supported in DDR4 geardown mode. +*/ +#undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL +#undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT +#undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK +#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 10 +#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK 0x00000400U + +/* +* When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci + * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full + * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer + * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is + * disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl + * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported + * , and this bit must be set to '0' +*/ +#undef DDRC_MSTR_BURSTCHOP_DEFVAL +#undef DDRC_MSTR_BURSTCHOP_SHIFT +#undef DDRC_MSTR_BURSTCHOP_MASK +#define DDRC_MSTR_BURSTCHOP_DEFVAL 0x03040001 +#define DDRC_MSTR_BURSTCHOP_SHIFT 9 +#define DDRC_MSTR_BURSTCHOP_MASK 0x00000200U + +/* +* Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d + * evice in use Present only in designs configured to support LPDDR4. +*/ +#undef DDRC_MSTR_LPDDR4_DEFVAL +#undef DDRC_MSTR_LPDDR4_SHIFT +#undef DDRC_MSTR_LPDDR4_MASK +#define DDRC_MSTR_LPDDR4_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR4_SHIFT 5 +#define DDRC_MSTR_LPDDR4_MASK 0x00000020U + +/* +* Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device + * in use Present only in designs configured to support DDR4. +*/ +#undef DDRC_MSTR_DDR4_DEFVAL +#undef DDRC_MSTR_DDR4_SHIFT +#undef DDRC_MSTR_DDR4_MASK +#define DDRC_MSTR_DDR4_DEFVAL 0x03040001 +#define DDRC_MSTR_DDR4_SHIFT 4 +#define DDRC_MSTR_DDR4_MASK 0x00000010U + +/* +* Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d + * evice in use Present only in designs configured to support LPDDR3. +*/ +#undef DDRC_MSTR_LPDDR3_DEFVAL +#undef DDRC_MSTR_LPDDR3_SHIFT +#undef DDRC_MSTR_LPDDR3_MASK +#define DDRC_MSTR_LPDDR3_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR3_SHIFT 3 +#define DDRC_MSTR_LPDDR3_MASK 0x00000008U + +/* +* Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d + * evice in use Present only in designs configured to support LPDDR2. +*/ +#undef DDRC_MSTR_LPDDR2_DEFVAL +#undef DDRC_MSTR_LPDDR2_SHIFT +#undef DDRC_MSTR_LPDDR2_MASK +#define DDRC_MSTR_LPDDR2_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR2_SHIFT 2 +#define DDRC_MSTR_LPDDR2_MASK 0x00000004U + +/* +* Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de + * vice in use Only present in designs that support DDR3. +*/ +#undef DDRC_MSTR_DDR3_DEFVAL +#undef DDRC_MSTR_DDR3_SHIFT +#undef DDRC_MSTR_DDR3_MASK +#define DDRC_MSTR_DDR3_DEFVAL 0x03040001 +#define DDRC_MSTR_DDR3_SHIFT 0 +#define DDRC_MSTR_DDR3_MASK 0x00000001U + +/* +* Setting this register bit to 1 triggers a mode register read or write op + * eration. When the MR operation is complete, the uMCTL2 automatically cle + * ars this bit. The other register fields of this register must be written + * in a separate APB transaction, before setting this mr_wr bit. It is rec + * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper + * ating modes. +*/ +#undef DDRC_MRCTRL0_MR_WR_DEFVAL +#undef DDRC_MRCTRL0_MR_WR_SHIFT +#undef DDRC_MRCTRL0_MR_WR_MASK +#define DDRC_MRCTRL0_MR_WR_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_WR_SHIFT 31 +#define DDRC_MRCTRL0_MR_WR_MASK 0x80000000U + +/* +* Address of the mode register that is to be written to. - 0000 - MR0 - 00 + * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR + * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data + * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als + * o used for writing to control words of RDIMMs. In that case, it correspo + * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[ + * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a + * s the bit[2:0] must be set to an appropriate value which is considered b + * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R + * DIMMs. +*/ +#undef DDRC_MRCTRL0_MR_ADDR_DEFVAL +#undef DDRC_MRCTRL0_MR_ADDR_SHIFT +#undef DDRC_MRCTRL0_MR_ADDR_MASK +#define DDRC_MRCTRL0_MR_ADDR_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_ADDR_SHIFT 12 +#define DDRC_MRCTRL0_MR_ADDR_MASK 0x0000F000U + +/* +* Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire + * d to access all ranks, so all bits should be set to 1. However, for mult + * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess + * ary to access ranks individually. Examples (assume uMCTL2 is configured + * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x + * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran + * ks 0, 1, 2 and 3 +*/ +#undef DDRC_MRCTRL0_MR_RANK_DEFVAL +#undef DDRC_MRCTRL0_MR_RANK_SHIFT +#undef DDRC_MRCTRL0_MR_RANK_MASK +#define DDRC_MRCTRL0_MR_RANK_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_RANK_SHIFT 4 +#define DDRC_MRCTRL0_MR_RANK_MASK 0x00000030U + +/* +* Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b + * efore automatic SDRAM initialization routine or not. For DDR4, this bit + * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init + * ialization. For LPDDR4, this bit can be used to program additional mode + * registers before automatic SDRAM initialization if necessary. Note: This + * must be cleared to 0 after completing Software operation. Otherwise, SD + * RAM initialization routine will not re-start. - 0 - Software interventio + * n is not allowed - 1 - Software intervention is allowed +*/ +#undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL +#undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT +#undef DDRC_MRCTRL0_SW_INIT_INT_MASK +#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT 3 +#define DDRC_MRCTRL0_SW_INIT_INT_MASK 0x00000008U + +/* +* Indicates whether the mode register operation is MRS in PDA mode or not + * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode +*/ +#undef DDRC_MRCTRL0_PDA_EN_DEFVAL +#undef DDRC_MRCTRL0_PDA_EN_SHIFT +#undef DDRC_MRCTRL0_PDA_EN_MASK +#define DDRC_MRCTRL0_PDA_EN_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_PDA_EN_SHIFT 2 +#define DDRC_MRCTRL0_PDA_EN_MASK 0x00000004U + +/* +* Indicates whether the mode register operation is MRS or WR/RD for MPR (o + * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR +*/ +#undef DDRC_MRCTRL0_MPR_EN_DEFVAL +#undef DDRC_MRCTRL0_MPR_EN_SHIFT +#undef DDRC_MRCTRL0_MPR_EN_MASK +#define DDRC_MRCTRL0_MPR_EN_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MPR_EN_SHIFT 1 +#define DDRC_MRCTRL0_MPR_EN_MASK 0x00000002U + +/* +* Indicates whether the mode register operation is read or write. Only use + * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read +*/ +#undef DDRC_MRCTRL0_MR_TYPE_DEFVAL +#undef DDRC_MRCTRL0_MR_TYPE_SHIFT +#undef DDRC_MRCTRL0_MR_TYPE_MASK +#define DDRC_MRCTRL0_MR_TYPE_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_TYPE_SHIFT 0 +#define DDRC_MRCTRL0_MR_TYPE_MASK 0x00000001U + +/* +* Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us + * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d + * esigns configured to support LPDDR4. The required number of cycles for d + * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p + * eriod, and rounding up the next integer. +*/ +#undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL +#undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT +#undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK +#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 8 +#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK 0x00000300U + +/* +* Derate byte Present only in designs configured to support LPDDR2/LPDDR3/ + * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma + * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. +*/ +#undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL +#undef DDRC_DERATEEN_DERATE_BYTE_SHIFT +#undef DDRC_DERATEEN_DERATE_BYTE_MASK +#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_BYTE_SHIFT 4 +#define DDRC_DERATEEN_DERATE_BYTE_MASK 0x000000F0U + +/* +* Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl + * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all + * LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ + * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8 + * 75 ns is less than a core_ddrc_core_clk period or not. +*/ +#undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL +#undef DDRC_DERATEEN_DERATE_VALUE_SHIFT +#undef DDRC_DERATEEN_DERATE_VALUE_MASK +#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1 +#define DDRC_DERATEEN_DERATE_VALUE_MASK 0x00000002U + +/* +* Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin + * g parameter derating is enabled using MR4 read value. Present only in de + * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set + * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. +*/ +#undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL +#undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT +#undef DDRC_DERATEEN_DERATE_ENABLE_MASK +#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0 +#define DDRC_DERATEEN_DERATE_ENABLE_MASK 0x00000001U + +/* +* Interval between two MR4 reads, used to derate the timing parameters. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r + * egister must not be set to zero +*/ +#undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL +#undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT +#undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK +#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL +#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0 +#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFU + +/* +* Self refresh state is an intermediate state to enter to Self refresh pow + * er down state or exit Self refresh power down state for LPDDR4. This reg + * ister controls transition from the Self refresh state. - 1 - Prohibit tr + * ansition from Self refresh state - 0 - Allow transition from Self refres + * h state +*/ +#undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL +#undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT +#undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK +#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 0x00000000 +#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 6 +#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK 0x00000040U + +/* +* A value of 1 to this register causes system to move to Self Refresh stat + * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa + * re Entry to Self Refresh - 0 - Software Exit from Self Refresh +*/ +#undef DDRC_PWRCTL_SELFREF_SW_DEFVAL +#undef DDRC_PWRCTL_SELFREF_SW_SHIFT +#undef DDRC_PWRCTL_SELFREF_SW_MASK +#define DDRC_PWRCTL_SELFREF_SW_DEFVAL 0x00000000 +#define DDRC_PWRCTL_SELFREF_SW_SHIFT 5 +#define DDRC_PWRCTL_SELFREF_SW_MASK 0x00000020U + +/* +* When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode + * when the transaction store is empty. This register must be reset to '0' + * to bring uMCTL2 out of maximum power saving mode. Present only in desig + * ns configured to support DDR4. For non-DDR4, this register should not be + * set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if + * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r + * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PWRCTL_MPSM_EN_DEFVAL +#undef DDRC_PWRCTL_MPSM_EN_SHIFT +#undef DDRC_PWRCTL_MPSM_EN_MASK +#define DDRC_PWRCTL_MPSM_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_MPSM_EN_SHIFT 4 +#define DDRC_PWRCTL_MPSM_EN_MASK 0x00000010U + +/* +* Enable the assertion of dfi_dram_clk_disable whenever a clock is not req + * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. + * Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only + * be asserted in Self Refresh. In DDR4, can be asserted in following: - i + * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca + * n be asserted in following: - in Self Refresh - in Power Down - in Deep + * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse + * rted in following: - in Self Refresh Power Down - in Power Down - during + * Normal operation (Clock Stop) +*/ +#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL +#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT +#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 0x00000000 +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3 +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x00000008U + +/* +* When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the + * transaction store is empty. This register must be reset to '0' to bring + * uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM + * initialization on deep power-down exit. Present only in designs configu + * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD + * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL +#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT +#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 2 +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 0x00000004U + +/* +* If true then the uMCTL2 goes into power-down after a programmable number + * of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_ + * x32). This register bit may be re-programmed during the course of normal + * operation. +*/ +#undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL +#undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT +#undef DDRC_PWRCTL_POWERDOWN_EN_MASK +#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT 1 +#define DDRC_PWRCTL_POWERDOWN_EN_MASK 0x00000002U + +/* +* If true then the uMCTL2 puts the SDRAM into Self Refresh after a program + * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG. + * selfref_to_x32)'. This register bit may be re-programmed during the cour + * se of normal operation. +*/ +#undef DDRC_PWRCTL_SELFREF_EN_DEFVAL +#undef DDRC_PWRCTL_SELFREF_EN_SHIFT +#undef DDRC_PWRCTL_SELFREF_EN_MASK +#define DDRC_PWRCTL_SELFREF_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_SELFREF_EN_SHIFT 0 +#define DDRC_PWRCTL_SELFREF_EN_MASK 0x00000001U + +/* +* After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_ + * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL +#undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT +#undef DDRC_PWRTMG_SELFREF_TO_X32_MASK +#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 0x00402010 +#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 16 +#define DDRC_PWRTMG_SELFREF_TO_X32_MASK 0x00FF0000U + +/* +* Minimum deep power-down time. For mDDR, value from the JEDEC specificati + * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL + * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE + * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i + * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + * ONLY. +*/ +#undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL +#undef DDRC_PWRTMG_T_DPD_X4096_SHIFT +#undef DDRC_PWRTMG_T_DPD_X4096_MASK +#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL 0x00402010 +#define DDRC_PWRTMG_T_DPD_X4096_SHIFT 8 +#define DDRC_PWRTMG_T_DPD_X4096_MASK 0x0000FF00U + +/* +* After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_ + * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL +#undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT +#undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK +#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 0x00402010 +#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 0 +#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 0x0000001FU + +/* +* Threshold value in number of clock cycles before the critical refresh or + * page timer expires. A critical refresh is to be issued before this thre + * shold is reached. It is recommended that this not be changed from the de + * fault value, currently shown as 0x2. It must always be less than interna + * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u + * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i + * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n + * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo + * cks. +*/ +#undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL +#undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT +#undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK +#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 20 +#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 0x00F00000U + +/* +* If the refresh timer (tRFCnom, also known as tREFI) has expired at least + * once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then + * a speculative refresh may be performed. A speculative refresh is a refr + * esh performed at a time when refresh would be useful, but before it is a + * bsolutely required. When the SDRAM bus is idle for a period of time dete + * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired + * at least once since the last refresh, then a speculative refresh is per + * formed. Speculative refreshes continues successively until there are no + * refreshes pending or until new reads or writes are issued to the uMCTL2. + * FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL +#undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT +#undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK +#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 12 +#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 0x0001F000U + +/* +* The programmed value + 1 is the number of refresh timeouts that is allow + * ed to accumulate before traffic is blocked and the refreshes are forced + * to execute. Closing pages to perform a refresh is a one-time penalty tha + * t must be paid for each group of refreshes. Therefore, performing refres + * hes in a burst reduces the per-refresh penalty of these page closings. H + * igher numbers for RFSHCTL.refresh_burst slightly increases utilization; + * lower numbers decreases the worst-case latency associated with refreshes + * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh + * For information on burst refresh feature refer to section 3.9 of DDR2 J + * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe + * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF + * I cycles using the burst refresh feature. In DDR4 mode, according to Fin + * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre + * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda + * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens + * ure that tRFCmax is not violated due to a PHY-initiated update occurring + * shortly before a refresh burst was due. In this situation, the refresh + * burst will be delayed until the PHY-initiated update is complete. +*/ +#undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL +#undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT +#undef DDRC_RFSHCTL0_REFRESH_BURST_MASK +#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 4 +#define DDRC_RFSHCTL0_REFRESH_BURST_MASK 0x000001F0U + +/* +* - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + * traffic to flow to other banks. Per bank refresh is not supported by all + * LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4 +*/ +#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL +#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT +#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 2 +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 0x00000004U + +/* +* Refresh timer start for rank 1 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL 0x00000000 +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT 16 +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK 0x0FFF0000U + +/* +* Refresh timer start for rank 0 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL 0x00000000 +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT 0 +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK 0x00000FFFU + +/* +* Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix + * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11 + * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No + * te: The on-the-fly modes is not supported in this version of the uMCTL2. + * Note: This must be set up while the Controller is in reset or while the + * Controller is in self-refresh mode. Changing this during normal operati + * on is not allowed. Making this a dynamic register will be supported in f + * uture version of the uMCTL2. +*/ +#undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL +#undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT +#undef DDRC_RFSHCTL3_REFRESH_MODE_MASK +#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 4 +#define DDRC_RFSHCTL3_REFRESH_MODE_MASK 0x00000070U + +/* +* Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + * the refresh register(s) have been updated. The value is automatically up + * dated when exiting reset, so it does not need to be toggled initially. +*/ +#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL +#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT +#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1 +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 0x00000002U + +/* +* When '1', disable auto-refresh generated by the uMCTL2. When auto-refres + * h is disabled, the SoC core must generate refreshes using the registers + * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a + * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1 + * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 + * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d + * isable auto-refresh is not supported, and this bit must be set to '0'. T + * his register field is changeable on the fly. +*/ +#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL +#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT +#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 0 +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 0x00000001U + +/* +* tREFI: Average time interval between refreshes per rank (Specification: + * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, + * LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre + * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE + * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + * register should be set to tREFIpb For configurations with MEMC_FREQ_RAT + * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val + * ue is different depending on the refresh mode. The user should program t + * he appropriate value from the spec based on the value programmed in the + * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea + * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th + * an 0x1. Unit: Multiples of 32 clocks. +*/ +#undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL +#undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT +#undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK +#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16 +#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 0x0FFF0000U + +/* +* Used only when LPDDR3 memory type is connected. Should only be changed w + * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r + * equired by some LPDDR3 devices which comply with earlier versions of the + * LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 + * - tREFBW parameter used +*/ +#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL +#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT +#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 15 +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 0x00008000U + +/* +* tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F + * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t + * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro + * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using + * all-bank refreshes, the tRFCmin value in the above equations is equal to + * tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq + * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above + * equations is different depending on the refresh mode (fixed 1X,2X,4X) an + * d the device density. The user should program the appropriate value from + * the spec based on the 'refresh_mode' and the device density that is use + * d. Unit: Clocks. +*/ +#undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL +#undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT +#undef DDRC_RFSHTMG_T_RFC_MIN_MASK +#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT 0 +#define DDRC_RFSHTMG_T_RFC_MIN_MASK 0x000003FFU + +/* +* Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U + * SE_RMW is defined +*/ +#undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL +#undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT +#undef DDRC_ECCCFG0_DIS_SCRUB_MASK +#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 0x00000000 +#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT 4 +#define DDRC_ECCCFG0_DIS_SCRUB_MASK 0x00000010U + +/* +* ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov + * er 1 beat - all other settings are reserved for future use +*/ +#undef DDRC_ECCCFG0_ECC_MODE_DEFVAL +#undef DDRC_ECCCFG0_ECC_MODE_SHIFT +#undef DDRC_ECCCFG0_ECC_MODE_MASK +#define DDRC_ECCCFG0_ECC_MODE_DEFVAL 0x00000000 +#define DDRC_ECCCFG0_ECC_MODE_SHIFT 0 +#define DDRC_ECCCFG0_ECC_MODE_MASK 0x00000007U + +/* +* Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da + * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat + * a_poison_en=1 +*/ +#undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL +#undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT +#undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK +#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 0x00000000 +#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 1 +#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK 0x00000002U + +/* +* Enable ECC data poisoning - introduces ECC errors on writes to address s + * pecified by the ECCPOISONADDR0/1 registers +*/ +#undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL +#undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT +#undef DDRC_ECCCFG1_DATA_POISON_EN_MASK +#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 0x00000000 +#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 0 +#define DDRC_ECCCFG1_DATA_POISON_EN_MASK 0x00000001U + +/* +* The maximum number of DFI PHY clock cycles allowed from the assertion of + * the dfi_rddata_en signal to the assertion of each of the corresponding + * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing + * parameter tphy_rdlat. Refer to PHY specification for correct value. This + * value it only used for detecting read data timeout when DDR4 retry is e + * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: + * - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r + * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 + * : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d + * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ + * rdlat < 'd114 Unit: DFI Clocks +*/ +#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL +#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT +#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 24 +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 0x3F000000U + +/* +* After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa + * re has an option to read the mode registers in the DRAM before the hardw + * are begins the retry process - 1: Wait for software to read/write the mo + * de registers before hardware begins the retry. After software is done wi + * th its operations, it will clear the alert interrupt register bit - 0: H + * ardware can begin the retry right away after the dfi_alert_n pulse goes + * away. The value on this register is valid only when retry is enabled (PA + * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t + * he software doesn't clear the interrupt register after handling the pari + * ty/CRC error, then the hardware will not begin the retry process and the + * system will hang. In the case of Parity/CRC error, there are two possib + * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten + * t parity' mode register bit is NOT set: the commands sent during retry a + * nd normal operation are executed without parity checking. The value in t + * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent + * parity' mode register bit is SET: Parity checking is done for commands s + * ent during retry and normal operation. If multiple errors occur before M + * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don' + * t care'. +*/ +#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL +#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT +#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 9 +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 0x00000200U + +/* +* - 1: Enable command retry mechanism in case of C/A Parity or CRC error - + * 0: Disable command retry mechanism when C/A Parity or CRC features are + * enabled. Note that retry functionality is not supported if burst chop is + * enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF + * SHCTL3.dis_auto_refresh = 1) +*/ +#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL +#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT +#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 8 +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 0x00000100U + +/* +* CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no + * t includes DM signal Present only in designs configured to support DDR4. +*/ +#undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL +#undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT +#undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK +#define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 7 +#define DDRC_CRCPARCTL1_CRC_INC_DM_MASK 0x00000080U + +/* +* CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio + * n of CRC The setting of this register should match the CRC mode register + * setting in the DRAM. +*/ +#undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL +#undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT +#undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK +#define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 4 +#define DDRC_CRCPARCTL1_CRC_ENABLE_MASK 0x00000010U + +/* +* C/A Parity enable register - 1: Enable generation of C/A parity and dete + * ction of C/A parity error - 0: Disable generation of C/A parity and disa + * ble detection of C/A parity error If RCD's parity error detection or SDR + * AM's parity detection is enabled, this register should be 1. +*/ +#undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL +#undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT +#undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK +#define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 0 +#define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 0x00000001U + +/* +* Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M + * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT + * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i + * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. +*/ +#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL +#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT +#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 16 +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 0x01FF0000U + +/* +* Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX + * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW + * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille + * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. +*/ +#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL +#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT +#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 8 +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 0x00001F00U + +/* +* Indicates the maximum duration in number of DRAM clock cycles for which + * a command should be held in the Command Retry FIFO before it is popped o + * ut. Every location in the Command Retry FIFO has an associated down coun + * ting timer that will use this register as the start value. The down coun + * ting starts when a command is loaded into the FIFO. The timer counts dow + * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe + * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err + * or occurs before the counter reaches zero. The counter is reset to 0, af + * ter all the commands in the FIFO are retried. Recommended(minimum) value + * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten + * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable + * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R + * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be + * in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n + * ) should be considered. Note 3: Use the worst case(longer) value for PHY + * Latencies/Board delay Note 4: The Recommended values are minimum value + * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max + * value can be set to this register is defined below: - MEMC_BURST_LENGTH + * == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 + * Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b + * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod + * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C + * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC= + * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 + * Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full + * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod + * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC + * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF + * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma + * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal + * . +*/ +#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL +#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT +#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 0 +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 0x0000003FU + +/* +* If lower bit is enabled the SDRAM initialization routine is skipped. The + * upper bit decides what state the controller starts up in when reset is + * removed - 00 - SDRAM Intialization routine is run after power-up - 01 - + * SDRAM Intialization routine is skipped after power-up. Controller starts + * up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p + * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ + * ation routine is run after power-up. Note: The only 2'b00 is supported f + * or LPDDR4 in this version of the uMCTL2. +*/ +#undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL +#undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT +#undef DDRC_INIT0_SKIP_DRAM_INIT_MASK +#define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 0x0002004E +#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 30 +#define DDRC_INIT0_SKIP_DRAM_INIT_MASK 0xC0000000U + +/* +* Cycles to wait after driving CKE high to start the SDRAM initialization + * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req + * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD + * R3 typically requires this to be programmed for a delay of 200 us. LPDDR + * 4 typically requires this to be programmed for a delay of 2 us. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi + * ded by 2, and round it up to next integer value. +*/ +#undef DDRC_INIT0_POST_CKE_X1024_DEFVAL +#undef DDRC_INIT0_POST_CKE_X1024_SHIFT +#undef DDRC_INIT0_POST_CKE_X1024_MASK +#define DDRC_INIT0_POST_CKE_X1024_DEFVAL 0x0002004E +#define DDRC_INIT0_POST_CKE_X1024_SHIFT 16 +#define DDRC_INIT0_POST_CKE_X1024_MASK 0x03FF0000U + +/* +* Cycles to wait after reset before driving CKE high to start the SDRAM in + * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi + * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD + * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati + * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by + * 2, and round it up to next integer value. +*/ +#undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL +#undef DDRC_INIT0_PRE_CKE_X1024_SHIFT +#undef DDRC_INIT0_PRE_CKE_X1024_MASK +#define DDRC_INIT0_PRE_CKE_X1024_DEFVAL 0x0002004E +#define DDRC_INIT0_PRE_CKE_X1024_SHIFT 0 +#define DDRC_INIT0_PRE_CKE_X1024_MASK 0x00000FFFU + +/* +* Number of cycles to assert SDRAM reset signal during init sequence. This + * is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo + * r use with a DDR PHY, this should be set to a minimum of 1 +*/ +#undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL +#undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT +#undef DDRC_INIT1_DRAM_RSTN_X1024_MASK +#define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 0x00000000 +#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 16 +#define DDRC_INIT1_DRAM_RSTN_X1024_MASK 0x01FF0000U + +/* +* Cycles to wait after completing the SDRAM initialization sequence before + * starting the dynamic scheduler. Unit: Counts of a global timer that pul + * ses every 32 clock cycles. There is no known specific requirement for th + * is; it may be set to zero. +*/ +#undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL +#undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT +#undef DDRC_INIT1_FINAL_WAIT_X32_MASK +#define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 0x00000000 +#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT 8 +#define DDRC_INIT1_FINAL_WAIT_X32_MASK 0x00007F00U + +/* +* Wait period before driving the OCD complete command to SDRAM. Unit: Coun + * ts of a global timer that pulses every 32 clock cycles. There is no know + * n specific requirement for this; it may be set to zero. +*/ +#undef DDRC_INIT1_PRE_OCD_X32_DEFVAL +#undef DDRC_INIT1_PRE_OCD_X32_SHIFT +#undef DDRC_INIT1_PRE_OCD_X32_MASK +#define DDRC_INIT1_PRE_OCD_X32_DEFVAL 0x00000000 +#define DDRC_INIT1_PRE_OCD_X32_SHIFT 0 +#define DDRC_INIT1_PRE_OCD_X32_MASK 0x0000000FU + +/* +* Idle time after the reset command, tINIT4. Present only in designs confi + * gured to support LPDDR2. Unit: 32 clock cycles. +*/ +#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL +#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT +#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 0x00000D05 +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 8 +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 0x0000FF00U + +/* +* Time to wait after the first CKE high, tINIT2. Present only in designs c + * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t + * ypically requires 5 x tCK delay. +*/ +#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL +#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT +#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 0x00000D05 +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 0 +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 0x0000000FU + +/* +* DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he + * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value + * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP + * DDR3/LPDDR4 - Value to write to MR1 register +*/ +#undef DDRC_INIT3_MR_DEFVAL +#undef DDRC_INIT3_MR_SHIFT +#undef DDRC_INIT3_MR_MASK +#define DDRC_INIT3_MR_DEFVAL 0x00000510 +#define DDRC_INIT3_MR_SHIFT 16 +#define DDRC_INIT3_MR_MASK 0xFFFF0000U + +/* +* DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti + * ng in this register is ignored. The uMCTL2 sets those bits appropriately + * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu + * ation mode training is enabled, this bit is set appropriately by the uMC + * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/ + * LPDDR3/LPDDR4 - Value to write to MR2 register +*/ +#undef DDRC_INIT3_EMR_DEFVAL +#undef DDRC_INIT3_EMR_SHIFT +#undef DDRC_INIT3_EMR_MASK +#define DDRC_INIT3_EMR_DEFVAL 0x00000510 +#define DDRC_INIT3_EMR_SHIFT 0 +#define DDRC_INIT3_EMR_MASK 0x0000FFFFU + +/* +* DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 + * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus + * ed +*/ +#undef DDRC_INIT4_EMR2_DEFVAL +#undef DDRC_INIT4_EMR2_SHIFT +#undef DDRC_INIT4_EMR2_MASK +#define DDRC_INIT4_EMR2_DEFVAL 0x00000000 +#define DDRC_INIT4_EMR2_SHIFT 16 +#define DDRC_INIT4_EMR2_MASK 0xFFFF0000U + +/* +* DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 + * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis + * ter +*/ +#undef DDRC_INIT4_EMR3_DEFVAL +#undef DDRC_INIT4_EMR3_SHIFT +#undef DDRC_INIT4_EMR3_MASK +#define DDRC_INIT4_EMR3_DEFVAL 0x00000000 +#define DDRC_INIT4_EMR3_SHIFT 0 +#define DDRC_INIT4_EMR3_MASK 0x0000FFFFU + +/* +* ZQ initial calibration, tZQINIT. Present only in designs configured to s + * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica + * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir + * es 1 us. +*/ +#undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL +#undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT +#undef DDRC_INIT5_DEV_ZQINIT_X32_MASK +#define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 0x00100004 +#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 16 +#define DDRC_INIT5_DEV_ZQINIT_X32_MASK 0x00FF0000U + +/* +* Maximum duration of the auto initialization, tINIT5. Present only in des + * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir + * es 10 us. +*/ +#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL +#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT +#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 0x00100004 +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 0 +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 0x000003FFU + +/* +* DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs + * only. +*/ +#undef DDRC_INIT6_MR4_DEFVAL +#undef DDRC_INIT6_MR4_SHIFT +#undef DDRC_INIT6_MR4_MASK +#define DDRC_INIT6_MR4_DEFVAL 0x00000000 +#define DDRC_INIT6_MR4_SHIFT 16 +#define DDRC_INIT6_MR4_MASK 0xFFFF0000U + +/* +* DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs + * only. +*/ +#undef DDRC_INIT6_MR5_DEFVAL +#undef DDRC_INIT6_MR5_SHIFT +#undef DDRC_INIT6_MR5_MASK +#define DDRC_INIT6_MR5_DEFVAL 0x00000000 +#define DDRC_INIT6_MR5_SHIFT 0 +#define DDRC_INIT6_MR5_MASK 0x0000FFFFU + +/* +* DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs + * only. +*/ +#undef DDRC_INIT7_MR6_DEFVAL +#undef DDRC_INIT7_MR6_SHIFT +#undef DDRC_INIT7_MR6_MASK +#define DDRC_INIT7_MR6_DEFVAL +#define DDRC_INIT7_MR6_SHIFT 16 +#define DDRC_INIT7_MR6_MASK 0xFFFF0000U + +/* +* Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r + * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp + * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. +*/ +#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL +#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT +#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 5 +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 0x00000020U + +/* +* Enable for BG1 bit of MRS command. BG1 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have BG1 are attached and + * both the CA parity and the Output Inversion are enabled, this must be s + * et to 0, so that the calculation of CA parity will not include BG1 bit. + * Note: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. If address mirroring is enab + * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En + * abled - 0 - Disabled +*/ +#undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL +#undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT +#undef DDRC_DIMMCTL_MRS_BG1_EN_MASK +#define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 4 +#define DDRC_DIMMCTL_MRS_BG1_EN_MASK 0x00000010U + +/* +* Enable for A17 bit of MRS command. A17 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have A17 are attached and + * the Output Inversion are enabled, this must be set to 0, so that the ca + * lculation of CA parity will not include A17 bit. Note: This has no effec + * t on the address of any other memory accesses, or of software-driven mod + * e register accesses. - 1 - Enabled - 0 - Disabled +*/ +#undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL +#undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT +#undef DDRC_DIMMCTL_MRS_A17_EN_MASK +#define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT 3 +#define DDRC_DIMMCTL_MRS_A17_EN_MASK 0x00000008U + +/* +* Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM + * M implements the Output Inversion feature by default, which means that t + * he following address, bank address and bank group bits of B-side DRAMs a + * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en + * sures that, for mode register accesses generated by the uMCTL2 during th + * e automatic initialization routine and enabling of a particular DDR4 fea + * ture, separate A-side and B-side mode register accesses are generated. F + * or B-side mode register accesses, these bits are inverted within the uMC + * TL2 to compensate for this RDIMM inversion. Note: This has no effect on + * the address of any other memory accesses, or of software-driven mode reg + * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - + * Do not implement output inversion for B-side DRAMs. +*/ +#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL +#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT +#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 2 +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 0x00000004U + +/* +* Address Mirroring Enable (for multi-rank UDIMM implementations and multi + * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement + * address mirroring for odd ranks, which means that the following address + * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, + * A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t + * his bit ensures that, for mode register accesses during the automatic in + * itialization routine, these bits are swapped within the uMCTL2 to compen + * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial + * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th + * e automatic MRS access to enable/disable of a particular DDR4 feature. N + * ote: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. This is not supported for mDD + * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 + * output of MRS for the odd ranks is same as BG0 because BG1 is invalid, + * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran + * ks, implement address mirroring for MRS commands to during initializatio + * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp + * lements address mirroring) - 0 - Do not implement address mirroring +*/ +#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL +#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT +#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 1 +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 0x00000002U + +/* +* Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM + * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 + * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of + * software driven MR commands (via MRCTRL0/MRCTRL1), where software is re + * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se + * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma + * nds to even and odd ranks seperately - 0 - Do not stagger accesses +*/ +#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL +#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT +#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 0 +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 0x00000001U + +/* +* Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive writes to differ + * ent ranks. This is used to switch the delays in the PHY to match the ran + * k requirements. This value should consider both PHY requirement and ODT + * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v + * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by + * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas + * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc + * reased by 1. - ODT requirement: The value programmed in this register ta + * kes care of the ODT switch off timing requirement when switching ranks d + * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 + * For configurations with MEMC_FREQ_RATIO=1, program this to the larger o + * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_ + * RATIO=2, program this to the larger value divided by two and round it up + * to the next integer. +*/ +#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL +#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT +#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 0x0000066F +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 8 +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 0x00000F00U + +/* +* Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive reads to differe + * nt ranks. This is used to switch the delays in the PHY to match the rank + * requirements. This value should consider both PHY requirement and ODT r + * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va + * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), + * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only + * ), should be increased by 1. - ODT requirement: The value programmed in + * this register takes care of the ODT switch off timing requirement when s + * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, + * program this to the larger of PHY requirement or ODT requirement. For co + * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di + * vided by two and round it up to the next integer. +*/ +#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL +#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT +#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 0x0000066F +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 4 +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 0x000000F0U + +/* +* Only present for multi-rank configurations. Background: Reads to the sam + * e rank can be performed back-to-back. Reads to different ranks require a + * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is + * to avoid possible data bus contention as well as to give PHY enough tim + * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus + * access on a cycle-by-cycle basis; therefore after a read is scheduled, + * there are few clock cycles (determined by the value on RANKCTL.diff_rank + * _rd_gap register) in which only reads from the same rank are eligible to + * be scheduled. This prevents reads from other ranks from having fair acc + * ess to the data bus. This parameter represents the maximum number of rea + * ds that can be scheduled consecutively to the same rank. After this numb + * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by + * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig + * her numbers increase bandwidth utilization, lower numbers increase fairn + * ess. This feature can be DISABLED by setting this register to 0. When se + * t to 0, the Controller will stay on the same rank as long as commands ar + * e available for it. Minimum programmable value is 0 (feature disabled) a + * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL +#undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT +#undef DDRC_RANKCTL_MAX_RANK_RD_MASK +#define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 0x0000066F +#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT 0 +#define DDRC_RANKCTL_MAX_RANK_RD_MASK 0x0000000FU + +/* +* Minimum time between write and precharge to same bank. Unit: Clocks Spec + * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks + * @400MHz and less for lower frequencies where: - WL = write latency - BL + * = burst length. This must match the value programmed in the BL bit of t + * he mode register to the SDRAM. BST (burst terminate) is not supported at + * present. - tWR = Write recovery time. This comes directly from the SDRA + * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p + * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the + * above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT + * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u + * p to the next integer value. +*/ +#undef DDRC_DRAMTMG0_WR2PRE_DEFVAL +#undef DDRC_DRAMTMG0_WR2PRE_SHIFT +#undef DDRC_DRAMTMG0_WR2PRE_MASK +#define DDRC_DRAMTMG0_WR2PRE_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_WR2PRE_SHIFT 24 +#define DDRC_DRAMTMG0_WR2PRE_MASK 0x7F000000U + +/* +* tFAW Valid only when 8 or more banks(or banks x bank groups) are present + * . In 8-bank design, at most 4 banks must be activated in a rolling windo + * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se + * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + * Unit: Clocks +*/ +#undef DDRC_DRAMTMG0_T_FAW_DEFVAL +#undef DDRC_DRAMTMG0_T_FAW_SHIFT +#undef DDRC_DRAMTMG0_T_FAW_MASK +#define DDRC_DRAMTMG0_T_FAW_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_FAW_SHIFT 16 +#define DDRC_DRAMTMG0_T_FAW_MASK 0x003F0000U + +/* +* tRAS(max): Maximum time between activate and precharge to same bank. Thi + * s is the maximum time that a page can be kept open Minimum value of this + * register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO + * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of + * 1024 clocks. +*/ +#undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL +#undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT +#undef DDRC_DRAMTMG0_T_RAS_MAX_MASK +#define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 8 +#define DDRC_DRAMTMG0_T_RAS_MAX_MASK 0x00007F00U + +/* +* tRAS(min): Minimum time between activate and precharge to the same bank. + * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA + * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T + * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th + * e next integer value. Unit: Clocks +*/ +#undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL +#undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT +#undef DDRC_DRAMTMG0_T_RAS_MIN_MASK +#define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 0 +#define DDRC_DRAMTMG0_T_RAS_MIN_MASK 0x0000003FU + +/* +* tXP: Minimum time after power-down exit to any operation. For DDR3, this + * should be programmed to tXPDLL if slow powerdown exit is selected in MR + * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it + * up to the next integer value. Units: Clocks +*/ +#undef DDRC_DRAMTMG1_T_XP_DEFVAL +#undef DDRC_DRAMTMG1_T_XP_SHIFT +#undef DDRC_DRAMTMG1_T_XP_MASK +#define DDRC_DRAMTMG1_T_XP_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_T_XP_SHIFT 16 +#define DDRC_DRAMTMG1_T_XP_MASK 0x001F0000U + +/* +* tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL + * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi + * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 + * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t + * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) + * - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_ + * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi + * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo + * ve value by 2 and round it up to the next integer value. Unit: Clocks. +*/ +#undef DDRC_DRAMTMG1_RD2PRE_DEFVAL +#undef DDRC_DRAMTMG1_RD2PRE_SHIFT +#undef DDRC_DRAMTMG1_RD2PRE_MASK +#define DDRC_DRAMTMG1_RD2PRE_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_RD2PRE_SHIFT 8 +#define DDRC_DRAMTMG1_RD2PRE_MASK 0x00001F00U + +/* +* tRC: Minimum time between activates to same bank. For configurations wit + * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege + * r value. Unit: Clocks. +*/ +#undef DDRC_DRAMTMG1_T_RC_DEFVAL +#undef DDRC_DRAMTMG1_T_RC_SHIFT +#undef DDRC_DRAMTMG1_T_RC_MASK +#define DDRC_DRAMTMG1_T_RC_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_T_RC_SHIFT 0 +#define DDRC_DRAMTMG1_T_RC_MASK 0x0000007FU + +/* +* Set to WL Time from write command to write data on SDRAM interface. This + * must be set to WL. For mDDR, it should normally be set to 1. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use a valu + * e of WL + 1 to compensate for the extra cycle of latency through the RDI + * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate + * d using the above equation by 2, and round it up to next integer. This r + * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING + * is set), as the DFI read and write latencies defined in DFITMG0 and DFI + * TMG1 are sufficient for those protocols Unit: clocks +*/ +#undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL +#undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT +#undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK +#define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 24 +#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK 0x3F000000U + +/* +* Set to RL Time from read command to read data on SDRAM interface. This m + * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma + * t be necessary to use a value of RL + 1 to compensate for the extra cycl + * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2 + * , divide the value calculated using the above equation by 2, and round i + * t up to next integer. This register field is not required for DDR2 and D + * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie + * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit + * : clocks +*/ +#undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL +#undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT +#undef DDRC_DRAMTMG2_READ_LATENCY_MASK +#define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT 16 +#define DDRC_DRAMTMG2_READ_LATENCY_MASK 0x003F0000U + +/* +* DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L + * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di + * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL + * LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL + * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write + * command. Include time for bus turnaround and all per-bank, per-rank, an + * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b + * urst length. This must match the value programmed in the BL bit of the m + * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL + * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = + * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d + * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should + * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal + * culated using the above equation by 2, and round it up to next integer. +*/ +#undef DDRC_DRAMTMG2_RD2WR_DEFVAL +#undef DDRC_DRAMTMG2_RD2WR_SHIFT +#undef DDRC_DRAMTMG2_RD2WR_MASK +#define DDRC_DRAMTMG2_RD2WR_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_RD2WR_SHIFT 8 +#define DDRC_DRAMTMG2_RD2WR_MASK 0x00003F00U + +/* +* DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu + * m time from write command to read command for same bank group. In others + * , minimum time from write command to read command. Includes time for bus + * turnaround, recovery times, and all per-bank, per-rank, and global cons + * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la + * tency - BL = burst length. This must match the value programmed in the B + * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea + * d command delay for same bank group. This comes directly from the SDRAM + * specification. - tWTR = internal write to read command delay. This comes + * directly from the SDRAM specification. Add one extra cycle for LPDDR2/L + * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid + * e the value calculated using the above equation by 2, and round it up to + * next integer. +*/ +#undef DDRC_DRAMTMG2_WR2RD_DEFVAL +#undef DDRC_DRAMTMG2_WR2RD_SHIFT +#undef DDRC_DRAMTMG2_WR2RD_MASK +#define DDRC_DRAMTMG2_WR2RD_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_WR2RD_SHIFT 0 +#define DDRC_DRAMTMG2_WR2RD_MASK 0x0000003FU + +/* +* Time to wait after a mode register write or read (MRW or MRR). Present o + * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty + * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD + * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist + * er is used for the time from a MRW/MRR to all other commands. For LDPDR3 + * , this register is used for the time from a MRW/MRR to a MRW/MRR. +*/ +#undef DDRC_DRAMTMG3_T_MRW_DEFVAL +#undef DDRC_DRAMTMG3_T_MRW_SHIFT +#undef DDRC_DRAMTMG3_T_MRW_MASK +#define DDRC_DRAMTMG3_T_MRW_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MRW_SHIFT 20 +#define DDRC_DRAMTMG3_T_MRW_MASK 0x3FF00000U + +/* +* tMRD: Cycles to wait after a mode register write or read. Depending on t + * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com + * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim + * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2, + * program this to (tMRD/2) and round it up to the next integer value. If + * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. +*/ +#undef DDRC_DRAMTMG3_T_MRD_DEFVAL +#undef DDRC_DRAMTMG3_T_MRD_SHIFT +#undef DDRC_DRAMTMG3_T_MRD_MASK +#define DDRC_DRAMTMG3_T_MRD_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MRD_SHIFT 12 +#define DDRC_DRAMTMG3_T_MRD_MASK 0x0003F000U + +/* +* tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com + * mand and following non-load mode command. If C/A parity for DDR4 is used + * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or + * tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if + * using RDIMM, depending on the PHY, it may be necessary to use a value of + * tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a + * pplied to mode register writes by the RDIMM chip. +*/ +#undef DDRC_DRAMTMG3_T_MOD_DEFVAL +#undef DDRC_DRAMTMG3_T_MOD_SHIFT +#undef DDRC_DRAMTMG3_T_MOD_MASK +#define DDRC_DRAMTMG3_T_MOD_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MOD_SHIFT 0 +#define DDRC_DRAMTMG3_T_MOD_MASK 0x000003FFU + +/* +* tRCD - tAL: Minimum time from activate to read or write command to same + * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD + * - tAL)/2) and round it up to the next integer value. Minimum value allow + * ed for this register is 1, which implies minimum (tRCD - tAL) value to b + * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. +*/ +#undef DDRC_DRAMTMG4_T_RCD_DEFVAL +#undef DDRC_DRAMTMG4_T_RCD_SHIFT +#undef DDRC_DRAMTMG4_T_RCD_MASK +#define DDRC_DRAMTMG4_T_RCD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RCD_SHIFT 24 +#define DDRC_DRAMTMG4_T_RCD_MASK 0x1F000000U + +/* +* DDR4: tCCD_L: This is the minimum time between two reads or two writes f + * or same bank group. Others: tCCD: This is the minimum time between two r + * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t + * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U + * nit: clocks. +*/ +#undef DDRC_DRAMTMG4_T_CCD_DEFVAL +#undef DDRC_DRAMTMG4_T_CCD_SHIFT +#undef DDRC_DRAMTMG4_T_CCD_MASK +#define DDRC_DRAMTMG4_T_CCD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_CCD_SHIFT 16 +#define DDRC_DRAMTMG4_T_CCD_MASK 0x000F0000U + +/* +* DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f + * or same bank group. Others: tRRD: Minimum time between activates from ba + * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni + * t: Clocks. +*/ +#undef DDRC_DRAMTMG4_T_RRD_DEFVAL +#undef DDRC_DRAMTMG4_T_RRD_SHIFT +#undef DDRC_DRAMTMG4_T_RRD_MASK +#define DDRC_DRAMTMG4_T_RRD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RRD_SHIFT 8 +#define DDRC_DRAMTMG4_T_RRD_MASK 0x00000F00U + +/* +* tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ + * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM + * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t + * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho + * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. +*/ +#undef DDRC_DRAMTMG4_T_RP_DEFVAL +#undef DDRC_DRAMTMG4_T_RP_SHIFT +#undef DDRC_DRAMTMG4_T_RP_MASK +#define DDRC_DRAMTMG4_T_RP_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RP_SHIFT 0 +#define DDRC_DRAMTMG4_T_RP_MASK 0x0000001FU + +/* +* This is the time before Self Refresh Exit that CK is maintained as a val + * id clock before issuing SRX. Specifies the clock stable time before SRX. + * Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK + * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. +*/ +#undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL +#undef DDRC_DRAMTMG5_T_CKSRX_SHIFT +#undef DDRC_DRAMTMG5_T_CKSRX_MASK +#define DDRC_DRAMTMG5_T_CKSRX_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKSRX_SHIFT 24 +#define DDRC_DRAMTMG5_T_CKSRX_MASK 0x0F000000U + +/* +* This is the time after Self Refresh Down Entry that CK is maintained as + * a valid clock. Specifies the clock disable delay after SRE. Recommended + * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 + * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations + * with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw + * o and round it up to next integer. +*/ +#undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL +#undef DDRC_DRAMTMG5_T_CKSRE_SHIFT +#undef DDRC_DRAMTMG5_T_CKSRE_MASK +#define DDRC_DRAMTMG5_T_CKSRE_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKSRE_SHIFT 16 +#define DDRC_DRAMTMG5_T_CKSRE_MASK 0x000F0000U + +/* +* Minimum CKE low width for Self refresh or Self refresh power down entry + * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF + * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: + * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ + * _RATIO=2, program this to recommended value divided by two and round it + * up to next integer. +*/ +#undef DDRC_DRAMTMG5_T_CKESR_DEFVAL +#undef DDRC_DRAMTMG5_T_CKESR_SHIFT +#undef DDRC_DRAMTMG5_T_CKESR_MASK +#define DDRC_DRAMTMG5_T_CKESR_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKESR_SHIFT 8 +#define DDRC_DRAMTMG5_T_CKESR_MASK 0x00003F00U + +/* +* Minimum number of cycles of CKE HIGH/LOW during power-down and self refr + * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP + * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/ + * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration + * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and + * round it up to the next integer value. Unit: Clocks. +*/ +#undef DDRC_DRAMTMG5_T_CKE_DEFVAL +#undef DDRC_DRAMTMG5_T_CKE_SHIFT +#undef DDRC_DRAMTMG5_T_CKE_MASK +#define DDRC_DRAMTMG5_T_CKE_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKE_SHIFT 0 +#define DDRC_DRAMTMG5_T_CKE_MASK 0x0000001FU + +/* +* This is the time after Deep Power Down Entry that CK is maintained as a + * valid clock. Specifies the clock disable delay after DPDE. Recommended s + * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. This is only present for designs supporting mDDR + * or LPDDR2/LPDDR3 devices. +*/ +#undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL +#undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT +#undef DDRC_DRAMTMG6_T_CKDPDE_MASK +#define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT 24 +#define DDRC_DRAMTMG6_T_CKDPDE_MASK 0x0F000000U + +/* +* This is the time before Deep Power Down Exit that CK is maintained as a + * valid clock before issuing DPDX. Specifies the clock stable time before + * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config + * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid + * ed by two and round it up to next integer. This is only present for desi + * gns supporting mDDR or LPDDR2 devices. +*/ +#undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL +#undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT +#undef DDRC_DRAMTMG6_T_CKDPDX_MASK +#define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT 16 +#define DDRC_DRAMTMG6_T_CKDPDX_MASK 0x000F0000U + +/* +* This is the time before Clock Stop Exit that CK is maintained as a valid + * clock before issuing Clock Stop Exit. Specifies the clock stable time b + * efore next command after Clock Stop Exit. Recommended settings: - mDDR: + * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio + * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by + * two and round it up to next integer. This is only present for designs su + * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ +#undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL +#undef DDRC_DRAMTMG6_T_CKCSX_SHIFT +#undef DDRC_DRAMTMG6_T_CKCSX_MASK +#define DDRC_DRAMTMG6_T_CKCSX_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKCSX_SHIFT 0 +#define DDRC_DRAMTMG6_T_CKCSX_MASK 0x0000000FU + +/* +* This is the time after Power Down Entry that CK is maintained as a valid + * clock. Specifies the clock disable delay after PDE. Recommended setting + * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration + * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t + * wo and round it up to next integer. This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ +#undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL +#undef DDRC_DRAMTMG7_T_CKPDE_SHIFT +#undef DDRC_DRAMTMG7_T_CKPDE_MASK +#define DDRC_DRAMTMG7_T_CKPDE_DEFVAL 0x00000202 +#define DDRC_DRAMTMG7_T_CKPDE_SHIFT 8 +#define DDRC_DRAMTMG7_T_CKPDE_MASK 0x00000F00U + +/* +* This is the time before Power Down Exit that CK is maintained as a valid + * clock before issuing PDX. Specifies the clock stable time before PDX. R + * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c + * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value + * divided by two and round it up to next integer. This is only present for + * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ +#undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL +#undef DDRC_DRAMTMG7_T_CKPDX_SHIFT +#undef DDRC_DRAMTMG7_T_CKPDX_MASK +#define DDRC_DRAMTMG7_T_CKPDX_DEFVAL 0x00000202 +#define DDRC_DRAMTMG7_T_CKPDX_SHIFT 0 +#define DDRC_DRAMTMG7_T_CKPDX_MASK 0x0000000FU + +/* +* tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and + * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this + * to the above value divided by 2 and round up to next integer value. Unit + * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com + * mands. Note: Ensure this is less than or equal to t_xs_x32. +*/ +#undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL +#undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT +#undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK +#define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 24 +#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 0x7F000000U + +/* +* tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S + * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th + * is to the above value divided by 2 and round up to next integer value. U + * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to + * t_xs_x32. +*/ +#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL +#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT +#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 16 +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 0x007F0000U + +/* +* tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config + * urations with MEMC_FREQ_RATIO=2, program this to the above value divided + * by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. +*/ +#undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL +#undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT +#undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK +#define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 8 +#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 0x00007F00U + +/* +* tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi + * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide + * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. +*/ +#undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL +#undef DDRC_DRAMTMG8_T_XS_X32_SHIFT +#undef DDRC_DRAMTMG8_T_XS_X32_MASK +#define DDRC_DRAMTMG8_T_XS_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_X32_SHIFT 0 +#define DDRC_DRAMTMG8_T_XS_X32_MASK 0x0000007FU + +/* +* DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o + * nly with MEMC_FREQ_RATIO=2 +*/ +#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL +#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT +#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 30 +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 0x40000000U + +/* +* tCCD_S: This is the minimum time between two reads or two writes for dif + * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m + * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2 + * , program this to (tCCD_S/2) and round it up to the next integer value. + * Present only in designs configured to support DDR4. Unit: clocks. +*/ +#undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL +#undef DDRC_DRAMTMG9_T_CCD_S_SHIFT +#undef DDRC_DRAMTMG9_T_CCD_S_MASK +#define DDRC_DRAMTMG9_T_CCD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_T_CCD_S_SHIFT 16 +#define DDRC_DRAMTMG9_T_CCD_S_MASK 0x00070000U + +/* +* tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif + * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th + * is to (tRRD_S/2) and round it up to the next integer value. Present only + * in designs configured to support DDR4. Unit: Clocks. +*/ +#undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL +#undef DDRC_DRAMTMG9_T_RRD_S_SHIFT +#undef DDRC_DRAMTMG9_T_RRD_S_MASK +#define DDRC_DRAMTMG9_T_RRD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_T_RRD_S_SHIFT 8 +#define DDRC_DRAMTMG9_T_RRD_S_MASK 0x00000F00U + +/* +* CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command + * for different bank group. Includes time for bus turnaround, recovery ti + * mes, and all per-bank, per-rank, and global constraints. Present only in + * designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr + * ite latency - PL = Parity latency - BL = burst length. This must match t + * he value programmed in the BL bit of the mode register to the SDRAM - tW + * TR_S = internal write to read command delay for different bank group. Th + * is comes directly from the SDRAM specification. For configurations with + * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation + * by 2, and round it up to next integer. +*/ +#undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL +#undef DDRC_DRAMTMG9_WR2RD_S_SHIFT +#undef DDRC_DRAMTMG9_WR2RD_S_MASK +#define DDRC_DRAMTMG9_WR2RD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_WR2RD_S_SHIFT 0 +#define DDRC_DRAMTMG9_WR2RD_S_MASK 0x0000003FU + +/* +* tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL + * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2 + * ) and round it up to the next integer value. Present only in designs con + * figured to support DDR4. Unit: Multiples of 32 clocks. +*/ +#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL +#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT +#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 24 +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 0x7F000000U + +/* +* tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For + * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2 + * )+1. Present only in designs configured to support DDR4. Unit: clocks. +*/ +#undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL +#undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT +#undef DDRC_DRAMTMG11_T_MPX_LH_MASK +#define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT 16 +#define DDRC_DRAMTMG11_T_MPX_LH_MASK 0x001F0000U + +/* +* tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_ + * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int + * eger value. Present only in designs configured to support DDR4. Unit: Cl + * ocks. +*/ +#undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL +#undef DDRC_DRAMTMG11_T_MPX_S_SHIFT +#undef DDRC_DRAMTMG11_T_MPX_S_MASK +#define DDRC_DRAMTMG11_T_MPX_S_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_MPX_S_SHIFT 8 +#define DDRC_DRAMTMG11_T_MPX_S_MASK 0x00000300U + +/* +* tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i + * n designs configured to support DDR4. Unit: Clocks. For configurations w + * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat + * ion by 2, and round it up to next integer. +*/ +#undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL +#undef DDRC_DRAMTMG11_T_CKMPE_SHIFT +#undef DDRC_DRAMTMG11_T_CKMPE_MASK +#define DDRC_DRAMTMG11_T_CKMPE_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_CKMPE_SHIFT 0 +#define DDRC_DRAMTMG11_T_CKMPE_MASK 0x0000001FU + +/* +* tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg + * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr + * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu + * e. +*/ +#undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL +#undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT +#undef DDRC_DRAMTMG12_T_CMDCKE_MASK +#define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT 16 +#define DDRC_DRAMTMG12_T_CMDCKE_MASK 0x00030000U + +/* +* tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat + * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u + * p to next integer value. +*/ +#undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL +#undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT +#undef DDRC_DRAMTMG12_T_CKEHCMD_MASK +#define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 8 +#define DDRC_DRAMTMG12_T_CKEHCMD_MASK 0x00000F00U + +/* +* tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2) + * and round it up to next integer value. +*/ +#undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL +#undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT +#undef DDRC_DRAMTMG12_T_MRD_PDA_MASK +#define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 0 +#define DDRC_DRAMTMG12_T_MRD_PDA_MASK 0x0000001FU + +/* +* - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg + * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration + * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati + * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre + * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ +#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL +#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT +#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 31 +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 0x80000000U + +/* +* - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres + * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 + * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio + * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i + * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present + * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ +#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL +#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT +#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 30 +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 0x40000000U + +/* +* - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC + * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co + * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share + * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR + * 3/LPDDR4 devices. +*/ +#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL +#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT +#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 29 +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 0x20000000U + +/* +* - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. + * Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com + * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4 + * mode. This is only present for designs supporting DDR4 devices. +*/ +#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL +#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT +#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 28 +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 0x10000000U + +/* +* tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe + * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St + * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO + * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int + * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th + * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t + * o the next integer value. Unit: Clock cycles. This is only present for d + * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ +#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL +#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT +#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 16 +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 0x07FF0000U + +/* +* tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of + * NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command + * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t + * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy + * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP + * DDR3/LPDDR4 devices. +*/ +#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL +#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT +#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 0 +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 0x000003FFU + +/* +* tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati + * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_ + * RATIO=2, program this to tZQReset/2 and round it up to the next integer + * value. Unit: Clock cycles. This is only present for designs supporting L + * PDDR2/LPDDR3/LPDDR4 devices. +*/ +#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL +#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT +#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 0x02000100 +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 20 +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 0x3FF00000U + +/* +* Average interval to wait between automatically issuing ZQCS (ZQ calibrat + * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR + * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles + * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 + * /LPDDR4 devices. +*/ +#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL +#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT +#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 0x02000100 +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 0 +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 0x000FFFFFU + +/* +* Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. +*/ +#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL +#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT +#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 24 +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 0x1F000000U + +/* +* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. +*/ +#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL +#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT +#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 23 +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 0x00800000U + +/* +* Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks +*/ +#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL +#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT +#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 16 +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 0x003F0000U + +/* +* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. +*/ +#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL +#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT +#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 15 +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 0x00008000U + +/* +* Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks +*/ +#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL +#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT +#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 8 +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 0x00003F00U + +/* +* Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. +*/ +#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL +#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT +#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 0 +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 0x0000003FU + +/* +* Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated command is driven. This field is used + * for CAL mode, should be set to '0' or the value which matches the CAL mo + * de register setting in the DRAM. If the PHY can add the latency for CAL + * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 +*/ +#undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL +#undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT +#undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK +#define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 28 +#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 0xF0000000U + +/* +* Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated dfi_parity_in signal is driven. +*/ +#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL +#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT +#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 24 +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 0x03000000U + +/* +* Specifies the number of DFI clocks between when the dfi_wrdata_en signal + * is asserted and when the corresponding write data transfer is completed + * on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d + * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set + * to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI + * 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va + * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_ + * RATIO=2, divide PHY's value by 2 and round up to next integer. If using + * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks +*/ +#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL +#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT +#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 16 +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 0x001F0000U + +/* +* Specifies the number of DFI clock cycles from the assertion of the dfi_d + * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev + * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock + * and the memory clock are not phase aligned, this timing parameter should + * be rounded up to the next integer value. +*/ +#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL +#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT +#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 8 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 0x00000F00U + +/* +* Specifies the number of DFI clock cycles from the de-assertion of the df + * i_dram_clk_disable signal on the DFI until the first valid rising edge o + * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the + * DFI clock and the memory clock are not phase aligned, this timing param + * eter should be rounded up to the next integer value. +*/ +#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL +#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT +#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 0 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 0x0000000FU + +/* +* Setting for DFI's tlp_resp time. Same value is used for both Power Down, + * Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s + * pecification onwards, recommends using a fixed value of 7 always. +*/ +#undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL +#undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT +#undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK +#define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 24 +#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 0x0F000000U + +/* +* Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente + * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 + * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5 + * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - + * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553 + * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T + * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices + * . +*/ +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 20 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 0x00F00000U + +/* +* Enables DFI Low Power interface handshaking during Deep Power Down Entry + * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3 devices. +*/ +#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL +#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT +#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 16 +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 0x00010000U + +/* +* Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered + * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc + * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 + * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 + * - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c + * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited +*/ +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 12 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 0x0000F000U + +/* +* Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex + * it. - 0 - Disabled - 1 - Enabled +*/ +#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL +#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT +#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 8 +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 0x00000100U + +/* +* Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle + * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy + * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - + * 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc + * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited +*/ +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 4 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 0x000000F0U + +/* +* Enables DFI Low Power interface handshaking during Power Down Entry/Exit + * . - 0 - Disabled - 1 - Enabled +*/ +#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL +#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT +#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 0 +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 0x00000001U + +/* +* Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is + * entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 + * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x + * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl + * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - + * 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi + * ted This is only present for designs supporting DDR4 devices. +*/ +#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL +#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT +#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 0x00000000 +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 4 +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 0x000000F0U + +/* +* Enables DFI Low Power interface handshaking during Maximum Power Saving + * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d + * esigns supporting DDR4 devices. +*/ +#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL +#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT +#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 0x00000000 +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 0 +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 0x00000001U + +/* +* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc + * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. +*/ +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT 31 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK 0x80000000U + +/* +* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * following a self-refresh exit. The core must issue the dfi_ctrlupd_req + * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct + * rlupd_req after exiting self-refresh. +*/ +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT 30 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK 0x40000000U + +/* +* Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si + * gnal can assert. Lowest value to assign to this variable is 0x40. Unit: + * Clocks +*/ +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT 16 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK 0x03FF0000U + +/* +* Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si + * gnal must be asserted. The uMCTL2 expects the PHY to respond within this + * time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup + * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this + * variable is 0x3. Unit: Clocks +*/ +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT 0 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK 0x000003FFU + +/* +* This is the minimum amount of time between uMCTL2 initiated DFI update r + * equests (which is executed whenever the uMCTL2 is idle). Set this number + * higher to reduce the frequency of update requests, which can have a sma + * ll impact on the latency of the first read request when the uMCTL2 is id + * le. Unit: 1024 clocks +*/ +#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL +#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT +#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 0x00000000 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 16 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 0x00FF0000U + +/* +* This is the maximum amount of time between uMCTL2 initiated DFI update r + * equests. This timer resets with each update request; when the timer expi + * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd + * _ackx is received. PHY can use this idle time to recalibrate the delay l + * ines to the DLLs. The DFI controller update is also used to reset PHY FI + * FO pointers in case of data capture errors. Updates are required to main + * tain calibration over PVT, but frequent updates may impact performance. + * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must + * be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl + * ocks +*/ +#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL +#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT +#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 0x00000000 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 0 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 0x000000FFU + +/* +* Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal + * s are active low - 1: Signals are active high +*/ +#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL +#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT +#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 0x00000001 +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 2 +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 0x00000004U + +/* +* DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. + * - 1 - PHY implements DBI functionality. Present only in designs configu + * red to support DDR4 and LPDDR4. +*/ +#undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL +#undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT +#undef DDRC_DFIMISC_PHY_DBI_MODE_MASK +#define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 0x00000001 +#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 1 +#define DDRC_DFIMISC_PHY_DBI_MODE_MASK 0x00000002U + +/* +* PHY initialization complete enable signal. When asserted the dfi_init_co + * mplete signal can be used to trigger SDRAM initialisation +*/ +#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL +#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT +#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 0x00000001 +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 0 +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 0x00000001U + +/* +* >Number of clocks between when a read command is sent on the DFI control + * interface and when the associated dfi_rddata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe + * cification for correct value. +*/ +#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL +#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT +#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 0x00000202 +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 8 +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 0x00003F00U + +/* +* Number of clocks between when a write command is sent on the DFI control + * interface and when the associated dfi_wrdata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe + * cification for correct value. +*/ +#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL +#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT +#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 0x00000202 +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 0 +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 0x0000003FU + +/* +* Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D + * BI is enabled. This signal must be set the same value as DRAM's mode reg + * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b + * e set to 0. - LPDDR4: MR3[6] +*/ +#undef DDRC_DBICTL_RD_DBI_EN_DEFVAL +#undef DDRC_DBICTL_RD_DBI_EN_SHIFT +#undef DDRC_DBICTL_RD_DBI_EN_MASK +#define DDRC_DBICTL_RD_DBI_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_RD_DBI_EN_SHIFT 2 +#define DDRC_DBICTL_RD_DBI_EN_MASK 0x00000004U + +/* +* Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ + * e DBI is enabled. This signal must be set the same value as DRAM's mode + * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus + * t be set to 0. - LPDDR4: MR3[7] +*/ +#undef DDRC_DBICTL_WR_DBI_EN_DEFVAL +#undef DDRC_DBICTL_WR_DBI_EN_SHIFT +#undef DDRC_DBICTL_WR_DBI_EN_MASK +#define DDRC_DBICTL_WR_DBI_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_WR_DBI_EN_SHIFT 1 +#define DDRC_DBICTL_WR_DBI_EN_MASK 0x00000002U + +/* +* DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi + * s signal must be set the same logical value as DRAM's mode register. - D + * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th + * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13 + * [5] which is opposite polarity from this signal +*/ +#undef DDRC_DBICTL_DM_EN_DEFVAL +#undef DDRC_DBICTL_DM_EN_SHIFT +#undef DDRC_DBICTL_DM_EN_MASK +#define DDRC_DBICTL_DM_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_DM_EN_SHIFT 0 +#define DDRC_DBICTL_DM_EN_MASK 0x00000001U + +/* +* Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t + * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, r + * ank address bit 0 is set to 0. +*/ +#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL +#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT +#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 0 +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 0x0000001FU + +/* +* Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t + * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, ba + * nk address bit 2 is set to 0. +*/ +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 16 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 0x001F0000U + +/* +* Selects the HIF address bits used as bank address bit 1. Valid Range: 0 + * to 30 Internal Base: 3 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. +*/ +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 8 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 0x00001F00U + +/* +* Selects the HIF address bits used as bank address bit 0. Valid Range: 0 + * to 30 Internal Base: 2 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. +*/ +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 0 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 0x0000001FU + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base + * : 5 The selected HIF address bit is determined by adding the internal ba + * se to the value of this field. If set to 15, this column address bit is + * set to 0. +*/ +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 24 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 0x0F000000U + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: + * 4 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 16 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 0x000F0000U + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1 + * 6, it is required to program this to 0, hence register does not exist in + * this case. +*/ +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 8 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 0x00000F00U + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 + * or 16, it is required to program this to 0. +*/ +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 0 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 0x0000000FU + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: + * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/ + * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + * HIF address bit is determined by adding the internal base to the value o + * f this field. If set to 15, this column address bit is set to 0. Note: P + * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo + * r indicating auto-precharge, and hence no source address bit can be mapp + * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit + * for auto-precharge in the CA bus and hence column bit 10 is used. +*/ +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 24 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 0x0F000000U + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 + * to 7, and 15 Internal Base: 8 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi + * cation, column address bit 10 is reserved for indicating auto-precharge, + * and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA + * bus and hence column bit 10 is used. +*/ +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 16 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 0x000F0000U + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: + * 7 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 8 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 0x00000F00U + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: + * 6 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 0 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 0x0000000FU + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m + * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un + * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, + * and 15 Internal Base: 11 The selected HIF address bit is determined by + * adding the internal base to the value of this field. If set to 15, this + * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio + * n, column address bit 10 is reserved for indicating auto-precharge, and + * hence no source address bit can be mapped to column address bit 10. In L + * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus + * and hence column bit 10 is used. +*/ +#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL +#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT +#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 0x00000000 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 8 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 0x00000F00U + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the + * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) + * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied + * to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + * address bit is determined by adding the internal base to the value of t + * his field. If set to 15, this column address bit is set to 0. Note: Per + * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i + * ndicating auto-precharge, and hence no source address bit can be mapped + * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + * auto-precharge in the CA bus and hence column bit 10 is used. +*/ +#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL +#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT +#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 0x00000000 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 0 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 0x0000000FU + +/* +* Selects the HIF address bit used as row address bit 11. Valid Range: 0 t + * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 11 is set to 0. +*/ +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 24 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 0x0F000000U + +/* +* Selects the HIF address bits used as row address bits 2 to 10. Valid Ran + * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row + * address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro + * w address bit 10) The selected HIF address bit for each of the row addre + * ss bits is determined by adding the internal base to the value of this f + * ield. When value 15 is used the values of row address bits 2 to 10 are d + * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. +*/ +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 16 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 0x000F0000U + +/* +* Selects the HIF address bits used as row address bit 1. Valid Range: 0 t + * o 11 Internal Base: 7 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. +*/ +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 8 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 0x00000F00U + +/* +* Selects the HIF address bits used as row address bit 0. Valid Range: 0 t + * o 11 Internal Base: 6 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. +*/ +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 0 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 0x0000000FU + +/* +* Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 + * - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]= + * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. + * All addresses are valid Present only in designs configured to support L + * PDDR3. +*/ +#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL +#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT +#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 31 +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 0x80000000U + +/* +* Selects the HIF address bit used as row address bit 15. Valid Range: 0 t + * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 15 is set to 0. +*/ +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 24 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 0x0F000000U + +/* +* Selects the HIF address bit used as row address bit 14. Valid Range: 0 t + * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 14 is set to 0. +*/ +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 16 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 0x000F0000U + +/* +* Selects the HIF address bit used as row address bit 13. Valid Range: 0 t + * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 13 is set to 0. +*/ +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 8 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 0x00000F00U + +/* +* Selects the HIF address bit used as row address bit 12. Valid Range: 0 t + * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 12 is set to 0. +*/ +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 0 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 0x0000000FU + +/* +* Selects the HIF address bit used as row address bit 17. Valid Range: 0 t + * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 17 is set to 0. +*/ +#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL +#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT +#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 0x00000000 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 8 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 0x00000F00U + +/* +* Selects the HIF address bit used as row address bit 16. Valid Range: 0 t + * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 16 is set to 0. +*/ +#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL +#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT +#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 0x00000000 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 0 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 0x0000000FU + +/* +* Selects the HIF address bits used as bank group address bit 1. Valid Ran + * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea + * ch of the bank group address bits is determined by adding the internal b + * ase to the value of this field. If set to 31, bank group address bit 1 i + * s set to 0. +*/ +#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL +#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT +#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 8 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 0x00001F00U + +/* +* Selects the HIF address bits used as bank group address bit 0. Valid Ran + * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th + * e bank group address bits is determined by adding the internal base to t + * he value of this field. +*/ +#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL +#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT +#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 0 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 0x0000001FU + +/* +* Selects the HIF address bits used as row address bit 5. Valid Range: 0 t + * o 11 Internal Base: 11 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 24 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 0x0F000000U + +/* +* Selects the HIF address bits used as row address bit 4. Valid Range: 0 t + * o 11 Internal Base: 10 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 16 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 0x000F0000U + +/* +* Selects the HIF address bits used as row address bit 3. Valid Range: 0 t + * o 11 Internal Base: 9 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. +*/ +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 8 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 0x00000F00U + +/* +* Selects the HIF address bits used as row address bit 2. Valid Range: 0 t + * o 11 Internal Base: 8 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. +*/ +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 0 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 0x0000000FU + +/* +* Selects the HIF address bits used as row address bit 9. Valid Range: 0 t + * o 11 Internal Base: 15 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 24 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 0x0F000000U + +/* +* Selects the HIF address bits used as row address bit 8. Valid Range: 0 t + * o 11 Internal Base: 14 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 16 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 0x000F0000U + +/* +* Selects the HIF address bits used as row address bit 7. Valid Range: 0 t + * o 11 Internal Base: 13 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 8 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 0x00000F00U + +/* +* Selects the HIF address bits used as row address bit 6. Valid Range: 0 t + * o 11 Internal Base: 12 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 0 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 0x0000000FU + +/* +* Selects the HIF address bits used as row address bit 10. Valid Range: 0 + * to 11 Internal Base: 16 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of + * this field. This register field is used only when ADDRMAP5.addrmap_row_b + * 2_10 is set to value 15. +*/ +#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL +#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT +#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 0 +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 0x0000000FU + +/* +* Cycles to hold ODT for a write command. The minimum supported value is 2 + * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800 + * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D + * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR + * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 ( + * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) +*/ +#undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL +#undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT +#undef DDRC_ODTCFG_WR_ODT_HOLD_MASK +#define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 0x04000400 +#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 24 +#define DDRC_ODTCFG_WR_ODT_HOLD_MASK 0x0F000000U + +/* +* The delay, in clock cycles, from issuing a write command to setting ODT + * values associated with that command. ODT setting must remain constant fo + * r the entire time that DQS is driven by the uMCTL2. Recommended values: + * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + + * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo + * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust + * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) +*/ +#undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL +#undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT +#undef DDRC_ODTCFG_WR_ODT_DELAY_MASK +#define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 0x04000400 +#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 16 +#define DDRC_ODTCFG_WR_ODT_DELAY_MASK 0x001F0000U + +/* +* Cycles to hold ODT for a read command. The minimum supported value is 2. + * Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - + * BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 + * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p + * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + + * RU(tODTon(max)/tCK) +*/ +#undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL +#undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT +#undef DDRC_ODTCFG_RD_ODT_HOLD_MASK +#define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 0x04000400 +#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 8 +#define DDRC_ODTCFG_RD_ODT_HOLD_MASK 0x00000F00U + +/* +* The delay, in clock cycles, from issuing a read command to setting ODT v + * alues associated with that command. ODT setting must remain constant for + * the entire time that DQS is driven by the uMCTL2. Recommended values: D + * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL + * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C + * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat + * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK + * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre + * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su + * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R + * U(tODTon(max)/tCK) +*/ +#undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL +#undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT +#undef DDRC_ODTCFG_RD_ODT_DELAY_MASK +#define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 0x04000400 +#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 2 +#define DDRC_ODTCFG_RD_ODT_DELAY_MASK 0x0000007CU + +/* +* Indicates which remote ODTs must be turned on during a read from rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. Present only in configurations that have 2 or more + * ranks +*/ +#undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL +#undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT +#undef DDRC_ODTMAP_RANK1_RD_ODT_MASK +#define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 12 +#define DDRC_ODTMAP_RANK1_RD_ODT_MASK 0x00003000U + +/* +* Indicates which remote ODTs must be turned on during a write to rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. Present only in configurations that have 2 or more r + * anks +*/ +#undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL +#undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT +#undef DDRC_ODTMAP_RANK1_WR_ODT_MASK +#define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 8 +#define DDRC_ODTMAP_RANK1_WR_ODT_MASK 0x00000300U + +/* +* Indicates which remote ODTs must be turned on during a read from rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. +*/ +#undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL +#undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT +#undef DDRC_ODTMAP_RANK0_RD_ODT_MASK +#define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 4 +#define DDRC_ODTMAP_RANK0_RD_ODT_MASK 0x00000030U + +/* +* Indicates which remote ODTs must be turned on during a write to rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. +*/ +#undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL +#undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT +#undef DDRC_ODTMAP_RANK0_WR_ODT_MASK +#define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 0 +#define DDRC_ODTMAP_RANK0_WR_ODT_MASK 0x00000003U + +/* +* When the preferred transaction store is empty for these many clock cycle + * s, switch to the alternate transaction store if it is non-empty. The rea + * d transaction store (both high and low priority) is the default preferre + * d transaction store and the write transaction store is the alternative s + * tore. When prefer write over read is set this is reversed. 0x0 is a lega + * l value for this register. When set to 0x0, the transaction store switch + * ing will happen immediately when the switching conditions become true. F + * OR PERFORMANCE ONLY +*/ +#undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL +#undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT +#undef DDRC_SCHED_RDWR_IDLE_GAP_MASK +#define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 0x00002005 +#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 24 +#define DDRC_SCHED_RDWR_IDLE_GAP_MASK 0x7F000000U + +/* +* UNUSED +*/ +#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL +#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT +#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 0x00002005 +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 16 +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 0x00FF0000U + +/* +* Number of entries in the low priority transaction store is this value + + * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent + * ries available for the high priority transaction store. Setting this to + * maximum value allocates all entries to low priority transaction store. S + * etting this to 0 allocates 1 entry to low priority transaction store and + * the rest to high priority transaction store. Note: In ECC configuration + * s, the numbers of write and low priority read credits issued is one less + * than in the non-ECC case. One entry each is reserved in the write and l + * ow-priority read CAMs for storing the RMW requests arising out of single + * bit error correction RMW operation. +*/ +#undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL +#undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT +#undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK +#define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 0x00002005 +#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 8 +#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK 0x00003F00U + +/* +* If true, bank is kept open only while there are page hit transactions av + * ailable in the CAM to that bank. The last read or write command in the C + * AM with a bank and page hit will be executed with auto-precharge if SCHE + * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos + * e_timer is set to 0, explicit precharge (and not auto-precharge) may be + * issued in some cases where there is a mode switch between Write and Read + * or between LPR and HPR. The Read and Write commands that are executed a + * s part of the ECC scrub requests are also executed without auto-precharg + * e. If false, the bank remains open until there is a need to close it (to + * open a different page, or for page timeout or refresh timeout) - also k + * nown as open page policy. The open page policy can be overridden by sett + * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + * The pageclose feature provids a midway between Open and Close page polic + * ies. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_SCHED_PAGECLOSE_DEFVAL +#undef DDRC_SCHED_PAGECLOSE_SHIFT +#undef DDRC_SCHED_PAGECLOSE_MASK +#define DDRC_SCHED_PAGECLOSE_DEFVAL 0x00002005 +#define DDRC_SCHED_PAGECLOSE_SHIFT 2 +#define DDRC_SCHED_PAGECLOSE_MASK 0x00000004U + +/* +* If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. +*/ +#undef DDRC_SCHED_PREFER_WRITE_DEFVAL +#undef DDRC_SCHED_PREFER_WRITE_SHIFT +#undef DDRC_SCHED_PREFER_WRITE_MASK +#define DDRC_SCHED_PREFER_WRITE_DEFVAL 0x00002005 +#define DDRC_SCHED_PREFER_WRITE_SHIFT 1 +#define DDRC_SCHED_PREFER_WRITE_MASK 0x00000002U + +/* +* Active low signal. When asserted ('0'), all incoming transactions are fo + * rced to low priority. This implies that all High Priority Read (HPR) and + * Variable Priority Read commands (VPR) will be treated as Low Priority R + * ead (LPR) commands. On the write side, all Variable Priority Write (VPW) + * commands will be treated as Normal Priority Write (NPW) commands. Forci + * ng the incoming transactions to low priority implicitly turns off Bypass + * path for read commands. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL +#undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT +#undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK +#define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 0x00002005 +#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 0 +#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK 0x00000001U + +/* +* Number of transactions that are serviced once the LPR queue goes critica + * l is the smaller of: - (a) This number - (b) Number of transactions avai + * lable. Unit: Transaction. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL +#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT +#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 0x0F00007F +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 24 +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 0xFF000000U + +/* +* Number of clocks that the LPR queue can be starved before it goes critic + * al. The minimum valid functional value for this register is 0x1. Program + * ming it to 0x0 will disable the starvation functionality; during normal + * operation, this function should not be disabled as it will cause excessi + * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL +#undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT +#undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK +#define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 0x0F00007F +#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 0 +#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 0x0000FFFFU + +/* +* Number of transactions that are serviced once the WR queue goes critical + * is the smaller of: - (a) This number - (b) Number of transactions avail + * able. Unit: Transaction. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL +#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT +#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 0x0F00007F +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 24 +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 0xFF000000U + +/* +* Number of clocks that the WR queue can be starved before it goes critica + * l. The minimum valid functional value for this register is 0x1. Programm + * ing it to 0x0 will disable the starvation functionality; during normal o + * peration, this function should not be disabled as it will cause excessiv + * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL +#undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT +#undef DDRC_PERFWR1_W_MAX_STARVE_MASK +#define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 0x0F00007F +#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT 0 +#define DDRC_PERFWR1_W_MAX_STARVE_MASK 0x0000FFFFU + +/* +* DQ nibble map for DQ bits [12-15] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT 24 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [8-11] Present only in designs configured to s + * upport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT 16 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [4-7] Present only in designs configured to su + * pport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT 8 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [0-3] Present only in designs configured to su + * pport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT 0 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [28-31] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT 24 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [24-27] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT 16 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [20-23] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT 8 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [16-19] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT 0 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [44-47] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT 24 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [40-43] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT 16 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [36-39] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT 8 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [32-35] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT 0 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [60-63] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT 24 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [56-59] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT 16 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [52-55] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT 8 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [48-51] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT 0 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK 0x000000FFU + +/* +* DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf + * igured to support DDR4. +*/ +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL 0x00000000 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT 8 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK 0x0000FF00U + +/* +* DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf + * igured to support DDR4. +*/ +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL 0x00000000 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT 0 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK 0x000000FFU + +/* +* All even ranks have the same DQ mapping controled by DQMAP0-4 register a + * s rank 0. This register provides DQ swap function for all odd ranks to s + * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b + * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba + * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs + * configured to support DDR4. +*/ +#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL +#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT +#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 0 +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 0x00000001U + +/* +* When this is set to '0', auto-precharge is disabled for the flushed comm + * and in a collision case. Collision cases are write followed by read to s + * ame address, read followed by write to same address, or write followed b + * y write to same address with DBG0.dis_wc bit = 1 (where same address com + * parisons exclude the two address bits representing critical word). FOR D + * EBUG ONLY. +*/ +#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL +#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT +#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 0x00000000 +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 4 +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 0x00000010U + +/* +* When 1, disable write combine. FOR DEBUG ONLY +*/ +#undef DDRC_DBG0_DIS_WC_DEFVAL +#undef DDRC_DBG0_DIS_WC_SHIFT +#undef DDRC_DBG0_DIS_WC_MASK +#define DDRC_DBG0_DIS_WC_DEFVAL 0x00000000 +#define DDRC_DBG0_DIS_WC_SHIFT 0 +#define DDRC_DBG0_DIS_WC_MASK 0x00000001U + +/* +* Setting this register bit to 1 allows refresh and ZQCS commands to be tr + * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD. + * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore + * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and + * ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor + * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no + * function, and are ignored by the uMCTL2 logic. This register is static, + * and may only be changed when the DDRC reset signal, core_ddrc_rstn, is + * asserted (0). +*/ +#undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL +#undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT +#undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK +#define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 0x00000000 +#define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 31 +#define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 0x80000000U + +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct + * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit + * is automatically cleared. This operation must only be performed when DF + * IUPD0.dis_auto_ctrlupd=1. +*/ +#undef DDRC_DBGCMD_CTRLUPD_DEFVAL +#undef DDRC_DBGCMD_CTRLUPD_SHIFT +#undef DDRC_DBGCMD_CTRLUPD_MASK +#define DDRC_DBGCMD_CTRLUPD_DEFVAL 0x00000000 +#define DDRC_DBGCMD_CTRLUPD_SHIFT 5 +#define DDRC_DBGCMD_CTRLUPD_MASK 0x00000020U + +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS ( + * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi + * s request is stored in the uMCTL2, the bit is automatically cleared. Thi + * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom + * mended NOT to set this register bit if in Init operating mode. This regi + * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown + * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo + * de. +*/ +#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL +#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT +#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 0x00000000 +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 4 +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 0x00000010U + +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be + * set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. +*/ +#undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL +#undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT +#undef DDRC_DBGCMD_RANK1_REFRESH_MASK +#define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 0x00000000 +#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT 1 +#define DDRC_DBGCMD_RANK1_REFRESH_MASK 0x00000002U + +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be + * set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. +*/ +#undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL +#undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT +#undef DDRC_DBGCMD_RANK0_REFRESH_MASK +#define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 0x00000000 +#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT 0 +#define DDRC_DBGCMD_RANK0_REFRESH_MASK 0x00000001U + +/* +* Enable quasi-dynamic register programming outside reset. Program registe + * r to 0 to enable quasi-dynamic programming. Set back register to 1 once + * programming is done. +*/ +#undef DDRC_SWCTL_SW_DONE_DEFVAL +#undef DDRC_SWCTL_SW_DONE_SHIFT +#undef DDRC_SWCTL_SW_DONE_MASK +#define DDRC_SWCTL_SW_DONE_DEFVAL +#define DDRC_SWCTL_SW_DONE_SHIFT 0 +#define DDRC_SWCTL_SW_DONE_MASK 0x00000001U + +/* +* Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand + * s every AXI burst into multiple HIF commands, using the memory burst len + * gth as a unit. If set to 1, then XPI will use half of the memory burst l + * ength as a unit. This applies to both reads and writes. When MSTR.data_b + * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i + * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d + * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd + * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali + * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT + * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an + * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST + * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs + * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR + * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared + * -AC is enabled +*/ +#undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL +#undef DDRC_PCCFG_BL_EXP_MODE_SHIFT +#undef DDRC_PCCFG_BL_EXP_MODE_MASK +#define DDRC_PCCFG_BL_EXP_MODE_DEFVAL 0x00000000 +#define DDRC_PCCFG_BL_EXP_MODE_SHIFT 8 +#define DDRC_PCCFG_BL_EXP_MODE_MASK 0x00000100U + +/* +* Page match four limit. If set to 1, limits the number of consecutive sam + * e page DDRC transactions that can be granted by the Port Arbiter to four + * when Page Match feature is enabled. If set to 0, there is no limit impo + * sed on number of consecutive same page DDRC transactions. +*/ +#undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL +#undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT +#undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK +#define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 0x00000000 +#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 4 +#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 0x00000010U + +/* +* If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l + * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw + * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_ + * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a + * t DDRC are driven to 1b'0. +*/ +#undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL +#undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT +#undef DDRC_PCCFG_GO2CRITICAL_EN_MASK +#define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 0x00000000 +#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 0 +#define DDRC_PCCFG_GO2CRITICAL_EN_MASK 0x00000001U + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ +#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the read channel of the port. +*/ +#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ +#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 0x000003FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ +#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the write channel of the port. +*/ +#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ +#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 0x000003FFU + +/* +* Enables port n. +*/ +#undef DDRC_PCTRL_0_PORT_EN_DEFVAL +#undef DDRC_PCTRL_0_PORT_EN_SHIFT +#undef DDRC_PCTRL_0_PORT_EN_MASK +#define DDRC_PCTRL_0_PORT_EN_DEFVAL +#define DDRC_PCTRL_0_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_0_PORT_EN_MASK 0x00000001U + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL +#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT +#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 0x0000000FU + +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ +#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL +#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT +#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U + +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ +#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL +#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT +#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ +#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the read channel of the port. +*/ +#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ +#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 0x000003FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ +#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the write channel of the port. +*/ +#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ +#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 0x000003FFU + +/* +* Enables port n. +*/ +#undef DDRC_PCTRL_1_PORT_EN_DEFVAL +#undef DDRC_PCTRL_1_PORT_EN_SHIFT +#undef DDRC_PCTRL_1_PORT_EN_MASK +#define DDRC_PCTRL_1_PORT_EN_DEFVAL +#define DDRC_PCTRL_1_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_1_PORT_EN_MASK 0x00000001U + +/* +* This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. +*/ +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 24 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 0x03000000U + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL +#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT +#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 8 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 0x00000F00U + +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL +#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT +#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 0x0000000FU + +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ +#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL +#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT +#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U + +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ +#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL +#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT +#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ +#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the read channel of the port. +*/ +#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ +#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 0x000003FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ +#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the write channel of the port. +*/ +#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ +#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 0x000003FFU + +/* +* Enables port n. +*/ +#undef DDRC_PCTRL_2_PORT_EN_DEFVAL +#undef DDRC_PCTRL_2_PORT_EN_SHIFT +#undef DDRC_PCTRL_2_PORT_EN_MASK +#define DDRC_PCTRL_2_PORT_EN_DEFVAL +#define DDRC_PCTRL_2_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_2_PORT_EN_MASK 0x00000001U + +/* +* This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. +*/ +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 24 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 0x03000000U + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL +#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT +#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 8 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 0x00000F00U + +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL +#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT +#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 0x0000000FU + +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ +#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL +#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT +#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U + +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ +#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL +#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT +#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ +#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the read channel of the port. +*/ +#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ +#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 0x000003FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ +#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the write channel of the port. +*/ +#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ +#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 0x000003FFU + +/* +* Enables port n. +*/ +#undef DDRC_PCTRL_3_PORT_EN_DEFVAL +#undef DDRC_PCTRL_3_PORT_EN_SHIFT +#undef DDRC_PCTRL_3_PORT_EN_MASK +#define DDRC_PCTRL_3_PORT_EN_DEFVAL +#define DDRC_PCTRL_3_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_3_PORT_EN_MASK 0x00000001U + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL +#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT +#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 0x0000000FU + +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ +#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL +#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT +#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U + +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ +#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL +#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT +#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 0x0000000FU + +/* +* Specifies the timeout value for write transactions. +*/ +#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL +#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT +#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 0x000007FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ +#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the read channel of the port. +*/ +#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ +#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 0x000003FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ +#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the write channel of the port. +*/ +#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ +#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 0x000003FFU + +/* +* Enables port n. +*/ +#undef DDRC_PCTRL_4_PORT_EN_DEFVAL +#undef DDRC_PCTRL_4_PORT_EN_SHIFT +#undef DDRC_PCTRL_4_PORT_EN_MASK +#define DDRC_PCTRL_4_PORT_EN_DEFVAL +#define DDRC_PCTRL_4_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_4_PORT_EN_MASK 0x00000001U + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL +#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT +#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 0x0000000FU + +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ +#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL +#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT +#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U + +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ +#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL +#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT +#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 0x0000000FU + +/* +* Specifies the timeout value for write transactions. +*/ +#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL +#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT +#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 0x000007FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ +#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the read channel of the port. +*/ +#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ +#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 0x000003FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ +#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the write channel of the port. +*/ +#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ +#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 0x000003FFU + +/* +* Enables port n. +*/ +#undef DDRC_PCTRL_5_PORT_EN_DEFVAL +#undef DDRC_PCTRL_5_PORT_EN_SHIFT +#undef DDRC_PCTRL_5_PORT_EN_MASK +#define DDRC_PCTRL_5_PORT_EN_DEFVAL +#define DDRC_PCTRL_5_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_5_PORT_EN_MASK 0x00000001U + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL +#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT +#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 0x0000000FU + +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ +#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL +#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT +#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U + +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ +#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL +#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT +#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 0x0000000FU + +/* +* Specifies the timeout value for write transactions. +*/ +#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL +#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT +#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 0x000007FFU + +/* +* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). +*/ +#undef DDRC_SARBASE0_BASE_ADDR_DEFVAL +#undef DDRC_SARBASE0_BASE_ADDR_SHIFT +#undef DDRC_SARBASE0_BASE_ADDR_MASK +#define DDRC_SARBASE0_BASE_ADDR_DEFVAL +#define DDRC_SARBASE0_BASE_ADDR_SHIFT 0 +#define DDRC_SARBASE0_BASE_ADDR_MASK 0x000001FFU + +/* +* Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. +*/ +#undef DDRC_SARSIZE0_NBLOCKS_DEFVAL +#undef DDRC_SARSIZE0_NBLOCKS_SHIFT +#undef DDRC_SARSIZE0_NBLOCKS_MASK +#define DDRC_SARSIZE0_NBLOCKS_DEFVAL +#define DDRC_SARSIZE0_NBLOCKS_SHIFT 0 +#define DDRC_SARSIZE0_NBLOCKS_MASK 0x000000FFU + +/* +* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). +*/ +#undef DDRC_SARBASE1_BASE_ADDR_DEFVAL +#undef DDRC_SARBASE1_BASE_ADDR_SHIFT +#undef DDRC_SARBASE1_BASE_ADDR_MASK +#define DDRC_SARBASE1_BASE_ADDR_DEFVAL +#define DDRC_SARBASE1_BASE_ADDR_SHIFT 0 +#define DDRC_SARBASE1_BASE_ADDR_MASK 0x000001FFU + +/* +* Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. +*/ +#undef DDRC_SARSIZE1_NBLOCKS_DEFVAL +#undef DDRC_SARSIZE1_NBLOCKS_SHIFT +#undef DDRC_SARSIZE1_NBLOCKS_MASK +#define DDRC_SARSIZE1_NBLOCKS_DEFVAL +#define DDRC_SARSIZE1_NBLOCKS_SHIFT 0 +#define DDRC_SARSIZE1_NBLOCKS_MASK 0x000000FFU + +/* +* Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. +*/ +#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL +#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT +#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 24 +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 0x1F000000U + +/* +* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. +*/ +#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL +#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT +#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 23 +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 0x00800000U + +/* +* Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks +*/ +#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL +#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT +#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 16 +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 0x003F0000U + +/* +* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. +*/ +#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL +#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT +#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 15 +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 0x00008000U + +/* +* Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks +*/ +#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL +#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT +#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 8 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 0x00003F00U + +/* +* Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. +*/ +#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL +#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT +#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 0 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 0x0000003FU + +/* +* DDR block level reset inside of the DDR Sub System +*/ +#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL +#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT +#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK +#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 +#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U + +/* +* APM block level reset inside of the DDR Sub System +*/ +#undef CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL +#undef CRF_APB_RST_DDR_SS_APM_RESET_SHIFT +#undef CRF_APB_RST_DDR_SS_APM_RESET_MASK +#define CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_APM_RESET_SHIFT 2 +#define CRF_APB_RST_DDR_SS_APM_RESET_MASK 0x00000004U + +/* +* Address Copy +*/ +#undef DDR_PHY_PGCR0_ADCP_DEFVAL +#undef DDR_PHY_PGCR0_ADCP_SHIFT +#undef DDR_PHY_PGCR0_ADCP_MASK +#define DDR_PHY_PGCR0_ADCP_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_ADCP_SHIFT 31 +#define DDR_PHY_PGCR0_ADCP_MASK 0x80000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL +#undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT +#undef DDR_PHY_PGCR0_RESERVED_30_27_MASK +#define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 27 +#define DDR_PHY_PGCR0_RESERVED_30_27_MASK 0x78000000U + +/* +* PHY FIFO Reset +*/ +#undef DDR_PHY_PGCR0_PHYFRST_DEFVAL +#undef DDR_PHY_PGCR0_PHYFRST_SHIFT +#undef DDR_PHY_PGCR0_PHYFRST_MASK +#define DDR_PHY_PGCR0_PHYFRST_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_PHYFRST_SHIFT 26 +#define DDR_PHY_PGCR0_PHYFRST_MASK 0x04000000U + +/* +* Oscillator Mode Address/Command Delay Line Select +*/ +#undef DDR_PHY_PGCR0_OSCACDL_DEFVAL +#undef DDR_PHY_PGCR0_OSCACDL_SHIFT +#undef DDR_PHY_PGCR0_OSCACDL_MASK +#define DDR_PHY_PGCR0_OSCACDL_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCACDL_SHIFT 24 +#define DDR_PHY_PGCR0_OSCACDL_MASK 0x03000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL +#undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT +#undef DDR_PHY_PGCR0_RESERVED_23_19_MASK +#define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 19 +#define DDR_PHY_PGCR0_RESERVED_23_19_MASK 0x00F80000U + +/* +* Digital Test Output Select +*/ +#undef DDR_PHY_PGCR0_DTOSEL_DEFVAL +#undef DDR_PHY_PGCR0_DTOSEL_SHIFT +#undef DDR_PHY_PGCR0_DTOSEL_MASK +#define DDR_PHY_PGCR0_DTOSEL_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_DTOSEL_SHIFT 14 +#define DDR_PHY_PGCR0_DTOSEL_MASK 0x0007C000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL +#undef DDR_PHY_PGCR0_RESERVED_13_SHIFT +#undef DDR_PHY_PGCR0_RESERVED_13_MASK +#define DDR_PHY_PGCR0_RESERVED_13_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_13_SHIFT 13 +#define DDR_PHY_PGCR0_RESERVED_13_MASK 0x00002000U + +/* +* Oscillator Mode Division +*/ +#undef DDR_PHY_PGCR0_OSCDIV_DEFVAL +#undef DDR_PHY_PGCR0_OSCDIV_SHIFT +#undef DDR_PHY_PGCR0_OSCDIV_MASK +#define DDR_PHY_PGCR0_OSCDIV_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCDIV_SHIFT 9 +#define DDR_PHY_PGCR0_OSCDIV_MASK 0x00001E00U + +/* +* Oscillator Enable +*/ +#undef DDR_PHY_PGCR0_OSCEN_DEFVAL +#undef DDR_PHY_PGCR0_OSCEN_SHIFT +#undef DDR_PHY_PGCR0_OSCEN_MASK +#define DDR_PHY_PGCR0_OSCEN_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCEN_SHIFT 8 +#define DDR_PHY_PGCR0_OSCEN_MASK 0x00000100U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL +#undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT +#undef DDR_PHY_PGCR0_RESERVED_7_0_MASK +#define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 0 +#define DDR_PHY_PGCR0_RESERVED_7_0_MASK 0x000000FFU + +/* +* Clear Training Status Registers +*/ +#undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL +#undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT +#undef DDR_PHY_PGCR2_CLRTSTAT_MASK +#define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRTSTAT_SHIFT 31 +#define DDR_PHY_PGCR2_CLRTSTAT_MASK 0x80000000U + +/* +* Clear Impedance Calibration +*/ +#undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL +#undef DDR_PHY_PGCR2_CLRZCAL_SHIFT +#undef DDR_PHY_PGCR2_CLRZCAL_MASK +#define DDR_PHY_PGCR2_CLRZCAL_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRZCAL_SHIFT 30 +#define DDR_PHY_PGCR2_CLRZCAL_MASK 0x40000000U + +/* +* Clear Parity Error +*/ +#undef DDR_PHY_PGCR2_CLRPERR_DEFVAL +#undef DDR_PHY_PGCR2_CLRPERR_SHIFT +#undef DDR_PHY_PGCR2_CLRPERR_MASK +#define DDR_PHY_PGCR2_CLRPERR_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRPERR_SHIFT 29 +#define DDR_PHY_PGCR2_CLRPERR_MASK 0x20000000U + +/* +* Initialization Complete Pin Configuration +*/ +#undef DDR_PHY_PGCR2_ICPC_DEFVAL +#undef DDR_PHY_PGCR2_ICPC_SHIFT +#undef DDR_PHY_PGCR2_ICPC_MASK +#define DDR_PHY_PGCR2_ICPC_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_ICPC_SHIFT 28 +#define DDR_PHY_PGCR2_ICPC_MASK 0x10000000U + +/* +* Data Training PUB Mode Exit Timer +*/ +#undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL +#undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT +#undef DDR_PHY_PGCR2_DTPMXTMR_MASK +#define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_DTPMXTMR_SHIFT 20 +#define DDR_PHY_PGCR2_DTPMXTMR_MASK 0x0FF00000U + +/* +* Initialization Bypass +*/ +#undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL +#undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT +#undef DDR_PHY_PGCR2_INITFSMBYP_MASK +#define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_INITFSMBYP_SHIFT 19 +#define DDR_PHY_PGCR2_INITFSMBYP_MASK 0x00080000U + +/* +* PLL FSM Bypass +*/ +#undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL +#undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT +#undef DDR_PHY_PGCR2_PLLFSMBYP_MASK +#define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 18 +#define DDR_PHY_PGCR2_PLLFSMBYP_MASK 0x00040000U + +/* +* Refresh Period +*/ +#undef DDR_PHY_PGCR2_TREFPRD_DEFVAL +#undef DDR_PHY_PGCR2_TREFPRD_SHIFT +#undef DDR_PHY_PGCR2_TREFPRD_MASK +#define DDR_PHY_PGCR2_TREFPRD_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_TREFPRD_SHIFT 0 +#define DDR_PHY_PGCR2_TREFPRD_MASK 0x0003FFFFU + +/* +* CKN Enable +*/ +#undef DDR_PHY_PGCR3_CKNEN_DEFVAL +#undef DDR_PHY_PGCR3_CKNEN_SHIFT +#undef DDR_PHY_PGCR3_CKNEN_MASK +#define DDR_PHY_PGCR3_CKNEN_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CKNEN_SHIFT 24 +#define DDR_PHY_PGCR3_CKNEN_MASK 0xFF000000U + +/* +* CK Enable +*/ +#undef DDR_PHY_PGCR3_CKEN_DEFVAL +#undef DDR_PHY_PGCR3_CKEN_SHIFT +#undef DDR_PHY_PGCR3_CKEN_MASK +#define DDR_PHY_PGCR3_CKEN_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CKEN_SHIFT 16 +#define DDR_PHY_PGCR3_CKEN_MASK 0x00FF0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL +#undef DDR_PHY_PGCR3_RESERVED_15_SHIFT +#undef DDR_PHY_PGCR3_RESERVED_15_MASK +#define DDR_PHY_PGCR3_RESERVED_15_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RESERVED_15_SHIFT 15 +#define DDR_PHY_PGCR3_RESERVED_15_MASK 0x00008000U + +/* +* Enable Clock Gating for AC [0] ctl_rd_clk +*/ +#undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL +#undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT +#undef DDR_PHY_PGCR3_GATEACRDCLK_MASK +#define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 13 +#define DDR_PHY_PGCR3_GATEACRDCLK_MASK 0x00006000U + +/* +* Enable Clock Gating for AC [0] ddr_clk +*/ +#undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL +#undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT +#undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK +#define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 11 +#define DDR_PHY_PGCR3_GATEACDDRCLK_MASK 0x00001800U + +/* +* Enable Clock Gating for AC [0] ctl_clk +*/ +#undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL +#undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT +#undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK +#define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 9 +#define DDR_PHY_PGCR3_GATEACCTLCLK_MASK 0x00000600U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL +#undef DDR_PHY_PGCR3_RESERVED_8_SHIFT +#undef DDR_PHY_PGCR3_RESERVED_8_MASK +#define DDR_PHY_PGCR3_RESERVED_8_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RESERVED_8_SHIFT 8 +#define DDR_PHY_PGCR3_RESERVED_8_MASK 0x00000100U + +/* +* Controls DDL Bypass Modes +*/ +#undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL +#undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT +#undef DDR_PHY_PGCR3_DDLBYPMODE_MASK +#define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6 +#define DDR_PHY_PGCR3_DDLBYPMODE_MASK 0x000000C0U + +/* +* IO Loop-Back Select +*/ +#undef DDR_PHY_PGCR3_IOLB_DEFVAL +#undef DDR_PHY_PGCR3_IOLB_SHIFT +#undef DDR_PHY_PGCR3_IOLB_MASK +#define DDR_PHY_PGCR3_IOLB_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_IOLB_SHIFT 5 +#define DDR_PHY_PGCR3_IOLB_MASK 0x00000020U + +/* +* AC Receive FIFO Read Mode +*/ +#undef DDR_PHY_PGCR3_RDMODE_DEFVAL +#undef DDR_PHY_PGCR3_RDMODE_SHIFT +#undef DDR_PHY_PGCR3_RDMODE_MASK +#define DDR_PHY_PGCR3_RDMODE_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RDMODE_SHIFT 3 +#define DDR_PHY_PGCR3_RDMODE_MASK 0x00000018U + +/* +* Read FIFO Reset Disable +*/ +#undef DDR_PHY_PGCR3_DISRST_DEFVAL +#undef DDR_PHY_PGCR3_DISRST_SHIFT +#undef DDR_PHY_PGCR3_DISRST_MASK +#define DDR_PHY_PGCR3_DISRST_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_DISRST_SHIFT 2 +#define DDR_PHY_PGCR3_DISRST_MASK 0x00000004U + +/* +* Clock Level when Clock Gating +*/ +#undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL +#undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT +#undef DDR_PHY_PGCR3_CLKLEVEL_MASK +#define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CLKLEVEL_SHIFT 0 +#define DDR_PHY_PGCR3_CLKLEVEL_MASK 0x00000003U + +/* +* Frequency B Ratio Term +*/ +#undef DDR_PHY_PGCR5_FRQBT_DEFVAL +#undef DDR_PHY_PGCR5_FRQBT_SHIFT +#undef DDR_PHY_PGCR5_FRQBT_MASK +#define DDR_PHY_PGCR5_FRQBT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_FRQBT_SHIFT 24 +#define DDR_PHY_PGCR5_FRQBT_MASK 0xFF000000U + +/* +* Frequency A Ratio Term +*/ +#undef DDR_PHY_PGCR5_FRQAT_DEFVAL +#undef DDR_PHY_PGCR5_FRQAT_SHIFT +#undef DDR_PHY_PGCR5_FRQAT_MASK +#define DDR_PHY_PGCR5_FRQAT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_FRQAT_SHIFT 16 +#define DDR_PHY_PGCR5_FRQAT_MASK 0x00FF0000U + +/* +* DFI Disconnect Time Period +*/ +#undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL +#undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT +#undef DDR_PHY_PGCR5_DISCNPERIOD_MASK +#define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 8 +#define DDR_PHY_PGCR5_DISCNPERIOD_MASK 0x0000FF00U + +/* +* Receiver bias core side control +*/ +#undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL +#undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT +#undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK +#define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 4 +#define DDR_PHY_PGCR5_VREF_RBCTRL_MASK 0x000000F0U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL +#undef DDR_PHY_PGCR5_RESERVED_3_SHIFT +#undef DDR_PHY_PGCR5_RESERVED_3_MASK +#define DDR_PHY_PGCR5_RESERVED_3_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_RESERVED_3_SHIFT 3 +#define DDR_PHY_PGCR5_RESERVED_3_MASK 0x00000008U + +/* +* Internal VREF generator REFSEL ragne select +*/ +#undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL +#undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT +#undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK +#define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 2 +#define DDR_PHY_PGCR5_DXREFISELRANGE_MASK 0x00000004U + +/* +* DDL Page Read Write select +*/ +#undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL +#undef DDR_PHY_PGCR5_DDLPGACT_SHIFT +#undef DDR_PHY_PGCR5_DDLPGACT_MASK +#define DDR_PHY_PGCR5_DDLPGACT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DDLPGACT_SHIFT 1 +#define DDR_PHY_PGCR5_DDLPGACT_MASK 0x00000002U + +/* +* DDL Page Read Write select +*/ +#undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL +#undef DDR_PHY_PGCR5_DDLPGRW_SHIFT +#undef DDR_PHY_PGCR5_DDLPGRW_MASK +#define DDR_PHY_PGCR5_DDLPGRW_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DDLPGRW_SHIFT 0 +#define DDR_PHY_PGCR5_DDLPGRW_MASK 0x00000001U + +/* +* PLL Power-Down Time +*/ +#undef DDR_PHY_PTR0_TPLLPD_DEFVAL +#undef DDR_PHY_PTR0_TPLLPD_SHIFT +#undef DDR_PHY_PTR0_TPLLPD_MASK +#define DDR_PHY_PTR0_TPLLPD_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPLLPD_SHIFT 21 +#define DDR_PHY_PTR0_TPLLPD_MASK 0xFFE00000U + +/* +* PLL Gear Shift Time +*/ +#undef DDR_PHY_PTR0_TPLLGS_DEFVAL +#undef DDR_PHY_PTR0_TPLLGS_SHIFT +#undef DDR_PHY_PTR0_TPLLGS_MASK +#define DDR_PHY_PTR0_TPLLGS_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPLLGS_SHIFT 6 +#define DDR_PHY_PTR0_TPLLGS_MASK 0x001FFFC0U + +/* +* PHY Reset Time +*/ +#undef DDR_PHY_PTR0_TPHYRST_DEFVAL +#undef DDR_PHY_PTR0_TPHYRST_SHIFT +#undef DDR_PHY_PTR0_TPHYRST_MASK +#define DDR_PHY_PTR0_TPHYRST_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPHYRST_SHIFT 0 +#define DDR_PHY_PTR0_TPHYRST_MASK 0x0000003FU + +/* +* PLL Lock Time +*/ +#undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL +#undef DDR_PHY_PTR1_TPLLLOCK_SHIFT +#undef DDR_PHY_PTR1_TPLLLOCK_MASK +#define DDR_PHY_PTR1_TPLLLOCK_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_TPLLLOCK_SHIFT 16 +#define DDR_PHY_PTR1_TPLLLOCK_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL +#undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT +#undef DDR_PHY_PTR1_RESERVED_15_13_MASK +#define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_RESERVED_15_13_SHIFT 13 +#define DDR_PHY_PTR1_RESERVED_15_13_MASK 0x0000E000U + +/* +* PLL Reset Time +*/ +#undef DDR_PHY_PTR1_TPLLRST_DEFVAL +#undef DDR_PHY_PTR1_TPLLRST_SHIFT +#undef DDR_PHY_PTR1_TPLLRST_MASK +#define DDR_PHY_PTR1_TPLLRST_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_TPLLRST_SHIFT 0 +#define DDR_PHY_PTR1_TPLLRST_MASK 0x00001FFFU + +/* +* PLL Bypass +*/ +#undef DDR_PHY_PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_PLLCR0_PLLBYP_MASK +#define DDR_PHY_PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_PLLCR0_PLLRST_MASK +#define DDR_PHY_PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_PLLCR0_PLLPD_MASK +#define DDR_PHY_PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_PLLCR0_RSTOPM_MASK +#define DDR_PHY_PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_PLLCR0_FRQSEL_MASK +#define DDR_PHY_PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_PLLCR0_RLOCKM_MASK +#define DDR_PHY_PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_PLLCR0_CPPC_SHIFT +#undef DDR_PHY_PLLCR0_CPPC_MASK +#define DDR_PHY_PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_PLLCR0_CPIC_SHIFT +#undef DDR_PHY_PLLCR0_CPIC_MASK +#define DDR_PHY_PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_PLLCR0_GSHIFT_MASK +#define DDR_PHY_PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable +*/ +#undef DDR_PHY_PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_PLLCR0_ATOEN_MASK +#define DDR_PHY_PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_PLLCR0_ATC_DEFVAL +#undef DDR_PHY_PLLCR0_ATC_SHIFT +#undef DDR_PHY_PLLCR0_ATC_MASK +#define DDR_PHY_PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_PLLCR0_DTC_DEFVAL +#undef DDR_PHY_PLLCR0_DTC_SHIFT +#undef DDR_PHY_PLLCR0_DTC_MASK +#define DDR_PHY_PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL +#undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT +#undef DDR_PHY_DSGCR_RESERVED_31_28_MASK +#define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 28 +#define DDR_PHY_DSGCR_RESERVED_31_28_MASK 0xF0000000U + +/* +* When RDBI enabled, this bit is used to select RDBI CL calculation, if it + * is 1b1, calculation will use RDBICL, otherwise use default calculation. +*/ +#undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL +#undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT +#undef DDR_PHY_DSGCR_RDBICLSEL_MASK +#define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RDBICLSEL_SHIFT 27 +#define DDR_PHY_DSGCR_RDBICLSEL_MASK 0x08000000U + +/* +* When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v + * alue. +*/ +#undef DDR_PHY_DSGCR_RDBICL_DEFVAL +#undef DDR_PHY_DSGCR_RDBICL_SHIFT +#undef DDR_PHY_DSGCR_RDBICL_MASK +#define DDR_PHY_DSGCR_RDBICL_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RDBICL_SHIFT 24 +#define DDR_PHY_DSGCR_RDBICL_MASK 0x07000000U + +/* +* PHY Impedance Update Enable +*/ +#undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL +#undef DDR_PHY_DSGCR_PHYZUEN_SHIFT +#undef DDR_PHY_DSGCR_PHYZUEN_MASK +#define DDR_PHY_DSGCR_PHYZUEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PHYZUEN_SHIFT 23 +#define DDR_PHY_DSGCR_PHYZUEN_MASK 0x00800000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL +#undef DDR_PHY_DSGCR_RESERVED_22_SHIFT +#undef DDR_PHY_DSGCR_RESERVED_22_MASK +#define DDR_PHY_DSGCR_RESERVED_22_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_22_SHIFT 22 +#define DDR_PHY_DSGCR_RESERVED_22_MASK 0x00400000U + +/* +* SDRAM Reset Output Enable +*/ +#undef DDR_PHY_DSGCR_RSTOE_DEFVAL +#undef DDR_PHY_DSGCR_RSTOE_SHIFT +#undef DDR_PHY_DSGCR_RSTOE_MASK +#define DDR_PHY_DSGCR_RSTOE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RSTOE_SHIFT 21 +#define DDR_PHY_DSGCR_RSTOE_MASK 0x00200000U + +/* +* Single Data Rate Mode +*/ +#undef DDR_PHY_DSGCR_SDRMODE_DEFVAL +#undef DDR_PHY_DSGCR_SDRMODE_SHIFT +#undef DDR_PHY_DSGCR_SDRMODE_MASK +#define DDR_PHY_DSGCR_SDRMODE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_SDRMODE_SHIFT 19 +#define DDR_PHY_DSGCR_SDRMODE_MASK 0x00180000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL +#undef DDR_PHY_DSGCR_RESERVED_18_SHIFT +#undef DDR_PHY_DSGCR_RESERVED_18_MASK +#define DDR_PHY_DSGCR_RESERVED_18_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_18_SHIFT 18 +#define DDR_PHY_DSGCR_RESERVED_18_MASK 0x00040000U + +/* +* ATO Analog Test Enable +*/ +#undef DDR_PHY_DSGCR_ATOAE_DEFVAL +#undef DDR_PHY_DSGCR_ATOAE_SHIFT +#undef DDR_PHY_DSGCR_ATOAE_MASK +#define DDR_PHY_DSGCR_ATOAE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_ATOAE_SHIFT 17 +#define DDR_PHY_DSGCR_ATOAE_MASK 0x00020000U + +/* +* DTO Output Enable +*/ +#undef DDR_PHY_DSGCR_DTOOE_DEFVAL +#undef DDR_PHY_DSGCR_DTOOE_SHIFT +#undef DDR_PHY_DSGCR_DTOOE_MASK +#define DDR_PHY_DSGCR_DTOOE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOOE_SHIFT 16 +#define DDR_PHY_DSGCR_DTOOE_MASK 0x00010000U + +/* +* DTO I/O Mode +*/ +#undef DDR_PHY_DSGCR_DTOIOM_DEFVAL +#undef DDR_PHY_DSGCR_DTOIOM_SHIFT +#undef DDR_PHY_DSGCR_DTOIOM_MASK +#define DDR_PHY_DSGCR_DTOIOM_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOIOM_SHIFT 15 +#define DDR_PHY_DSGCR_DTOIOM_MASK 0x00008000U + +/* +* DTO Power Down Receiver +*/ +#undef DDR_PHY_DSGCR_DTOPDR_DEFVAL +#undef DDR_PHY_DSGCR_DTOPDR_SHIFT +#undef DDR_PHY_DSGCR_DTOPDR_MASK +#define DDR_PHY_DSGCR_DTOPDR_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOPDR_SHIFT 14 +#define DDR_PHY_DSGCR_DTOPDR_MASK 0x00004000U + +/* +* Reserved. Return zeroes on reads +*/ +#undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL +#undef DDR_PHY_DSGCR_RESERVED_13_SHIFT +#undef DDR_PHY_DSGCR_RESERVED_13_MASK +#define DDR_PHY_DSGCR_RESERVED_13_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_13_SHIFT 13 +#define DDR_PHY_DSGCR_RESERVED_13_MASK 0x00002000U + +/* +* DTO On-Die Termination +*/ +#undef DDR_PHY_DSGCR_DTOODT_DEFVAL +#undef DDR_PHY_DSGCR_DTOODT_SHIFT +#undef DDR_PHY_DSGCR_DTOODT_MASK +#define DDR_PHY_DSGCR_DTOODT_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOODT_SHIFT 12 +#define DDR_PHY_DSGCR_DTOODT_MASK 0x00001000U + +/* +* PHY Update Acknowledge Delay +*/ +#undef DDR_PHY_DSGCR_PUAD_DEFVAL +#undef DDR_PHY_DSGCR_PUAD_SHIFT +#undef DDR_PHY_DSGCR_PUAD_MASK +#define DDR_PHY_DSGCR_PUAD_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PUAD_SHIFT 6 +#define DDR_PHY_DSGCR_PUAD_MASK 0x00000FC0U + +/* +* Controller Update Acknowledge Enable +*/ +#undef DDR_PHY_DSGCR_CUAEN_DEFVAL +#undef DDR_PHY_DSGCR_CUAEN_SHIFT +#undef DDR_PHY_DSGCR_CUAEN_MASK +#define DDR_PHY_DSGCR_CUAEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_CUAEN_SHIFT 5 +#define DDR_PHY_DSGCR_CUAEN_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads +*/ +#undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL +#undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT +#undef DDR_PHY_DSGCR_RESERVED_4_3_MASK +#define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 3 +#define DDR_PHY_DSGCR_RESERVED_4_3_MASK 0x00000018U + +/* +* Controller Impedance Update Enable +*/ +#undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL +#undef DDR_PHY_DSGCR_CTLZUEN_SHIFT +#undef DDR_PHY_DSGCR_CTLZUEN_MASK +#define DDR_PHY_DSGCR_CTLZUEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_CTLZUEN_SHIFT 2 +#define DDR_PHY_DSGCR_CTLZUEN_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads +*/ +#undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL +#undef DDR_PHY_DSGCR_RESERVED_1_SHIFT +#undef DDR_PHY_DSGCR_RESERVED_1_MASK +#define DDR_PHY_DSGCR_RESERVED_1_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_1_SHIFT 1 +#define DDR_PHY_DSGCR_RESERVED_1_MASK 0x00000002U + +/* +* PHY Update Request Enable +*/ +#undef DDR_PHY_DSGCR_PUREN_DEFVAL +#undef DDR_PHY_DSGCR_PUREN_SHIFT +#undef DDR_PHY_DSGCR_PUREN_MASK +#define DDR_PHY_DSGCR_PUREN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PUREN_SHIFT 0 +#define DDR_PHY_DSGCR_PUREN_MASK 0x00000001U + +/* +* General Purpose Register 0 +*/ +#undef DDR_PHY_GPR0_GPR0_DEFVAL +#undef DDR_PHY_GPR0_GPR0_SHIFT +#undef DDR_PHY_GPR0_GPR0_MASK +#define DDR_PHY_GPR0_GPR0_DEFVAL +#define DDR_PHY_GPR0_GPR0_SHIFT 0 +#define DDR_PHY_GPR0_GPR0_MASK 0xFFFFFFFFU + +/* +* General Purpose Register 1 +*/ +#undef DDR_PHY_GPR1_GPR1_DEFVAL +#undef DDR_PHY_GPR1_GPR1_SHIFT +#undef DDR_PHY_GPR1_GPR1_MASK +#define DDR_PHY_GPR1_GPR1_DEFVAL +#define DDR_PHY_GPR1_GPR1_SHIFT 0 +#define DDR_PHY_GPR1_GPR1_MASK 0xFFFFFFFFU + +/* +* DDR4 Gear Down Timing. +*/ +#undef DDR_PHY_DCR_GEARDN_DEFVAL +#undef DDR_PHY_DCR_GEARDN_SHIFT +#undef DDR_PHY_DCR_GEARDN_MASK +#define DDR_PHY_DCR_GEARDN_DEFVAL 0x0000040D +#define DDR_PHY_DCR_GEARDN_SHIFT 31 +#define DDR_PHY_DCR_GEARDN_MASK 0x80000000U + +/* +* Un-used Bank Group +*/ +#undef DDR_PHY_DCR_UBG_DEFVAL +#undef DDR_PHY_DCR_UBG_SHIFT +#undef DDR_PHY_DCR_UBG_MASK +#define DDR_PHY_DCR_UBG_DEFVAL 0x0000040D +#define DDR_PHY_DCR_UBG_SHIFT 30 +#define DDR_PHY_DCR_UBG_MASK 0x40000000U + +/* +* Un-buffered DIMM Address Mirroring +*/ +#undef DDR_PHY_DCR_UDIMM_DEFVAL +#undef DDR_PHY_DCR_UDIMM_SHIFT +#undef DDR_PHY_DCR_UDIMM_MASK +#define DDR_PHY_DCR_UDIMM_DEFVAL 0x0000040D +#define DDR_PHY_DCR_UDIMM_SHIFT 29 +#define DDR_PHY_DCR_UDIMM_MASK 0x20000000U + +/* +* DDR 2T Timing +*/ +#undef DDR_PHY_DCR_DDR2T_DEFVAL +#undef DDR_PHY_DCR_DDR2T_SHIFT +#undef DDR_PHY_DCR_DDR2T_MASK +#define DDR_PHY_DCR_DDR2T_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDR2T_SHIFT 28 +#define DDR_PHY_DCR_DDR2T_MASK 0x10000000U + +/* +* No Simultaneous Rank Access +*/ +#undef DDR_PHY_DCR_NOSRA_DEFVAL +#undef DDR_PHY_DCR_NOSRA_SHIFT +#undef DDR_PHY_DCR_NOSRA_MASK +#define DDR_PHY_DCR_NOSRA_DEFVAL 0x0000040D +#define DDR_PHY_DCR_NOSRA_SHIFT 27 +#define DDR_PHY_DCR_NOSRA_MASK 0x08000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL +#undef DDR_PHY_DCR_RESERVED_26_18_SHIFT +#undef DDR_PHY_DCR_RESERVED_26_18_MASK +#define DDR_PHY_DCR_RESERVED_26_18_DEFVAL 0x0000040D +#define DDR_PHY_DCR_RESERVED_26_18_SHIFT 18 +#define DDR_PHY_DCR_RESERVED_26_18_MASK 0x07FC0000U + +/* +* Byte Mask +*/ +#undef DDR_PHY_DCR_BYTEMASK_DEFVAL +#undef DDR_PHY_DCR_BYTEMASK_SHIFT +#undef DDR_PHY_DCR_BYTEMASK_MASK +#define DDR_PHY_DCR_BYTEMASK_DEFVAL 0x0000040D +#define DDR_PHY_DCR_BYTEMASK_SHIFT 10 +#define DDR_PHY_DCR_BYTEMASK_MASK 0x0003FC00U + +/* +* DDR Type +*/ +#undef DDR_PHY_DCR_DDRTYPE_DEFVAL +#undef DDR_PHY_DCR_DDRTYPE_SHIFT +#undef DDR_PHY_DCR_DDRTYPE_MASK +#define DDR_PHY_DCR_DDRTYPE_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDRTYPE_SHIFT 8 +#define DDR_PHY_DCR_DDRTYPE_MASK 0x00000300U + +/* +* Multi-Purpose Register (MPR) DQ (DDR3 Only) +*/ +#undef DDR_PHY_DCR_MPRDQ_DEFVAL +#undef DDR_PHY_DCR_MPRDQ_SHIFT +#undef DDR_PHY_DCR_MPRDQ_MASK +#define DDR_PHY_DCR_MPRDQ_DEFVAL 0x0000040D +#define DDR_PHY_DCR_MPRDQ_SHIFT 7 +#define DDR_PHY_DCR_MPRDQ_MASK 0x00000080U + +/* +* Primary DQ (DDR3 Only) +*/ +#undef DDR_PHY_DCR_PDQ_DEFVAL +#undef DDR_PHY_DCR_PDQ_SHIFT +#undef DDR_PHY_DCR_PDQ_MASK +#define DDR_PHY_DCR_PDQ_DEFVAL 0x0000040D +#define DDR_PHY_DCR_PDQ_SHIFT 4 +#define DDR_PHY_DCR_PDQ_MASK 0x00000070U + +/* +* DDR 8-Bank +*/ +#undef DDR_PHY_DCR_DDR8BNK_DEFVAL +#undef DDR_PHY_DCR_DDR8BNK_SHIFT +#undef DDR_PHY_DCR_DDR8BNK_MASK +#define DDR_PHY_DCR_DDR8BNK_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDR8BNK_SHIFT 3 +#define DDR_PHY_DCR_DDR8BNK_MASK 0x00000008U + +/* +* DDR Mode +*/ +#undef DDR_PHY_DCR_DDRMD_DEFVAL +#undef DDR_PHY_DCR_DDRMD_SHIFT +#undef DDR_PHY_DCR_DDRMD_MASK +#define DDR_PHY_DCR_DDRMD_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDRMD_SHIFT 0 +#define DDR_PHY_DCR_DDRMD_MASK 0x00000007U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT +#undef DDR_PHY_DTPR0_RESERVED_31_29_MASK +#define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DTPR0_RESERVED_31_29_MASK 0xE0000000U + +/* +* Activate to activate command delay (different banks) +*/ +#undef DDR_PHY_DTPR0_TRRD_DEFVAL +#undef DDR_PHY_DTPR0_TRRD_SHIFT +#undef DDR_PHY_DTPR0_TRRD_MASK +#define DDR_PHY_DTPR0_TRRD_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRRD_SHIFT 24 +#define DDR_PHY_DTPR0_TRRD_MASK 0x1F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL +#undef DDR_PHY_DTPR0_RESERVED_23_SHIFT +#undef DDR_PHY_DTPR0_RESERVED_23_MASK +#define DDR_PHY_DTPR0_RESERVED_23_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_23_SHIFT 23 +#define DDR_PHY_DTPR0_RESERVED_23_MASK 0x00800000U + +/* +* Activate to precharge command delay +*/ +#undef DDR_PHY_DTPR0_TRAS_DEFVAL +#undef DDR_PHY_DTPR0_TRAS_SHIFT +#undef DDR_PHY_DTPR0_TRAS_MASK +#define DDR_PHY_DTPR0_TRAS_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRAS_SHIFT 16 +#define DDR_PHY_DTPR0_TRAS_MASK 0x007F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL +#undef DDR_PHY_DTPR0_RESERVED_15_SHIFT +#undef DDR_PHY_DTPR0_RESERVED_15_MASK +#define DDR_PHY_DTPR0_RESERVED_15_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_15_SHIFT 15 +#define DDR_PHY_DTPR0_RESERVED_15_MASK 0x00008000U + +/* +* Precharge command period +*/ +#undef DDR_PHY_DTPR0_TRP_DEFVAL +#undef DDR_PHY_DTPR0_TRP_SHIFT +#undef DDR_PHY_DTPR0_TRP_MASK +#define DDR_PHY_DTPR0_TRP_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRP_SHIFT 8 +#define DDR_PHY_DTPR0_TRP_MASK 0x00007F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL +#undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT +#undef DDR_PHY_DTPR0_RESERVED_7_5_MASK +#define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR0_RESERVED_7_5_MASK 0x000000E0U + +/* +* Internal read to precharge command delay +*/ +#undef DDR_PHY_DTPR0_TRTP_DEFVAL +#undef DDR_PHY_DTPR0_TRTP_SHIFT +#undef DDR_PHY_DTPR0_TRTP_MASK +#define DDR_PHY_DTPR0_TRTP_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRTP_SHIFT 0 +#define DDR_PHY_DTPR0_TRTP_MASK 0x0000001FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL +#undef DDR_PHY_DTPR1_RESERVED_31_SHIFT +#undef DDR_PHY_DTPR1_RESERVED_31_MASK +#define DDR_PHY_DTPR1_RESERVED_31_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_31_SHIFT 31 +#define DDR_PHY_DTPR1_RESERVED_31_MASK 0x80000000U + +/* +* Minimum delay from when write leveling mode is programmed to the first D + * QS/DQS# rising edge. +*/ +#undef DDR_PHY_DTPR1_TWLMRD_DEFVAL +#undef DDR_PHY_DTPR1_TWLMRD_SHIFT +#undef DDR_PHY_DTPR1_TWLMRD_MASK +#define DDR_PHY_DTPR1_TWLMRD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TWLMRD_SHIFT 24 +#define DDR_PHY_DTPR1_TWLMRD_MASK 0x7F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL +#undef DDR_PHY_DTPR1_RESERVED_23_SHIFT +#undef DDR_PHY_DTPR1_RESERVED_23_MASK +#define DDR_PHY_DTPR1_RESERVED_23_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_23_SHIFT 23 +#define DDR_PHY_DTPR1_RESERVED_23_MASK 0x00800000U + +/* +* 4-bank activate period +*/ +#undef DDR_PHY_DTPR1_TFAW_DEFVAL +#undef DDR_PHY_DTPR1_TFAW_SHIFT +#undef DDR_PHY_DTPR1_TFAW_MASK +#define DDR_PHY_DTPR1_TFAW_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TFAW_SHIFT 16 +#define DDR_PHY_DTPR1_TFAW_MASK 0x007F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL +#undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT +#undef DDR_PHY_DTPR1_RESERVED_15_11_MASK +#define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 11 +#define DDR_PHY_DTPR1_RESERVED_15_11_MASK 0x0000F800U + +/* +* Load mode update delay (DDR4 and DDR3 only) +*/ +#undef DDR_PHY_DTPR1_TMOD_DEFVAL +#undef DDR_PHY_DTPR1_TMOD_SHIFT +#undef DDR_PHY_DTPR1_TMOD_MASK +#define DDR_PHY_DTPR1_TMOD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TMOD_SHIFT 8 +#define DDR_PHY_DTPR1_TMOD_MASK 0x00000700U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL +#undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT +#undef DDR_PHY_DTPR1_RESERVED_7_5_MASK +#define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR1_RESERVED_7_5_MASK 0x000000E0U + +/* +* Load mode cycle time +*/ +#undef DDR_PHY_DTPR1_TMRD_DEFVAL +#undef DDR_PHY_DTPR1_TMRD_SHIFT +#undef DDR_PHY_DTPR1_TMRD_MASK +#define DDR_PHY_DTPR1_TMRD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TMRD_SHIFT 0 +#define DDR_PHY_DTPR1_TMRD_MASK 0x0000001FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT +#undef DDR_PHY_DTPR2_RESERVED_31_29_MASK +#define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DTPR2_RESERVED_31_29_MASK 0xE0000000U + +/* +* Read to Write command delay. Valid values are +*/ +#undef DDR_PHY_DTPR2_TRTW_DEFVAL +#undef DDR_PHY_DTPR2_TRTW_SHIFT +#undef DDR_PHY_DTPR2_TRTW_MASK +#define DDR_PHY_DTPR2_TRTW_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TRTW_SHIFT 28 +#define DDR_PHY_DTPR2_TRTW_MASK 0x10000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL +#undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT +#undef DDR_PHY_DTPR2_RESERVED_27_25_MASK +#define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 25 +#define DDR_PHY_DTPR2_RESERVED_27_25_MASK 0x0E000000U + +/* +* Read to ODT delay (DDR3 only) +*/ +#undef DDR_PHY_DTPR2_TRTODT_DEFVAL +#undef DDR_PHY_DTPR2_TRTODT_SHIFT +#undef DDR_PHY_DTPR2_TRTODT_MASK +#define DDR_PHY_DTPR2_TRTODT_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TRTODT_SHIFT 24 +#define DDR_PHY_DTPR2_TRTODT_MASK 0x01000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL +#undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT +#undef DDR_PHY_DTPR2_RESERVED_23_20_MASK +#define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 20 +#define DDR_PHY_DTPR2_RESERVED_23_20_MASK 0x00F00000U + +/* +* CKE minimum pulse width +*/ +#undef DDR_PHY_DTPR2_TCKE_DEFVAL +#undef DDR_PHY_DTPR2_TCKE_SHIFT +#undef DDR_PHY_DTPR2_TCKE_MASK +#define DDR_PHY_DTPR2_TCKE_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TCKE_SHIFT 16 +#define DDR_PHY_DTPR2_TCKE_MASK 0x000F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL +#undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT +#undef DDR_PHY_DTPR2_RESERVED_15_10_MASK +#define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_DTPR2_RESERVED_15_10_MASK 0x0000FC00U + +/* +* Self refresh exit delay +*/ +#undef DDR_PHY_DTPR2_TXS_DEFVAL +#undef DDR_PHY_DTPR2_TXS_SHIFT +#undef DDR_PHY_DTPR2_TXS_MASK +#define DDR_PHY_DTPR2_TXS_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TXS_SHIFT 0 +#define DDR_PHY_DTPR2_TXS_MASK 0x000003FFU + +/* +* ODT turn-off delay extension +*/ +#undef DDR_PHY_DTPR3_TOFDX_DEFVAL +#undef DDR_PHY_DTPR3_TOFDX_SHIFT +#undef DDR_PHY_DTPR3_TOFDX_MASK +#define DDR_PHY_DTPR3_TOFDX_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TOFDX_SHIFT 29 +#define DDR_PHY_DTPR3_TOFDX_MASK 0xE0000000U + +/* +* Read to read and write to write command delay +*/ +#undef DDR_PHY_DTPR3_TCCD_DEFVAL +#undef DDR_PHY_DTPR3_TCCD_SHIFT +#undef DDR_PHY_DTPR3_TCCD_MASK +#define DDR_PHY_DTPR3_TCCD_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TCCD_SHIFT 26 +#define DDR_PHY_DTPR3_TCCD_MASK 0x1C000000U + +/* +* DLL locking time +*/ +#undef DDR_PHY_DTPR3_TDLLK_DEFVAL +#undef DDR_PHY_DTPR3_TDLLK_SHIFT +#undef DDR_PHY_DTPR3_TDLLK_MASK +#define DDR_PHY_DTPR3_TDLLK_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDLLK_SHIFT 16 +#define DDR_PHY_DTPR3_TDLLK_MASK 0x03FF0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL +#undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT +#undef DDR_PHY_DTPR3_RESERVED_15_12_MASK +#define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 12 +#define DDR_PHY_DTPR3_RESERVED_15_12_MASK 0x0000F000U + +/* +* Maximum DQS output access time from CK/CK# (LPDDR2/3 only) +*/ +#undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL +#undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT +#undef DDR_PHY_DTPR3_TDQSCKMAX_MASK +#define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 8 +#define DDR_PHY_DTPR3_TDQSCKMAX_MASK 0x00000F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL +#undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT +#undef DDR_PHY_DTPR3_RESERVED_7_3_MASK +#define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 3 +#define DDR_PHY_DTPR3_RESERVED_7_3_MASK 0x000000F8U + +/* +* DQS output access time from CK/CK# (LPDDR2/3 only) +*/ +#undef DDR_PHY_DTPR3_TDQSCK_DEFVAL +#undef DDR_PHY_DTPR3_TDQSCK_SHIFT +#undef DDR_PHY_DTPR3_TDQSCK_MASK +#define DDR_PHY_DTPR3_TDQSCK_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDQSCK_SHIFT 0 +#define DDR_PHY_DTPR3_TDQSCK_MASK 0x00000007U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT +#undef DDR_PHY_DTPR4_RESERVED_31_30_MASK +#define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DTPR4_RESERVED_31_30_MASK 0xC0000000U + +/* +* ODT turn-on/turn-off delays (DDR2 only) +*/ +#undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL +#undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT +#undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK +#define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 28 +#define DDR_PHY_DTPR4_TAOND_TAOFD_MASK 0x30000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL +#undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT +#undef DDR_PHY_DTPR4_RESERVED_27_26_MASK +#define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 26 +#define DDR_PHY_DTPR4_RESERVED_27_26_MASK 0x0C000000U + +/* +* Refresh-to-Refresh +*/ +#undef DDR_PHY_DTPR4_TRFC_DEFVAL +#undef DDR_PHY_DTPR4_TRFC_SHIFT +#undef DDR_PHY_DTPR4_TRFC_MASK +#define DDR_PHY_DTPR4_TRFC_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TRFC_SHIFT 16 +#define DDR_PHY_DTPR4_TRFC_MASK 0x03FF0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT +#undef DDR_PHY_DTPR4_RESERVED_15_14_MASK +#define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DTPR4_RESERVED_15_14_MASK 0x0000C000U + +/* +* Write leveling output delay +*/ +#undef DDR_PHY_DTPR4_TWLO_DEFVAL +#undef DDR_PHY_DTPR4_TWLO_SHIFT +#undef DDR_PHY_DTPR4_TWLO_MASK +#define DDR_PHY_DTPR4_TWLO_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TWLO_SHIFT 8 +#define DDR_PHY_DTPR4_TWLO_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL +#undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT +#undef DDR_PHY_DTPR4_RESERVED_7_5_MASK +#define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR4_RESERVED_7_5_MASK 0x000000E0U + +/* +* Power down exit delay +*/ +#undef DDR_PHY_DTPR4_TXP_DEFVAL +#undef DDR_PHY_DTPR4_TXP_SHIFT +#undef DDR_PHY_DTPR4_TXP_MASK +#define DDR_PHY_DTPR4_TXP_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TXP_SHIFT 0 +#define DDR_PHY_DTPR4_TXP_MASK 0x0000001FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL +#undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT +#undef DDR_PHY_DTPR5_RESERVED_31_24_MASK +#define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DTPR5_RESERVED_31_24_MASK 0xFF000000U + +/* +* Activate to activate command delay (same bank) +*/ +#undef DDR_PHY_DTPR5_TRC_DEFVAL +#undef DDR_PHY_DTPR5_TRC_SHIFT +#undef DDR_PHY_DTPR5_TRC_MASK +#define DDR_PHY_DTPR5_TRC_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TRC_SHIFT 16 +#define DDR_PHY_DTPR5_TRC_MASK 0x00FF0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DTPR5_RESERVED_15_SHIFT +#undef DDR_PHY_DTPR5_RESERVED_15_MASK +#define DDR_PHY_DTPR5_RESERVED_15_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DTPR5_RESERVED_15_MASK 0x00008000U + +/* +* Activate to read or write delay +*/ +#undef DDR_PHY_DTPR5_TRCD_DEFVAL +#undef DDR_PHY_DTPR5_TRCD_SHIFT +#undef DDR_PHY_DTPR5_TRCD_MASK +#define DDR_PHY_DTPR5_TRCD_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TRCD_SHIFT 8 +#define DDR_PHY_DTPR5_TRCD_MASK 0x00007F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL +#undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT +#undef DDR_PHY_DTPR5_RESERVED_7_5_MASK +#define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR5_RESERVED_7_5_MASK 0x000000E0U + +/* +* Internal write to read command delay +*/ +#undef DDR_PHY_DTPR5_TWTR_DEFVAL +#undef DDR_PHY_DTPR5_TWTR_SHIFT +#undef DDR_PHY_DTPR5_TWTR_MASK +#define DDR_PHY_DTPR5_TWTR_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TWTR_SHIFT 0 +#define DDR_PHY_DTPR5_TWTR_MASK 0x0000001FU + +/* +* PUB Write Latency Enable +*/ +#undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL +#undef DDR_PHY_DTPR6_PUBWLEN_SHIFT +#undef DDR_PHY_DTPR6_PUBWLEN_MASK +#define DDR_PHY_DTPR6_PUBWLEN_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBWLEN_SHIFT 31 +#define DDR_PHY_DTPR6_PUBWLEN_MASK 0x80000000U + +/* +* PUB Read Latency Enable +*/ +#undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL +#undef DDR_PHY_DTPR6_PUBRLEN_SHIFT +#undef DDR_PHY_DTPR6_PUBRLEN_MASK +#define DDR_PHY_DTPR6_PUBRLEN_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBRLEN_SHIFT 30 +#define DDR_PHY_DTPR6_PUBRLEN_MASK 0x40000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL +#undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT +#undef DDR_PHY_DTPR6_RESERVED_29_14_MASK +#define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 14 +#define DDR_PHY_DTPR6_RESERVED_29_14_MASK 0x3FFFC000U + +/* +* Write Latency +*/ +#undef DDR_PHY_DTPR6_PUBWL_DEFVAL +#undef DDR_PHY_DTPR6_PUBWL_SHIFT +#undef DDR_PHY_DTPR6_PUBWL_MASK +#define DDR_PHY_DTPR6_PUBWL_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBWL_SHIFT 8 +#define DDR_PHY_DTPR6_PUBWL_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DTPR6_RESERVED_7_6_MASK +#define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DTPR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* Read Latency +*/ +#undef DDR_PHY_DTPR6_PUBRL_DEFVAL +#undef DDR_PHY_DTPR6_PUBRL_SHIFT +#undef DDR_PHY_DTPR6_PUBRL_MASK +#define DDR_PHY_DTPR6_PUBRL_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBRL_SHIFT 0 +#define DDR_PHY_DTPR6_PUBRL_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT +#undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK +#define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 31 +#define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 0x80000000U + +/* +* RDMIMM Quad CS Enable +*/ +#undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL +#undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT +#undef DDR_PHY_RDIMMGCR0_QCSEN_MASK +#define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 30 +#define DDR_PHY_RDIMMGCR0_QCSEN_MASK 0x40000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT +#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 28 +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 0x30000000U + +/* +* RDIMM Outputs I/O Mode +*/ +#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT +#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 27 +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 0x08000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT +#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 24 +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 0x07000000U + +/* +* ERROUT# Output Enable +*/ +#undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL +#undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT +#undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK +#define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 23 +#define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 0x00800000U + +/* +* ERROUT# I/O Mode +*/ +#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL +#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT +#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 22 +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 0x00400000U + +/* +* ERROUT# Power Down Receiver +*/ +#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL +#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT +#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 21 +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 0x00200000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT +#undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK +#define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 20 +#define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 0x00100000U + +/* +* ERROUT# On-Die Termination +*/ +#undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL +#undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT +#undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK +#define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 19 +#define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 0x00080000U + +/* +* Load Reduced DIMM +*/ +#undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL +#undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT +#undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK +#define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 18 +#define DDR_PHY_RDIMMGCR0_LRDIMM_MASK 0x00040000U + +/* +* PAR_IN I/O Mode +*/ +#undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL +#undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT +#undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK +#define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 17 +#define DDR_PHY_RDIMMGCR0_PARINIOM_MASK 0x00020000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT +#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 8 +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 0x0001FF00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT +#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 6 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 0x000000C0U + +/* +* Rank Mirror Enable. +*/ +#undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT +#undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK +#define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 4 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 0x00000030U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT +#undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK +#define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 3 +#define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 0x00000008U + +/* +* Stop on Parity Error +*/ +#undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL +#undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT +#undef DDR_PHY_RDIMMGCR0_SOPERR_MASK +#define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 2 +#define DDR_PHY_RDIMMGCR0_SOPERR_MASK 0x00000004U + +/* +* Parity Error No Registering +*/ +#undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL +#undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT +#undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK +#define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 1 +#define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 0x00000002U + +/* +* Registered DIMM +*/ +#undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT +#undef DDR_PHY_RDIMMGCR0_RDIMM_MASK +#define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 0 +#define DDR_PHY_RDIMMGCR0_RDIMM_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL +#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT +#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 0xE0000000U + +/* +* Address [17] B-side Inversion Disable +*/ +#undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL +#undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT +#undef DDR_PHY_RDIMMGCR1_A17BID_MASK +#define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_A17BID_SHIFT 28 +#define DDR_PHY_RDIMMGCR1_A17BID_MASK 0x10000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL +#undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT +#undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK +#define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 27 +#define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 0x08000000U + +/* +* Command word to command word programming delay +*/ +#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL +#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT +#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 24 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 0x07000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL +#undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT +#undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK +#define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 23 +#define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 0x00800000U + +/* +* Command word to command word programming delay +*/ +#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL +#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT +#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 20 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 0x00700000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL +#undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT +#undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK +#define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 19 +#define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 0x00080000U + +/* +* Command word to command word programming delay +*/ +#undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL +#undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT +#undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK +#define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 16 +#define DDR_PHY_RDIMMGCR1_TBCMRD_MASK 0x00070000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL +#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT +#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 0x0000C000U + +/* +* Stabilization time +*/ +#undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL +#undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT +#undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK +#define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 0 +#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 0x00003FFFU + +/* +* DDR4/DDR3 Control Word 7 +*/ +#undef DDR_PHY_RDIMMCR0_RC7_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC7_SHIFT +#undef DDR_PHY_RDIMMCR0_RC7_MASK +#define DDR_PHY_RDIMMCR0_RC7_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC7_SHIFT 28 +#define DDR_PHY_RDIMMCR0_RC7_MASK 0xF0000000U + +/* +* DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved +*/ +#undef DDR_PHY_RDIMMCR0_RC6_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC6_SHIFT +#undef DDR_PHY_RDIMMCR0_RC6_MASK +#define DDR_PHY_RDIMMCR0_RC6_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC6_SHIFT 24 +#define DDR_PHY_RDIMMCR0_RC6_MASK 0x0F000000U + +/* +* DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) +*/ +#undef DDR_PHY_RDIMMCR0_RC5_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC5_SHIFT +#undef DDR_PHY_RDIMMCR0_RC5_MASK +#define DDR_PHY_RDIMMCR0_RC5_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC5_SHIFT 20 +#define DDR_PHY_RDIMMCR0_RC5_MASK 0x00F00000U + +/* +* DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control + * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont + * rol Word) +*/ +#undef DDR_PHY_RDIMMCR0_RC4_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC4_SHIFT +#undef DDR_PHY_RDIMMCR0_RC4_MASK +#define DDR_PHY_RDIMMCR0_RC4_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC4_SHIFT 16 +#define DDR_PHY_RDIMMCR0_RC4_MASK 0x000F0000U + +/* +* DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo + * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri + * cs Control Word) +*/ +#undef DDR_PHY_RDIMMCR0_RC3_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC3_SHIFT +#undef DDR_PHY_RDIMMCR0_RC3_MASK +#define DDR_PHY_RDIMMCR0_RC3_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC3_SHIFT 12 +#define DDR_PHY_RDIMMCR0_RC3_MASK 0x0000F000U + +/* +* DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 + * (Timing Control Word) +*/ +#undef DDR_PHY_RDIMMCR0_RC2_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC2_SHIFT +#undef DDR_PHY_RDIMMCR0_RC2_MASK +#define DDR_PHY_RDIMMCR0_RC2_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC2_SHIFT 8 +#define DDR_PHY_RDIMMCR0_RC2_MASK 0x00000F00U + +/* +* DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) +*/ +#undef DDR_PHY_RDIMMCR0_RC1_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC1_SHIFT +#undef DDR_PHY_RDIMMCR0_RC1_MASK +#define DDR_PHY_RDIMMCR0_RC1_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC1_SHIFT 4 +#define DDR_PHY_RDIMMCR0_RC1_MASK 0x000000F0U + +/* +* DDR4/DDR3 Control Word 0 (Global Features Control Word) +*/ +#undef DDR_PHY_RDIMMCR0_RC0_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC0_SHIFT +#undef DDR_PHY_RDIMMCR0_RC0_MASK +#define DDR_PHY_RDIMMCR0_RC0_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC0_SHIFT 0 +#define DDR_PHY_RDIMMCR0_RC0_MASK 0x0000000FU + +/* +* Control Word 15 +*/ +#undef DDR_PHY_RDIMMCR1_RC15_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC15_SHIFT +#undef DDR_PHY_RDIMMCR1_RC15_MASK +#define DDR_PHY_RDIMMCR1_RC15_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC15_SHIFT 28 +#define DDR_PHY_RDIMMCR1_RC15_MASK 0xF0000000U + +/* +* DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved +*/ +#undef DDR_PHY_RDIMMCR1_RC14_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC14_SHIFT +#undef DDR_PHY_RDIMMCR1_RC14_MASK +#define DDR_PHY_RDIMMCR1_RC14_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC14_SHIFT 24 +#define DDR_PHY_RDIMMCR1_RC14_MASK 0x0F000000U + +/* +* DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved +*/ +#undef DDR_PHY_RDIMMCR1_RC13_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC13_SHIFT +#undef DDR_PHY_RDIMMCR1_RC13_MASK +#define DDR_PHY_RDIMMCR1_RC13_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC13_SHIFT 20 +#define DDR_PHY_RDIMMCR1_RC13_MASK 0x00F00000U + +/* +* DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved +*/ +#undef DDR_PHY_RDIMMCR1_RC12_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC12_SHIFT +#undef DDR_PHY_RDIMMCR1_RC12_MASK +#define DDR_PHY_RDIMMCR1_RC12_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC12_SHIFT 16 +#define DDR_PHY_RDIMMCR1_RC12_MASK 0x000F0000U + +/* +* DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo + * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word) +*/ +#undef DDR_PHY_RDIMMCR1_RC11_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC11_SHIFT +#undef DDR_PHY_RDIMMCR1_RC11_MASK +#define DDR_PHY_RDIMMCR1_RC11_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC11_SHIFT 12 +#define DDR_PHY_RDIMMCR1_RC11_MASK 0x0000F000U + +/* +* DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) +*/ +#undef DDR_PHY_RDIMMCR1_RC10_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC10_SHIFT +#undef DDR_PHY_RDIMMCR1_RC10_MASK +#define DDR_PHY_RDIMMCR1_RC10_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC10_SHIFT 8 +#define DDR_PHY_RDIMMCR1_RC10_MASK 0x00000F00U + +/* +* DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) +*/ +#undef DDR_PHY_RDIMMCR1_RC9_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC9_SHIFT +#undef DDR_PHY_RDIMMCR1_RC9_MASK +#define DDR_PHY_RDIMMCR1_RC9_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC9_SHIFT 4 +#define DDR_PHY_RDIMMCR1_RC9_MASK 0x000000F0U + +/* +* DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con + * trol Word 8 (Additional Input Bus Termination Setting Control Word) +*/ +#undef DDR_PHY_RDIMMCR1_RC8_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC8_SHIFT +#undef DDR_PHY_RDIMMCR1_RC8_MASK +#define DDR_PHY_RDIMMCR1_RC8_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC8_SHIFT 0 +#define DDR_PHY_RDIMMCR1_RC8_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR0_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR0_RESERVED_31_8_MASK +#define DDR_PHY_MR0_RESERVED_31_8_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR0_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* CA Terminating Rank +*/ +#undef DDR_PHY_MR0_CATR_DEFVAL +#undef DDR_PHY_MR0_CATR_SHIFT +#undef DDR_PHY_MR0_CATR_MASK +#define DDR_PHY_MR0_CATR_DEFVAL 0x00000052 +#define DDR_PHY_MR0_CATR_SHIFT 7 +#define DDR_PHY_MR0_CATR_MASK 0x00000080U + +/* +* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. +*/ +#undef DDR_PHY_MR0_RSVD_6_5_DEFVAL +#undef DDR_PHY_MR0_RSVD_6_5_SHIFT +#undef DDR_PHY_MR0_RSVD_6_5_MASK +#define DDR_PHY_MR0_RSVD_6_5_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RSVD_6_5_SHIFT 5 +#define DDR_PHY_MR0_RSVD_6_5_MASK 0x00000060U + +/* +* Built-in Self-Test for RZQ +*/ +#undef DDR_PHY_MR0_RZQI_DEFVAL +#undef DDR_PHY_MR0_RZQI_SHIFT +#undef DDR_PHY_MR0_RZQI_MASK +#define DDR_PHY_MR0_RZQI_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RZQI_SHIFT 3 +#define DDR_PHY_MR0_RZQI_MASK 0x00000018U + +/* +* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. +*/ +#undef DDR_PHY_MR0_RSVD_2_0_DEFVAL +#undef DDR_PHY_MR0_RSVD_2_0_SHIFT +#undef DDR_PHY_MR0_RSVD_2_0_MASK +#define DDR_PHY_MR0_RSVD_2_0_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RSVD_2_0_SHIFT 0 +#define DDR_PHY_MR0_RSVD_2_0_MASK 0x00000007U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR1_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR1_RESERVED_31_8_MASK +#define DDR_PHY_MR1_RESERVED_31_8_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR1_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* Read Postamble Length +*/ +#undef DDR_PHY_MR1_RDPST_DEFVAL +#undef DDR_PHY_MR1_RDPST_SHIFT +#undef DDR_PHY_MR1_RDPST_MASK +#define DDR_PHY_MR1_RDPST_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RDPST_SHIFT 7 +#define DDR_PHY_MR1_RDPST_MASK 0x00000080U + +/* +* Write-recovery for auto-precharge command +*/ +#undef DDR_PHY_MR1_NWR_DEFVAL +#undef DDR_PHY_MR1_NWR_SHIFT +#undef DDR_PHY_MR1_NWR_MASK +#define DDR_PHY_MR1_NWR_DEFVAL 0x00000004 +#define DDR_PHY_MR1_NWR_SHIFT 4 +#define DDR_PHY_MR1_NWR_MASK 0x00000070U + +/* +* Read Preamble Length +*/ +#undef DDR_PHY_MR1_RDPRE_DEFVAL +#undef DDR_PHY_MR1_RDPRE_SHIFT +#undef DDR_PHY_MR1_RDPRE_MASK +#define DDR_PHY_MR1_RDPRE_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RDPRE_SHIFT 3 +#define DDR_PHY_MR1_RDPRE_MASK 0x00000008U + +/* +* Write Preamble Length +*/ +#undef DDR_PHY_MR1_WRPRE_DEFVAL +#undef DDR_PHY_MR1_WRPRE_SHIFT +#undef DDR_PHY_MR1_WRPRE_MASK +#define DDR_PHY_MR1_WRPRE_DEFVAL 0x00000004 +#define DDR_PHY_MR1_WRPRE_SHIFT 2 +#define DDR_PHY_MR1_WRPRE_MASK 0x00000004U + +/* +* Burst Length +*/ +#undef DDR_PHY_MR1_BL_DEFVAL +#undef DDR_PHY_MR1_BL_SHIFT +#undef DDR_PHY_MR1_BL_MASK +#define DDR_PHY_MR1_BL_DEFVAL 0x00000004 +#define DDR_PHY_MR1_BL_SHIFT 0 +#define DDR_PHY_MR1_BL_MASK 0x00000003U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR2_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR2_RESERVED_31_8_MASK +#define DDR_PHY_MR2_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR2_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR2_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* Write Leveling +*/ +#undef DDR_PHY_MR2_WRL_DEFVAL +#undef DDR_PHY_MR2_WRL_SHIFT +#undef DDR_PHY_MR2_WRL_MASK +#define DDR_PHY_MR2_WRL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WRL_SHIFT 7 +#define DDR_PHY_MR2_WRL_MASK 0x00000080U + +/* +* Write Latency Set +*/ +#undef DDR_PHY_MR2_WLS_DEFVAL +#undef DDR_PHY_MR2_WLS_SHIFT +#undef DDR_PHY_MR2_WLS_MASK +#define DDR_PHY_MR2_WLS_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WLS_SHIFT 6 +#define DDR_PHY_MR2_WLS_MASK 0x00000040U + +/* +* Write Latency +*/ +#undef DDR_PHY_MR2_WL_DEFVAL +#undef DDR_PHY_MR2_WL_SHIFT +#undef DDR_PHY_MR2_WL_MASK +#define DDR_PHY_MR2_WL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WL_SHIFT 3 +#define DDR_PHY_MR2_WL_MASK 0x00000038U + +/* +* Read Latency +*/ +#undef DDR_PHY_MR2_RL_DEFVAL +#undef DDR_PHY_MR2_RL_SHIFT +#undef DDR_PHY_MR2_RL_MASK +#define DDR_PHY_MR2_RL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_RL_SHIFT 0 +#define DDR_PHY_MR2_RL_MASK 0x00000007U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR3_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR3_RESERVED_31_8_MASK +#define DDR_PHY_MR3_RESERVED_31_8_DEFVAL 0x00000031 +#define DDR_PHY_MR3_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR3_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* DBI-Write Enable +*/ +#undef DDR_PHY_MR3_DBIWR_DEFVAL +#undef DDR_PHY_MR3_DBIWR_SHIFT +#undef DDR_PHY_MR3_DBIWR_MASK +#define DDR_PHY_MR3_DBIWR_DEFVAL 0x00000031 +#define DDR_PHY_MR3_DBIWR_SHIFT 7 +#define DDR_PHY_MR3_DBIWR_MASK 0x00000080U + +/* +* DBI-Read Enable +*/ +#undef DDR_PHY_MR3_DBIRD_DEFVAL +#undef DDR_PHY_MR3_DBIRD_SHIFT +#undef DDR_PHY_MR3_DBIRD_MASK +#define DDR_PHY_MR3_DBIRD_DEFVAL 0x00000031 +#define DDR_PHY_MR3_DBIRD_SHIFT 6 +#define DDR_PHY_MR3_DBIRD_MASK 0x00000040U + +/* +* Pull-down Drive Strength +*/ +#undef DDR_PHY_MR3_PDDS_DEFVAL +#undef DDR_PHY_MR3_PDDS_SHIFT +#undef DDR_PHY_MR3_PDDS_MASK +#define DDR_PHY_MR3_PDDS_DEFVAL 0x00000031 +#define DDR_PHY_MR3_PDDS_SHIFT 3 +#define DDR_PHY_MR3_PDDS_MASK 0x00000038U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR3_RSVD_DEFVAL +#undef DDR_PHY_MR3_RSVD_SHIFT +#undef DDR_PHY_MR3_RSVD_MASK +#define DDR_PHY_MR3_RSVD_DEFVAL 0x00000031 +#define DDR_PHY_MR3_RSVD_SHIFT 2 +#define DDR_PHY_MR3_RSVD_MASK 0x00000004U + +/* +* Write Postamble Length +*/ +#undef DDR_PHY_MR3_WRPST_DEFVAL +#undef DDR_PHY_MR3_WRPST_SHIFT +#undef DDR_PHY_MR3_WRPST_MASK +#define DDR_PHY_MR3_WRPST_DEFVAL 0x00000031 +#define DDR_PHY_MR3_WRPST_SHIFT 1 +#define DDR_PHY_MR3_WRPST_MASK 0x00000002U + +/* +* Pull-up Calibration Point +*/ +#undef DDR_PHY_MR3_PUCAL_DEFVAL +#undef DDR_PHY_MR3_PUCAL_SHIFT +#undef DDR_PHY_MR3_PUCAL_MASK +#define DDR_PHY_MR3_PUCAL_DEFVAL 0x00000031 +#define DDR_PHY_MR3_PUCAL_SHIFT 0 +#define DDR_PHY_MR3_PUCAL_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL +#undef DDR_PHY_MR4_RESERVED_31_16_SHIFT +#undef DDR_PHY_MR4_RESERVED_31_16_MASK +#define DDR_PHY_MR4_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR4_RESERVED_31_16_MASK 0xFFFF0000U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR4_RSVD_15_13_DEFVAL +#undef DDR_PHY_MR4_RSVD_15_13_SHIFT +#undef DDR_PHY_MR4_RSVD_15_13_MASK +#define DDR_PHY_MR4_RSVD_15_13_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD_15_13_SHIFT 13 +#define DDR_PHY_MR4_RSVD_15_13_MASK 0x0000E000U + +/* +* Write Preamble +*/ +#undef DDR_PHY_MR4_WRP_DEFVAL +#undef DDR_PHY_MR4_WRP_SHIFT +#undef DDR_PHY_MR4_WRP_MASK +#define DDR_PHY_MR4_WRP_DEFVAL 0x00000000 +#define DDR_PHY_MR4_WRP_SHIFT 12 +#define DDR_PHY_MR4_WRP_MASK 0x00001000U + +/* +* Read Preamble +*/ +#undef DDR_PHY_MR4_RDP_DEFVAL +#undef DDR_PHY_MR4_RDP_SHIFT +#undef DDR_PHY_MR4_RDP_MASK +#define DDR_PHY_MR4_RDP_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RDP_SHIFT 11 +#define DDR_PHY_MR4_RDP_MASK 0x00000800U + +/* +* Read Preamble Training Mode +*/ +#undef DDR_PHY_MR4_RPTM_DEFVAL +#undef DDR_PHY_MR4_RPTM_SHIFT +#undef DDR_PHY_MR4_RPTM_MASK +#define DDR_PHY_MR4_RPTM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RPTM_SHIFT 10 +#define DDR_PHY_MR4_RPTM_MASK 0x00000400U + +/* +* Self Refresh Abort +*/ +#undef DDR_PHY_MR4_SRA_DEFVAL +#undef DDR_PHY_MR4_SRA_SHIFT +#undef DDR_PHY_MR4_SRA_MASK +#define DDR_PHY_MR4_SRA_DEFVAL 0x00000000 +#define DDR_PHY_MR4_SRA_SHIFT 9 +#define DDR_PHY_MR4_SRA_MASK 0x00000200U + +/* +* CS to Command Latency Mode +*/ +#undef DDR_PHY_MR4_CS2CMDL_DEFVAL +#undef DDR_PHY_MR4_CS2CMDL_SHIFT +#undef DDR_PHY_MR4_CS2CMDL_MASK +#define DDR_PHY_MR4_CS2CMDL_DEFVAL 0x00000000 +#define DDR_PHY_MR4_CS2CMDL_SHIFT 6 +#define DDR_PHY_MR4_CS2CMDL_MASK 0x000001C0U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR4_RSVD1_DEFVAL +#undef DDR_PHY_MR4_RSVD1_SHIFT +#undef DDR_PHY_MR4_RSVD1_MASK +#define DDR_PHY_MR4_RSVD1_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD1_SHIFT 5 +#define DDR_PHY_MR4_RSVD1_MASK 0x00000020U + +/* +* Internal VREF Monitor +*/ +#undef DDR_PHY_MR4_IVM_DEFVAL +#undef DDR_PHY_MR4_IVM_SHIFT +#undef DDR_PHY_MR4_IVM_MASK +#define DDR_PHY_MR4_IVM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_IVM_SHIFT 4 +#define DDR_PHY_MR4_IVM_MASK 0x00000010U + +/* +* Temperature Controlled Refresh Mode +*/ +#undef DDR_PHY_MR4_TCRM_DEFVAL +#undef DDR_PHY_MR4_TCRM_SHIFT +#undef DDR_PHY_MR4_TCRM_MASK +#define DDR_PHY_MR4_TCRM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_TCRM_SHIFT 3 +#define DDR_PHY_MR4_TCRM_MASK 0x00000008U + +/* +* Temperature Controlled Refresh Range +*/ +#undef DDR_PHY_MR4_TCRR_DEFVAL +#undef DDR_PHY_MR4_TCRR_SHIFT +#undef DDR_PHY_MR4_TCRR_MASK +#define DDR_PHY_MR4_TCRR_DEFVAL 0x00000000 +#define DDR_PHY_MR4_TCRR_SHIFT 2 +#define DDR_PHY_MR4_TCRR_MASK 0x00000004U + +/* +* Maximum Power Down Mode +*/ +#undef DDR_PHY_MR4_MPDM_DEFVAL +#undef DDR_PHY_MR4_MPDM_SHIFT +#undef DDR_PHY_MR4_MPDM_MASK +#define DDR_PHY_MR4_MPDM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_MPDM_SHIFT 1 +#define DDR_PHY_MR4_MPDM_MASK 0x00000002U + +/* +* This is a JEDEC reserved bit and is recommended by JEDEC to be programme + * d to 0x0. +*/ +#undef DDR_PHY_MR4_RSVD_0_DEFVAL +#undef DDR_PHY_MR4_RSVD_0_SHIFT +#undef DDR_PHY_MR4_RSVD_0_MASK +#define DDR_PHY_MR4_RSVD_0_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD_0_SHIFT 0 +#define DDR_PHY_MR4_RSVD_0_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL +#undef DDR_PHY_MR5_RESERVED_31_16_SHIFT +#undef DDR_PHY_MR5_RESERVED_31_16_MASK +#define DDR_PHY_MR5_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR5_RESERVED_31_16_MASK 0xFFFF0000U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR5_RSVD_DEFVAL +#undef DDR_PHY_MR5_RSVD_SHIFT +#undef DDR_PHY_MR5_RSVD_MASK +#define DDR_PHY_MR5_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RSVD_SHIFT 13 +#define DDR_PHY_MR5_RSVD_MASK 0x0000E000U + +/* +* Read DBI +*/ +#undef DDR_PHY_MR5_RDBI_DEFVAL +#undef DDR_PHY_MR5_RDBI_SHIFT +#undef DDR_PHY_MR5_RDBI_MASK +#define DDR_PHY_MR5_RDBI_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RDBI_SHIFT 12 +#define DDR_PHY_MR5_RDBI_MASK 0x00001000U + +/* +* Write DBI +*/ +#undef DDR_PHY_MR5_WDBI_DEFVAL +#undef DDR_PHY_MR5_WDBI_SHIFT +#undef DDR_PHY_MR5_WDBI_MASK +#define DDR_PHY_MR5_WDBI_DEFVAL 0x00000000 +#define DDR_PHY_MR5_WDBI_SHIFT 11 +#define DDR_PHY_MR5_WDBI_MASK 0x00000800U + +/* +* Data Mask +*/ +#undef DDR_PHY_MR5_DM_DEFVAL +#undef DDR_PHY_MR5_DM_SHIFT +#undef DDR_PHY_MR5_DM_MASK +#define DDR_PHY_MR5_DM_DEFVAL 0x00000000 +#define DDR_PHY_MR5_DM_SHIFT 10 +#define DDR_PHY_MR5_DM_MASK 0x00000400U + +/* +* CA Parity Persistent Error +*/ +#undef DDR_PHY_MR5_CAPPE_DEFVAL +#undef DDR_PHY_MR5_CAPPE_SHIFT +#undef DDR_PHY_MR5_CAPPE_MASK +#define DDR_PHY_MR5_CAPPE_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPPE_SHIFT 9 +#define DDR_PHY_MR5_CAPPE_MASK 0x00000200U + +/* +* RTT_PARK +*/ +#undef DDR_PHY_MR5_RTTPARK_DEFVAL +#undef DDR_PHY_MR5_RTTPARK_SHIFT +#undef DDR_PHY_MR5_RTTPARK_MASK +#define DDR_PHY_MR5_RTTPARK_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RTTPARK_SHIFT 6 +#define DDR_PHY_MR5_RTTPARK_MASK 0x000001C0U + +/* +* ODT Input Buffer during Power Down mode +*/ +#undef DDR_PHY_MR5_ODTIBPD_DEFVAL +#undef DDR_PHY_MR5_ODTIBPD_SHIFT +#undef DDR_PHY_MR5_ODTIBPD_MASK +#define DDR_PHY_MR5_ODTIBPD_DEFVAL 0x00000000 +#define DDR_PHY_MR5_ODTIBPD_SHIFT 5 +#define DDR_PHY_MR5_ODTIBPD_MASK 0x00000020U + +/* +* C/A Parity Error Status +*/ +#undef DDR_PHY_MR5_CAPES_DEFVAL +#undef DDR_PHY_MR5_CAPES_SHIFT +#undef DDR_PHY_MR5_CAPES_MASK +#define DDR_PHY_MR5_CAPES_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPES_SHIFT 4 +#define DDR_PHY_MR5_CAPES_MASK 0x00000010U + +/* +* CRC Error Clear +*/ +#undef DDR_PHY_MR5_CRCEC_DEFVAL +#undef DDR_PHY_MR5_CRCEC_SHIFT +#undef DDR_PHY_MR5_CRCEC_MASK +#define DDR_PHY_MR5_CRCEC_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CRCEC_SHIFT 3 +#define DDR_PHY_MR5_CRCEC_MASK 0x00000008U + +/* +* C/A Parity Latency Mode +*/ +#undef DDR_PHY_MR5_CAPM_DEFVAL +#undef DDR_PHY_MR5_CAPM_SHIFT +#undef DDR_PHY_MR5_CAPM_MASK +#define DDR_PHY_MR5_CAPM_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPM_SHIFT 0 +#define DDR_PHY_MR5_CAPM_MASK 0x00000007U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL +#undef DDR_PHY_MR6_RESERVED_31_16_SHIFT +#undef DDR_PHY_MR6_RESERVED_31_16_MASK +#define DDR_PHY_MR6_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR6_RESERVED_31_16_MASK 0xFFFF0000U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR6_RSVD_15_13_DEFVAL +#undef DDR_PHY_MR6_RSVD_15_13_SHIFT +#undef DDR_PHY_MR6_RSVD_15_13_MASK +#define DDR_PHY_MR6_RSVD_15_13_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RSVD_15_13_SHIFT 13 +#define DDR_PHY_MR6_RSVD_15_13_MASK 0x0000E000U + +/* +* CAS_n to CAS_n command delay for same bank group (tCCD_L) +*/ +#undef DDR_PHY_MR6_TCCDL_DEFVAL +#undef DDR_PHY_MR6_TCCDL_SHIFT +#undef DDR_PHY_MR6_TCCDL_MASK +#define DDR_PHY_MR6_TCCDL_DEFVAL 0x00000000 +#define DDR_PHY_MR6_TCCDL_SHIFT 10 +#define DDR_PHY_MR6_TCCDL_MASK 0x00001C00U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR6_RSVD_9_8_DEFVAL +#undef DDR_PHY_MR6_RSVD_9_8_SHIFT +#undef DDR_PHY_MR6_RSVD_9_8_MASK +#define DDR_PHY_MR6_RSVD_9_8_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RSVD_9_8_SHIFT 8 +#define DDR_PHY_MR6_RSVD_9_8_MASK 0x00000300U + +/* +* VrefDQ Training Enable +*/ +#undef DDR_PHY_MR6_VDDQTEN_DEFVAL +#undef DDR_PHY_MR6_VDDQTEN_SHIFT +#undef DDR_PHY_MR6_VDDQTEN_MASK +#define DDR_PHY_MR6_VDDQTEN_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDDQTEN_SHIFT 7 +#define DDR_PHY_MR6_VDDQTEN_MASK 0x00000080U + +/* +* VrefDQ Training Range +*/ +#undef DDR_PHY_MR6_VDQTRG_DEFVAL +#undef DDR_PHY_MR6_VDQTRG_SHIFT +#undef DDR_PHY_MR6_VDQTRG_MASK +#define DDR_PHY_MR6_VDQTRG_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDQTRG_SHIFT 6 +#define DDR_PHY_MR6_VDQTRG_MASK 0x00000040U + +/* +* VrefDQ Training Values +*/ +#undef DDR_PHY_MR6_VDQTVAL_DEFVAL +#undef DDR_PHY_MR6_VDQTVAL_SHIFT +#undef DDR_PHY_MR6_VDQTVAL_MASK +#define DDR_PHY_MR6_VDQTVAL_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDQTVAL_SHIFT 0 +#define DDR_PHY_MR6_VDQTVAL_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR11_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR11_RESERVED_31_8_MASK +#define DDR_PHY_MR11_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR11_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR11_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR11_RSVD_DEFVAL +#undef DDR_PHY_MR11_RSVD_SHIFT +#undef DDR_PHY_MR11_RSVD_MASK +#define DDR_PHY_MR11_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR11_RSVD_SHIFT 3 +#define DDR_PHY_MR11_RSVD_MASK 0x000000F8U + +/* +* Power Down Control +*/ +#undef DDR_PHY_MR11_PDCTL_DEFVAL +#undef DDR_PHY_MR11_PDCTL_SHIFT +#undef DDR_PHY_MR11_PDCTL_MASK +#define DDR_PHY_MR11_PDCTL_DEFVAL 0x00000000 +#define DDR_PHY_MR11_PDCTL_SHIFT 2 +#define DDR_PHY_MR11_PDCTL_MASK 0x00000004U + +/* +* DQ Bus Receiver On-Die-Termination +*/ +#undef DDR_PHY_MR11_DQODT_DEFVAL +#undef DDR_PHY_MR11_DQODT_SHIFT +#undef DDR_PHY_MR11_DQODT_MASK +#define DDR_PHY_MR11_DQODT_DEFVAL 0x00000000 +#define DDR_PHY_MR11_DQODT_SHIFT 0 +#define DDR_PHY_MR11_DQODT_MASK 0x00000003U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR12_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR12_RESERVED_31_8_MASK +#define DDR_PHY_MR12_RESERVED_31_8_DEFVAL 0x0000004D +#define DDR_PHY_MR12_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR12_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR12_RSVD_DEFVAL +#undef DDR_PHY_MR12_RSVD_SHIFT +#undef DDR_PHY_MR12_RSVD_MASK +#define DDR_PHY_MR12_RSVD_DEFVAL 0x0000004D +#define DDR_PHY_MR12_RSVD_SHIFT 7 +#define DDR_PHY_MR12_RSVD_MASK 0x00000080U + +/* +* VREF_CA Range Select. +*/ +#undef DDR_PHY_MR12_VR_CA_DEFVAL +#undef DDR_PHY_MR12_VR_CA_SHIFT +#undef DDR_PHY_MR12_VR_CA_MASK +#define DDR_PHY_MR12_VR_CA_DEFVAL 0x0000004D +#define DDR_PHY_MR12_VR_CA_SHIFT 6 +#define DDR_PHY_MR12_VR_CA_MASK 0x00000040U + +/* +* Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. +*/ +#undef DDR_PHY_MR12_VREF_CA_DEFVAL +#undef DDR_PHY_MR12_VREF_CA_SHIFT +#undef DDR_PHY_MR12_VREF_CA_MASK +#define DDR_PHY_MR12_VREF_CA_DEFVAL 0x0000004D +#define DDR_PHY_MR12_VREF_CA_SHIFT 0 +#define DDR_PHY_MR12_VREF_CA_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR13_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR13_RESERVED_31_8_MASK +#define DDR_PHY_MR13_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR13_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* Frequency Set Point Operation Mode +*/ +#undef DDR_PHY_MR13_FSPOP_DEFVAL +#undef DDR_PHY_MR13_FSPOP_SHIFT +#undef DDR_PHY_MR13_FSPOP_MASK +#define DDR_PHY_MR13_FSPOP_DEFVAL 0x00000000 +#define DDR_PHY_MR13_FSPOP_SHIFT 7 +#define DDR_PHY_MR13_FSPOP_MASK 0x00000080U + +/* +* Frequency Set Point Write Enable +*/ +#undef DDR_PHY_MR13_FSPWR_DEFVAL +#undef DDR_PHY_MR13_FSPWR_SHIFT +#undef DDR_PHY_MR13_FSPWR_MASK +#define DDR_PHY_MR13_FSPWR_DEFVAL 0x00000000 +#define DDR_PHY_MR13_FSPWR_SHIFT 6 +#define DDR_PHY_MR13_FSPWR_MASK 0x00000040U + +/* +* Data Mask Enable +*/ +#undef DDR_PHY_MR13_DMD_DEFVAL +#undef DDR_PHY_MR13_DMD_SHIFT +#undef DDR_PHY_MR13_DMD_MASK +#define DDR_PHY_MR13_DMD_DEFVAL 0x00000000 +#define DDR_PHY_MR13_DMD_SHIFT 5 +#define DDR_PHY_MR13_DMD_MASK 0x00000020U + +/* +* Refresh Rate Option +*/ +#undef DDR_PHY_MR13_RRO_DEFVAL +#undef DDR_PHY_MR13_RRO_SHIFT +#undef DDR_PHY_MR13_RRO_MASK +#define DDR_PHY_MR13_RRO_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RRO_SHIFT 4 +#define DDR_PHY_MR13_RRO_MASK 0x00000010U + +/* +* VREF Current Generator +*/ +#undef DDR_PHY_MR13_VRCG_DEFVAL +#undef DDR_PHY_MR13_VRCG_SHIFT +#undef DDR_PHY_MR13_VRCG_MASK +#define DDR_PHY_MR13_VRCG_DEFVAL 0x00000000 +#define DDR_PHY_MR13_VRCG_SHIFT 3 +#define DDR_PHY_MR13_VRCG_MASK 0x00000008U + +/* +* VREF Output +*/ +#undef DDR_PHY_MR13_VRO_DEFVAL +#undef DDR_PHY_MR13_VRO_SHIFT +#undef DDR_PHY_MR13_VRO_MASK +#define DDR_PHY_MR13_VRO_DEFVAL 0x00000000 +#define DDR_PHY_MR13_VRO_SHIFT 2 +#define DDR_PHY_MR13_VRO_MASK 0x00000004U + +/* +* Read Preamble Training Mode +*/ +#undef DDR_PHY_MR13_RPT_DEFVAL +#undef DDR_PHY_MR13_RPT_SHIFT +#undef DDR_PHY_MR13_RPT_MASK +#define DDR_PHY_MR13_RPT_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RPT_SHIFT 1 +#define DDR_PHY_MR13_RPT_MASK 0x00000002U + +/* +* Command Bus Training +*/ +#undef DDR_PHY_MR13_CBT_DEFVAL +#undef DDR_PHY_MR13_CBT_SHIFT +#undef DDR_PHY_MR13_CBT_MASK +#define DDR_PHY_MR13_CBT_DEFVAL 0x00000000 +#define DDR_PHY_MR13_CBT_SHIFT 0 +#define DDR_PHY_MR13_CBT_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR14_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR14_RESERVED_31_8_MASK +#define DDR_PHY_MR14_RESERVED_31_8_DEFVAL 0x0000004D +#define DDR_PHY_MR14_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR14_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR14_RSVD_DEFVAL +#undef DDR_PHY_MR14_RSVD_SHIFT +#undef DDR_PHY_MR14_RSVD_MASK +#define DDR_PHY_MR14_RSVD_DEFVAL 0x0000004D +#define DDR_PHY_MR14_RSVD_SHIFT 7 +#define DDR_PHY_MR14_RSVD_MASK 0x00000080U + +/* +* VREFDQ Range Selects. +*/ +#undef DDR_PHY_MR14_VR_DQ_DEFVAL +#undef DDR_PHY_MR14_VR_DQ_SHIFT +#undef DDR_PHY_MR14_VR_DQ_MASK +#define DDR_PHY_MR14_VR_DQ_DEFVAL 0x0000004D +#define DDR_PHY_MR14_VR_DQ_SHIFT 6 +#define DDR_PHY_MR14_VR_DQ_MASK 0x00000040U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR14_VREF_DQ_DEFVAL +#undef DDR_PHY_MR14_VREF_DQ_SHIFT +#undef DDR_PHY_MR14_VREF_DQ_MASK +#define DDR_PHY_MR14_VREF_DQ_DEFVAL 0x0000004D +#define DDR_PHY_MR14_VREF_DQ_SHIFT 0 +#define DDR_PHY_MR14_VREF_DQ_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR22_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR22_RESERVED_31_8_MASK +#define DDR_PHY_MR22_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR22_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR22_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR22_RSVD_DEFVAL +#undef DDR_PHY_MR22_RSVD_SHIFT +#undef DDR_PHY_MR22_RSVD_MASK +#define DDR_PHY_MR22_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR22_RSVD_SHIFT 6 +#define DDR_PHY_MR22_RSVD_MASK 0x000000C0U + +/* +* CA ODT termination disable. +*/ +#undef DDR_PHY_MR22_ODTD_CA_DEFVAL +#undef DDR_PHY_MR22_ODTD_CA_SHIFT +#undef DDR_PHY_MR22_ODTD_CA_MASK +#define DDR_PHY_MR22_ODTD_CA_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTD_CA_SHIFT 5 +#define DDR_PHY_MR22_ODTD_CA_MASK 0x00000020U + +/* +* ODT CS override. +*/ +#undef DDR_PHY_MR22_ODTE_CS_DEFVAL +#undef DDR_PHY_MR22_ODTE_CS_SHIFT +#undef DDR_PHY_MR22_ODTE_CS_MASK +#define DDR_PHY_MR22_ODTE_CS_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTE_CS_SHIFT 4 +#define DDR_PHY_MR22_ODTE_CS_MASK 0x00000010U + +/* +* ODT CK override. +*/ +#undef DDR_PHY_MR22_ODTE_CK_DEFVAL +#undef DDR_PHY_MR22_ODTE_CK_SHIFT +#undef DDR_PHY_MR22_ODTE_CK_MASK +#define DDR_PHY_MR22_ODTE_CK_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTE_CK_SHIFT 3 +#define DDR_PHY_MR22_ODTE_CK_MASK 0x00000008U + +/* +* Controller ODT value for VOH calibration. +*/ +#undef DDR_PHY_MR22_CODT_DEFVAL +#undef DDR_PHY_MR22_CODT_SHIFT +#undef DDR_PHY_MR22_CODT_MASK +#define DDR_PHY_MR22_CODT_DEFVAL 0x00000000 +#define DDR_PHY_MR22_CODT_SHIFT 0 +#define DDR_PHY_MR22_CODT_MASK 0x00000007U + +/* +* Refresh During Training +*/ +#undef DDR_PHY_DTCR0_RFSHDT_DEFVAL +#undef DDR_PHY_DTCR0_RFSHDT_SHIFT +#undef DDR_PHY_DTCR0_RFSHDT_MASK +#define DDR_PHY_DTCR0_RFSHDT_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RFSHDT_SHIFT 28 +#define DDR_PHY_DTCR0_RFSHDT_MASK 0xF0000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL +#undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT +#undef DDR_PHY_DTCR0_RESERVED_27_26_MASK +#define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 26 +#define DDR_PHY_DTCR0_RESERVED_27_26_MASK 0x0C000000U + +/* +* Data Training Debug Rank Select +*/ +#undef DDR_PHY_DTCR0_DTDRS_DEFVAL +#undef DDR_PHY_DTCR0_DTDRS_SHIFT +#undef DDR_PHY_DTCR0_DTDRS_MASK +#define DDR_PHY_DTCR0_DTDRS_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDRS_SHIFT 24 +#define DDR_PHY_DTCR0_DTDRS_MASK 0x03000000U + +/* +* Data Training with Early/Extended Gate +*/ +#undef DDR_PHY_DTCR0_DTEXG_DEFVAL +#undef DDR_PHY_DTCR0_DTEXG_SHIFT +#undef DDR_PHY_DTCR0_DTEXG_MASK +#define DDR_PHY_DTCR0_DTEXG_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTEXG_SHIFT 23 +#define DDR_PHY_DTCR0_DTEXG_MASK 0x00800000U + +/* +* Data Training Extended Write DQS +*/ +#undef DDR_PHY_DTCR0_DTEXD_DEFVAL +#undef DDR_PHY_DTCR0_DTEXD_SHIFT +#undef DDR_PHY_DTCR0_DTEXD_MASK +#define DDR_PHY_DTCR0_DTEXD_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTEXD_SHIFT 22 +#define DDR_PHY_DTCR0_DTEXD_MASK 0x00400000U + +/* +* Data Training Debug Step +*/ +#undef DDR_PHY_DTCR0_DTDSTP_DEFVAL +#undef DDR_PHY_DTCR0_DTDSTP_SHIFT +#undef DDR_PHY_DTCR0_DTDSTP_MASK +#define DDR_PHY_DTCR0_DTDSTP_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDSTP_SHIFT 21 +#define DDR_PHY_DTCR0_DTDSTP_MASK 0x00200000U + +/* +* Data Training Debug Enable +*/ +#undef DDR_PHY_DTCR0_DTDEN_DEFVAL +#undef DDR_PHY_DTCR0_DTDEN_SHIFT +#undef DDR_PHY_DTCR0_DTDEN_MASK +#define DDR_PHY_DTCR0_DTDEN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDEN_SHIFT 20 +#define DDR_PHY_DTCR0_DTDEN_MASK 0x00100000U + +/* +* Data Training Debug Byte Select +*/ +#undef DDR_PHY_DTCR0_DTDBS_DEFVAL +#undef DDR_PHY_DTCR0_DTDBS_SHIFT +#undef DDR_PHY_DTCR0_DTDBS_MASK +#define DDR_PHY_DTCR0_DTDBS_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDBS_SHIFT 16 +#define DDR_PHY_DTCR0_DTDBS_MASK 0x000F0000U + +/* +* Data Training read DBI deskewing configuration +*/ +#undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL +#undef DDR_PHY_DTCR0_DTRDBITR_SHIFT +#undef DDR_PHY_DTCR0_DTRDBITR_MASK +#define DDR_PHY_DTCR0_DTRDBITR_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTRDBITR_SHIFT 14 +#define DDR_PHY_DTCR0_DTRDBITR_MASK 0x0000C000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL +#undef DDR_PHY_DTCR0_RESERVED_13_SHIFT +#undef DDR_PHY_DTCR0_RESERVED_13_MASK +#define DDR_PHY_DTCR0_RESERVED_13_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_13_SHIFT 13 +#define DDR_PHY_DTCR0_RESERVED_13_MASK 0x00002000U + +/* +* Data Training Write Bit Deskew Data Mask +*/ +#undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL +#undef DDR_PHY_DTCR0_DTWBDDM_SHIFT +#undef DDR_PHY_DTCR0_DTWBDDM_MASK +#define DDR_PHY_DTCR0_DTWBDDM_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTWBDDM_SHIFT 12 +#define DDR_PHY_DTCR0_DTWBDDM_MASK 0x00001000U + +/* +* Refreshes Issued During Entry to Training +*/ +#undef DDR_PHY_DTCR0_RFSHEN_DEFVAL +#undef DDR_PHY_DTCR0_RFSHEN_SHIFT +#undef DDR_PHY_DTCR0_RFSHEN_MASK +#define DDR_PHY_DTCR0_RFSHEN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RFSHEN_SHIFT 8 +#define DDR_PHY_DTCR0_RFSHEN_MASK 0x00000F00U + +/* +* Data Training Compare Data +*/ +#undef DDR_PHY_DTCR0_DTCMPD_DEFVAL +#undef DDR_PHY_DTCR0_DTCMPD_SHIFT +#undef DDR_PHY_DTCR0_DTCMPD_MASK +#define DDR_PHY_DTCR0_DTCMPD_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTCMPD_SHIFT 7 +#define DDR_PHY_DTCR0_DTCMPD_MASK 0x00000080U + +/* +* Data Training Using MPR +*/ +#undef DDR_PHY_DTCR0_DTMPR_DEFVAL +#undef DDR_PHY_DTCR0_DTMPR_SHIFT +#undef DDR_PHY_DTCR0_DTMPR_MASK +#define DDR_PHY_DTCR0_DTMPR_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTMPR_SHIFT 6 +#define DDR_PHY_DTCR0_DTMPR_MASK 0x00000040U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL +#undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT +#undef DDR_PHY_DTCR0_RESERVED_5_4_MASK +#define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 4 +#define DDR_PHY_DTCR0_RESERVED_5_4_MASK 0x00000030U + +/* +* Data Training Repeat Number +*/ +#undef DDR_PHY_DTCR0_DTRPTN_DEFVAL +#undef DDR_PHY_DTCR0_DTRPTN_SHIFT +#undef DDR_PHY_DTCR0_DTRPTN_MASK +#define DDR_PHY_DTCR0_DTRPTN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTRPTN_SHIFT 0 +#define DDR_PHY_DTCR0_DTRPTN_MASK 0x0000000FU + +/* +* Rank Enable. +*/ +#undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL +#undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT +#undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK +#define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 18 +#define DDR_PHY_DTCR1_RANKEN_RSVD_MASK 0xFFFC0000U + +/* +* Rank Enable. +*/ +#undef DDR_PHY_DTCR1_RANKEN_DEFVAL +#undef DDR_PHY_DTCR1_RANKEN_SHIFT +#undef DDR_PHY_DTCR1_RANKEN_MASK +#define DDR_PHY_DTCR1_RANKEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RANKEN_SHIFT 16 +#define DDR_PHY_DTCR1_RANKEN_MASK 0x00030000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT +#undef DDR_PHY_DTCR1_RESERVED_15_14_MASK +#define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DTCR1_RESERVED_15_14_MASK 0x0000C000U + +/* +* Data Training Rank +*/ +#undef DDR_PHY_DTCR1_DTRANK_DEFVAL +#undef DDR_PHY_DTCR1_DTRANK_SHIFT +#undef DDR_PHY_DTCR1_DTRANK_MASK +#define DDR_PHY_DTCR1_DTRANK_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_DTRANK_SHIFT 12 +#define DDR_PHY_DTCR1_DTRANK_MASK 0x00003000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL +#undef DDR_PHY_DTCR1_RESERVED_11_SHIFT +#undef DDR_PHY_DTCR1_RESERVED_11_MASK +#define DDR_PHY_DTCR1_RESERVED_11_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_11_SHIFT 11 +#define DDR_PHY_DTCR1_RESERVED_11_MASK 0x00000800U + +/* +* Read Leveling Gate Sampling Difference +*/ +#undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL +#undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT +#undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK +#define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 8 +#define DDR_PHY_DTCR1_RDLVLGDIFF_MASK 0x00000700U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL +#undef DDR_PHY_DTCR1_RESERVED_7_SHIFT +#undef DDR_PHY_DTCR1_RESERVED_7_MASK +#define DDR_PHY_DTCR1_RESERVED_7_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_7_SHIFT 7 +#define DDR_PHY_DTCR1_RESERVED_7_MASK 0x00000080U + +/* +* Read Leveling Gate Shift +*/ +#undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL +#undef DDR_PHY_DTCR1_RDLVLGS_SHIFT +#undef DDR_PHY_DTCR1_RDLVLGS_MASK +#define DDR_PHY_DTCR1_RDLVLGS_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLGS_SHIFT 4 +#define DDR_PHY_DTCR1_RDLVLGS_MASK 0x00000070U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL +#undef DDR_PHY_DTCR1_RESERVED_3_SHIFT +#undef DDR_PHY_DTCR1_RESERVED_3_MASK +#define DDR_PHY_DTCR1_RESERVED_3_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_3_SHIFT 3 +#define DDR_PHY_DTCR1_RESERVED_3_MASK 0x00000008U + +/* +* Read Preamble Training enable +*/ +#undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL +#undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT +#undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK +#define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 2 +#define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 0x00000004U + +/* +* Read Leveling Enable +*/ +#undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL +#undef DDR_PHY_DTCR1_RDLVLEN_SHIFT +#undef DDR_PHY_DTCR1_RDLVLEN_MASK +#define DDR_PHY_DTCR1_RDLVLEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLEN_SHIFT 1 +#define DDR_PHY_DTCR1_RDLVLEN_MASK 0x00000002U + +/* +* Basic Gate Training Enable +*/ +#undef DDR_PHY_DTCR1_BSTEN_DEFVAL +#undef DDR_PHY_DTCR1_BSTEN_SHIFT +#undef DDR_PHY_DTCR1_BSTEN_MASK +#define DDR_PHY_DTCR1_BSTEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_BSTEN_SHIFT 0 +#define DDR_PHY_DTCR1_BSTEN_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL +#undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT +#undef DDR_PHY_CATR0_RESERVED_31_21_MASK +#define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_RESERVED_31_21_SHIFT 21 +#define DDR_PHY_CATR0_RESERVED_31_21_MASK 0xFFE00000U + +/* +* Minimum time (in terms of number of dram clocks) between two consectuve + * CA calibration command +*/ +#undef DDR_PHY_CATR0_CACD_DEFVAL +#undef DDR_PHY_CATR0_CACD_SHIFT +#undef DDR_PHY_CATR0_CACD_MASK +#define DDR_PHY_CATR0_CACD_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CACD_SHIFT 16 +#define DDR_PHY_CATR0_CACD_MASK 0x001F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL +#undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT +#undef DDR_PHY_CATR0_RESERVED_15_13_MASK +#define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_RESERVED_15_13_SHIFT 13 +#define DDR_PHY_CATR0_RESERVED_15_13_MASK 0x0000E000U + +/* +* Minimum time (in terms of number of dram clocks) PUB should wait before + * sampling the CA response after Calibration command has been sent to the + * memory +*/ +#undef DDR_PHY_CATR0_CAADR_DEFVAL +#undef DDR_PHY_CATR0_CAADR_SHIFT +#undef DDR_PHY_CATR0_CAADR_MASK +#define DDR_PHY_CATR0_CAADR_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CAADR_SHIFT 8 +#define DDR_PHY_CATR0_CAADR_MASK 0x00001F00U + +/* +* CA_1 Response Byte Lane 1 +*/ +#undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL +#undef DDR_PHY_CATR0_CA1BYTE1_SHIFT +#undef DDR_PHY_CATR0_CA1BYTE1_MASK +#define DDR_PHY_CATR0_CA1BYTE1_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CA1BYTE1_SHIFT 4 +#define DDR_PHY_CATR0_CA1BYTE1_MASK 0x000000F0U + +/* +* CA_1 Response Byte Lane 0 +*/ +#undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL +#undef DDR_PHY_CATR0_CA1BYTE0_SHIFT +#undef DDR_PHY_CATR0_CA1BYTE0_MASK +#define DDR_PHY_CATR0_CA1BYTE0_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CA1BYTE0_SHIFT 0 +#define DDR_PHY_CATR0_CA1BYTE0_MASK 0x0000000FU + +/* +* Number of delay taps by which the DQS gate LCDL will be updated when DQS + * drift is detected +*/ +#undef DDR_PHY_DQSDR0_DFTDLY_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDLY_SHIFT +#undef DDR_PHY_DQSDR0_DFTDLY_MASK +#define DDR_PHY_DQSDR0_DFTDLY_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDLY_SHIFT 28 +#define DDR_PHY_DQSDR0_DFTDLY_MASK 0xF0000000U + +/* +* Drift Impedance Update +*/ +#undef DDR_PHY_DQSDR0_DFTZQUP_DEFVAL +#undef DDR_PHY_DQSDR0_DFTZQUP_SHIFT +#undef DDR_PHY_DQSDR0_DFTZQUP_MASK +#define DDR_PHY_DQSDR0_DFTZQUP_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTZQUP_SHIFT 27 +#define DDR_PHY_DQSDR0_DFTZQUP_MASK 0x08000000U + +/* +* Drift DDL Update +*/ +#undef DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDDLUP_SHIFT +#undef DDR_PHY_DQSDR0_DFTDDLUP_MASK +#define DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDDLUP_SHIFT 26 +#define DDR_PHY_DQSDR0_DFTDDLUP_MASK 0x04000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL +#undef DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT +#undef DDR_PHY_DQSDR0_RESERVED_25_22_MASK +#define DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT 22 +#define DDR_PHY_DQSDR0_RESERVED_25_22_MASK 0x03C00000U + +/* +* Drift Read Spacing +*/ +#undef DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL +#undef DDR_PHY_DQSDR0_DFTRDSPC_SHIFT +#undef DDR_PHY_DQSDR0_DFTRDSPC_MASK +#define DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTRDSPC_SHIFT 20 +#define DDR_PHY_DQSDR0_DFTRDSPC_MASK 0x00300000U + +/* +* Drift Back-to-Back Reads +*/ +#undef DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL +#undef DDR_PHY_DQSDR0_DFTB2BRD_SHIFT +#undef DDR_PHY_DQSDR0_DFTB2BRD_MASK +#define DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTB2BRD_SHIFT 16 +#define DDR_PHY_DQSDR0_DFTB2BRD_MASK 0x000F0000U + +/* +* Drift Idle Reads +*/ +#undef DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL +#undef DDR_PHY_DQSDR0_DFTIDLRD_SHIFT +#undef DDR_PHY_DQSDR0_DFTIDLRD_MASK +#define DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTIDLRD_SHIFT 12 +#define DDR_PHY_DQSDR0_DFTIDLRD_MASK 0x0000F000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL +#undef DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT +#undef DDR_PHY_DQSDR0_RESERVED_11_8_MASK +#define DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT 8 +#define DDR_PHY_DQSDR0_RESERVED_11_8_MASK 0x00000F00U + +/* +* Gate Pulse Enable +*/ +#undef DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTGPULSE_SHIFT +#undef DDR_PHY_DQSDR0_DFTGPULSE_MASK +#define DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTGPULSE_SHIFT 4 +#define DDR_PHY_DQSDR0_DFTGPULSE_MASK 0x000000F0U + +/* +* DQS Drift Update Mode +*/ +#undef DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTUPMODE_SHIFT +#undef DDR_PHY_DQSDR0_DFTUPMODE_MASK +#define DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTUPMODE_SHIFT 2 +#define DDR_PHY_DQSDR0_DFTUPMODE_MASK 0x0000000CU + +/* +* DQS Drift Detection Mode +*/ +#undef DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDTMODE_SHIFT +#undef DDR_PHY_DQSDR0_DFTDTMODE_MASK +#define DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDTMODE_SHIFT 1 +#define DDR_PHY_DQSDR0_DFTDTMODE_MASK 0x00000002U + +/* +* DQS Drift Detection Enable +*/ +#undef DDR_PHY_DQSDR0_DFTDTEN_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDTEN_SHIFT +#undef DDR_PHY_DQSDR0_DFTDTEN_MASK +#define DDR_PHY_DQSDR0_DFTDTEN_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDTEN_SHIFT 0 +#define DDR_PHY_DQSDR0_DFTDTEN_MASK 0x00000001U + +/* +* LFSR seed for pseudo-random BIST patterns +*/ +#undef DDR_PHY_BISTLSR_SEED_DEFVAL +#undef DDR_PHY_BISTLSR_SEED_SHIFT +#undef DDR_PHY_BISTLSR_SEED_MASK +#define DDR_PHY_BISTLSR_SEED_DEFVAL +#define DDR_PHY_BISTLSR_SEED_SHIFT 0 +#define DDR_PHY_BISTLSR_SEED_MASK 0xFFFFFFFFU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL +#undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT +#undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK +#define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_RIOCR5_RESERVED_31_16_MASK 0xFFFF0000U + +/* +* Reserved. Return zeros on reads. +*/ +#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL +#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT +#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 4 +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 0x0000FFF0U + +/* +* SDRAM On-die Termination Output Enable (OE) Mode Selection. +*/ +#undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL +#undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT +#undef DDR_PHY_RIOCR5_ODTOEMODE_MASK +#define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 0 +#define DDR_PHY_RIOCR5_ODTOEMODE_MASK 0x0000000FU + +/* +* Address/Command Slew Rate (D3F I/O Only) +*/ +#undef DDR_PHY_ACIOCR0_ACSR_DEFVAL +#undef DDR_PHY_ACIOCR0_ACSR_SHIFT +#undef DDR_PHY_ACIOCR0_ACSR_MASK +#define DDR_PHY_ACIOCR0_ACSR_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACSR_SHIFT 30 +#define DDR_PHY_ACIOCR0_ACSR_MASK 0xC0000000U + +/* +* SDRAM Reset I/O Mode +*/ +#undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL +#undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT +#undef DDR_PHY_ACIOCR0_RSTIOM_MASK +#define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTIOM_SHIFT 29 +#define DDR_PHY_ACIOCR0_RSTIOM_MASK 0x20000000U + +/* +* SDRAM Reset Power Down Receiver +*/ +#undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL +#undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT +#undef DDR_PHY_ACIOCR0_RSTPDR_MASK +#define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTPDR_SHIFT 28 +#define DDR_PHY_ACIOCR0_RSTPDR_MASK 0x10000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL +#undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT +#undef DDR_PHY_ACIOCR0_RESERVED_27_MASK +#define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 27 +#define DDR_PHY_ACIOCR0_RESERVED_27_MASK 0x08000000U + +/* +* SDRAM Reset On-Die Termination +*/ +#undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL +#undef DDR_PHY_ACIOCR0_RSTODT_SHIFT +#undef DDR_PHY_ACIOCR0_RSTODT_MASK +#define DDR_PHY_ACIOCR0_RSTODT_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTODT_SHIFT 26 +#define DDR_PHY_ACIOCR0_RSTODT_MASK 0x04000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL +#undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT +#undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK +#define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 10 +#define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 0x03FFFC00U + +/* +* CK Duty Cycle Correction +*/ +#undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL +#undef DDR_PHY_ACIOCR0_CKDCC_SHIFT +#undef DDR_PHY_ACIOCR0_CKDCC_MASK +#define DDR_PHY_ACIOCR0_CKDCC_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_CKDCC_SHIFT 6 +#define DDR_PHY_ACIOCR0_CKDCC_MASK 0x000003C0U + +/* +* AC Power Down Receiver Mode +*/ +#undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL +#undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT +#undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK +#define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 4 +#define DDR_PHY_ACIOCR0_ACPDRMODE_MASK 0x00000030U + +/* +* AC On-die Termination Mode +*/ +#undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL +#undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT +#undef DDR_PHY_ACIOCR0_ACODTMODE_MASK +#define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 2 +#define DDR_PHY_ACIOCR0_ACODTMODE_MASK 0x0000000CU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL +#undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT +#undef DDR_PHY_ACIOCR0_RESERVED_1_MASK +#define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 1 +#define DDR_PHY_ACIOCR0_RESERVED_1_MASK 0x00000002U + +/* +* Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. +*/ +#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL +#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT +#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 0 +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 0x00000001U + +/* +* Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL + * slice +*/ +#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL +#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT +#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 31 +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 0x80000000U + +/* +* Clock gating for Output Enable D slices [0] +*/ +#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL +#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT +#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 30 +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 0x40000000U + +/* +* Clock gating for Power Down Receiver D slices [0] +*/ +#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL +#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT +#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 29 +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 0x20000000U + +/* +* Clock gating for Termination Enable D slices [0] +*/ +#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL +#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT +#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 28 +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 0x10000000U + +/* +* Clock gating for CK# D slices [1:0] +*/ +#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL +#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT +#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 26 +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 0x0C000000U + +/* +* Clock gating for CK D slices [1:0] +*/ +#undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL +#undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT +#undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK +#define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 24 +#define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 0x03000000U + +/* +* Clock gating for AC D slices [23:0] +*/ +#undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL +#undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT +#undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK +#define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 0 +#define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 0x00FFFFFFU + +/* +* SDRAM Parity Output Enable (OE) Mode Selection +*/ +#undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL +#undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT +#undef DDR_PHY_ACIOCR3_PAROEMODE_MASK +#define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 30 +#define DDR_PHY_ACIOCR3_PAROEMODE_MASK 0xC0000000U + +/* +* SDRAM Bank Group Output Enable (OE) Mode Selection +*/ +#undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL +#undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT +#undef DDR_PHY_ACIOCR3_BGOEMODE_MASK +#define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 26 +#define DDR_PHY_ACIOCR3_BGOEMODE_MASK 0x3C000000U + +/* +* SDRAM Bank Address Output Enable (OE) Mode Selection +*/ +#undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL +#undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT +#undef DDR_PHY_ACIOCR3_BAOEMODE_MASK +#define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 22 +#define DDR_PHY_ACIOCR3_BAOEMODE_MASK 0x03C00000U + +/* +* SDRAM A[17] Output Enable (OE) Mode Selection +*/ +#undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL +#undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT +#undef DDR_PHY_ACIOCR3_A17OEMODE_MASK +#define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 20 +#define DDR_PHY_ACIOCR3_A17OEMODE_MASK 0x00300000U + +/* +* SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection +*/ +#undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL +#undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT +#undef DDR_PHY_ACIOCR3_A16OEMODE_MASK +#define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 18 +#define DDR_PHY_ACIOCR3_A16OEMODE_MASK 0x000C0000U + +/* +* SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) +*/ +#undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL +#undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT +#undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK +#define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 16 +#define DDR_PHY_ACIOCR3_ACTOEMODE_MASK 0x00030000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL +#undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT +#undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK +#define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 8 +#define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 0x0000FF00U + +/* +* Reserved. Return zeros on reads. +*/ +#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL +#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT +#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 4 +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 0x000000F0U + +/* +* SDRAM CK Output Enable (OE) Mode Selection. +*/ +#undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL +#undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT +#undef DDR_PHY_ACIOCR3_CKOEMODE_MASK +#define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 0 +#define DDR_PHY_ACIOCR3_CKOEMODE_MASK 0x0000000FU + +/* +* Clock gating for AC LB slices and loopback read valid slices +*/ +#undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL +#undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT +#undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK +#define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 31 +#define DDR_PHY_ACIOCR4_LBCLKGATE_MASK 0x80000000U + +/* +* Clock gating for Output Enable D slices [1] +*/ +#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL +#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT +#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 30 +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 0x40000000U + +/* +* Clock gating for Power Down Receiver D slices [1] +*/ +#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL +#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT +#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 29 +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 0x20000000U + +/* +* Clock gating for Termination Enable D slices [1] +*/ +#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL +#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT +#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 28 +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 0x10000000U + +/* +* Clock gating for CK# D slices [3:2] +*/ +#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL +#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT +#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 26 +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 0x0C000000U + +/* +* Clock gating for CK D slices [3:2] +*/ +#undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL +#undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT +#undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK +#define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 24 +#define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 0x03000000U + +/* +* Clock gating for AC D slices [47:24] +*/ +#undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL +#undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT +#undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK +#define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 0 +#define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 0x00FFFFFFU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL +#undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT +#undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK +#define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_IOVCR0_RESERVED_31_29_MASK 0xE0000000U + +/* +* Address/command lane VREF Pad Enable +*/ +#undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT +#undef DDR_PHY_IOVCR0_ACREFPEN_MASK +#define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFPEN_SHIFT 28 +#define DDR_PHY_IOVCR0_ACREFPEN_MASK 0x10000000U + +/* +* Address/command lane Internal VREF Enable +*/ +#undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT +#undef DDR_PHY_IOVCR0_ACREFEEN_MASK +#define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFEEN_SHIFT 26 +#define DDR_PHY_IOVCR0_ACREFEEN_MASK 0x0C000000U + +/* +* Address/command lane Single-End VREF Enable +*/ +#undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT +#undef DDR_PHY_IOVCR0_ACREFSEN_MASK +#define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSEN_SHIFT 25 +#define DDR_PHY_IOVCR0_ACREFSEN_MASK 0x02000000U + +/* +* Address/command lane Internal VREF Enable +*/ +#undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT +#undef DDR_PHY_IOVCR0_ACREFIEN_MASK +#define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFIEN_SHIFT 24 +#define DDR_PHY_IOVCR0_ACREFIEN_MASK 0x01000000U + +/* +* External VREF generato REFSEL range select +*/ +#undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT +#undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK +#define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 23 +#define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 0x00800000U + +/* +* Address/command lane External VREF Select +*/ +#undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT +#undef DDR_PHY_IOVCR0_ACREFESEL_MASK +#define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFESEL_SHIFT 16 +#define DDR_PHY_IOVCR0_ACREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT +#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 15 +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 0x00008000U + +/* +* Address/command lane Single-End VREF Select +*/ +#undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT +#undef DDR_PHY_IOVCR0_ACREFSSEL_MASK +#define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 8 +#define DDR_PHY_IOVCR0_ACREFSSEL_MASK 0x00007F00U + +/* +* Internal VREF generator REFSEL ragne select +*/ +#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL +#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT +#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 7 +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 0x00000080U + +/* +* REFSEL Control for internal AC IOs +*/ +#undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL +#undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT +#undef DDR_PHY_IOVCR0_ACVREFISEL_MASK +#define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 0 +#define DDR_PHY_IOVCR0_ACVREFISEL_MASK 0x0000007FU + +/* +* Number of ctl_clk required to meet (> 150ns) timing requirements during + * DRAM DQ VREF training +*/ +#undef DDR_PHY_VTCR0_TVREF_DEFVAL +#undef DDR_PHY_VTCR0_TVREF_SHIFT +#undef DDR_PHY_VTCR0_TVREF_MASK +#define DDR_PHY_VTCR0_TVREF_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_TVREF_SHIFT 29 +#define DDR_PHY_VTCR0_TVREF_MASK 0xE0000000U + +/* +* DRM DQ VREF training Enable +*/ +#undef DDR_PHY_VTCR0_DVEN_DEFVAL +#undef DDR_PHY_VTCR0_DVEN_SHIFT +#undef DDR_PHY_VTCR0_DVEN_MASK +#define DDR_PHY_VTCR0_DVEN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVEN_SHIFT 28 +#define DDR_PHY_VTCR0_DVEN_MASK 0x10000000U + +/* +* Per Device Addressability Enable +*/ +#undef DDR_PHY_VTCR0_PDAEN_DEFVAL +#undef DDR_PHY_VTCR0_PDAEN_SHIFT +#undef DDR_PHY_VTCR0_PDAEN_MASK +#define DDR_PHY_VTCR0_PDAEN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_PDAEN_SHIFT 27 +#define DDR_PHY_VTCR0_PDAEN_MASK 0x08000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL +#undef DDR_PHY_VTCR0_RESERVED_26_SHIFT +#undef DDR_PHY_VTCR0_RESERVED_26_MASK +#define DDR_PHY_VTCR0_RESERVED_26_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_RESERVED_26_SHIFT 26 +#define DDR_PHY_VTCR0_RESERVED_26_MASK 0x04000000U + +/* +* VREF Word Count +*/ +#undef DDR_PHY_VTCR0_VWCR_DEFVAL +#undef DDR_PHY_VTCR0_VWCR_SHIFT +#undef DDR_PHY_VTCR0_VWCR_MASK +#define DDR_PHY_VTCR0_VWCR_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_VWCR_SHIFT 22 +#define DDR_PHY_VTCR0_VWCR_MASK 0x03C00000U + +/* +* DRAM DQ VREF step size used during DRAM VREF training +*/ +#undef DDR_PHY_VTCR0_DVSS_DEFVAL +#undef DDR_PHY_VTCR0_DVSS_SHIFT +#undef DDR_PHY_VTCR0_DVSS_MASK +#define DDR_PHY_VTCR0_DVSS_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVSS_SHIFT 18 +#define DDR_PHY_VTCR0_DVSS_MASK 0x003C0000U + +/* +* Maximum VREF limit value used during DRAM VREF training +*/ +#undef DDR_PHY_VTCR0_DVMAX_DEFVAL +#undef DDR_PHY_VTCR0_DVMAX_SHIFT +#undef DDR_PHY_VTCR0_DVMAX_MASK +#define DDR_PHY_VTCR0_DVMAX_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVMAX_SHIFT 12 +#define DDR_PHY_VTCR0_DVMAX_MASK 0x0003F000U + +/* +* Minimum VREF limit value used during DRAM VREF training +*/ +#undef DDR_PHY_VTCR0_DVMIN_DEFVAL +#undef DDR_PHY_VTCR0_DVMIN_SHIFT +#undef DDR_PHY_VTCR0_DVMIN_MASK +#define DDR_PHY_VTCR0_DVMIN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVMIN_SHIFT 6 +#define DDR_PHY_VTCR0_DVMIN_MASK 0x00000FC0U + +/* +* Initial DRAM DQ VREF value used during DRAM VREF training +*/ +#undef DDR_PHY_VTCR0_DVINIT_DEFVAL +#undef DDR_PHY_VTCR0_DVINIT_SHIFT +#undef DDR_PHY_VTCR0_DVINIT_MASK +#define DDR_PHY_VTCR0_DVINIT_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVINIT_SHIFT 0 +#define DDR_PHY_VTCR0_DVINIT_MASK 0x0000003FU + +/* +* Host VREF step size used during VREF training. The register value of N i + * ndicates step size of (N+1) +*/ +#undef DDR_PHY_VTCR1_HVSS_DEFVAL +#undef DDR_PHY_VTCR1_HVSS_SHIFT +#undef DDR_PHY_VTCR1_HVSS_MASK +#define DDR_PHY_VTCR1_HVSS_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVSS_SHIFT 28 +#define DDR_PHY_VTCR1_HVSS_MASK 0xF0000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL +#undef DDR_PHY_VTCR1_RESERVED_27_SHIFT +#undef DDR_PHY_VTCR1_RESERVED_27_MASK +#define DDR_PHY_VTCR1_RESERVED_27_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_27_SHIFT 27 +#define DDR_PHY_VTCR1_RESERVED_27_MASK 0x08000000U + +/* +* Maximum VREF limit value used during DRAM VREF training. +*/ +#undef DDR_PHY_VTCR1_HVMAX_DEFVAL +#undef DDR_PHY_VTCR1_HVMAX_SHIFT +#undef DDR_PHY_VTCR1_HVMAX_MASK +#define DDR_PHY_VTCR1_HVMAX_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVMAX_SHIFT 20 +#define DDR_PHY_VTCR1_HVMAX_MASK 0x07F00000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL +#undef DDR_PHY_VTCR1_RESERVED_19_SHIFT +#undef DDR_PHY_VTCR1_RESERVED_19_MASK +#define DDR_PHY_VTCR1_RESERVED_19_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_19_SHIFT 19 +#define DDR_PHY_VTCR1_RESERVED_19_MASK 0x00080000U + +/* +* Minimum VREF limit value used during DRAM VREF training. +*/ +#undef DDR_PHY_VTCR1_HVMIN_DEFVAL +#undef DDR_PHY_VTCR1_HVMIN_SHIFT +#undef DDR_PHY_VTCR1_HVMIN_MASK +#define DDR_PHY_VTCR1_HVMIN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVMIN_SHIFT 12 +#define DDR_PHY_VTCR1_HVMIN_MASK 0x0007F000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL +#undef DDR_PHY_VTCR1_RESERVED_11_SHIFT +#undef DDR_PHY_VTCR1_RESERVED_11_MASK +#define DDR_PHY_VTCR1_RESERVED_11_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_11_SHIFT 11 +#define DDR_PHY_VTCR1_RESERVED_11_MASK 0x00000800U + +/* +* Static Host Vref Rank Value +*/ +#undef DDR_PHY_VTCR1_SHRNK_DEFVAL +#undef DDR_PHY_VTCR1_SHRNK_SHIFT +#undef DDR_PHY_VTCR1_SHRNK_MASK +#define DDR_PHY_VTCR1_SHRNK_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_SHRNK_SHIFT 9 +#define DDR_PHY_VTCR1_SHRNK_MASK 0x00000600U + +/* +* Static Host Vref Rank Enable +*/ +#undef DDR_PHY_VTCR1_SHREN_DEFVAL +#undef DDR_PHY_VTCR1_SHREN_SHIFT +#undef DDR_PHY_VTCR1_SHREN_MASK +#define DDR_PHY_VTCR1_SHREN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_SHREN_SHIFT 8 +#define DDR_PHY_VTCR1_SHREN_MASK 0x00000100U + +/* +* Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir + * ements during Host IO VREF training +*/ +#undef DDR_PHY_VTCR1_TVREFIO_DEFVAL +#undef DDR_PHY_VTCR1_TVREFIO_SHIFT +#undef DDR_PHY_VTCR1_TVREFIO_MASK +#define DDR_PHY_VTCR1_TVREFIO_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_TVREFIO_SHIFT 5 +#define DDR_PHY_VTCR1_TVREFIO_MASK 0x000000E0U + +/* +* Eye LCDL Offset value for VREF training +*/ +#undef DDR_PHY_VTCR1_EOFF_DEFVAL +#undef DDR_PHY_VTCR1_EOFF_SHIFT +#undef DDR_PHY_VTCR1_EOFF_MASK +#define DDR_PHY_VTCR1_EOFF_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_EOFF_SHIFT 3 +#define DDR_PHY_VTCR1_EOFF_MASK 0x00000018U + +/* +* Number of LCDL Eye points for which VREF training is repeated +*/ +#undef DDR_PHY_VTCR1_ENUM_DEFVAL +#undef DDR_PHY_VTCR1_ENUM_SHIFT +#undef DDR_PHY_VTCR1_ENUM_MASK +#define DDR_PHY_VTCR1_ENUM_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_ENUM_SHIFT 2 +#define DDR_PHY_VTCR1_ENUM_MASK 0x00000004U + +/* +* HOST (IO) internal VREF training Enable +*/ +#undef DDR_PHY_VTCR1_HVEN_DEFVAL +#undef DDR_PHY_VTCR1_HVEN_SHIFT +#undef DDR_PHY_VTCR1_HVEN_MASK +#define DDR_PHY_VTCR1_HVEN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVEN_SHIFT 1 +#define DDR_PHY_VTCR1_HVEN_MASK 0x00000002U + +/* +* Host IO Type Control +*/ +#undef DDR_PHY_VTCR1_HVIO_DEFVAL +#undef DDR_PHY_VTCR1_HVIO_SHIFT +#undef DDR_PHY_VTCR1_HVIO_MASK +#define DDR_PHY_VTCR1_HVIO_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVIO_SHIFT 0 +#define DDR_PHY_VTCR1_HVIO_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL +#undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT +#undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK +#define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 0xC0000000U + +/* +* Delay select for the BDL on Parity. +*/ +#undef DDR_PHY_ACBDLR1_PARBD_DEFVAL +#undef DDR_PHY_ACBDLR1_PARBD_SHIFT +#undef DDR_PHY_ACBDLR1_PARBD_MASK +#define DDR_PHY_ACBDLR1_PARBD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_PARBD_SHIFT 24 +#define DDR_PHY_ACBDLR1_PARBD_MASK 0x3F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL +#undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT +#undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK +#define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 0x00C00000U + +/* +* Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn + * ected to WE. +*/ +#undef DDR_PHY_ACBDLR1_A16BD_DEFVAL +#undef DDR_PHY_ACBDLR1_A16BD_SHIFT +#undef DDR_PHY_ACBDLR1_A16BD_MASK +#define DDR_PHY_ACBDLR1_A16BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_A16BD_SHIFT 16 +#define DDR_PHY_ACBDLR1_A16BD_MASK 0x003F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL +#undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT +#undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK +#define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 0x0000C000U + +/* +* Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi + * s pin is connected to CAS. +*/ +#undef DDR_PHY_ACBDLR1_A17BD_DEFVAL +#undef DDR_PHY_ACBDLR1_A17BD_SHIFT +#undef DDR_PHY_ACBDLR1_A17BD_MASK +#define DDR_PHY_ACBDLR1_A17BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_A17BD_SHIFT 8 +#define DDR_PHY_ACBDLR1_A17BD_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL +#undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT +#undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK +#define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 0x000000C0U + +/* +* Delay select for the BDL on ACTN. +*/ +#undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL +#undef DDR_PHY_ACBDLR1_ACTBD_SHIFT +#undef DDR_PHY_ACBDLR1_ACTBD_MASK +#define DDR_PHY_ACBDLR1_ACTBD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_ACTBD_SHIFT 0 +#define DDR_PHY_ACBDLR1_ACTBD_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL +#undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT +#undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK +#define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 0xC0000000U + +/* +* Delay select for the BDL on BG[1]. +*/ +#undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL +#undef DDR_PHY_ACBDLR2_BG1BD_SHIFT +#undef DDR_PHY_ACBDLR2_BG1BD_MASK +#define DDR_PHY_ACBDLR2_BG1BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BG1BD_SHIFT 24 +#define DDR_PHY_ACBDLR2_BG1BD_MASK 0x3F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL +#undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT +#undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK +#define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 0x00C00000U + +/* +* Delay select for the BDL on BG[0]. +*/ +#undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL +#undef DDR_PHY_ACBDLR2_BG0BD_SHIFT +#undef DDR_PHY_ACBDLR2_BG0BD_MASK +#define DDR_PHY_ACBDLR2_BG0BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BG0BD_SHIFT 16 +#define DDR_PHY_ACBDLR2_BG0BD_MASK 0x003F0000U + +/* +* Reser.ved Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL +#undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT +#undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK +#define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 0x0000C000U + +/* +* Delay select for the BDL on BA[1]. +*/ +#undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL +#undef DDR_PHY_ACBDLR2_BA1BD_SHIFT +#undef DDR_PHY_ACBDLR2_BA1BD_MASK +#define DDR_PHY_ACBDLR2_BA1BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BA1BD_SHIFT 8 +#define DDR_PHY_ACBDLR2_BA1BD_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL +#undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT +#undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK +#define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 0x000000C0U + +/* +* Delay select for the BDL on BA[0]. +*/ +#undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL +#undef DDR_PHY_ACBDLR2_BA0BD_SHIFT +#undef DDR_PHY_ACBDLR2_BA0BD_MASK +#define DDR_PHY_ACBDLR2_BA0BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BA0BD_SHIFT 0 +#define DDR_PHY_ACBDLR2_BA0BD_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK +#define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* Delay select for the BDL on Address A[3]. +*/ +#undef DDR_PHY_ACBDLR6_A03BD_DEFVAL +#undef DDR_PHY_ACBDLR6_A03BD_SHIFT +#undef DDR_PHY_ACBDLR6_A03BD_MASK +#define DDR_PHY_ACBDLR6_A03BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A03BD_SHIFT 24 +#define DDR_PHY_ACBDLR6_A03BD_MASK 0x3F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK +#define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* Delay select for the BDL on Address A[2]. +*/ +#undef DDR_PHY_ACBDLR6_A02BD_DEFVAL +#undef DDR_PHY_ACBDLR6_A02BD_SHIFT +#undef DDR_PHY_ACBDLR6_A02BD_MASK +#define DDR_PHY_ACBDLR6_A02BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A02BD_SHIFT 16 +#define DDR_PHY_ACBDLR6_A02BD_MASK 0x003F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK +#define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* Delay select for the BDL on Address A[1]. +*/ +#undef DDR_PHY_ACBDLR6_A01BD_DEFVAL +#undef DDR_PHY_ACBDLR6_A01BD_SHIFT +#undef DDR_PHY_ACBDLR6_A01BD_MASK +#define DDR_PHY_ACBDLR6_A01BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A01BD_SHIFT 8 +#define DDR_PHY_ACBDLR6_A01BD_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK +#define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* Delay select for the BDL on Address A[0]. +*/ +#undef DDR_PHY_ACBDLR6_A00BD_DEFVAL +#undef DDR_PHY_ACBDLR6_A00BD_SHIFT +#undef DDR_PHY_ACBDLR6_A00BD_MASK +#define DDR_PHY_ACBDLR6_A00BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A00BD_SHIFT 0 +#define DDR_PHY_ACBDLR6_A00BD_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL +#undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT +#undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK +#define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 0xC0000000U + +/* +* Delay select for the BDL on Address A[7]. +*/ +#undef DDR_PHY_ACBDLR7_A07BD_DEFVAL +#undef DDR_PHY_ACBDLR7_A07BD_SHIFT +#undef DDR_PHY_ACBDLR7_A07BD_MASK +#define DDR_PHY_ACBDLR7_A07BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A07BD_SHIFT 24 +#define DDR_PHY_ACBDLR7_A07BD_MASK 0x3F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL +#undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT +#undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK +#define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 0x00C00000U + +/* +* Delay select for the BDL on Address A[6]. +*/ +#undef DDR_PHY_ACBDLR7_A06BD_DEFVAL +#undef DDR_PHY_ACBDLR7_A06BD_SHIFT +#undef DDR_PHY_ACBDLR7_A06BD_MASK +#define DDR_PHY_ACBDLR7_A06BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A06BD_SHIFT 16 +#define DDR_PHY_ACBDLR7_A06BD_MASK 0x003F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL +#undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT +#undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK +#define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 0x0000C000U + +/* +* Delay select for the BDL on Address A[5]. +*/ +#undef DDR_PHY_ACBDLR7_A05BD_DEFVAL +#undef DDR_PHY_ACBDLR7_A05BD_SHIFT +#undef DDR_PHY_ACBDLR7_A05BD_MASK +#define DDR_PHY_ACBDLR7_A05BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A05BD_SHIFT 8 +#define DDR_PHY_ACBDLR7_A05BD_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL +#undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT +#undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK +#define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 0x000000C0U + +/* +* Delay select for the BDL on Address A[4]. +*/ +#undef DDR_PHY_ACBDLR7_A04BD_DEFVAL +#undef DDR_PHY_ACBDLR7_A04BD_SHIFT +#undef DDR_PHY_ACBDLR7_A04BD_MASK +#define DDR_PHY_ACBDLR7_A04BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A04BD_SHIFT 0 +#define DDR_PHY_ACBDLR7_A04BD_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL +#undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT +#undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK +#define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 0xC0000000U + +/* +* Delay select for the BDL on Address A[11]. +*/ +#undef DDR_PHY_ACBDLR8_A11BD_DEFVAL +#undef DDR_PHY_ACBDLR8_A11BD_SHIFT +#undef DDR_PHY_ACBDLR8_A11BD_MASK +#define DDR_PHY_ACBDLR8_A11BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A11BD_SHIFT 24 +#define DDR_PHY_ACBDLR8_A11BD_MASK 0x3F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL +#undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT +#undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK +#define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 0x00C00000U + +/* +* Delay select for the BDL on Address A[10]. +*/ +#undef DDR_PHY_ACBDLR8_A10BD_DEFVAL +#undef DDR_PHY_ACBDLR8_A10BD_SHIFT +#undef DDR_PHY_ACBDLR8_A10BD_MASK +#define DDR_PHY_ACBDLR8_A10BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A10BD_SHIFT 16 +#define DDR_PHY_ACBDLR8_A10BD_MASK 0x003F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL +#undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT +#undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK +#define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 0x0000C000U + +/* +* Delay select for the BDL on Address A[9]. +*/ +#undef DDR_PHY_ACBDLR8_A09BD_DEFVAL +#undef DDR_PHY_ACBDLR8_A09BD_SHIFT +#undef DDR_PHY_ACBDLR8_A09BD_MASK +#define DDR_PHY_ACBDLR8_A09BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A09BD_SHIFT 8 +#define DDR_PHY_ACBDLR8_A09BD_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL +#undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT +#undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK +#define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 0x000000C0U + +/* +* Delay select for the BDL on Address A[8]. +*/ +#undef DDR_PHY_ACBDLR8_A08BD_DEFVAL +#undef DDR_PHY_ACBDLR8_A08BD_SHIFT +#undef DDR_PHY_ACBDLR8_A08BD_MASK +#define DDR_PHY_ACBDLR8_A08BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A08BD_SHIFT 0 +#define DDR_PHY_ACBDLR8_A08BD_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL +#undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT +#undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK +#define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 0xC0000000U + +/* +* Delay select for the BDL on Address A[15]. +*/ +#undef DDR_PHY_ACBDLR9_A15BD_DEFVAL +#undef DDR_PHY_ACBDLR9_A15BD_SHIFT +#undef DDR_PHY_ACBDLR9_A15BD_MASK +#define DDR_PHY_ACBDLR9_A15BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A15BD_SHIFT 24 +#define DDR_PHY_ACBDLR9_A15BD_MASK 0x3F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL +#undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT +#undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK +#define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 0x00C00000U + +/* +* Delay select for the BDL on Address A[14]. +*/ +#undef DDR_PHY_ACBDLR9_A14BD_DEFVAL +#undef DDR_PHY_ACBDLR9_A14BD_SHIFT +#undef DDR_PHY_ACBDLR9_A14BD_MASK +#define DDR_PHY_ACBDLR9_A14BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A14BD_SHIFT 16 +#define DDR_PHY_ACBDLR9_A14BD_MASK 0x003F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL +#undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT +#undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK +#define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 0x0000C000U + +/* +* Delay select for the BDL on Address A[13]. +*/ +#undef DDR_PHY_ACBDLR9_A13BD_DEFVAL +#undef DDR_PHY_ACBDLR9_A13BD_SHIFT +#undef DDR_PHY_ACBDLR9_A13BD_MASK +#define DDR_PHY_ACBDLR9_A13BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A13BD_SHIFT 8 +#define DDR_PHY_ACBDLR9_A13BD_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL +#undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT +#undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK +#define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 0x000000C0U + +/* +* Delay select for the BDL on Address A[12]. +*/ +#undef DDR_PHY_ACBDLR9_A12BD_DEFVAL +#undef DDR_PHY_ACBDLR9_A12BD_SHIFT +#undef DDR_PHY_ACBDLR9_A12BD_MASK +#define DDR_PHY_ACBDLR9_A12BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A12BD_SHIFT 0 +#define DDR_PHY_ACBDLR9_A12BD_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL +#undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT +#undef DDR_PHY_ZQCR_RESERVED_31_26_MASK +#define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQCR_RESERVED_31_26_MASK 0xFC000000U + +/* +* ZQ VREF Range +*/ +#undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL +#undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT +#undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK +#define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 25 +#define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 0x02000000U + +/* +* Programmable Wait for Frequency B +*/ +#undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL +#undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT +#undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK +#define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 19 +#define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 0x01F80000U + +/* +* Programmable Wait for Frequency A +*/ +#undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL +#undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT +#undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK +#define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 13 +#define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 0x0007E000U + +/* +* ZQ VREF Pad Enable +*/ +#undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL +#undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT +#undef DDR_PHY_ZQCR_ZQREFPEN_MASK +#define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFPEN_SHIFT 12 +#define DDR_PHY_ZQCR_ZQREFPEN_MASK 0x00001000U + +/* +* ZQ Internal VREF Enable +*/ +#undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL +#undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT +#undef DDR_PHY_ZQCR_ZQREFIEN_MASK +#define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFIEN_SHIFT 11 +#define DDR_PHY_ZQCR_ZQREFIEN_MASK 0x00000800U + +/* +* Choice of termination mode +*/ +#undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL +#undef DDR_PHY_ZQCR_ODT_MODE_SHIFT +#undef DDR_PHY_ZQCR_ODT_MODE_MASK +#define DDR_PHY_ZQCR_ODT_MODE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ODT_MODE_SHIFT 9 +#define DDR_PHY_ZQCR_ODT_MODE_MASK 0x00000600U + +/* +* Force ZCAL VT update +*/ +#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL +#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT +#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 8 +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 0x00000100U + +/* +* IO VT Drift Limit +*/ +#undef DDR_PHY_ZQCR_IODLMT_DEFVAL +#undef DDR_PHY_ZQCR_IODLMT_SHIFT +#undef DDR_PHY_ZQCR_IODLMT_MASK +#define DDR_PHY_ZQCR_IODLMT_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_IODLMT_SHIFT 5 +#define DDR_PHY_ZQCR_IODLMT_MASK 0x000000E0U + +/* +* Averaging algorithm enable, if set, enables averaging algorithm +*/ +#undef DDR_PHY_ZQCR_AVGEN_DEFVAL +#undef DDR_PHY_ZQCR_AVGEN_SHIFT +#undef DDR_PHY_ZQCR_AVGEN_MASK +#define DDR_PHY_ZQCR_AVGEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_AVGEN_SHIFT 4 +#define DDR_PHY_ZQCR_AVGEN_MASK 0x00000010U + +/* +* Maximum number of averaging rounds to be used by averaging algorithm +*/ +#undef DDR_PHY_ZQCR_AVGMAX_DEFVAL +#undef DDR_PHY_ZQCR_AVGMAX_SHIFT +#undef DDR_PHY_ZQCR_AVGMAX_MASK +#define DDR_PHY_ZQCR_AVGMAX_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_AVGMAX_SHIFT 2 +#define DDR_PHY_ZQCR_AVGMAX_MASK 0x0000000CU + +/* +* ZQ Calibration Type +*/ +#undef DDR_PHY_ZQCR_ZCALT_DEFVAL +#undef DDR_PHY_ZQCR_ZCALT_SHIFT +#undef DDR_PHY_ZQCR_ZCALT_MASK +#define DDR_PHY_ZQCR_ZCALT_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZCALT_SHIFT 1 +#define DDR_PHY_ZQCR_ZCALT_MASK 0x00000002U + +/* +* ZQ Power Down +*/ +#undef DDR_PHY_ZQCR_ZQPD_DEFVAL +#undef DDR_PHY_ZQCR_ZQPD_SHIFT +#undef DDR_PHY_ZQCR_ZQPD_MASK +#define DDR_PHY_ZQCR_ZQPD_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQPD_SHIFT 0 +#define DDR_PHY_ZQCR_ZQPD_MASK 0x00000001U + +/* +* Pull-down drive strength ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL +#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT +#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 31 +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 0x80000000U + +/* +* Pull-up drive strength ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL +#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT +#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 30 +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 0x40000000U + +/* +* Pull-down termination ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL +#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT +#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 29 +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 0x20000000U + +/* +* Pull-up termination ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL +#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT +#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 28 +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 0x10000000U + +/* +* Calibration segment bypass +*/ +#undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL +#undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT +#undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK +#define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 27 +#define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 0x08000000U + +/* +* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB +*/ +#undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL +#undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT +#undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK +#define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 25 +#define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 0x06000000U + +/* +* Termination adjustment +*/ +#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL +#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT +#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 22 +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 0x01C00000U + +/* +* Pulldown drive strength adjustment +*/ +#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL +#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT +#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 19 +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 0x00380000U + +/* +* Pullup drive strength adjustment +*/ +#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL +#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT +#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 16 +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 0x00070000U + +/* +* DRAM Impedance Divide Ratio +*/ +#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL +#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT +#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 12 +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U + +/* +* HOST Impedance Divide Ratio +*/ +#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL +#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT +#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 8 +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 0x00000F00U + +/* +* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) +*/ +#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL +#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT +#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U + +/* +* Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) +*/ +#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL +#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT +#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU + +/* +* Reserved. Return zeros on reads. +*/ +#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL +#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT +#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 0xFC000000U + +/* +* Override value for the pull-up output impedance +*/ +#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL +#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT +#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 16 +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 0x03FF0000U + +/* +* Reserved. Return zeros on reads. +*/ +#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL +#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT +#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 0x0000FC00U + +/* +* Override value for the pull-down output impedance +*/ +#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL +#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT +#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 0 +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 0x000003FFU + +/* +* Reserved. Return zeros on reads. +*/ +#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL +#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT +#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 0xFC000000U + +/* +* Override value for the pull-up termination +*/ +#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL +#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT +#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 16 +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 0x03FF0000U + +/* +* Reserved. Return zeros on reads. +*/ +#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL +#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT +#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 0x0000FC00U + +/* +* Override value for the pull-down termination +*/ +#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL +#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT +#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 0 +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 0x000003FFU + +/* +* Pull-down drive strength ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL +#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT +#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 31 +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 0x80000000U + +/* +* Pull-up drive strength ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL +#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT +#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 30 +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 0x40000000U + +/* +* Pull-down termination ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL +#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT +#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 29 +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 0x20000000U + +/* +* Pull-up termination ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL +#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT +#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 28 +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 0x10000000U + +/* +* Calibration segment bypass +*/ +#undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL +#undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT +#undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK +#define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 27 +#define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 0x08000000U + +/* +* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB +*/ +#undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL +#undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT +#undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK +#define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 25 +#define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 0x06000000U + +/* +* Termination adjustment +*/ +#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL +#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT +#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 22 +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 0x01C00000U + +/* +* Pulldown drive strength adjustment +*/ +#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL +#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT +#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 19 +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 0x00380000U + +/* +* Pullup drive strength adjustment +*/ +#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL +#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT +#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 16 +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 0x00070000U + +/* +* DRAM Impedance Divide Ratio +*/ +#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL +#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT +#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 12 +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U + +/* +* HOST Impedance Divide Ratio +*/ +#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL +#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT +#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 8 +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 0x00000F00U + +/* +* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) +*/ +#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL +#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT +#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U + +/* +* Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) +*/ +#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL +#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT +#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX0GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX0GCR0_CALBYP_MASK +#define DDR_PHY_DX0GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX0GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX0GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX0GCR0_MDLEN_MASK +#define DDR_PHY_DX0GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX0GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX0GCR0_CODTSHFT_MASK +#define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX0GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX0GCR0_DQSDCC_MASK +#define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX0GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX0GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX0GCR0_RDDLY_MASK +#define DDR_PHY_DX0GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX0GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX0GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX0GCR0_RTTOAL_MASK +#define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX0GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX0GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX0GCR0_RTTOH_MASK +#define DDR_PHY_DX0GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX0GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX0GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX0GCR0_DQSRPD_MASK +#define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX0GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX0GCR0_DQSGPDR_MASK +#define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX0GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX0GCR0_RESERVED_4_MASK +#define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX0GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX0GCR0_DQSGODT_MASK +#define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX0GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX0GCR0_DQSGOE_MASK +#define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX0GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX0GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX0GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX0GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX0GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX0GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX0GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX0GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX0GCR1_RESERVED_15_MASK +#define DDR_PHY_DX0GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX0GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX0GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX0GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX0GCR1_QSNSEL_MASK +#define DDR_PHY_DX0GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX0GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX0GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX0GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX0GCR1_QSSEL_MASK +#define DDR_PHY_DX0GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX0GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX0GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX0GCR1_OEEN_SHIFT +#undef DDR_PHY_DX0GCR1_OEEN_MASK +#define DDR_PHY_DX0GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX0GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX0GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX0GCR1_PDREN_SHIFT +#undef DDR_PHY_DX0GCR1_PDREN_MASK +#define DDR_PHY_DX0GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX0GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX0GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX0GCR1_TEEN_SHIFT +#undef DDR_PHY_DX0GCR1_TEEN_MASK +#define DDR_PHY_DX0GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX0GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX0GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX0GCR1_DSEN_SHIFT +#undef DDR_PHY_DX0GCR1_DSEN_MASK +#define DDR_PHY_DX0GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX0GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX0GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX0GCR1_DMEN_SHIFT +#undef DDR_PHY_DX0GCR1_DMEN_MASK +#define DDR_PHY_DX0GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX0GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX0GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX0GCR1_DQEN_SHIFT +#undef DDR_PHY_DX0GCR1_DQEN_MASK +#define DDR_PHY_DX0GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX0GCR1_DQEN_MASK 0x000000FFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX0GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX0GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX0GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX0GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX0GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX0GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX0GCR3_RDBVT_MASK +#define DDR_PHY_DX0GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX0GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX0GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX0GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX0GCR3_WDBVT_MASK +#define DDR_PHY_DX0GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX0GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX0GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX0GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX0GCR3_RGLVT_MASK +#define DDR_PHY_DX0GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX0GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX0GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX0GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX0GCR3_RDLVT_MASK +#define DDR_PHY_DX0GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX0GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX0GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX0GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX0GCR3_WDLVT_MASK +#define DDR_PHY_DX0GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX0GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX0GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX0GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX0GCR3_WLLVT_MASK +#define DDR_PHY_DX0GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX0GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX0GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX0GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX0GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX0GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX0GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX0GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX0GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX0GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX0GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX0GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX0GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX0GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX0GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX0GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX0GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DMOEMODE_MASK +#define DDR_PHY_DX0GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX0GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX0GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DMTEMODE_MASK +#define DDR_PHY_DX0GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX0GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX0GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX0GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX0GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX0GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX0GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX0GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX0GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX0GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX0GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DSOEMODE_MASK +#define DDR_PHY_DX0GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX0GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX0GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DSTEMODE_MASK +#define DDR_PHY_DX0GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX0GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX0GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX0GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX0GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX0GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX0GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX0GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX0GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX0GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFPEN_MASK +#define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX0GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFEEN_MASK +#define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX0GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFSEN_MASK +#define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX0GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX0GCR4_RESERVED_24_MASK +#define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX0GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFESEL_MASK +#define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX0GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX0GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFIEN_MASK +#define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX0GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFIMON_MASK +#define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX0GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX0GCR5_RESERVED_31_MASK +#define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX0GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX0GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX0GCR5_RESERVED_23_MASK +#define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX0GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX0GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX0GCR5_RESERVED_15_MASK +#define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX0GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX0GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX0GCR5_RESERVED_7_MASK +#define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX0GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX0GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX1GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX1GCR0_CALBYP_MASK +#define DDR_PHY_DX1GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX1GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX1GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX1GCR0_MDLEN_MASK +#define DDR_PHY_DX1GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX1GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX1GCR0_CODTSHFT_MASK +#define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX1GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX1GCR0_DQSDCC_MASK +#define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX1GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX1GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX1GCR0_RDDLY_MASK +#define DDR_PHY_DX1GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX1GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX1GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX1GCR0_RTTOAL_MASK +#define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX1GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX1GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX1GCR0_RTTOH_MASK +#define DDR_PHY_DX1GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX1GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX1GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX1GCR0_DQSRPD_MASK +#define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX1GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX1GCR0_DQSGPDR_MASK +#define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX1GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX1GCR0_RESERVED_4_MASK +#define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX1GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX1GCR0_DQSGODT_MASK +#define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX1GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX1GCR0_DQSGOE_MASK +#define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX1GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX1GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX1GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX1GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX1GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX1GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX1GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX1GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX1GCR1_RESERVED_15_MASK +#define DDR_PHY_DX1GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX1GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX1GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX1GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX1GCR1_QSNSEL_MASK +#define DDR_PHY_DX1GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX1GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX1GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX1GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX1GCR1_QSSEL_MASK +#define DDR_PHY_DX1GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX1GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX1GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX1GCR1_OEEN_SHIFT +#undef DDR_PHY_DX1GCR1_OEEN_MASK +#define DDR_PHY_DX1GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX1GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX1GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX1GCR1_PDREN_SHIFT +#undef DDR_PHY_DX1GCR1_PDREN_MASK +#define DDR_PHY_DX1GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX1GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX1GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX1GCR1_TEEN_SHIFT +#undef DDR_PHY_DX1GCR1_TEEN_MASK +#define DDR_PHY_DX1GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX1GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX1GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX1GCR1_DSEN_SHIFT +#undef DDR_PHY_DX1GCR1_DSEN_MASK +#define DDR_PHY_DX1GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX1GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX1GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX1GCR1_DMEN_SHIFT +#undef DDR_PHY_DX1GCR1_DMEN_MASK +#define DDR_PHY_DX1GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX1GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX1GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX1GCR1_DQEN_SHIFT +#undef DDR_PHY_DX1GCR1_DQEN_MASK +#define DDR_PHY_DX1GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX1GCR1_DQEN_MASK 0x000000FFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX1GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX1GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX1GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX1GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX1GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX1GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX1GCR3_RDBVT_MASK +#define DDR_PHY_DX1GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX1GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX1GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX1GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX1GCR3_WDBVT_MASK +#define DDR_PHY_DX1GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX1GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX1GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX1GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX1GCR3_RGLVT_MASK +#define DDR_PHY_DX1GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX1GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX1GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX1GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX1GCR3_RDLVT_MASK +#define DDR_PHY_DX1GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX1GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX1GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX1GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX1GCR3_WDLVT_MASK +#define DDR_PHY_DX1GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX1GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX1GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX1GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX1GCR3_WLLVT_MASK +#define DDR_PHY_DX1GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX1GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX1GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX1GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX1GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX1GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX1GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX1GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX1GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX1GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX1GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX1GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX1GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX1GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX1GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX1GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX1GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DMOEMODE_MASK +#define DDR_PHY_DX1GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX1GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX1GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DMTEMODE_MASK +#define DDR_PHY_DX1GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX1GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX1GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX1GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX1GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX1GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX1GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX1GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX1GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX1GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX1GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DSOEMODE_MASK +#define DDR_PHY_DX1GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX1GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX1GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DSTEMODE_MASK +#define DDR_PHY_DX1GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX1GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX1GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX1GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX1GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX1GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX1GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX1GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX1GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX1GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFPEN_MASK +#define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX1GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFEEN_MASK +#define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX1GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFSEN_MASK +#define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX1GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX1GCR4_RESERVED_24_MASK +#define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX1GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFESEL_MASK +#define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX1GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX1GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFIEN_MASK +#define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX1GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFIMON_MASK +#define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX1GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX1GCR5_RESERVED_31_MASK +#define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX1GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX1GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX1GCR5_RESERVED_23_MASK +#define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX1GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX1GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX1GCR5_RESERVED_15_MASK +#define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX1GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX1GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX1GCR5_RESERVED_7_MASK +#define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX1GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX1GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX2GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX2GCR0_CALBYP_MASK +#define DDR_PHY_DX2GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX2GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX2GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX2GCR0_MDLEN_MASK +#define DDR_PHY_DX2GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX2GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX2GCR0_CODTSHFT_MASK +#define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX2GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX2GCR0_DQSDCC_MASK +#define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX2GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX2GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX2GCR0_RDDLY_MASK +#define DDR_PHY_DX2GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX2GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX2GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX2GCR0_RTTOAL_MASK +#define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX2GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX2GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX2GCR0_RTTOH_MASK +#define DDR_PHY_DX2GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX2GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX2GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX2GCR0_DQSRPD_MASK +#define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX2GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX2GCR0_DQSGPDR_MASK +#define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX2GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX2GCR0_RESERVED_4_MASK +#define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX2GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX2GCR0_DQSGODT_MASK +#define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX2GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX2GCR0_DQSGOE_MASK +#define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX2GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX2GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX2GCR1_RESERVED_15_MASK +#define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX2GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX2GCR1_QSNSEL_MASK +#define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX2GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX2GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX2GCR1_QSSEL_MASK +#define DDR_PHY_DX2GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX2GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX2GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX2GCR1_OEEN_SHIFT +#undef DDR_PHY_DX2GCR1_OEEN_MASK +#define DDR_PHY_DX2GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX2GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX2GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX2GCR1_PDREN_SHIFT +#undef DDR_PHY_DX2GCR1_PDREN_MASK +#define DDR_PHY_DX2GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX2GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX2GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX2GCR1_TEEN_SHIFT +#undef DDR_PHY_DX2GCR1_TEEN_MASK +#define DDR_PHY_DX2GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX2GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX2GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX2GCR1_DSEN_SHIFT +#undef DDR_PHY_DX2GCR1_DSEN_MASK +#define DDR_PHY_DX2GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX2GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX2GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX2GCR1_DMEN_SHIFT +#undef DDR_PHY_DX2GCR1_DMEN_MASK +#define DDR_PHY_DX2GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX2GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX2GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX2GCR1_DQEN_SHIFT +#undef DDR_PHY_DX2GCR1_DQEN_MASK +#define DDR_PHY_DX2GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX2GCR1_DQEN_MASK 0x000000FFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX2GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX2GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX2GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX2GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX2GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX2GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX2GCR3_RDBVT_MASK +#define DDR_PHY_DX2GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX2GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX2GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX2GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX2GCR3_WDBVT_MASK +#define DDR_PHY_DX2GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX2GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX2GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX2GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX2GCR3_RGLVT_MASK +#define DDR_PHY_DX2GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX2GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX2GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX2GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX2GCR3_RDLVT_MASK +#define DDR_PHY_DX2GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX2GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX2GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX2GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX2GCR3_WDLVT_MASK +#define DDR_PHY_DX2GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX2GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX2GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX2GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX2GCR3_WLLVT_MASK +#define DDR_PHY_DX2GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX2GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX2GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX2GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX2GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX2GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX2GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX2GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX2GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX2GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX2GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX2GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX2GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX2GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX2GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX2GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX2GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DMOEMODE_MASK +#define DDR_PHY_DX2GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX2GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX2GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DMTEMODE_MASK +#define DDR_PHY_DX2GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX2GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX2GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX2GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX2GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX2GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX2GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX2GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX2GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX2GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX2GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DSOEMODE_MASK +#define DDR_PHY_DX2GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX2GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX2GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DSTEMODE_MASK +#define DDR_PHY_DX2GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX2GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX2GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX2GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX2GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX2GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX2GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX2GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX2GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX2GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFPEN_MASK +#define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX2GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFEEN_MASK +#define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX2GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFSEN_MASK +#define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX2GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX2GCR4_RESERVED_24_MASK +#define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX2GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFESEL_MASK +#define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX2GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX2GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFIEN_MASK +#define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX2GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFIMON_MASK +#define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX2GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX2GCR5_RESERVED_31_MASK +#define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX2GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX2GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX2GCR5_RESERVED_23_MASK +#define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX2GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX2GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX2GCR5_RESERVED_15_MASK +#define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX2GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX2GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX2GCR5_RESERVED_7_MASK +#define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX2GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX2GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX3GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX3GCR0_CALBYP_MASK +#define DDR_PHY_DX3GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX3GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX3GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX3GCR0_MDLEN_MASK +#define DDR_PHY_DX3GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX3GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX3GCR0_CODTSHFT_MASK +#define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX3GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX3GCR0_DQSDCC_MASK +#define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX3GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX3GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX3GCR0_RDDLY_MASK +#define DDR_PHY_DX3GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX3GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX3GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX3GCR0_RTTOAL_MASK +#define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX3GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX3GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX3GCR0_RTTOH_MASK +#define DDR_PHY_DX3GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX3GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX3GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX3GCR0_DQSRPD_MASK +#define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX3GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX3GCR0_DQSGPDR_MASK +#define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX3GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX3GCR0_RESERVED_4_MASK +#define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX3GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX3GCR0_DQSGODT_MASK +#define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX3GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX3GCR0_DQSGOE_MASK +#define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX3GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX3GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX3GCR1_RESERVED_15_MASK +#define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX3GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX3GCR1_QSNSEL_MASK +#define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX3GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX3GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX3GCR1_QSSEL_MASK +#define DDR_PHY_DX3GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX3GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX3GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX3GCR1_OEEN_SHIFT +#undef DDR_PHY_DX3GCR1_OEEN_MASK +#define DDR_PHY_DX3GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX3GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX3GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX3GCR1_PDREN_SHIFT +#undef DDR_PHY_DX3GCR1_PDREN_MASK +#define DDR_PHY_DX3GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX3GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX3GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX3GCR1_TEEN_SHIFT +#undef DDR_PHY_DX3GCR1_TEEN_MASK +#define DDR_PHY_DX3GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX3GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX3GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX3GCR1_DSEN_SHIFT +#undef DDR_PHY_DX3GCR1_DSEN_MASK +#define DDR_PHY_DX3GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX3GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX3GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX3GCR1_DMEN_SHIFT +#undef DDR_PHY_DX3GCR1_DMEN_MASK +#define DDR_PHY_DX3GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX3GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX3GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX3GCR1_DQEN_SHIFT +#undef DDR_PHY_DX3GCR1_DQEN_MASK +#define DDR_PHY_DX3GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX3GCR1_DQEN_MASK 0x000000FFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX3GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX3GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX3GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX3GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX3GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX3GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX3GCR3_RDBVT_MASK +#define DDR_PHY_DX3GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX3GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX3GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX3GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX3GCR3_WDBVT_MASK +#define DDR_PHY_DX3GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX3GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX3GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX3GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX3GCR3_RGLVT_MASK +#define DDR_PHY_DX3GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX3GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX3GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX3GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX3GCR3_RDLVT_MASK +#define DDR_PHY_DX3GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX3GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX3GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX3GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX3GCR3_WDLVT_MASK +#define DDR_PHY_DX3GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX3GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX3GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX3GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX3GCR3_WLLVT_MASK +#define DDR_PHY_DX3GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX3GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX3GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX3GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX3GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX3GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX3GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX3GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX3GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX3GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX3GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX3GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX3GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX3GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX3GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX3GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX3GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DMOEMODE_MASK +#define DDR_PHY_DX3GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX3GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX3GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DMTEMODE_MASK +#define DDR_PHY_DX3GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX3GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX3GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX3GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX3GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX3GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX3GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX3GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX3GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX3GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX3GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DSOEMODE_MASK +#define DDR_PHY_DX3GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX3GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX3GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DSTEMODE_MASK +#define DDR_PHY_DX3GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX3GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX3GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX3GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX3GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX3GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX3GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX3GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX3GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX3GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFPEN_MASK +#define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX3GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFEEN_MASK +#define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX3GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFSEN_MASK +#define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX3GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX3GCR4_RESERVED_24_MASK +#define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX3GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFESEL_MASK +#define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX3GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX3GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFIEN_MASK +#define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX3GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFIMON_MASK +#define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX3GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX3GCR5_RESERVED_31_MASK +#define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX3GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX3GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX3GCR5_RESERVED_23_MASK +#define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX3GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX3GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX3GCR5_RESERVED_15_MASK +#define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX3GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX3GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX3GCR5_RESERVED_7_MASK +#define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX3GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX3GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX4GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX4GCR0_CALBYP_MASK +#define DDR_PHY_DX4GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX4GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX4GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX4GCR0_MDLEN_MASK +#define DDR_PHY_DX4GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX4GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX4GCR0_CODTSHFT_MASK +#define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX4GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX4GCR0_DQSDCC_MASK +#define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX4GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX4GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX4GCR0_RDDLY_MASK +#define DDR_PHY_DX4GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX4GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX4GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX4GCR0_RTTOAL_MASK +#define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX4GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX4GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX4GCR0_RTTOH_MASK +#define DDR_PHY_DX4GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX4GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX4GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX4GCR0_DQSRPD_MASK +#define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX4GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX4GCR0_DQSGPDR_MASK +#define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX4GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX4GCR0_RESERVED_4_MASK +#define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX4GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX4GCR0_DQSGODT_MASK +#define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX4GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX4GCR0_DQSGOE_MASK +#define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX4GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX4GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX4GCR1_RESERVED_15_MASK +#define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX4GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX4GCR1_QSNSEL_MASK +#define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX4GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX4GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX4GCR1_QSSEL_MASK +#define DDR_PHY_DX4GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX4GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX4GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX4GCR1_OEEN_SHIFT +#undef DDR_PHY_DX4GCR1_OEEN_MASK +#define DDR_PHY_DX4GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX4GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX4GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX4GCR1_PDREN_SHIFT +#undef DDR_PHY_DX4GCR1_PDREN_MASK +#define DDR_PHY_DX4GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX4GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX4GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX4GCR1_TEEN_SHIFT +#undef DDR_PHY_DX4GCR1_TEEN_MASK +#define DDR_PHY_DX4GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX4GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX4GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX4GCR1_DSEN_SHIFT +#undef DDR_PHY_DX4GCR1_DSEN_MASK +#define DDR_PHY_DX4GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX4GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX4GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX4GCR1_DMEN_SHIFT +#undef DDR_PHY_DX4GCR1_DMEN_MASK +#define DDR_PHY_DX4GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX4GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX4GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX4GCR1_DQEN_SHIFT +#undef DDR_PHY_DX4GCR1_DQEN_MASK +#define DDR_PHY_DX4GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX4GCR1_DQEN_MASK 0x000000FFU + +/* +* Enables the OE mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX4GCR2_DXOEMODE_DEFVAL +#undef DDR_PHY_DX4GCR2_DXOEMODE_SHIFT +#undef DDR_PHY_DX4GCR2_DXOEMODE_MASK +#define DDR_PHY_DX4GCR2_DXOEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX4GCR2_DXOEMODE_SHIFT 16 +#define DDR_PHY_DX4GCR2_DXOEMODE_MASK 0xFFFF0000U + +/* +* Enables the TE (ODT) mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX4GCR2_DXTEMODE_DEFVAL +#undef DDR_PHY_DX4GCR2_DXTEMODE_SHIFT +#undef DDR_PHY_DX4GCR2_DXTEMODE_MASK +#define DDR_PHY_DX4GCR2_DXTEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX4GCR2_DXTEMODE_SHIFT 0 +#define DDR_PHY_DX4GCR2_DXTEMODE_MASK 0x0000FFFFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX4GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX4GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX4GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX4GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX4GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX4GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX4GCR3_RDBVT_MASK +#define DDR_PHY_DX4GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX4GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX4GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX4GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX4GCR3_WDBVT_MASK +#define DDR_PHY_DX4GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX4GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX4GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX4GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX4GCR3_RGLVT_MASK +#define DDR_PHY_DX4GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX4GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX4GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX4GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX4GCR3_RDLVT_MASK +#define DDR_PHY_DX4GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX4GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX4GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX4GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX4GCR3_WDLVT_MASK +#define DDR_PHY_DX4GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX4GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX4GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX4GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX4GCR3_WLLVT_MASK +#define DDR_PHY_DX4GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX4GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX4GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX4GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX4GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX4GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX4GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX4GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX4GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX4GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX4GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX4GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX4GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX4GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX4GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX4GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX4GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DMOEMODE_MASK +#define DDR_PHY_DX4GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX4GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX4GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DMTEMODE_MASK +#define DDR_PHY_DX4GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX4GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX4GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX4GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX4GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX4GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX4GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX4GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX4GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX4GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX4GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DSOEMODE_MASK +#define DDR_PHY_DX4GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX4GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX4GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DSTEMODE_MASK +#define DDR_PHY_DX4GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX4GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX4GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX4GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX4GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX4GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX4GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX4GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX4GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX4GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFPEN_MASK +#define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX4GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFEEN_MASK +#define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX4GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFSEN_MASK +#define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX4GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX4GCR4_RESERVED_24_MASK +#define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX4GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFESEL_MASK +#define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX4GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX4GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFIEN_MASK +#define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX4GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFIMON_MASK +#define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX4GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX4GCR5_RESERVED_31_MASK +#define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX4GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX4GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX4GCR5_RESERVED_23_MASK +#define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX4GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX4GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX4GCR5_RESERVED_15_MASK +#define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX4GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX4GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX4GCR5_RESERVED_7_MASK +#define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX4GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX4GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX5GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX5GCR0_CALBYP_MASK +#define DDR_PHY_DX5GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX5GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX5GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX5GCR0_MDLEN_MASK +#define DDR_PHY_DX5GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX5GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX5GCR0_CODTSHFT_MASK +#define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX5GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX5GCR0_DQSDCC_MASK +#define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX5GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX5GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX5GCR0_RDDLY_MASK +#define DDR_PHY_DX5GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX5GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX5GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX5GCR0_RTTOAL_MASK +#define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX5GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX5GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX5GCR0_RTTOH_MASK +#define DDR_PHY_DX5GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX5GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX5GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX5GCR0_DQSRPD_MASK +#define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX5GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX5GCR0_DQSGPDR_MASK +#define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX5GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX5GCR0_RESERVED_4_MASK +#define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX5GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX5GCR0_DQSGODT_MASK +#define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX5GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX5GCR0_DQSGOE_MASK +#define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX5GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX5GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX5GCR1_RESERVED_15_MASK +#define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX5GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX5GCR1_QSNSEL_MASK +#define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX5GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX5GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX5GCR1_QSSEL_MASK +#define DDR_PHY_DX5GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX5GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX5GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX5GCR1_OEEN_SHIFT +#undef DDR_PHY_DX5GCR1_OEEN_MASK +#define DDR_PHY_DX5GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX5GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX5GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX5GCR1_PDREN_SHIFT +#undef DDR_PHY_DX5GCR1_PDREN_MASK +#define DDR_PHY_DX5GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX5GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX5GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX5GCR1_TEEN_SHIFT +#undef DDR_PHY_DX5GCR1_TEEN_MASK +#define DDR_PHY_DX5GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX5GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX5GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX5GCR1_DSEN_SHIFT +#undef DDR_PHY_DX5GCR1_DSEN_MASK +#define DDR_PHY_DX5GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX5GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX5GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX5GCR1_DMEN_SHIFT +#undef DDR_PHY_DX5GCR1_DMEN_MASK +#define DDR_PHY_DX5GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX5GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX5GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX5GCR1_DQEN_SHIFT +#undef DDR_PHY_DX5GCR1_DQEN_MASK +#define DDR_PHY_DX5GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX5GCR1_DQEN_MASK 0x000000FFU + +/* +* Enables the OE mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX5GCR2_DXOEMODE_DEFVAL +#undef DDR_PHY_DX5GCR2_DXOEMODE_SHIFT +#undef DDR_PHY_DX5GCR2_DXOEMODE_MASK +#define DDR_PHY_DX5GCR2_DXOEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX5GCR2_DXOEMODE_SHIFT 16 +#define DDR_PHY_DX5GCR2_DXOEMODE_MASK 0xFFFF0000U + +/* +* Enables the TE (ODT) mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX5GCR2_DXTEMODE_DEFVAL +#undef DDR_PHY_DX5GCR2_DXTEMODE_SHIFT +#undef DDR_PHY_DX5GCR2_DXTEMODE_MASK +#define DDR_PHY_DX5GCR2_DXTEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX5GCR2_DXTEMODE_SHIFT 0 +#define DDR_PHY_DX5GCR2_DXTEMODE_MASK 0x0000FFFFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX5GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX5GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX5GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX5GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX5GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX5GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX5GCR3_RDBVT_MASK +#define DDR_PHY_DX5GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX5GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX5GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX5GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX5GCR3_WDBVT_MASK +#define DDR_PHY_DX5GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX5GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX5GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX5GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX5GCR3_RGLVT_MASK +#define DDR_PHY_DX5GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX5GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX5GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX5GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX5GCR3_RDLVT_MASK +#define DDR_PHY_DX5GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX5GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX5GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX5GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX5GCR3_WDLVT_MASK +#define DDR_PHY_DX5GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX5GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX5GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX5GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX5GCR3_WLLVT_MASK +#define DDR_PHY_DX5GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX5GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX5GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX5GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX5GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX5GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX5GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX5GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX5GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX5GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX5GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX5GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX5GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX5GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX5GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX5GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX5GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DMOEMODE_MASK +#define DDR_PHY_DX5GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX5GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX5GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DMTEMODE_MASK +#define DDR_PHY_DX5GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX5GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX5GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX5GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX5GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX5GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX5GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX5GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX5GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX5GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX5GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DSOEMODE_MASK +#define DDR_PHY_DX5GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX5GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX5GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DSTEMODE_MASK +#define DDR_PHY_DX5GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX5GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX5GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX5GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX5GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX5GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX5GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX5GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX5GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX5GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFPEN_MASK +#define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX5GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFEEN_MASK +#define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX5GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFSEN_MASK +#define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX5GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX5GCR4_RESERVED_24_MASK +#define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX5GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFESEL_MASK +#define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX5GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX5GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFIEN_MASK +#define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX5GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFIMON_MASK +#define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX5GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX5GCR5_RESERVED_31_MASK +#define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX5GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX5GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX5GCR5_RESERVED_23_MASK +#define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX5GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX5GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX5GCR5_RESERVED_15_MASK +#define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX5GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX5GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX5GCR5_RESERVED_7_MASK +#define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX5GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX5GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX6GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX6GCR0_CALBYP_MASK +#define DDR_PHY_DX6GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX6GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX6GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX6GCR0_MDLEN_MASK +#define DDR_PHY_DX6GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX6GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX6GCR0_CODTSHFT_MASK +#define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX6GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX6GCR0_DQSDCC_MASK +#define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX6GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX6GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX6GCR0_RDDLY_MASK +#define DDR_PHY_DX6GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX6GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX6GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX6GCR0_RTTOAL_MASK +#define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX6GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX6GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX6GCR0_RTTOH_MASK +#define DDR_PHY_DX6GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX6GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX6GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX6GCR0_DQSRPD_MASK +#define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX6GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX6GCR0_DQSGPDR_MASK +#define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX6GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX6GCR0_RESERVED_4_MASK +#define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX6GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX6GCR0_DQSGODT_MASK +#define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX6GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX6GCR0_DQSGOE_MASK +#define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX6GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX6GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX6GCR1_RESERVED_15_MASK +#define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX6GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX6GCR1_QSNSEL_MASK +#define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX6GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX6GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX6GCR1_QSSEL_MASK +#define DDR_PHY_DX6GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX6GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX6GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX6GCR1_OEEN_SHIFT +#undef DDR_PHY_DX6GCR1_OEEN_MASK +#define DDR_PHY_DX6GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX6GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX6GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX6GCR1_PDREN_SHIFT +#undef DDR_PHY_DX6GCR1_PDREN_MASK +#define DDR_PHY_DX6GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX6GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX6GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX6GCR1_TEEN_SHIFT +#undef DDR_PHY_DX6GCR1_TEEN_MASK +#define DDR_PHY_DX6GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX6GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX6GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX6GCR1_DSEN_SHIFT +#undef DDR_PHY_DX6GCR1_DSEN_MASK +#define DDR_PHY_DX6GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX6GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX6GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX6GCR1_DMEN_SHIFT +#undef DDR_PHY_DX6GCR1_DMEN_MASK +#define DDR_PHY_DX6GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX6GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX6GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX6GCR1_DQEN_SHIFT +#undef DDR_PHY_DX6GCR1_DQEN_MASK +#define DDR_PHY_DX6GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX6GCR1_DQEN_MASK 0x000000FFU + +/* +* Enables the OE mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX6GCR2_DXOEMODE_DEFVAL +#undef DDR_PHY_DX6GCR2_DXOEMODE_SHIFT +#undef DDR_PHY_DX6GCR2_DXOEMODE_MASK +#define DDR_PHY_DX6GCR2_DXOEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX6GCR2_DXOEMODE_SHIFT 16 +#define DDR_PHY_DX6GCR2_DXOEMODE_MASK 0xFFFF0000U + +/* +* Enables the TE (ODT) mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX6GCR2_DXTEMODE_DEFVAL +#undef DDR_PHY_DX6GCR2_DXTEMODE_SHIFT +#undef DDR_PHY_DX6GCR2_DXTEMODE_MASK +#define DDR_PHY_DX6GCR2_DXTEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX6GCR2_DXTEMODE_SHIFT 0 +#define DDR_PHY_DX6GCR2_DXTEMODE_MASK 0x0000FFFFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX6GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX6GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX6GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX6GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX6GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX6GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX6GCR3_RDBVT_MASK +#define DDR_PHY_DX6GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX6GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX6GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX6GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX6GCR3_WDBVT_MASK +#define DDR_PHY_DX6GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX6GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX6GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX6GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX6GCR3_RGLVT_MASK +#define DDR_PHY_DX6GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX6GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX6GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX6GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX6GCR3_RDLVT_MASK +#define DDR_PHY_DX6GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX6GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX6GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX6GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX6GCR3_WDLVT_MASK +#define DDR_PHY_DX6GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX6GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX6GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX6GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX6GCR3_WLLVT_MASK +#define DDR_PHY_DX6GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX6GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX6GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX6GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX6GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX6GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX6GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX6GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX6GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX6GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX6GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX6GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX6GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX6GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX6GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX6GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX6GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DMOEMODE_MASK +#define DDR_PHY_DX6GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX6GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX6GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DMTEMODE_MASK +#define DDR_PHY_DX6GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX6GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX6GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX6GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX6GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX6GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX6GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX6GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX6GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX6GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX6GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DSOEMODE_MASK +#define DDR_PHY_DX6GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX6GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX6GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DSTEMODE_MASK +#define DDR_PHY_DX6GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX6GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX6GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX6GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX6GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX6GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX6GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX6GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX6GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX6GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFPEN_MASK +#define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX6GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFEEN_MASK +#define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX6GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFSEN_MASK +#define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX6GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX6GCR4_RESERVED_24_MASK +#define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX6GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFESEL_MASK +#define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX6GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX6GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFIEN_MASK +#define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX6GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFIMON_MASK +#define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX6GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX6GCR5_RESERVED_31_MASK +#define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX6GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX6GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX6GCR5_RESERVED_23_MASK +#define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX6GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX6GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX6GCR5_RESERVED_15_MASK +#define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX6GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX6GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX6GCR5_RESERVED_7_MASK +#define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX6GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX6GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX7GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX7GCR0_CALBYP_MASK +#define DDR_PHY_DX7GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX7GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX7GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX7GCR0_MDLEN_MASK +#define DDR_PHY_DX7GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX7GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX7GCR0_CODTSHFT_MASK +#define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX7GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX7GCR0_DQSDCC_MASK +#define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX7GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX7GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX7GCR0_RDDLY_MASK +#define DDR_PHY_DX7GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX7GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX7GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX7GCR0_RTTOAL_MASK +#define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX7GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX7GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX7GCR0_RTTOH_MASK +#define DDR_PHY_DX7GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX7GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX7GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX7GCR0_DQSRPD_MASK +#define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX7GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX7GCR0_DQSGPDR_MASK +#define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX7GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX7GCR0_RESERVED_4_MASK +#define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX7GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX7GCR0_DQSGODT_MASK +#define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX7GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX7GCR0_DQSGOE_MASK +#define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX7GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX7GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX7GCR1_RESERVED_15_MASK +#define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX7GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX7GCR1_QSNSEL_MASK +#define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX7GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX7GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX7GCR1_QSSEL_MASK +#define DDR_PHY_DX7GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX7GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX7GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX7GCR1_OEEN_SHIFT +#undef DDR_PHY_DX7GCR1_OEEN_MASK +#define DDR_PHY_DX7GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX7GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX7GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX7GCR1_PDREN_SHIFT +#undef DDR_PHY_DX7GCR1_PDREN_MASK +#define DDR_PHY_DX7GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX7GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX7GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX7GCR1_TEEN_SHIFT +#undef DDR_PHY_DX7GCR1_TEEN_MASK +#define DDR_PHY_DX7GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX7GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX7GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX7GCR1_DSEN_SHIFT +#undef DDR_PHY_DX7GCR1_DSEN_MASK +#define DDR_PHY_DX7GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX7GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX7GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX7GCR1_DMEN_SHIFT +#undef DDR_PHY_DX7GCR1_DMEN_MASK +#define DDR_PHY_DX7GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX7GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX7GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX7GCR1_DQEN_SHIFT +#undef DDR_PHY_DX7GCR1_DQEN_MASK +#define DDR_PHY_DX7GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX7GCR1_DQEN_MASK 0x000000FFU + +/* +* Enables the OE mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX7GCR2_DXOEMODE_DEFVAL +#undef DDR_PHY_DX7GCR2_DXOEMODE_SHIFT +#undef DDR_PHY_DX7GCR2_DXOEMODE_MASK +#define DDR_PHY_DX7GCR2_DXOEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX7GCR2_DXOEMODE_SHIFT 16 +#define DDR_PHY_DX7GCR2_DXOEMODE_MASK 0xFFFF0000U + +/* +* Enables the TE (ODT) mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX7GCR2_DXTEMODE_DEFVAL +#undef DDR_PHY_DX7GCR2_DXTEMODE_SHIFT +#undef DDR_PHY_DX7GCR2_DXTEMODE_MASK +#define DDR_PHY_DX7GCR2_DXTEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX7GCR2_DXTEMODE_SHIFT 0 +#define DDR_PHY_DX7GCR2_DXTEMODE_MASK 0x0000FFFFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX7GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX7GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX7GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX7GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX7GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX7GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX7GCR3_RDBVT_MASK +#define DDR_PHY_DX7GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX7GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX7GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX7GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX7GCR3_WDBVT_MASK +#define DDR_PHY_DX7GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX7GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX7GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX7GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX7GCR3_RGLVT_MASK +#define DDR_PHY_DX7GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX7GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX7GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX7GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX7GCR3_RDLVT_MASK +#define DDR_PHY_DX7GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX7GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX7GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX7GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX7GCR3_WDLVT_MASK +#define DDR_PHY_DX7GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX7GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX7GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX7GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX7GCR3_WLLVT_MASK +#define DDR_PHY_DX7GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX7GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX7GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX7GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX7GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX7GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX7GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX7GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX7GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX7GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX7GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX7GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX7GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX7GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX7GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX7GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX7GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DMOEMODE_MASK +#define DDR_PHY_DX7GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX7GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX7GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DMTEMODE_MASK +#define DDR_PHY_DX7GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX7GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX7GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX7GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX7GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX7GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX7GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX7GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX7GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX7GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX7GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DSOEMODE_MASK +#define DDR_PHY_DX7GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX7GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX7GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DSTEMODE_MASK +#define DDR_PHY_DX7GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX7GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX7GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX7GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX7GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX7GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX7GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX7GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX7GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX7GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFPEN_MASK +#define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX7GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFEEN_MASK +#define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX7GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFSEN_MASK +#define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX7GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX7GCR4_RESERVED_24_MASK +#define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX7GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFESEL_MASK +#define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX7GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX7GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFIEN_MASK +#define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX7GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFIMON_MASK +#define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX7GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX7GCR5_RESERVED_31_MASK +#define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX7GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX7GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX7GCR5_RESERVED_23_MASK +#define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX7GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX7GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX7GCR5_RESERVED_15_MASK +#define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX7GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX7GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX7GCR5_RESERVED_7_MASK +#define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX7GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX7GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX8GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX8GCR0_CALBYP_MASK +#define DDR_PHY_DX8GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX8GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX8GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX8GCR0_MDLEN_MASK +#define DDR_PHY_DX8GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX8GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX8GCR0_CODTSHFT_MASK +#define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX8GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX8GCR0_DQSDCC_MASK +#define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX8GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX8GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX8GCR0_RDDLY_MASK +#define DDR_PHY_DX8GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX8GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX8GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX8GCR0_RTTOAL_MASK +#define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX8GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX8GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX8GCR0_RTTOH_MASK +#define DDR_PHY_DX8GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX8GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX8GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX8GCR0_DQSRPD_MASK +#define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX8GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX8GCR0_DQSGPDR_MASK +#define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX8GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX8GCR0_RESERVED_4_MASK +#define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX8GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX8GCR0_DQSGODT_MASK +#define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX8GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX8GCR0_DQSGOE_MASK +#define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX8GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX8GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX8GCR1_RESERVED_15_MASK +#define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX8GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX8GCR1_QSNSEL_MASK +#define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX8GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX8GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX8GCR1_QSSEL_MASK +#define DDR_PHY_DX8GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX8GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX8GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX8GCR1_OEEN_SHIFT +#undef DDR_PHY_DX8GCR1_OEEN_MASK +#define DDR_PHY_DX8GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX8GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX8GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX8GCR1_PDREN_SHIFT +#undef DDR_PHY_DX8GCR1_PDREN_MASK +#define DDR_PHY_DX8GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX8GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX8GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX8GCR1_TEEN_SHIFT +#undef DDR_PHY_DX8GCR1_TEEN_MASK +#define DDR_PHY_DX8GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX8GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX8GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX8GCR1_DSEN_SHIFT +#undef DDR_PHY_DX8GCR1_DSEN_MASK +#define DDR_PHY_DX8GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX8GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX8GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX8GCR1_DMEN_SHIFT +#undef DDR_PHY_DX8GCR1_DMEN_MASK +#define DDR_PHY_DX8GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX8GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX8GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX8GCR1_DQEN_SHIFT +#undef DDR_PHY_DX8GCR1_DQEN_MASK +#define DDR_PHY_DX8GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX8GCR1_DQEN_MASK 0x000000FFU + +/* +* Enables the OE mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX8GCR2_DXOEMODE_DEFVAL +#undef DDR_PHY_DX8GCR2_DXOEMODE_SHIFT +#undef DDR_PHY_DX8GCR2_DXOEMODE_MASK +#define DDR_PHY_DX8GCR2_DXOEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8GCR2_DXOEMODE_SHIFT 16 +#define DDR_PHY_DX8GCR2_DXOEMODE_MASK 0xFFFF0000U + +/* +* Enables the TE (ODT) mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX8GCR2_DXTEMODE_DEFVAL +#undef DDR_PHY_DX8GCR2_DXTEMODE_SHIFT +#undef DDR_PHY_DX8GCR2_DXTEMODE_MASK +#define DDR_PHY_DX8GCR2_DXTEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8GCR2_DXTEMODE_SHIFT 0 +#define DDR_PHY_DX8GCR2_DXTEMODE_MASK 0x0000FFFFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX8GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX8GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX8GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX8GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX8GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX8GCR3_RDBVT_MASK +#define DDR_PHY_DX8GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX8GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX8GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX8GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX8GCR3_WDBVT_MASK +#define DDR_PHY_DX8GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX8GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX8GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX8GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX8GCR3_RGLVT_MASK +#define DDR_PHY_DX8GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX8GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX8GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX8GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX8GCR3_RDLVT_MASK +#define DDR_PHY_DX8GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX8GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX8GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX8GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX8GCR3_WDLVT_MASK +#define DDR_PHY_DX8GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX8GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX8GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX8GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX8GCR3_WLLVT_MASK +#define DDR_PHY_DX8GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX8GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX8GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX8GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX8GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX8GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX8GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX8GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX8GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX8GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX8GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX8GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX8GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX8GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DMOEMODE_MASK +#define DDR_PHY_DX8GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX8GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX8GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DMTEMODE_MASK +#define DDR_PHY_DX8GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX8GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX8GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX8GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX8GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX8GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX8GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX8GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX8GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX8GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX8GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DSOEMODE_MASK +#define DDR_PHY_DX8GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX8GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX8GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DSTEMODE_MASK +#define DDR_PHY_DX8GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX8GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX8GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX8GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX8GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX8GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX8GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX8GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX8GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX8GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFPEN_MASK +#define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX8GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFEEN_MASK +#define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX8GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFSEN_MASK +#define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX8GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX8GCR4_RESERVED_24_MASK +#define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX8GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFESEL_MASK +#define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX8GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX8GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFIEN_MASK +#define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX8GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFIMON_MASK +#define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX8GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX8GCR5_RESERVED_31_MASK +#define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX8GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX8GCR5_RESERVED_23_MASK +#define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX8GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX8GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX8GCR5_RESERVED_15_MASK +#define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX8GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX8GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX8GCR5_RESERVED_7_MASK +#define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX8GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX8GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 0xC0000000U + +/* +* Enable Clock Gating for DX ddr_clk +*/ +#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL +#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT +#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 0x30000000U + +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ +#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL +#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT +#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 0x0C000000U + +/* +* Enable Clock Gating for DX ctl_clk +*/ +#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL +#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT +#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 0x03000000U + +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ +#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL +#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT +#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 0x00C00000U + +/* +* Loopback Mode +*/ +#undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL +#undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT +#undef DDR_PHY_DX8SL0OSC_LBMODE_MASK +#define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL0OSC_LBMODE_MASK 0x00200000U + +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ +#undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL +#undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT +#undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK +#define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 0x00100000U + +/* +* Loopback DQS Gating +*/ +#undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL +#undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT +#undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK +#define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL0OSC_LBGDQS_MASK 0x000C0000U + +/* +* Loopback DQS Shift +*/ +#undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL +#undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT +#undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK +#define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL0OSC_LBDQSS_MASK 0x00020000U + +/* +* PHY High-Speed Reset +*/ +#undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL +#undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT +#undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK +#define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL0OSC_PHYHRST_MASK 0x00010000U + +/* +* PHY FIFO Reset +*/ +#undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL +#undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT +#undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK +#define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL0OSC_PHYFRST_MASK 0x00008000U + +/* +* Delay Line Test Start +*/ +#undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL +#undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT +#undef DDR_PHY_DX8SL0OSC_DLTST_MASK +#define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL0OSC_DLTST_MASK 0x00004000U + +/* +* Delay Line Test Mode +*/ +#undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL +#undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT +#undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK +#define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL0OSC_DLTMODE_MASK 0x00002000U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL +#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT +#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 0x00001800U + +/* +* Oscillator Mode Write-Data Delay Line Select +*/ +#undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL +#undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT +#undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK +#define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 0x00000600U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL +#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT +#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 0x00000180U + +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ +#undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL +#undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT +#undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK +#define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL0OSC_OSCWDL_MASK 0x00000060U + +/* +* Oscillator Mode Division +*/ +#undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL +#undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT +#undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK +#define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL0OSC_OSCDIV_MASK 0x0000001EU + +/* +* Oscillator Enable +*/ +#undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL +#undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT +#undef DDR_PHY_DX8SL0OSC_OSCEN_MASK +#define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL0OSC_OSCEN_MASK 0x00000001U + +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL0PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL0PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL0PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL0PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 0xFE000000U + +/* +* Read Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 0x01000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 0x00C00000U + +/* +* Write Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 0x00200000U + +/* +* DQS Gate Extension +*/ +#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 0x00180000U + +/* +* Low Power PLL Power Down +*/ +#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 0x00040000U + +/* +* Low Power I/O Power Down +*/ +#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 0x00020000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 0x00018000U + +/* +* QS Counter Enable +*/ +#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 0x00004000U + +/* +* Unused DQ I/O Mode +*/ +#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 0x00002000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 0x00001C00U + +/* +* Data Slew Rate +*/ +#undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK +#define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 0x00000300U + +/* +* DQS_N Resistor +*/ +#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 0x000000F0U + +/* +* DQS Resistor +*/ +#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 0xFF000000U + +/* +* Configurable Read Data Enable +*/ +#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 0x00800000U + +/* +* OX Extension during Post-amble +*/ +#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 0x00700000U + +/* +* OE Extension during Pre-amble +*/ +#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 0x000C0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 0x00020000U + +/* +* I/O Assisted Gate Select +*/ +#undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK +#define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 0x00010000U + +/* +* I/O Loopback Select +*/ +#undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK +#define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 0x00008000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 0x00006000U + +/* +* Low Power Wakeup Threshold +*/ +#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U + +/* +* Read Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK +#define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 0x00000100U + +/* +* Write Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK +#define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 0x00000080U + +/* +* PUB Read FIFO Bypass +*/ +#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 0x00000040U + +/* +* DATX8 Receive FIFO Read Mode +*/ +#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 0x00000030U + +/* +* Disables the Read FIFO Reset +*/ +#undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK +#define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 0x00000008U + +/* +* Read DQS Gate I/O Loopback +*/ +#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 0x00000006U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL +#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT +#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 0x80000000U + +/* +* PVREF_DAC REFSEL range select +*/ +#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL +#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT +#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 0x70000000U + +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ +#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL +#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT +#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 0x0E000000U + +/* +* DX IO Mode +*/ +#undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL +#undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT +#undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK +#define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL0IOCR_DXIOM_MASK 0x01C00000U + +/* +* DX IO Transmitter Mode +*/ +#undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL +#undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT +#undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK +#define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL0IOCR_DXTXM_MASK 0x003FF800U + +/* +* DX IO Receiver Mode +*/ +#undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL +#undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT +#undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK +#define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK 0x000007FFU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 0xC0000000U + +/* +* Enable Clock Gating for DX ddr_clk +*/ +#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL +#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT +#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 0x30000000U + +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ +#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL +#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT +#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 0x0C000000U + +/* +* Enable Clock Gating for DX ctl_clk +*/ +#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL +#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT +#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 0x03000000U + +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ +#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL +#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT +#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 0x00C00000U + +/* +* Loopback Mode +*/ +#undef DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL +#undef DDR_PHY_DX8SL1OSC_LBMODE_SHIFT +#undef DDR_PHY_DX8SL1OSC_LBMODE_MASK +#define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL1OSC_LBMODE_MASK 0x00200000U + +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ +#undef DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL +#undef DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT +#undef DDR_PHY_DX8SL1OSC_LBGSDQS_MASK +#define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 0x00100000U + +/* +* Loopback DQS Gating +*/ +#undef DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL +#undef DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT +#undef DDR_PHY_DX8SL1OSC_LBGDQS_MASK +#define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL1OSC_LBGDQS_MASK 0x000C0000U + +/* +* Loopback DQS Shift +*/ +#undef DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL +#undef DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT +#undef DDR_PHY_DX8SL1OSC_LBDQSS_MASK +#define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL1OSC_LBDQSS_MASK 0x00020000U + +/* +* PHY High-Speed Reset +*/ +#undef DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL +#undef DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT +#undef DDR_PHY_DX8SL1OSC_PHYHRST_MASK +#define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL1OSC_PHYHRST_MASK 0x00010000U + +/* +* PHY FIFO Reset +*/ +#undef DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL +#undef DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT +#undef DDR_PHY_DX8SL1OSC_PHYFRST_MASK +#define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL1OSC_PHYFRST_MASK 0x00008000U + +/* +* Delay Line Test Start +*/ +#undef DDR_PHY_DX8SL1OSC_DLTST_DEFVAL +#undef DDR_PHY_DX8SL1OSC_DLTST_SHIFT +#undef DDR_PHY_DX8SL1OSC_DLTST_MASK +#define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL1OSC_DLTST_MASK 0x00004000U + +/* +* Delay Line Test Mode +*/ +#undef DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL +#undef DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT +#undef DDR_PHY_DX8SL1OSC_DLTMODE_MASK +#define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL1OSC_DLTMODE_MASK 0x00002000U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL +#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT +#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 0x00001800U + +/* +* Oscillator Mode Write-Data Delay Line Select +*/ +#undef DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL +#undef DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT +#undef DDR_PHY_DX8SL1OSC_OSCWDDL_MASK +#define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 0x00000600U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL +#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT +#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 0x00000180U + +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ +#undef DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL +#undef DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT +#undef DDR_PHY_DX8SL1OSC_OSCWDL_MASK +#define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL1OSC_OSCWDL_MASK 0x00000060U + +/* +* Oscillator Mode Division +*/ +#undef DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL +#undef DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT +#undef DDR_PHY_DX8SL1OSC_OSCDIV_MASK +#define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL1OSC_OSCDIV_MASK 0x0000001EU + +/* +* Oscillator Enable +*/ +#undef DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL +#undef DDR_PHY_DX8SL1OSC_OSCEN_SHIFT +#undef DDR_PHY_DX8SL1OSC_OSCEN_MASK +#define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL1OSC_OSCEN_MASK 0x00000001U + +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL1PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL1PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL1PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL1PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 0xFE000000U + +/* +* Read Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 0x01000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 0x00C00000U + +/* +* Write Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 0x00200000U + +/* +* DQS Gate Extension +*/ +#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 0x00180000U + +/* +* Low Power PLL Power Down +*/ +#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 0x00040000U + +/* +* Low Power I/O Power Down +*/ +#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 0x00020000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 0x00018000U + +/* +* QS Counter Enable +*/ +#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 0x00004000U + +/* +* Unused DQ I/O Mode +*/ +#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 0x00002000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 0x00001C00U + +/* +* Data Slew Rate +*/ +#undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK +#define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 0x00000300U + +/* +* DQS_N Resistor +*/ +#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 0x000000F0U + +/* +* DQS Resistor +*/ +#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 0xFF000000U + +/* +* Configurable Read Data Enable +*/ +#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 0x00800000U + +/* +* OX Extension during Post-amble +*/ +#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 0x00700000U + +/* +* OE Extension during Pre-amble +*/ +#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 0x000C0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 0x00020000U + +/* +* I/O Assisted Gate Select +*/ +#undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK +#define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 0x00010000U + +/* +* I/O Loopback Select +*/ +#undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK +#define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 0x00008000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 0x00006000U + +/* +* Low Power Wakeup Threshold +*/ +#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U + +/* +* Read Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK +#define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 0x00000100U + +/* +* Write Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK +#define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 0x00000080U + +/* +* PUB Read FIFO Bypass +*/ +#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 0x00000040U + +/* +* DATX8 Receive FIFO Read Mode +*/ +#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 0x00000030U + +/* +* Disables the Read FIFO Reset +*/ +#undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK +#define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 0x00000008U + +/* +* Read DQS Gate I/O Loopback +*/ +#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 0x00000006U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL +#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT +#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 0x80000000U + +/* +* PVREF_DAC REFSEL range select +*/ +#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL +#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT +#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 0x70000000U + +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ +#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL +#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT +#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 0x0E000000U + +/* +* DX IO Mode +*/ +#undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL +#undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT +#undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK +#define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL1IOCR_DXIOM_MASK 0x01C00000U + +/* +* DX IO Transmitter Mode +*/ +#undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL +#undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT +#undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK +#define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL1IOCR_DXTXM_MASK 0x003FF800U + +/* +* DX IO Receiver Mode +*/ +#undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL +#undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT +#undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK +#define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK 0x000007FFU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 0xC0000000U + +/* +* Enable Clock Gating for DX ddr_clk +*/ +#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL +#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT +#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 0x30000000U + +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ +#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL +#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT +#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 0x0C000000U + +/* +* Enable Clock Gating for DX ctl_clk +*/ +#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL +#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT +#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 0x03000000U + +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ +#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL +#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT +#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 0x00C00000U + +/* +* Loopback Mode +*/ +#undef DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL +#undef DDR_PHY_DX8SL2OSC_LBMODE_SHIFT +#undef DDR_PHY_DX8SL2OSC_LBMODE_MASK +#define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL2OSC_LBMODE_MASK 0x00200000U + +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ +#undef DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL +#undef DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT +#undef DDR_PHY_DX8SL2OSC_LBGSDQS_MASK +#define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 0x00100000U + +/* +* Loopback DQS Gating +*/ +#undef DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL +#undef DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT +#undef DDR_PHY_DX8SL2OSC_LBGDQS_MASK +#define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL2OSC_LBGDQS_MASK 0x000C0000U + +/* +* Loopback DQS Shift +*/ +#undef DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL +#undef DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT +#undef DDR_PHY_DX8SL2OSC_LBDQSS_MASK +#define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL2OSC_LBDQSS_MASK 0x00020000U + +/* +* PHY High-Speed Reset +*/ +#undef DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL +#undef DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT +#undef DDR_PHY_DX8SL2OSC_PHYHRST_MASK +#define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL2OSC_PHYHRST_MASK 0x00010000U + +/* +* PHY FIFO Reset +*/ +#undef DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL +#undef DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT +#undef DDR_PHY_DX8SL2OSC_PHYFRST_MASK +#define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL2OSC_PHYFRST_MASK 0x00008000U + +/* +* Delay Line Test Start +*/ +#undef DDR_PHY_DX8SL2OSC_DLTST_DEFVAL +#undef DDR_PHY_DX8SL2OSC_DLTST_SHIFT +#undef DDR_PHY_DX8SL2OSC_DLTST_MASK +#define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL2OSC_DLTST_MASK 0x00004000U + +/* +* Delay Line Test Mode +*/ +#undef DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL +#undef DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT +#undef DDR_PHY_DX8SL2OSC_DLTMODE_MASK +#define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL2OSC_DLTMODE_MASK 0x00002000U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL +#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT +#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 0x00001800U + +/* +* Oscillator Mode Write-Data Delay Line Select +*/ +#undef DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL +#undef DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT +#undef DDR_PHY_DX8SL2OSC_OSCWDDL_MASK +#define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 0x00000600U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL +#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT +#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 0x00000180U + +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ +#undef DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL +#undef DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT +#undef DDR_PHY_DX8SL2OSC_OSCWDL_MASK +#define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL2OSC_OSCWDL_MASK 0x00000060U + +/* +* Oscillator Mode Division +*/ +#undef DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL +#undef DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT +#undef DDR_PHY_DX8SL2OSC_OSCDIV_MASK +#define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL2OSC_OSCDIV_MASK 0x0000001EU + +/* +* Oscillator Enable +*/ +#undef DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL +#undef DDR_PHY_DX8SL2OSC_OSCEN_SHIFT +#undef DDR_PHY_DX8SL2OSC_OSCEN_MASK +#define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL2OSC_OSCEN_MASK 0x00000001U + +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL2PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL2PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL2PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL2PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 0xFE000000U + +/* +* Read Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 0x01000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 0x00C00000U + +/* +* Write Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 0x00200000U + +/* +* DQS Gate Extension +*/ +#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 0x00180000U + +/* +* Low Power PLL Power Down +*/ +#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 0x00040000U + +/* +* Low Power I/O Power Down +*/ +#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 0x00020000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 0x00018000U + +/* +* QS Counter Enable +*/ +#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 0x00004000U + +/* +* Unused DQ I/O Mode +*/ +#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 0x00002000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 0x00001C00U + +/* +* Data Slew Rate +*/ +#undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK +#define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 0x00000300U + +/* +* DQS_N Resistor +*/ +#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 0x000000F0U + +/* +* DQS Resistor +*/ +#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 0xFF000000U + +/* +* Configurable Read Data Enable +*/ +#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 0x00800000U + +/* +* OX Extension during Post-amble +*/ +#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 0x00700000U + +/* +* OE Extension during Pre-amble +*/ +#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 0x000C0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 0x00020000U + +/* +* I/O Assisted Gate Select +*/ +#undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK +#define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 0x00010000U + +/* +* I/O Loopback Select +*/ +#undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK +#define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 0x00008000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 0x00006000U + +/* +* Low Power Wakeup Threshold +*/ +#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U + +/* +* Read Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK +#define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 0x00000100U + +/* +* Write Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK +#define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 0x00000080U + +/* +* PUB Read FIFO Bypass +*/ +#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 0x00000040U + +/* +* DATX8 Receive FIFO Read Mode +*/ +#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 0x00000030U + +/* +* Disables the Read FIFO Reset +*/ +#undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK +#define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 0x00000008U + +/* +* Read DQS Gate I/O Loopback +*/ +#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 0x00000006U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL +#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT +#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 0x80000000U + +/* +* PVREF_DAC REFSEL range select +*/ +#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL +#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT +#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 0x70000000U + +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ +#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL +#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT +#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 0x0E000000U + +/* +* DX IO Mode +*/ +#undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL +#undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT +#undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK +#define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL2IOCR_DXIOM_MASK 0x01C00000U + +/* +* DX IO Transmitter Mode +*/ +#undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL +#undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT +#undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK +#define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL2IOCR_DXTXM_MASK 0x003FF800U + +/* +* DX IO Receiver Mode +*/ +#undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL +#undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT +#undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK +#define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK 0x000007FFU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 0xC0000000U + +/* +* Enable Clock Gating for DX ddr_clk +*/ +#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL +#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT +#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 0x30000000U + +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ +#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL +#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT +#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 0x0C000000U + +/* +* Enable Clock Gating for DX ctl_clk +*/ +#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL +#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT +#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 0x03000000U + +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ +#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL +#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT +#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 0x00C00000U + +/* +* Loopback Mode +*/ +#undef DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL +#undef DDR_PHY_DX8SL3OSC_LBMODE_SHIFT +#undef DDR_PHY_DX8SL3OSC_LBMODE_MASK +#define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL3OSC_LBMODE_MASK 0x00200000U + +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ +#undef DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL +#undef DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT +#undef DDR_PHY_DX8SL3OSC_LBGSDQS_MASK +#define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 0x00100000U + +/* +* Loopback DQS Gating +*/ +#undef DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL +#undef DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT +#undef DDR_PHY_DX8SL3OSC_LBGDQS_MASK +#define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL3OSC_LBGDQS_MASK 0x000C0000U + +/* +* Loopback DQS Shift +*/ +#undef DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL +#undef DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT +#undef DDR_PHY_DX8SL3OSC_LBDQSS_MASK +#define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL3OSC_LBDQSS_MASK 0x00020000U + +/* +* PHY High-Speed Reset +*/ +#undef DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL +#undef DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT +#undef DDR_PHY_DX8SL3OSC_PHYHRST_MASK +#define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL3OSC_PHYHRST_MASK 0x00010000U + +/* +* PHY FIFO Reset +*/ +#undef DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL +#undef DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT +#undef DDR_PHY_DX8SL3OSC_PHYFRST_MASK +#define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL3OSC_PHYFRST_MASK 0x00008000U + +/* +* Delay Line Test Start +*/ +#undef DDR_PHY_DX8SL3OSC_DLTST_DEFVAL +#undef DDR_PHY_DX8SL3OSC_DLTST_SHIFT +#undef DDR_PHY_DX8SL3OSC_DLTST_MASK +#define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL3OSC_DLTST_MASK 0x00004000U + +/* +* Delay Line Test Mode +*/ +#undef DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL +#undef DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT +#undef DDR_PHY_DX8SL3OSC_DLTMODE_MASK +#define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL3OSC_DLTMODE_MASK 0x00002000U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL +#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT +#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 0x00001800U + +/* +* Oscillator Mode Write-Data Delay Line Select +*/ +#undef DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL +#undef DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT +#undef DDR_PHY_DX8SL3OSC_OSCWDDL_MASK +#define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 0x00000600U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL +#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT +#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 0x00000180U + +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ +#undef DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL +#undef DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT +#undef DDR_PHY_DX8SL3OSC_OSCWDL_MASK +#define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL3OSC_OSCWDL_MASK 0x00000060U + +/* +* Oscillator Mode Division +*/ +#undef DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL +#undef DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT +#undef DDR_PHY_DX8SL3OSC_OSCDIV_MASK +#define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL3OSC_OSCDIV_MASK 0x0000001EU + +/* +* Oscillator Enable +*/ +#undef DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL +#undef DDR_PHY_DX8SL3OSC_OSCEN_SHIFT +#undef DDR_PHY_DX8SL3OSC_OSCEN_MASK +#define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL3OSC_OSCEN_MASK 0x00000001U + +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL3PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL3PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL3PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL3PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 0xFE000000U + +/* +* Read Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 0x01000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 0x00C00000U + +/* +* Write Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 0x00200000U + +/* +* DQS Gate Extension +*/ +#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 0x00180000U + +/* +* Low Power PLL Power Down +*/ +#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 0x00040000U + +/* +* Low Power I/O Power Down +*/ +#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 0x00020000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 0x00018000U + +/* +* QS Counter Enable +*/ +#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 0x00004000U + +/* +* Unused DQ I/O Mode +*/ +#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 0x00002000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 0x00001C00U + +/* +* Data Slew Rate +*/ +#undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK +#define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 0x00000300U + +/* +* DQS_N Resistor +*/ +#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 0x000000F0U + +/* +* DQS Resistor +*/ +#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 0xFF000000U + +/* +* Configurable Read Data Enable +*/ +#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 0x00800000U + +/* +* OX Extension during Post-amble +*/ +#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 0x00700000U + +/* +* OE Extension during Pre-amble +*/ +#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 0x000C0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 0x00020000U + +/* +* I/O Assisted Gate Select +*/ +#undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK +#define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 0x00010000U + +/* +* I/O Loopback Select +*/ +#undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK +#define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 0x00008000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 0x00006000U + +/* +* Low Power Wakeup Threshold +*/ +#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U + +/* +* Read Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK +#define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 0x00000100U + +/* +* Write Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK +#define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 0x00000080U + +/* +* PUB Read FIFO Bypass +*/ +#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 0x00000040U + +/* +* DATX8 Receive FIFO Read Mode +*/ +#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 0x00000030U + +/* +* Disables the Read FIFO Reset +*/ +#undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK +#define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 0x00000008U + +/* +* Read DQS Gate I/O Loopback +*/ +#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 0x00000006U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL +#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT +#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 0x80000000U + +/* +* PVREF_DAC REFSEL range select +*/ +#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL +#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT +#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 0x70000000U + +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ +#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL +#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT +#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 0x0E000000U + +/* +* DX IO Mode +*/ +#undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL +#undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT +#undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK +#define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL3IOCR_DXIOM_MASK 0x01C00000U + +/* +* DX IO Transmitter Mode +*/ +#undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL +#undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT +#undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK +#define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL3IOCR_DXTXM_MASK 0x003FF800U + +/* +* DX IO Receiver Mode +*/ +#undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL +#undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT +#undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK +#define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK 0x000007FFU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 0xC0000000U + +/* +* Enable Clock Gating for DX ddr_clk +*/ +#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL +#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT +#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 0x30000000U + +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ +#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL +#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT +#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 0x0C000000U + +/* +* Enable Clock Gating for DX ctl_clk +*/ +#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL +#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT +#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 0x03000000U + +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ +#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL +#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT +#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 0x00C00000U + +/* +* Loopback Mode +*/ +#undef DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL +#undef DDR_PHY_DX8SL4OSC_LBMODE_SHIFT +#undef DDR_PHY_DX8SL4OSC_LBMODE_MASK +#define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL4OSC_LBMODE_MASK 0x00200000U + +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ +#undef DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL +#undef DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT +#undef DDR_PHY_DX8SL4OSC_LBGSDQS_MASK +#define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 0x00100000U + +/* +* Loopback DQS Gating +*/ +#undef DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL +#undef DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT +#undef DDR_PHY_DX8SL4OSC_LBGDQS_MASK +#define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL4OSC_LBGDQS_MASK 0x000C0000U + +/* +* Loopback DQS Shift +*/ +#undef DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL +#undef DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT +#undef DDR_PHY_DX8SL4OSC_LBDQSS_MASK +#define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL4OSC_LBDQSS_MASK 0x00020000U + +/* +* PHY High-Speed Reset +*/ +#undef DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL +#undef DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT +#undef DDR_PHY_DX8SL4OSC_PHYHRST_MASK +#define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL4OSC_PHYHRST_MASK 0x00010000U + +/* +* PHY FIFO Reset +*/ +#undef DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL +#undef DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT +#undef DDR_PHY_DX8SL4OSC_PHYFRST_MASK +#define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL4OSC_PHYFRST_MASK 0x00008000U + +/* +* Delay Line Test Start +*/ +#undef DDR_PHY_DX8SL4OSC_DLTST_DEFVAL +#undef DDR_PHY_DX8SL4OSC_DLTST_SHIFT +#undef DDR_PHY_DX8SL4OSC_DLTST_MASK +#define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL4OSC_DLTST_MASK 0x00004000U + +/* +* Delay Line Test Mode +*/ +#undef DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL +#undef DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT +#undef DDR_PHY_DX8SL4OSC_DLTMODE_MASK +#define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL4OSC_DLTMODE_MASK 0x00002000U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL +#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT +#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 0x00001800U + +/* +* Oscillator Mode Write-Data Delay Line Select +*/ +#undef DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL +#undef DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT +#undef DDR_PHY_DX8SL4OSC_OSCWDDL_MASK +#define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 0x00000600U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL +#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT +#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 0x00000180U + +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ +#undef DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL +#undef DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT +#undef DDR_PHY_DX8SL4OSC_OSCWDL_MASK +#define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL4OSC_OSCWDL_MASK 0x00000060U + +/* +* Oscillator Mode Division +*/ +#undef DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL +#undef DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT +#undef DDR_PHY_DX8SL4OSC_OSCDIV_MASK +#define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL4OSC_OSCDIV_MASK 0x0000001EU + +/* +* Oscillator Enable +*/ +#undef DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL +#undef DDR_PHY_DX8SL4OSC_OSCEN_SHIFT +#undef DDR_PHY_DX8SL4OSC_OSCEN_MASK +#define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL4OSC_OSCEN_MASK 0x00000001U + +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL4PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL4PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL4PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL4PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 0xFE000000U + +/* +* Read Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 0x01000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 0x00C00000U + +/* +* Write Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 0x00200000U + +/* +* DQS Gate Extension +*/ +#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 0x00180000U + +/* +* Low Power PLL Power Down +*/ +#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 0x00040000U + +/* +* Low Power I/O Power Down +*/ +#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 0x00020000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 0x00018000U + +/* +* QS Counter Enable +*/ +#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 0x00004000U + +/* +* Unused DQ I/O Mode +*/ +#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 0x00002000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 0x00001C00U + +/* +* Data Slew Rate +*/ +#undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK +#define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 0x00000300U + +/* +* DQS_N Resistor +*/ +#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 0x000000F0U + +/* +* DQS Resistor +*/ +#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 0xFF000000U + +/* +* Configurable Read Data Enable +*/ +#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 0x00800000U + +/* +* OX Extension during Post-amble +*/ +#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 0x00700000U + +/* +* OE Extension during Pre-amble +*/ +#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 0x000C0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 0x00020000U + +/* +* I/O Assisted Gate Select +*/ +#undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK +#define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 0x00010000U + +/* +* I/O Loopback Select +*/ +#undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK +#define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 0x00008000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 0x00006000U + +/* +* Low Power Wakeup Threshold +*/ +#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U + +/* +* Read Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK +#define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 0x00000100U + +/* +* Write Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK +#define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 0x00000080U + +/* +* PUB Read FIFO Bypass +*/ +#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 0x00000040U + +/* +* DATX8 Receive FIFO Read Mode +*/ +#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 0x00000030U + +/* +* Disables the Read FIFO Reset +*/ +#undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK +#define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 0x00000008U + +/* +* Read DQS Gate I/O Loopback +*/ +#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 0x00000006U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL +#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT +#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 0x80000000U + +/* +* PVREF_DAC REFSEL range select +*/ +#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL +#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT +#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 0x70000000U + +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ +#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL +#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT +#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 0x0E000000U + +/* +* DX IO Mode +*/ +#undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL +#undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT +#undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK +#define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL4IOCR_DXIOM_MASK 0x01C00000U + +/* +* DX IO Transmitter Mode +*/ +#undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL +#undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT +#undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK +#define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL4IOCR_DXTXM_MASK 0x003FF800U + +/* +* DX IO Receiver Mode +*/ +#undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL +#undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT +#undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK +#define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL4IOCR_DXRXM_MASK 0x000007FFU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 0xFE000000U + +/* +* Read Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 0x01000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 0x00C00000U + +/* +* Write Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 0x00200000U + +/* +* DQS Gate Extension +*/ +#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 0x00180000U + +/* +* Low Power PLL Power Down +*/ +#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 0x00040000U + +/* +* Low Power I/O Power Down +*/ +#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 0x00020000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 0x00018000U + +/* +* QS Counter Enable +*/ +#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 0x00004000U + +/* +* Unused DQ I/O Mode +*/ +#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 0x00002000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 0x00001C00U + +/* +* Data Slew Rate +*/ +#undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK +#define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 0x00000300U + +/* +* DQS# Resistor +*/ +#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 0x000000F0U + +/* +* DQS Resistor +*/ +#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 0x0000000FU +#undef AFIFM0_AFIFM_RDQOS_OFFSET +#define AFIFM0_AFIFM_RDQOS_OFFSET 0XFD360008 +#undef AFIFM0_AFIFM_WRQOS_OFFSET +#define AFIFM0_AFIFM_WRQOS_OFFSET 0XFD36001C +#undef AFIFM1_AFIFM_RDQOS_OFFSET +#define AFIFM1_AFIFM_RDQOS_OFFSET 0XFD370008 +#undef AFIFM1_AFIFM_WRQOS_OFFSET +#define AFIFM1_AFIFM_WRQOS_OFFSET 0XFD37001C +#undef AFIFM2_AFIFM_RDQOS_OFFSET +#define AFIFM2_AFIFM_RDQOS_OFFSET 0XFD380008 +#undef AFIFM2_AFIFM_WRQOS_OFFSET +#define AFIFM2_AFIFM_WRQOS_OFFSET 0XFD38001C +#undef AFIFM3_AFIFM_RDQOS_OFFSET +#define AFIFM3_AFIFM_RDQOS_OFFSET 0XFD390008 +#undef AFIFM3_AFIFM_WRQOS_OFFSET +#define AFIFM3_AFIFM_WRQOS_OFFSET 0XFD39001C +#undef AFIFM4_AFIFM_RDQOS_OFFSET +#define AFIFM4_AFIFM_RDQOS_OFFSET 0XFD3A0008 +#undef AFIFM4_AFIFM_WRQOS_OFFSET +#define AFIFM4_AFIFM_WRQOS_OFFSET 0XFD3A001C +#undef AFIFM5_AFIFM_RDQOS_OFFSET +#define AFIFM5_AFIFM_RDQOS_OFFSET 0XFD3B0008 +#undef AFIFM5_AFIFM_WRQOS_OFFSET +#define AFIFM5_AFIFM_WRQOS_OFFSET 0XFD3B001C +#undef AFIFM6_AFIFM_RDQOS_OFFSET +#define AFIFM6_AFIFM_RDQOS_OFFSET 0XFF9B0008 +#undef AFIFM6_AFIFM_WRQOS_OFFSET +#define AFIFM6_AFIFM_WRQOS_OFFSET 0XFF9B001C + +/* +* Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM0_AFIFM_RDQOS_VALUE_DEFVAL +#undef AFIFM0_AFIFM_RDQOS_VALUE_SHIFT +#undef AFIFM0_AFIFM_RDQOS_VALUE_MASK +#define AFIFM0_AFIFM_RDQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM0_AFIFM_RDQOS_VALUE_SHIFT 0 +#define AFIFM0_AFIFM_RDQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM0_AFIFM_WRQOS_VALUE_DEFVAL +#undef AFIFM0_AFIFM_WRQOS_VALUE_SHIFT +#undef AFIFM0_AFIFM_WRQOS_VALUE_MASK +#define AFIFM0_AFIFM_WRQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM0_AFIFM_WRQOS_VALUE_SHIFT 0 +#define AFIFM0_AFIFM_WRQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM1_AFIFM_RDQOS_VALUE_DEFVAL +#undef AFIFM1_AFIFM_RDQOS_VALUE_SHIFT +#undef AFIFM1_AFIFM_RDQOS_VALUE_MASK +#define AFIFM1_AFIFM_RDQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM1_AFIFM_RDQOS_VALUE_SHIFT 0 +#define AFIFM1_AFIFM_RDQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM1_AFIFM_WRQOS_VALUE_DEFVAL +#undef AFIFM1_AFIFM_WRQOS_VALUE_SHIFT +#undef AFIFM1_AFIFM_WRQOS_VALUE_MASK +#define AFIFM1_AFIFM_WRQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM1_AFIFM_WRQOS_VALUE_SHIFT 0 +#define AFIFM1_AFIFM_WRQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM2_AFIFM_RDQOS_VALUE_DEFVAL +#undef AFIFM2_AFIFM_RDQOS_VALUE_SHIFT +#undef AFIFM2_AFIFM_RDQOS_VALUE_MASK +#define AFIFM2_AFIFM_RDQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM2_AFIFM_RDQOS_VALUE_SHIFT 0 +#define AFIFM2_AFIFM_RDQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM2_AFIFM_WRQOS_VALUE_DEFVAL +#undef AFIFM2_AFIFM_WRQOS_VALUE_SHIFT +#undef AFIFM2_AFIFM_WRQOS_VALUE_MASK +#define AFIFM2_AFIFM_WRQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM2_AFIFM_WRQOS_VALUE_SHIFT 0 +#define AFIFM2_AFIFM_WRQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM3_AFIFM_RDQOS_VALUE_DEFVAL +#undef AFIFM3_AFIFM_RDQOS_VALUE_SHIFT +#undef AFIFM3_AFIFM_RDQOS_VALUE_MASK +#define AFIFM3_AFIFM_RDQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM3_AFIFM_RDQOS_VALUE_SHIFT 0 +#define AFIFM3_AFIFM_RDQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM3_AFIFM_WRQOS_VALUE_DEFVAL +#undef AFIFM3_AFIFM_WRQOS_VALUE_SHIFT +#undef AFIFM3_AFIFM_WRQOS_VALUE_MASK +#define AFIFM3_AFIFM_WRQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM3_AFIFM_WRQOS_VALUE_SHIFT 0 +#define AFIFM3_AFIFM_WRQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM4_AFIFM_RDQOS_VALUE_DEFVAL +#undef AFIFM4_AFIFM_RDQOS_VALUE_SHIFT +#undef AFIFM4_AFIFM_RDQOS_VALUE_MASK +#define AFIFM4_AFIFM_RDQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM4_AFIFM_RDQOS_VALUE_SHIFT 0 +#define AFIFM4_AFIFM_RDQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM4_AFIFM_WRQOS_VALUE_DEFVAL +#undef AFIFM4_AFIFM_WRQOS_VALUE_SHIFT +#undef AFIFM4_AFIFM_WRQOS_VALUE_MASK +#define AFIFM4_AFIFM_WRQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM4_AFIFM_WRQOS_VALUE_SHIFT 0 +#define AFIFM4_AFIFM_WRQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM5_AFIFM_RDQOS_VALUE_DEFVAL +#undef AFIFM5_AFIFM_RDQOS_VALUE_SHIFT +#undef AFIFM5_AFIFM_RDQOS_VALUE_MASK +#define AFIFM5_AFIFM_RDQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM5_AFIFM_RDQOS_VALUE_SHIFT 0 +#define AFIFM5_AFIFM_RDQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM5_AFIFM_WRQOS_VALUE_DEFVAL +#undef AFIFM5_AFIFM_WRQOS_VALUE_SHIFT +#undef AFIFM5_AFIFM_WRQOS_VALUE_MASK +#define AFIFM5_AFIFM_WRQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM5_AFIFM_WRQOS_VALUE_SHIFT 0 +#define AFIFM5_AFIFM_WRQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM6_AFIFM_RDQOS_VALUE_DEFVAL +#undef AFIFM6_AFIFM_RDQOS_VALUE_SHIFT +#undef AFIFM6_AFIFM_RDQOS_VALUE_MASK +#define AFIFM6_AFIFM_RDQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM6_AFIFM_RDQOS_VALUE_SHIFT 0 +#define AFIFM6_AFIFM_RDQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM6_AFIFM_WRQOS_VALUE_DEFVAL +#undef AFIFM6_AFIFM_WRQOS_VALUE_SHIFT +#undef AFIFM6_AFIFM_WRQOS_VALUE_MASK +#define AFIFM6_AFIFM_WRQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM6_AFIFM_WRQOS_VALUE_SHIFT 0 +#define AFIFM6_AFIFM_WRQOS_VALUE_MASK 0x0000000FU +#undef IOU_SLCR_MIO_PIN_0_OFFSET +#define IOU_SLCR_MIO_PIN_0_OFFSET 0XFF180000 +#undef IOU_SLCR_MIO_PIN_1_OFFSET +#define IOU_SLCR_MIO_PIN_1_OFFSET 0XFF180004 +#undef IOU_SLCR_MIO_PIN_2_OFFSET +#define IOU_SLCR_MIO_PIN_2_OFFSET 0XFF180008 +#undef IOU_SLCR_MIO_PIN_3_OFFSET +#define IOU_SLCR_MIO_PIN_3_OFFSET 0XFF18000C +#undef IOU_SLCR_MIO_PIN_4_OFFSET +#define IOU_SLCR_MIO_PIN_4_OFFSET 0XFF180010 +#undef IOU_SLCR_MIO_PIN_5_OFFSET +#define IOU_SLCR_MIO_PIN_5_OFFSET 0XFF180014 +#undef IOU_SLCR_MIO_PIN_6_OFFSET +#define IOU_SLCR_MIO_PIN_6_OFFSET 0XFF180018 +#undef IOU_SLCR_MIO_PIN_7_OFFSET +#define IOU_SLCR_MIO_PIN_7_OFFSET 0XFF18001C +#undef IOU_SLCR_MIO_PIN_8_OFFSET +#define IOU_SLCR_MIO_PIN_8_OFFSET 0XFF180020 +#undef IOU_SLCR_MIO_PIN_9_OFFSET +#define IOU_SLCR_MIO_PIN_9_OFFSET 0XFF180024 +#undef IOU_SLCR_MIO_PIN_10_OFFSET +#define IOU_SLCR_MIO_PIN_10_OFFSET 0XFF180028 +#undef IOU_SLCR_MIO_PIN_11_OFFSET +#define IOU_SLCR_MIO_PIN_11_OFFSET 0XFF18002C +#undef IOU_SLCR_MIO_PIN_12_OFFSET +#define IOU_SLCR_MIO_PIN_12_OFFSET 0XFF180030 +#undef IOU_SLCR_MIO_PIN_13_OFFSET +#define IOU_SLCR_MIO_PIN_13_OFFSET 0XFF180034 +#undef IOU_SLCR_MIO_PIN_14_OFFSET +#define IOU_SLCR_MIO_PIN_14_OFFSET 0XFF180038 +#undef IOU_SLCR_MIO_PIN_15_OFFSET +#define IOU_SLCR_MIO_PIN_15_OFFSET 0XFF18003C +#undef IOU_SLCR_MIO_PIN_16_OFFSET +#define IOU_SLCR_MIO_PIN_16_OFFSET 0XFF180040 +#undef IOU_SLCR_MIO_PIN_17_OFFSET +#define IOU_SLCR_MIO_PIN_17_OFFSET 0XFF180044 +#undef IOU_SLCR_MIO_PIN_18_OFFSET +#define IOU_SLCR_MIO_PIN_18_OFFSET 0XFF180048 +#undef IOU_SLCR_MIO_PIN_19_OFFSET +#define IOU_SLCR_MIO_PIN_19_OFFSET 0XFF18004C +#undef IOU_SLCR_MIO_PIN_20_OFFSET +#define IOU_SLCR_MIO_PIN_20_OFFSET 0XFF180050 +#undef IOU_SLCR_MIO_PIN_21_OFFSET +#define IOU_SLCR_MIO_PIN_21_OFFSET 0XFF180054 +#undef IOU_SLCR_MIO_PIN_22_OFFSET +#define IOU_SLCR_MIO_PIN_22_OFFSET 0XFF180058 +#undef IOU_SLCR_MIO_PIN_23_OFFSET +#define IOU_SLCR_MIO_PIN_23_OFFSET 0XFF18005C +#undef IOU_SLCR_MIO_PIN_24_OFFSET +#define IOU_SLCR_MIO_PIN_24_OFFSET 0XFF180060 +#undef IOU_SLCR_MIO_PIN_25_OFFSET +#define IOU_SLCR_MIO_PIN_25_OFFSET 0XFF180064 +#undef IOU_SLCR_MIO_PIN_26_OFFSET +#define IOU_SLCR_MIO_PIN_26_OFFSET 0XFF180068 +#undef IOU_SLCR_MIO_PIN_27_OFFSET +#define IOU_SLCR_MIO_PIN_27_OFFSET 0XFF18006C +#undef IOU_SLCR_MIO_PIN_28_OFFSET +#define IOU_SLCR_MIO_PIN_28_OFFSET 0XFF180070 +#undef IOU_SLCR_MIO_PIN_29_OFFSET +#define IOU_SLCR_MIO_PIN_29_OFFSET 0XFF180074 +#undef IOU_SLCR_MIO_PIN_30_OFFSET +#define IOU_SLCR_MIO_PIN_30_OFFSET 0XFF180078 +#undef IOU_SLCR_MIO_PIN_31_OFFSET +#define IOU_SLCR_MIO_PIN_31_OFFSET 0XFF18007C +#undef IOU_SLCR_MIO_PIN_32_OFFSET +#define IOU_SLCR_MIO_PIN_32_OFFSET 0XFF180080 +#undef IOU_SLCR_MIO_PIN_33_OFFSET +#define IOU_SLCR_MIO_PIN_33_OFFSET 0XFF180084 +#undef IOU_SLCR_MIO_PIN_38_OFFSET +#define IOU_SLCR_MIO_PIN_38_OFFSET 0XFF180098 +#undef IOU_SLCR_MIO_PIN_39_OFFSET +#define IOU_SLCR_MIO_PIN_39_OFFSET 0XFF18009C +#undef IOU_SLCR_MIO_PIN_40_OFFSET +#define IOU_SLCR_MIO_PIN_40_OFFSET 0XFF1800A0 +#undef IOU_SLCR_MIO_PIN_41_OFFSET +#define IOU_SLCR_MIO_PIN_41_OFFSET 0XFF1800A4 +#undef IOU_SLCR_MIO_PIN_42_OFFSET +#define IOU_SLCR_MIO_PIN_42_OFFSET 0XFF1800A8 +#undef IOU_SLCR_MIO_PIN_43_OFFSET +#define IOU_SLCR_MIO_PIN_43_OFFSET 0XFF1800AC +#undef IOU_SLCR_MIO_PIN_44_OFFSET +#define IOU_SLCR_MIO_PIN_44_OFFSET 0XFF1800B0 +#undef IOU_SLCR_MIO_PIN_45_OFFSET +#define IOU_SLCR_MIO_PIN_45_OFFSET 0XFF1800B4 +#undef IOU_SLCR_MIO_PIN_46_OFFSET +#define IOU_SLCR_MIO_PIN_46_OFFSET 0XFF1800B8 +#undef IOU_SLCR_MIO_PIN_47_OFFSET +#define IOU_SLCR_MIO_PIN_47_OFFSET 0XFF1800BC +#undef IOU_SLCR_MIO_PIN_48_OFFSET +#define IOU_SLCR_MIO_PIN_48_OFFSET 0XFF1800C0 +#undef IOU_SLCR_MIO_PIN_49_OFFSET +#define IOU_SLCR_MIO_PIN_49_OFFSET 0XFF1800C4 +#undef IOU_SLCR_MIO_PIN_50_OFFSET +#define IOU_SLCR_MIO_PIN_50_OFFSET 0XFF1800C8 +#undef IOU_SLCR_MIO_PIN_51_OFFSET +#define IOU_SLCR_MIO_PIN_51_OFFSET 0XFF1800CC +#undef IOU_SLCR_MIO_PIN_52_OFFSET +#define IOU_SLCR_MIO_PIN_52_OFFSET 0XFF1800D0 +#undef IOU_SLCR_MIO_PIN_53_OFFSET +#define IOU_SLCR_MIO_PIN_53_OFFSET 0XFF1800D4 +#undef IOU_SLCR_MIO_PIN_54_OFFSET +#define IOU_SLCR_MIO_PIN_54_OFFSET 0XFF1800D8 +#undef IOU_SLCR_MIO_PIN_55_OFFSET +#define IOU_SLCR_MIO_PIN_55_OFFSET 0XFF1800DC +#undef IOU_SLCR_MIO_PIN_56_OFFSET +#define IOU_SLCR_MIO_PIN_56_OFFSET 0XFF1800E0 +#undef IOU_SLCR_MIO_PIN_57_OFFSET +#define IOU_SLCR_MIO_PIN_57_OFFSET 0XFF1800E4 +#undef IOU_SLCR_MIO_PIN_58_OFFSET +#define IOU_SLCR_MIO_PIN_58_OFFSET 0XFF1800E8 +#undef IOU_SLCR_MIO_PIN_59_OFFSET +#define IOU_SLCR_MIO_PIN_59_OFFSET 0XFF1800EC +#undef IOU_SLCR_MIO_PIN_60_OFFSET +#define IOU_SLCR_MIO_PIN_60_OFFSET 0XFF1800F0 +#undef IOU_SLCR_MIO_PIN_61_OFFSET +#define IOU_SLCR_MIO_PIN_61_OFFSET 0XFF1800F4 +#undef IOU_SLCR_MIO_PIN_62_OFFSET +#define IOU_SLCR_MIO_PIN_62_OFFSET 0XFF1800F8 +#undef IOU_SLCR_MIO_PIN_63_OFFSET +#define IOU_SLCR_MIO_PIN_63_OFFSET 0XFF1800FC +#undef IOU_SLCR_MIO_PIN_64_OFFSET +#define IOU_SLCR_MIO_PIN_64_OFFSET 0XFF180100 +#undef IOU_SLCR_MIO_PIN_65_OFFSET +#define IOU_SLCR_MIO_PIN_65_OFFSET 0XFF180104 +#undef IOU_SLCR_MIO_PIN_66_OFFSET +#define IOU_SLCR_MIO_PIN_66_OFFSET 0XFF180108 +#undef IOU_SLCR_MIO_PIN_67_OFFSET +#define IOU_SLCR_MIO_PIN_67_OFFSET 0XFF18010C +#undef IOU_SLCR_MIO_PIN_68_OFFSET +#define IOU_SLCR_MIO_PIN_68_OFFSET 0XFF180110 +#undef IOU_SLCR_MIO_PIN_69_OFFSET +#define IOU_SLCR_MIO_PIN_69_OFFSET 0XFF180114 +#undef IOU_SLCR_MIO_PIN_70_OFFSET +#define IOU_SLCR_MIO_PIN_70_OFFSET 0XFF180118 +#undef IOU_SLCR_MIO_PIN_71_OFFSET +#define IOU_SLCR_MIO_PIN_71_OFFSET 0XFF18011C +#undef IOU_SLCR_MIO_PIN_72_OFFSET +#define IOU_SLCR_MIO_PIN_72_OFFSET 0XFF180120 +#undef IOU_SLCR_MIO_PIN_73_OFFSET +#define IOU_SLCR_MIO_PIN_73_OFFSET 0XFF180124 +#undef IOU_SLCR_MIO_PIN_74_OFFSET +#define IOU_SLCR_MIO_PIN_74_OFFSET 0XFF180128 +#undef IOU_SLCR_MIO_PIN_75_OFFSET +#define IOU_SLCR_MIO_PIN_75_OFFSET 0XFF18012C +#undef IOU_SLCR_MIO_PIN_76_OFFSET +#define IOU_SLCR_MIO_PIN_76_OFFSET 0XFF180130 +#undef IOU_SLCR_MIO_PIN_77_OFFSET +#define IOU_SLCR_MIO_PIN_77_OFFSET 0XFF180134 +#undef IOU_SLCR_MIO_MST_TRI0_OFFSET +#define IOU_SLCR_MIO_MST_TRI0_OFFSET 0XFF180204 +#undef IOU_SLCR_MIO_MST_TRI1_OFFSET +#define IOU_SLCR_MIO_MST_TRI1_OFFSET 0XFF180208 +#undef IOU_SLCR_MIO_MST_TRI2_OFFSET +#define IOU_SLCR_MIO_MST_TRI2_OFFSET 0XFF18020C +#undef IOU_SLCR_BANK0_CTRL0_OFFSET +#define IOU_SLCR_BANK0_CTRL0_OFFSET 0XFF180138 +#undef IOU_SLCR_BANK0_CTRL1_OFFSET +#define IOU_SLCR_BANK0_CTRL1_OFFSET 0XFF18013C +#undef IOU_SLCR_BANK0_CTRL3_OFFSET +#define IOU_SLCR_BANK0_CTRL3_OFFSET 0XFF180140 +#undef IOU_SLCR_BANK0_CTRL4_OFFSET +#define IOU_SLCR_BANK0_CTRL4_OFFSET 0XFF180144 +#undef IOU_SLCR_BANK0_CTRL5_OFFSET +#define IOU_SLCR_BANK0_CTRL5_OFFSET 0XFF180148 +#undef IOU_SLCR_BANK0_CTRL6_OFFSET +#define IOU_SLCR_BANK0_CTRL6_OFFSET 0XFF18014C +#undef IOU_SLCR_BANK1_CTRL0_OFFSET +#define IOU_SLCR_BANK1_CTRL0_OFFSET 0XFF180154 +#undef IOU_SLCR_BANK1_CTRL1_OFFSET +#define IOU_SLCR_BANK1_CTRL1_OFFSET 0XFF180158 +#undef IOU_SLCR_BANK1_CTRL3_OFFSET +#define IOU_SLCR_BANK1_CTRL3_OFFSET 0XFF18015C +#undef IOU_SLCR_BANK1_CTRL4_OFFSET +#define IOU_SLCR_BANK1_CTRL4_OFFSET 0XFF180160 +#undef IOU_SLCR_BANK1_CTRL5_OFFSET +#define IOU_SLCR_BANK1_CTRL5_OFFSET 0XFF180164 +#undef IOU_SLCR_BANK1_CTRL6_OFFSET +#define IOU_SLCR_BANK1_CTRL6_OFFSET 0XFF180168 +#undef IOU_SLCR_BANK2_CTRL0_OFFSET +#define IOU_SLCR_BANK2_CTRL0_OFFSET 0XFF180170 +#undef IOU_SLCR_BANK2_CTRL1_OFFSET +#define IOU_SLCR_BANK2_CTRL1_OFFSET 0XFF180174 +#undef IOU_SLCR_BANK2_CTRL3_OFFSET +#define IOU_SLCR_BANK2_CTRL3_OFFSET 0XFF180178 +#undef IOU_SLCR_BANK2_CTRL4_OFFSET +#define IOU_SLCR_BANK2_CTRL4_OFFSET 0XFF18017C +#undef IOU_SLCR_BANK2_CTRL5_OFFSET +#define IOU_SLCR_BANK2_CTRL5_OFFSET 0XFF180180 +#undef IOU_SLCR_BANK2_CTRL6_OFFSET +#define IOU_SLCR_BANK2_CTRL6_OFFSET 0XFF180184 +#undef IOU_SLCR_MIO_LOOPBACK_OFFSET +#define IOU_SLCR_MIO_LOOPBACK_OFFSET 0XFF180200 + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- + * (QSPI Clock) +*/ +#undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) +*/ +#undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q + * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +*/ +#undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou + * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) +*/ +#undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI + * Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +*/ +#undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I + * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI + * Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +*/ +#undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- ( + * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +*/ +#undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- + * (QSPI Slave Select) +*/ +#undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l + * pbk- (QSPI Clock to be fed-back) +*/ +#undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s + * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT + * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, + * Output, tracedq[4]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_ + * upper- (QSPI Slave Select upper) +*/ +#undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma + * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua + * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t + * racedq[5]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D + * atabus) +*/ +#undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste + * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_ + * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra + * ce Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D + * atabus) +*/ +#undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) +*/ +#undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S + * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, + * Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA + * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D + * atabus) +*/ +#undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) +*/ +#undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 10]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D + * atabus) +*/ +#undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) +*/ +#undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 11]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_ + * upper- (QSPI Upper Clock) +*/ +#undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) +*/ +#undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 12]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT + * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_ + * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O + * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace + * dq[10]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA + * ND chip enable) +*/ +#undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, + * test_scan_out[13]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA + * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, + * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR + * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND + * Command Latch Enable) +*/ +#undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, + * test_scan_out[14]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT + * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, + * Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver + * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND + * Address Latch Enable) +*/ +#undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, + * test_scan_out[15]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT + * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp + * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou + * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria + * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, + * test_scan_out[16]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, + * test_scan_out[17]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, + * test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, + * test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, + * test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua + * 1_txd- (UART transmitter serial output) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes + * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t + * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E + * xt Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc + * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- ( + * UART receiver serial input) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN + * D Write Enable) +*/ +#undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = + * test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c + * su_ext_tamper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed +*/ +#undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po + * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp + * ut, csu_ext_tamper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test + * Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= + * csu, Input, csu_ext_tamper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N + * ot Used +*/ +#undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN + * D Read Enable) +*/ +#undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]- + * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port + * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou + * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in + * put) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * clk- (TX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) +*/ +#undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [0]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) +*/ +#undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ +#undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) +*/ +#undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [1]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) +*/ +#undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) +*/ +#undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [2]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ +#undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ +#undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, + * spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [3]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ +#undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) +*/ +#undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0 + * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock + * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, + * tracedq[8]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * ctl- (TX RGMII control) +*/ +#undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ +#undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT + * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp + * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * lk- (RX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) +*/ +#undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t + * race, Output, tracedq[10]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ +#undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas + * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1 + * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq + * [11]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * clk- (TX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA + * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s + * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In + * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- + * (Trace Port Clock) +*/ +#undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [0]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b + * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT + * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, + * Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U + * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port + * Control Signal) +*/ +#undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [1]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1 + * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[ + * 5]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ + * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3 + * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi + * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [2]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[6]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA + * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu + * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out + * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp + * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [3]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[7]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp + * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[2]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * ctl- (TX RGMII control) +*/ +#undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) + * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * lk- (RX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4 + * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * Not Used +*/ +#undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste + * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt + * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us + * ed +*/ +#undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * tl- (RX RGMII control ) +*/ +#undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd + * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) +*/ +#undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind + * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= + * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece + * iver serial input) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) +*/ +#undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi + * o1_clk_out- (SDSDIO clock) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat + * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa + * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter + * serial output) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * clk- (TX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i + * n- (ULPI Clock) +*/ +#undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) +*/ +#undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [0]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- + * (Data bus direction control) +*/ +#undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou + * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) +*/ +#undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [1]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I + * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [2]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- + * (Data flow control signal from the PHY) +*/ +#undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [3]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * ctl- (TX RGMII control) +*/ +#undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * lk- (RX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- + * (Asserted to end or interrupt transfers) +*/ +#undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) +*/ +#undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, + * spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * tl- (RX RGMII control ) +*/ +#undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * clk- (TX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i + * n- (ULPI Clock) +*/ +#undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4 + * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * trace, Output, tracedq[10]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [0]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- + * (Data bus direction control) +*/ +#undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= Not Used 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace + * dq[11]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [1]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not + * Used 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace + * Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [2]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- + * (Data flow control signal from the PHY) +*/ +#undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N + * ot Used 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste + * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt + * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace + * Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [3]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N + * ot Used 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * ctl- (TX RGMII control) +*/ +#undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * lk- (RX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- + * (Asserted to end or interrupt transfers) +*/ +#undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed +*/ +#undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri + * al output) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not + * Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[3]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- ( + * UART receiver serial input) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * tl- (RX RGMII control ) +*/ +#undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1 + * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t + * xd- (UART transmitter serial output) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO + * clock) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI + * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2 + * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio + * 1_cd_n- (SD card detect from connector) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M + * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, + * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5 + * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou + * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp + * ut, gem3_mdio_out- (MDIO Data) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000E0U + +/* +* Master Tri-state Enable for pin 0, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001U + +/* +* Master Tri-state Enable for pin 1, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002U + +/* +* Master Tri-state Enable for pin 2, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004U + +/* +* Master Tri-state Enable for pin 3, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008U + +/* +* Master Tri-state Enable for pin 4, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010U + +/* +* Master Tri-state Enable for pin 5, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020U + +/* +* Master Tri-state Enable for pin 6, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040U + +/* +* Master Tri-state Enable for pin 7, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080U + +/* +* Master Tri-state Enable for pin 8, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100U + +/* +* Master Tri-state Enable for pin 9, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200U + +/* +* Master Tri-state Enable for pin 10, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400U + +/* +* Master Tri-state Enable for pin 11, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800U + +/* +* Master Tri-state Enable for pin 12, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000U + +/* +* Master Tri-state Enable for pin 13, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000U + +/* +* Master Tri-state Enable for pin 14, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14 +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000U + +/* +* Master Tri-state Enable for pin 15, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15 +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000U + +/* +* Master Tri-state Enable for pin 16, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16 +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000U + +/* +* Master Tri-state Enable for pin 17, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17 +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000U + +/* +* Master Tri-state Enable for pin 18, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18 +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000U + +/* +* Master Tri-state Enable for pin 19, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19 +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000U + +/* +* Master Tri-state Enable for pin 20, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20 +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000U + +/* +* Master Tri-state Enable for pin 21, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21 +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000U + +/* +* Master Tri-state Enable for pin 22, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22 +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000U + +/* +* Master Tri-state Enable for pin 23, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23 +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000U + +/* +* Master Tri-state Enable for pin 24, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24 +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000U + +/* +* Master Tri-state Enable for pin 25, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25 +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000U + +/* +* Master Tri-state Enable for pin 26, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26 +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000U + +/* +* Master Tri-state Enable for pin 27, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27 +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000U + +/* +* Master Tri-state Enable for pin 28, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28 +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000U + +/* +* Master Tri-state Enable for pin 29, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29 +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000U + +/* +* Master Tri-state Enable for pin 30, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30 +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000U + +/* +* Master Tri-state Enable for pin 31, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31 +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000U + +/* +* Master Tri-state Enable for pin 32, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001U + +/* +* Master Tri-state Enable for pin 33, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002U + +/* +* Master Tri-state Enable for pin 34, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004U + +/* +* Master Tri-state Enable for pin 35, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008U + +/* +* Master Tri-state Enable for pin 36, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010U + +/* +* Master Tri-state Enable for pin 37, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020U + +/* +* Master Tri-state Enable for pin 38, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040U + +/* +* Master Tri-state Enable for pin 39, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080U + +/* +* Master Tri-state Enable for pin 40, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100U + +/* +* Master Tri-state Enable for pin 41, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200U + +/* +* Master Tri-state Enable for pin 42, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400U + +/* +* Master Tri-state Enable for pin 43, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800U + +/* +* Master Tri-state Enable for pin 44, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000U + +/* +* Master Tri-state Enable for pin 45, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000U + +/* +* Master Tri-state Enable for pin 46, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14 +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000U + +/* +* Master Tri-state Enable for pin 47, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15 +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000U + +/* +* Master Tri-state Enable for pin 48, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16 +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000U + +/* +* Master Tri-state Enable for pin 49, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17 +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000U + +/* +* Master Tri-state Enable for pin 50, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18 +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000U + +/* +* Master Tri-state Enable for pin 51, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19 +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000U + +/* +* Master Tri-state Enable for pin 52, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20 +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000U + +/* +* Master Tri-state Enable for pin 53, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21 +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000U + +/* +* Master Tri-state Enable for pin 54, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22 +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000U + +/* +* Master Tri-state Enable for pin 55, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23 +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000U + +/* +* Master Tri-state Enable for pin 56, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24 +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000U + +/* +* Master Tri-state Enable for pin 57, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25 +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000U + +/* +* Master Tri-state Enable for pin 58, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26 +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000U + +/* +* Master Tri-state Enable for pin 59, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27 +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000U + +/* +* Master Tri-state Enable for pin 60, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28 +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000U + +/* +* Master Tri-state Enable for pin 61, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29 +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000U + +/* +* Master Tri-state Enable for pin 62, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30 +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000U + +/* +* Master Tri-state Enable for pin 63, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31 +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000U + +/* +* Master Tri-state Enable for pin 64, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001U + +/* +* Master Tri-state Enable for pin 65, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002U + +/* +* Master Tri-state Enable for pin 66, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004U + +/* +* Master Tri-state Enable for pin 67, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008U + +/* +* Master Tri-state Enable for pin 68, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010U + +/* +* Master Tri-state Enable for pin 69, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020U + +/* +* Master Tri-state Enable for pin 70, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040U + +/* +* Master Tri-state Enable for pin 71, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080U + +/* +* Master Tri-state Enable for pin 72, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100U + +/* +* Master Tri-state Enable for pin 73, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200U + +/* +* Master Tri-state Enable for pin 74, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400U + +/* +* Master Tri-state Enable for pin 75, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800U + +/* +* Master Tri-state Enable for pin 76, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000U + +/* +* Master Tri-state Enable for pin 77, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U + +/* +* I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 + * = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs + * . +*/ +#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL +#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT +#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 3 +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 0x00000008U + +/* +* CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 + * = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. +*/ +#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL +#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT +#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 2 +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 0x00000004U + +/* +* UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. + * 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 + * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD + * and RI not used. +*/ +#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL +#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT +#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 1 +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 0x00000002U + +/* +* SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 + * = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs + * . The other SPI core will appear on the LS Slave Select. +*/ +#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL +#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT +#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0 +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U +#undef CRL_APB_AMS_REF_CTRL_OFFSET +#define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 + +/* +* 6 bit divider +*/ +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK +#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK +#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0 +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef CRL_APB_RST_LPD_IOU0_OFFSET +#define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET +#define IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET 0XFF180390 +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef IOU_SLCR_CTRL_REG_SD_OFFSET +#define IOU_SLCR_CTRL_REG_SD_OFFSET 0XFF180310 +#undef IOU_SLCR_SD_CONFIG_REG2_OFFSET +#define IOU_SLCR_SD_CONFIG_REG2_OFFSET 0XFF180320 +#undef IOU_SLCR_SD_CONFIG_REG1_OFFSET +#define IOU_SLCR_SD_CONFIG_REG1_OFFSET 0XFF18031C +#undef IOU_SLCR_SD_DLL_CTRL_OFFSET +#define IOU_SLCR_SD_DLL_CTRL_OFFSET 0XFF180358 +#undef IOU_SLCR_SD_CONFIG_REG3_OFFSET +#define IOU_SLCR_SD_CONFIG_REG3_OFFSET 0XFF180324 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET +#define UART0_BAUD_RATE_DIVIDER_REG0_OFFSET 0XFF000034 +#undef UART0_BAUD_RATE_GEN_REG0_OFFSET +#define UART0_BAUD_RATE_GEN_REG0_OFFSET 0XFF000018 +#undef UART0_CONTROL_REG0_OFFSET +#define UART0_CONTROL_REG0_OFFSET 0XFF000000 +#undef UART0_MODE_REG0_OFFSET +#define UART0_MODE_REG0_OFFSET 0XFF000004 +#undef UART1_BAUD_RATE_DIVIDER_REG0_OFFSET +#define UART1_BAUD_RATE_DIVIDER_REG0_OFFSET 0XFF010034 +#undef UART1_BAUD_RATE_GEN_REG0_OFFSET +#define UART1_BAUD_RATE_GEN_REG0_OFFSET 0XFF010018 +#undef UART1_CONTROL_REG0_OFFSET +#define UART1_CONTROL_REG0_OFFSET 0XFF010000 +#undef UART1_MODE_REG0_OFFSET +#define UART1_MODE_REG0_OFFSET 0XFF010004 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET +#define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024 +#undef CSU_TAMPER_STATUS_OFFSET +#define CSU_TAMPER_STATUS_OFFSET 0XFFCA5000 +#undef APU_ACE_CTRL_OFFSET +#define APU_ACE_CTRL_OFFSET 0XFD5C0060 +#undef RTC_CONTROL_OFFSET +#define RTC_CONTROL_OFFSET 0XFFA60040 +#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET 0XFF260020 +#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET 0XFF260000 +#undef CRL_APB_BOOT_PIN_CTRL_OFFSET +#define CRL_APB_BOOT_PIN_CTRL_OFFSET 0XFF5E0250 +#undef CRL_APB_BOOT_PIN_CTRL_OFFSET +#define CRL_APB_BOOT_PIN_CTRL_OFFSET 0XFF5E0250 +#undef CRL_APB_BOOT_PIN_CTRL_OFFSET +#define CRL_APB_BOOT_PIN_CTRL_OFFSET 0XFF5E0250 +#undef GPIO_DIRM_1_OFFSET +#define GPIO_DIRM_1_OFFSET 0XFF0A0244 +#undef GPIO_OEN_1_OFFSET +#define GPIO_OEN_1_OFFSET 0XFF0A0248 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 +#undef GPIO_DIRM_1_OFFSET +#define GPIO_DIRM_1_OFFSET 0XFF0A0244 +#undef GPIO_OEN_1_OFFSET +#define GPIO_OEN_1_OFFSET 0XFF0A0248 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 + +/* +* PCIE config reset +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U + +/* +* PCIE control block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U + +/* +* PCIE bridge block level reset (AXI interface) +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U + +/* +* Display Port block level reset (includes DPDMA) +*/ +#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U + +/* +* FPD WDT reset +*/ +#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 15 +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 0x00008000U + +/* +* GDMA block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 6 +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 0x00000040U + +/* +* Pixel Processor (submodule of GPU) block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 4 +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 0x00000010U + +/* +* Pixel Processor (submodule of GPU) block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 5 +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 0x00000020U + +/* +* GPU block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK +#define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 3 +#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 0x00000008U + +/* +* GT block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK +#define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 2 +#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK 0x00000004U + +/* +* Sata block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20 +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 0x00100000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT 19 +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK 0x00080000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT 17 +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK 0x00020000U + +/* +* Reset entire full power domain. +*/ +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_MASK +#define CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT 23 +#define CRL_APB_RST_LPD_TOP_FPD_RESET_MASK 0x00800000U + +/* +* LPD SWDT +*/ +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT 20 +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK 0x00100000U + +/* +* Sysmonitor reset +*/ +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT 17 +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK 0x00020000U + +/* +* Real Time Clock reset +*/ +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_MASK +#define CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT 16 +#define CRL_APB_RST_LPD_TOP_RTC_RESET_MASK 0x00010000U + +/* +* APM reset +*/ +#undef CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_APM_RESET_MASK +#define CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT 15 +#define CRL_APB_RST_LPD_TOP_APM_RESET_MASK 0x00008000U + +/* +* IPI reset +*/ +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_MASK +#define CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT 14 +#define CRL_APB_RST_LPD_TOP_IPI_RESET_MASK 0x00004000U + +/* +* reset entire RPU power island +*/ +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT 4 +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK 0x00000010U + +/* +* reset ocm +*/ +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_MASK +#define CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_TOP_OCM_RESET_MASK 0x00000008U + +/* +* GEM 3 reset +*/ +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0 +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U + +/* +* 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa + * ss the Tap delay on the Rx clock signal of LQSPI +*/ +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x00000007 +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2 +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U + +/* +* USB 0 reset for control registers +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 6 +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 0x00000040U + +/* +* SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled +*/ +#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL +#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT +#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 15 +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 0x00008000U + +/* +* Should be set based on the final product usage 00 - Removable SCard Slot + * 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved +*/ +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 28 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 0x30000000U + +/* +* 8-bit Support for Embedded Device 1: The Core supports 8-bit Interface 0 + * : Supports only 4-bit SD Interface +*/ +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_8BIT_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_8BIT_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_8BIT_MASK +#define IOU_SLCR_SD_CONFIG_REG2_SD1_8BIT_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_8BIT_SHIFT 18 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_8BIT_MASK 0x00040000U + +/* +* 1.8V Support 1: 1.8V supported 0: 1.8V not supported support +*/ +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 25 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 0x02000000U + +/* +* 3.0V Support 1: 3.0V supported 0: 3.0V not supported support +*/ +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 24 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 0x01000000U + +/* +* 3.3V Support 1: 3.3V supported 0: 3.3V not supported support +*/ +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 23 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 0x00800000U + +/* +* Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. +*/ +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 0x32403240 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 23 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 0x7F800000U + +/* +* Configures the Number of Taps (Phases) of the rxclk_in that is supported + * . +*/ +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL 0x32403240 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT 17 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK 0x007E0000U + +/* +* Reserved. +*/ +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL 0x00080008 +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT 3 +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK 0x00000008U + +/* +* This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S + * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other + * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n + * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved +*/ +#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 0x06070607 +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 22 +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 0x03C00000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8 +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 0x00000100U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9 +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 0x00000200U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 0x00000400U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 15 +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 0x00008000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11 +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 0x00000800U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12 +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 0x00001000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13 +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 0x00002000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14 +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1 +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 0x00000002U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2 +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 0x00000004U + +/* +* Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +*/ +#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL +#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT +#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU + +/* +* Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +*/ +#undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL +#undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT +#undef UART0_BAUD_RATE_GEN_REG0_CD_MASK +#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B +#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0 +#define UART0_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU + +/* +* Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. +*/ +#undef UART0_CONTROL_REG0_STPBRK_DEFVAL +#undef UART0_CONTROL_REG0_STPBRK_SHIFT +#undef UART0_CONTROL_REG0_STPBRK_MASK +#define UART0_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_STPBRK_SHIFT 8 +#define UART0_CONTROL_REG0_STPBRK_MASK 0x00000100U + +/* +* Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. +*/ +#undef UART0_CONTROL_REG0_STTBRK_DEFVAL +#undef UART0_CONTROL_REG0_STTBRK_SHIFT +#undef UART0_CONTROL_REG0_STTBRK_MASK +#define UART0_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_STTBRK_SHIFT 7 +#define UART0_CONTROL_REG0_STTBRK_MASK 0x00000080U + +/* +* Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. +*/ +#undef UART0_CONTROL_REG0_RSTTO_DEFVAL +#undef UART0_CONTROL_REG0_RSTTO_SHIFT +#undef UART0_CONTROL_REG0_RSTTO_MASK +#define UART0_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RSTTO_SHIFT 6 +#define UART0_CONTROL_REG0_RSTTO_MASK 0x00000040U + +/* +* Transmit disable: 0: enable transmitter 1: disable transmitter +*/ +#undef UART0_CONTROL_REG0_TXDIS_DEFVAL +#undef UART0_CONTROL_REG0_TXDIS_SHIFT +#undef UART0_CONTROL_REG0_TXDIS_MASK +#define UART0_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXDIS_SHIFT 5 +#define UART0_CONTROL_REG0_TXDIS_MASK 0x00000020U + +/* +* Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. +*/ +#undef UART0_CONTROL_REG0_TXEN_DEFVAL +#undef UART0_CONTROL_REG0_TXEN_SHIFT +#undef UART0_CONTROL_REG0_TXEN_MASK +#define UART0_CONTROL_REG0_TXEN_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXEN_SHIFT 4 +#define UART0_CONTROL_REG0_TXEN_MASK 0x00000010U + +/* +* Receive disable: 0: enable 1: disable, regardless of the value of RXEN +*/ +#undef UART0_CONTROL_REG0_RXDIS_DEFVAL +#undef UART0_CONTROL_REG0_RXDIS_SHIFT +#undef UART0_CONTROL_REG0_RXDIS_MASK +#define UART0_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXDIS_SHIFT 3 +#define UART0_CONTROL_REG0_RXDIS_MASK 0x00000008U + +/* +* Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. +*/ +#undef UART0_CONTROL_REG0_RXEN_DEFVAL +#undef UART0_CONTROL_REG0_RXEN_SHIFT +#undef UART0_CONTROL_REG0_RXEN_MASK +#define UART0_CONTROL_REG0_RXEN_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXEN_SHIFT 2 +#define UART0_CONTROL_REG0_RXEN_MASK 0x00000004U + +/* +* Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. +*/ +#undef UART0_CONTROL_REG0_TXRES_DEFVAL +#undef UART0_CONTROL_REG0_TXRES_SHIFT +#undef UART0_CONTROL_REG0_TXRES_MASK +#define UART0_CONTROL_REG0_TXRES_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXRES_SHIFT 1 +#define UART0_CONTROL_REG0_TXRES_MASK 0x00000002U + +/* +* Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. +*/ +#undef UART0_CONTROL_REG0_RXRES_DEFVAL +#undef UART0_CONTROL_REG0_RXRES_SHIFT +#undef UART0_CONTROL_REG0_RXRES_MASK +#define UART0_CONTROL_REG0_RXRES_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXRES_SHIFT 0 +#define UART0_CONTROL_REG0_RXRES_MASK 0x00000001U + +/* +* Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback +*/ +#undef UART0_MODE_REG0_CHMODE_DEFVAL +#undef UART0_MODE_REG0_CHMODE_SHIFT +#undef UART0_MODE_REG0_CHMODE_MASK +#define UART0_MODE_REG0_CHMODE_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CHMODE_SHIFT 8 +#define UART0_MODE_REG0_CHMODE_MASK 0x00000300U + +/* +* Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved +*/ +#undef UART0_MODE_REG0_NBSTOP_DEFVAL +#undef UART0_MODE_REG0_NBSTOP_SHIFT +#undef UART0_MODE_REG0_NBSTOP_MASK +#define UART0_MODE_REG0_NBSTOP_DEFVAL 0x00000000 +#define UART0_MODE_REG0_NBSTOP_SHIFT 6 +#define UART0_MODE_REG0_NBSTOP_MASK 0x000000C0U + +/* +* Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty +*/ +#undef UART0_MODE_REG0_PAR_DEFVAL +#undef UART0_MODE_REG0_PAR_SHIFT +#undef UART0_MODE_REG0_PAR_MASK +#define UART0_MODE_REG0_PAR_DEFVAL 0x00000000 +#define UART0_MODE_REG0_PAR_SHIFT 3 +#define UART0_MODE_REG0_PAR_MASK 0x00000038U + +/* +* Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits +*/ +#undef UART0_MODE_REG0_CHRL_DEFVAL +#undef UART0_MODE_REG0_CHRL_SHIFT +#undef UART0_MODE_REG0_CHRL_MASK +#define UART0_MODE_REG0_CHRL_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CHRL_SHIFT 1 +#define UART0_MODE_REG0_CHRL_MASK 0x00000006U + +/* +* Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 +*/ +#undef UART0_MODE_REG0_CLKS_DEFVAL +#undef UART0_MODE_REG0_CLKS_SHIFT +#undef UART0_MODE_REG0_CLKS_MASK +#define UART0_MODE_REG0_CLKS_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CLKS_SHIFT 0 +#define UART0_MODE_REG0_CLKS_MASK 0x00000001U + +/* +* Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +*/ +#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL +#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT +#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU + +/* +* Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +*/ +#undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL +#undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT +#undef UART1_BAUD_RATE_GEN_REG0_CD_MASK +#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B +#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0 +#define UART1_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU + +/* +* Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. +*/ +#undef UART1_CONTROL_REG0_STPBRK_DEFVAL +#undef UART1_CONTROL_REG0_STPBRK_SHIFT +#undef UART1_CONTROL_REG0_STPBRK_MASK +#define UART1_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_STPBRK_SHIFT 8 +#define UART1_CONTROL_REG0_STPBRK_MASK 0x00000100U + +/* +* Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. +*/ +#undef UART1_CONTROL_REG0_STTBRK_DEFVAL +#undef UART1_CONTROL_REG0_STTBRK_SHIFT +#undef UART1_CONTROL_REG0_STTBRK_MASK +#define UART1_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_STTBRK_SHIFT 7 +#define UART1_CONTROL_REG0_STTBRK_MASK 0x00000080U + +/* +* Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. +*/ +#undef UART1_CONTROL_REG0_RSTTO_DEFVAL +#undef UART1_CONTROL_REG0_RSTTO_SHIFT +#undef UART1_CONTROL_REG0_RSTTO_MASK +#define UART1_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RSTTO_SHIFT 6 +#define UART1_CONTROL_REG0_RSTTO_MASK 0x00000040U + +/* +* Transmit disable: 0: enable transmitter 1: disable transmitter +*/ +#undef UART1_CONTROL_REG0_TXDIS_DEFVAL +#undef UART1_CONTROL_REG0_TXDIS_SHIFT +#undef UART1_CONTROL_REG0_TXDIS_MASK +#define UART1_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXDIS_SHIFT 5 +#define UART1_CONTROL_REG0_TXDIS_MASK 0x00000020U + +/* +* Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. +*/ +#undef UART1_CONTROL_REG0_TXEN_DEFVAL +#undef UART1_CONTROL_REG0_TXEN_SHIFT +#undef UART1_CONTROL_REG0_TXEN_MASK +#define UART1_CONTROL_REG0_TXEN_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXEN_SHIFT 4 +#define UART1_CONTROL_REG0_TXEN_MASK 0x00000010U + +/* +* Receive disable: 0: enable 1: disable, regardless of the value of RXEN +*/ +#undef UART1_CONTROL_REG0_RXDIS_DEFVAL +#undef UART1_CONTROL_REG0_RXDIS_SHIFT +#undef UART1_CONTROL_REG0_RXDIS_MASK +#define UART1_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXDIS_SHIFT 3 +#define UART1_CONTROL_REG0_RXDIS_MASK 0x00000008U + +/* +* Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. +*/ +#undef UART1_CONTROL_REG0_RXEN_DEFVAL +#undef UART1_CONTROL_REG0_RXEN_SHIFT +#undef UART1_CONTROL_REG0_RXEN_MASK +#define UART1_CONTROL_REG0_RXEN_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXEN_SHIFT 2 +#define UART1_CONTROL_REG0_RXEN_MASK 0x00000004U + +/* +* Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. +*/ +#undef UART1_CONTROL_REG0_TXRES_DEFVAL +#undef UART1_CONTROL_REG0_TXRES_SHIFT +#undef UART1_CONTROL_REG0_TXRES_MASK +#define UART1_CONTROL_REG0_TXRES_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXRES_SHIFT 1 +#define UART1_CONTROL_REG0_TXRES_MASK 0x00000002U + +/* +* Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. +*/ +#undef UART1_CONTROL_REG0_RXRES_DEFVAL +#undef UART1_CONTROL_REG0_RXRES_SHIFT +#undef UART1_CONTROL_REG0_RXRES_MASK +#define UART1_CONTROL_REG0_RXRES_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXRES_SHIFT 0 +#define UART1_CONTROL_REG0_RXRES_MASK 0x00000001U + +/* +* Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback +*/ +#undef UART1_MODE_REG0_CHMODE_DEFVAL +#undef UART1_MODE_REG0_CHMODE_SHIFT +#undef UART1_MODE_REG0_CHMODE_MASK +#define UART1_MODE_REG0_CHMODE_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CHMODE_SHIFT 8 +#define UART1_MODE_REG0_CHMODE_MASK 0x00000300U + +/* +* Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved +*/ +#undef UART1_MODE_REG0_NBSTOP_DEFVAL +#undef UART1_MODE_REG0_NBSTOP_SHIFT +#undef UART1_MODE_REG0_NBSTOP_MASK +#define UART1_MODE_REG0_NBSTOP_DEFVAL 0x00000000 +#define UART1_MODE_REG0_NBSTOP_SHIFT 6 +#define UART1_MODE_REG0_NBSTOP_MASK 0x000000C0U + +/* +* Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty +*/ +#undef UART1_MODE_REG0_PAR_DEFVAL +#undef UART1_MODE_REG0_PAR_SHIFT +#undef UART1_MODE_REG0_PAR_MASK +#define UART1_MODE_REG0_PAR_DEFVAL 0x00000000 +#define UART1_MODE_REG0_PAR_SHIFT 3 +#define UART1_MODE_REG0_PAR_MASK 0x00000038U + +/* +* Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits +*/ +#undef UART1_MODE_REG0_CHRL_DEFVAL +#undef UART1_MODE_REG0_CHRL_SHIFT +#undef UART1_MODE_REG0_CHRL_MASK +#define UART1_MODE_REG0_CHRL_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CHRL_SHIFT 1 +#define UART1_MODE_REG0_CHRL_MASK 0x00000006U + +/* +* Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 +*/ +#undef UART1_MODE_REG0_CLKS_DEFVAL +#undef UART1_MODE_REG0_CLKS_SHIFT +#undef UART1_MODE_REG0_CLKS_MASK +#define UART1_MODE_REG0_CLKS_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CLKS_SHIFT 0 +#define UART1_MODE_REG0_CLKS_MASK 0x00000001U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT 18 +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK 0x00040000U + +/* +* TrustZone Classification for ADMA +*/ +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU + +/* +* CSU regsiter +*/ +#undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_0_MASK +#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT 0 +#define CSU_TAMPER_STATUS_TAMPER_0_MASK 0x00000001U + +/* +* External MIO +*/ +#undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_1_MASK +#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT 1 +#define CSU_TAMPER_STATUS_TAMPER_1_MASK 0x00000002U + +/* +* JTAG toggle detect +*/ +#undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_2_MASK +#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT 2 +#define CSU_TAMPER_STATUS_TAMPER_2_MASK 0x00000004U + +/* +* PL SEU error +*/ +#undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_3_MASK +#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT 3 +#define CSU_TAMPER_STATUS_TAMPER_3_MASK 0x00000008U + +/* +* AMS over temperature alarm for LPD +*/ +#undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_4_MASK +#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT 4 +#define CSU_TAMPER_STATUS_TAMPER_4_MASK 0x00000010U + +/* +* AMS over temperature alarm for APU +*/ +#undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_5_MASK +#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT 5 +#define CSU_TAMPER_STATUS_TAMPER_5_MASK 0x00000020U + +/* +* AMS voltage alarm for VCCPINT_FPD +*/ +#undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_6_MASK +#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT 6 +#define CSU_TAMPER_STATUS_TAMPER_6_MASK 0x00000040U + +/* +* AMS voltage alarm for VCCPINT_LPD +*/ +#undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_7_MASK +#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT 7 +#define CSU_TAMPER_STATUS_TAMPER_7_MASK 0x00000080U + +/* +* AMS voltage alarm for VCCPAUX +*/ +#undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_8_MASK +#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT 8 +#define CSU_TAMPER_STATUS_TAMPER_8_MASK 0x00000100U + +/* +* AMS voltage alarm for DDRPHY +*/ +#undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_9_MASK +#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT 9 +#define CSU_TAMPER_STATUS_TAMPER_9_MASK 0x00000200U + +/* +* AMS voltage alarm for PSIO bank 0/1/2 +*/ +#undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_10_MASK +#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT 10 +#define CSU_TAMPER_STATUS_TAMPER_10_MASK 0x00000400U + +/* +* AMS voltage alarm for PSIO bank 3 (dedicated pins) +*/ +#undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_11_MASK +#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT 11 +#define CSU_TAMPER_STATUS_TAMPER_11_MASK 0x00000800U + +/* +* AMS voltaage alarm for GT +*/ +#undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_12_MASK +#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT 12 +#define CSU_TAMPER_STATUS_TAMPER_12_MASK 0x00001000U + +/* +* Set ACE outgoing AWQOS value +*/ +#undef APU_ACE_CTRL_AWQOS_DEFVAL +#undef APU_ACE_CTRL_AWQOS_SHIFT +#undef APU_ACE_CTRL_AWQOS_MASK +#define APU_ACE_CTRL_AWQOS_DEFVAL 0x000F000F +#define APU_ACE_CTRL_AWQOS_SHIFT 16 +#define APU_ACE_CTRL_AWQOS_MASK 0x000F0000U + +/* +* Set ACE outgoing ARQOS value +*/ +#undef APU_ACE_CTRL_ARQOS_DEFVAL +#undef APU_ACE_CTRL_ARQOS_SHIFT +#undef APU_ACE_CTRL_ARQOS_MASK +#define APU_ACE_CTRL_ARQOS_DEFVAL 0x000F000F +#define APU_ACE_CTRL_ARQOS_SHIFT 0 +#define APU_ACE_CTRL_ARQOS_MASK 0x0000000FU + +/* +* Enables the RTC. By writing a 0 to this bit, RTC will be powered off and + * the only module that potentially draws current from the battery will be + * BBRAM. The value read through this bit does not necessarily reflect whe + * ther RTC is enabled or not. It is expected that RTC is enabled every tim + * e it is being configured. If RTC is not used in the design, FSBL will di + * sable it by writing a 0 to this bit. +*/ +#undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL +#undef RTC_CONTROL_BATTERY_DISABLE_SHIFT +#undef RTC_CONTROL_BATTERY_DISABLE_MASK +#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL 0x01000000 +#define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31 +#define RTC_CONTROL_BATTERY_DISABLE_MASK 0x80000000U + +/* +* Frequency in number of ticks per second. Valid range from 10 MHz to 100 + * MHz. +*/ +#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL +#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT +#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 0 +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 0xFFFFFFFFU + +/* +* Enable 0: The counter is disabled and not incrementing. 1: The counter i + * s enabled and is incrementing. +*/ +#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL +#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT +#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 0x00000000 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 0 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 0x00000001U + +/* +* Value driven onto the mode pins, when out_en = 1 +*/ +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_DEFVAL +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_MASK +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_DEFVAL 0x00000000 +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_MASK 0x00000F00U + +/* +* When 0, the pins will be inputs from the board to the PS. When 1, the PS + * will drive these pins +*/ +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_DEFVAL +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_MASK +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_DEFVAL 0x00000000 +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_MASK 0x0000000FU + +/* +* Value driven onto the mode pins, when out_en = 1 +*/ +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_DEFVAL +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_MASK +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_DEFVAL 0x00000000 +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_MASK 0x00000F00U + +/* +* When 0, the pins will be inputs from the board to the PS. When 1, the PS + * will drive these pins +*/ +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_DEFVAL +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_MASK +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_DEFVAL 0x00000000 +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_MASK 0x0000000FU + +/* +* Value driven onto the mode pins, when out_en = 1 +*/ +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_DEFVAL +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_MASK +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_DEFVAL 0x00000000 +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_MASK 0x00000F00U + +/* +* When 0, the pins will be inputs from the board to the PS. When 1, the PS + * will drive these pins +*/ +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_DEFVAL +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_MASK +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_DEFVAL 0x00000000 +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_MASK 0x0000000FU + +/* +* Operation is the same as DIRM_0[DIRECTION_0] +*/ +#undef GPIO_DIRM_1_DIRECTION_1_DEFVAL +#undef GPIO_DIRM_1_DIRECTION_1_SHIFT +#undef GPIO_DIRM_1_DIRECTION_1_MASK +#define GPIO_DIRM_1_DIRECTION_1_DEFVAL 0x00000000 +#define GPIO_DIRM_1_DIRECTION_1_SHIFT 0 +#define GPIO_DIRM_1_DIRECTION_1_MASK 0x03FFFFFFU + +/* +* Operation is the same as OEN_0[OP_ENABLE_0] +*/ +#undef GPIO_OEN_1_OP_ENABLE_1_DEFVAL +#undef GPIO_OEN_1_OP_ENABLE_1_SHIFT +#undef GPIO_OEN_1_OP_ENABLE_1_MASK +#define GPIO_OEN_1_OP_ENABLE_1_DEFVAL 0x00000000 +#define GPIO_OEN_1_OP_ENABLE_1_SHIFT 0 +#define GPIO_OEN_1_OP_ENABLE_1_MASK 0x03FFFFFFU + +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U + +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU + +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U + +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU + +/* +* Operation is the same as DIRM_0[DIRECTION_0] +*/ +#undef GPIO_DIRM_1_DIRECTION_1_DEFVAL +#undef GPIO_DIRM_1_DIRECTION_1_SHIFT +#undef GPIO_DIRM_1_DIRECTION_1_MASK +#define GPIO_DIRM_1_DIRECTION_1_DEFVAL 0x00000000 +#define GPIO_DIRM_1_DIRECTION_1_SHIFT 0 +#define GPIO_DIRM_1_DIRECTION_1_MASK 0x03FFFFFFU + +/* +* Operation is the same as OEN_0[OP_ENABLE_0] +*/ +#undef GPIO_OEN_1_OP_ENABLE_1_DEFVAL +#undef GPIO_OEN_1_OP_ENABLE_1_SHIFT +#undef GPIO_OEN_1_OP_ENABLE_1_MASK +#define GPIO_OEN_1_OP_ENABLE_1_DEFVAL 0x00000000 +#define GPIO_OEN_1_OP_ENABLE_1_SHIFT 0 +#define GPIO_OEN_1_OP_ENABLE_1_MASK 0x03FFFFFFU + +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U + +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU +#undef FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET +#define FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET 0XFD690040 +#undef FPD_SLCR_SECURE_SLCR_PCIE_OFFSET +#define FPD_SLCR_SECURE_SLCR_PCIE_OFFSET 0XFD690030 +#undef LPD_SLCR_SECURE_SLCR_USB_OFFSET +#define LPD_SLCR_SECURE_SLCR_USB_OFFSET 0XFF4B0034 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET +#define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024 +#undef FPD_SLCR_SECURE_SLCR_GDMA_OFFSET +#define FPD_SLCR_SECURE_SLCR_GDMA_OFFSET 0XFD690050 + +/* +* TrustZone classification for DisplayPort DMA +*/ +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL 0x00000001 +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK 0x00000001U + +/* +* TrustZone classification for DMA Channel 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT 21 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK 0x00200000U + +/* +* TrustZone classification for DMA Channel 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT 22 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK 0x00400000U + +/* +* TrustZone classification for DMA Channel 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT 23 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK 0x00800000U + +/* +* TrustZone classification for DMA Channel 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT 24 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK 0x01000000U + +/* +* TrustZone classification for Ingress Address Translation 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT 13 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK 0x00002000U + +/* +* TrustZone classification for Ingress Address Translation 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT 14 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK 0x00004000U + +/* +* TrustZone classification for Ingress Address Translation 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT 15 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK 0x00008000U + +/* +* TrustZone classification for Ingress Address Translation 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT 16 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK 0x00010000U + +/* +* TrustZone classification for Ingress Address Translation 4 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT 17 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK 0x00020000U + +/* +* TrustZone classification for Ingress Address Translation 5 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT 18 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK 0x00040000U + +/* +* TrustZone classification for Ingress Address Translation 6 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT 19 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK 0x00080000U + +/* +* TrustZone classification for Ingress Address Translation 7 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT 20 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK 0x00100000U + +/* +* TrustZone classification for Egress Address Translation 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT 5 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK 0x00000020U + +/* +* TrustZone classification for Egress Address Translation 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT 6 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK 0x00000040U + +/* +* TrustZone classification for Egress Address Translation 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT 7 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK 0x00000080U + +/* +* TrustZone classification for Egress Address Translation 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT 8 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK 0x00000100U + +/* +* TrustZone classification for Egress Address Translation 4 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT 9 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK 0x00000200U + +/* +* TrustZone classification for Egress Address Translation 5 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT 10 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK 0x00000400U + +/* +* TrustZone classification for Egress Address Translation 6 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT 11 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK 0x00000800U + +/* +* TrustZone classification for Egress Address Translation 7 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT 12 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK 0x00001000U + +/* +* TrustZone classification for DMA Registers +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT 4 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK 0x00000010U + +/* +* TrustZone classification for MSIx Table +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT 2 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK 0x00000004U + +/* +* TrustZone classification for MSIx PBA +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT 3 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK 0x00000008U + +/* +* TrustZone classification for ECAM +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT 1 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK 0x00000002U + +/* +* TrustZone classification for Bridge Common Registers +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001U + +/* +* TrustZone Classification for USB3_0 +*/ +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL 0x00000003 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK 0x00000001U + +/* +* TrustZone Classification for USB3_1 +*/ +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL 0x00000003 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT 1 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK 0x00000002U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT 16 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK 0x00070000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT 19 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK 0x00380000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT 16 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK 0x00070000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT 19 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK 0x00380000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT 0 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK 0x00000007U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT 3 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK 0x00000038U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT 6 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK 0x000001C0U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT 9 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK 0x00000E00U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT 0 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK 0x00000007U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT 3 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK 0x00000038U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT 6 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK 0x000001C0U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT 9 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK 0x00000E00U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT 25 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK 0x0E000000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT 22 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK 0x01C00000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT 22 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK 0x01C00000U + +/* +* TrustZone Classification for ADMA +*/ +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU + +/* +* TrustZone Classification for GDMA +*/ +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK 0x000000FFU +#undef SERDES_PLL_REF_SEL0_OFFSET +#define SERDES_PLL_REF_SEL0_OFFSET 0XFD410000 +#undef SERDES_PLL_REF_SEL1_OFFSET +#define SERDES_PLL_REF_SEL1_OFFSET 0XFD410004 +#undef SERDES_PLL_REF_SEL2_OFFSET +#define SERDES_PLL_REF_SEL2_OFFSET 0XFD410008 +#undef SERDES_PLL_REF_SEL3_OFFSET +#define SERDES_PLL_REF_SEL3_OFFSET 0XFD41000C +#undef SERDES_L0_L0_REF_CLK_SEL_OFFSET +#define SERDES_L0_L0_REF_CLK_SEL_OFFSET 0XFD402860 +#undef SERDES_L0_L1_REF_CLK_SEL_OFFSET +#define SERDES_L0_L1_REF_CLK_SEL_OFFSET 0XFD402864 +#undef SERDES_L0_L2_REF_CLK_SEL_OFFSET +#define SERDES_L0_L2_REF_CLK_SEL_OFFSET 0XFD402868 +#undef SERDES_L0_L3_REF_CLK_SEL_OFFSET +#define SERDES_L0_L3_REF_CLK_SEL_OFFSET 0XFD40286C +#undef SERDES_L2_TM_PLL_DIG_37_OFFSET +#define SERDES_L2_TM_PLL_DIG_37_OFFSET 0XFD40A094 +#undef SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET +#define SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET 0XFD40A368 +#undef SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET +#define SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40A36C +#undef SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET +#define SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET 0XFD40E368 +#undef SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET +#define SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40E36C +#undef SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET +#define SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET 0XFD406368 +#undef SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET +#define SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40636C +#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET 0XFD406370 +#undef SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET +#define SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET 0XFD406374 +#undef SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET +#define SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET 0XFD406378 +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET 0XFD40637C +#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET 0XFD40A370 +#undef SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET +#define SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET 0XFD40A374 +#undef SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET +#define SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET 0XFD40A378 +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET 0XFD40A37C +#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET 0XFD40E370 +#undef SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET +#define SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET 0XFD40E374 +#undef SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET +#define SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET 0XFD40E378 +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET 0XFD40E37C +#undef SERDES_L2_TM_DIG_6_OFFSET +#define SERDES_L2_TM_DIG_6_OFFSET 0XFD40906C +#undef SERDES_L2_TX_DIG_TM_61_OFFSET +#define SERDES_L2_TX_DIG_TM_61_OFFSET 0XFD4080F4 +#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET 0XFD40E360 +#undef SERDES_L3_TM_DIG_6_OFFSET +#define SERDES_L3_TM_DIG_6_OFFSET 0XFD40D06C +#undef SERDES_L3_TX_DIG_TM_61_OFFSET +#define SERDES_L3_TX_DIG_TM_61_OFFSET 0XFD40C0F4 +#undef SERDES_L0_TM_AUX_0_OFFSET +#define SERDES_L0_TM_AUX_0_OFFSET 0XFD4010CC +#undef SERDES_L2_TM_AUX_0_OFFSET +#define SERDES_L2_TM_AUX_0_OFFSET 0XFD4090CC +#undef SERDES_L0_TM_DIG_8_OFFSET +#define SERDES_L0_TM_DIG_8_OFFSET 0XFD401074 +#undef SERDES_L1_TM_DIG_8_OFFSET +#define SERDES_L1_TM_DIG_8_OFFSET 0XFD405074 +#undef SERDES_L2_TM_DIG_8_OFFSET +#define SERDES_L2_TM_DIG_8_OFFSET 0XFD409074 +#undef SERDES_L3_TM_DIG_8_OFFSET +#define SERDES_L3_TM_DIG_8_OFFSET 0XFD40D074 +#undef SERDES_L0_TM_MISC2_OFFSET +#define SERDES_L0_TM_MISC2_OFFSET 0XFD40189C +#undef SERDES_L0_TM_IQ_ILL1_OFFSET +#define SERDES_L0_TM_IQ_ILL1_OFFSET 0XFD4018F8 +#undef SERDES_L0_TM_IQ_ILL2_OFFSET +#define SERDES_L0_TM_IQ_ILL2_OFFSET 0XFD4018FC +#undef SERDES_L0_TM_ILL12_OFFSET +#define SERDES_L0_TM_ILL12_OFFSET 0XFD401990 +#undef SERDES_L0_TM_E_ILL1_OFFSET +#define SERDES_L0_TM_E_ILL1_OFFSET 0XFD401924 +#undef SERDES_L0_TM_E_ILL2_OFFSET +#define SERDES_L0_TM_E_ILL2_OFFSET 0XFD401928 +#undef SERDES_L0_TM_IQ_ILL3_OFFSET +#define SERDES_L0_TM_IQ_ILL3_OFFSET 0XFD401900 +#undef SERDES_L0_TM_E_ILL3_OFFSET +#define SERDES_L0_TM_E_ILL3_OFFSET 0XFD40192C +#undef SERDES_L0_TM_ILL8_OFFSET +#define SERDES_L0_TM_ILL8_OFFSET 0XFD401980 +#undef SERDES_L0_TM_IQ_ILL8_OFFSET +#define SERDES_L0_TM_IQ_ILL8_OFFSET 0XFD401914 +#undef SERDES_L0_TM_IQ_ILL9_OFFSET +#define SERDES_L0_TM_IQ_ILL9_OFFSET 0XFD401918 +#undef SERDES_L0_TM_E_ILL8_OFFSET +#define SERDES_L0_TM_E_ILL8_OFFSET 0XFD401940 +#undef SERDES_L0_TM_E_ILL9_OFFSET +#define SERDES_L0_TM_E_ILL9_OFFSET 0XFD401944 +#undef SERDES_L0_TM_ILL13_OFFSET +#define SERDES_L0_TM_ILL13_OFFSET 0XFD401994 +#undef SERDES_L1_TM_ILL13_OFFSET +#define SERDES_L1_TM_ILL13_OFFSET 0XFD405994 +#undef SERDES_L2_TM_MISC2_OFFSET +#define SERDES_L2_TM_MISC2_OFFSET 0XFD40989C +#undef SERDES_L2_TM_IQ_ILL1_OFFSET +#define SERDES_L2_TM_IQ_ILL1_OFFSET 0XFD4098F8 +#undef SERDES_L2_TM_IQ_ILL2_OFFSET +#define SERDES_L2_TM_IQ_ILL2_OFFSET 0XFD4098FC +#undef SERDES_L2_TM_ILL12_OFFSET +#define SERDES_L2_TM_ILL12_OFFSET 0XFD409990 +#undef SERDES_L2_TM_E_ILL1_OFFSET +#define SERDES_L2_TM_E_ILL1_OFFSET 0XFD409924 +#undef SERDES_L2_TM_E_ILL2_OFFSET +#define SERDES_L2_TM_E_ILL2_OFFSET 0XFD409928 +#undef SERDES_L2_TM_IQ_ILL3_OFFSET +#define SERDES_L2_TM_IQ_ILL3_OFFSET 0XFD409900 +#undef SERDES_L2_TM_E_ILL3_OFFSET +#define SERDES_L2_TM_E_ILL3_OFFSET 0XFD40992C +#undef SERDES_L2_TM_ILL8_OFFSET +#define SERDES_L2_TM_ILL8_OFFSET 0XFD409980 +#undef SERDES_L2_TM_IQ_ILL8_OFFSET +#define SERDES_L2_TM_IQ_ILL8_OFFSET 0XFD409914 +#undef SERDES_L2_TM_IQ_ILL9_OFFSET +#define SERDES_L2_TM_IQ_ILL9_OFFSET 0XFD409918 +#undef SERDES_L2_TM_E_ILL8_OFFSET +#define SERDES_L2_TM_E_ILL8_OFFSET 0XFD409940 +#undef SERDES_L2_TM_E_ILL9_OFFSET +#define SERDES_L2_TM_E_ILL9_OFFSET 0XFD409944 +#undef SERDES_L2_TM_ILL13_OFFSET +#define SERDES_L2_TM_ILL13_OFFSET 0XFD409994 +#undef SERDES_L3_TM_MISC2_OFFSET +#define SERDES_L3_TM_MISC2_OFFSET 0XFD40D89C +#undef SERDES_L3_TM_IQ_ILL1_OFFSET +#define SERDES_L3_TM_IQ_ILL1_OFFSET 0XFD40D8F8 +#undef SERDES_L3_TM_IQ_ILL2_OFFSET +#define SERDES_L3_TM_IQ_ILL2_OFFSET 0XFD40D8FC +#undef SERDES_L3_TM_ILL12_OFFSET +#define SERDES_L3_TM_ILL12_OFFSET 0XFD40D990 +#undef SERDES_L3_TM_E_ILL1_OFFSET +#define SERDES_L3_TM_E_ILL1_OFFSET 0XFD40D924 +#undef SERDES_L3_TM_E_ILL2_OFFSET +#define SERDES_L3_TM_E_ILL2_OFFSET 0XFD40D928 +#undef SERDES_L3_TM_ILL11_OFFSET +#define SERDES_L3_TM_ILL11_OFFSET 0XFD40D98C +#undef SERDES_L3_TM_IQ_ILL3_OFFSET +#define SERDES_L3_TM_IQ_ILL3_OFFSET 0XFD40D900 +#undef SERDES_L3_TM_E_ILL3_OFFSET +#define SERDES_L3_TM_E_ILL3_OFFSET 0XFD40D92C +#undef SERDES_L3_TM_ILL8_OFFSET +#define SERDES_L3_TM_ILL8_OFFSET 0XFD40D980 +#undef SERDES_L3_TM_IQ_ILL8_OFFSET +#define SERDES_L3_TM_IQ_ILL8_OFFSET 0XFD40D914 +#undef SERDES_L3_TM_IQ_ILL9_OFFSET +#define SERDES_L3_TM_IQ_ILL9_OFFSET 0XFD40D918 +#undef SERDES_L3_TM_E_ILL8_OFFSET +#define SERDES_L3_TM_E_ILL8_OFFSET 0XFD40D940 +#undef SERDES_L3_TM_E_ILL9_OFFSET +#define SERDES_L3_TM_E_ILL9_OFFSET 0XFD40D944 +#undef SERDES_L3_TM_ILL13_OFFSET +#define SERDES_L3_TM_ILL13_OFFSET 0XFD40D994 +#undef SERDES_L0_TM_DIG_10_OFFSET +#define SERDES_L0_TM_DIG_10_OFFSET 0XFD40107C +#undef SERDES_L1_TM_DIG_10_OFFSET +#define SERDES_L1_TM_DIG_10_OFFSET 0XFD40507C +#undef SERDES_L2_TM_DIG_10_OFFSET +#define SERDES_L2_TM_DIG_10_OFFSET 0XFD40907C +#undef SERDES_L3_TM_DIG_10_OFFSET +#define SERDES_L3_TM_DIG_10_OFFSET 0XFD40D07C +#undef SERDES_L0_TM_RST_DLY_OFFSET +#define SERDES_L0_TM_RST_DLY_OFFSET 0XFD4019A4 +#undef SERDES_L0_TM_ANA_BYP_15_OFFSET +#define SERDES_L0_TM_ANA_BYP_15_OFFSET 0XFD401038 +#undef SERDES_L0_TM_ANA_BYP_12_OFFSET +#define SERDES_L0_TM_ANA_BYP_12_OFFSET 0XFD40102C +#undef SERDES_L1_TM_RST_DLY_OFFSET +#define SERDES_L1_TM_RST_DLY_OFFSET 0XFD4059A4 +#undef SERDES_L1_TM_ANA_BYP_15_OFFSET +#define SERDES_L1_TM_ANA_BYP_15_OFFSET 0XFD405038 +#undef SERDES_L1_TM_ANA_BYP_12_OFFSET +#define SERDES_L1_TM_ANA_BYP_12_OFFSET 0XFD40502C +#undef SERDES_L2_TM_RST_DLY_OFFSET +#define SERDES_L2_TM_RST_DLY_OFFSET 0XFD4099A4 +#undef SERDES_L2_TM_ANA_BYP_15_OFFSET +#define SERDES_L2_TM_ANA_BYP_15_OFFSET 0XFD409038 +#undef SERDES_L2_TM_ANA_BYP_12_OFFSET +#define SERDES_L2_TM_ANA_BYP_12_OFFSET 0XFD40902C +#undef SERDES_L3_TM_RST_DLY_OFFSET +#define SERDES_L3_TM_RST_DLY_OFFSET 0XFD40D9A4 +#undef SERDES_L3_TM_ANA_BYP_15_OFFSET +#define SERDES_L3_TM_ANA_BYP_15_OFFSET 0XFD40D038 +#undef SERDES_L3_TM_ANA_BYP_12_OFFSET +#define SERDES_L3_TM_ANA_BYP_12_OFFSET 0XFD40D02C +#undef SERDES_L0_TM_MISC3_OFFSET +#define SERDES_L0_TM_MISC3_OFFSET 0XFD4019AC +#undef SERDES_L1_TM_MISC3_OFFSET +#define SERDES_L1_TM_MISC3_OFFSET 0XFD4059AC +#undef SERDES_L2_TM_MISC3_OFFSET +#define SERDES_L2_TM_MISC3_OFFSET 0XFD4099AC +#undef SERDES_L3_TM_MISC3_OFFSET +#define SERDES_L3_TM_MISC3_OFFSET 0XFD40D9AC +#undef SERDES_L0_TM_EQ11_OFFSET +#define SERDES_L0_TM_EQ11_OFFSET 0XFD401978 +#undef SERDES_L1_TM_EQ11_OFFSET +#define SERDES_L1_TM_EQ11_OFFSET 0XFD405978 +#undef SERDES_L2_TM_EQ11_OFFSET +#define SERDES_L2_TM_EQ11_OFFSET 0XFD409978 +#undef SERDES_L3_TM_EQ11_OFFSET +#define SERDES_L3_TM_EQ11_OFFSET 0XFD40D978 +#undef SIOU_ECO_0_OFFSET +#define SIOU_ECO_0_OFFSET 0XFD3D001C +#undef SERDES_ICM_CFG0_OFFSET +#define SERDES_ICM_CFG0_OFFSET 0XFD410010 +#undef SERDES_ICM_CFG1_OFFSET +#define SERDES_ICM_CFG1_OFFSET 0XFD410014 +#undef SERDES_L1_TXPMD_TM_45_OFFSET +#define SERDES_L1_TXPMD_TM_45_OFFSET 0XFD404CB4 +#undef SERDES_L1_TX_ANA_TM_118_OFFSET +#define SERDES_L1_TX_ANA_TM_118_OFFSET 0XFD4041D8 +#undef SERDES_L3_TX_ANA_TM_118_OFFSET +#define SERDES_L3_TX_ANA_TM_118_OFFSET 0XFD40C1D8 +#undef SERDES_L3_TM_CDR5_OFFSET +#define SERDES_L3_TM_CDR5_OFFSET 0XFD40DC14 +#undef SERDES_L3_TM_CDR16_OFFSET +#define SERDES_L3_TM_CDR16_OFFSET 0XFD40DC40 +#undef SERDES_L3_TM_EQ0_OFFSET +#define SERDES_L3_TM_EQ0_OFFSET 0XFD40D94C +#undef SERDES_L3_TM_EQ1_OFFSET +#define SERDES_L3_TM_EQ1_OFFSET 0XFD40D950 +#undef SERDES_L1_TXPMD_TM_48_OFFSET +#define SERDES_L1_TXPMD_TM_48_OFFSET 0XFD404CC0 +#undef SERDES_L1_TX_ANA_TM_18_OFFSET +#define SERDES_L1_TX_ANA_TM_18_OFFSET 0XFD404048 +#undef SERDES_L3_TX_ANA_TM_18_OFFSET +#define SERDES_L3_TX_ANA_TM_18_OFFSET 0XFD40C048 + +/* +* PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ +#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL +#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT +#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 0x0000000D +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 0 +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 0x0000001FU + +/* +* PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ +#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL +#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT +#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 0x00000008 +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 0 +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 0x0000001FU + +/* +* PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ +#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL +#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT +#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 0x0000000F +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 0 +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 0x0000001FU + +/* +* PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ +#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL +#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT +#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 0x0000000E +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 0 +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 0x0000001FU + +/* +* Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp + * ut. Set to 0 to select lane0 ref clock mux output. +*/ +#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL +#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT +#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 0x00000080U + +/* +* Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane1 ref clock mux output. +*/ +#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL +#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT +#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 0x00000080U + +/* +* Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli + * cer output from ref clock network +*/ +#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL +#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT +#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 0x00000080 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 3 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 0x00000008U + +/* +* Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane2 ref clock mux output. +*/ +#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL +#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT +#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 0x00000080U + +/* +* Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp + * ut. Set to 0 to select lane3 ref clock mux output. +*/ +#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL +#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT +#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 0x00000080U + +/* +* Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli + * cer output from ref clock network +*/ +#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL +#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT +#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 0x00000080 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 1 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 0x00000002U + +/* +* Enable/Disable coarse code satureation limiting logic +*/ +#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL +#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT +#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 0x00000000 +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 4 +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 0x00000010U + +/* +* Spread Spectrum No of Steps [7:0] +*/ +#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL +#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT +#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU + +/* +* Spread Spectrum No of Steps [10:8] +*/ +#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL +#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT +#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U + +/* +* Spread Spectrum No of Steps [7:0] +*/ +#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL +#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT +#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU + +/* +* Spread Spectrum No of Steps [10:8] +*/ +#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL +#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT +#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U + +/* +* Spread Spectrum No of Steps [7:0] +*/ +#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL +#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT +#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU + +/* +* Spread Spectrum No of Steps [10:8] +*/ +#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL +#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT +#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U + +/* +* Step Size for Spread Spectrum [7:0] +*/ +#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL +#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT +#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [15:8] +*/ +#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL +#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT +#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [23:16] +*/ +#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL +#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT +#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [25:24] +*/ +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U + +/* +* Enable/Disable test mode force on SS step size +*/ +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U + +/* +* Enable/Disable test mode force on SS no of steps +*/ +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U + +/* +* Step Size for Spread Spectrum [7:0] +*/ +#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL +#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT +#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [15:8] +*/ +#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL +#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT +#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [23:16] +*/ +#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL +#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT +#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [25:24] +*/ +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U + +/* +* Enable/Disable test mode force on SS step size +*/ +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U + +/* +* Enable/Disable test mode force on SS no of steps +*/ +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U + +/* +* Step Size for Spread Spectrum [7:0] +*/ +#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL +#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT +#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [15:8] +*/ +#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL +#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT +#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [23:16] +*/ +#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL +#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT +#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [25:24] +*/ +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U + +/* +* Enable/Disable test mode force on SS step size +*/ +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U + +/* +* Enable/Disable test mode force on SS no of steps +*/ +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U + +/* +* Enable test mode forcing on enable Spread Spectrum +*/ +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 7 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 0x00000080U + +/* +* Bypass Descrambler +*/ +#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL +#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT +#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U + +/* +* Enable Bypass for <1> TM_DIG_CTRL_6 +*/ +#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL +#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT +#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U + +/* +* Bypass scrambler signal +*/ +#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL +#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT +#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U + +/* +* Enable/disable scrambler bypass signal +*/ +#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL +#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT +#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U + +/* +* Enable test mode force on fractional mode enable +*/ +#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL +#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT +#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 0x00000000 +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 6 +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 0x00000040U + +/* +* Bypass 8b10b decoder +*/ +#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL +#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT +#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 3 +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 0x00000008U + +/* +* Enable Bypass for <3> TM_DIG_CTRL_6 +*/ +#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL +#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT +#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 2 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 0x00000004U + +/* +* Bypass Descrambler +*/ +#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL +#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT +#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U + +/* +* Enable Bypass for <1> TM_DIG_CTRL_6 +*/ +#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL +#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT +#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U + +/* +* Enable/disable encoder bypass signal +*/ +#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL +#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT +#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 3 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 0x00000008U + +/* +* Bypass scrambler signal +*/ +#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL +#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT +#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U + +/* +* Enable/disable scrambler bypass signal +*/ +#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL +#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT +#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U + +/* +* Spare- not used +*/ +#undef SERDES_L0_TM_AUX_0_BIT_2_DEFVAL +#undef SERDES_L0_TM_AUX_0_BIT_2_SHIFT +#undef SERDES_L0_TM_AUX_0_BIT_2_MASK +#define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 0x00000000 +#define SERDES_L0_TM_AUX_0_BIT_2_SHIFT 5 +#define SERDES_L0_TM_AUX_0_BIT_2_MASK 0x00000020U + +/* +* Spare- not used +*/ +#undef SERDES_L2_TM_AUX_0_BIT_2_DEFVAL +#undef SERDES_L2_TM_AUX_0_BIT_2_SHIFT +#undef SERDES_L2_TM_AUX_0_BIT_2_MASK +#define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 0x00000000 +#define SERDES_L2_TM_AUX_0_BIT_2_SHIFT 5 +#define SERDES_L2_TM_AUX_0_BIT_2_MASK 0x00000020U + +/* +* Enable Eye Surf +*/ +#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL +#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT +#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U + +/* +* Enable Eye Surf +*/ +#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL +#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT +#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U + +/* +* Enable Eye Surf +*/ +#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL +#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT +#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U + +/* +* Enable Eye Surf +*/ +#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL +#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT +#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U + +/* +* ILL calib counts BYPASSED with calcode bits +*/ +#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL +#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT +#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U + +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ +#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL +#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT +#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU + +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ +#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL +#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT +#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU + +/* +* G1A pll ctr bypass value +*/ +#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL +#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT +#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU + +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ +#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL +#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT +#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU + +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ +#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL +#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT +#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU + +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ +#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL +#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT +#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU + +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ +#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL +#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT +#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU + +/* +* ILL calibration code change wait time +*/ +#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL +#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT +#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU + +/* +* IQ ILL polytrim bypass value +*/ +#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL +#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT +#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU + +/* +* bypass IQ polytrim +*/ +#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL +#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT +#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U + +/* +* E ILL polytrim bypass value +*/ +#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL +#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT +#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU + +/* +* bypass E polytrim +*/ +#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL +#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT +#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U + +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL calib counts BYPASSED with calcode bits +*/ +#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL +#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT +#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U + +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ +#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL +#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT +#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU + +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ +#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL +#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT +#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU + +/* +* G1A pll ctr bypass value +*/ +#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL +#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT +#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU + +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ +#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL +#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT +#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU + +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ +#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL +#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT +#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU + +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ +#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL +#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT +#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU + +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ +#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL +#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT +#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU + +/* +* ILL calibration code change wait time +*/ +#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL +#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT +#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU + +/* +* IQ ILL polytrim bypass value +*/ +#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL +#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT +#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU + +/* +* bypass IQ polytrim +*/ +#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL +#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT +#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U + +/* +* E ILL polytrim bypass value +*/ +#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL +#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT +#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU + +/* +* bypass E polytrim +*/ +#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL +#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT +#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U + +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL calib counts BYPASSED with calcode bits +*/ +#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL +#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT +#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U + +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ +#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL +#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT +#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU + +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ +#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL +#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT +#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU + +/* +* G1A pll ctr bypass value +*/ +#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL +#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT +#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU + +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ +#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL +#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT +#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU + +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ +#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL +#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT +#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU + +/* +* G2A_PCIe1 PLL ctr bypass value +*/ +#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL +#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT +#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 4 +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 0x000000F0U + +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ +#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL +#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT +#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU + +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ +#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL +#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT +#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU + +/* +* ILL calibration code change wait time +*/ +#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL +#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT +#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU + +/* +* IQ ILL polytrim bypass value +*/ +#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL +#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT +#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU + +/* +* bypass IQ polytrim +*/ +#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL +#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT +#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U + +/* +* E ILL polytrim bypass value +*/ +#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL +#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT +#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU + +/* +* bypass E polytrim +*/ +#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL +#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT +#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U + +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* Delay apb reset by specified amount +*/ +#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL +#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT +#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ +#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL +#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT +#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ +#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL +#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT +#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U + +/* +* Delay apb reset by specified amount +*/ +#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL +#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT +#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ +#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL +#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT +#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ +#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL +#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT +#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U + +/* +* Delay apb reset by specified amount +*/ +#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL +#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT +#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ +#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL +#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT +#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ +#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL +#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT +#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U + +/* +* Delay apb reset by specified amount +*/ +#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL +#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT +#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ +#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL +#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT +#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ +#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL +#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT +#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* For future use +*/ +#undef SIOU_ECO_0_FIELD_DEFVAL +#undef SIOU_ECO_0_FIELD_SHIFT +#undef SIOU_ECO_0_FIELD_MASK +#define SIOU_ECO_0_FIELD_DEFVAL +#define SIOU_ECO_0_FIELD_SHIFT 0 +#define SIOU_ECO_0_FIELD_MASK 0xFFFFFFFFU + +/* +* Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused +*/ +#undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL +#undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT +#undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK +#define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 0 +#define SERDES_ICM_CFG0_L0_ICM_CFG_MASK 0x00000007U + +/* +* Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused +*/ +#undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL +#undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT +#undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK +#define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 4 +#define SERDES_ICM_CFG0_L1_ICM_CFG_MASK 0x00000070U + +/* +* Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused +*/ +#undef SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL +#undef SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT +#undef SERDES_ICM_CFG1_L2_ICM_CFG_MASK +#define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 0 +#define SERDES_ICM_CFG1_L2_ICM_CFG_MASK 0x00000007U + +/* +* Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, + * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused +*/ +#undef SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL +#undef SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT +#undef SERDES_ICM_CFG1_L3_ICM_CFG_MASK +#define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 4 +#define SERDES_ICM_CFG1_L3_ICM_CFG_MASK 0x00000070U + +/* +* Enable/disable DP post2 path +*/ +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 5 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 0x00000020U + +/* +* Override enable/disable of DP post2 path +*/ +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 4 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 0x00000010U + +/* +* Override enable/disable of DP post1 path +*/ +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 2 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 0x00000004U + +/* +* Enable/disable DP main path +*/ +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 1 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 0x00000002U + +/* +* Override enable/disable of DP main path +*/ +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 0 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 0x00000001U + +/* +* Test register force for enabling/disablign TX deemphasis bits <17:0> +*/ +#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL +#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT +#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U + +/* +* Test register force for enabling/disablign TX deemphasis bits <17:0> +*/ +#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL +#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT +#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U + +/* +* FPHL FSM accumulate cycles +*/ +#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL +#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT +#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 5 +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 0x000000E0U + +/* +* FFL Phase0 int gain aka 2ol SD update rate +*/ +#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL +#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT +#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 0 +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 0x0000001FU + +/* +* FFL Phase0 prop gain aka 1ol SD update rate +*/ +#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL +#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT +#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 0 +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 0x0000001FU + +/* +* EQ stg 2 controls BYPASSED +*/ +#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL +#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT +#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 5 +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 0x00000020U + +/* +* EQ STG2 RL PROG +*/ +#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL +#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT +#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 0 +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 0x00000003U + +/* +* EQ stg 2 preamp mode val +*/ +#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL +#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT +#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 2 +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 0x00000004U + +/* +* Margining factor value +*/ +#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL +#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT +#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 0 +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 0x0000001FU + +/* +* pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved +*/ +#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL +#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT +#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU + +/* +* pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved +*/ +#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL +#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT +#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef USB3_0_FPD_POWER_PRSNT_OFFSET +#define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080 +#undef USB3_0_FPD_PIPE_CLK_OFFSET +#define USB3_0_FPD_PIPE_CLK_OFFSET 0XFF9D007C +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef CRL_APB_RST_LPD_IOU0_OFFSET +#define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230 +#undef SIOU_SATA_MISC_CTRL_OFFSET +#define SIOU_SATA_MISC_CTRL_OFFSET 0XFD3D0100 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef DP_DP_PHY_RESET_OFFSET +#define DP_DP_PHY_RESET_OFFSET 0XFD4A0200 +#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET +#define DP_DP_TX_PHY_POWER_DOWN_OFFSET 0XFD4A0238 +#undef USB3_0_XHCI_GUSB2PHYCFG_OFFSET +#define USB3_0_XHCI_GUSB2PHYCFG_OFFSET 0XFE20C200 +#undef USB3_0_XHCI_GFLADJ_OFFSET +#define USB3_0_XHCI_GFLADJ_OFFSET 0XFE20C630 +#undef USB3_0_XHCI_GUCTL1_OFFSET +#define USB3_0_XHCI_GUCTL1_OFFSET 0XFE20C11C +#undef USB3_0_XHCI_GUCTL_OFFSET +#define USB3_0_XHCI_GUCTL_OFFSET 0XFE20C12C +#undef PCIE_ATTRIB_ATTR_25_OFFSET +#define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064 +#undef PCIE_ATTRIB_ATTR_7_OFFSET +#define PCIE_ATTRIB_ATTR_7_OFFSET 0XFD48001C +#undef PCIE_ATTRIB_ATTR_8_OFFSET +#define PCIE_ATTRIB_ATTR_8_OFFSET 0XFD480020 +#undef PCIE_ATTRIB_ATTR_9_OFFSET +#define PCIE_ATTRIB_ATTR_9_OFFSET 0XFD480024 +#undef PCIE_ATTRIB_ATTR_10_OFFSET +#define PCIE_ATTRIB_ATTR_10_OFFSET 0XFD480028 +#undef PCIE_ATTRIB_ATTR_11_OFFSET +#define PCIE_ATTRIB_ATTR_11_OFFSET 0XFD48002C +#undef PCIE_ATTRIB_ATTR_12_OFFSET +#define PCIE_ATTRIB_ATTR_12_OFFSET 0XFD480030 +#undef PCIE_ATTRIB_ATTR_13_OFFSET +#define PCIE_ATTRIB_ATTR_13_OFFSET 0XFD480034 +#undef PCIE_ATTRIB_ATTR_14_OFFSET +#define PCIE_ATTRIB_ATTR_14_OFFSET 0XFD480038 +#undef PCIE_ATTRIB_ATTR_15_OFFSET +#define PCIE_ATTRIB_ATTR_15_OFFSET 0XFD48003C +#undef PCIE_ATTRIB_ATTR_16_OFFSET +#define PCIE_ATTRIB_ATTR_16_OFFSET 0XFD480040 +#undef PCIE_ATTRIB_ATTR_17_OFFSET +#define PCIE_ATTRIB_ATTR_17_OFFSET 0XFD480044 +#undef PCIE_ATTRIB_ATTR_18_OFFSET +#define PCIE_ATTRIB_ATTR_18_OFFSET 0XFD480048 +#undef PCIE_ATTRIB_ATTR_27_OFFSET +#define PCIE_ATTRIB_ATTR_27_OFFSET 0XFD48006C +#undef PCIE_ATTRIB_ATTR_50_OFFSET +#define PCIE_ATTRIB_ATTR_50_OFFSET 0XFD4800C8 +#undef PCIE_ATTRIB_ATTR_105_OFFSET +#define PCIE_ATTRIB_ATTR_105_OFFSET 0XFD4801A4 +#undef PCIE_ATTRIB_ATTR_106_OFFSET +#define PCIE_ATTRIB_ATTR_106_OFFSET 0XFD4801A8 +#undef PCIE_ATTRIB_ATTR_107_OFFSET +#define PCIE_ATTRIB_ATTR_107_OFFSET 0XFD4801AC +#undef PCIE_ATTRIB_ATTR_108_OFFSET +#define PCIE_ATTRIB_ATTR_108_OFFSET 0XFD4801B0 +#undef PCIE_ATTRIB_ATTR_109_OFFSET +#define PCIE_ATTRIB_ATTR_109_OFFSET 0XFD4801B4 +#undef PCIE_ATTRIB_ATTR_34_OFFSET +#define PCIE_ATTRIB_ATTR_34_OFFSET 0XFD480088 +#undef PCIE_ATTRIB_ATTR_53_OFFSET +#define PCIE_ATTRIB_ATTR_53_OFFSET 0XFD4800D4 +#undef PCIE_ATTRIB_ATTR_41_OFFSET +#define PCIE_ATTRIB_ATTR_41_OFFSET 0XFD4800A4 +#undef PCIE_ATTRIB_ATTR_97_OFFSET +#define PCIE_ATTRIB_ATTR_97_OFFSET 0XFD480184 +#undef PCIE_ATTRIB_ATTR_100_OFFSET +#define PCIE_ATTRIB_ATTR_100_OFFSET 0XFD480190 +#undef PCIE_ATTRIB_ATTR_101_OFFSET +#define PCIE_ATTRIB_ATTR_101_OFFSET 0XFD480194 +#undef PCIE_ATTRIB_ATTR_37_OFFSET +#define PCIE_ATTRIB_ATTR_37_OFFSET 0XFD480094 +#undef PCIE_ATTRIB_ATTR_93_OFFSET +#define PCIE_ATTRIB_ATTR_93_OFFSET 0XFD480174 +#undef PCIE_ATTRIB_ID_OFFSET +#define PCIE_ATTRIB_ID_OFFSET 0XFD480200 +#undef PCIE_ATTRIB_SUBSYS_ID_OFFSET +#define PCIE_ATTRIB_SUBSYS_ID_OFFSET 0XFD480204 +#undef PCIE_ATTRIB_REV_ID_OFFSET +#define PCIE_ATTRIB_REV_ID_OFFSET 0XFD480208 +#undef PCIE_ATTRIB_ATTR_24_OFFSET +#define PCIE_ATTRIB_ATTR_24_OFFSET 0XFD480060 +#undef PCIE_ATTRIB_ATTR_25_OFFSET +#define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064 +#undef PCIE_ATTRIB_ATTR_4_OFFSET +#define PCIE_ATTRIB_ATTR_4_OFFSET 0XFD480010 +#undef PCIE_ATTRIB_ATTR_89_OFFSET +#define PCIE_ATTRIB_ATTR_89_OFFSET 0XFD480164 +#undef PCIE_ATTRIB_ATTR_79_OFFSET +#define PCIE_ATTRIB_ATTR_79_OFFSET 0XFD48013C +#undef PCIE_ATTRIB_ATTR_43_OFFSET +#define PCIE_ATTRIB_ATTR_43_OFFSET 0XFD4800AC +#undef PCIE_ATTRIB_ATTR_48_OFFSET +#define PCIE_ATTRIB_ATTR_48_OFFSET 0XFD4800C0 +#undef PCIE_ATTRIB_ATTR_46_OFFSET +#define PCIE_ATTRIB_ATTR_46_OFFSET 0XFD4800B8 +#undef PCIE_ATTRIB_ATTR_47_OFFSET +#define PCIE_ATTRIB_ATTR_47_OFFSET 0XFD4800BC +#undef PCIE_ATTRIB_ATTR_44_OFFSET +#define PCIE_ATTRIB_ATTR_44_OFFSET 0XFD4800B0 +#undef PCIE_ATTRIB_ATTR_45_OFFSET +#define PCIE_ATTRIB_ATTR_45_OFFSET 0XFD4800B4 +#undef PCIE_ATTRIB_CB_OFFSET +#define PCIE_ATTRIB_CB_OFFSET 0XFD48031C +#undef PCIE_ATTRIB_ATTR_35_OFFSET +#define PCIE_ATTRIB_ATTR_35_OFFSET 0XFD48008C +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 +#undef SATA_AHCI_VENDOR_PP2C_OFFSET +#define SATA_AHCI_VENDOR_PP2C_OFFSET 0XFD0C00AC +#undef SATA_AHCI_VENDOR_PP3C_OFFSET +#define SATA_AHCI_VENDOR_PP3C_OFFSET 0XFD0C00B0 +#undef SATA_AHCI_VENDOR_PP4C_OFFSET +#define SATA_AHCI_VENDOR_PP4C_OFFSET 0XFD0C00B4 +#undef SATA_AHCI_VENDOR_PP5C_OFFSET +#define SATA_AHCI_VENDOR_PP5C_OFFSET 0XFD0C00B8 + +/* +* USB 0 reset for control registers +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U + +/* +* This bit is used to choose between PIPE power present and 1'b1 +*/ +#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL +#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT +#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK +#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL +#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0 +#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U + +/* +* This bit is used to choose between PIPE clock coming from SerDes and the + * suspend clk +*/ +#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL +#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT +#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK +#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL +#define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 0 +#define USB3_0_FPD_PIPE_CLK_OPTION_MASK 0x00000001U + +/* +* USB 0 sleep circuit reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U + +/* +* USB 0 reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U + +/* +* GEM 3 reset +*/ +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U + +/* +* Sata PM clock control select +*/ +#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL +#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT +#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 0 +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 0x00000003U + +/* +* Sata block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U + +/* +* PCIE config reset +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U + +/* +* PCIE bridge block level reset (AXI interface) +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U + +/* +* Display Port block level reset (includes DPDMA) +*/ +#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U + +/* +* Set to '1' to hold the GT in reset. Clear to release. +*/ +#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL +#undef DP_DP_PHY_RESET_GT_RESET_SHIFT +#undef DP_DP_PHY_RESET_GT_RESET_MASK +#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 +#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 +#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U + +/* +* Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 +*/ +#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL +#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT +#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU + +/* +* USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc + * ks. Specifies the response time for a MAC request to the Packet FIFO Con + * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th + * e required values for the minimum SoC bus frequency of 60 MHz. USB turna + * round time is a critical certification criteria when using long cables a + * nd five hub levels. The required values for this field: - 4'h5: When the + * MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit + * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim + * e is not critical, this field can be set to a larger value. Note: This f + * ield is valid only in device mode. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 10 +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 0x00003C00U + +/* +* Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP + * I Transceiver Select signal (for HS) and the assertion of the TxValid si + * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima + * tely 2.5 us) is introduced from the time when the Transceiver Select is + * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the + * chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you + * enable the hibernation feature when the device core comes out of power- + * off, you must re-initialize this bit with the appropriate value because + * the core does not save and restore this bit value during hibernation. - + * This bit is valid only in device mode. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 9 +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 0x00000200U + +/* +* Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use + * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th + * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert + * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s + * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t + * he external PHY. Note: This bit must be set high for Port0 if PHY is use + * d. Note: In Device mode - Before issuing any device endpoint command whe + * n operating in 2.0 speeds, disable this bit and enable it after the comm + * and completes. Without disabling this bit, if a command is issued when t + * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of + * f, the command will not get completed. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 8 +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 0x00000100U + +/* +* USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T + * he application uses this bit to select a high-speed PHY or a full-speed + * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a + * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans + * ceiver. This bit is always 1, with Write Only access. If both interface + * types are selected in coreConsultant (that is, parameters' values are no + * t zero), the application uses this bit to select the active interface is + * active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv + * er is not supported. This bit always reads as 1'b0. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U + +/* +* Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend + * mode if Suspend conditions are valid. For DRD/OTG configurations, it is + * recommended that this bit is set to 0 during coreConsultant configurati + * on. If it is set to 1, then the application must clear this bit after po + * wer-on reset. Application needs to set it to 1 after the core initializa + * tion completes. For all other configurations, this bit can be set to 1 d + * uring core configuration. Note: - In host mode, on reset, this bit is se + * t to 1. Software can override this bit after reset. - In device mode, be + * fore issuing any device endpoint command when operating in 2.0 speeds, d + * isable this bit and enable it after the command completes. If you issue + * a command without disabling this bit when the device is in L2 state and + * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c + * ompleted. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 6 +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 0x00000040U + +/* +* Full-Speed Serial Interface Select (FSIntf) The application uses this bi + * t to select a unidirectional or bidirectional USB 1.1 full-speed serial + * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in + * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir + * ectional full-speed serial interface. This bit is set to 0 with Read Onl + * y access. Note: USB 1.1 full-speed serial interface is not supported. Th + * is bit always reads as 1'b0. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 5 +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 0x00000020U + +/* +* ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se + * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int + * erface This bit is writable only if UTMI+ and ULPI is specified for High + * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_ + * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o + * n the interface selected through DWC_USB3_HSPHY_INTERFACE. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 4 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 0x00000010U + +/* +* PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi + * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte + * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en + * abled 2.0 ports must have the same clock frequency as Port0 clock freque + * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge + * ther for different ports at the same time (that is, all the ports must b + * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If + * any of the USB 2.0 ports is selected as ULPI port for operation, then a + * ll the USB 2.0 ports must be operating at 60 MHz. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 3 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 0x00000008U + +/* +* HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat + * ed by the application in this field, is multiplied by a bit-time factor; + * this factor is added to the high-speed/full-speed interpacket timeout d + * uration in the core to account for additional delays introduced by the P + * HY. This may be required, since the delay introduced by the PHY in gener + * ating the linestate condition may vary among PHYs. The USB standard time + * out value for high-speed operation is 736 to 816 (inclusive) bit times. + * The USB standard timeout value for full-speed operation is 16 to 18 (inc + * lusive) bit times. The application must program this field based on the + * speed of connection. The number of bit times added per PHY clock are: Hi + * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P + * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0. + * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc + * k = 0.25 bit times +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 0 +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 0x00000007U + +/* +* ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive + * 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char + * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl + * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3) +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT 17 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK 0x00020000U + +/* +* This field indicates the frame length adjustment to be applied when SOF/ + * ITP counter is running on the ref_clk. This register value is used to ad + * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i + * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must + * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t + * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows: + * FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe + * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege + * r value of the ref_clk period got by truncating the decimal (fractional) + * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c + * lk_period is the ref_clk period including the fractional value. Examples + * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA + * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin + * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE + * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2 + * 0.8333 = 5208 (ignoring the fractional value) +*/ +#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL +#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT +#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 0x00000000 +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8 +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U + +/* +* When this bit is set to '0', termsel, xcvrsel will become 0 during end o + * f resume while the opmode will become 0 once controller completes end of + * resume and enters U0 state (2 separate commandswill be issued). When th + * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during + * end of resume itself (only 1 command will be issued) +*/ +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT 10 +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK 0x00000400U + +/* +* Reserved +*/ +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_MASK +#define USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT 9 +#define USB3_0_XHCI_GUCTL1_RESERVED_9_MASK 0x00000200U + +/* +* Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th + * e Auto Retry feature. For IN transfers (non-isochronous) that encounter + * data packets with CRC errors or internal overrun scenarios, the auto ret + * ry feature causes the Host core to reply to the device with a non-termin + * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N + * umP != 0). If the Auto Retry feature is disabled (default), the core wil + * l respond with a terminating retry ACK (that is, an ACK transaction pack + * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut + * o Retry Enabled Note: This bit is also applicable to the device mode. +*/ +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT 14 +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK 0x00004000U + +/* +* If TRUE Completion Timeout Disable is supported. This is required to be + * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi + * ce Capability 2 [4]; EP=0x0001; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL +#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT +#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 9 +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 0x00000200U + +/* +* Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0x0004; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL +#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT +#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 0 +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 0x0000FFFFU + +/* +* Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0xFFF0; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL +#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT +#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 0 +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 0x0000FFFFU + +/* +* Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL +#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT +#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 0 +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 0x0000FFFFU + +/* +* Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL +#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT +#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 0 +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFFF +*/ +#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL +#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT +#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 0 +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0x00FF +*/ +#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL +#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT +#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 0 +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL +#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT +#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 0 +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0xFFFF +*/ +#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL +#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT +#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 0 +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFF0 +*/ +#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL +#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT +#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 0 +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0xFFF0 +*/ +#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL +#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT +#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 0 +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 +*/ +#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL +#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT +#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 0 +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 +*/ +#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL +#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT +#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 0 +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 0x0000FFFFU + +/* +* Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1 + * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa + * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo + * rted; EP=0x0001; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL +#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT +#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 0x00002138 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 8 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 0x00000700U + +/* +* Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca + * n withstand on transitions from L1 state to L0 (if L1 state supported). + * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to + * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For + * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL +#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT +#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 0x00002138 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 3 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 0x00000038U + +/* +* Identifies the type of device/port as follows: 0000b PCI Express Endpoin + * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P + * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110 + * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X + * Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre + * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM + * _FACING settings.; EP=0x0000; RP=0x0004 +*/ +#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL +#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT +#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 0x00009C02 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 4 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 0x000000F0U + +/* +* PCIe Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x009C; + * RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL +#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT +#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 0x00009C02 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 8 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 0x0000FF00U + +/* +* Number of credits that should be advertised for Completion data received + * on Virtual Channel 0. The bytes advertised must be less than or equal t + * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD +*/ +#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL +#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT +#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 0x000007FFU + +/* +* Number of credits that should be advertised for Completion headers recei + * ved on Virtual Channel 0. The sum of the posted, non posted, and complet + * ion header credits must be <= 80; EP=0x0048; RP=0x0024 +*/ +#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL +#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT +#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 0x00000248 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 0x0000007FU + +/* +* Number of credits that should be advertised for Non-Posted headers recei + * ved on Virtual Channel 0. The number of non posted data credits advertis + * ed by the block is equal to the number of non posted header credits. The + * sum of the posted, non posted, and completion header credits must be <= + * 80; EP=0x0004; RP=0x000C +*/ +#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL +#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT +#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 0x00000248 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 7 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 0x00003F80U + +/* +* Number of credits that should be advertised for Non-Posted data received + * on Virtual Channel 0. The number of non posted data credits advertised + * by the block is equal to two times the number of non posted header credi + * ts if atomic operations are supported or is equal to the number of non p + * osted header credits if atomic operations are not supported. The bytes a + * dvertised must be less than or equal to the bram bytes available. See VC + * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 +*/ +#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL +#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT +#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 0x000007FFU + +/* +* Number of credits that should be advertised for Posted data received on + * Virtual Channel 0. The bytes advertised must be less than or equal to th + * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 +*/ +#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL +#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT +#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 0x000007FFU + +/* +* Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_ + * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL +#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT +#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 15 +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 0x00008000U + +/* +* Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim + * TRUE == trim.; EP=0x0001; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL +#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT +#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 14 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 0x00004000U + +/* +* Enables ECRC check on received TLP's 0 == don't check 1 == always check + * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP= + * 0x0003; RP=0x0003 +*/ +#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL +#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT +#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 12 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 0x00003000U + +/* +* Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). + * Calculated from max payload size supported and the number of brams conf + * igured for transmit; EP=0x001C; RP=0x001C +*/ +#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL +#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT +#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 7 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 0x00000F80U + +/* +* Number of credits that should be advertised for Posted headers received + * on Virtual Channel 0. The sum of the posted, non posted, and completion + * header credits must be <= 80; EP=0x0004; RP=0x0020 +*/ +#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL +#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT +#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 0x0000007FU + +/* +* Specifies values to be transferred to Header Type register. Bit 7 should + * be set to '0' indicating single-function device. Bit 0 identifies heade + * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; + * RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL +#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT +#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 0x00000100 +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 0x000000FFU + +/* +* PM Capability's Next Capability Offset pointer to the next item in the c + * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP + * =0x0060 +*/ +#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL +#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT +#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 0x00003D48 +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 0 +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 0x000000FFU + +/* +* MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont + * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure; + * EP=0x0000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 9 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 0x00000200U + +/* +* Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U + +/* +* MSI Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x0060; R + * P=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 0 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 0x000000FFU + +/* +* Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U + +/* +* Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b + * x4, 001000b x8.; EP=0x0004; RP=0x0004 +*/ +#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL +#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT +#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 0x00000104 +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 0x0000003FU + +/* +* Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1 + * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004 +*/ +#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL +#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT +#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 0x00000104 +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 6 +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 0x00000FC0U + +/* +* TRUE specifies upstream-facing port. FALSE specifies downstream-facing p + * ort.; EP=0x0001; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL +#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT +#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 0x000000F0 +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 6 +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 0x00000040U + +/* +* Enable the routing of message TLPs to the user through the TRN RX interf + * ace. A bit value of 1 enables routing of the message TLP to the user. Me + * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 + * - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I + * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit + * 10 PME_Turn_Off; EP=0x0000; RP=0x07FF +*/ +#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL +#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT +#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 5 +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 0x0000FFE0U + +/* +* Disable BAR filtering. Does not change the behavior of the bar hit outpu + * ts; EP=0x0000; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL +#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT +#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 1 +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 0x00000002U + +/* +* Link Bandwidth notification capability. Indicates support for the link b + * andwidth notification status and interrupt mechanism. Required for Root. + * ; EP=0x0000; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 0x000009FF +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 9 +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 0x00000200U + +/* +* Maximum Link Speed. Valid settings are: 0001b [2.5 GT/s], 0010b [5.0 GT/ + * s and 2.5 GT/s].; EP=0x0002; RP=0x0002 +*/ +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_MAX_LINK_SPEED_DEFVAL +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_MAX_LINK_SPEED_SHIFT +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_MAX_LINK_SPEED_MASK +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_MAX_LINK_SPEED_DEFVAL 0x000009FF +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_MAX_LINK_SPEED_SHIFT 10 +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_MAX_LINK_SPEED_MASK 0x00003C00U + +/* +* Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op + * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001 + * ; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14 +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U + +/* +* Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value + * (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU + * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL +#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT +#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 15 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 0x00008000U + +/* +* Sets a user-defined timeout for the Replay Timer to force cause the retr + * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_ + * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att + * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.; + * EP=0x0000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL +#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT +#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 0 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 0x00007FFFU + +/* +* Device ID for the the PCIe Cap Structure Device ID field +*/ +#undef PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL +#undef PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT +#undef PCIE_ATTRIB_ID_CFG_DEV_ID_MASK +#define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 0x10EE7024 +#define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 0 +#define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 0x0000FFFFU + +/* +* Vendor ID for the PCIe Cap Structure Vendor ID field +*/ +#undef PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL +#undef PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT +#undef PCIE_ATTRIB_ID_CFG_VEND_ID_MASK +#define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 0x10EE7024 +#define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 16 +#define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 0xFFFF0000U + +/* +* Subsystem ID for the the PCIe Cap Structure Subsystem ID field +*/ +#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL +#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT +#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 0x10EE0007 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 0 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 0x0000FFFFU + +/* +* Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field +*/ +#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL +#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT +#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 0x10EE0007 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 16 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 0xFFFF0000U + +/* +* Revision ID for the the PCIe Cap Structure +*/ +#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL +#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT +#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 0 +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 0x000000FFU + +/* +* Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000 +*/ +#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL +#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT +#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 0x0000FFFFU + +/* +* Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006 +*/ +#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL +#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT +#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 0x000000FFU + +/* +* INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] + * to be hardwired to 0.; EP=0x0001; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL +#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT +#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 8 +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 0x00000100U + +/* +* Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL +#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT +#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U + +/* +* Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL +#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT +#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U + +/* +* VSEC's Next Capability Offset pointer to the next item in the capabiliti + * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140 +*/ +#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL +#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT +#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 0x00002281 +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 1 +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 0x00001FFEU + +/* +* CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the + * Root Capabilities register.; EP=0x0000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL +#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT +#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 5 +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 0x00000020U + +/* +* Indicates that the MSIX structures exists. If this is FALSE, then the MS + * IX structure cannot be accessed via either the link or the management po + * rt.; EP=0x0001; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL +#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT +#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100 +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U + +/* +* MSI-X Table Size. This value is transferred to the MSI-X Message Control + * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does + * not implement the table; that must be implemented in user logic.; EP=0x0 + * 003; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL +#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT +#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 0x000007FFU + +/* +* MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT +#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x0000FFFFU + +/* +* MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT +#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x00001FFFU + +/* +* MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL +#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT +#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFFFU + +/* +* MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL +#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT +#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 0x00008000 +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 3 +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFF8U + +/* +* DT837748 Enable +*/ +#undef PCIE_ATTRIB_CB_CB1_DEFVAL +#undef PCIE_ATTRIB_CB_CB1_SHIFT +#undef PCIE_ATTRIB_CB_CB1_MASK +#define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001 +#define PCIE_ATTRIB_CB_CB1_SHIFT 1 +#define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U + +/* +* Active State PM Support. Indicates the level of active state power manag + * ement supported by the selected PCI Express Link, encoded as follows: 0 + * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte + * d.; EP=0x0001; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL +#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT +#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12 +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U + +/* +* Data Link Layer Link Active status notification is supported. This is op + * tional for Upstream ports.; EP=0x0000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_DEFVAL +#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_SHIFT +#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_MASK +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_DEFVAL 0x00001FFD +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_SHIFT 15 +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_MASK 0x00008000U + +/* +* PCIE control block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U + +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U + +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU + +/* +* Status Read value of PLL Lock +*/ +#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL +#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT +#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L0_PLL_STATUS_READ_1_OFFSET 0XFD4023E4 + +/* +* Status Read value of PLL Lock +*/ +#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL +#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT +#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L1_PLL_STATUS_READ_1_OFFSET 0XFD4063E4 + +/* +* Status Read value of PLL Lock +*/ +#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL +#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT +#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L2_PLL_STATUS_READ_1_OFFSET 0XFD40A3E4 + +/* +* Status Read value of PLL Lock +*/ +#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL +#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT +#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L3_PLL_STATUS_READ_1_OFFSET 0XFD40E3E4 + +/* +* CIBGMN: COMINIT Burst Gap Minimum. +*/ +#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL +#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT +#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 0 +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 0x000000FFU + +/* +* CIBGMX: COMINIT Burst Gap Maximum. +*/ +#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL +#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT +#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 8 +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 0x0000FF00U + +/* +* CIBGN: COMINIT Burst Gap Nominal. +*/ +#undef SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL +#undef SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT +#undef SATA_AHCI_VENDOR_PP2C_CIBGN_MASK +#define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 16 +#define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 0x00FF0000U + +/* +* CINMP: COMINIT Negate Minimum Period. +*/ +#undef SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL +#undef SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT +#undef SATA_AHCI_VENDOR_PP2C_CINMP_MASK +#define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 24 +#define SATA_AHCI_VENDOR_PP2C_CINMP_MASK 0xFF000000U + +/* +* CWBGMN: COMWAKE Burst Gap Minimum. +*/ +#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL +#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT +#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 0 +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 0x000000FFU + +/* +* CWBGMX: COMWAKE Burst Gap Maximum. +*/ +#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL +#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT +#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 8 +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 0x0000FF00U + +/* +* CWBGN: COMWAKE Burst Gap Nominal. +*/ +#undef SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL +#undef SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT +#undef SATA_AHCI_VENDOR_PP3C_CWBGN_MASK +#define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 16 +#define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 0x00FF0000U + +/* +* CWNMP: COMWAKE Negate Minimum Period. +*/ +#undef SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL +#undef SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT +#undef SATA_AHCI_VENDOR_PP3C_CWNMP_MASK +#define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 24 +#define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 0xFF000000U + +/* +* BMX: COM Burst Maximum. +*/ +#undef SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL +#undef SATA_AHCI_VENDOR_PP4C_BMX_SHIFT +#undef SATA_AHCI_VENDOR_PP4C_BMX_MASK +#define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 0 +#define SATA_AHCI_VENDOR_PP4C_BMX_MASK 0x000000FFU + +/* +* BNM: COM Burst Nominal. +*/ +#undef SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL +#undef SATA_AHCI_VENDOR_PP4C_BNM_SHIFT +#undef SATA_AHCI_VENDOR_PP4C_BNM_MASK +#define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 8 +#define SATA_AHCI_VENDOR_PP4C_BNM_MASK 0x0000FF00U + +/* +* SFD: Signal Failure Detection, if the signal detection de-asserts for a + * time greater than this then the OOB detector will determine this is a li + * ne idle and cause the PhyInit state machine to exit the Phy Ready State. + * A value of zero disables the Signal Failure Detector. The value is base + * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving + * a nominal time of 500ns based on a 150MHz PMCLK. +*/ +#undef SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL +#undef SATA_AHCI_VENDOR_PP4C_SFD_SHIFT +#undef SATA_AHCI_VENDOR_PP4C_SFD_MASK +#define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 16 +#define SATA_AHCI_VENDOR_PP4C_SFD_MASK 0x00FF0000U + +/* +* PTST: Partial to Slumber timer value, specific delay the controller shou + * ld apply while in partial before entering slumber. The value is bases on + * the system clock divided by 128, total delay = (Sys Clock Period) * PTS + * T * 128 +*/ +#undef SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL +#undef SATA_AHCI_VENDOR_PP4C_PTST_SHIFT +#undef SATA_AHCI_VENDOR_PP4C_PTST_MASK +#define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 24 +#define SATA_AHCI_VENDOR_PP4C_PTST_MASK 0xFF000000U + +/* +* RIT: Retry Interval Timer. The calculated value divided by two, the lowe + * r digit of precision is not needed. +*/ +#undef SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL +#undef SATA_AHCI_VENDOR_PP5C_RIT_SHIFT +#undef SATA_AHCI_VENDOR_PP5C_RIT_MASK +#define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 0x3FFC96A4 +#define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 0 +#define SATA_AHCI_VENDOR_PP5C_RIT_MASK 0x000FFFFFU + +/* +* RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev + * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a + * fast SERDES it is suggested that this value be 54.2us / 4 +*/ +#undef SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL +#undef SATA_AHCI_VENDOR_PP5C_RCT_SHIFT +#undef SATA_AHCI_VENDOR_PP5C_RCT_MASK +#define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 0x3FFC96A4 +#define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 20 +#define SATA_AHCI_VENDOR_PP5C_RCT_MASK 0xFFF00000U +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef CRL_APB_RST_LPD_IOU0_OFFSET +#define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET +#define DP_DP_TX_PHY_POWER_DOWN_OFFSET 0XFD4A0238 +#undef DP_DP_PHY_RESET_OFFSET +#define DP_DP_PHY_RESET_OFFSET 0XFD4A0200 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 + +/* +* USB 0 reset for control registers +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U + +/* +* USB 0 sleep circuit reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U + +/* +* USB 0 reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U + +/* +* GEM 3 reset +*/ +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U + +/* +* Sata block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U + +/* +* PCIE config reset +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U + +/* +* PCIE control block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U + +/* +* PCIE bridge block level reset (AXI interface) +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U + +/* +* Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 +*/ +#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL +#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT +#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU + +/* +* Set to '1' to hold the GT in reset. Clear to release. +*/ +#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL +#undef DP_DP_PHY_RESET_GT_RESET_SHIFT +#undef DP_DP_PHY_RESET_GT_RESET_MASK +#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 +#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 +#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U + +/* +* Display Port block level reset (includes DPDMA) +*/ +#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U +#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET 0XFFD80118 +#undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET +#define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET 0XFFD80120 + +/* +* Power-up Request Interrupt Enable for PL +*/ +#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL +#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT +#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 0x00800000U + +/* +* Power-up Request Trigger for PL +*/ +#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL +#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT +#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 0x00800000U + +/* +* Power-up Request Status for PL +*/ +#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL +#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT +#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 0x00800000U +#define PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET 0XFFD80110 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef LPD_SLCR_AFI_FS_OFFSET +#define LPD_SLCR_AFI_FS_OFFSET 0XFF419000 +#undef AFIFM2_AFIFM_RDCTRL_OFFSET +#define AFIFM2_AFIFM_RDCTRL_OFFSET 0XFD380000 +#undef AFIFM2_AFIFM_WRCTRL_OFFSET +#define AFIFM2_AFIFM_WRCTRL_OFFSET 0XFD380014 + +/* +* AF_FM0 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT 7 +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK 0x00000080U + +/* +* AF_FM1 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT 8 +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK 0x00000100U + +/* +* AF_FM2 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT 9 +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK 0x00000200U + +/* +* AF_FM3 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT 10 +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK 0x00000400U + +/* +* AF_FM4 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT 11 +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK 0x00000800U + +/* +* AF_FM5 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT 12 +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK 0x00001000U + +/* +* AFI FM 6 +*/ +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT 19 +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK 0x00080000U + +/* +* Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved +*/ +#undef LPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL +#undef LPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT +#undef LPD_SLCR_AFI_FS_DW_SS2_SEL_MASK +#define LPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL 0x00000200 +#define LPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT 8 +#define LPD_SLCR_AFI_FS_DW_SS2_SEL_MASK 0x00000300U + +/* +* Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b + * 10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128-bit enabled +*/ +#undef AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL +#undef AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT +#undef AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_MASK +#define AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0 +#define AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT 0 +#define AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_MASK 0x00000003U + +/* +* Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2' + * b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128-bit enabled +*/ +#undef AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL +#undef AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT +#undef AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_MASK +#define AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0 +#define AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT 0 +#define AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_MASK 0x00000003U +#undef GPIO_MASK_DATA_5_MSW_OFFSET +#define GPIO_MASK_DATA_5_MSW_OFFSET 0XFF0A002C +#undef GPIO_DIRM_5_OFFSET +#define GPIO_DIRM_5_OFFSET 0XFF0A0344 +#undef GPIO_OEN_5_OFFSET +#define GPIO_OEN_5_OFFSET 0XFF0A0348 +#undef GPIO_DATA_5_OFFSET +#define GPIO_DATA_5_OFFSET 0XFF0A0054 +#undef GPIO_DATA_5_OFFSET +#define GPIO_DATA_5_OFFSET 0XFF0A0054 +#undef GPIO_DATA_5_OFFSET +#define GPIO_DATA_5_OFFSET 0XFF0A0054 + +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL +#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT +#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 16 +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 0xFFFF0000U + +/* +* Operation is the same as DIRM_0[DIRECTION_0] +*/ +#undef GPIO_DIRM_5_DIRECTION_5_DEFVAL +#undef GPIO_DIRM_5_DIRECTION_5_SHIFT +#undef GPIO_DIRM_5_DIRECTION_5_MASK +#define GPIO_DIRM_5_DIRECTION_5_DEFVAL +#define GPIO_DIRM_5_DIRECTION_5_SHIFT 0 +#define GPIO_DIRM_5_DIRECTION_5_MASK 0xFFFFFFFFU + +/* +* Operation is the same as OEN_0[OP_ENABLE_0] +*/ +#undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL +#undef GPIO_OEN_5_OP_ENABLE_5_SHIFT +#undef GPIO_OEN_5_OP_ENABLE_5_MASK +#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL +#define GPIO_OEN_5_OP_ENABLE_5_SHIFT 0 +#define GPIO_OEN_5_OP_ENABLE_5_MASK 0xFFFFFFFFU + +/* +* Output Data +*/ +#undef GPIO_DATA_5_DATA_5_DEFVAL +#undef GPIO_DATA_5_DATA_5_SHIFT +#undef GPIO_DATA_5_DATA_5_MASK +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU + +/* +* Output Data +*/ +#undef GPIO_DATA_5_DATA_5_DEFVAL +#undef GPIO_DATA_5_DATA_5_SHIFT +#undef GPIO_DATA_5_DATA_5_MASK +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU + +/* +* Output Data +*/ +#undef GPIO_DATA_5_DATA_5_DEFVAL +#undef GPIO_DATA_5_DATA_5_SHIFT +#undef GPIO_DATA_5_DATA_5_MASK +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU +#ifdef __cplusplus +extern "C" { +#endif + int psu_init (); + unsigned long psu_ps_pl_isolation_removal_data(); + unsigned long psu_ps_pl_reset_config_data(); + int psu_protection(); + int psu_fpd_protection(); + int psu_ocm_protection(); + int psu_ddr_protection(); + int psu_lpd_protection(); + int psu_protection_lock(); + unsigned long psu_ddr_qos_init_data(void); + unsigned long psu_apply_master_tz(); +#ifdef __cplusplus +} +#endif diff --git a/Petalinux/project-spec/hw-description/psu_init.html b/Petalinux/project-spec/hw-description/psu_init.html new file mode 100644 index 0000000..8f9bd3c --- /dev/null +++ b/Petalinux/project-spec/hw-description/psu_init.html @@ -0,0 +1,3087 @@ + + + + +Zynq UltraScale+ MPSoC PS configuration detail + + + +
+
+ +
  • +
    Zynq UltraScale+ PS Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq UltraScale+ Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    GT Configurations +
    +     +
    +
    This design is targeted for xczu7ev board (part number: xczu7ev-ffvc1156-2-e) + +
    +

    Zynq UltraScale+ Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xczu7ev +
    +SpeedGrade + +-2 +
    +Part + +xczu7ev-ffvc1156-2-e +
    +Description + +Zynq UltraScale+ PS Configuration Report +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction + +Drive Strength(mA) +
    +MIO 0 + +Quad SPI Flash + +sclk_out + +cmos + +slow + +pullup + +out + +12 +
    +MIO 1 + +Quad SPI Flash + +miso_mo1 + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 2 + +Quad SPI Flash + +mo2 + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 3 + +Quad SPI Flash + +mo3 + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 4 + +Quad SPI Flash + +mosi_mi0 + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 5 + +Quad SPI Flash + +n_ss_out + +cmos + +slow + +pullup + +out + +12 +
    +MIO 6 + +Feedback Clk + +clk_for_lpbk + +cmos + +slow + +pullup + +out + +12 +
    +MIO 7 + +Quad SPI Flash + +n_ss_out_upper + +cmos + +slow + +pullup + +out + +12 +
    +MIO 8 + +Quad SPI Flash + +mo_upper[0] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 9 + +Quad SPI Flash + +mo_upper[1] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 10 + +Quad SPI Flash + +mo_upper[2] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 11 + +Quad SPI Flash + +mo_upper[3] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 12 + +Quad SPI Flash + +sclk_out_upper + +cmos + +slow + +pullup + +out + +12 +
    +MIO 13 + +GPIO0 MIO + +gpio0[13] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 14 + +I2C 0 + +scl_out + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 15 + +I2C 0 + +sda_out + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 16 + +I2C 1 + +scl_out + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 17 + +I2C 1 + +sda_out + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 18 + +UART 0 + +rxd + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 19 + +UART 0 + +txd + +cmos + +slow + +pullup + +out + +12 +
    +MIO 20 + +UART 1 + +txd + +cmos + +slow + +pullup + +out + +12 +
    +MIO 21 + +UART 1 + +rxd + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 22 + +GPIO0 MIO + +gpio0[22] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 23 + +GPIO0 MIO + +gpio0[23] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 24 + +CAN 1 + +phy_tx + +cmos + +slow + +pullup + +out + +12 +
    +MIO 25 + +CAN 1 + +phy_rx + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 26 + +GPIO1 MIO + +gpio1[26] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 27 + +DPAUX + +dp_aux_data_out + +cmos + +slow + +pullup + +out + +12 +
    +MIO 28 + +DPAUX + +dp_hot_plug_detect + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 29 + +DPAUX + +dp_aux_data_oe + +cmos + +slow + +pullup + +out + +12 +
    +MIO 30 + +DPAUX + +dp_aux_data_in + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 31 + +PCIE + +reset_n + +cmos + +slow + +pullup + +out + +12 +
    +MIO 32 + +PMU GPO 0 + +gpo[0] + +cmos + +slow + +pullup + +out + +12 +
    +MIO 33 + +PMU GPO 1 + +gpo[1] + +cmos + +slow + +pullup + +out + +12 +
    +MIO 34 + +PMU GPO 2 + +gpo[2] + +cmos + +slow + +pullup + +out + +12 +
    +MIO 35 + +PMU GPO 3 + +gpo[3] + +cmos + +slow + +pullup + +out + +12 +
    +MIO 36 + +PMU GPO 4 + +gpo[4] + +cmos + +slow + +pullup + +out + +12 +
    +MIO 37 + +PMU GPO 5 + +gpo[5] + +cmos + +slow + +pullup + +out + +12 +
    +MIO 38 + +GPIO1 MIO + +gpio1[38] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 39 + +SD 1 + +sdio1_data_out[4] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 40 + +SD 1 + +sdio1_data_out[5] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 41 + +SD 1 + +sdio1_data_out[6] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 42 + +SD 1 + +sdio1_data_out[7] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 43 + +SD 1 + +sdio1_bus_pow + +cmos + +slow + +pullup + +out + +12 +
    +MIO 44 + +SD 1 + +sdio1_wp + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 45 + +SD 1 + +sdio1_cd_n + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 46 + +SD 1 + +sdio1_data_out[0] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 47 + +SD 1 + +sdio1_data_out[1] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 48 + +SD 1 + +sdio1_data_out[2] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 49 + +SD 1 + +sdio1_data_out[3] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 50 + +SD 1 + +sdio1_cmd_out + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 51 + +SD 1 + +sdio1_clk_out + +cmos + +slow + +pullup + +out + +12 +
    +MIO 52 + +USB 0 + +ulpi_clk_in + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 53 + +USB 0 + +ulpi_dir + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 54 + +USB 0 + +ulpi_tx_data[2] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 55 + +USB 0 + +ulpi_nxt + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 56 + +USB 0 + +ulpi_tx_data[0] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 57 + +USB 0 + +ulpi_tx_data[1] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 58 + +USB 0 + +ulpi_stp + +cmos + +slow + +pullup + +out + +12 +
    +MIO 59 + +USB 0 + +ulpi_tx_data[3] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 60 + +USB 0 + +ulpi_tx_data[4] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 61 + +USB 0 + +ulpi_tx_data[5] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 62 + +USB 0 + +ulpi_tx_data[6] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 63 + +USB 0 + +ulpi_tx_data[7] + +schmitt + +slow + +pullup + +inout + +12 +
    +MIO 64 + +Gem 3 + +rgmii_tx_clk + +cmos + +slow + +pullup + +out + +12 +
    +MIO 65 + +Gem 3 + +rgmii_txd[0] + +cmos + +slow + +pullup + +out + +12 +
    +MIO 66 + +Gem 3 + +rgmii_txd[1] + +cmos + +slow + +pullup + +out + +12 +
    +MIO 67 + +Gem 3 + +rgmii_txd[2] + +cmos + +slow + +pullup + +out + +12 +
    +MIO 68 + +Gem 3 + +rgmii_txd[3] + +cmos + +slow + +pullup + +out + +12 +
    +MIO 69 + +Gem 3 + +rgmii_tx_ctl + +cmos + +slow + +pullup + +out + +12 +
    +MIO 70 + +Gem 3 + +rgmii_rx_clk + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 71 + +Gem 3 + +rgmii_rxd[0] + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 72 + +Gem 3 + +rgmii_rxd[1] + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 73 + +Gem 3 + +rgmii_rxd[2] + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 74 + +Gem 3 + +rgmii_rxd[3] + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 75 + +Gem 3 + +rgmii_rx_ctl + +schmitt + +fast + +pullup + +in + +12 +
    +MIO 76 + +MDIO 3 + +gem3_mdc + +cmos + +slow + +pullup + +out + +12 +
    +MIO 77 + +MDIO 3 + +gem3_mdio_out + +schmitt + +slow + +pullup + +inout + +12 +
    +

    PS Clocks information

    +PSS REF CLK : 33.333 +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Name + +Source + +Input Frequency (MHz) +
    +APLL + +PSS_REF_CLK + +2399.976 +
    +DPLL + +PSS_REF_CLK + +2133.312 +
    +VPLL + +PSS_REF_CLK + +2999.970 +
    +RPLL + +PSS_REF_CLK + +2999.970 +
    +IOPLL + +PSS_REF_CLK + +2999.970 +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +Requested Frequency (MHz) + +Source + +Actual Frequency (MHz) +
    +GEM3 freq (MHz) + +125 + +IOPLL + +124.998749 +
    +USB0 freq (MHz) + +250 + +IOPLL + +249.997498 +
    +QSPI freq (MHz) + +300 + +IOPLL + +299.997009 +
    +SDIO1 freq (MHz) + +200 + +IOPLL + +187.498123 +
    +UART0 freq (MHz) + +100 + +IOPLL + +99.999001 +
    +UART1 freq (MHz) + +100 + +IOPLL + +99.999001 +
    +I2C0 freq (MHz) + +100 + +IOPLL + +99.999001 +
    +I2C1 freq (MHz) + +100 + +IOPLL + +99.999001 +
    +CAN1 freq (MHz) + +100 + +IOPLL + +99.999001 +
    +CPU_R5 freq (MHz) + +533.333 + +IOPLL + +499.994995 +
    +IOU_SWITCH freq (MHz) + +267 + +IOPLL + +249.997498 +
    +LPD_SWITCH freq (MHz) + +533.333 + +IOPLL + +499.994995 +
    +LPD_LSBUS freq (MHz) + +100 + +IOPLL + +99.999001 +
    +GEM_TSU freq (MHz) + +250 + +IOPLL + +249.997498 +
    +TIMESTAMP freq (MHz) + +100 + +IOPLL + +99.999001 +
    +PSU__CRL_APB__USB3_REF_CTRL__freqmhz + +20 + +IOPLL + +19.999800 +
    +PCAP freq (MHz) + +200 + +IOPLL + +187.498123 +
    +DBG_LPD freq (MHz) + +250 + +IOPLL + +249.997498 +
    +ADMA freq (MHz) + +533.333 + +IOPLL + +499.994995 +
    +PL0 freq (MHz) + +125 + +RPLL + +124.998749 +
    +PL1 freq (MHz) + +100 + +RPLL + +99.999001 +
    +AMS freq (MHz) + +50 + +IOPLL + +49.999500 +
    +ACPU freq (MHz) + +1333.333 + +APLL + +1199.988037 +
    +DBG FPD freq (MHz) + +250 + +IOPLL + +249.997498 +
    +DP VIDEO freq (MHz) + +300 + +VPLL + +299.997009 +
    +DP AUDIO freq (MHz) + +25 + +RPLL + +24.999750 +
    +DP STC freq (MHz) + +27 + +RPLL + +26.315527 +
    +SATA freq (MHz) + +250 + +IOPLL + +249.997498 +
    +PCIE freq (MHz) + +250 + +IOPLL + +249.997498 +
    +DDR_CTRL freq MHz) + +533.500 + +DPLL + +533.328003 +
    +GPU freq (MHz) + +600 + +IOPLL + +499.994995 +
    +GDMA freq (MHz) + +600 + +APLL + +599.994019 +
    +DPDMA freq (MHz) + +600 + +APLL + +599.994019 +
    +TOPSW_MAIN freq (MHz) + +533.333 + +DPLL + +533.328003 +
    +TOPSW_LSBUS freq (MHz) + +100 + +IOPLL + +99.999001 +
    +DBG TSTMP freq (MHz) + +250 + +IOPLL + +249.997498 +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +ENABLE + +1 + +Enable the PS DDR Controller +
    +DDR Interface freq (MHz) + +1067 + +-- +
    +MEMORY TYPE + +DDR 4 + +Type of memory interface +
    +DM DBI + +UDIMM + + +
    +BUS WIDTH + +64 Bit + +Data width of DDR interface, not including ECC data width +
    +ECC + +Disabled + +Enables error correction code support +
    +SPEED BIN + +DDR4_2133P + +Speed Bin +
    +CL + +15 + +Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CWL + +14 + +CAS write latency setting in memory clock cycles +
    +DDR AL + +0 + +Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +T RCD + +15 + +tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +T RP + +15 + +Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row +
    +T RC + +47.06 + +Row cycle time (ns) +
    +T RAS MIN + +33 + +Minimum number of memory clock cycles required between an Active and Precharge command +
    +T FAW + +30.0 + +Determines the number of activates that can be performed within a certain window of time +
    +DRAM WIDTH + +16 Bits + +Width of individual DRAM components +
    +DEVICE CAPACITY + +8192 MBits + +Storage capacity of individual DRAM components +
    +BG ADDR COUNT + +1 + +Number of bank group address pins +
    +RANK ADDR COUNT + +0 + +Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N) +
    +BANK ADDR COUNT + +2 + +Number of bank address pins +
    +ROW ADDR COUNT + +16 + +Number of row address pins +
    +COL ADDR COUNT + +10 + +Number of column address bits +
    +C_DDR_RAM_HIGHADDR + +0xFFFFFFFF + +-- +
    +

    GT lanes information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Protocol + +GT lane# + +Ref Clk Sel + +Ref freq (MHz) +
    +PCIe + +GT Lane0 + +Ref Clk0 + +100 +
    +DP + +GT Lane1 + +Ref Clk3 + +27 +
    +USB0 + +GT Lane2 + +Ref Clk2 + +26 +
    +SATA + +GT Lane3 + +Ref Clk1 + +125 +
    +
    +
    + + + + diff --git a/Petalinux/project-spec/hw-description/psu_init.tcl b/Petalinux/project-spec/hw-description/psu_init.tcl new file mode 100644 index 0000000..b94425d --- /dev/null +++ b/Petalinux/project-spec/hw-description/psu_init.tcl @@ -0,0 +1,18127 @@ +#**************************************************************************** +### +# +# @file psu_init.tcl +# +# This file is automatically generated +# +#**************************************************************************** +set psu_pll_init_data { + # : RPLL INIT + # Register : RPLL_CFG @ 0XFF5E0034

    + + # PLL loop filter resistor control + # PSU_CRL_APB_RPLL_CFG_RES 0x2 + + # PLL charge pump control + # PSU_CRL_APB_RPLL_CFG_CP 0x4 + + # PLL loop filter high frequency capacitor control + # PSU_CRL_APB_RPLL_CFG_LFHF 0x3 + + # Lock circuit counter setting + # PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x258 + + # Lock circuit configuration settings for lock windowsize + # PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f + + # Helper data. Values are to be looked up in a table from Data Sheet + #(OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C82U) */ + mask_write 0XFF5E0034 0xFE7FEDEF 0x7E4B0C82 + # : UPDATE FB_DIV + # Register : RPLL_CTRL @ 0XFF5E0030

    + + # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + # PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0 + + # The integer portion of the feedback divider to the PLL + # PSU_CRL_APB_RPLL_CTRL_FBDIV 0x5a + + # This turns on the divide by 2 that is inside of the PLL. This does not c + # hange the VCO frequency, just the output frequency + # PSU_CRL_APB_RPLL_CTRL_DIV2 0x1 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00015A00U) */ + mask_write 0XFF5E0030 0x00717F00 0x00015A00 + # : BY PASS PLL + # Register : RPLL_CTRL @ 0XFF5E0030

    + + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) + # PSU_CRL_APB_RPLL_CTRL_BYPASS 1 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) */ + mask_write 0XFF5E0030 0x00000008 0x00000008 + # : ASSERT RESET + # Register : RPLL_CTRL @ 0XFF5E0030

    + + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. + # PSU_CRL_APB_RPLL_CTRL_RESET 1 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) */ + mask_write 0XFF5E0030 0x00000001 0x00000001 + # : DEASSERT RESET + # Register : RPLL_CTRL @ 0XFF5E0030

    + + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. + # PSU_CRL_APB_RPLL_CTRL_RESET 0 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) */ + mask_write 0XFF5E0030 0x00000001 0x00000000 + # : CHECK PLL STATUS + # Register : PLL_STATUS @ 0XFF5E0040

    + + # RPLL is locked + # PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1 + mask_poll 0XFF5E0040 0x00000002 + # : REMOVE PLL BY PASS + # Register : RPLL_CTRL @ 0XFF5E0030

    + + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) + # PSU_CRL_APB_RPLL_CTRL_BYPASS 0 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U) */ + mask_write 0XFF5E0030 0x00000008 0x00000000 + # Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048

    + + # Divisor value for this clock. + # PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x3 + + # Control for a clock that will be generated in the LPD, but used in the F + # PD as a clock source for the peripheral clock muxes. + #(OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000300U) */ + mask_write 0XFF5E0048 0x00003F00 0x00000300 + # : RPLL FRAC CFG + # : SYSMON CLOCK PRESET TO RPLL AGAIN TO AVOID GLITCH WHEN NEXT IOPLL WILL BE PUT IN BYPASS MODE + # Register : AMS_REF_CTRL @ 0XFF5E0108

    + + # 6 bit divider + # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 1 + + # 6 bit divider + # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 35 + + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_AMS_REF_CTRL_CLKACT 1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01012300U) */ + mask_write 0XFF5E0108 0x013F3F07 0x01012300 + # : IOPLL INIT + # Register : IOPLL_CFG @ 0XFF5E0024

    + + # PLL loop filter resistor control + # PSU_CRL_APB_IOPLL_CFG_RES 0x2 + + # PLL charge pump control + # PSU_CRL_APB_IOPLL_CFG_CP 0x4 + + # PLL loop filter high frequency capacitor control + # PSU_CRL_APB_IOPLL_CFG_LFHF 0x3 + + # Lock circuit counter setting + # PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x258 + + # Lock circuit configuration settings for lock windowsize + # PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f + + # Helper data. Values are to be looked up in a table from Data Sheet + #(OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E4B0C82U) */ + mask_write 0XFF5E0024 0xFE7FEDEF 0x7E4B0C82 + # : UPDATE FB_DIV + # Register : IOPLL_CTRL @ 0XFF5E0020

    + + # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + # PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0 + + # The integer portion of the feedback divider to the PLL + # PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x5a + + # This turns on the divide by 2 that is inside of the PLL. This does not c + # hange the VCO frequency, just the output frequency + # PSU_CRL_APB_IOPLL_CTRL_DIV2 0x1 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00015A00U) */ + mask_write 0XFF5E0020 0x00717F00 0x00015A00 + # : BY PASS PLL + # Register : IOPLL_CTRL @ 0XFF5E0020

    + + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) + # PSU_CRL_APB_IOPLL_CTRL_BYPASS 1 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U) */ + mask_write 0XFF5E0020 0x00000008 0x00000008 + # : ASSERT RESET + # Register : IOPLL_CTRL @ 0XFF5E0020

    + + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. + # PSU_CRL_APB_IOPLL_CTRL_RESET 1 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U) */ + mask_write 0XFF5E0020 0x00000001 0x00000001 + # : DEASSERT RESET + # Register : IOPLL_CTRL @ 0XFF5E0020

    + + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. + # PSU_CRL_APB_IOPLL_CTRL_RESET 0 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U) */ + mask_write 0XFF5E0020 0x00000001 0x00000000 + # : CHECK PLL STATUS + # Register : PLL_STATUS @ 0XFF5E0040

    + + # IOPLL is locked + # PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1 + mask_poll 0XFF5E0040 0x00000001 + # : REMOVE PLL BY PASS + # Register : IOPLL_CTRL @ 0XFF5E0020

    + + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) + # PSU_CRL_APB_IOPLL_CTRL_BYPASS 0 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U) */ + mask_write 0XFF5E0020 0x00000008 0x00000000 + # Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044

    + + # Divisor value for this clock. + # PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3 + + # Control for a clock that will be generated in the LPD, but used in the F + # PD as a clock source for the peripheral clock muxes. + #(OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) */ + mask_write 0XFF5E0044 0x00003F00 0x00000300 + # : IOPLL FRAC CFG + # : APU_PLL INIT + # Register : APLL_CFG @ 0XFD1A0024

    + + # PLL loop filter resistor control + # PSU_CRF_APB_APLL_CFG_RES 0x2 + + # PLL charge pump control + # PSU_CRF_APB_APLL_CFG_CP 0x3 + + # PLL loop filter high frequency capacitor control + # PSU_CRF_APB_APLL_CFG_LFHF 0x3 + + # Lock circuit counter setting + # PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258 + + # Lock circuit configuration settings for lock windowsize + # PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f + + # Helper data. Values are to be looked up in a table from Data Sheet + #(OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U) */ + mask_write 0XFD1A0024 0xFE7FEDEF 0x7E4B0C62 + # : UPDATE FB_DIV + # Register : APLL_CTRL @ 0XFD1A0020

    + + # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + # PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0 + + # The integer portion of the feedback divider to the PLL + # PSU_CRF_APB_APLL_CTRL_FBDIV 0x48 + + # This turns on the divide by 2 that is inside of the PLL. This does not c + # hange the VCO frequency, just the output frequency + # PSU_CRF_APB_APLL_CTRL_DIV2 0x1 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014800U) */ + mask_write 0XFD1A0020 0x00717F00 0x00014800 + # : BY PASS PLL + # Register : APLL_CTRL @ 0XFD1A0020

    + + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) + # PSU_CRF_APB_APLL_CTRL_BYPASS 1 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U) */ + mask_write 0XFD1A0020 0x00000008 0x00000008 + # : ASSERT RESET + # Register : APLL_CTRL @ 0XFD1A0020

    + + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. + # PSU_CRF_APB_APLL_CTRL_RESET 1 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U) */ + mask_write 0XFD1A0020 0x00000001 0x00000001 + # : DEASSERT RESET + # Register : APLL_CTRL @ 0XFD1A0020

    + + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. + # PSU_CRF_APB_APLL_CTRL_RESET 0 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U) */ + mask_write 0XFD1A0020 0x00000001 0x00000000 + # : CHECK PLL STATUS + # Register : PLL_STATUS @ 0XFD1A0044

    + + # APLL is locked + # PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1 + mask_poll 0XFD1A0044 0x00000001 + # : REMOVE PLL BY PASS + # Register : APLL_CTRL @ 0XFD1A0020

    + + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) + # PSU_CRF_APB_APLL_CTRL_BYPASS 0 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U) */ + mask_write 0XFD1A0020 0x00000008 0x00000000 + # Register : APLL_TO_LPD_CTRL @ 0XFD1A0048

    + + # Divisor value for this clock. + # PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3 + + # Control for a clock that will be generated in the FPD, but used in the L + # PD as a clock source for the peripheral clock muxes. + #(OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) */ + mask_write 0XFD1A0048 0x00003F00 0x00000300 + # : APLL FRAC CFG + # : DDR_PLL INIT + # Register : DPLL_CFG @ 0XFD1A0030

    + + # PLL loop filter resistor control + # PSU_CRF_APB_DPLL_CFG_RES 0x2 + + # PLL charge pump control + # PSU_CRF_APB_DPLL_CFG_CP 0x3 + + # PLL loop filter high frequency capacitor control + # PSU_CRF_APB_DPLL_CFG_LFHF 0x3 + + # Lock circuit counter setting + # PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258 + + # Lock circuit configuration settings for lock windowsize + # PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f + + # Helper data. Values are to be looked up in a table from Data Sheet + #(OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U) */ + mask_write 0XFD1A0030 0xFE7FEDEF 0x7E4B0C62 + # : UPDATE FB_DIV + # Register : DPLL_CTRL @ 0XFD1A002C

    + + # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + # PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0 + + # The integer portion of the feedback divider to the PLL + # PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40 + + # This turns on the divide by 2 that is inside of the PLL. This does not c + # hange the VCO frequency, just the output frequency + # PSU_CRF_APB_DPLL_CTRL_DIV2 0x1 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U) */ + mask_write 0XFD1A002C 0x00717F00 0x00014000 + # : BY PASS PLL + # Register : DPLL_CTRL @ 0XFD1A002C

    + + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) + # PSU_CRF_APB_DPLL_CTRL_BYPASS 1 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U) */ + mask_write 0XFD1A002C 0x00000008 0x00000008 + # : ASSERT RESET + # Register : DPLL_CTRL @ 0XFD1A002C

    + + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. + # PSU_CRF_APB_DPLL_CTRL_RESET 1 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U) */ + mask_write 0XFD1A002C 0x00000001 0x00000001 + # : DEASSERT RESET + # Register : DPLL_CTRL @ 0XFD1A002C

    + + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. + # PSU_CRF_APB_DPLL_CTRL_RESET 0 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U) */ + mask_write 0XFD1A002C 0x00000001 0x00000000 + # : CHECK PLL STATUS + # Register : PLL_STATUS @ 0XFD1A0044

    + + # DPLL is locked + # PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1 + mask_poll 0XFD1A0044 0x00000002 + # : REMOVE PLL BY PASS + # Register : DPLL_CTRL @ 0XFD1A002C

    + + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) + # PSU_CRF_APB_DPLL_CTRL_BYPASS 0 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U) */ + mask_write 0XFD1A002C 0x00000008 0x00000000 + # Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C

    + + # Divisor value for this clock. + # PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x2 + + # Control for a clock that will be generated in the FPD, but used in the L + # PD as a clock source for the peripheral clock muxes. + #(OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000200U) */ + mask_write 0XFD1A004C 0x00003F00 0x00000200 + # : DPLL FRAC CFG + # : VIDEO_PLL INIT + # Register : VPLL_CFG @ 0XFD1A003C

    + + # PLL loop filter resistor control + # PSU_CRF_APB_VPLL_CFG_RES 0x2 + + # PLL charge pump control + # PSU_CRF_APB_VPLL_CFG_CP 0x4 + + # PLL loop filter high frequency capacitor control + # PSU_CRF_APB_VPLL_CFG_LFHF 0x3 + + # Lock circuit counter setting + # PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x258 + + # Lock circuit configuration settings for lock windowsize + # PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f + + # Helper data. Values are to be looked up in a table from Data Sheet + #(OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E4B0C82U) */ + mask_write 0XFD1A003C 0xFE7FEDEF 0x7E4B0C82 + # : UPDATE FB_DIV + # Register : VPLL_CTRL @ 0XFD1A0038

    + + # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + # PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0 + + # The integer portion of the feedback divider to the PLL + # PSU_CRF_APB_VPLL_CTRL_FBDIV 0x5a + + # This turns on the divide by 2 that is inside of the PLL. This does not c + # hange the VCO frequency, just the output frequency + # PSU_CRF_APB_VPLL_CTRL_DIV2 0x1 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00015A00U) */ + mask_write 0XFD1A0038 0x00717F00 0x00015A00 + # : BY PASS PLL + # Register : VPLL_CTRL @ 0XFD1A0038

    + + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) + # PSU_CRF_APB_VPLL_CTRL_BYPASS 1 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U) */ + mask_write 0XFD1A0038 0x00000008 0x00000008 + # : ASSERT RESET + # Register : VPLL_CTRL @ 0XFD1A0038

    + + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. + # PSU_CRF_APB_VPLL_CTRL_RESET 1 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U) */ + mask_write 0XFD1A0038 0x00000001 0x00000001 + # : DEASSERT RESET + # Register : VPLL_CTRL @ 0XFD1A0038

    + + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. + # PSU_CRF_APB_VPLL_CTRL_RESET 0 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U) */ + mask_write 0XFD1A0038 0x00000001 0x00000000 + # : CHECK PLL STATUS + # Register : PLL_STATUS @ 0XFD1A0044

    + + # VPLL is locked + # PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1 + mask_poll 0XFD1A0044 0x00000004 + # : REMOVE PLL BY PASS + # Register : VPLL_CTRL @ 0XFD1A0038

    + + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) + # PSU_CRF_APB_VPLL_CTRL_BYPASS 0 + + # PLL Basic Control + #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U) */ + mask_write 0XFD1A0038 0x00000008 0x00000000 + # Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050

    + + # Divisor value for this clock. + # PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3 + + # Control for a clock that will be generated in the FPD, but used in the L + # PD as a clock source for the peripheral clock muxes. + #(OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) */ + mask_write 0XFD1A0050 0x00003F00 0x00000300 + # : VIDEO FRAC CFG +} + +set psu_clock_init_data { + # : CLOCK CONTROL SLCR REGISTER + # Register : GEM3_REF_CTRL @ 0XFF5E005C

    + + # Clock active for the RX channel + # PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1 + + # 6 bit divider + # PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc + + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) */ + mask_write 0XFF5E005C 0x063F3F07 0x06010C00 + # Register : GEM_TSU_REF_CTRL @ 0XFF5E0100

    + + # 6 bit divider + # PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6 + + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x0 + + # 6 bit divider + # PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010600U) */ + mask_write 0XFF5E0100 0x013F3F07 0x01010600 + # Register : USB0_BUS_REF_CTRL @ 0XFF5E0060

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1 + + # 6 bit divider + # PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6 + + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U) */ + mask_write 0XFF5E0060 0x023F3F07 0x02010600 + # Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0x3 + + # 6 bit divider + # PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x19 + + # 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x02031900U) */ + mask_write 0XFF5E004C 0x023F3F07 0x02031900 + # Register : QSPI_REF_CTRL @ 0XFF5E0068

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1 + + # 6 bit divider + # PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0x5 + + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010500U) */ + mask_write 0XFF5E0068 0x013F3F07 0x01010500 + # Register : SDIO1_REF_CTRL @ 0XFF5E0070

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1 + + # 6 bit divider + # PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x8 + + # 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x0 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010800U) */ + mask_write 0XFF5E0070 0x013F3F07 0x01010800 + # Register : SDIO_CLK_CTRL @ 0XFF18030C

    + + # MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO + # [51] 1: MIO [76] + # PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0 + + # SoC Debug Clock Control + #(OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U) */ + mask_write 0XFF18030C 0x00020000 0x00000000 + # Register : UART0_REF_CTRL @ 0XFF5E0074

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1 + + # 6 bit divider + # PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf + + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U) */ + mask_write 0XFF5E0074 0x013F3F07 0x01010F00 + # Register : UART1_REF_CTRL @ 0XFF5E0078

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1 + + # 6 bit divider + # PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf + + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U) */ + mask_write 0XFF5E0078 0x013F3F07 0x01010F00 + # Register : I2C0_REF_CTRL @ 0XFF5E0120

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1 + + # 6 bit divider + # PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf + + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U) */ + mask_write 0XFF5E0120 0x013F3F07 0x01010F00 + # Register : I2C1_REF_CTRL @ 0XFF5E0124

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1 + + # 6 bit divider + # PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf + + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U) */ + mask_write 0XFF5E0124 0x013F3F07 0x01010F00 + # Register : CAN1_REF_CTRL @ 0XFF5E0088

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1 + + # 6 bit divider + # PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf + + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U) */ + mask_write 0XFF5E0088 0x013F3F07 0x01010F00 + # Register : CPU_R5_CTRL @ 0XFF5E0090

    + + # Turing this off will shut down the OCM, some parts of the APM, and preve + # nt transactions going from the FPD to the LPD and could lead to system h + # ang + # PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3 + + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U) */ + mask_write 0XFF5E0090 0x01003F07 0x01000302 + # Register : IOU_SWITCH_CTRL @ 0XFF5E009C

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6 + + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U) */ + mask_write 0XFF5E009C 0x01003F07 0x01000602 + # Register : PCAP_CTRL @ 0XFF5E00A4

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x8 + + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x0 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000800U) */ + mask_write 0XFF5E00A4 0x01003F07 0x01000800 + # Register : LPD_SWITCH_CTRL @ 0XFF5E00A8

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3 + + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U) */ + mask_write 0XFF5E00A8 0x01003F07 0x01000302 + # Register : LPD_LSBUS_CTRL @ 0XFF5E00AC

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf + + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U) */ + mask_write 0XFF5E00AC 0x01003F07 0x01000F02 + # Register : DBG_LPD_CTRL @ 0XFF5E00B0

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6 + + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U) */ + mask_write 0XFF5E00B0 0x01003F07 0x01000602 + # Register : ADMA_REF_CTRL @ 0XFF5E00B8

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3 + + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U) */ + mask_write 0XFF5E00B8 0x01003F07 0x01000302 + # Register : PL0_REF_CTRL @ 0XFF5E00C0

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1 + + # 6 bit divider + # PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xc + + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x2 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010C02U) */ + mask_write 0XFF5E00C0 0x013F3F07 0x01010C02 + # Register : PL1_REF_CTRL @ 0XFF5E00C4

    + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_PL1_REF_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1 0x1 + + # 6 bit divider + # PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0 0xf + + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_PL1_REF_CTRL_SRCSEL 0x2 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E00C4, 0x013F3F07U ,0x01010F02U) */ + mask_write 0XFF5E00C4 0x013F3F07 0x01010F02 + # Register : AMS_REF_CTRL @ 0XFF5E0108

    + + # 6 bit divider + # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1 + + # 6 bit divider + # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1e + + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011E02U) */ + mask_write 0XFF5E0108 0x013F3F07 0x01011E02 + # Register : DLL_REF_CTRL @ 0XFF5E0104

    + + # 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles + # of the old clock and 4 cycles of the new clock. This is not usually an + # issue, but designers must be aware.) + # PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U) */ + mask_write 0XFF5E0104 0x00000007 0x00000000 + # Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128

    + + # 6 bit divider + # PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf + + # 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may + # only be toggled after 4 cycles of the old clock and 4 cycles of the new + # clock. This is not usually an issue, but designers must be aware.) + # PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U) */ + mask_write 0XFF5E0128 0x01003F07 0x01000F00 + # Register : SATA_REF_CTRL @ 0XFD1A00A0

    + + # 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog + # gled after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) + # PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U) */ + mask_write 0XFD1A00A0 0x01003F07 0x01000200 + # Register : PCIE_REF_CTRL @ 0XFD1A00B4

    + + # 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only + # be toggled after 4 cycles of the old clock and 4 cycles of the new cloc + # k. This is not usually an issue, but designers must be aware.) + # PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1 + + # 6 bit divider + # PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U) */ + mask_write 0XFD1A00B4 0x01003F07 0x01000200 + # Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070

    + + # 6 bit divider + # PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1 + + # 6 bit divider + # PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x5 + + # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + # his signal may only be toggled after 4 cycles of the old clock and 4 cyc + # les of the new clock. This is not usually an issue, but designers must b + # e aware.) + # PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x0 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010500U) */ + mask_write 0XFD1A0070 0x013F3F07 0x01010500 + # Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074

    + + # 6 bit divider + # PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1 + + # 6 bit divider + # PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0x14 + + # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + # his signal may only be toggled after 4 cycles of the old clock and 4 cyc + # les of the new clock. This is not usually an issue, but designers must b + # e aware.) + # PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x3 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01011403U) */ + mask_write 0XFD1A0074 0x013F3F07 0x01011403 + # Register : DP_STC_REF_CTRL @ 0XFD1A007C

    + + # 6 bit divider + # PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1 + + # 6 bit divider + # PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0x13 + + # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg + # led after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) + # PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01011303U) */ + mask_write 0XFD1A007C 0x013F3F07 0x01011303 + # Register : ACPU_CTRL @ 0XFD1A0060

    + + # 6 bit divider + # PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1 + + # 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft + # er 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0 + + # Clock active signal. Switch to 0 to disable the clock. For the half spee + # d APU Clock + # PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1 + + # Clock active signal. Switch to 0 to disable the clock. For the full spee + # d ACPUX Clock. This will shut off the high speed clock to the entire APU + # PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U) */ + mask_write 0XFD1A0060 0x03003F07 0x03000100 + # Register : DBG_FPD_CTRL @ 0XFD1A0068

    + + # 6 bit divider + # PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2 + + # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + # gled after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) + # PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U) */ + mask_write 0XFD1A0068 0x01003F07 0x01000200 + # Register : DDR_CTRL @ 0XFD1A0080

    + + # 6 bit divider + # PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2 + + # 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles + # of the old clock and 4 cycles of the new clock. This is not usually an i + # ssue, but designers must be aware.) + # PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U) */ + mask_write 0XFD1A0080 0x00003F07 0x00000200 + # Register : GPU_REF_CTRL @ 0XFD1A0084

    + + # 6 bit divider + # PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1 + + # 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog + # gled after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) + # PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0 + + # Clock active signal. Switch to 0 to disable the clock, which will stop c + # lock for GPU (and both Pixel Processors). + # PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1 + + # Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + # k only to this Pixel Processor + # PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1 + + # Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + # k only to this Pixel Processor + # PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U) */ + mask_write 0XFD1A0084 0x07003F07 0x07000100 + # Register : GDMA_REF_CTRL @ 0XFD1A00B8

    + + # 6 bit divider + # PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2 + + # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + # er 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U) */ + mask_write 0XFD1A00B8 0x01003F07 0x01000200 + # Register : DPDMA_REF_CTRL @ 0XFD1A00BC

    + + # 6 bit divider + # PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2 + + # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + # er 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U) */ + mask_write 0XFD1A00BC 0x01003F07 0x01000200 + # Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0

    + + # 6 bit divider + # PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2 + + # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + # er 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x3 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000203U) */ + mask_write 0XFD1A00C0 0x01003F07 0x01000203 + # Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4

    + + # 6 bit divider + # PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5 + + # 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog + # gled after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) + # PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U) */ + mask_write 0XFD1A00C4 0x01003F07 0x01000502 + # Register : DBG_TSTMP_CTRL @ 0XFD1A00F8

    + + # 6 bit divider + # PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2 + + # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + # gled after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) + # PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U) */ + mask_write 0XFD1A00F8 0x00003F07 0x00000200 + # Register : IOU_TTC_APB_CLK @ 0XFF180380

    + + # 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se + # lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5 + # clock for the APB interface of TTC0 + # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0 + + # 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se + # lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5 + # clock for the APB interface of TTC1 + # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0 + + # 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se + # lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5 + # clock for the APB interface of TTC2 + # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0 + + # 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se + # lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5 + # clock for the APB interface of TTC3 + # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0 + + # TTC APB clock select + #(OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U) */ + mask_write 0XFF180380 0x000000FF 0x00000000 + # Register : WDT_CLK_SEL @ 0XFD610100

    + + # System watchdog timer clock source selection: 0: Internal APB clock 1: E + # xternal (PL clock via EMIO or Pinout clock via MIO) + # PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0 + + # SWDT clock source select + #(OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U) */ + mask_write 0XFD610100 0x00000001 0x00000000 + # Register : WDT_CLK_SEL @ 0XFF180300

    + + # System watchdog timer clock source selection: 0: internal clock APB cloc + # k 1: external clock from PL via EMIO, or from pinout via MIO + # PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0 + + # SWDT clock source select + #(OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U) */ + mask_write 0XFF180300 0x00000001 0x00000000 + # Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050

    + + # System watchdog timer clock source selection: 0: internal clock APB cloc + # k 1: external clock pss_ref_clk + # PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0 + + # SWDT clock source select + #(OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U) */ + mask_write 0XFF410050 0x00000001 0x00000000 +} + +set psu_ddr_init_data { + # : DDR INITIALIZATION + # : DDR CONTROLLER RESET + # Register : RST_DDR_SS @ 0XFD1A0108

    + + # DDR block level reset inside of the DDR Sub System + # PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1 + + # DDR sub system block level reset + #(OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U) */ + mask_write 0XFD1A0108 0x00000008 0x00000008 + # Register : MSTR @ 0XFD070000

    + + # Indicates the configuration of the device used in the system. - 00 - x4 + # device - 01 - x8 device - 10 - x16 device - 11 - x32 device + # PSU_DDRC_MSTR_DEVICE_CONFIG 0x2 + + # Choose which registers are used. - 0 - Original registers - 1 - Shadow r + # egisters + # PSU_DDRC_MSTR_FREQUENCY_MODE 0x0 + + # Only present for multi-rank configurations. Each bit represents one rank + # . For two-rank configurations, only bits[25:24] are present. - 1 - popul + # ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow + # ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others - + # Reserved. For 4 ranks following combinations are legal: - 0001 - One ran + # k - 0011 - Two ranks - 1111 - Four ranks + # PSU_DDRC_MSTR_ACTIVE_RANKS 0x1 + + # SDRAM burst length used: - 0001 - Burst length of 2 (only supported for + # mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur + # st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other + # values are reserved. This controls the burst size used to access the SDR + # AM. This must match the burst length mode register setting in the SDRAM. + # (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) + # Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH + # is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 + # PSU_DDRC_MSTR_BURST_RDWR 0x4 + + # Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low + # frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for + # normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC + # TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi + # s bit must be set to '0'. + # PSU_DDRC_MSTR_DLL_OFF_MODE 0x0 + + # Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full + # DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter + # DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is + # only supported when the SDRAM bus width is a multiple of 16, and quarter + # bus width mode is only supported when the SDRAM bus width is a multiple + # of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid + # th refers to DQ bus width (excluding any ECC width). + # PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0 + + # 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D + # RAM in normal mode (1N). This register can be changed, only when the Con + # troller is in self-refresh mode. This signal must be set the same value + # as MR3 bit A3. Note: Geardown mode is not supported if the configuration + # parameter MEMC_CMD_RTN2IDLE is set + # PSU_DDRC_MSTR_GEARDOWN_MODE 0x0 + + # If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin + # g, all command signals (except chip select) are held for 2 clocks on the + # SDRAM bus. Chip select is asserted on the second cycle of the command N + # ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti + # ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i + # s set Note: 2T timing is not supported in DDR4 geardown mode. + # PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0 + + # When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci + # sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full + # bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer + # cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is + # disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl + # ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported + # , and this bit must be set to '0' + # PSU_DDRC_MSTR_BURSTCHOP 0x0 + + # Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d + # evice in use Present only in designs configured to support LPDDR4. + # PSU_DDRC_MSTR_LPDDR4 0x0 + + # Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device + # in use Present only in designs configured to support DDR4. + # PSU_DDRC_MSTR_DDR4 0x1 + + # Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d + # evice in use Present only in designs configured to support LPDDR3. + # PSU_DDRC_MSTR_LPDDR3 0x0 + + # Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d + # evice in use Present only in designs configured to support LPDDR2. + # PSU_DDRC_MSTR_LPDDR2 0x0 + + # Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de + # vice in use Only present in designs that support DDR3. + # PSU_DDRC_MSTR_DDR3 0x0 + + # Master Register + #(OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x81040010U) */ + mask_write 0XFD070000 0xE30FBE3D 0x81040010 + # Register : MRCTRL0 @ 0XFD070010

    + + # Setting this register bit to 1 triggers a mode register read or write op + # eration. When the MR operation is complete, the uMCTL2 automatically cle + # ars this bit. The other register fields of this register must be written + # in a separate APB transaction, before setting this mr_wr bit. It is rec + # ommended NOT to set this signal if in Init, Deep power-down or MPSM oper + # ating modes. + # PSU_DDRC_MRCTRL0_MR_WR 0x0 + + # Address of the mode register that is to be written to. - 0000 - MR0 - 00 + # 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR + # 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data + # for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als + # o used for writing to control words of RDIMMs. In that case, it correspo + # nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[ + # 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a + # s the bit[2:0] must be set to an appropriate value which is considered b + # oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R + # DIMMs. + # PSU_DDRC_MRCTRL0_MR_ADDR 0x0 + + # Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire + # d to access all ranks, so all bits should be set to 1. However, for mult + # i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess + # ary to access ranks individually. Examples (assume uMCTL2 is configured + # for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x + # 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran + # ks 0, 1, 2 and 3 + # PSU_DDRC_MRCTRL0_MR_RANK 0x3 + + # Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b + # efore automatic SDRAM initialization routine or not. For DDR4, this bit + # can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init + # ialization. For LPDDR4, this bit can be used to program additional mode + # registers before automatic SDRAM initialization if necessary. Note: This + # must be cleared to 0 after completing Software operation. Otherwise, SD + # RAM initialization routine will not re-start. - 0 - Software interventio + # n is not allowed - 1 - Software intervention is allowed + # PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0 + + # Indicates whether the mode register operation is MRS in PDA mode or not + # - 0 - MRS - 1 - MRS in Per DRAM Addressability mode + # PSU_DDRC_MRCTRL0_PDA_EN 0x0 + + # Indicates whether the mode register operation is MRS or WR/RD for MPR (o + # nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR + # PSU_DDRC_MRCTRL0_MPR_EN 0x0 + + # Indicates whether the mode register operation is read or write. Only use + # d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read + # PSU_DDRC_MRCTRL0_MR_TYPE 0x0 + + # Mode Register Read/Write Control Register 0. Note: Do not enable more th + # an one of the following fields simultaneously: - sw_init_int - pda_en - + # mpr_en + #(OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U) */ + mask_write 0XFD070010 0x8000F03F 0x00000030 + # Register : DERATEEN @ 0XFD070020

    + + # Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us + # es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d + # esigns configured to support LPDDR4. The required number of cycles for d + # erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p + # eriod, and rounding up the next integer. + # PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x2 + + # Derate byte Present only in designs configured to support LPDDR2/LPDDR3/ + # LPDDR4 Indicates which byte of the MRR data is used for derating. The ma + # ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. + # PSU_DDRC_DERATEEN_DERATE_BYTE 0x0 + + # Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl + # y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all + # LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ + # ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8 + # 75 ns is less than a core_ddrc_core_clk period or not. + # PSU_DDRC_DERATEEN_DERATE_VALUE 0x0 + + # Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin + # g parameter derating is enabled using MR4 read value. Present only in de + # signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set + # to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. + # PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0 + + # Temperature Derate Enable Register + #(OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000200U) */ + mask_write 0XFD070020 0x000003F3 0x00000200 + # Register : DERATEINT @ 0XFD070024

    + + # Interval between two MR4 reads, used to derate the timing parameters. Pr + # esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r + # egister must not be set to zero + # PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000 + + # Temperature Derate Interval Register + #(OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U) */ + mask_write 0XFD070024 0xFFFFFFFF 0x00800000 + # Register : PWRCTL @ 0XFD070030

    + + # Self refresh state is an intermediate state to enter to Self refresh pow + # er down state or exit Self refresh power down state for LPDDR4. This reg + # ister controls transition from the Self refresh state. - 1 - Prohibit tr + # ansition from Self refresh state - 0 - Allow transition from Self refres + # h state + # PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0 + + # A value of 1 to this register causes system to move to Self Refresh stat + # e immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + # This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa + # re Entry to Self Refresh - 0 - Software Exit from Self Refresh + # PSU_DDRC_PWRCTL_SELFREF_SW 0x0 + + # When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode + # when the transaction store is empty. This register must be reset to '0' + # to bring uMCTL2 out of maximum power saving mode. Present only in desig + # ns configured to support DDR4. For non-DDR4, this register should not be + # set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if + # the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r + # equires the chip-select signal to toggle. FOR PERFORMANCE ONLY. + # PSU_DDRC_PWRCTL_MPSM_EN 0x0 + + # Enable the assertion of dfi_dram_clk_disable whenever a clock is not req + # uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. + # Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only + # be asserted in Self Refresh. In DDR4, can be asserted in following: - i + # n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca + # n be asserted in following: - in Self Refresh - in Power Down - in Deep + # Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse + # rted in following: - in Self Refresh Power Down - in Power Down - during + # Normal operation (Clock Stop) + # PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0 + + # When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the + # transaction store is empty. This register must be reset to '0' to bring + # uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM + # initialization on deep power-down exit. Present only in designs configu + # red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD + # DR3, this register should not be set to 1. FOR PERFORMANCE ONLY. + # PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0 + + # If true then the uMCTL2 goes into power-down after a programmable number + # of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_ + # x32). This register bit may be re-programmed during the course of normal + # operation. + # PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0 + + # If true then the uMCTL2 puts the SDRAM into Self Refresh after a program + # mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG. + # selfref_to_x32)'. This register bit may be re-programmed during the cour + # se of normal operation. + # PSU_DDRC_PWRCTL_SELFREF_EN 0x0 + + # Low Power Control Register + #(OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U) */ + mask_write 0XFD070030 0x0000007F 0x00000000 + # Register : PWRTMG @ 0XFD070034

    + + # After this many clocks of NOP or deselect the uMCTL2 automatically puts + # the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_ + # en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + # PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40 + + # Minimum deep power-down time. For mDDR, value from the JEDEC specificati + # on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL + # .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE + # C specification is 500us. Unit: Multiples of 4096 clocks. Present only i + # n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + # ONLY. + # PSU_DDRC_PWRTMG_T_DPD_X4096 0x84 + + # After this many clocks of NOP or deselect the uMCTL2 automatically puts + # the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_ + # en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. + # PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10 + + # Low Power Timing Register + #(OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U) */ + mask_write 0XFD070034 0x00FFFF1F 0x00408410 + # Register : RFSHCTL0 @ 0XFD070050

    + + # Threshold value in number of clock cycles before the critical refresh or + # page timer expires. A critical refresh is to be issued before this thre + # shold is reached. It is recommended that this not be changed from the de + # fault value, currently shown as 0x2. It must always be less than interna + # lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u + # sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i + # s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n + # om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo + # cks. + # PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2 + + # If the refresh timer (tRFCnom, also known as tREFI) has expired at least + # once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then + # a speculative refresh may be performed. A speculative refresh is a refr + # esh performed at a time when refresh would be useful, but before it is a + # bsolutely required. When the SDRAM bus is idle for a period of time dete + # rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired + # at least once since the last refresh, then a speculative refresh is per + # formed. Speculative refreshes continues successively until there are no + # refreshes pending or until new reads or writes are issued to the uMCTL2. + # FOR PERFORMANCE ONLY. + # PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10 + + # The programmed value + 1 is the number of refresh timeouts that is allow + # ed to accumulate before traffic is blocked and the refreshes are forced + # to execute. Closing pages to perform a refresh is a one-time penalty tha + # t must be paid for each group of refreshes. Therefore, performing refres + # hes in a burst reduces the per-refresh penalty of these page closings. H + # igher numbers for RFSHCTL.refresh_burst slightly increases utilization; + # lower numbers decreases the worst-case latency associated with refreshes + # . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh + # For information on burst refresh feature refer to section 3.9 of DDR2 J + # EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe + # r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF + # I cycles using the burst refresh feature. In DDR4 mode, according to Fin + # e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre + # shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda + # tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens + # ure that tRFCmax is not violated due to a PHY-initiated update occurring + # shortly before a refresh burst was due. In this situation, the refresh + # burst will be delayed until the PHY-initiated update is complete. + # PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0 + + # - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + # traffic to flow to other banks. Per bank refresh is not supported by all + # LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr + # esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4 + # PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0 + + # Refresh Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U) */ + mask_write 0XFD070050 0x00F1F1F4 0x00210000 + # Register : RFSHCTL1 @ 0XFD070054

    + + # Refresh timer start for rank 1 (only present in multi-rank configuration + # s). This is useful in staggering the refreshes to multiple ranks to help + # traffic to proceed. This is explained in Refresh Controls section of ar + # chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + # PSU_DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32 0x0 + + # Refresh timer start for rank 0 (only present in multi-rank configuration + # s). This is useful in staggering the refreshes to multiple ranks to help + # traffic to proceed. This is explained in Refresh Controls section of ar + # chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + # PSU_DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32 0x0 + + # Refresh Control Register 1 + #(OFFSET, MASK, VALUE) (0XFD070054, 0x0FFF0FFFU ,0x00000000U) */ + mask_write 0XFD070054 0x0FFF0FFF 0x00000000 + # Register : RFSHCTL3 @ 0XFD070060

    + + # Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix + # ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11 + # 0 - Enable on the fly 4x (not supported) - Everything else - reserved No + # te: The on-the-fly modes is not supported in this version of the uMCTL2. + # Note: This must be set up while the Controller is in reset or while the + # Controller is in self-refresh mode. Changing this during normal operati + # on is not allowed. Making this a dynamic register will be supported in f + # uture version of the uMCTL2. + # PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0 + + # Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + # the refresh register(s) have been updated. The value is automatically up + # dated when exiting reset, so it does not need to be toggled initially. + # PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0 + + # When '1', disable auto-refresh generated by the uMCTL2. When auto-refres + # h is disabled, the SoC core must generate refreshes using the registers + # reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a + # nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1 + # , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 + # CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d + # isable auto-refresh is not supported, and this bit must be set to '0'. T + # his register field is changeable on the fly. + # PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1 + + # Refresh Control Register 3 + #(OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U) */ + mask_write 0XFD070060 0x00000073 0x00000001 + # Register : RFSHTMG @ 0XFD070064

    + + # tREFI: Average time interval between refreshes per rank (Specification: + # 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, + # LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre + # shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE + # FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + # register should be set to tREFIpb For configurations with MEMC_FREQ_RAT + # IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val + # ue is different depending on the refresh mode. The user should program t + # he appropriate value from the spec based on the value programmed in the + # refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea + # ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th + # an 0x1. Unit: Multiples of 32 clocks. + # PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x81 + + # Used only when LPDDR3 memory type is connected. Should only be changed w + # hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r + # equired by some LPDDR3 devices which comply with earlier versions of the + # LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 + # - tREFBW parameter used + # PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1 + + # tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F + # REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t + # CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro + # undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using + # all-bank refreshes, the tRFCmin value in the above equations is equal to + # tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq + # uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above + # equations is different depending on the refresh mode (fixed 1X,2X,4X) an + # d the device density. The user should program the appropriate value from + # the spec based on the 'refresh_mode' and the device density that is use + # d. Unit: Clocks. + # PSU_DDRC_RFSHTMG_T_RFC_MIN 0xbb + + # Refresh Timing Register + #(OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x008180BBU) */ + mask_write 0XFD070064 0x0FFF83FF 0x008180BB + # Register : ECCCFG0 @ 0XFD070070

    + + # Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U + # SE_RMW is defined + # PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1 + + # ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov + # er 1 beat - all other settings are reserved for future use + # PSU_DDRC_ECCCFG0_ECC_MODE 0x0 + + # ECC Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U) */ + mask_write 0XFD070070 0x00000017 0x00000010 + # Register : ECCCFG1 @ 0XFD070074

    + + # Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da + # ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat + # a_poison_en=1 + # PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0 + + # Enable ECC data poisoning - introduces ECC errors on writes to address s + # pecified by the ECCPOISONADDR0/1 registers + # PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0 + + # ECC Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U) */ + mask_write 0XFD070074 0x00000003 0x00000000 + # Register : CRCPARCTL1 @ 0XFD0700C4

    + + # The maximum number of DFI PHY clock cycles allowed from the assertion of + # the dfi_rddata_en signal to the assertion of each of the corresponding + # bits of the dfi_rddata_valid signal. This corresponds to the DFI timing + # parameter tphy_rdlat. Refer to PHY specification for correct value. This + # value it only used for detecting read data timeout when DDR4 retry is e + # nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: + # - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r + # dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 + # : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d + # fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ + # rdlat < 'd114 Unit: DFI Clocks + # PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10 + + # After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa + # re has an option to read the mode registers in the DRAM before the hardw + # are begins the retry process - 1: Wait for software to read/write the mo + # de registers before hardware begins the retry. After software is done wi + # th its operations, it will clear the alert interrupt register bit - 0: H + # ardware can begin the retry right away after the dfi_alert_n pulse goes + # away. The value on this register is valid only when retry is enabled (PA + # RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t + # he software doesn't clear the interrupt register after handling the pari + # ty/CRC error, then the hardware will not begin the retry process and the + # system will hang. In the case of Parity/CRC error, there are two possib + # ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten + # t parity' mode register bit is NOT set: the commands sent during retry a + # nd normal operation are executed without parity checking. The value in t + # he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent + # parity' mode register bit is SET: Parity checking is done for commands s + # ent during retry and normal operation. If multiple errors occur before M + # R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don' + # t care'. + # PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1 + + # - 1: Enable command retry mechanism in case of C/A Parity or CRC error - + # 0: Disable command retry mechanism when C/A Parity or CRC features are + # enabled. Note that retry functionality is not supported if burst chop is + # enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF + # SHCTL3.dis_auto_refresh = 1) + # PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0 + + # CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no + # t includes DM signal Present only in designs configured to support DDR4. + # PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0 + + # CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio + # n of CRC The setting of this register should match the CRC mode register + # setting in the DRAM. + # PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0 + + # C/A Parity enable register - 1: Enable generation of C/A parity and dete + # ction of C/A parity error - 0: Disable generation of C/A parity and disa + # ble detection of C/A parity error If RCD's parity error detection or SDR + # AM's parity detection is enabled, this register should be 1. + # PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0 + + # CRC Parity Control Register1 + #(OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U) */ + mask_write 0XFD0700C4 0x3F000391 0x10000200 + # Register : CRCPARCTL2 @ 0XFD0700C8

    + + # Value from the DRAM spec indicating the maximum width of the dfi_alert_n + # pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M + # AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT + # _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i + # llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. + # PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40 + + # Value from the DRAM spec indicating the maximum width of the dfi_alert_n + # pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX + # For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW + # .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille + # gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. + # PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5 + + # Indicates the maximum duration in number of DRAM clock cycles for which + # a command should be held in the Command Retry FIFO before it is popped o + # ut. Every location in the Command Retry FIFO has an associated down coun + # ting timer that will use this register as the start value. The down coun + # ting starts when a command is loaded into the FIFO. The timer counts dow + # n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe + # d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err + # or occurs before the counter reaches zero. The counter is reset to 0, af + # ter all the commands in the FIFO are retried. Recommended(minimum) value + # s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + # + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten + # cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable + # d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R + # DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + # + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be + # in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n + # ) should be considered. Note 3: Use the worst case(longer) value for PHY + # Latencies/Board delay Note 4: The Recommended values are minimum value + # to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max + # value can be set to this register is defined below: - MEMC_BURST_LENGTH + # == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 + # Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b + # us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod + # e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C + # RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC= + # ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 + # Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full + # bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod + # e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC + # =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF + # ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma + # x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal + # . + # PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f + + # CRC Parity Control Register2 + #(OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU) */ + mask_write 0XFD0700C8 0x01FF1F3F 0x0040051F + # Register : INIT0 @ 0XFD0700D0

    + + # If lower bit is enabled the SDRAM initialization routine is skipped. The + # upper bit decides what state the controller starts up in when reset is + # removed - 00 - SDRAM Intialization routine is run after power-up - 01 - + # SDRAM Intialization routine is skipped after power-up. Controller starts + # up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p + # ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ + # ation routine is run after power-up. Note: The only 2'b00 is supported f + # or LPDDR4 in this version of the uMCTL2. + # PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0 + + # Cycles to wait after driving CKE high to start the SDRAM initialization + # sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req + # uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD + # R3 typically requires this to be programmed for a delay of 200 us. LPDDR + # 4 typically requires this to be programmed for a delay of 2 us. For conf + # igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi + # ded by 2, and round it up to next integer value. + # PSU_DDRC_INIT0_POST_CKE_X1024 0x2 + + # Cycles to wait after reset before driving CKE high to start the SDRAM in + # itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi + # cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD + # DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati + # ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by + # 2, and round it up to next integer value. + # PSU_DDRC_INIT0_PRE_CKE_X1024 0x106 + + # SDRAM Initialization Register 0 + #(OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U) */ + mask_write 0XFD0700D0 0xC3FF0FFF 0x00020106 + # Register : INIT1 @ 0XFD0700D4

    + + # Number of cycles to assert SDRAM reset signal during init sequence. This + # is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo + # r use with a DDR PHY, this should be set to a minimum of 1 + # PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2 + + # Cycles to wait after completing the SDRAM initialization sequence before + # starting the dynamic scheduler. Unit: Counts of a global timer that pul + # ses every 32 clock cycles. There is no known specific requirement for th + # is; it may be set to zero. + # PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0 + + # Wait period before driving the OCD complete command to SDRAM. Unit: Coun + # ts of a global timer that pulses every 32 clock cycles. There is no know + # n specific requirement for this; it may be set to zero. + # PSU_DDRC_INIT1_PRE_OCD_X32 0x0 + + # SDRAM Initialization Register 1 + #(OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U) */ + mask_write 0XFD0700D4 0x01FF7F0F 0x00020000 + # Register : INIT2 @ 0XFD0700D8

    + + # Idle time after the reset command, tINIT4. Present only in designs confi + # gured to support LPDDR2. Unit: 32 clock cycles. + # PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23 + + # Time to wait after the first CKE high, tINIT2. Present only in designs c + # onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t + # ypically requires 5 x tCK delay. + # PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5 + + # SDRAM Initialization Register 2 + #(OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U) */ + mask_write 0XFD0700D8 0x0000FF0F 0x00002305 + # Register : INIT3 @ 0XFD0700DC

    + + # DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he + # re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value + # loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP + # DDR3/LPDDR4 - Value to write to MR1 register + # PSU_DDRC_INIT3_MR 0x730 + + # DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti + # ng in this register is ignored. The uMCTL2 sets those bits appropriately + # . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu + # ation mode training is enabled, this bit is set appropriately by the uMC + # TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/ + # LPDDR3/LPDDR4 - Value to write to MR2 register + # PSU_DDRC_INIT3_EMR 0x301 + + # SDRAM Initialization Register 3 + #(OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x07300301U) */ + mask_write 0XFD0700DC 0xFFFFFFFF 0x07300301 + # Register : INIT4 @ 0XFD0700E0

    + + # DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 + # register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus + # ed + # PSU_DDRC_INIT4_EMR2 0x20 + + # DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 + # register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis + # ter + # PSU_DDRC_INIT4_EMR3 0x200 + + # SDRAM Initialization Register 4 + #(OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U) */ + mask_write 0XFD0700E0 0xFFFFFFFF 0x00200200 + # Register : INIT5 @ 0XFD0700E4

    + + # ZQ initial calibration, tZQINIT. Present only in designs configured to s + # upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica + # lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir + # es 1 us. + # PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21 + + # Maximum duration of the auto initialization, tINIT5. Present only in des + # igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir + # es 10 us. + # PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4 + + # SDRAM Initialization Register 5 + #(OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U) */ + mask_write 0XFD0700E4 0x00FF03FF 0x00210004 + # Register : INIT6 @ 0XFD0700E8

    + + # DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs + # only. + # PSU_DDRC_INIT6_MR4 0x0 + + # DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs + # only. + # PSU_DDRC_INIT6_MR5 0x6c0 + + # SDRAM Initialization Register 6 + #(OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U) */ + mask_write 0XFD0700E8 0xFFFFFFFF 0x000006C0 + # Register : INIT7 @ 0XFD0700EC

    + + # DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs + # only. + # PSU_DDRC_INIT7_MR6 0x819 + + # SDRAM Initialization Register 7 + #(OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U) */ + mask_write 0XFD0700EC 0xFFFF0000 0x08190000 + # Register : DIMMCTL @ 0XFD0700F0

    + + # Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + # BG1 are NOT swapped even if Address Mirroring is enabled. This will be r + # equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp + # ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. + # PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0 + + # Enable for BG1 bit of MRS command. BG1 bit of the mode register address + # is specified as RFU (Reserved for Future Use) and must be programmed to + # 0 during MRS. In case where DRAMs which do not have BG1 are attached and + # both the CA parity and the Output Inversion are enabled, this must be s + # et to 0, so that the calculation of CA parity will not include BG1 bit. + # Note: This has no effect on the address of any other memory accesses, or + # of software-driven mode register accesses. If address mirroring is enab + # led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En + # abled - 0 - Disabled + # PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1 + + # Enable for A17 bit of MRS command. A17 bit of the mode register address + # is specified as RFU (Reserved for Future Use) and must be programmed to + # 0 during MRS. In case where DRAMs which do not have A17 are attached and + # the Output Inversion are enabled, this must be set to 0, so that the ca + # lculation of CA parity will not include A17 bit. Note: This has no effec + # t on the address of any other memory accesses, or of software-driven mod + # e register accesses. - 1 - Enabled - 0 - Disabled + # PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0 + + # Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM + # M implements the Output Inversion feature by default, which means that t + # he following address, bank address and bank group bits of B-side DRAMs a + # re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en + # sures that, for mode register accesses generated by the uMCTL2 during th + # e automatic initialization routine and enabling of a particular DDR4 fea + # ture, separate A-side and B-side mode register accesses are generated. F + # or B-side mode register accesses, these bits are inverted within the uMC + # TL2 to compensate for this RDIMM inversion. Note: This has no effect on + # the address of any other memory accesses, or of software-driven mode reg + # ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - + # Do not implement output inversion for B-side DRAMs. + # PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0 + + # Address Mirroring Enable (for multi-rank UDIMM implementations and multi + # -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement + # address mirroring for odd ranks, which means that the following address + # , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, + # A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t + # his bit ensures that, for mode register accesses during the automatic in + # itialization routine, these bits are swapped within the uMCTL2 to compen + # sate for this UDIMM/RDIMM swapping. In addition to the automatic initial + # ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th + # e automatic MRS access to enable/disable of a particular DDR4 feature. N + # ote: This has no effect on the address of any other memory accesses, or + # of software-driven mode register accesses. This is not supported for mDD + # R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 + # output of MRS for the odd ranks is same as BG0 because BG1 is invalid, + # hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran + # ks, implement address mirroring for MRS commands to during initializatio + # n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp + # lements address mirroring) - 0 - Do not implement address mirroring + # PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0 + + # Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM + # M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 + # or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of + # software driven MR commands (via MRCTRL0/MRCTRL1), where software is re + # sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se + # nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma + # nds to even and odd ranks seperately - 0 - Do not stagger accesses + # PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0 + + # DIMM Control Register + #(OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U) */ + mask_write 0XFD0700F0 0x0000003F 0x00000010 + # Register : RANKCTL @ 0XFD0700F4

    + + # Only present for multi-rank configurations. Indicates the number of cloc + # ks of gap in data responses when performing consecutive writes to differ + # ent ranks. This is used to switch the delays in the PHY to match the ran + # k requirements. This value should consider both PHY requirement and ODT + # requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v + # alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by + # 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas + # ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc + # reased by 1. - ODT requirement: The value programmed in this register ta + # kes care of the ODT switch off timing requirement when switching ranks d + # uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 + # For configurations with MEMC_FREQ_RATIO=1, program this to the larger o + # f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_ + # RATIO=2, program this to the larger value divided by two and round it up + # to the next integer. + # PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6 + + # Only present for multi-rank configurations. Indicates the number of cloc + # ks of gap in data responses when performing consecutive reads to differe + # nt ranks. This is used to switch the delays in the PHY to match the rank + # requirements. This value should consider both PHY requirement and ODT r + # equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va + # lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), + # should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only + # ), should be increased by 1. - ODT requirement: The value programmed in + # this register takes care of the ODT switch off timing requirement when s + # witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, + # program this to the larger of PHY requirement or ODT requirement. For co + # nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di + # vided by two and round it up to the next integer. + # PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6 + + # Only present for multi-rank configurations. Background: Reads to the sam + # e rank can be performed back-to-back. Reads to different ranks require a + # dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is + # to avoid possible data bus contention as well as to give PHY enough tim + # e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus + # access on a cycle-by-cycle basis; therefore after a read is scheduled, + # there are few clock cycles (determined by the value on RANKCTL.diff_rank + # _rd_gap register) in which only reads from the same rank are eligible to + # be scheduled. This prevents reads from other ranks from having fair acc + # ess to the data bus. This parameter represents the maximum number of rea + # ds that can be scheduled consecutively to the same rank. After this numb + # er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by + # the scheduler to allow all ranks a fair opportunity to be scheduled. Hig + # her numbers increase bandwidth utilization, lower numbers increase fairn + # ess. This feature can be DISABLED by setting this register to 0. When se + # t to 0, the Controller will stay on the same rank as long as commands ar + # e available for it. Minimum programmable value is 0 (feature disabled) a + # nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY. + # PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf + + # Rank Control Register + #(OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU) */ + mask_write 0XFD0700F4 0x00000FFF 0x0000066F + # Register : DRAMTMG0 @ 0XFD070100

    + + # Minimum time between write and precharge to same bank. Unit: Clocks Spec + # ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks + # @400MHz and less for lower frequencies where: - WL = write latency - BL + # = burst length. This must match the value programmed in the BL bit of t + # he mode register to the SDRAM. BST (burst terminate) is not supported at + # present. - tWR = Write recovery time. This comes directly from the SDRA + # M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p + # arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the + # above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT + # IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u + # p to the next integer value. + # PSU_DDRC_DRAMTMG0_WR2PRE 0x11 + + # tFAW Valid only when 8 or more banks(or banks x bank groups) are present + # . In 8-bank design, at most 4 banks must be activated in a rolling windo + # w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi + # s to (tFAW/2) and round up to next integer value. In a 4-bank design, se + # t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + # Unit: Clocks + # PSU_DDRC_DRAMTMG0_T_FAW 0x10 + + # tRAS(max): Maximum time between activate and precharge to same bank. Thi + # s is the maximum time that a page can be kept open Minimum value of this + # register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO + # =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of + # 1024 clocks. + # PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24 + + # tRAS(min): Minimum time between activate and precharge to the same bank. + # For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA + # S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T + # mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th + # e next integer value. Unit: Clocks + # PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12 + + # SDRAM Timing Register 0 + #(OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x11102412U) */ + mask_write 0XFD070100 0x7F3F7F3F 0x11102412 + # Register : DRAMTMG1 @ 0XFD070104

    + + # tXP: Minimum time after power-down exit to any operation. For DDR3, this + # should be programmed to tXPDLL if slow powerdown exit is selected in MR + # 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf + # igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it + # up to the next integer value. Units: Clocks + # PSU_DDRC_DRAMTMG1_T_XP 0x4 + + # tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL + # /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi + # ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 + # - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t + # RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) + # - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_ + # RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi + # gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo + # ve value by 2 and round it up to the next integer value. Unit: Clocks. + # PSU_DDRC_DRAMTMG1_RD2PRE 0x4 + + # tRC: Minimum time between activates to same bank. For configurations wit + # h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege + # r value. Unit: Clocks. + # PSU_DDRC_DRAMTMG1_T_RC 0x1a + + # SDRAM Timing Register 1 + #(OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x0004041AU) */ + mask_write 0XFD070104 0x001F1F7F 0x0004041A + # Register : DRAMTMG2 @ 0XFD070108

    + + # Set to WL Time from write command to write data on SDRAM interface. This + # must be set to WL. For mDDR, it should normally be set to 1. Note that, + # depending on the PHY, if using RDIMM, it may be necessary to use a valu + # e of WL + 1 to compensate for the extra cycle of latency through the RDI + # MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate + # d using the above equation by 2, and round it up to next integer. This r + # egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING + # is set), as the DFI read and write latencies defined in DFITMG0 and DFI + # TMG1 are sufficient for those protocols Unit: clocks + # PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7 + + # Set to RL Time from read command to read data on SDRAM interface. This m + # ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma + # t be necessary to use a value of RL + 1 to compensate for the extra cycl + # e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2 + # , divide the value calculated using the above equation by 2, and round i + # t up to next integer. This register field is not required for DDR2 and D + # DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie + # s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit + # : clocks + # PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8 + + # DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L + # PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di + # sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL + # LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL + # E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write + # command. Include time for bus turnaround and all per-bank, per-rank, an + # d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b + # urst length. This must match the value programmed in the BL bit of the m + # ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL + # E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = + # read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d + # erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should + # be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal + # culated using the above equation by 2, and round it up to next integer. + # PSU_DDRC_DRAMTMG2_RD2WR 0x6 + + # DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu + # m time from write command to read command for same bank group. In others + # , minimum time from write command to read command. Includes time for bus + # turnaround, recovery times, and all per-bank, per-rank, and global cons + # traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la + # tency - BL = burst length. This must match the value programmed in the B + # L bit of the mode register to the SDRAM - tWTR_L = internal write to rea + # d command delay for same bank group. This comes directly from the SDRAM + # specification. - tWTR = internal write to read command delay. This comes + # directly from the SDRAM specification. Add one extra cycle for LPDDR2/L + # PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid + # e the value calculated using the above equation by 2, and round it up to + # next integer. + # PSU_DDRC_DRAMTMG2_WR2RD 0xd + + # SDRAM Timing Register 2 + #(OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060DU) */ + mask_write 0XFD070108 0x3F3F3F3F 0x0708060D + # Register : DRAMTMG3 @ 0XFD07010C

    + + # Time to wait after a mode register write or read (MRW or MRR). Present o + # nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty + # pically requires value of 5. LPDDR3 typically requires value of 10. LPDD + # R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist + # er is used for the time from a MRW/MRR to all other commands. For LDPDR3 + # , this register is used for the time from a MRW/MRR to a MRW/MRR. + # PSU_DDRC_DRAMTMG3_T_MRW 0x5 + + # tMRD: Cycles to wait after a mode register write or read. Depending on t + # he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com + # mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim + # e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2, + # program this to (tMRD/2) and round it up to the next integer value. If + # C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. + # PSU_DDRC_DRAMTMG3_T_MRD 0x4 + + # tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com + # mand and following non-load mode command. If C/A parity for DDR4 is used + # , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or + # tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if + # using RDIMM, depending on the PHY, it may be necessary to use a value of + # tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a + # pplied to mode register writes by the RDIMM chip. + # PSU_DDRC_DRAMTMG3_T_MOD 0xc + + # SDRAM Timing Register 3 + #(OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU) */ + mask_write 0XFD07010C 0x3FF3F3FF 0x0050400C + # Register : DRAMTMG4 @ 0XFD070110

    + + # tRCD - tAL: Minimum time from activate to read or write command to same + # bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD + # - tAL)/2) and round it up to the next integer value. Minimum value allow + # ed for this register is 1, which implies minimum (tRCD - tAL) value to b + # e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. + # PSU_DDRC_DRAMTMG4_T_RCD 0x8 + + # DDR4: tCCD_L: This is the minimum time between two reads or two writes f + # or same bank group. Others: tCCD: This is the minimum time between two r + # eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t + # his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U + # nit: clocks. + # PSU_DDRC_DRAMTMG4_T_CCD 0x3 + + # DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f + # or same bank group. Others: tRRD: Minimum time between activates from ba + # nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi + # s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni + # t: Clocks. + # PSU_DDRC_DRAMTMG4_T_RRD 0x4 + + # tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ + # _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM + # C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t + # RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho + # uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. + # PSU_DDRC_DRAMTMG4_T_RP 0x9 + + # SDRAM Timing Register 4 + #(OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030409U) */ + mask_write 0XFD070110 0x1F0F0F1F 0x08030409 + # Register : DRAMTMG5 @ 0XFD070114

    + + # This is the time before Self Refresh Exit that CK is maintained as a val + # id clock before issuing SRX. Specifies the clock stable time before SRX. + # Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK + # EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_ + # FREQ_RATIO=2, program this to recommended value divided by two and round + # it up to next integer. + # PSU_DDRC_DRAMTMG5_T_CKSRX 0x6 + + # This is the time after Self Refresh Down Entry that CK is maintained as + # a valid clock. Specifies the clock disable delay after SRE. Recommended + # settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 + # - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations + # with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw + # o and round it up to next integer. + # PSU_DDRC_DRAMTMG5_T_CKSRE 0x6 + + # Minimum CKE low width for Self refresh or Self refresh power down entry + # to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF + # C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: + # tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ + # _RATIO=2, program this to recommended value divided by two and round it + # up to next integer. + # PSU_DDRC_DRAMTMG5_T_CKESR 0x4 + + # Minimum number of cycles of CKE HIGH/LOW during power-down and self refr + # esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP + # DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/ + # non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration + # s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and + # round it up to the next integer value. Unit: Clocks. + # PSU_DDRC_DRAMTMG5_T_CKE 0x3 + + # SDRAM Timing Register 5 + #(OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U) */ + mask_write 0XFD070114 0x0F0F3F1F 0x06060403 + # Register : DRAMTMG6 @ 0XFD070118

    + + # This is the time after Deep Power Down Entry that CK is maintained as a + # valid clock. Specifies the clock disable delay after DPDE. Recommended s + # ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_ + # FREQ_RATIO=2, program this to recommended value divided by two and round + # it up to next integer. This is only present for designs supporting mDDR + # or LPDDR2/LPDDR3 devices. + # PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1 + + # This is the time before Deep Power Down Exit that CK is maintained as a + # valid clock before issuing DPDX. Specifies the clock stable time before + # DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config + # urations with MEMC_FREQ_RATIO=2, program this to recommended value divid + # ed by two and round it up to next integer. This is only present for desi + # gns supporting mDDR or LPDDR2 devices. + # PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1 + + # This is the time before Clock Stop Exit that CK is maintained as a valid + # clock before issuing Clock Stop Exit. Specifies the clock stable time b + # efore next command after Clock Stop Exit. Recommended settings: - mDDR: + # 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio + # ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by + # two and round it up to next integer. This is only present for designs su + # pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + # PSU_DDRC_DRAMTMG6_T_CKCSX 0x4 + + # SDRAM Timing Register 6 + #(OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U) */ + mask_write 0XFD070118 0x0F0F000F 0x01010004 + # Register : DRAMTMG7 @ 0XFD07011C

    + + # This is the time after Power Down Entry that CK is maintained as a valid + # clock. Specifies the clock disable delay after PDE. Recommended setting + # s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration + # s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t + # wo and round it up to next integer. This is only present for designs sup + # porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + # PSU_DDRC_DRAMTMG7_T_CKPDE 0x6 + + # This is the time before Power Down Exit that CK is maintained as a valid + # clock before issuing PDX. Specifies the clock stable time before PDX. R + # ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c + # onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value + # divided by two and round it up to next integer. This is only present for + # designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + # PSU_DDRC_DRAMTMG7_T_CKPDX 0x6 + + # SDRAM Timing Register 7 + #(OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U) */ + mask_write 0XFD07011C 0x00000F0F 0x00000606 + # Register : DRAMTMG8 @ 0XFD070120

    + + # tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and + # Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this + # to the above value divided by 2 and round up to next integer value. Unit + # : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com + # mands. Note: Ensure this is less than or equal to t_xs_x32. + # PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x4 + + # tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S + # elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th + # is to the above value divided by 2 and round up to next integer value. U + # nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to + # t_xs_x32. + # PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x4 + + # tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config + # urations with MEMC_FREQ_RATIO=2, program this to the above value divided + # by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + # Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + # PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd + + # tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi + # gurations with MEMC_FREQ_RATIO=2, program this to the above value divide + # d by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + # Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + # PSU_DDRC_DRAMTMG8_T_XS_X32 0x7 + + # SDRAM Timing Register 8 + #(OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x04040D07U) */ + mask_write 0XFD070120 0x7F7F7F7F 0x04040D07 + # Register : DRAMTMG9 @ 0XFD070124

    + + # DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o + # nly with MEMC_FREQ_RATIO=2 + # PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0 + + # tCCD_S: This is the minimum time between two reads or two writes for dif + # ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m + # inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2 + # , program this to (tCCD_S/2) and round it up to the next integer value. + # Present only in designs configured to support DDR4. Unit: clocks. + # PSU_DDRC_DRAMTMG9_T_CCD_S 0x2 + + # tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif + # ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th + # is to (tRRD_S/2) and round it up to the next integer value. Present only + # in designs configured to support DDR4. Unit: Clocks. + # PSU_DDRC_DRAMTMG9_T_RRD_S 0x3 + + # CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command + # for different bank group. Includes time for bus turnaround, recovery ti + # mes, and all per-bank, per-rank, and global constraints. Present only in + # designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr + # ite latency - PL = Parity latency - BL = burst length. This must match t + # he value programmed in the BL bit of the mode register to the SDRAM - tW + # TR_S = internal write to read command delay for different bank group. Th + # is comes directly from the SDRAM specification. For configurations with + # MEMC_FREQ_RATIO=2, divide the value calculated using the above equation + # by 2, and round it up to next integer. + # PSU_DDRC_DRAMTMG9_WR2RD_S 0xb + + # SDRAM Timing Register 9 + #(OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002030BU) */ + mask_write 0XFD070124 0x40070F3F 0x0002030B + # Register : DRAMTMG11 @ 0XFD07012C

    + + # tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL + # L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2 + # ) and round it up to the next integer value. Present only in designs con + # figured to support DDR4. Unit: Multiples of 32 clocks. + # PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x12 + + # tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For + # configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2 + # )+1. Present only in designs configured to support DDR4. Unit: clocks. + # PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7 + + # tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_ + # FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int + # eger value. Present only in designs configured to support DDR4. Unit: Cl + # ocks. + # PSU_DDRC_DRAMTMG11_T_MPX_S 0x1 + + # tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i + # n designs configured to support DDR4. Unit: Clocks. For configurations w + # ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat + # ion by 2, and round it up to next integer. + # PSU_DDRC_DRAMTMG11_T_CKMPE 0xe + + # SDRAM Timing Register 11 + #(OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x1207010EU) */ + mask_write 0XFD07012C 0x7F1F031F 0x1207010E + # Register : DRAMTMG12 @ 0XFD070130

    + + # tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg + # er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr + # am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu + # e. + # PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2 + + # tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat + # ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u + # p to next integer value. + # PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6 + + # tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. + # For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2) + # and round it up to next integer value. + # PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8 + + # SDRAM Timing Register 12 + #(OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U) */ + mask_write 0XFD070130 0x00030F1F 0x00020608 + # Register : ZQCTL0 @ 0XFD070180

    + + # - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg + # ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration + # request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati + # on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre + # sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + # PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1 + + # - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres + # h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 + # or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio + # n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i + # n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present + # for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + # PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0 + + # - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC + # L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + # tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co + # mmands to different ranks do not overlap. - 0 - ZQ resistor is not share + # d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR + # 3/LPDDR4 devices. + # PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0 + + # - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. + # Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com + # mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4 + # mode. This is only present for designs supporting DDR4 devices. + # PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0 + + # tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe + # r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St + # art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO + # =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int + # eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th + # e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t + # o the next integer value. Unit: Clock cycles. This is only present for d + # esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + # PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100 + + # tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of + # NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command + # is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t + # his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy + # cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP + # DDR3/LPDDR4 devices. + # PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40 + + # ZQ Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U) */ + mask_write 0XFD070180 0xF7FF03FF 0x81000040 + # Register : ZQCTL1 @ 0XFD070184

    + + # tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati + # on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_ + # RATIO=2, program this to tZQReset/2 and round it up to the next integer + # value. Unit: Clock cycles. This is only present for designs supporting L + # PDDR2/LPDDR3/LPDDR4 devices. + # PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20 + + # Average interval to wait between automatically issuing ZQCS (ZQ calibrat + # ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR + # 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles + # . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 + # /LPDDR4 devices. + # PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x196e5 + + # ZQ Control Register 1 + #(OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x020196E5U) */ + mask_write 0XFD070184 0x3FFFFFFF 0x020196E5 + # Register : DFITMG0 @ 0XFD070190

    + + # Specifies the number of DFI clock cycles after an assertion or de-assert + # ion of the DFI control signals that the control signals at the PHY-DRAM + # interface reflect the assertion or de-assertion. If the DFI clock and th + # e memory clock are not phase-aligned, this timing parameter should be ro + # unded up to the next integer value. Note that if using RDIMM, it is nece + # ssary to increment this parameter by RDIMM's extra cycle of latency in t + # erms of DFI clock. + # PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4 + + # Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + # sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + # is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + # - 1 in terms of SDR clock cycles Refer to PHY specification for correct + # value. + # PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1 + + # Time from the assertion of a read command on the DFI interface to the as + # sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + # ect value. This corresponds to the DFI parameter trddata_en. Note that, + # depending on the PHY, if using RDIMM, it may be necessary to use the val + # ue (CL + 1) in the calculation of trddata_en. This is to compensate for + # the extra cycle of latency through the RDIMM. Unit: Clocks + # PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb + + # Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + # ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + # in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + # i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + # clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + # n for correct value. + # PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1 + + # Specifies the number of clock cycles between when dfi_wrdata_en is asser + # ted to when the associated write data is driven on the dfi_wrdata signal + # . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + # specification for correct value. Note, max supported value is 8. Unit: + # Clocks + # PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2 + + # Write latency Number of clocks from the write command to write data enab + # le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + # lat. Refer to PHY specification for correct value.Note that, depending o + # n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + # in the calculation of tphy_wrlat. This is to compensate for the extra c + # ycle of latency through the RDIMM. + # PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb + + # DFI Timing Register 0 + #(OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU) */ + mask_write 0XFD070190 0x1FBFBF3F 0x048B820B + # Register : DFITMG1 @ 0XFD070194

    + + # Specifies the number of DFI PHY clocks between when the dfi_cs signal is + # asserted and when the associated command is driven. This field is used + # for CAL mode, should be set to '0' or the value which matches the CAL mo + # de register setting in the DRAM. If the PHY can add the latency for CAL + # mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 + # PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0 + + # Specifies the number of DFI PHY clocks between when the dfi_cs signal is + # asserted and when the associated dfi_parity_in signal is driven. + # PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0 + + # Specifies the number of DFI clocks between when the dfi_wrdata_en signal + # is asserted and when the corresponding write data transfer is completed + # on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d + # elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set + # to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI + # 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va + # lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_ + # RATIO=2, divide PHY's value by 2 and round up to next integer. If using + # DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks + # PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3 + + # Specifies the number of DFI clock cycles from the assertion of the dfi_d + # ram_clk_disable signal on the DFI until the clock to the DRAM memory dev + # ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock + # and the memory clock are not phase aligned, this timing parameter should + # be rounded up to the next integer value. + # PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3 + + # Specifies the number of DFI clock cycles from the de-assertion of the df + # i_dram_clk_disable signal on the DFI until the first valid rising edge o + # f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the + # DFI clock and the memory clock are not phase aligned, this timing param + # eter should be rounded up to the next integer value. + # PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4 + + # DFI Timing Register 1 + #(OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U) */ + mask_write 0XFD070194 0xF31F0F0F 0x00030304 + # Register : DFILPCFG0 @ 0XFD070198

    + + # Setting for DFI's tlp_resp time. Same value is used for both Power Down, + # Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s + # pecification onwards, recommends using a fixed value of 7 always. + # PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7 + + # Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente + # red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 + # cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5 + # 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - + # 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553 + # 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T + # his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices + # . + # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0 + + # Enables DFI Low Power interface handshaking during Deep Power Down Entry + # /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup + # porting mDDR or LPDDR2/LPDDR3 devices. + # PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0 + + # Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered + # . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc + # les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 + # cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 + # - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c + # ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited + # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0 + + # Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex + # it. - 0 - Disabled - 1 - Enabled + # PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1 + + # Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + # Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle + # s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy + # cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - + # 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc + # les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited + # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0 + + # Enables DFI Low Power interface handshaking during Power Down Entry/Exit + # . - 0 - Disabled - 1 - Enabled + # PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1 + + # DFI Low Power Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U) */ + mask_write 0XFD070198 0x0FF1F1F1 0x07000101 + # Register : DFILPCFG1 @ 0XFD07019C

    + + # Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is + # entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 + # - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x + # 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl + # es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - + # 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi + # ted This is only present for designs supporting DDR4 devices. + # PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2 + + # Enables DFI Low Power interface handshaking during Maximum Power Saving + # Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d + # esigns supporting DDR4 devices. + # PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1 + + # DFI Low Power Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U) */ + mask_write 0XFD07019C 0x000000F1 0x00000021 + # Register : DFIUPD0 @ 0XFD0701A0

    + + # When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + # . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc + # _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. + # PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD 0x0 + + # When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + # following a self-refresh exit. The core must issue the dfi_ctrlupd_req + # signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct + # rlupd_req after exiting self-refresh. + # PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX 0x0 + + # Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si + # gnal can assert. Lowest value to assign to this variable is 0x40. Unit: + # Clocks + # PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MAX 0x40 + + # Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si + # gnal must be asserted. The uMCTL2 expects the PHY to respond within this + # time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup + # d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this + # variable is 0x3. Unit: Clocks + # PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MIN 0x3 + + # DFI Update Register 0 + #(OFFSET, MASK, VALUE) (0XFD0701A0, 0xC3FF03FFU ,0x00400003U) */ + mask_write 0XFD0701A0 0xC3FF03FF 0x00400003 + # Register : DFIUPD1 @ 0XFD0701A4

    + + # This is the minimum amount of time between uMCTL2 initiated DFI update r + # equests (which is executed whenever the uMCTL2 is idle). Set this number + # higher to reduce the frequency of update requests, which can have a sma + # ll impact on the latency of the first read request when the uMCTL2 is id + # le. Unit: 1024 clocks + # PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0xc8 + + # This is the maximum amount of time between uMCTL2 initiated DFI update r + # equests. This timer resets with each update request; when the timer expi + # res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd + # _ackx is received. PHY can use this idle time to recalibrate the delay l + # ines to the DLLs. The DFI controller update is also used to reset PHY FI + # FO pointers in case of data capture errors. Updates are required to main + # tain calibration over PVT, but frequent updates may impact performance. + # Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must + # be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl + # ocks + # PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xff + + # DFI Update Register 1 + #(OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x00C800FFU) */ + mask_write 0XFD0701A4 0x00FF00FF 0x00C800FF + # Register : DFIMISC @ 0XFD0701B0

    + + # Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal + # s are active low - 1: Signals are active high + # PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0 + + # DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. + # - 1 - PHY implements DBI functionality. Present only in designs configu + # red to support DDR4 and LPDDR4. + # PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0 + + # PHY initialization complete enable signal. When asserted the dfi_init_co + # mplete signal can be used to trigger SDRAM initialisation + # PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0 + + # DFI Miscellaneous Control Register + #(OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U) */ + mask_write 0XFD0701B0 0x00000007 0x00000000 + # Register : DFITMG2 @ 0XFD0701B4

    + + # >Number of clocks between when a read command is sent on the DFI control + # interface and when the associated dfi_rddata_cs signal is asserted. Thi + # s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe + # cification for correct value. + # PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9 + + # Number of clocks between when a write command is sent on the DFI control + # interface and when the associated dfi_wrdata_cs signal is asserted. Thi + # s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe + # cification for correct value. + # PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x9 + + # DFI Timing Register 2 + #(OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000909U) */ + mask_write 0XFD0701B4 0x00003F3F 0x00000909 + # Register : DBICTL @ 0XFD0701C0

    + + # Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D + # BI is enabled. This signal must be set the same value as DRAM's mode reg + # ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b + # e set to 0. - LPDDR4: MR3[6] + # PSU_DDRC_DBICTL_RD_DBI_EN 0x0 + + # Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ + # e DBI is enabled. This signal must be set the same value as DRAM's mode + # register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus + # t be set to 0. - LPDDR4: MR3[7] + # PSU_DDRC_DBICTL_WR_DBI_EN 0x0 + + # DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi + # s signal must be set the same logical value as DRAM's mode register. - D + # DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th + # is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13 + # [5] which is opposite polarity from this signal + # PSU_DDRC_DBICTL_DM_EN 0x1 + + # DM/DBI Control Register + #(OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U) */ + mask_write 0XFD0701C0 0x00000007 0x00000001 + # Register : ADDRMAP0 @ 0XFD070200

    + + # Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t + # o 27, and 31 Internal Base: 6 The selected HIF address bit is determined + # by adding the internal base to the value of this field. If set to 31, r + # ank address bit 0 is set to 0. + # PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f + + # Address Map Register 0 + #(OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU) */ + mask_write 0XFD070200 0x0000001F 0x0000001F + # Register : ADDRMAP1 @ 0XFD070204

    + + # Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t + # o 29 and 31 Internal Base: 4 The selected HIF address bit is determined + # by adding the internal base to the value of this field. If set to 31, ba + # nk address bit 2 is set to 0. + # PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f + + # Selects the HIF address bits used as bank address bit 1. Valid Range: 0 + # to 30 Internal Base: 3 The selected HIF address bit for each of the bank + # address bits is determined by adding the internal base to the value of + # this field. + # PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0x9 + + # Selects the HIF address bits used as bank address bit 0. Valid Range: 0 + # to 30 Internal Base: 2 The selected HIF address bit for each of the bank + # address bits is determined by adding the internal base to the value of + # this field. + # PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0x9 + + # Address Map Register 1 + #(OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0909U) */ + mask_write 0XFD070204 0x001F1F1F 0x001F0909 + # Register : ADDRMAP2 @ 0XFD070208

    + + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 5. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 6. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base + # : 5 The selected HIF address bit is determined by adding the internal ba + # se to the value of this field. If set to 15, this column address bit is + # set to 0. + # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x1 + + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 4. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 5. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: + # 4 The selected HIF address bit is determined by adding the internal bas + # e to the value of this field. If set to 15, this column address bit is s + # et to 0. + # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x1 + + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 3. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 4. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s + # elected HIF address bit is determined by adding the internal base to the + # value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1 + # 6, it is required to program this to 0, hence register does not exist in + # this case. + # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x1 + + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 2. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 3. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s + # elected HIF address bit is determined by adding the internal base to the + # value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 + # or 16, it is required to program this to 0. + # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0 + + # Address Map Register 2 + #(OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x01010100U) */ + mask_write 0XFD070208 0x0F0F0F0F 0x01010100 + # Register : ADDRMAP3 @ 0XFD07020C

    + + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 9. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: + # Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/ + # LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + # HIF address bit is determined by adding the internal base to the value o + # f this field. If set to 15, this column address bit is set to 0. Note: P + # er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo + # r indicating auto-precharge, and hence no source address bit can be mapp + # ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit + # for auto-precharge in the CA bus and hence column bit 10 is used. + # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x1 + + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 8. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 9. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 + # to 7, and 15 Internal Base: 8 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi + # cation, column address bit 10 is reserved for indicating auto-precharge, + # and hence no source address bit can be mapped to column address bit 10. + # In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA + # bus and hence column bit 10 is used. + # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x1 + + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 7. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 8. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: + # 7 The selected HIF address bit is determined by adding the internal bas + # e to the value of this field. If set to 15, this column address bit is s + # et to 0. + # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x1 + + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 6. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 7. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: + # 6 The selected HIF address bit is determined by adding the internal bas + # e to the value of this field. If set to 15, this column address bit is s + # et to 0. + # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x1 + + # Address Map Register 3 + #(OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x01010101U) */ + mask_write 0XFD07020C 0x0F0F0F0F 0x01010101 + # Register : ADDRMAP4 @ 0XFD070210

    + + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m + # ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un + # used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, + # and 15 Internal Base: 11 The selected HIF address bit is determined by + # adding the internal base to the value of this field. If set to 15, this + # column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio + # n, column address bit 10 is reserved for indicating auto-precharge, and + # hence no source address bit can be mapped to column address bit 10. In L + # PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus + # and hence column bit 10 is used. + # PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf + + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the + # HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) + # . - Quarter bus width mode: UNUSED. To make it unused, this must be tied + # to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + # address bit is determined by adding the internal base to the value of t + # his field. If set to 15, this column address bit is set to 0. Note: Per + # JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i + # ndicating auto-precharge, and hence no source address bit can be mapped + # to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + # auto-precharge in the CA bus and hence column bit 10 is used. + # PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf + + # Address Map Register 4 + #(OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU) */ + mask_write 0XFD070210 0x00000F0F 0x00000F0F + # Register : ADDRMAP5 @ 0XFD070214

    + + # Selects the HIF address bit used as row address bit 11. Valid Range: 0 t + # o 11, and 15 Internal Base: 17 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 11 is set to 0. + # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x7 + + # Selects the HIF address bits used as row address bits 2 to 10. Valid Ran + # ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row + # address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro + # w address bit 10) The selected HIF address bit for each of the row addre + # ss bits is determined by adding the internal base to the value of this f + # ield. When value 15 is used the values of row address bits 2 to 10 are d + # efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. + # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf + + # Selects the HIF address bits used as row address bit 1. Valid Range: 0 t + # o 11 Internal Base: 7 The selected HIF address bit for each of the row a + # ddress bits is determined by adding the internal base to the value of th + # is field. + # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x7 + + # Selects the HIF address bits used as row address bit 0. Valid Range: 0 t + # o 11 Internal Base: 6 The selected HIF address bit for each of the row a + # ddress bits is determined by adding the internal base to the value of th + # is field. + # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x7 + + # Address Map Register 5 + #(OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x070F0707U) */ + mask_write 0XFD070214 0x0F0F0F0F 0x070F0707 + # Register : ADDRMAP6 @ 0XFD070218

    + + # Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 + # - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]= + # =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. + # All addresses are valid Present only in designs configured to support L + # PDDR3. + # PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0 + + # Selects the HIF address bit used as row address bit 15. Valid Range: 0 t + # o 11, and 15 Internal Base: 21 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 15 is set to 0. + # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0x7 + + # Selects the HIF address bit used as row address bit 14. Valid Range: 0 t + # o 11, and 15 Internal Base: 20 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 14 is set to 0. + # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x7 + + # Selects the HIF address bit used as row address bit 13. Valid Range: 0 t + # o 11, and 15 Internal Base: 19 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 13 is set to 0. + # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x7 + + # Selects the HIF address bit used as row address bit 12. Valid Range: 0 t + # o 11, and 15 Internal Base: 18 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 12 is set to 0. + # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x7 + + # Address Map Register 6 + #(OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x07070707U) */ + mask_write 0XFD070218 0x8F0F0F0F 0x07070707 + # Register : ADDRMAP7 @ 0XFD07021C

    + + # Selects the HIF address bit used as row address bit 17. Valid Range: 0 t + # o 10, and 15 Internal Base: 23 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 17 is set to 0. + # PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf + + # Selects the HIF address bit used as row address bit 16. Valid Range: 0 t + # o 11, and 15 Internal Base: 22 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 16 is set to 0. + # PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf + + # Address Map Register 7 + #(OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU) */ + mask_write 0XFD07021C 0x00000F0F 0x00000F0F + # Register : ADDRMAP8 @ 0XFD070220

    + + # Selects the HIF address bits used as bank group address bit 1. Valid Ran + # ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea + # ch of the bank group address bits is determined by adding the internal b + # ase to the value of this field. If set to 31, bank group address bit 1 i + # s set to 0. + # PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x1f + + # Selects the HIF address bits used as bank group address bit 0. Valid Ran + # ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th + # e bank group address bits is determined by adding the internal base to t + # he value of this field. + # PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x1 + + # Address Map Register 8 + #(OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00001F01U) */ + mask_write 0XFD070220 0x00001F1F 0x00001F01 + # Register : ADDRMAP9 @ 0XFD070224

    + + # Selects the HIF address bits used as row address bit 5. Valid Range: 0 t + # o 11 Internal Base: 11 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. + # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x7 + + # Selects the HIF address bits used as row address bit 4. Valid Range: 0 t + # o 11 Internal Base: 10 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. + # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x7 + + # Selects the HIF address bits used as row address bit 3. Valid Range: 0 t + # o 11 Internal Base: 9 The selected HIF address bit for each of the row a + # ddress bits is determined by adding the internal base to the value of th + # is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + # 10 is set to value 15. + # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x7 + + # Selects the HIF address bits used as row address bit 2. Valid Range: 0 t + # o 11 Internal Base: 8 The selected HIF address bit for each of the row a + # ddress bits is determined by adding the internal base to the value of th + # is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + # 10 is set to value 15. + # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x7 + + # Address Map Register 9 + #(OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x07070707U) */ + mask_write 0XFD070224 0x0F0F0F0F 0x07070707 + # Register : ADDRMAP10 @ 0XFD070228

    + + # Selects the HIF address bits used as row address bit 9. Valid Range: 0 t + # o 11 Internal Base: 15 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. + # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x7 + + # Selects the HIF address bits used as row address bit 8. Valid Range: 0 t + # o 11 Internal Base: 14 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. + # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x7 + + # Selects the HIF address bits used as row address bit 7. Valid Range: 0 t + # o 11 Internal Base: 13 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. + # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x7 + + # Selects the HIF address bits used as row address bit 6. Valid Range: 0 t + # o 11 Internal Base: 12 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. + # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x7 + + # Address Map Register 10 + #(OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x07070707U) */ + mask_write 0XFD070228 0x0F0F0F0F 0x07070707 + # Register : ADDRMAP11 @ 0XFD07022C

    + + # Selects the HIF address bits used as row address bit 10. Valid Range: 0 + # to 11 Internal Base: 16 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of + # this field. This register field is used only when ADDRMAP5.addrmap_row_b + # 2_10 is set to value 15. + # PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x7 + + # Address Map Register 11 + #(OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000007U) */ + mask_write 0XFD07022C 0x0000000F 0x00000007 + # Register : ODTCFG @ 0XFD070240

    + + # Cycles to hold ODT for a write command. The minimum supported value is 2 + # . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800 + # ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D + # DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR + # EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 ( + # not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) + # PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6 + + # The delay, in clock cycles, from issuing a write command to setting ODT + # values associated with that command. ODT setting must remain constant fo + # r the entire time that DQS is driven by the uMCTL2. Recommended values: + # DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + + # AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo + # r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust + # for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) + # PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0 + + # Cycles to hold ODT for a read command. The minimum supported value is 2. + # Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - + # BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 + # : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p + # reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + + # RU(tODTon(max)/tCK) + # PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6 + + # The delay, in clock cycles, from issuing a read command to setting ODT v + # alues associated with that command. ODT setting must remain constant for + # the entire time that DQS is driven by the uMCTL2. Recommended values: D + # DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL + # - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C + # WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat + # (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK + # write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre + # amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su + # pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R + # U(tODTon(max)/tCK) + # PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0 + + # ODT Configuration Register + #(OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U) */ + mask_write 0XFD070240 0x0F1F0F7C 0x06000600 + # Register : ODTMAP @ 0XFD070244

    + + # Indicates which remote ODTs must be turned on during a read from rank 1. + # Each rank has a remote ODT (in the SDRAM) which can be turned on by set + # ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + # s controlled by bit next to the LSB, etc. For each rank, set its bit to + # 1 to enable its ODT. Present only in configurations that have 2 or more + # ranks + # PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0 + + # Indicates which remote ODTs must be turned on during a write to rank 1. + # Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + # ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + # controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + # to enable its ODT. Present only in configurations that have 2 or more r + # anks + # PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0 + + # Indicates which remote ODTs must be turned on during a read from rank 0. + # Each rank has a remote ODT (in the SDRAM) which can be turned on by set + # ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + # s controlled by bit next to the LSB, etc. For each rank, set its bit to + # 1 to enable its ODT. + # PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0 + + # Indicates which remote ODTs must be turned on during a write to rank 0. + # Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + # ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + # controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + # to enable its ODT. + # PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1 + + # ODT/Rank Map Register + #(OFFSET, MASK, VALUE) (0XFD070244, 0x00003333U ,0x00000001U) */ + mask_write 0XFD070244 0x00003333 0x00000001 + # Register : SCHED @ 0XFD070250

    + + # When the preferred transaction store is empty for these many clock cycle + # s, switch to the alternate transaction store if it is non-empty. The rea + # d transaction store (both high and low priority) is the default preferre + # d transaction store and the write transaction store is the alternative s + # tore. When prefer write over read is set this is reversed. 0x0 is a lega + # l value for this register. When set to 0x0, the transaction store switch + # ing will happen immediately when the switching conditions become true. F + # OR PERFORMANCE ONLY + # PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1 + + # UNUSED + # PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0 + + # Number of entries in the low priority transaction store is this value + + # 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent + # ries available for the high priority transaction store. Setting this to + # maximum value allocates all entries to low priority transaction store. S + # etting this to 0 allocates 1 entry to low priority transaction store and + # the rest to high priority transaction store. Note: In ECC configuration + # s, the numbers of write and low priority read credits issued is one less + # than in the non-ECC case. One entry each is reserved in the write and l + # ow-priority read CAMs for storing the RMW requests arising out of single + # bit error correction RMW operation. + # PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20 + + # If true, bank is kept open only while there are page hit transactions av + # ailable in the CAM to that bank. The last read or write command in the C + # AM with a bank and page hit will be executed with auto-precharge if SCHE + # D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos + # e_timer is set to 0, explicit precharge (and not auto-precharge) may be + # issued in some cases where there is a mode switch between Write and Read + # or between LPR and HPR. The Read and Write commands that are executed a + # s part of the ECC scrub requests are also executed without auto-precharg + # e. If false, the bank remains open until there is a need to close it (to + # open a different page, or for page timeout or refresh timeout) - also k + # nown as open page policy. The open page policy can be overridden by sett + # ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + # The pageclose feature provids a midway between Open and Close page polic + # ies. FOR PERFORMANCE ONLY. + # PSU_DDRC_SCHED_PAGECLOSE 0x0 + + # If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. + # PSU_DDRC_SCHED_PREFER_WRITE 0x0 + + # Active low signal. When asserted ('0'), all incoming transactions are fo + # rced to low priority. This implies that all High Priority Read (HPR) and + # Variable Priority Read commands (VPR) will be treated as Low Priority R + # ead (LPR) commands. On the write side, all Variable Priority Write (VPW) + # commands will be treated as Normal Priority Write (NPW) commands. Forci + # ng the incoming transactions to low priority implicitly turns off Bypass + # path for read commands. FOR PERFORMANCE ONLY. + # PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1 + + # Scheduler Control Register + #(OFFSET, MASK, VALUE) (0XFD070250, 0x7FFF3F07U ,0x01002001U) */ + mask_write 0XFD070250 0x7FFF3F07 0x01002001 + # Register : PERFLPR1 @ 0XFD070264

    + + # Number of transactions that are serviced once the LPR queue goes critica + # l is the smaller of: - (a) This number - (b) Number of transactions avai + # lable. Unit: Transaction. FOR PERFORMANCE ONLY. + # PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8 + + # Number of clocks that the LPR queue can be starved before it goes critic + # al. The minimum valid functional value for this register is 0x1. Program + # ming it to 0x0 will disable the starvation functionality; during normal + # operation, this function should not be disabled as it will cause excessi + # ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + # PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40 + + # Low Priority Read CAM Register 1 + #(OFFSET, MASK, VALUE) (0XFD070264, 0xFF00FFFFU ,0x08000040U) */ + mask_write 0XFD070264 0xFF00FFFF 0x08000040 + # Register : PERFWR1 @ 0XFD07026C

    + + # Number of transactions that are serviced once the WR queue goes critical + # is the smaller of: - (a) This number - (b) Number of transactions avail + # able. Unit: Transaction. FOR PERFORMANCE ONLY. + # PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8 + + # Number of clocks that the WR queue can be starved before it goes critica + # l. The minimum valid functional value for this register is 0x1. Programm + # ing it to 0x0 will disable the starvation functionality; during normal o + # peration, this function should not be disabled as it will cause excessiv + # e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + # PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40 + + # Write CAM Register 1 + #(OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U) */ + mask_write 0XFD07026C 0xFF00FFFF 0x08000040 + # Register : DQMAP0 @ 0XFD070280

    + + # DQ nibble map for DQ bits [12-15] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15 0x0 + + # DQ nibble map for DQ bits [8-11] Present only in designs configured to s + # upport DDR4. + # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11 0x0 + + # DQ nibble map for DQ bits [4-7] Present only in designs configured to su + # pport DDR4. + # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7 0x0 + + # DQ nibble map for DQ bits [0-3] Present only in designs configured to su + # pport DDR4. + # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3 0x0 + + # DQ Map Register 0 + #(OFFSET, MASK, VALUE) (0XFD070280, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD070280 0xFFFFFFFF 0x00000000 + # Register : DQMAP1 @ 0XFD070284

    + + # DQ nibble map for DQ bits [28-31] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31 0x0 + + # DQ nibble map for DQ bits [24-27] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27 0x0 + + # DQ nibble map for DQ bits [20-23] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23 0x0 + + # DQ nibble map for DQ bits [16-19] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19 0x0 + + # DQ Map Register 1 + #(OFFSET, MASK, VALUE) (0XFD070284, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD070284 0xFFFFFFFF 0x00000000 + # Register : DQMAP2 @ 0XFD070288

    + + # DQ nibble map for DQ bits [44-47] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47 0x0 + + # DQ nibble map for DQ bits [40-43] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43 0x0 + + # DQ nibble map for DQ bits [36-39] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39 0x0 + + # DQ nibble map for DQ bits [32-35] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35 0x0 + + # DQ Map Register 2 + #(OFFSET, MASK, VALUE) (0XFD070288, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD070288 0xFFFFFFFF 0x00000000 + # Register : DQMAP3 @ 0XFD07028C

    + + # DQ nibble map for DQ bits [60-63] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63 0x0 + + # DQ nibble map for DQ bits [56-59] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59 0x0 + + # DQ nibble map for DQ bits [52-55] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55 0x0 + + # DQ nibble map for DQ bits [48-51] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51 0x0 + + # DQ Map Register 3 + #(OFFSET, MASK, VALUE) (0XFD07028C, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD07028C 0xFFFFFFFF 0x00000000 + # Register : DQMAP4 @ 0XFD070290

    + + # DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf + # igured to support DDR4. + # PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7 0x0 + + # DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf + # igured to support DDR4. + # PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3 0x0 + + # DQ Map Register 4 + #(OFFSET, MASK, VALUE) (0XFD070290, 0x0000FFFFU ,0x00000000U) */ + mask_write 0XFD070290 0x0000FFFF 0x00000000 + # Register : DQMAP5 @ 0XFD070294

    + + # All even ranks have the same DQ mapping controled by DQMAP0-4 register a + # s rank 0. This register provides DQ swap function for all odd ranks to s + # upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b + # it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba + # sed DQ swapping 0: Enable rank based DQ swapping Present only in designs + # configured to support DDR4. + # PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1 + + # DQ Map Register 5 + #(OFFSET, MASK, VALUE) (0XFD070294, 0x00000001U ,0x00000001U) */ + mask_write 0XFD070294 0x00000001 0x00000001 + # Register : DBG0 @ 0XFD070300

    + + # When this is set to '0', auto-precharge is disabled for the flushed comm + # and in a collision case. Collision cases are write followed by read to s + # ame address, read followed by write to same address, or write followed b + # y write to same address with DBG0.dis_wc bit = 1 (where same address com + # parisons exclude the two address bits representing critical word). FOR D + # EBUG ONLY. + # PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0 + + # When 1, disable write combine. FOR DEBUG ONLY + # PSU_DDRC_DBG0_DIS_WC 0x0 + + # Debug Register 0 + #(OFFSET, MASK, VALUE) (0XFD070300, 0x00000011U ,0x00000000U) */ + mask_write 0XFD070300 0x00000011 0x00000000 + # Register : DBGCMD @ 0XFD07030C

    + + # Setting this register bit to 1 allows refresh and ZQCS commands to be tr + # iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD. + # zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore + # d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and + # ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor + # t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no + # function, and are ignored by the uMCTL2 logic. This register is static, + # and may only be changed when the DDRC reset signal, core_ddrc_rstn, is + # asserted (0). + # PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0 + + # Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct + # rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit + # is automatically cleared. This operation must only be performed when DF + # IUPD0.dis_auto_ctrlupd=1. + # PSU_DDRC_DBGCMD_CTRLUPD 0x0 + + # Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS ( + # ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi + # s request is stored in the uMCTL2, the bit is automatically cleared. Thi + # s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom + # mended NOT to set this register bit if in Init operating mode. This regi + # ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown + # (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo + # de. + # PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0 + + # Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + # h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be + # set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s + # tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + # auto_refresh=1. It is recommended NOT to set this register bit if in Ini + # t or Deep power-down operating modes or Maximum Power Saving Mode. + # PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0 + + # Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + # h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be + # set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s + # tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + # auto_refresh=1. It is recommended NOT to set this register bit if in Ini + # t or Deep power-down operating modes or Maximum Power Saving Mode. + # PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0 + + # Command Debug Register + #(OFFSET, MASK, VALUE) (0XFD07030C, 0x80000033U ,0x00000000U) */ + mask_write 0XFD07030C 0x80000033 0x00000000 + # Register : SWCTL @ 0XFD070320

    + + # Enable quasi-dynamic register programming outside reset. Program registe + # r to 0 to enable quasi-dynamic programming. Set back register to 1 once + # programming is done. + # PSU_DDRC_SWCTL_SW_DONE 0x0 + + # Software register programming control enable + #(OFFSET, MASK, VALUE) (0XFD070320, 0x00000001U ,0x00000000U) */ + mask_write 0XFD070320 0x00000001 0x00000000 + # Register : PCCFG @ 0XFD070400

    + + # Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand + # s every AXI burst into multiple HIF commands, using the memory burst len + # gth as a unit. If set to 1, then XPI will use half of the memory burst l + # ength as a unit. This applies to both reads and writes. When MSTR.data_b + # us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i + # n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d + # is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd + # _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali + # ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT + # L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an + # d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST + # R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs + # t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR + # CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared + # -AC is enabled + # PSU_DDRC_PCCFG_BL_EXP_MODE 0x0 + + # Page match four limit. If set to 1, limits the number of consecutive sam + # e page DDRC transactions that can be granted by the Port Arbiter to four + # when Page Match feature is enabled. If set to 0, there is no limit impo + # sed on number of consecutive same page DDRC transactions. + # PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0 + + # If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l + # pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw + # urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_ + # go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a + # t DDRC are driven to 1b'0. + # PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1 + + # Port Common Configuration Register + #(OFFSET, MASK, VALUE) (0XFD070400, 0x00000111U ,0x00000001U) */ + mask_write 0XFD070400 0x00000111 0x00000001 + # Register : PCFGR_0 @ 0XFD070404

    + + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0 + + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). + # PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1 + + # If set to 1, enables aging function for the read channel of the port. + # PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0 + + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. + # PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf + + # Port n Configuration Read Register + #(OFFSET, MASK, VALUE) (0XFD070404, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070404 0x000073FF 0x0000200F + # Register : PCFGW_0 @ 0XFD070408

    + + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x0 + + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). + # PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1 + + # If set to 1, enables aging function for the write channel of the port. + # PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0 + + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. + # PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf + + # Port n Configuration Write Register + #(OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070408 0x000073FF 0x0000200F + # Register : PCTRL_0 @ 0XFD070490

    + + # Enables port n. + # PSU_DDRC_PCTRL_0_PORT_EN 0x1 + + # Port n Control Register + #(OFFSET, MASK, VALUE) (0XFD070490, 0x00000001U ,0x00000001U) */ + mask_write 0XFD070490 0x00000001 0x00000001 + # Register : PCFGQOS0_0 @ 0XFD070494

    + + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. + # PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2 + + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. + # PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0 + + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. + # PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb + + # Port n Read QoS Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD070494, 0x0033000FU ,0x0020000BU) */ + mask_write 0XFD070494 0x0033000F 0x0020000B + # Register : PCFGQOS1_0 @ 0XFD070498

    + + # Specifies the timeout value for transactions mapped to the red address q + # ueue. + # PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0 + + # Specifies the timeout value for transactions mapped to the blue address + # queue. + # PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0 + + # Port n Read QoS Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD070498, 0x07FF07FFU ,0x00000000U) */ + mask_write 0XFD070498 0x07FF07FF 0x00000000 + # Register : PCFGR_1 @ 0XFD0704B4

    + + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0 + + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). + # PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1 + + # If set to 1, enables aging function for the read channel of the port. + # PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0 + + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. + # PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf + + # Port n Configuration Read Register + #(OFFSET, MASK, VALUE) (0XFD0704B4, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD0704B4 0x000073FF 0x0000200F + # Register : PCFGW_1 @ 0XFD0704B8

    + + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x0 + + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). + # PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1 + + # If set to 1, enables aging function for the write channel of the port. + # PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0 + + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. + # PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf + + # Port n Configuration Write Register + #(OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD0704B8 0x000073FF 0x0000200F + # Register : PCTRL_1 @ 0XFD070540

    + + # Enables port n. + # PSU_DDRC_PCTRL_1_PORT_EN 0x1 + + # Port n Control Register + #(OFFSET, MASK, VALUE) (0XFD070540, 0x00000001U ,0x00000001U) */ + mask_write 0XFD070540 0x00000001 0x00000001 + # Register : PCFGQOS0_1 @ 0XFD070544

    + + # This bitfield indicates the traffic class of region2. For dual address q + # ueue configurations, region2 maps to the red address queue. Valid values + # are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + # = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + # ased to LPR traffic. + # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2 + + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. + # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0 + + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. + # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0 + + # Separation level2 indicating the end of region1 mapping; start of region + # 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + # ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + # that for PA, arqos values are used directly as port priorities, where t + # he higher the value corresponds to higher port priority. All of the map_ + # level* registers must be set to distinct values. + # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb + + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. + # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3 + + # Port n Read QoS Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD070544, 0x03330F0FU ,0x02000B03U) */ + mask_write 0XFD070544 0x03330F0F 0x02000B03 + # Register : PCFGQOS1_1 @ 0XFD070548

    + + # Specifies the timeout value for transactions mapped to the red address q + # ueue. + # PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0 + + # Specifies the timeout value for transactions mapped to the blue address + # queue. + # PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0 + + # Port n Read QoS Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD070548, 0x07FF07FFU ,0x00000000U) */ + mask_write 0XFD070548 0x07FF07FF 0x00000000 + # Register : PCFGR_2 @ 0XFD070564

    + + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0 + + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). + # PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1 + + # If set to 1, enables aging function for the read channel of the port. + # PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0 + + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. + # PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf + + # Port n Configuration Read Register + #(OFFSET, MASK, VALUE) (0XFD070564, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070564 0x000073FF 0x0000200F + # Register : PCFGW_2 @ 0XFD070568

    + + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x0 + + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). + # PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1 + + # If set to 1, enables aging function for the write channel of the port. + # PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0 + + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. + # PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf + + # Port n Configuration Write Register + #(OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070568 0x000073FF 0x0000200F + # Register : PCTRL_2 @ 0XFD0705F0

    + + # Enables port n. + # PSU_DDRC_PCTRL_2_PORT_EN 0x1 + + # Port n Control Register + #(OFFSET, MASK, VALUE) (0XFD0705F0, 0x00000001U ,0x00000001U) */ + mask_write 0XFD0705F0 0x00000001 0x00000001 + # Register : PCFGQOS0_2 @ 0XFD0705F4

    + + # This bitfield indicates the traffic class of region2. For dual address q + # ueue configurations, region2 maps to the red address queue. Valid values + # are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + # = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + # ased to LPR traffic. + # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2 + + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. + # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0 + + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. + # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0 + + # Separation level2 indicating the end of region1 mapping; start of region + # 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + # ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + # that for PA, arqos values are used directly as port priorities, where t + # he higher the value corresponds to higher port priority. All of the map_ + # level* registers must be set to distinct values. + # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb + + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. + # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3 + + # Port n Read QoS Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD0705F4, 0x03330F0FU ,0x02000B03U) */ + mask_write 0XFD0705F4 0x03330F0F 0x02000B03 + # Register : PCFGQOS1_2 @ 0XFD0705F8

    + + # Specifies the timeout value for transactions mapped to the red address q + # ueue. + # PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0 + + # Specifies the timeout value for transactions mapped to the blue address + # queue. + # PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0 + + # Port n Read QoS Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD0705F8, 0x07FF07FFU ,0x00000000U) */ + mask_write 0XFD0705F8 0x07FF07FF 0x00000000 + # Register : PCFGR_3 @ 0XFD070614

    + + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0 + + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). + # PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1 + + # If set to 1, enables aging function for the read channel of the port. + # PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0 + + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. + # PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf + + # Port n Configuration Read Register + #(OFFSET, MASK, VALUE) (0XFD070614, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070614 0x000073FF 0x0000200F + # Register : PCFGW_3 @ 0XFD070618

    + + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x0 + + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). + # PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1 + + # If set to 1, enables aging function for the write channel of the port. + # PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0 + + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. + # PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf + + # Port n Configuration Write Register + #(OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070618 0x000073FF 0x0000200F + # Register : PCTRL_3 @ 0XFD0706A0

    + + # Enables port n. + # PSU_DDRC_PCTRL_3_PORT_EN 0x1 + + # Port n Control Register + #(OFFSET, MASK, VALUE) (0XFD0706A0, 0x00000001U ,0x00000001U) */ + mask_write 0XFD0706A0 0x00000001 0x00000001 + # Register : PCFGQOS0_3 @ 0XFD0706A4

    + + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. + # PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1 + + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. + # PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0 + + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. + # PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3 + + # Port n Read QoS Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD0706A4, 0x0033000FU ,0x00100003U) */ + mask_write 0XFD0706A4 0x0033000F 0x00100003 + # Register : PCFGQOS1_3 @ 0XFD0706A8

    + + # Specifies the timeout value for transactions mapped to the red address q + # ueue. + # PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0 + + # Specifies the timeout value for transactions mapped to the blue address + # queue. + # PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f + + # Port n Read QoS Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD0706A8, 0x07FF07FFU ,0x0000004FU) */ + mask_write 0XFD0706A8 0x07FF07FF 0x0000004F + # Register : PCFGWQOS0_3 @ 0XFD0706AC

    + + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + # traffic. + # PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1 + + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + # traffic. + # PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0 + + # Separation level indicating the end of region0 mapping; start of region0 + # is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + # . Note that for PA, awqos values are used directly as port priorities, w + # here the higher the value corresponds to higher port priority. + # PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3 + + # Port n Write QoS Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD0706AC, 0x0033000FU ,0x00100003U) */ + mask_write 0XFD0706AC 0x0033000F 0x00100003 + # Register : PCFGWQOS1_3 @ 0XFD0706B0

    + + # Specifies the timeout value for write transactions. + # PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT 0x4f + + # Port n Write QoS Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD0706B0, 0x000007FFU ,0x0000004FU) */ + mask_write 0XFD0706B0 0x000007FF 0x0000004F + # Register : PCFGR_4 @ 0XFD0706C4

    + + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x0 + + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). + # PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1 + + # If set to 1, enables aging function for the read channel of the port. + # PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0 + + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. + # PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf + + # Port n Configuration Read Register + #(OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD0706C4 0x000073FF 0x0000200F + # Register : PCFGW_4 @ 0XFD0706C8

    + + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x0 + + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). + # PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1 + + # If set to 1, enables aging function for the write channel of the port. + # PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0 + + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. + # PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf + + # Port n Configuration Write Register + #(OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD0706C8 0x000073FF 0x0000200F + # Register : PCTRL_4 @ 0XFD070750

    + + # Enables port n. + # PSU_DDRC_PCTRL_4_PORT_EN 0x1 + + # Port n Control Register + #(OFFSET, MASK, VALUE) (0XFD070750, 0x00000001U ,0x00000001U) */ + mask_write 0XFD070750 0x00000001 0x00000001 + # Register : PCFGQOS0_4 @ 0XFD070754

    + + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. + # PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1 + + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. + # PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0 + + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. + # PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3 + + # Port n Read QoS Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD070754, 0x0033000FU ,0x00100003U) */ + mask_write 0XFD070754 0x0033000F 0x00100003 + # Register : PCFGQOS1_4 @ 0XFD070758

    + + # Specifies the timeout value for transactions mapped to the red address q + # ueue. + # PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0 + + # Specifies the timeout value for transactions mapped to the blue address + # queue. + # PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f + + # Port n Read QoS Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD070758, 0x07FF07FFU ,0x0000004FU) */ + mask_write 0XFD070758 0x07FF07FF 0x0000004F + # Register : PCFGWQOS0_4 @ 0XFD07075C

    + + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + # traffic. + # PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1 + + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + # traffic. + # PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0 + + # Separation level indicating the end of region0 mapping; start of region0 + # is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + # . Note that for PA, awqos values are used directly as port priorities, w + # here the higher the value corresponds to higher port priority. + # PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3 + + # Port n Write QoS Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD07075C, 0x0033000FU ,0x00100003U) */ + mask_write 0XFD07075C 0x0033000F 0x00100003 + # Register : PCFGWQOS1_4 @ 0XFD070760

    + + # Specifies the timeout value for write transactions. + # PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT 0x4f + + # Port n Write QoS Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD070760, 0x000007FFU ,0x0000004FU) */ + mask_write 0XFD070760 0x000007FF 0x0000004F + # Register : PCFGR_5 @ 0XFD070774

    + + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0 + + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). + # PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1 + + # If set to 1, enables aging function for the read channel of the port. + # PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0 + + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. + # PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf + + # Port n Configuration Read Register + #(OFFSET, MASK, VALUE) (0XFD070774, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070774 0x000073FF 0x0000200F + # Register : PCFGW_5 @ 0XFD070778

    + + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x0 + + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). + # PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1 + + # If set to 1, enables aging function for the write channel of the port. + # PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0 + + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. + # PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf + + # Port n Configuration Write Register + #(OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070778 0x000073FF 0x0000200F + # Register : PCTRL_5 @ 0XFD070800

    + + # Enables port n. + # PSU_DDRC_PCTRL_5_PORT_EN 0x1 + + # Port n Control Register + #(OFFSET, MASK, VALUE) (0XFD070800, 0x00000001U ,0x00000001U) */ + mask_write 0XFD070800 0x00000001 0x00000001 + # Register : PCFGQOS0_5 @ 0XFD070804

    + + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. + # PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1 + + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. + # PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0 + + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. + # PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3 + + # Port n Read QoS Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD070804, 0x0033000FU ,0x00100003U) */ + mask_write 0XFD070804 0x0033000F 0x00100003 + # Register : PCFGQOS1_5 @ 0XFD070808

    + + # Specifies the timeout value for transactions mapped to the red address q + # ueue. + # PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0 + + # Specifies the timeout value for transactions mapped to the blue address + # queue. + # PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f + + # Port n Read QoS Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD070808, 0x07FF07FFU ,0x0000004FU) */ + mask_write 0XFD070808 0x07FF07FF 0x0000004F + # Register : PCFGWQOS0_5 @ 0XFD07080C

    + + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + # traffic. + # PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1 + + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + # traffic. + # PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0 + + # Separation level indicating the end of region0 mapping; start of region0 + # is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + # . Note that for PA, awqos values are used directly as port priorities, w + # here the higher the value corresponds to higher port priority. + # PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3 + + # Port n Write QoS Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD07080C, 0x0033000FU ,0x00100003U) */ + mask_write 0XFD07080C 0x0033000F 0x00100003 + # Register : PCFGWQOS1_5 @ 0XFD070810

    + + # Specifies the timeout value for write transactions. + # PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT 0x4f + + # Port n Write QoS Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD070810, 0x000007FFU ,0x0000004FU) */ + mask_write 0XFD070810 0x000007FF 0x0000004F + # Register : SARBASE0 @ 0XFD070F04

    + + # Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + # ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + # ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + # PSU_DDRC_SARBASE0_BASE_ADDR 0x0 + + # SAR Base Address Register n + #(OFFSET, MASK, VALUE) (0XFD070F04, 0x000001FFU ,0x00000000U) */ + mask_write 0XFD070F04 0x000001FF 0x00000000 + # Register : SARSIZE0 @ 0XFD070F08

    + + # Number of blocks for address region n. This register determines the tota + # l size of the region in multiples of minimum block size as specified by + # the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + # as number of blocks = nblocks + 1. For example, if register is programme + # d to 0, region will have 1 block. + # PSU_DDRC_SARSIZE0_NBLOCKS 0x0 + + # SAR Size Register n + #(OFFSET, MASK, VALUE) (0XFD070F08, 0x000000FFU ,0x00000000U) */ + mask_write 0XFD070F08 0x000000FF 0x00000000 + # Register : SARBASE1 @ 0XFD070F0C

    + + # Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + # ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + # ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + # PSU_DDRC_SARBASE1_BASE_ADDR 0x10 + + # SAR Base Address Register n + #(OFFSET, MASK, VALUE) (0XFD070F0C, 0x000001FFU ,0x00000010U) */ + mask_write 0XFD070F0C 0x000001FF 0x00000010 + # Register : SARSIZE1 @ 0XFD070F10

    + + # Number of blocks for address region n. This register determines the tota + # l size of the region in multiples of minimum block size as specified by + # the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + # as number of blocks = nblocks + 1. For example, if register is programme + # d to 0, region will have 1 block. + # PSU_DDRC_SARSIZE1_NBLOCKS 0xf + + # SAR Size Register n + #(OFFSET, MASK, VALUE) (0XFD070F10, 0x000000FFU ,0x0000000FU) */ + mask_write 0XFD070F10 0x000000FF 0x0000000F + # Register : DFITMG0_SHADOW @ 0XFD072190

    + + # Specifies the number of DFI clock cycles after an assertion or de-assert + # ion of the DFI control signals that the control signals at the PHY-DRAM + # interface reflect the assertion or de-assertion. If the DFI clock and th + # e memory clock are not phase-aligned, this timing parameter should be ro + # unded up to the next integer value. Note that if using RDIMM, it is nece + # ssary to increment this parameter by RDIMM's extra cycle of latency in t + # erms of DFI clock. + # PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7 + + # Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + # sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + # is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + # - 1 in terms of SDR clock cycles Refer to PHY specification for correct + # value. + # PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1 + + # Time from the assertion of a read command on the DFI interface to the as + # sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + # ect value. This corresponds to the DFI parameter trddata_en. Note that, + # depending on the PHY, if using RDIMM, it may be necessary to use the val + # ue (CL + 1) in the calculation of trddata_en. This is to compensate for + # the extra cycle of latency through the RDIMM. Unit: Clocks + # PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2 + + # Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + # ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + # in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + # i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + # clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + # n for correct value. + # PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1 + + # Specifies the number of clock cycles between when dfi_wrdata_en is asser + # ted to when the associated write data is driven on the dfi_wrdata signal + # . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + # specification for correct value. Note, max supported value is 8. Unit: + # Clocks + # PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0 + + # Write latency Number of clocks from the write command to write data enab + # le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + # lat. Refer to PHY specification for correct value.Note that, depending o + # n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + # in the calculation of tphy_wrlat. This is to compensate for the extra c + # ycle of latency through the RDIMM. + # PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2 + + # DFI Timing Shadow Register 0 + #(OFFSET, MASK, VALUE) (0XFD072190, 0x1FBFBF3FU ,0x07828002U) */ + mask_write 0XFD072190 0x1FBFBF3F 0x07828002 + # : DDR CONTROLLER RESET + # Register : RST_DDR_SS @ 0XFD1A0108

    + + # DDR block level reset inside of the DDR Sub System + # PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0 + + # APM block level reset inside of the DDR Sub System + # PSU_CRF_APB_RST_DDR_SS_APM_RESET 0X0 + + # DDR sub system block level reset + #(OFFSET, MASK, VALUE) (0XFD1A0108, 0x0000000CU ,0x00000000U) */ + mask_write 0XFD1A0108 0x0000000C 0x00000000 + # : DDR PHY + # Register : PGCR0 @ 0XFD080010

    + + # Address Copy + # PSU_DDR_PHY_PGCR0_ADCP 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_PGCR0_RESERVED_30_27 0x0 + + # PHY FIFO Reset + # PSU_DDR_PHY_PGCR0_PHYFRST 0x1 + + # Oscillator Mode Address/Command Delay Line Select + # PSU_DDR_PHY_PGCR0_OSCACDL 0x3 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_PGCR0_RESERVED_23_19 0x0 + + # Digital Test Output Select + # PSU_DDR_PHY_PGCR0_DTOSEL 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_PGCR0_RESERVED_13 0x0 + + # Oscillator Mode Division + # PSU_DDR_PHY_PGCR0_OSCDIV 0xf + + # Oscillator Enable + # PSU_DDR_PHY_PGCR0_OSCEN 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_PGCR0_RESERVED_7_0 0x0 + + # PHY General Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD080010, 0xFFFFFFFFU ,0x07001E00U) */ + mask_write 0XFD080010 0xFFFFFFFF 0x07001E00 + # Register : PGCR2 @ 0XFD080018

    + + # Clear Training Status Registers + # PSU_DDR_PHY_PGCR2_CLRTSTAT 0x0 + + # Clear Impedance Calibration + # PSU_DDR_PHY_PGCR2_CLRZCAL 0x0 + + # Clear Parity Error + # PSU_DDR_PHY_PGCR2_CLRPERR 0x0 + + # Initialization Complete Pin Configuration + # PSU_DDR_PHY_PGCR2_ICPC 0x0 + + # Data Training PUB Mode Exit Timer + # PSU_DDR_PHY_PGCR2_DTPMXTMR 0xf + + # Initialization Bypass + # PSU_DDR_PHY_PGCR2_INITFSMBYP 0x0 + + # PLL FSM Bypass + # PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0 + + # Refresh Period + # PSU_DDR_PHY_PGCR2_TREFPRD 0x10010 + + # PHY General Configuration Register 2 + #(OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10010U) */ + mask_write 0XFD080018 0xFFFFFFFF 0x00F10010 + # Register : PGCR3 @ 0XFD08001C

    + + # CKN Enable + # PSU_DDR_PHY_PGCR3_CKNEN 0x55 + + # CK Enable + # PSU_DDR_PHY_PGCR3_CKEN 0xaa + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_PGCR3_RESERVED_15 0x0 + + # Enable Clock Gating for AC [0] ctl_rd_clk + # PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2 + + # Enable Clock Gating for AC [0] ddr_clk + # PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2 + + # Enable Clock Gating for AC [0] ctl_clk + # PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_PGCR3_RESERVED_8 0x0 + + # Controls DDL Bypass Modes + # PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2 + + # IO Loop-Back Select + # PSU_DDR_PHY_PGCR3_IOLB 0x0 + + # AC Receive FIFO Read Mode + # PSU_DDR_PHY_PGCR3_RDMODE 0x0 + + # Read FIFO Reset Disable + # PSU_DDR_PHY_PGCR3_DISRST 0x0 + + # Clock Level when Clock Gating + # PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0 + + # PHY General Configuration Register 3 + #(OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U) */ + mask_write 0XFD08001C 0xFFFFFFFF 0x55AA5480 + # Register : PGCR5 @ 0XFD080024

    + + # Frequency B Ratio Term + # PSU_DDR_PHY_PGCR5_FRQBT 0x1 + + # Frequency A Ratio Term + # PSU_DDR_PHY_PGCR5_FRQAT 0x1 + + # DFI Disconnect Time Period + # PSU_DDR_PHY_PGCR5_DISCNPERIOD 0x0 + + # Receiver bias core side control + # PSU_DDR_PHY_PGCR5_VREF_RBCTRL 0xf + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_PGCR5_RESERVED_3 0x0 + + # Internal VREF generator REFSEL ragne select + # PSU_DDR_PHY_PGCR5_DXREFISELRANGE 0x1 + + # DDL Page Read Write select + # PSU_DDR_PHY_PGCR5_DDLPGACT 0x0 + + # DDL Page Read Write select + # PSU_DDR_PHY_PGCR5_DDLPGRW 0x0 + + # PHY General Configuration Register 5 + #(OFFSET, MASK, VALUE) (0XFD080024, 0xFFFFFFFFU ,0x010100F4U) */ + mask_write 0XFD080024 0xFFFFFFFF 0x010100F4 + # Register : PTR0 @ 0XFD080040

    + + # PLL Power-Down Time + # PSU_DDR_PHY_PTR0_TPLLPD 0x216 + + # PLL Gear Shift Time + # PSU_DDR_PHY_PTR0_TPLLGS 0x856 + + # PHY Reset Time + # PSU_DDR_PHY_PTR0_TPHYRST 0x10 + + # PHY Timing Register 0 + #(OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x42C21590U) */ + mask_write 0XFD080040 0xFFFFFFFF 0x42C21590 + # Register : PTR1 @ 0XFD080044

    + + # PLL Lock Time + # PSU_DDR_PHY_PTR1_TPLLLOCK 0xd055 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0 + + # PLL Reset Time + # PSU_DDR_PHY_PTR1_TPLLRST 0x12c0 + + # PHY Timing Register 1 + #(OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0xD05512C0U) */ + mask_write 0XFD080044 0xFFFFFFFF 0xD05512C0 + # Register : PLLCR0 @ 0XFD080068

    + + # PLL Bypass + # PSU_DDR_PHY_PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable + # PSU_DDR_PHY_PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_PLLCR0_DTC 0x0 + + # PLL Control Register 0 (Type B PLL Only) + #(OFFSET, MASK, VALUE) (0XFD080068, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD080068 0xFFFFFFFF 0x01100000 + # Register : DSGCR @ 0XFD080090

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0 + + # When RDBI enabled, this bit is used to select RDBI CL calculation, if it + # is 1b1, calculation will use RDBICL, otherwise use default calculation. + # PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0 + + # When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v + # alue. + # PSU_DDR_PHY_DSGCR_RDBICL 0x2 + + # PHY Impedance Update Enable + # PSU_DDR_PHY_DSGCR_PHYZUEN 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DSGCR_RESERVED_22 0x0 + + # SDRAM Reset Output Enable + # PSU_DDR_PHY_DSGCR_RSTOE 0x1 + + # Single Data Rate Mode + # PSU_DDR_PHY_DSGCR_SDRMODE 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DSGCR_RESERVED_18 0x0 + + # ATO Analog Test Enable + # PSU_DDR_PHY_DSGCR_ATOAE 0x0 + + # DTO Output Enable + # PSU_DDR_PHY_DSGCR_DTOOE 0x0 + + # DTO I/O Mode + # PSU_DDR_PHY_DSGCR_DTOIOM 0x0 + + # DTO Power Down Receiver + # PSU_DDR_PHY_DSGCR_DTOPDR 0x1 + + # Reserved. Return zeroes on reads + # PSU_DDR_PHY_DSGCR_RESERVED_13 0x0 + + # DTO On-Die Termination + # PSU_DDR_PHY_DSGCR_DTOODT 0x0 + + # PHY Update Acknowledge Delay + # PSU_DDR_PHY_DSGCR_PUAD 0x5 + + # Controller Update Acknowledge Enable + # PSU_DDR_PHY_DSGCR_CUAEN 0x1 + + # Reserved. Return zeroes on reads + # PSU_DDR_PHY_DSGCR_RESERVED_4_3 0x0 + + # Controller Impedance Update Enable + # PSU_DDR_PHY_DSGCR_CTLZUEN 0x0 + + # Reserved. Return zeroes on reads + # PSU_DDR_PHY_DSGCR_RESERVED_1 0x0 + + # PHY Update Request Enable + # PSU_DDR_PHY_DSGCR_PUREN 0x1 + + # DDR System General Configuration Register + #(OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04161U) */ + mask_write 0XFD080090 0xFFFFFFFF 0x02A04161 + # Register : GPR0 @ 0XFD0800C0

    + + # General Purpose Register 0 + # PSU_DDR_PHY_GPR0_GPR0 0x0 + + # General Purpose Register 0 + #(OFFSET, MASK, VALUE) (0XFD0800C0, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD0800C0 0xFFFFFFFF 0x00000000 + # Register : GPR1 @ 0XFD0800C4

    + + # General Purpose Register 1 + # PSU_DDR_PHY_GPR1_GPR1 0xe3 + + # General Purpose Register 1 + #(OFFSET, MASK, VALUE) (0XFD0800C4, 0xFFFFFFFFU ,0x000000E3U) */ + mask_write 0XFD0800C4 0xFFFFFFFF 0x000000E3 + # Register : DCR @ 0XFD080100

    + + # DDR4 Gear Down Timing. + # PSU_DDR_PHY_DCR_GEARDN 0x0 + + # Un-used Bank Group + # PSU_DDR_PHY_DCR_UBG 0x0 + + # Un-buffered DIMM Address Mirroring + # PSU_DDR_PHY_DCR_UDIMM 0x0 + + # DDR 2T Timing + # PSU_DDR_PHY_DCR_DDR2T 0x0 + + # No Simultaneous Rank Access + # PSU_DDR_PHY_DCR_NOSRA 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DCR_RESERVED_26_18 0x0 + + # Byte Mask + # PSU_DDR_PHY_DCR_BYTEMASK 0x1 + + # DDR Type + # PSU_DDR_PHY_DCR_DDRTYPE 0x0 + + # Multi-Purpose Register (MPR) DQ (DDR3 Only) + # PSU_DDR_PHY_DCR_MPRDQ 0x0 + + # Primary DQ (DDR3 Only) + # PSU_DDR_PHY_DCR_PDQ 0x0 + + # DDR 8-Bank + # PSU_DDR_PHY_DCR_DDR8BNK 0x1 + + # DDR Mode + # PSU_DDR_PHY_DCR_DDRMD 0x4 + + # DRAM Configuration Register + #(OFFSET, MASK, VALUE) (0XFD080100, 0xFFFFFFFFU ,0x0800040CU) */ + mask_write 0XFD080100 0xFFFFFFFF 0x0800040C + # Register : DTPR0 @ 0XFD080110

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR0_RESERVED_31_29 0x0 + + # Activate to activate command delay (different banks) + # PSU_DDR_PHY_DTPR0_TRRD 0x7 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR0_RESERVED_23 0x0 + + # Activate to precharge command delay + # PSU_DDR_PHY_DTPR0_TRAS 0x24 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR0_RESERVED_15 0x0 + + # Precharge command period + # PSU_DDR_PHY_DTPR0_TRP 0xf + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0 + + # Internal read to precharge command delay + # PSU_DDR_PHY_DTPR0_TRTP 0x8 + + # DRAM Timing Parameters Register 0 + #(OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x07240F08U) */ + mask_write 0XFD080110 0xFFFFFFFF 0x07240F08 + # Register : DTPR1 @ 0XFD080114

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR1_RESERVED_31 0x0 + + # Minimum delay from when write leveling mode is programmed to the first D + # QS/DQS# rising edge. + # PSU_DDR_PHY_DTPR1_TWLMRD 0x28 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR1_RESERVED_23 0x0 + + # 4-bank activate period + # PSU_DDR_PHY_DTPR1_TFAW 0x20 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0 + + # Load mode update delay (DDR4 and DDR3 only) + # PSU_DDR_PHY_DTPR1_TMOD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0 + + # Load mode cycle time + # PSU_DDR_PHY_DTPR1_TMRD 0x8 + + # DRAM Timing Parameters Register 1 + #(OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28200008U) */ + mask_write 0XFD080114 0xFFFFFFFF 0x28200008 + # Register : DTPR2 @ 0XFD080118

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR2_RESERVED_31_29 0x0 + + # Read to Write command delay. Valid values are + # PSU_DDR_PHY_DTPR2_TRTW 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR2_RESERVED_27_25 0x0 + + # Read to ODT delay (DDR3 only) + # PSU_DDR_PHY_DTPR2_TRTODT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0 + + # CKE minimum pulse width + # PSU_DDR_PHY_DTPR2_TCKE 0xf + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0 + + # Self refresh exit delay + # PSU_DDR_PHY_DTPR2_TXS 0x300 + + # DRAM Timing Parameters Register 2 + #(OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x000F0300U) */ + mask_write 0XFD080118 0xFFFFFFFF 0x000F0300 + # Register : DTPR3 @ 0XFD08011C

    + + # ODT turn-off delay extension + # PSU_DDR_PHY_DTPR3_TOFDX 0x4 + + # Read to read and write to write command delay + # PSU_DDR_PHY_DTPR3_TCCD 0x0 + + # DLL locking time + # PSU_DDR_PHY_DTPR3_TDLLK 0x300 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR3_RESERVED_15_12 0x0 + + # Maximum DQS output access time from CK/CK# (LPDDR2/3 only) + # PSU_DDR_PHY_DTPR3_TDQSCKMAX 0x8 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0 + + # DQS output access time from CK/CK# (LPDDR2/3 only) + # PSU_DDR_PHY_DTPR3_TDQSCK 0x0 + + # DRAM Timing Parameters Register 3 + #(OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U) */ + mask_write 0XFD08011C 0xFFFFFFFF 0x83000800 + # Register : DTPR4 @ 0XFD080120

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR4_RESERVED_31_30 0x0 + + # ODT turn-on/turn-off delays (DDR2 only) + # PSU_DDR_PHY_DTPR4_TAOND_TAOFD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR4_RESERVED_27_26 0x0 + + # Refresh-to-Refresh + # PSU_DDR_PHY_DTPR4_TRFC 0x176 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR4_RESERVED_15_14 0x0 + + # Write leveling output delay + # PSU_DDR_PHY_DTPR4_TWLO 0x2b + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0 + + # Power down exit delay + # PSU_DDR_PHY_DTPR4_TXP 0x7 + + # DRAM Timing Parameters Register 4 + #(OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01762B07U) */ + mask_write 0XFD080120 0xFFFFFFFF 0x01762B07 + # Register : DTPR5 @ 0XFD080124

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0 + + # Activate to activate command delay (same bank) + # PSU_DDR_PHY_DTPR5_TRC 0x33 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR5_RESERVED_15 0x0 + + # Activate to read or write delay + # PSU_DDR_PHY_DTPR5_TRCD 0xf + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0 + + # Internal write to read command delay + # PSU_DDR_PHY_DTPR5_TWTR 0x8 + + # DRAM Timing Parameters Register 5 + #(OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00330F08U) */ + mask_write 0XFD080124 0xFFFFFFFF 0x00330F08 + # Register : DTPR6 @ 0XFD080128

    + + # PUB Write Latency Enable + # PSU_DDR_PHY_DTPR6_PUBWLEN 0x0 + + # PUB Read Latency Enable + # PSU_DDR_PHY_DTPR6_PUBRLEN 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR6_RESERVED_29_14 0x0 + + # Write Latency + # PSU_DDR_PHY_DTPR6_PUBWL 0xe + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTPR6_RESERVED_7_6 0x0 + + # Read Latency + # PSU_DDR_PHY_DTPR6_PUBRL 0xf + + # DRAM Timing Parameters Register 6 + #(OFFSET, MASK, VALUE) (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU) */ + mask_write 0XFD080128 0xFFFFFFFF 0x00000E0F + # Register : RDIMMGCR0 @ 0XFD080140

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_RDIMMGCR0_RESERVED_31 0x0 + + # RDMIMM Quad CS Enable + # PSU_DDR_PHY_RDIMMGCR0_QCSEN 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28 0x0 + + # RDIMM Outputs I/O Mode + # PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24 0x0 + + # ERROUT# Output Enable + # PSU_DDR_PHY_RDIMMGCR0_ERROUTOE 0x0 + + # ERROUT# I/O Mode + # PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM 0x1 + + # ERROUT# Power Down Receiver + # PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_RDIMMGCR0_RESERVED_20 0x0 + + # ERROUT# On-Die Termination + # PSU_DDR_PHY_RDIMMGCR0_ERROUTODT 0x0 + + # Load Reduced DIMM + # PSU_DDR_PHY_RDIMMGCR0_LRDIMM 0x0 + + # PAR_IN I/O Mode + # PSU_DDR_PHY_RDIMMGCR0_PARINIOM 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD 0x0 + + # Rank Mirror Enable. + # PSU_DDR_PHY_RDIMMGCR0_RNKMRREN 0x2 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_RDIMMGCR0_RESERVED_3 0x0 + + # Stop on Parity Error + # PSU_DDR_PHY_RDIMMGCR0_SOPERR 0x0 + + # Parity Error No Registering + # PSU_DDR_PHY_RDIMMGCR0_ERRNOREG 0x0 + + # Registered DIMM + # PSU_DDR_PHY_RDIMMGCR0_RDIMM 0x0 + + # RDIMM General Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD080140, 0xFFFFFFFFU ,0x08400020U) */ + mask_write 0XFD080140 0xFFFFFFFF 0x08400020 + # Register : RDIMMGCR1 @ 0XFD080144

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29 0x0 + + # Address [17] B-side Inversion Disable + # PSU_DDR_PHY_RDIMMGCR1_A17BID 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_RDIMMGCR1_RESERVED_27 0x0 + + # Command word to command word programming delay + # PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_RDIMMGCR1_RESERVED_23 0x0 + + # Command word to command word programming delay + # PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_RDIMMGCR1_RESERVED_19 0x0 + + # Command word to command word programming delay + # PSU_DDR_PHY_RDIMMGCR1_TBCMRD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14 0x0 + + # Stabilization time + # PSU_DDR_PHY_RDIMMGCR1_TBCSTAB 0xc80 + + # RDIMM General Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U) */ + mask_write 0XFD080144 0xFFFFFFFF 0x00000C80 + # Register : RDIMMCR0 @ 0XFD080150

    + + # DDR4/DDR3 Control Word 7 + # PSU_DDR_PHY_RDIMMCR0_RC7 0x0 + + # DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved + # PSU_DDR_PHY_RDIMMCR0_RC6 0x0 + + # DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) + # PSU_DDR_PHY_RDIMMCR0_RC5 0x0 + + # DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control + # Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont + # rol Word) + # PSU_DDR_PHY_RDIMMCR0_RC4 0x0 + + # DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo + # rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri + # cs Control Word) + # PSU_DDR_PHY_RDIMMCR0_RC3 0x0 + + # DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 + # (Timing Control Word) + # PSU_DDR_PHY_RDIMMCR0_RC2 0x0 + + # DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) + # PSU_DDR_PHY_RDIMMCR0_RC1 0x0 + + # DDR4/DDR3 Control Word 0 (Global Features Control Word) + # PSU_DDR_PHY_RDIMMCR0_RC0 0x0 + + # RDIMM Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD080150 0xFFFFFFFF 0x00000000 + # Register : RDIMMCR1 @ 0XFD080154

    + + # Control Word 15 + # PSU_DDR_PHY_RDIMMCR1_RC15 0x0 + + # DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved + # PSU_DDR_PHY_RDIMMCR1_RC14 0x0 + + # DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved + # PSU_DDR_PHY_RDIMMCR1_RC13 0x0 + + # DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved + # PSU_DDR_PHY_RDIMMCR1_RC12 0x0 + + # DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo + # rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word) + # PSU_DDR_PHY_RDIMMCR1_RC11 0x0 + + # DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) + # PSU_DDR_PHY_RDIMMCR1_RC10 0x2 + + # DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) + # PSU_DDR_PHY_RDIMMCR1_RC9 0x0 + + # DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con + # trol Word 8 (Additional Input Bus Termination Setting Control Word) + # PSU_DDR_PHY_RDIMMCR1_RC8 0x0 + + # RDIMM Control Register 1 + #(OFFSET, MASK, VALUE) (0XFD080154, 0xFFFFFFFFU ,0x00000200U) */ + mask_write 0XFD080154 0xFFFFFFFF 0x00000200 + # Register : MR0 @ 0XFD080180

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_MR0_RESERVED_31_8 0x6 + + # CA Terminating Rank + # PSU_DDR_PHY_MR0_CATR 0x0 + + # Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + # be programmed to 0x0. + # PSU_DDR_PHY_MR0_RSVD_6_5 0x1 + + # Built-in Self-Test for RZQ + # PSU_DDR_PHY_MR0_RZQI 0x2 + + # Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + # be programmed to 0x0. + # PSU_DDR_PHY_MR0_RSVD_2_0 0x0 + + # LPDDR4 Mode Register 0 + #(OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000630U) */ + mask_write 0XFD080180 0xFFFFFFFF 0x00000630 + # Register : MR1 @ 0XFD080184

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_MR1_RESERVED_31_8 0x3 + + # Read Postamble Length + # PSU_DDR_PHY_MR1_RDPST 0x0 + + # Write-recovery for auto-precharge command + # PSU_DDR_PHY_MR1_NWR 0x0 + + # Read Preamble Length + # PSU_DDR_PHY_MR1_RDPRE 0x0 + + # Write Preamble Length + # PSU_DDR_PHY_MR1_WRPRE 0x0 + + # Burst Length + # PSU_DDR_PHY_MR1_BL 0x1 + + # LPDDR4 Mode Register 1 + #(OFFSET, MASK, VALUE) (0XFD080184, 0xFFFFFFFFU ,0x00000301U) */ + mask_write 0XFD080184 0xFFFFFFFF 0x00000301 + # Register : MR2 @ 0XFD080188

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_MR2_RESERVED_31_8 0x0 + + # Write Leveling + # PSU_DDR_PHY_MR2_WRL 0x0 + + # Write Latency Set + # PSU_DDR_PHY_MR2_WLS 0x0 + + # Write Latency + # PSU_DDR_PHY_MR2_WL 0x4 + + # Read Latency + # PSU_DDR_PHY_MR2_RL 0x0 + + # LPDDR4 Mode Register 2 + #(OFFSET, MASK, VALUE) (0XFD080188, 0xFFFFFFFFU ,0x00000020U) */ + mask_write 0XFD080188 0xFFFFFFFF 0x00000020 + # Register : MR3 @ 0XFD08018C

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_MR3_RESERVED_31_8 0x2 + + # DBI-Write Enable + # PSU_DDR_PHY_MR3_DBIWR 0x0 + + # DBI-Read Enable + # PSU_DDR_PHY_MR3_DBIRD 0x0 + + # Pull-down Drive Strength + # PSU_DDR_PHY_MR3_PDDS 0x0 + + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. + # PSU_DDR_PHY_MR3_RSVD 0x0 + + # Write Postamble Length + # PSU_DDR_PHY_MR3_WRPST 0x0 + + # Pull-up Calibration Point + # PSU_DDR_PHY_MR3_PUCAL 0x0 + + # LPDDR4 Mode Register 3 + #(OFFSET, MASK, VALUE) (0XFD08018C, 0xFFFFFFFFU ,0x00000200U) */ + mask_write 0XFD08018C 0xFFFFFFFF 0x00000200 + # Register : MR4 @ 0XFD080190

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_MR4_RESERVED_31_16 0x0 + + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. + # PSU_DDR_PHY_MR4_RSVD_15_13 0x0 + + # Write Preamble + # PSU_DDR_PHY_MR4_WRP 0x0 + + # Read Preamble + # PSU_DDR_PHY_MR4_RDP 0x0 + + # Read Preamble Training Mode + # PSU_DDR_PHY_MR4_RPTM 0x0 + + # Self Refresh Abort + # PSU_DDR_PHY_MR4_SRA 0x0 + + # CS to Command Latency Mode + # PSU_DDR_PHY_MR4_CS2CMDL 0x0 + + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. + # PSU_DDR_PHY_MR4_RSVD1 0x0 + + # Internal VREF Monitor + # PSU_DDR_PHY_MR4_IVM 0x0 + + # Temperature Controlled Refresh Mode + # PSU_DDR_PHY_MR4_TCRM 0x0 + + # Temperature Controlled Refresh Range + # PSU_DDR_PHY_MR4_TCRR 0x0 + + # Maximum Power Down Mode + # PSU_DDR_PHY_MR4_MPDM 0x0 + + # This is a JEDEC reserved bit and is recommended by JEDEC to be programme + # d to 0x0. + # PSU_DDR_PHY_MR4_RSVD_0 0x0 + + # DDR4 Mode Register 4 + #(OFFSET, MASK, VALUE) (0XFD080190, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD080190 0xFFFFFFFF 0x00000000 + # Register : MR5 @ 0XFD080194

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_MR5_RESERVED_31_16 0x0 + + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. + # PSU_DDR_PHY_MR5_RSVD 0x0 + + # Read DBI + # PSU_DDR_PHY_MR5_RDBI 0x0 + + # Write DBI + # PSU_DDR_PHY_MR5_WDBI 0x0 + + # Data Mask + # PSU_DDR_PHY_MR5_DM 0x1 + + # CA Parity Persistent Error + # PSU_DDR_PHY_MR5_CAPPE 0x1 + + # RTT_PARK + # PSU_DDR_PHY_MR5_RTTPARK 0x3 + + # ODT Input Buffer during Power Down mode + # PSU_DDR_PHY_MR5_ODTIBPD 0x0 + + # C/A Parity Error Status + # PSU_DDR_PHY_MR5_CAPES 0x0 + + # CRC Error Clear + # PSU_DDR_PHY_MR5_CRCEC 0x0 + + # C/A Parity Latency Mode + # PSU_DDR_PHY_MR5_CAPM 0x0 + + # DDR4 Mode Register 5 + #(OFFSET, MASK, VALUE) (0XFD080194, 0xFFFFFFFFU ,0x000006C0U) */ + mask_write 0XFD080194 0xFFFFFFFF 0x000006C0 + # Register : MR6 @ 0XFD080198

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_MR6_RESERVED_31_16 0x0 + + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. + # PSU_DDR_PHY_MR6_RSVD_15_13 0x0 + + # CAS_n to CAS_n command delay for same bank group (tCCD_L) + # PSU_DDR_PHY_MR6_TCCDL 0x2 + + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. + # PSU_DDR_PHY_MR6_RSVD_9_8 0x0 + + # VrefDQ Training Enable + # PSU_DDR_PHY_MR6_VDDQTEN 0x0 + + # VrefDQ Training Range + # PSU_DDR_PHY_MR6_VDQTRG 0x0 + + # VrefDQ Training Values + # PSU_DDR_PHY_MR6_VDQTVAL 0x19 + + # DDR4 Mode Register 6 + #(OFFSET, MASK, VALUE) (0XFD080198, 0xFFFFFFFFU ,0x00000819U) */ + mask_write 0XFD080198 0xFFFFFFFF 0x00000819 + # Register : MR11 @ 0XFD0801AC

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_MR11_RESERVED_31_8 0x0 + + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. + # PSU_DDR_PHY_MR11_RSVD 0x0 + + # Power Down Control + # PSU_DDR_PHY_MR11_PDCTL 0x0 + + # DQ Bus Receiver On-Die-Termination + # PSU_DDR_PHY_MR11_DQODT 0x0 + + # LPDDR4 Mode Register 11 + #(OFFSET, MASK, VALUE) (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD0801AC 0xFFFFFFFF 0x00000000 + # Register : MR12 @ 0XFD0801B0

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_MR12_RESERVED_31_8 0x0 + + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. + # PSU_DDR_PHY_MR12_RSVD 0x0 + + # VREF_CA Range Select. + # PSU_DDR_PHY_MR12_VR_CA 0x1 + + # Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. + # PSU_DDR_PHY_MR12_VREF_CA 0xd + + # LPDDR4 Mode Register 12 + #(OFFSET, MASK, VALUE) (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU) */ + mask_write 0XFD0801B0 0xFFFFFFFF 0x0000004D + # Register : MR13 @ 0XFD0801B4

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_MR13_RESERVED_31_8 0x0 + + # Frequency Set Point Operation Mode + # PSU_DDR_PHY_MR13_FSPOP 0x0 + + # Frequency Set Point Write Enable + # PSU_DDR_PHY_MR13_FSPWR 0x0 + + # Data Mask Enable + # PSU_DDR_PHY_MR13_DMD 0x0 + + # Refresh Rate Option + # PSU_DDR_PHY_MR13_RRO 0x0 + + # VREF Current Generator + # PSU_DDR_PHY_MR13_VRCG 0x1 + + # VREF Output + # PSU_DDR_PHY_MR13_VRO 0x0 + + # Read Preamble Training Mode + # PSU_DDR_PHY_MR13_RPT 0x0 + + # Command Bus Training + # PSU_DDR_PHY_MR13_CBT 0x0 + + # LPDDR4 Mode Register 13 + #(OFFSET, MASK, VALUE) (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U) */ + mask_write 0XFD0801B4 0xFFFFFFFF 0x00000008 + # Register : MR14 @ 0XFD0801B8

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_MR14_RESERVED_31_8 0x0 + + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. + # PSU_DDR_PHY_MR14_RSVD 0x0 + + # VREFDQ Range Selects. + # PSU_DDR_PHY_MR14_VR_DQ 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_MR14_VREF_DQ 0xd + + # LPDDR4 Mode Register 14 + #(OFFSET, MASK, VALUE) (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU) */ + mask_write 0XFD0801B8 0xFFFFFFFF 0x0000004D + # Register : MR22 @ 0XFD0801D8

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_MR22_RESERVED_31_8 0x0 + + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. + # PSU_DDR_PHY_MR22_RSVD 0x0 + + # CA ODT termination disable. + # PSU_DDR_PHY_MR22_ODTD_CA 0x0 + + # ODT CS override. + # PSU_DDR_PHY_MR22_ODTE_CS 0x0 + + # ODT CK override. + # PSU_DDR_PHY_MR22_ODTE_CK 0x0 + + # Controller ODT value for VOH calibration. + # PSU_DDR_PHY_MR22_CODT 0x0 + + # LPDDR4 Mode Register 22 + #(OFFSET, MASK, VALUE) (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD0801D8 0xFFFFFFFF 0x00000000 + # Register : DTCR0 @ 0XFD080200

    + + # Refresh During Training + # PSU_DDR_PHY_DTCR0_RFSHDT 0x8 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0 + + # Data Training Debug Rank Select + # PSU_DDR_PHY_DTCR0_DTDRS 0x0 + + # Data Training with Early/Extended Gate + # PSU_DDR_PHY_DTCR0_DTEXG 0x0 + + # Data Training Extended Write DQS + # PSU_DDR_PHY_DTCR0_DTEXD 0x0 + + # Data Training Debug Step + # PSU_DDR_PHY_DTCR0_DTDSTP 0x0 + + # Data Training Debug Enable + # PSU_DDR_PHY_DTCR0_DTDEN 0x0 + + # Data Training Debug Byte Select + # PSU_DDR_PHY_DTCR0_DTDBS 0x0 + + # Data Training read DBI deskewing configuration + # PSU_DDR_PHY_DTCR0_DTRDBITR 0x2 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTCR0_RESERVED_13 0x0 + + # Data Training Write Bit Deskew Data Mask + # PSU_DDR_PHY_DTCR0_DTWBDDM 0x1 + + # Refreshes Issued During Entry to Training + # PSU_DDR_PHY_DTCR0_RFSHEN 0x1 + + # Data Training Compare Data + # PSU_DDR_PHY_DTCR0_DTCMPD 0x1 + + # Data Training Using MPR + # PSU_DDR_PHY_DTCR0_DTMPR 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTCR0_RESERVED_5_4 0x0 + + # Data Training Repeat Number + # PSU_DDR_PHY_DTCR0_DTRPTN 0x7 + + # Data Training Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U) */ + mask_write 0XFD080200 0xFFFFFFFF 0x800091C7 + # Register : DTCR1 @ 0XFD080204

    + + # Rank Enable. + # PSU_DDR_PHY_DTCR1_RANKEN_RSVD 0x0 + + # Rank Enable. + # PSU_DDR_PHY_DTCR1_RANKEN 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTCR1_RESERVED_15_14 0x0 + + # Data Training Rank + # PSU_DDR_PHY_DTCR1_DTRANK 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTCR1_RESERVED_11 0x0 + + # Read Leveling Gate Sampling Difference + # PSU_DDR_PHY_DTCR1_RDLVLGDIFF 0x2 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTCR1_RESERVED_7 0x0 + + # Read Leveling Gate Shift + # PSU_DDR_PHY_DTCR1_RDLVLGS 0x3 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DTCR1_RESERVED_3 0x0 + + # Read Preamble Training enable + # PSU_DDR_PHY_DTCR1_RDPRMVL_TRN 0x1 + + # Read Leveling Enable + # PSU_DDR_PHY_DTCR1_RDLVLEN 0x1 + + # Basic Gate Training Enable + # PSU_DDR_PHY_DTCR1_BSTEN 0x0 + + # Data Training Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD080204, 0xFFFFFFFFU ,0x00010236U) */ + mask_write 0XFD080204 0xFFFFFFFF 0x00010236 + # Register : CATR0 @ 0XFD080240

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0 + + # Minimum time (in terms of number of dram clocks) between two consectuve + # CA calibration command + # PSU_DDR_PHY_CATR0_CACD 0x14 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0 + + # Minimum time (in terms of number of dram clocks) PUB should wait before + # sampling the CA response after Calibration command has been sent to the + # memory + # PSU_DDR_PHY_CATR0_CAADR 0x10 + + # CA_1 Response Byte Lane 1 + # PSU_DDR_PHY_CATR0_CA1BYTE1 0x5 + + # CA_1 Response Byte Lane 0 + # PSU_DDR_PHY_CATR0_CA1BYTE0 0x4 + + # CA Training Register 0 + #(OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) */ + mask_write 0XFD080240 0xFFFFFFFF 0x00141054 + # Register : DQSDR0 @ 0XFD080250

    + + # Number of delay taps by which the DQS gate LCDL will be updated when DQS + # drift is detected + # PSU_DDR_PHY_DQSDR0_DFTDLY 0x0 + + # Drift Impedance Update + # PSU_DDR_PHY_DQSDR0_DFTZQUP 0x0 + + # Drift DDL Update + # PSU_DDR_PHY_DQSDR0_DFTDDLUP 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DQSDR0_RESERVED_25_22 0x0 + + # Drift Read Spacing + # PSU_DDR_PHY_DQSDR0_DFTRDSPC 0x0 + + # Drift Back-to-Back Reads + # PSU_DDR_PHY_DQSDR0_DFTB2BRD 0x8 + + # Drift Idle Reads + # PSU_DDR_PHY_DQSDR0_DFTIDLRD 0x8 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DQSDR0_RESERVED_11_8 0x0 + + # Gate Pulse Enable + # PSU_DDR_PHY_DQSDR0_DFTGPULSE 0x0 + + # DQS Drift Update Mode + # PSU_DDR_PHY_DQSDR0_DFTUPMODE 0x0 + + # DQS Drift Detection Mode + # PSU_DDR_PHY_DQSDR0_DFTDTMODE 0x0 + + # DQS Drift Detection Enable + # PSU_DDR_PHY_DQSDR0_DFTDTEN 0x0 + + # DQS Drift Register 0 + #(OFFSET, MASK, VALUE) (0XFD080250, 0xFFFFFFFFU ,0x00088000U) */ + mask_write 0XFD080250 0xFFFFFFFF 0x00088000 + # Register : BISTLSR @ 0XFD080414

    + + # LFSR seed for pseudo-random BIST patterns + # PSU_DDR_PHY_BISTLSR_SEED 0x12341000 + + # BIST LFSR Seed Register + #(OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U) */ + mask_write 0XFD080414 0xFFFFFFFF 0x12341000 + # Register : RIOCR5 @ 0XFD0804F4

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_RIOCR5_RESERVED_31_16 0x0 + + # Reserved. Return zeros on reads. + # PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD 0x0 + + # SDRAM On-die Termination Output Enable (OE) Mode Selection. + # PSU_DDR_PHY_RIOCR5_ODTOEMODE 0x5 + + # Rank I/O Configuration Register 5 + #(OFFSET, MASK, VALUE) (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U) */ + mask_write 0XFD0804F4 0xFFFFFFFF 0x00000005 + # Register : ACIOCR0 @ 0XFD080500

    + + # Address/Command Slew Rate (D3F I/O Only) + # PSU_DDR_PHY_ACIOCR0_ACSR 0x0 + + # SDRAM Reset I/O Mode + # PSU_DDR_PHY_ACIOCR0_RSTIOM 0x1 + + # SDRAM Reset Power Down Receiver + # PSU_DDR_PHY_ACIOCR0_RSTPDR 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACIOCR0_RESERVED_27 0x0 + + # SDRAM Reset On-Die Termination + # PSU_DDR_PHY_ACIOCR0_RSTODT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACIOCR0_RESERVED_25_10 0x0 + + # CK Duty Cycle Correction + # PSU_DDR_PHY_ACIOCR0_CKDCC 0x0 + + # AC Power Down Receiver Mode + # PSU_DDR_PHY_ACIOCR0_ACPDRMODE 0x2 + + # AC On-die Termination Mode + # PSU_DDR_PHY_ACIOCR0_ACODTMODE 0x2 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACIOCR0_RESERVED_1 0x0 + + # Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. + # PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL 0x0 + + # AC I/O Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD080500, 0xFFFFFFFFU ,0x30000028U) */ + mask_write 0XFD080500 0xFFFFFFFF 0x30000028 + # Register : ACIOCR2 @ 0XFD080508

    + + # Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL + # slice + # PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0 + + # Clock gating for Output Enable D slices [0] + # PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0 0x0 + + # Clock gating for Power Down Receiver D slices [0] + # PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0 0x0 + + # Clock gating for Termination Enable D slices [0] + # PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0 0x0 + + # Clock gating for CK# D slices [1:0] + # PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0 0x2 + + # Clock gating for CK D slices [1:0] + # PSU_DDR_PHY_ACIOCR2_CKCLKGATE0 0x2 + + # Clock gating for AC D slices [23:0] + # PSU_DDR_PHY_ACIOCR2_ACCLKGATE0 0x0 + + # AC I/O Configuration Register 2 + #(OFFSET, MASK, VALUE) (0XFD080508, 0xFFFFFFFFU ,0x0A000000U) */ + mask_write 0XFD080508 0xFFFFFFFF 0x0A000000 + # Register : ACIOCR3 @ 0XFD08050C

    + + # SDRAM Parity Output Enable (OE) Mode Selection + # PSU_DDR_PHY_ACIOCR3_PAROEMODE 0x0 + + # SDRAM Bank Group Output Enable (OE) Mode Selection + # PSU_DDR_PHY_ACIOCR3_BGOEMODE 0x0 + + # SDRAM Bank Address Output Enable (OE) Mode Selection + # PSU_DDR_PHY_ACIOCR3_BAOEMODE 0x0 + + # SDRAM A[17] Output Enable (OE) Mode Selection + # PSU_DDR_PHY_ACIOCR3_A17OEMODE 0x0 + + # SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection + # PSU_DDR_PHY_ACIOCR3_A16OEMODE 0x0 + + # SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) + # PSU_DDR_PHY_ACIOCR3_ACTOEMODE 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACIOCR3_RESERVED_15_8 0x0 + + # Reserved. Return zeros on reads. + # PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD 0x0 + + # SDRAM CK Output Enable (OE) Mode Selection. + # PSU_DDR_PHY_ACIOCR3_CKOEMODE 0x9 + + # AC I/O Configuration Register 3 + #(OFFSET, MASK, VALUE) (0XFD08050C, 0xFFFFFFFFU ,0x00000009U) */ + mask_write 0XFD08050C 0xFFFFFFFF 0x00000009 + # Register : ACIOCR4 @ 0XFD080510

    + + # Clock gating for AC LB slices and loopback read valid slices + # PSU_DDR_PHY_ACIOCR4_LBCLKGATE 0x0 + + # Clock gating for Output Enable D slices [1] + # PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1 0x0 + + # Clock gating for Power Down Receiver D slices [1] + # PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1 0x0 + + # Clock gating for Termination Enable D slices [1] + # PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1 0x0 + + # Clock gating for CK# D slices [3:2] + # PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1 0x2 + + # Clock gating for CK D slices [3:2] + # PSU_DDR_PHY_ACIOCR4_CKCLKGATE1 0x2 + + # Clock gating for AC D slices [47:24] + # PSU_DDR_PHY_ACIOCR4_ACCLKGATE1 0x0 + + # AC I/O Configuration Register 4 + #(OFFSET, MASK, VALUE) (0XFD080510, 0xFFFFFFFFU ,0x0A000000U) */ + mask_write 0XFD080510 0xFFFFFFFF 0x0A000000 + # Register : IOVCR0 @ 0XFD080520

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_IOVCR0_RESERVED_31_29 0x0 + + # Address/command lane VREF Pad Enable + # PSU_DDR_PHY_IOVCR0_ACREFPEN 0x0 + + # Address/command lane Internal VREF Enable + # PSU_DDR_PHY_IOVCR0_ACREFEEN 0x0 + + # Address/command lane Single-End VREF Enable + # PSU_DDR_PHY_IOVCR0_ACREFSEN 0x1 + + # Address/command lane Internal VREF Enable + # PSU_DDR_PHY_IOVCR0_ACREFIEN 0x1 + + # External VREF generato REFSEL range select + # PSU_DDR_PHY_IOVCR0_ACREFESELRANGE 0x0 + + # Address/command lane External VREF Select + # PSU_DDR_PHY_IOVCR0_ACREFESEL 0x0 + + # Single ended VREF generator REFSEL range select + # PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE 0x1 + + # Address/command lane Single-End VREF Select + # PSU_DDR_PHY_IOVCR0_ACREFSSEL 0x30 + + # Internal VREF generator REFSEL ragne select + # PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1 + + # REFSEL Control for internal AC IOs + # PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x4e + + # IO VREF Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0CEU) */ + mask_write 0XFD080520 0xFFFFFFFF 0x0300B0CE + # Register : VTCR0 @ 0XFD080528

    + + # Number of ctl_clk required to meet (> 150ns) timing requirements during + # DRAM DQ VREF training + # PSU_DDR_PHY_VTCR0_TVREF 0x7 + + # DRM DQ VREF training Enable + # PSU_DDR_PHY_VTCR0_DVEN 0x1 + + # Per Device Addressability Enable + # PSU_DDR_PHY_VTCR0_PDAEN 0x1 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_VTCR0_RESERVED_26 0x0 + + # VREF Word Count + # PSU_DDR_PHY_VTCR0_VWCR 0x4 + + # DRAM DQ VREF step size used during DRAM VREF training + # PSU_DDR_PHY_VTCR0_DVSS 0x0 + + # Maximum VREF limit value used during DRAM VREF training + # PSU_DDR_PHY_VTCR0_DVMAX 0x32 + + # Minimum VREF limit value used during DRAM VREF training + # PSU_DDR_PHY_VTCR0_DVMIN 0x0 + + # Initial DRAM DQ VREF value used during DRAM VREF training + # PSU_DDR_PHY_VTCR0_DVINIT 0x19 + + # VREF Training Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD080528, 0xFFFFFFFFU ,0xF9032019U) */ + mask_write 0XFD080528 0xFFFFFFFF 0xF9032019 + # Register : VTCR1 @ 0XFD08052C

    + + # Host VREF step size used during VREF training. The register value of N i + # ndicates step size of (N+1) + # PSU_DDR_PHY_VTCR1_HVSS 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_VTCR1_RESERVED_27 0x0 + + # Maximum VREF limit value used during DRAM VREF training. + # PSU_DDR_PHY_VTCR1_HVMAX 0x7f + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_VTCR1_RESERVED_19 0x0 + + # Minimum VREF limit value used during DRAM VREF training. + # PSU_DDR_PHY_VTCR1_HVMIN 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_VTCR1_RESERVED_11 0x0 + + # Static Host Vref Rank Value + # PSU_DDR_PHY_VTCR1_SHRNK 0x0 + + # Static Host Vref Rank Enable + # PSU_DDR_PHY_VTCR1_SHREN 0x1 + + # Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir + # ements during Host IO VREF training + # PSU_DDR_PHY_VTCR1_TVREFIO 0x7 + + # Eye LCDL Offset value for VREF training + # PSU_DDR_PHY_VTCR1_EOFF 0x0 + + # Number of LCDL Eye points for which VREF training is repeated + # PSU_DDR_PHY_VTCR1_ENUM 0x0 + + # HOST (IO) internal VREF training Enable + # PSU_DDR_PHY_VTCR1_HVEN 0x1 + + # Host IO Type Control + # PSU_DDR_PHY_VTCR1_HVIO 0x1 + + # VREF Training Control Register 1 + #(OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U) */ + mask_write 0XFD08052C 0xFFFFFFFF 0x07F001E3 + # Register : ACBDLR1 @ 0XFD080544

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0 + + # Delay select for the BDL on Parity. + # PSU_DDR_PHY_ACBDLR1_PARBD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0 + + # Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn + # ected to WE. + # PSU_DDR_PHY_ACBDLR1_A16BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0 + + # Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi + # s pin is connected to CAS. + # PSU_DDR_PHY_ACBDLR1_A17BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0 + + # Delay select for the BDL on ACTN. + # PSU_DDR_PHY_ACBDLR1_ACTBD 0x0 + + # AC Bit Delay Line Register 1 + #(OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD080544 0xFFFFFFFF 0x00000000 + # Register : ACBDLR2 @ 0XFD080548

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0 + + # Delay select for the BDL on BG[1]. + # PSU_DDR_PHY_ACBDLR2_BG1BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0 + + # Delay select for the BDL on BG[0]. + # PSU_DDR_PHY_ACBDLR2_BG0BD 0x0 + + # Reser.ved Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0 + + # Delay select for the BDL on BA[1]. + # PSU_DDR_PHY_ACBDLR2_BA1BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0 + + # Delay select for the BDL on BA[0]. + # PSU_DDR_PHY_ACBDLR2_BA0BD 0x0 + + # AC Bit Delay Line Register 2 + #(OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD080548 0xFFFFFFFF 0x00000000 + # Register : ACBDLR6 @ 0XFD080558

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0 + + # Delay select for the BDL on Address A[3]. + # PSU_DDR_PHY_ACBDLR6_A03BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0 + + # Delay select for the BDL on Address A[2]. + # PSU_DDR_PHY_ACBDLR6_A02BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0 + + # Delay select for the BDL on Address A[1]. + # PSU_DDR_PHY_ACBDLR6_A01BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0 + + # Delay select for the BDL on Address A[0]. + # PSU_DDR_PHY_ACBDLR6_A00BD 0x0 + + # AC Bit Delay Line Register 6 + #(OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD080558 0xFFFFFFFF 0x00000000 + # Register : ACBDLR7 @ 0XFD08055C

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0 + + # Delay select for the BDL on Address A[7]. + # PSU_DDR_PHY_ACBDLR7_A07BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0 + + # Delay select for the BDL on Address A[6]. + # PSU_DDR_PHY_ACBDLR7_A06BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR7_RESERVED_15_14 0x0 + + # Delay select for the BDL on Address A[5]. + # PSU_DDR_PHY_ACBDLR7_A05BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR7_RESERVED_7_6 0x0 + + # Delay select for the BDL on Address A[4]. + # PSU_DDR_PHY_ACBDLR7_A04BD 0x0 + + # AC Bit Delay Line Register 7 + #(OFFSET, MASK, VALUE) (0XFD08055C, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD08055C 0xFFFFFFFF 0x00000000 + # Register : ACBDLR8 @ 0XFD080560

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR8_RESERVED_31_30 0x0 + + # Delay select for the BDL on Address A[11]. + # PSU_DDR_PHY_ACBDLR8_A11BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR8_RESERVED_23_22 0x0 + + # Delay select for the BDL on Address A[10]. + # PSU_DDR_PHY_ACBDLR8_A10BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR8_RESERVED_15_14 0x0 + + # Delay select for the BDL on Address A[9]. + # PSU_DDR_PHY_ACBDLR8_A09BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR8_RESERVED_7_6 0x0 + + # Delay select for the BDL on Address A[8]. + # PSU_DDR_PHY_ACBDLR8_A08BD 0x0 + + # AC Bit Delay Line Register 8 + #(OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD080560 0xFFFFFFFF 0x00000000 + # Register : ACBDLR9 @ 0XFD080564

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0 + + # Delay select for the BDL on Address A[15]. + # PSU_DDR_PHY_ACBDLR9_A15BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0 + + # Delay select for the BDL on Address A[14]. + # PSU_DDR_PHY_ACBDLR9_A14BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0 + + # Delay select for the BDL on Address A[13]. + # PSU_DDR_PHY_ACBDLR9_A13BD 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0 + + # Delay select for the BDL on Address A[12]. + # PSU_DDR_PHY_ACBDLR9_A12BD 0x0 + + # AC Bit Delay Line Register 9 + #(OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD080564 0xFFFFFFFF 0x00000000 + # Register : ZQCR @ 0XFD080680

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0 + + # ZQ VREF Range + # PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0 + + # Programmable Wait for Frequency B + # PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11 + + # Programmable Wait for Frequency A + # PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x15 + + # ZQ VREF Pad Enable + # PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0 + + # ZQ Internal VREF Enable + # PSU_DDR_PHY_ZQCR_ZQREFIEN 0x1 + + # Choice of termination mode + # PSU_DDR_PHY_ZQCR_ODT_MODE 0x1 + + # Force ZCAL VT update + # PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE 0x0 + + # IO VT Drift Limit + # PSU_DDR_PHY_ZQCR_IODLMT 0x2 + + # Averaging algorithm enable, if set, enables averaging algorithm + # PSU_DDR_PHY_ZQCR_AVGEN 0x1 + + # Maximum number of averaging rounds to be used by averaging algorithm + # PSU_DDR_PHY_ZQCR_AVGMAX 0x2 + + # ZQ Calibration Type + # PSU_DDR_PHY_ZQCR_ZCALT 0x0 + + # ZQ Power Down + # PSU_DDR_PHY_ZQCR_ZQPD 0x0 + + # ZQ Impedance Control Register + #(OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008AAA58U) */ + mask_write 0XFD080680 0xFFFFFFFF 0x008AAA58 + # Register : ZQ0PR0 @ 0XFD080684

    + + # Pull-down drive strength ZCTRL over-ride enable + # PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN 0x0 + + # Pull-up drive strength ZCTRL over-ride enable + # PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN 0x0 + + # Pull-down termination ZCTRL over-ride enable + # PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN 0x0 + + # Pull-up termination ZCTRL over-ride enable + # PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN 0x0 + + # Calibration segment bypass + # PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0 + + # VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + # is driven by the PUB + # PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0 + + # Termination adjustment + # PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST 0x0 + + # Pulldown drive strength adjustment + # PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST 0x0 + + # Pullup drive strength adjustment + # PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST 0x0 + + # DRAM Impedance Divide Ratio + # PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7 + + # HOST Impedance Divide Ratio + # PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x9 + + # Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + # ve strength calibration) + # PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd + + # Impedance Divide Ratio (pullup drive calibration during asymmetric drive + # strength calibration) + # PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd + + # ZQ n Impedance Control Program Register 0 + #(OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000079DDU) */ + mask_write 0XFD080684 0xFFFFFFFF 0x000079DD + # Register : ZQ0OR0 @ 0XFD080694

    + + # Reserved. Return zeros on reads. + # PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26 0x0 + + # Override value for the pull-up output impedance + # PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD 0x1e1 + + # Reserved. Return zeros on reads. + # PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10 0x0 + + # Override value for the pull-down output impedance + # PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD 0x210 + + # ZQ n Impedance Control Override Data Register 0 + #(OFFSET, MASK, VALUE) (0XFD080694, 0xFFFFFFFFU ,0x01E10210U) */ + mask_write 0XFD080694 0xFFFFFFFF 0x01E10210 + # Register : ZQ0OR1 @ 0XFD080698

    + + # Reserved. Return zeros on reads. + # PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26 0x0 + + # Override value for the pull-up termination + # PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD 0x1e1 + + # Reserved. Return zeros on reads. + # PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10 0x0 + + # Override value for the pull-down termination + # PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD 0x0 + + # ZQ n Impedance Control Override Data Register 1 + #(OFFSET, MASK, VALUE) (0XFD080698, 0xFFFFFFFFU ,0x01E10000U) */ + mask_write 0XFD080698 0xFFFFFFFF 0x01E10000 + # Register : ZQ1PR0 @ 0XFD0806A4

    + + # Pull-down drive strength ZCTRL over-ride enable + # PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN 0x0 + + # Pull-up drive strength ZCTRL over-ride enable + # PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN 0x0 + + # Pull-down termination ZCTRL over-ride enable + # PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN 0x0 + + # Pull-up termination ZCTRL over-ride enable + # PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN 0x0 + + # Calibration segment bypass + # PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0 + + # VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + # is driven by the PUB + # PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0 + + # Termination adjustment + # PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST 0x0 + + # Pulldown drive strength adjustment + # PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST 0x1 + + # Pullup drive strength adjustment + # PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST 0x0 + + # DRAM Impedance Divide Ratio + # PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT 0x7 + + # HOST Impedance Divide Ratio + # PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb + + # Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + # ve strength calibration) + # PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd + + # Impedance Divide Ratio (pullup drive calibration during asymmetric drive + # strength calibration) + # PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb + + # ZQ n Impedance Control Program Register 0 + #(OFFSET, MASK, VALUE) (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU) */ + mask_write 0XFD0806A4 0xFFFFFFFF 0x00087BDB + # Register : DX0GCR0 @ 0XFD080700

    + + # Calibration Bypass + # PSU_DDR_PHY_DX0GCR0_CALBYP 0x0 + + # Master Delay Line Enable + # PSU_DDR_PHY_DX0GCR0_MDLEN 0x1 + + # Configurable ODT(TE) Phase Shift + # PSU_DDR_PHY_DX0GCR0_CODTSHFT 0x0 + + # DQS Duty Cycle Correction + # PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0 + + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY + # PSU_DDR_PHY_DX0GCR0_RDDLY 0x8 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX0GCR0_RESERVED_19_14 0x0 + + # DQSNSE Power Down Receiver + # PSU_DDR_PHY_DX0GCR0_DQSNSEPDR 0x0 + + # DQSSE Power Down Receiver + # PSU_DDR_PHY_DX0GCR0_DQSSEPDR 0x0 + + # RTT On Additive Latency + # PSU_DDR_PHY_DX0GCR0_RTTOAL 0x0 + + # RTT Output Hold + # PSU_DDR_PHY_DX0GCR0_RTTOH 0x3 + + # Configurable PDR Phase Shift + # PSU_DDR_PHY_DX0GCR0_CPDRSHFT 0x0 + + # DQSR Power Down + # PSU_DDR_PHY_DX0GCR0_DQSRPD 0x0 + + # DQSG Power Down Receiver + # PSU_DDR_PHY_DX0GCR0_DQSGPDR 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX0GCR0_RESERVED_4 0x0 + + # DQSG On-Die Termination + # PSU_DDR_PHY_DX0GCR0_DQSGODT 0x0 + + # DQSG Output Enable + # PSU_DDR_PHY_DX0GCR0_DQSGOE 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX0GCR0_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD080700, 0xFFFFFFFFU ,0x40800604U) */ + mask_write 0XFD080700 0xFFFFFFFF 0x40800604 + # Register : DX0GCR1 @ 0XFD080704

    + + # Enables the PDR mode for DQ[7:0] + # PSU_DDR_PHY_DX0GCR1_DXPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX0GCR1_RESERVED_15 0x0 + + # Select the delayed or non-delayed read data strobe # + # PSU_DDR_PHY_DX0GCR1_QSNSEL 0x1 + + # Select the delayed or non-delayed read data strobe + # PSU_DDR_PHY_DX0GCR1_QSSEL 0x1 + + # Enables Read Data Strobe in a byte lane + # PSU_DDR_PHY_DX0GCR1_OEEN 0x1 + + # Enables PDR in a byte lane + # PSU_DDR_PHY_DX0GCR1_PDREN 0x1 + + # Enables ODT/TE in a byte lane + # PSU_DDR_PHY_DX0GCR1_TEEN 0x1 + + # Enables Write Data strobe in a byte lane + # PSU_DDR_PHY_DX0GCR1_DSEN 0x1 + + # Enables DM pin in a byte lane + # PSU_DDR_PHY_DX0GCR1_DMEN 0x1 + + # Enables DQ corresponding to each bit in a byte + # PSU_DDR_PHY_DX0GCR1_DQEN 0xff + + # DATX8 n General Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD080704, 0xFFFFFFFFU ,0x00007FFFU) */ + mask_write 0XFD080704 0xFFFFFFFF 0x00007FFF + # Register : DX0GCR3 @ 0XFD08070C

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX0GCR3_RESERVED_31_30 0x0 + + # Read Data BDL VT Compensation + # PSU_DDR_PHY_DX0GCR3_RDBVT 0x1 + + # Write Data BDL VT Compensation + # PSU_DDR_PHY_DX0GCR3_WDBVT 0x1 + + # Read DQS Gating LCDL Delay VT Compensation + # PSU_DDR_PHY_DX0GCR3_RGLVT 0x1 + + # Read DQS LCDL Delay VT Compensation + # PSU_DDR_PHY_DX0GCR3_RDLVT 0x1 + + # Write DQ LCDL Delay VT Compensation + # PSU_DDR_PHY_DX0GCR3_WDLVT 0x1 + + # Write Leveling LCDL Delay VT Compensation + # PSU_DDR_PHY_DX0GCR3_WLLVT 0x1 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX0GCR3_RESERVED_23_22 0x0 + + # Enables the OE mode for DQs + # PSU_DDR_PHY_DX0GCR3_DSNOEMODE 0x0 + + # Enables the TE mode for DQS + # PSU_DDR_PHY_DX0GCR3_DSNTEMODE 0x0 + + # Enables the PDR mode for DQS + # PSU_DDR_PHY_DX0GCR3_DSNPDRMODE 0x0 + + # Enables the OE mode values for DM. + # PSU_DDR_PHY_DX0GCR3_DMOEMODE 0x0 + + # Enables the TE mode values for DM. + # PSU_DDR_PHY_DX0GCR3_DMTEMODE 0x0 + + # Enables the PDR mode values for DM. + # PSU_DDR_PHY_DX0GCR3_DMPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX0GCR3_RESERVED_9_8 0x0 + + # Enables the OE mode values for DQS. + # PSU_DDR_PHY_DX0GCR3_DSOEMODE 0x0 + + # Enables the TE mode values for DQS. + # PSU_DDR_PHY_DX0GCR3_DSTEMODE 0x0 + + # Enables the PDR mode values for DQS. + # PSU_DDR_PHY_DX0GCR3_DSPDRMODE 0x2 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX0GCR3_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 3 + #(OFFSET, MASK, VALUE) (0XFD08070C, 0xFFFFFFFFU ,0x3F000008U) */ + mask_write 0XFD08070C 0xFFFFFFFF 0x3F000008 + # Register : DX0GCR4 @ 0XFD080710

    + + # Byte lane VREF IOM (Used only by D4MU IOs) + # PSU_DDR_PHY_DX0GCR4_RESERVED_31_29 0x0 + + # Byte Lane VREF Pad Enable + # PSU_DDR_PHY_DX0GCR4_DXREFPEN 0x0 + + # Byte Lane Internal VREF Enable + # PSU_DDR_PHY_DX0GCR4_DXREFEEN 0x3 + + # Byte Lane Single-End VREF Enable + # PSU_DDR_PHY_DX0GCR4_DXREFSEN 0x1 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX0GCR4_RESERVED_24 0x0 + + # External VREF generator REFSEL range select + # PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE 0x0 + + # Byte Lane External VREF Select + # PSU_DDR_PHY_DX0GCR4_DXREFESEL 0x0 + + # Single ended VREF generator REFSEL range select + # PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE 0x1 + + # Byte Lane Single-End VREF Select + # PSU_DDR_PHY_DX0GCR4_DXREFSSEL 0x30 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX0GCR4_RESERVED_7_6 0x0 + + # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX0GCR4_DXREFIEN 0xf + + # VRMON control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX0GCR4_DXREFIMON 0x0 + + # DATX8 n General Configuration Register 4 + #(OFFSET, MASK, VALUE) (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU) */ + mask_write 0XFD080710 0xFFFFFFFF 0x0E00B03C + # Register : DX0GCR5 @ 0XFD080714

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX0GCR5_RESERVED_31 0x0 + + # Byte Lane internal VREF Select for Rank 3 + # PSU_DDR_PHY_DX0GCR5_DXREFISELR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX0GCR5_RESERVED_23 0x0 + + # Byte Lane internal VREF Select for Rank 2 + # PSU_DDR_PHY_DX0GCR5_DXREFISELR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0 + + # Byte Lane internal VREF Select for Rank 1 + # PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0 + + # Byte Lane internal VREF Select for Rank 0 + # PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55 + + # DATX8 n General Configuration Register 5 + #(OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080714 0xFFFFFFFF 0x09095555 + # Register : DX0GCR6 @ 0XFD080718

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX0GCR6_RESERVED_31_30 0x0 + + # DRAM DQ VREF Select for Rank3 + # PSU_DDR_PHY_DX0GCR6_DXDQVREFR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX0GCR6_RESERVED_23_22 0x0 + + # DRAM DQ VREF Select for Rank2 + # PSU_DDR_PHY_DX0GCR6_DXDQVREFR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX0GCR6_RESERVED_15_14 0x0 + + # DRAM DQ VREF Select for Rank1 + # PSU_DDR_PHY_DX0GCR6_DXDQVREFR1 0x2b + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX0GCR6_RESERVED_7_6 0x0 + + # DRAM DQ VREF Select for Rank0 + # PSU_DDR_PHY_DX0GCR6_DXDQVREFR0 0x2b + + # DATX8 n General Configuration Register 6 + #(OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU) */ + mask_write 0XFD080718 0xFFFFFFFF 0x09092B2B + # Register : DX1GCR0 @ 0XFD080800

    + + # Calibration Bypass + # PSU_DDR_PHY_DX1GCR0_CALBYP 0x0 + + # Master Delay Line Enable + # PSU_DDR_PHY_DX1GCR0_MDLEN 0x1 + + # Configurable ODT(TE) Phase Shift + # PSU_DDR_PHY_DX1GCR0_CODTSHFT 0x0 + + # DQS Duty Cycle Correction + # PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0 + + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY + # PSU_DDR_PHY_DX1GCR0_RDDLY 0x8 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX1GCR0_RESERVED_19_14 0x0 + + # DQSNSE Power Down Receiver + # PSU_DDR_PHY_DX1GCR0_DQSNSEPDR 0x0 + + # DQSSE Power Down Receiver + # PSU_DDR_PHY_DX1GCR0_DQSSEPDR 0x0 + + # RTT On Additive Latency + # PSU_DDR_PHY_DX1GCR0_RTTOAL 0x0 + + # RTT Output Hold + # PSU_DDR_PHY_DX1GCR0_RTTOH 0x3 + + # Configurable PDR Phase Shift + # PSU_DDR_PHY_DX1GCR0_CPDRSHFT 0x0 + + # DQSR Power Down + # PSU_DDR_PHY_DX1GCR0_DQSRPD 0x0 + + # DQSG Power Down Receiver + # PSU_DDR_PHY_DX1GCR0_DQSGPDR 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX1GCR0_RESERVED_4 0x0 + + # DQSG On-Die Termination + # PSU_DDR_PHY_DX1GCR0_DQSGODT 0x0 + + # DQSG Output Enable + # PSU_DDR_PHY_DX1GCR0_DQSGOE 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX1GCR0_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD080800, 0xFFFFFFFFU ,0x40800604U) */ + mask_write 0XFD080800 0xFFFFFFFF 0x40800604 + # Register : DX1GCR1 @ 0XFD080804

    + + # Enables the PDR mode for DQ[7:0] + # PSU_DDR_PHY_DX1GCR1_DXPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX1GCR1_RESERVED_15 0x0 + + # Select the delayed or non-delayed read data strobe # + # PSU_DDR_PHY_DX1GCR1_QSNSEL 0x1 + + # Select the delayed or non-delayed read data strobe + # PSU_DDR_PHY_DX1GCR1_QSSEL 0x1 + + # Enables Read Data Strobe in a byte lane + # PSU_DDR_PHY_DX1GCR1_OEEN 0x1 + + # Enables PDR in a byte lane + # PSU_DDR_PHY_DX1GCR1_PDREN 0x1 + + # Enables ODT/TE in a byte lane + # PSU_DDR_PHY_DX1GCR1_TEEN 0x1 + + # Enables Write Data strobe in a byte lane + # PSU_DDR_PHY_DX1GCR1_DSEN 0x1 + + # Enables DM pin in a byte lane + # PSU_DDR_PHY_DX1GCR1_DMEN 0x1 + + # Enables DQ corresponding to each bit in a byte + # PSU_DDR_PHY_DX1GCR1_DQEN 0xff + + # DATX8 n General Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD080804, 0xFFFFFFFFU ,0x00007FFFU) */ + mask_write 0XFD080804 0xFFFFFFFF 0x00007FFF + # Register : DX1GCR3 @ 0XFD08080C

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX1GCR3_RESERVED_31_30 0x0 + + # Read Data BDL VT Compensation + # PSU_DDR_PHY_DX1GCR3_RDBVT 0x1 + + # Write Data BDL VT Compensation + # PSU_DDR_PHY_DX1GCR3_WDBVT 0x1 + + # Read DQS Gating LCDL Delay VT Compensation + # PSU_DDR_PHY_DX1GCR3_RGLVT 0x1 + + # Read DQS LCDL Delay VT Compensation + # PSU_DDR_PHY_DX1GCR3_RDLVT 0x1 + + # Write DQ LCDL Delay VT Compensation + # PSU_DDR_PHY_DX1GCR3_WDLVT 0x1 + + # Write Leveling LCDL Delay VT Compensation + # PSU_DDR_PHY_DX1GCR3_WLLVT 0x1 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX1GCR3_RESERVED_23_22 0x0 + + # Enables the OE mode for DQs + # PSU_DDR_PHY_DX1GCR3_DSNOEMODE 0x0 + + # Enables the TE mode for DQS + # PSU_DDR_PHY_DX1GCR3_DSNTEMODE 0x0 + + # Enables the PDR mode for DQS + # PSU_DDR_PHY_DX1GCR3_DSNPDRMODE 0x0 + + # Enables the OE mode values for DM. + # PSU_DDR_PHY_DX1GCR3_DMOEMODE 0x0 + + # Enables the TE mode values for DM. + # PSU_DDR_PHY_DX1GCR3_DMTEMODE 0x0 + + # Enables the PDR mode values for DM. + # PSU_DDR_PHY_DX1GCR3_DMPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX1GCR3_RESERVED_9_8 0x0 + + # Enables the OE mode values for DQS. + # PSU_DDR_PHY_DX1GCR3_DSOEMODE 0x0 + + # Enables the TE mode values for DQS. + # PSU_DDR_PHY_DX1GCR3_DSTEMODE 0x0 + + # Enables the PDR mode values for DQS. + # PSU_DDR_PHY_DX1GCR3_DSPDRMODE 0x2 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX1GCR3_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 3 + #(OFFSET, MASK, VALUE) (0XFD08080C, 0xFFFFFFFFU ,0x3F000008U) */ + mask_write 0XFD08080C 0xFFFFFFFF 0x3F000008 + # Register : DX1GCR4 @ 0XFD080810

    + + # Byte lane VREF IOM (Used only by D4MU IOs) + # PSU_DDR_PHY_DX1GCR4_RESERVED_31_29 0x0 + + # Byte Lane VREF Pad Enable + # PSU_DDR_PHY_DX1GCR4_DXREFPEN 0x0 + + # Byte Lane Internal VREF Enable + # PSU_DDR_PHY_DX1GCR4_DXREFEEN 0x3 + + # Byte Lane Single-End VREF Enable + # PSU_DDR_PHY_DX1GCR4_DXREFSEN 0x1 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX1GCR4_RESERVED_24 0x0 + + # External VREF generator REFSEL range select + # PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE 0x0 + + # Byte Lane External VREF Select + # PSU_DDR_PHY_DX1GCR4_DXREFESEL 0x0 + + # Single ended VREF generator REFSEL range select + # PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE 0x1 + + # Byte Lane Single-End VREF Select + # PSU_DDR_PHY_DX1GCR4_DXREFSSEL 0x30 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX1GCR4_RESERVED_7_6 0x0 + + # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX1GCR4_DXREFIEN 0xf + + # VRMON control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX1GCR4_DXREFIMON 0x0 + + # DATX8 n General Configuration Register 4 + #(OFFSET, MASK, VALUE) (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU) */ + mask_write 0XFD080810 0xFFFFFFFF 0x0E00B03C + # Register : DX1GCR5 @ 0XFD080814

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX1GCR5_RESERVED_31 0x0 + + # Byte Lane internal VREF Select for Rank 3 + # PSU_DDR_PHY_DX1GCR5_DXREFISELR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX1GCR5_RESERVED_23 0x0 + + # Byte Lane internal VREF Select for Rank 2 + # PSU_DDR_PHY_DX1GCR5_DXREFISELR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0 + + # Byte Lane internal VREF Select for Rank 1 + # PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0 + + # Byte Lane internal VREF Select for Rank 0 + # PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55 + + # DATX8 n General Configuration Register 5 + #(OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080814 0xFFFFFFFF 0x09095555 + # Register : DX1GCR6 @ 0XFD080818

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX1GCR6_RESERVED_31_30 0x0 + + # DRAM DQ VREF Select for Rank3 + # PSU_DDR_PHY_DX1GCR6_DXDQVREFR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX1GCR6_RESERVED_23_22 0x0 + + # DRAM DQ VREF Select for Rank2 + # PSU_DDR_PHY_DX1GCR6_DXDQVREFR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX1GCR6_RESERVED_15_14 0x0 + + # DRAM DQ VREF Select for Rank1 + # PSU_DDR_PHY_DX1GCR6_DXDQVREFR1 0x2b + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX1GCR6_RESERVED_7_6 0x0 + + # DRAM DQ VREF Select for Rank0 + # PSU_DDR_PHY_DX1GCR6_DXDQVREFR0 0x2b + + # DATX8 n General Configuration Register 6 + #(OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU) */ + mask_write 0XFD080818 0xFFFFFFFF 0x09092B2B + # Register : DX2GCR0 @ 0XFD080900

    + + # Calibration Bypass + # PSU_DDR_PHY_DX2GCR0_CALBYP 0x0 + + # Master Delay Line Enable + # PSU_DDR_PHY_DX2GCR0_MDLEN 0x1 + + # Configurable ODT(TE) Phase Shift + # PSU_DDR_PHY_DX2GCR0_CODTSHFT 0x0 + + # DQS Duty Cycle Correction + # PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0 + + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY + # PSU_DDR_PHY_DX2GCR0_RDDLY 0x8 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX2GCR0_RESERVED_19_14 0x0 + + # DQSNSE Power Down Receiver + # PSU_DDR_PHY_DX2GCR0_DQSNSEPDR 0x0 + + # DQSSE Power Down Receiver + # PSU_DDR_PHY_DX2GCR0_DQSSEPDR 0x0 + + # RTT On Additive Latency + # PSU_DDR_PHY_DX2GCR0_RTTOAL 0x0 + + # RTT Output Hold + # PSU_DDR_PHY_DX2GCR0_RTTOH 0x3 + + # Configurable PDR Phase Shift + # PSU_DDR_PHY_DX2GCR0_CPDRSHFT 0x0 + + # DQSR Power Down + # PSU_DDR_PHY_DX2GCR0_DQSRPD 0x0 + + # DQSG Power Down Receiver + # PSU_DDR_PHY_DX2GCR0_DQSGPDR 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX2GCR0_RESERVED_4 0x0 + + # DQSG On-Die Termination + # PSU_DDR_PHY_DX2GCR0_DQSGODT 0x0 + + # DQSG Output Enable + # PSU_DDR_PHY_DX2GCR0_DQSGOE 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX2GCR0_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD080900, 0xFFFFFFFFU ,0x40800604U) */ + mask_write 0XFD080900 0xFFFFFFFF 0x40800604 + # Register : DX2GCR1 @ 0XFD080904

    + + # Enables the PDR mode for DQ[7:0] + # PSU_DDR_PHY_DX2GCR1_DXPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX2GCR1_RESERVED_15 0x0 + + # Select the delayed or non-delayed read data strobe # + # PSU_DDR_PHY_DX2GCR1_QSNSEL 0x1 + + # Select the delayed or non-delayed read data strobe + # PSU_DDR_PHY_DX2GCR1_QSSEL 0x1 + + # Enables Read Data Strobe in a byte lane + # PSU_DDR_PHY_DX2GCR1_OEEN 0x1 + + # Enables PDR in a byte lane + # PSU_DDR_PHY_DX2GCR1_PDREN 0x1 + + # Enables ODT/TE in a byte lane + # PSU_DDR_PHY_DX2GCR1_TEEN 0x1 + + # Enables Write Data strobe in a byte lane + # PSU_DDR_PHY_DX2GCR1_DSEN 0x1 + + # Enables DM pin in a byte lane + # PSU_DDR_PHY_DX2GCR1_DMEN 0x1 + + # Enables DQ corresponding to each bit in a byte + # PSU_DDR_PHY_DX2GCR1_DQEN 0xff + + # DATX8 n General Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU) */ + mask_write 0XFD080904 0xFFFFFFFF 0x00007FFF + # Register : DX2GCR3 @ 0XFD08090C

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX2GCR3_RESERVED_31_30 0x0 + + # Read Data BDL VT Compensation + # PSU_DDR_PHY_DX2GCR3_RDBVT 0x1 + + # Write Data BDL VT Compensation + # PSU_DDR_PHY_DX2GCR3_WDBVT 0x1 + + # Read DQS Gating LCDL Delay VT Compensation + # PSU_DDR_PHY_DX2GCR3_RGLVT 0x1 + + # Read DQS LCDL Delay VT Compensation + # PSU_DDR_PHY_DX2GCR3_RDLVT 0x1 + + # Write DQ LCDL Delay VT Compensation + # PSU_DDR_PHY_DX2GCR3_WDLVT 0x1 + + # Write Leveling LCDL Delay VT Compensation + # PSU_DDR_PHY_DX2GCR3_WLLVT 0x1 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX2GCR3_RESERVED_23_22 0x0 + + # Enables the OE mode for DQs + # PSU_DDR_PHY_DX2GCR3_DSNOEMODE 0x0 + + # Enables the TE mode for DQS + # PSU_DDR_PHY_DX2GCR3_DSNTEMODE 0x0 + + # Enables the PDR mode for DQS + # PSU_DDR_PHY_DX2GCR3_DSNPDRMODE 0x0 + + # Enables the OE mode values for DM. + # PSU_DDR_PHY_DX2GCR3_DMOEMODE 0x0 + + # Enables the TE mode values for DM. + # PSU_DDR_PHY_DX2GCR3_DMTEMODE 0x0 + + # Enables the PDR mode values for DM. + # PSU_DDR_PHY_DX2GCR3_DMPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX2GCR3_RESERVED_9_8 0x0 + + # Enables the OE mode values for DQS. + # PSU_DDR_PHY_DX2GCR3_DSOEMODE 0x0 + + # Enables the TE mode values for DQS. + # PSU_DDR_PHY_DX2GCR3_DSTEMODE 0x0 + + # Enables the PDR mode values for DQS. + # PSU_DDR_PHY_DX2GCR3_DSPDRMODE 0x2 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX2GCR3_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 3 + #(OFFSET, MASK, VALUE) (0XFD08090C, 0xFFFFFFFFU ,0x3F000008U) */ + mask_write 0XFD08090C 0xFFFFFFFF 0x3F000008 + # Register : DX2GCR4 @ 0XFD080910

    + + # Byte lane VREF IOM (Used only by D4MU IOs) + # PSU_DDR_PHY_DX2GCR4_RESERVED_31_29 0x0 + + # Byte Lane VREF Pad Enable + # PSU_DDR_PHY_DX2GCR4_DXREFPEN 0x0 + + # Byte Lane Internal VREF Enable + # PSU_DDR_PHY_DX2GCR4_DXREFEEN 0x3 + + # Byte Lane Single-End VREF Enable + # PSU_DDR_PHY_DX2GCR4_DXREFSEN 0x1 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX2GCR4_RESERVED_24 0x0 + + # External VREF generator REFSEL range select + # PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE 0x0 + + # Byte Lane External VREF Select + # PSU_DDR_PHY_DX2GCR4_DXREFESEL 0x0 + + # Single ended VREF generator REFSEL range select + # PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE 0x1 + + # Byte Lane Single-End VREF Select + # PSU_DDR_PHY_DX2GCR4_DXREFSSEL 0x30 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX2GCR4_RESERVED_7_6 0x0 + + # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX2GCR4_DXREFIEN 0x1 + + # VRMON control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX2GCR4_DXREFIMON 0x0 + + # DATX8 n General Configuration Register 4 + #(OFFSET, MASK, VALUE) (0XFD080910, 0xFFFFFFFFU ,0x0E00B004U) */ + mask_write 0XFD080910 0xFFFFFFFF 0x0E00B004 + # Register : DX2GCR5 @ 0XFD080914

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX2GCR5_RESERVED_31 0x0 + + # Byte Lane internal VREF Select for Rank 3 + # PSU_DDR_PHY_DX2GCR5_DXREFISELR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX2GCR5_RESERVED_23 0x0 + + # Byte Lane internal VREF Select for Rank 2 + # PSU_DDR_PHY_DX2GCR5_DXREFISELR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0 + + # Byte Lane internal VREF Select for Rank 1 + # PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0 + + # Byte Lane internal VREF Select for Rank 0 + # PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55 + + # DATX8 n General Configuration Register 5 + #(OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080914 0xFFFFFFFF 0x09095555 + # Register : DX2GCR6 @ 0XFD080918

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX2GCR6_RESERVED_31_30 0x0 + + # DRAM DQ VREF Select for Rank3 + # PSU_DDR_PHY_DX2GCR6_DXDQVREFR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX2GCR6_RESERVED_23_22 0x0 + + # DRAM DQ VREF Select for Rank2 + # PSU_DDR_PHY_DX2GCR6_DXDQVREFR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX2GCR6_RESERVED_15_14 0x0 + + # DRAM DQ VREF Select for Rank1 + # PSU_DDR_PHY_DX2GCR6_DXDQVREFR1 0x2b + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX2GCR6_RESERVED_7_6 0x0 + + # DRAM DQ VREF Select for Rank0 + # PSU_DDR_PHY_DX2GCR6_DXDQVREFR0 0x2b + + # DATX8 n General Configuration Register 6 + #(OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU) */ + mask_write 0XFD080918 0xFFFFFFFF 0x09092B2B + # Register : DX3GCR0 @ 0XFD080A00

    + + # Calibration Bypass + # PSU_DDR_PHY_DX3GCR0_CALBYP 0x0 + + # Master Delay Line Enable + # PSU_DDR_PHY_DX3GCR0_MDLEN 0x1 + + # Configurable ODT(TE) Phase Shift + # PSU_DDR_PHY_DX3GCR0_CODTSHFT 0x0 + + # DQS Duty Cycle Correction + # PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0 + + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY + # PSU_DDR_PHY_DX3GCR0_RDDLY 0x8 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX3GCR0_RESERVED_19_14 0x0 + + # DQSNSE Power Down Receiver + # PSU_DDR_PHY_DX3GCR0_DQSNSEPDR 0x0 + + # DQSSE Power Down Receiver + # PSU_DDR_PHY_DX3GCR0_DQSSEPDR 0x0 + + # RTT On Additive Latency + # PSU_DDR_PHY_DX3GCR0_RTTOAL 0x0 + + # RTT Output Hold + # PSU_DDR_PHY_DX3GCR0_RTTOH 0x3 + + # Configurable PDR Phase Shift + # PSU_DDR_PHY_DX3GCR0_CPDRSHFT 0x0 + + # DQSR Power Down + # PSU_DDR_PHY_DX3GCR0_DQSRPD 0x0 + + # DQSG Power Down Receiver + # PSU_DDR_PHY_DX3GCR0_DQSGPDR 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX3GCR0_RESERVED_4 0x0 + + # DQSG On-Die Termination + # PSU_DDR_PHY_DX3GCR0_DQSGODT 0x0 + + # DQSG Output Enable + # PSU_DDR_PHY_DX3GCR0_DQSGOE 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX3GCR0_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD080A00, 0xFFFFFFFFU ,0x40800604U) */ + mask_write 0XFD080A00 0xFFFFFFFF 0x40800604 + # Register : DX3GCR1 @ 0XFD080A04

    + + # Enables the PDR mode for DQ[7:0] + # PSU_DDR_PHY_DX3GCR1_DXPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX3GCR1_RESERVED_15 0x0 + + # Select the delayed or non-delayed read data strobe # + # PSU_DDR_PHY_DX3GCR1_QSNSEL 0x1 + + # Select the delayed or non-delayed read data strobe + # PSU_DDR_PHY_DX3GCR1_QSSEL 0x1 + + # Enables Read Data Strobe in a byte lane + # PSU_DDR_PHY_DX3GCR1_OEEN 0x1 + + # Enables PDR in a byte lane + # PSU_DDR_PHY_DX3GCR1_PDREN 0x1 + + # Enables ODT/TE in a byte lane + # PSU_DDR_PHY_DX3GCR1_TEEN 0x1 + + # Enables Write Data strobe in a byte lane + # PSU_DDR_PHY_DX3GCR1_DSEN 0x1 + + # Enables DM pin in a byte lane + # PSU_DDR_PHY_DX3GCR1_DMEN 0x1 + + # Enables DQ corresponding to each bit in a byte + # PSU_DDR_PHY_DX3GCR1_DQEN 0xff + + # DATX8 n General Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU) */ + mask_write 0XFD080A04 0xFFFFFFFF 0x00007FFF + # Register : DX3GCR3 @ 0XFD080A0C

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX3GCR3_RESERVED_31_30 0x0 + + # Read Data BDL VT Compensation + # PSU_DDR_PHY_DX3GCR3_RDBVT 0x1 + + # Write Data BDL VT Compensation + # PSU_DDR_PHY_DX3GCR3_WDBVT 0x1 + + # Read DQS Gating LCDL Delay VT Compensation + # PSU_DDR_PHY_DX3GCR3_RGLVT 0x1 + + # Read DQS LCDL Delay VT Compensation + # PSU_DDR_PHY_DX3GCR3_RDLVT 0x1 + + # Write DQ LCDL Delay VT Compensation + # PSU_DDR_PHY_DX3GCR3_WDLVT 0x1 + + # Write Leveling LCDL Delay VT Compensation + # PSU_DDR_PHY_DX3GCR3_WLLVT 0x1 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX3GCR3_RESERVED_23_22 0x0 + + # Enables the OE mode for DQs + # PSU_DDR_PHY_DX3GCR3_DSNOEMODE 0x0 + + # Enables the TE mode for DQS + # PSU_DDR_PHY_DX3GCR3_DSNTEMODE 0x0 + + # Enables the PDR mode for DQS + # PSU_DDR_PHY_DX3GCR3_DSNPDRMODE 0x0 + + # Enables the OE mode values for DM. + # PSU_DDR_PHY_DX3GCR3_DMOEMODE 0x0 + + # Enables the TE mode values for DM. + # PSU_DDR_PHY_DX3GCR3_DMTEMODE 0x0 + + # Enables the PDR mode values for DM. + # PSU_DDR_PHY_DX3GCR3_DMPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX3GCR3_RESERVED_9_8 0x0 + + # Enables the OE mode values for DQS. + # PSU_DDR_PHY_DX3GCR3_DSOEMODE 0x0 + + # Enables the TE mode values for DQS. + # PSU_DDR_PHY_DX3GCR3_DSTEMODE 0x0 + + # Enables the PDR mode values for DQS. + # PSU_DDR_PHY_DX3GCR3_DSPDRMODE 0x2 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX3GCR3_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 3 + #(OFFSET, MASK, VALUE) (0XFD080A0C, 0xFFFFFFFFU ,0x3F000008U) */ + mask_write 0XFD080A0C 0xFFFFFFFF 0x3F000008 + # Register : DX3GCR4 @ 0XFD080A10

    + + # Byte lane VREF IOM (Used only by D4MU IOs) + # PSU_DDR_PHY_DX3GCR4_RESERVED_31_29 0x0 + + # Byte Lane VREF Pad Enable + # PSU_DDR_PHY_DX3GCR4_DXREFPEN 0x0 + + # Byte Lane Internal VREF Enable + # PSU_DDR_PHY_DX3GCR4_DXREFEEN 0x3 + + # Byte Lane Single-End VREF Enable + # PSU_DDR_PHY_DX3GCR4_DXREFSEN 0x1 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX3GCR4_RESERVED_24 0x0 + + # External VREF generator REFSEL range select + # PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE 0x0 + + # Byte Lane External VREF Select + # PSU_DDR_PHY_DX3GCR4_DXREFESEL 0x0 + + # Single ended VREF generator REFSEL range select + # PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE 0x1 + + # Byte Lane Single-End VREF Select + # PSU_DDR_PHY_DX3GCR4_DXREFSSEL 0x30 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX3GCR4_RESERVED_7_6 0x0 + + # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX3GCR4_DXREFIEN 0x1 + + # VRMON control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX3GCR4_DXREFIMON 0x0 + + # DATX8 n General Configuration Register 4 + #(OFFSET, MASK, VALUE) (0XFD080A10, 0xFFFFFFFFU ,0x0E00B004U) */ + mask_write 0XFD080A10 0xFFFFFFFF 0x0E00B004 + # Register : DX3GCR5 @ 0XFD080A14

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX3GCR5_RESERVED_31 0x0 + + # Byte Lane internal VREF Select for Rank 3 + # PSU_DDR_PHY_DX3GCR5_DXREFISELR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX3GCR5_RESERVED_23 0x0 + + # Byte Lane internal VREF Select for Rank 2 + # PSU_DDR_PHY_DX3GCR5_DXREFISELR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0 + + # Byte Lane internal VREF Select for Rank 1 + # PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0 + + # Byte Lane internal VREF Select for Rank 0 + # PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55 + + # DATX8 n General Configuration Register 5 + #(OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080A14 0xFFFFFFFF 0x09095555 + # Register : DX3GCR6 @ 0XFD080A18

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX3GCR6_RESERVED_31_30 0x0 + + # DRAM DQ VREF Select for Rank3 + # PSU_DDR_PHY_DX3GCR6_DXDQVREFR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX3GCR6_RESERVED_23_22 0x0 + + # DRAM DQ VREF Select for Rank2 + # PSU_DDR_PHY_DX3GCR6_DXDQVREFR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX3GCR6_RESERVED_15_14 0x0 + + # DRAM DQ VREF Select for Rank1 + # PSU_DDR_PHY_DX3GCR6_DXDQVREFR1 0x2b + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX3GCR6_RESERVED_7_6 0x0 + + # DRAM DQ VREF Select for Rank0 + # PSU_DDR_PHY_DX3GCR6_DXDQVREFR0 0x2b + + # DATX8 n General Configuration Register 6 + #(OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU) */ + mask_write 0XFD080A18 0xFFFFFFFF 0x09092B2B + # Register : DX4GCR0 @ 0XFD080B00

    + + # Calibration Bypass + # PSU_DDR_PHY_DX4GCR0_CALBYP 0x0 + + # Master Delay Line Enable + # PSU_DDR_PHY_DX4GCR0_MDLEN 0x1 + + # Configurable ODT(TE) Phase Shift + # PSU_DDR_PHY_DX4GCR0_CODTSHFT 0x0 + + # DQS Duty Cycle Correction + # PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0 + + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY + # PSU_DDR_PHY_DX4GCR0_RDDLY 0x8 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX4GCR0_RESERVED_19_14 0x0 + + # DQSNSE Power Down Receiver + # PSU_DDR_PHY_DX4GCR0_DQSNSEPDR 0x0 + + # DQSSE Power Down Receiver + # PSU_DDR_PHY_DX4GCR0_DQSSEPDR 0x0 + + # RTT On Additive Latency + # PSU_DDR_PHY_DX4GCR0_RTTOAL 0x0 + + # RTT Output Hold + # PSU_DDR_PHY_DX4GCR0_RTTOH 0x3 + + # Configurable PDR Phase Shift + # PSU_DDR_PHY_DX4GCR0_CPDRSHFT 0x0 + + # DQSR Power Down + # PSU_DDR_PHY_DX4GCR0_DQSRPD 0x0 + + # DQSG Power Down Receiver + # PSU_DDR_PHY_DX4GCR0_DQSGPDR 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX4GCR0_RESERVED_4 0x0 + + # DQSG On-Die Termination + # PSU_DDR_PHY_DX4GCR0_DQSGODT 0x0 + + # DQSG Output Enable + # PSU_DDR_PHY_DX4GCR0_DQSGOE 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX4GCR0_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD080B00, 0xFFFFFFFFU ,0x40800604U) */ + mask_write 0XFD080B00 0xFFFFFFFF 0x40800604 + # Register : DX4GCR1 @ 0XFD080B04

    + + # Enables the PDR mode for DQ[7:0] + # PSU_DDR_PHY_DX4GCR1_DXPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX4GCR1_RESERVED_15 0x0 + + # Select the delayed or non-delayed read data strobe # + # PSU_DDR_PHY_DX4GCR1_QSNSEL 0x1 + + # Select the delayed or non-delayed read data strobe + # PSU_DDR_PHY_DX4GCR1_QSSEL 0x1 + + # Enables Read Data Strobe in a byte lane + # PSU_DDR_PHY_DX4GCR1_OEEN 0x1 + + # Enables PDR in a byte lane + # PSU_DDR_PHY_DX4GCR1_PDREN 0x1 + + # Enables ODT/TE in a byte lane + # PSU_DDR_PHY_DX4GCR1_TEEN 0x1 + + # Enables Write Data strobe in a byte lane + # PSU_DDR_PHY_DX4GCR1_DSEN 0x1 + + # Enables DM pin in a byte lane + # PSU_DDR_PHY_DX4GCR1_DMEN 0x1 + + # Enables DQ corresponding to each bit in a byte + # PSU_DDR_PHY_DX4GCR1_DQEN 0xff + + # DATX8 n General Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU) */ + mask_write 0XFD080B04 0xFFFFFFFF 0x00007FFF + # Register : DX4GCR2 @ 0XFD080B08

    + + # Enables the OE mode values for DQ[7:0] + # PSU_DDR_PHY_DX4GCR2_DXOEMODE 0x0 + + # Enables the TE (ODT) mode values for DQ[7:0] + # PSU_DDR_PHY_DX4GCR2_DXTEMODE 0x0 + + # DATX8 n General Configuration Register 2 + #(OFFSET, MASK, VALUE) (0XFD080B08, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD080B08 0xFFFFFFFF 0x00000000 + # Register : DX4GCR3 @ 0XFD080B0C

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX4GCR3_RESERVED_31_30 0x0 + + # Read Data BDL VT Compensation + # PSU_DDR_PHY_DX4GCR3_RDBVT 0x1 + + # Write Data BDL VT Compensation + # PSU_DDR_PHY_DX4GCR3_WDBVT 0x1 + + # Read DQS Gating LCDL Delay VT Compensation + # PSU_DDR_PHY_DX4GCR3_RGLVT 0x1 + + # Read DQS LCDL Delay VT Compensation + # PSU_DDR_PHY_DX4GCR3_RDLVT 0x1 + + # Write DQ LCDL Delay VT Compensation + # PSU_DDR_PHY_DX4GCR3_WDLVT 0x1 + + # Write Leveling LCDL Delay VT Compensation + # PSU_DDR_PHY_DX4GCR3_WLLVT 0x1 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX4GCR3_RESERVED_23_22 0x0 + + # Enables the OE mode for DQs + # PSU_DDR_PHY_DX4GCR3_DSNOEMODE 0x0 + + # Enables the TE mode for DQS + # PSU_DDR_PHY_DX4GCR3_DSNTEMODE 0x0 + + # Enables the PDR mode for DQS + # PSU_DDR_PHY_DX4GCR3_DSNPDRMODE 0x0 + + # Enables the OE mode values for DM. + # PSU_DDR_PHY_DX4GCR3_DMOEMODE 0x0 + + # Enables the TE mode values for DM. + # PSU_DDR_PHY_DX4GCR3_DMTEMODE 0x0 + + # Enables the PDR mode values for DM. + # PSU_DDR_PHY_DX4GCR3_DMPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX4GCR3_RESERVED_9_8 0x0 + + # Enables the OE mode values for DQS. + # PSU_DDR_PHY_DX4GCR3_DSOEMODE 0x0 + + # Enables the TE mode values for DQS. + # PSU_DDR_PHY_DX4GCR3_DSTEMODE 0x0 + + # Enables the PDR mode values for DQS. + # PSU_DDR_PHY_DX4GCR3_DSPDRMODE 0x2 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX4GCR3_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 3 + #(OFFSET, MASK, VALUE) (0XFD080B0C, 0xFFFFFFFFU ,0x3F000008U) */ + mask_write 0XFD080B0C 0xFFFFFFFF 0x3F000008 + # Register : DX4GCR4 @ 0XFD080B10

    + + # Byte lane VREF IOM (Used only by D4MU IOs) + # PSU_DDR_PHY_DX4GCR4_RESERVED_31_29 0x0 + + # Byte Lane VREF Pad Enable + # PSU_DDR_PHY_DX4GCR4_DXREFPEN 0x0 + + # Byte Lane Internal VREF Enable + # PSU_DDR_PHY_DX4GCR4_DXREFEEN 0x3 + + # Byte Lane Single-End VREF Enable + # PSU_DDR_PHY_DX4GCR4_DXREFSEN 0x1 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX4GCR4_RESERVED_24 0x0 + + # External VREF generator REFSEL range select + # PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE 0x0 + + # Byte Lane External VREF Select + # PSU_DDR_PHY_DX4GCR4_DXREFESEL 0x0 + + # Single ended VREF generator REFSEL range select + # PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE 0x1 + + # Byte Lane Single-End VREF Select + # PSU_DDR_PHY_DX4GCR4_DXREFSSEL 0x30 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX4GCR4_RESERVED_7_6 0x0 + + # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX4GCR4_DXREFIEN 0x1 + + # VRMON control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX4GCR4_DXREFIMON 0x0 + + # DATX8 n General Configuration Register 4 + #(OFFSET, MASK, VALUE) (0XFD080B10, 0xFFFFFFFFU ,0x0E00B004U) */ + mask_write 0XFD080B10 0xFFFFFFFF 0x0E00B004 + # Register : DX4GCR5 @ 0XFD080B14

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX4GCR5_RESERVED_31 0x0 + + # Byte Lane internal VREF Select for Rank 3 + # PSU_DDR_PHY_DX4GCR5_DXREFISELR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX4GCR5_RESERVED_23 0x0 + + # Byte Lane internal VREF Select for Rank 2 + # PSU_DDR_PHY_DX4GCR5_DXREFISELR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0 + + # Byte Lane internal VREF Select for Rank 1 + # PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0 + + # Byte Lane internal VREF Select for Rank 0 + # PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55 + + # DATX8 n General Configuration Register 5 + #(OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080B14 0xFFFFFFFF 0x09095555 + # Register : DX4GCR6 @ 0XFD080B18

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX4GCR6_RESERVED_31_30 0x0 + + # DRAM DQ VREF Select for Rank3 + # PSU_DDR_PHY_DX4GCR6_DXDQVREFR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX4GCR6_RESERVED_23_22 0x0 + + # DRAM DQ VREF Select for Rank2 + # PSU_DDR_PHY_DX4GCR6_DXDQVREFR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX4GCR6_RESERVED_15_14 0x0 + + # DRAM DQ VREF Select for Rank1 + # PSU_DDR_PHY_DX4GCR6_DXDQVREFR1 0x2b + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX4GCR6_RESERVED_7_6 0x0 + + # DRAM DQ VREF Select for Rank0 + # PSU_DDR_PHY_DX4GCR6_DXDQVREFR0 0x2b + + # DATX8 n General Configuration Register 6 + #(OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU) */ + mask_write 0XFD080B18 0xFFFFFFFF 0x09092B2B + # Register : DX5GCR0 @ 0XFD080C00

    + + # Calibration Bypass + # PSU_DDR_PHY_DX5GCR0_CALBYP 0x0 + + # Master Delay Line Enable + # PSU_DDR_PHY_DX5GCR0_MDLEN 0x1 + + # Configurable ODT(TE) Phase Shift + # PSU_DDR_PHY_DX5GCR0_CODTSHFT 0x0 + + # DQS Duty Cycle Correction + # PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0 + + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY + # PSU_DDR_PHY_DX5GCR0_RDDLY 0x8 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX5GCR0_RESERVED_19_14 0x0 + + # DQSNSE Power Down Receiver + # PSU_DDR_PHY_DX5GCR0_DQSNSEPDR 0x0 + + # DQSSE Power Down Receiver + # PSU_DDR_PHY_DX5GCR0_DQSSEPDR 0x0 + + # RTT On Additive Latency + # PSU_DDR_PHY_DX5GCR0_RTTOAL 0x0 + + # RTT Output Hold + # PSU_DDR_PHY_DX5GCR0_RTTOH 0x3 + + # Configurable PDR Phase Shift + # PSU_DDR_PHY_DX5GCR0_CPDRSHFT 0x0 + + # DQSR Power Down + # PSU_DDR_PHY_DX5GCR0_DQSRPD 0x0 + + # DQSG Power Down Receiver + # PSU_DDR_PHY_DX5GCR0_DQSGPDR 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX5GCR0_RESERVED_4 0x0 + + # DQSG On-Die Termination + # PSU_DDR_PHY_DX5GCR0_DQSGODT 0x0 + + # DQSG Output Enable + # PSU_DDR_PHY_DX5GCR0_DQSGOE 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX5GCR0_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD080C00, 0xFFFFFFFFU ,0x40800604U) */ + mask_write 0XFD080C00 0xFFFFFFFF 0x40800604 + # Register : DX5GCR1 @ 0XFD080C04

    + + # Enables the PDR mode for DQ[7:0] + # PSU_DDR_PHY_DX5GCR1_DXPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX5GCR1_RESERVED_15 0x0 + + # Select the delayed or non-delayed read data strobe # + # PSU_DDR_PHY_DX5GCR1_QSNSEL 0x1 + + # Select the delayed or non-delayed read data strobe + # PSU_DDR_PHY_DX5GCR1_QSSEL 0x1 + + # Enables Read Data Strobe in a byte lane + # PSU_DDR_PHY_DX5GCR1_OEEN 0x1 + + # Enables PDR in a byte lane + # PSU_DDR_PHY_DX5GCR1_PDREN 0x1 + + # Enables ODT/TE in a byte lane + # PSU_DDR_PHY_DX5GCR1_TEEN 0x1 + + # Enables Write Data strobe in a byte lane + # PSU_DDR_PHY_DX5GCR1_DSEN 0x1 + + # Enables DM pin in a byte lane + # PSU_DDR_PHY_DX5GCR1_DMEN 0x1 + + # Enables DQ corresponding to each bit in a byte + # PSU_DDR_PHY_DX5GCR1_DQEN 0xff + + # DATX8 n General Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU) */ + mask_write 0XFD080C04 0xFFFFFFFF 0x00007FFF + # Register : DX5GCR2 @ 0XFD080C08

    + + # Enables the OE mode values for DQ[7:0] + # PSU_DDR_PHY_DX5GCR2_DXOEMODE 0x0 + + # Enables the TE (ODT) mode values for DQ[7:0] + # PSU_DDR_PHY_DX5GCR2_DXTEMODE 0x0 + + # DATX8 n General Configuration Register 2 + #(OFFSET, MASK, VALUE) (0XFD080C08, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD080C08 0xFFFFFFFF 0x00000000 + # Register : DX5GCR3 @ 0XFD080C0C

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX5GCR3_RESERVED_31_30 0x0 + + # Read Data BDL VT Compensation + # PSU_DDR_PHY_DX5GCR3_RDBVT 0x1 + + # Write Data BDL VT Compensation + # PSU_DDR_PHY_DX5GCR3_WDBVT 0x1 + + # Read DQS Gating LCDL Delay VT Compensation + # PSU_DDR_PHY_DX5GCR3_RGLVT 0x1 + + # Read DQS LCDL Delay VT Compensation + # PSU_DDR_PHY_DX5GCR3_RDLVT 0x1 + + # Write DQ LCDL Delay VT Compensation + # PSU_DDR_PHY_DX5GCR3_WDLVT 0x1 + + # Write Leveling LCDL Delay VT Compensation + # PSU_DDR_PHY_DX5GCR3_WLLVT 0x1 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX5GCR3_RESERVED_23_22 0x0 + + # Enables the OE mode for DQs + # PSU_DDR_PHY_DX5GCR3_DSNOEMODE 0x0 + + # Enables the TE mode for DQS + # PSU_DDR_PHY_DX5GCR3_DSNTEMODE 0x0 + + # Enables the PDR mode for DQS + # PSU_DDR_PHY_DX5GCR3_DSNPDRMODE 0x0 + + # Enables the OE mode values for DM. + # PSU_DDR_PHY_DX5GCR3_DMOEMODE 0x0 + + # Enables the TE mode values for DM. + # PSU_DDR_PHY_DX5GCR3_DMTEMODE 0x0 + + # Enables the PDR mode values for DM. + # PSU_DDR_PHY_DX5GCR3_DMPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX5GCR3_RESERVED_9_8 0x0 + + # Enables the OE mode values for DQS. + # PSU_DDR_PHY_DX5GCR3_DSOEMODE 0x0 + + # Enables the TE mode values for DQS. + # PSU_DDR_PHY_DX5GCR3_DSTEMODE 0x0 + + # Enables the PDR mode values for DQS. + # PSU_DDR_PHY_DX5GCR3_DSPDRMODE 0x2 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX5GCR3_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 3 + #(OFFSET, MASK, VALUE) (0XFD080C0C, 0xFFFFFFFFU ,0x3F000008U) */ + mask_write 0XFD080C0C 0xFFFFFFFF 0x3F000008 + # Register : DX5GCR4 @ 0XFD080C10

    + + # Byte lane VREF IOM (Used only by D4MU IOs) + # PSU_DDR_PHY_DX5GCR4_RESERVED_31_29 0x0 + + # Byte Lane VREF Pad Enable + # PSU_DDR_PHY_DX5GCR4_DXREFPEN 0x0 + + # Byte Lane Internal VREF Enable + # PSU_DDR_PHY_DX5GCR4_DXREFEEN 0x3 + + # Byte Lane Single-End VREF Enable + # PSU_DDR_PHY_DX5GCR4_DXREFSEN 0x1 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX5GCR4_RESERVED_24 0x0 + + # External VREF generator REFSEL range select + # PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE 0x0 + + # Byte Lane External VREF Select + # PSU_DDR_PHY_DX5GCR4_DXREFESEL 0x0 + + # Single ended VREF generator REFSEL range select + # PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE 0x1 + + # Byte Lane Single-End VREF Select + # PSU_DDR_PHY_DX5GCR4_DXREFSSEL 0x30 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX5GCR4_RESERVED_7_6 0x0 + + # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX5GCR4_DXREFIEN 0xf + + # VRMON control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX5GCR4_DXREFIMON 0x0 + + # DATX8 n General Configuration Register 4 + #(OFFSET, MASK, VALUE) (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU) */ + mask_write 0XFD080C10 0xFFFFFFFF 0x0E00B03C + # Register : DX5GCR5 @ 0XFD080C14

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX5GCR5_RESERVED_31 0x0 + + # Byte Lane internal VREF Select for Rank 3 + # PSU_DDR_PHY_DX5GCR5_DXREFISELR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX5GCR5_RESERVED_23 0x0 + + # Byte Lane internal VREF Select for Rank 2 + # PSU_DDR_PHY_DX5GCR5_DXREFISELR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0 + + # Byte Lane internal VREF Select for Rank 1 + # PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0 + + # Byte Lane internal VREF Select for Rank 0 + # PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55 + + # DATX8 n General Configuration Register 5 + #(OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080C14 0xFFFFFFFF 0x09095555 + # Register : DX5GCR6 @ 0XFD080C18

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX5GCR6_RESERVED_31_30 0x0 + + # DRAM DQ VREF Select for Rank3 + # PSU_DDR_PHY_DX5GCR6_DXDQVREFR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX5GCR6_RESERVED_23_22 0x0 + + # DRAM DQ VREF Select for Rank2 + # PSU_DDR_PHY_DX5GCR6_DXDQVREFR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX5GCR6_RESERVED_15_14 0x0 + + # DRAM DQ VREF Select for Rank1 + # PSU_DDR_PHY_DX5GCR6_DXDQVREFR1 0x2b + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX5GCR6_RESERVED_7_6 0x0 + + # DRAM DQ VREF Select for Rank0 + # PSU_DDR_PHY_DX5GCR6_DXDQVREFR0 0x2b + + # DATX8 n General Configuration Register 6 + #(OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU) */ + mask_write 0XFD080C18 0xFFFFFFFF 0x09092B2B + # Register : DX6GCR0 @ 0XFD080D00

    + + # Calibration Bypass + # PSU_DDR_PHY_DX6GCR0_CALBYP 0x0 + + # Master Delay Line Enable + # PSU_DDR_PHY_DX6GCR0_MDLEN 0x1 + + # Configurable ODT(TE) Phase Shift + # PSU_DDR_PHY_DX6GCR0_CODTSHFT 0x0 + + # DQS Duty Cycle Correction + # PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0 + + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY + # PSU_DDR_PHY_DX6GCR0_RDDLY 0x8 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX6GCR0_RESERVED_19_14 0x0 + + # DQSNSE Power Down Receiver + # PSU_DDR_PHY_DX6GCR0_DQSNSEPDR 0x0 + + # DQSSE Power Down Receiver + # PSU_DDR_PHY_DX6GCR0_DQSSEPDR 0x0 + + # RTT On Additive Latency + # PSU_DDR_PHY_DX6GCR0_RTTOAL 0x0 + + # RTT Output Hold + # PSU_DDR_PHY_DX6GCR0_RTTOH 0x3 + + # Configurable PDR Phase Shift + # PSU_DDR_PHY_DX6GCR0_CPDRSHFT 0x0 + + # DQSR Power Down + # PSU_DDR_PHY_DX6GCR0_DQSRPD 0x0 + + # DQSG Power Down Receiver + # PSU_DDR_PHY_DX6GCR0_DQSGPDR 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX6GCR0_RESERVED_4 0x0 + + # DQSG On-Die Termination + # PSU_DDR_PHY_DX6GCR0_DQSGODT 0x0 + + # DQSG Output Enable + # PSU_DDR_PHY_DX6GCR0_DQSGOE 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX6GCR0_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD080D00, 0xFFFFFFFFU ,0x40800604U) */ + mask_write 0XFD080D00 0xFFFFFFFF 0x40800604 + # Register : DX6GCR1 @ 0XFD080D04

    + + # Enables the PDR mode for DQ[7:0] + # PSU_DDR_PHY_DX6GCR1_DXPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX6GCR1_RESERVED_15 0x0 + + # Select the delayed or non-delayed read data strobe # + # PSU_DDR_PHY_DX6GCR1_QSNSEL 0x1 + + # Select the delayed or non-delayed read data strobe + # PSU_DDR_PHY_DX6GCR1_QSSEL 0x1 + + # Enables Read Data Strobe in a byte lane + # PSU_DDR_PHY_DX6GCR1_OEEN 0x1 + + # Enables PDR in a byte lane + # PSU_DDR_PHY_DX6GCR1_PDREN 0x1 + + # Enables ODT/TE in a byte lane + # PSU_DDR_PHY_DX6GCR1_TEEN 0x1 + + # Enables Write Data strobe in a byte lane + # PSU_DDR_PHY_DX6GCR1_DSEN 0x1 + + # Enables DM pin in a byte lane + # PSU_DDR_PHY_DX6GCR1_DMEN 0x1 + + # Enables DQ corresponding to each bit in a byte + # PSU_DDR_PHY_DX6GCR1_DQEN 0xff + + # DATX8 n General Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU) */ + mask_write 0XFD080D04 0xFFFFFFFF 0x00007FFF + # Register : DX6GCR2 @ 0XFD080D08

    + + # Enables the OE mode values for DQ[7:0] + # PSU_DDR_PHY_DX6GCR2_DXOEMODE 0x0 + + # Enables the TE (ODT) mode values for DQ[7:0] + # PSU_DDR_PHY_DX6GCR2_DXTEMODE 0x0 + + # DATX8 n General Configuration Register 2 + #(OFFSET, MASK, VALUE) (0XFD080D08, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD080D08 0xFFFFFFFF 0x00000000 + # Register : DX6GCR3 @ 0XFD080D0C

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX6GCR3_RESERVED_31_30 0x0 + + # Read Data BDL VT Compensation + # PSU_DDR_PHY_DX6GCR3_RDBVT 0x1 + + # Write Data BDL VT Compensation + # PSU_DDR_PHY_DX6GCR3_WDBVT 0x1 + + # Read DQS Gating LCDL Delay VT Compensation + # PSU_DDR_PHY_DX6GCR3_RGLVT 0x1 + + # Read DQS LCDL Delay VT Compensation + # PSU_DDR_PHY_DX6GCR3_RDLVT 0x1 + + # Write DQ LCDL Delay VT Compensation + # PSU_DDR_PHY_DX6GCR3_WDLVT 0x1 + + # Write Leveling LCDL Delay VT Compensation + # PSU_DDR_PHY_DX6GCR3_WLLVT 0x1 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX6GCR3_RESERVED_23_22 0x0 + + # Enables the OE mode for DQs + # PSU_DDR_PHY_DX6GCR3_DSNOEMODE 0x0 + + # Enables the TE mode for DQS + # PSU_DDR_PHY_DX6GCR3_DSNTEMODE 0x0 + + # Enables the PDR mode for DQS + # PSU_DDR_PHY_DX6GCR3_DSNPDRMODE 0x0 + + # Enables the OE mode values for DM. + # PSU_DDR_PHY_DX6GCR3_DMOEMODE 0x0 + + # Enables the TE mode values for DM. + # PSU_DDR_PHY_DX6GCR3_DMTEMODE 0x0 + + # Enables the PDR mode values for DM. + # PSU_DDR_PHY_DX6GCR3_DMPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX6GCR3_RESERVED_9_8 0x0 + + # Enables the OE mode values for DQS. + # PSU_DDR_PHY_DX6GCR3_DSOEMODE 0x0 + + # Enables the TE mode values for DQS. + # PSU_DDR_PHY_DX6GCR3_DSTEMODE 0x0 + + # Enables the PDR mode values for DQS. + # PSU_DDR_PHY_DX6GCR3_DSPDRMODE 0x2 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX6GCR3_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 3 + #(OFFSET, MASK, VALUE) (0XFD080D0C, 0xFFFFFFFFU ,0x3F000008U) */ + mask_write 0XFD080D0C 0xFFFFFFFF 0x3F000008 + # Register : DX6GCR4 @ 0XFD080D10

    + + # Byte lane VREF IOM (Used only by D4MU IOs) + # PSU_DDR_PHY_DX6GCR4_RESERVED_31_29 0x0 + + # Byte Lane VREF Pad Enable + # PSU_DDR_PHY_DX6GCR4_DXREFPEN 0x0 + + # Byte Lane Internal VREF Enable + # PSU_DDR_PHY_DX6GCR4_DXREFEEN 0x3 + + # Byte Lane Single-End VREF Enable + # PSU_DDR_PHY_DX6GCR4_DXREFSEN 0x1 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX6GCR4_RESERVED_24 0x0 + + # External VREF generator REFSEL range select + # PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE 0x0 + + # Byte Lane External VREF Select + # PSU_DDR_PHY_DX6GCR4_DXREFESEL 0x0 + + # Single ended VREF generator REFSEL range select + # PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE 0x1 + + # Byte Lane Single-End VREF Select + # PSU_DDR_PHY_DX6GCR4_DXREFSSEL 0x30 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX6GCR4_RESERVED_7_6 0x0 + + # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX6GCR4_DXREFIEN 0x1 + + # VRMON control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX6GCR4_DXREFIMON 0x0 + + # DATX8 n General Configuration Register 4 + #(OFFSET, MASK, VALUE) (0XFD080D10, 0xFFFFFFFFU ,0x0E00B004U) */ + mask_write 0XFD080D10 0xFFFFFFFF 0x0E00B004 + # Register : DX6GCR5 @ 0XFD080D14

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX6GCR5_RESERVED_31 0x0 + + # Byte Lane internal VREF Select for Rank 3 + # PSU_DDR_PHY_DX6GCR5_DXREFISELR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX6GCR5_RESERVED_23 0x0 + + # Byte Lane internal VREF Select for Rank 2 + # PSU_DDR_PHY_DX6GCR5_DXREFISELR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0 + + # Byte Lane internal VREF Select for Rank 1 + # PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0 + + # Byte Lane internal VREF Select for Rank 0 + # PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55 + + # DATX8 n General Configuration Register 5 + #(OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080D14 0xFFFFFFFF 0x09095555 + # Register : DX6GCR6 @ 0XFD080D18

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX6GCR6_RESERVED_31_30 0x0 + + # DRAM DQ VREF Select for Rank3 + # PSU_DDR_PHY_DX6GCR6_DXDQVREFR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX6GCR6_RESERVED_23_22 0x0 + + # DRAM DQ VREF Select for Rank2 + # PSU_DDR_PHY_DX6GCR6_DXDQVREFR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX6GCR6_RESERVED_15_14 0x0 + + # DRAM DQ VREF Select for Rank1 + # PSU_DDR_PHY_DX6GCR6_DXDQVREFR1 0x2b + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX6GCR6_RESERVED_7_6 0x0 + + # DRAM DQ VREF Select for Rank0 + # PSU_DDR_PHY_DX6GCR6_DXDQVREFR0 0x2b + + # DATX8 n General Configuration Register 6 + #(OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU) */ + mask_write 0XFD080D18 0xFFFFFFFF 0x09092B2B + # Register : DX7GCR0 @ 0XFD080E00

    + + # Calibration Bypass + # PSU_DDR_PHY_DX7GCR0_CALBYP 0x0 + + # Master Delay Line Enable + # PSU_DDR_PHY_DX7GCR0_MDLEN 0x1 + + # Configurable ODT(TE) Phase Shift + # PSU_DDR_PHY_DX7GCR0_CODTSHFT 0x0 + + # DQS Duty Cycle Correction + # PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0 + + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY + # PSU_DDR_PHY_DX7GCR0_RDDLY 0x8 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX7GCR0_RESERVED_19_14 0x0 + + # DQSNSE Power Down Receiver + # PSU_DDR_PHY_DX7GCR0_DQSNSEPDR 0x0 + + # DQSSE Power Down Receiver + # PSU_DDR_PHY_DX7GCR0_DQSSEPDR 0x0 + + # RTT On Additive Latency + # PSU_DDR_PHY_DX7GCR0_RTTOAL 0x0 + + # RTT Output Hold + # PSU_DDR_PHY_DX7GCR0_RTTOH 0x3 + + # Configurable PDR Phase Shift + # PSU_DDR_PHY_DX7GCR0_CPDRSHFT 0x0 + + # DQSR Power Down + # PSU_DDR_PHY_DX7GCR0_DQSRPD 0x0 + + # DQSG Power Down Receiver + # PSU_DDR_PHY_DX7GCR0_DQSGPDR 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX7GCR0_RESERVED_4 0x0 + + # DQSG On-Die Termination + # PSU_DDR_PHY_DX7GCR0_DQSGODT 0x0 + + # DQSG Output Enable + # PSU_DDR_PHY_DX7GCR0_DQSGOE 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX7GCR0_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD080E00, 0xFFFFFFFFU ,0x40800604U) */ + mask_write 0XFD080E00 0xFFFFFFFF 0x40800604 + # Register : DX7GCR1 @ 0XFD080E04

    + + # Enables the PDR mode for DQ[7:0] + # PSU_DDR_PHY_DX7GCR1_DXPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX7GCR1_RESERVED_15 0x0 + + # Select the delayed or non-delayed read data strobe # + # PSU_DDR_PHY_DX7GCR1_QSNSEL 0x1 + + # Select the delayed or non-delayed read data strobe + # PSU_DDR_PHY_DX7GCR1_QSSEL 0x1 + + # Enables Read Data Strobe in a byte lane + # PSU_DDR_PHY_DX7GCR1_OEEN 0x1 + + # Enables PDR in a byte lane + # PSU_DDR_PHY_DX7GCR1_PDREN 0x1 + + # Enables ODT/TE in a byte lane + # PSU_DDR_PHY_DX7GCR1_TEEN 0x1 + + # Enables Write Data strobe in a byte lane + # PSU_DDR_PHY_DX7GCR1_DSEN 0x1 + + # Enables DM pin in a byte lane + # PSU_DDR_PHY_DX7GCR1_DMEN 0x1 + + # Enables DQ corresponding to each bit in a byte + # PSU_DDR_PHY_DX7GCR1_DQEN 0xff + + # DATX8 n General Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU) */ + mask_write 0XFD080E04 0xFFFFFFFF 0x00007FFF + # Register : DX7GCR2 @ 0XFD080E08

    + + # Enables the OE mode values for DQ[7:0] + # PSU_DDR_PHY_DX7GCR2_DXOEMODE 0x0 + + # Enables the TE (ODT) mode values for DQ[7:0] + # PSU_DDR_PHY_DX7GCR2_DXTEMODE 0x0 + + # DATX8 n General Configuration Register 2 + #(OFFSET, MASK, VALUE) (0XFD080E08, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD080E08 0xFFFFFFFF 0x00000000 + # Register : DX7GCR3 @ 0XFD080E0C

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX7GCR3_RESERVED_31_30 0x0 + + # Read Data BDL VT Compensation + # PSU_DDR_PHY_DX7GCR3_RDBVT 0x1 + + # Write Data BDL VT Compensation + # PSU_DDR_PHY_DX7GCR3_WDBVT 0x1 + + # Read DQS Gating LCDL Delay VT Compensation + # PSU_DDR_PHY_DX7GCR3_RGLVT 0x1 + + # Read DQS LCDL Delay VT Compensation + # PSU_DDR_PHY_DX7GCR3_RDLVT 0x1 + + # Write DQ LCDL Delay VT Compensation + # PSU_DDR_PHY_DX7GCR3_WDLVT 0x1 + + # Write Leveling LCDL Delay VT Compensation + # PSU_DDR_PHY_DX7GCR3_WLLVT 0x1 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX7GCR3_RESERVED_23_22 0x0 + + # Enables the OE mode for DQs + # PSU_DDR_PHY_DX7GCR3_DSNOEMODE 0x0 + + # Enables the TE mode for DQS + # PSU_DDR_PHY_DX7GCR3_DSNTEMODE 0x0 + + # Enables the PDR mode for DQS + # PSU_DDR_PHY_DX7GCR3_DSNPDRMODE 0x0 + + # Enables the OE mode values for DM. + # PSU_DDR_PHY_DX7GCR3_DMOEMODE 0x0 + + # Enables the TE mode values for DM. + # PSU_DDR_PHY_DX7GCR3_DMTEMODE 0x0 + + # Enables the PDR mode values for DM. + # PSU_DDR_PHY_DX7GCR3_DMPDRMODE 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX7GCR3_RESERVED_9_8 0x0 + + # Enables the OE mode values for DQS. + # PSU_DDR_PHY_DX7GCR3_DSOEMODE 0x0 + + # Enables the TE mode values for DQS. + # PSU_DDR_PHY_DX7GCR3_DSTEMODE 0x0 + + # Enables the PDR mode values for DQS. + # PSU_DDR_PHY_DX7GCR3_DSPDRMODE 0x2 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX7GCR3_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 3 + #(OFFSET, MASK, VALUE) (0XFD080E0C, 0xFFFFFFFFU ,0x3F000008U) */ + mask_write 0XFD080E0C 0xFFFFFFFF 0x3F000008 + # Register : DX7GCR4 @ 0XFD080E10

    + + # Byte lane VREF IOM (Used only by D4MU IOs) + # PSU_DDR_PHY_DX7GCR4_RESERVED_31_29 0x0 + + # Byte Lane VREF Pad Enable + # PSU_DDR_PHY_DX7GCR4_DXREFPEN 0x0 + + # Byte Lane Internal VREF Enable + # PSU_DDR_PHY_DX7GCR4_DXREFEEN 0x3 + + # Byte Lane Single-End VREF Enable + # PSU_DDR_PHY_DX7GCR4_DXREFSEN 0x1 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX7GCR4_RESERVED_24 0x0 + + # External VREF generator REFSEL range select + # PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE 0x0 + + # Byte Lane External VREF Select + # PSU_DDR_PHY_DX7GCR4_DXREFESEL 0x0 + + # Single ended VREF generator REFSEL range select + # PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE 0x1 + + # Byte Lane Single-End VREF Select + # PSU_DDR_PHY_DX7GCR4_DXREFSSEL 0x30 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX7GCR4_RESERVED_7_6 0x0 + + # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX7GCR4_DXREFIEN 0xf + + # VRMON control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX7GCR4_DXREFIMON 0x0 + + # DATX8 n General Configuration Register 4 + #(OFFSET, MASK, VALUE) (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU) */ + mask_write 0XFD080E10 0xFFFFFFFF 0x0E00B03C + # Register : DX7GCR5 @ 0XFD080E14

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX7GCR5_RESERVED_31 0x0 + + # Byte Lane internal VREF Select for Rank 3 + # PSU_DDR_PHY_DX7GCR5_DXREFISELR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX7GCR5_RESERVED_23 0x0 + + # Byte Lane internal VREF Select for Rank 2 + # PSU_DDR_PHY_DX7GCR5_DXREFISELR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0 + + # Byte Lane internal VREF Select for Rank 1 + # PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0 + + # Byte Lane internal VREF Select for Rank 0 + # PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55 + + # DATX8 n General Configuration Register 5 + #(OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080E14 0xFFFFFFFF 0x09095555 + # Register : DX7GCR6 @ 0XFD080E18

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX7GCR6_RESERVED_31_30 0x0 + + # DRAM DQ VREF Select for Rank3 + # PSU_DDR_PHY_DX7GCR6_DXDQVREFR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX7GCR6_RESERVED_23_22 0x0 + + # DRAM DQ VREF Select for Rank2 + # PSU_DDR_PHY_DX7GCR6_DXDQVREFR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX7GCR6_RESERVED_15_14 0x0 + + # DRAM DQ VREF Select for Rank1 + # PSU_DDR_PHY_DX7GCR6_DXDQVREFR1 0x2b + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX7GCR6_RESERVED_7_6 0x0 + + # DRAM DQ VREF Select for Rank0 + # PSU_DDR_PHY_DX7GCR6_DXDQVREFR0 0x2b + + # DATX8 n General Configuration Register 6 + #(OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU) */ + mask_write 0XFD080E18 0xFFFFFFFF 0x09092B2B + # Register : DX8GCR0 @ 0XFD080F00

    + + # Calibration Bypass + # PSU_DDR_PHY_DX8GCR0_CALBYP 0x1 + + # Master Delay Line Enable + # PSU_DDR_PHY_DX8GCR0_MDLEN 0x0 + + # Configurable ODT(TE) Phase Shift + # PSU_DDR_PHY_DX8GCR0_CODTSHFT 0x0 + + # DQS Duty Cycle Correction + # PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0 + + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY + # PSU_DDR_PHY_DX8GCR0_RDDLY 0x8 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8GCR0_RESERVED_19_14 0x0 + + # DQSNSE Power Down Receiver + # PSU_DDR_PHY_DX8GCR0_DQSNSEPDR 0x1 + + # DQSSE Power Down Receiver + # PSU_DDR_PHY_DX8GCR0_DQSSEPDR 0x1 + + # RTT On Additive Latency + # PSU_DDR_PHY_DX8GCR0_RTTOAL 0x0 + + # RTT Output Hold + # PSU_DDR_PHY_DX8GCR0_RTTOH 0x3 + + # Configurable PDR Phase Shift + # PSU_DDR_PHY_DX8GCR0_CPDRSHFT 0x0 + + # DQSR Power Down + # PSU_DDR_PHY_DX8GCR0_DQSRPD 0x1 + + # DQSG Power Down Receiver + # PSU_DDR_PHY_DX8GCR0_DQSGPDR 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8GCR0_RESERVED_4 0x0 + + # DQSG On-Die Termination + # PSU_DDR_PHY_DX8GCR0_DQSGODT 0x0 + + # DQSG Output Enable + # PSU_DDR_PHY_DX8GCR0_DQSGOE 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8GCR0_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD080F00, 0xFFFFFFFFU ,0x80803660U) */ + mask_write 0XFD080F00 0xFFFFFFFF 0x80803660 + # Register : DX8GCR1 @ 0XFD080F04

    + + # Enables the PDR mode for DQ[7:0] + # PSU_DDR_PHY_DX8GCR1_DXPDRMODE 0x5555 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX8GCR1_RESERVED_15 0x0 + + # Select the delayed or non-delayed read data strobe # + # PSU_DDR_PHY_DX8GCR1_QSNSEL 0x1 + + # Select the delayed or non-delayed read data strobe + # PSU_DDR_PHY_DX8GCR1_QSSEL 0x1 + + # Enables Read Data Strobe in a byte lane + # PSU_DDR_PHY_DX8GCR1_OEEN 0x0 + + # Enables PDR in a byte lane + # PSU_DDR_PHY_DX8GCR1_PDREN 0x0 + + # Enables ODT/TE in a byte lane + # PSU_DDR_PHY_DX8GCR1_TEEN 0x0 + + # Enables Write Data strobe in a byte lane + # PSU_DDR_PHY_DX8GCR1_DSEN 0x0 + + # Enables DM pin in a byte lane + # PSU_DDR_PHY_DX8GCR1_DMEN 0x0 + + # Enables DQ corresponding to each bit in a byte + # PSU_DDR_PHY_DX8GCR1_DQEN 0x0 + + # DATX8 n General Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD080F04, 0xFFFFFFFFU ,0x55556000U) */ + mask_write 0XFD080F04 0xFFFFFFFF 0x55556000 + # Register : DX8GCR2 @ 0XFD080F08

    + + # Enables the OE mode values for DQ[7:0] + # PSU_DDR_PHY_DX8GCR2_DXOEMODE 0xaaaa + + # Enables the TE (ODT) mode values for DQ[7:0] + # PSU_DDR_PHY_DX8GCR2_DXTEMODE 0xaaaa + + # DATX8 n General Configuration Register 2 + #(OFFSET, MASK, VALUE) (0XFD080F08, 0xFFFFFFFFU ,0xAAAAAAAAU) */ + mask_write 0XFD080F08 0xFFFFFFFF 0xAAAAAAAA + # Register : DX8GCR3 @ 0XFD080F0C

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX8GCR3_RESERVED_31_30 0x0 + + # Read Data BDL VT Compensation + # PSU_DDR_PHY_DX8GCR3_RDBVT 0x0 + + # Write Data BDL VT Compensation + # PSU_DDR_PHY_DX8GCR3_WDBVT 0x0 + + # Read DQS Gating LCDL Delay VT Compensation + # PSU_DDR_PHY_DX8GCR3_RGLVT 0x0 + + # Read DQS LCDL Delay VT Compensation + # PSU_DDR_PHY_DX8GCR3_RDLVT 0x0 + + # Write DQ LCDL Delay VT Compensation + # PSU_DDR_PHY_DX8GCR3_WDLVT 0x0 + + # Write Leveling LCDL Delay VT Compensation + # PSU_DDR_PHY_DX8GCR3_WLLVT 0x0 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX8GCR3_RESERVED_23_22 0x0 + + # Enables the OE mode for DQs + # PSU_DDR_PHY_DX8GCR3_DSNOEMODE 0x2 + + # Enables the TE mode for DQS + # PSU_DDR_PHY_DX8GCR3_DSNTEMODE 0x2 + + # Enables the PDR mode for DQS + # PSU_DDR_PHY_DX8GCR3_DSNPDRMODE 0x1 + + # Enables the OE mode values for DM. + # PSU_DDR_PHY_DX8GCR3_DMOEMODE 0x2 + + # Enables the TE mode values for DM. + # PSU_DDR_PHY_DX8GCR3_DMTEMODE 0x2 + + # Enables the PDR mode values for DM. + # PSU_DDR_PHY_DX8GCR3_DMPDRMODE 0x1 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX8GCR3_RESERVED_9_8 0x0 + + # Enables the OE mode values for DQS. + # PSU_DDR_PHY_DX8GCR3_DSOEMODE 0x2 + + # Enables the TE mode values for DQS. + # PSU_DDR_PHY_DX8GCR3_DSTEMODE 0x2 + + # Enables the PDR mode values for DQS. + # PSU_DDR_PHY_DX8GCR3_DSPDRMODE 0x1 + + # Reserved. Returns zeroes on reads. + # PSU_DDR_PHY_DX8GCR3_RESERVED_1_0 0x0 + + # DATX8 n General Configuration Register 3 + #(OFFSET, MASK, VALUE) (0XFD080F0C, 0xFFFFFFFFU ,0x0029A4A4U) */ + mask_write 0XFD080F0C 0xFFFFFFFF 0x0029A4A4 + # Register : DX8GCR4 @ 0XFD080F10

    + + # Byte lane VREF IOM (Used only by D4MU IOs) + # PSU_DDR_PHY_DX8GCR4_RESERVED_31_29 0x0 + + # Byte Lane VREF Pad Enable + # PSU_DDR_PHY_DX8GCR4_DXREFPEN 0x0 + + # Byte Lane Internal VREF Enable + # PSU_DDR_PHY_DX8GCR4_DXREFEEN 0x3 + + # Byte Lane Single-End VREF Enable + # PSU_DDR_PHY_DX8GCR4_DXREFSEN 0x0 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX8GCR4_RESERVED_24 0x0 + + # External VREF generator REFSEL range select + # PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE 0x0 + + # Byte Lane External VREF Select + # PSU_DDR_PHY_DX8GCR4_DXREFESEL 0x0 + + # Single ended VREF generator REFSEL range select + # PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE 0x1 + + # Byte Lane Single-End VREF Select + # PSU_DDR_PHY_DX8GCR4_DXREFSSEL 0x30 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX8GCR4_RESERVED_7_6 0x0 + + # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX8GCR4_DXREFIEN 0x0 + + # VRMON control for DQ IO (Single Ended) buffers of a byte lane. + # PSU_DDR_PHY_DX8GCR4_DXREFIMON 0x0 + + # DATX8 n General Configuration Register 4 + #(OFFSET, MASK, VALUE) (0XFD080F10, 0xFFFFFFFFU ,0x0C00B000U) */ + mask_write 0XFD080F10 0xFFFFFFFF 0x0C00B000 + # Register : DX8GCR5 @ 0XFD080F14

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX8GCR5_RESERVED_31 0x0 + + # Byte Lane internal VREF Select for Rank 3 + # PSU_DDR_PHY_DX8GCR5_DXREFISELR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX8GCR5_RESERVED_23 0x0 + + # Byte Lane internal VREF Select for Rank 2 + # PSU_DDR_PHY_DX8GCR5_DXREFISELR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0 + + # Byte Lane internal VREF Select for Rank 1 + # PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0 + + # Byte Lane internal VREF Select for Rank 0 + # PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55 + + # DATX8 n General Configuration Register 5 + #(OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080F14 0xFFFFFFFF 0x09095555 + # Register : DX8GCR6 @ 0XFD080F18

    + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX8GCR6_RESERVED_31_30 0x0 + + # DRAM DQ VREF Select for Rank3 + # PSU_DDR_PHY_DX8GCR6_DXDQVREFR3 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX8GCR6_RESERVED_23_22 0x0 + + # DRAM DQ VREF Select for Rank2 + # PSU_DDR_PHY_DX8GCR6_DXDQVREFR2 0x9 + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX8GCR6_RESERVED_15_14 0x0 + + # DRAM DQ VREF Select for Rank1 + # PSU_DDR_PHY_DX8GCR6_DXDQVREFR1 0x2b + + # Reserved. Returns zeros on reads. + # PSU_DDR_PHY_DX8GCR6_RESERVED_7_6 0x0 + + # DRAM DQ VREF Select for Rank0 + # PSU_DDR_PHY_DX8GCR6_DXDQVREFR0 0x2b + + # DATX8 n General Configuration Register 6 + #(OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU) */ + mask_write 0XFD080F18 0xFFFFFFFF 0x09092B2B + # Register : DX8SL0OSC @ 0XFD081400

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0 + + # Enable Clock Gating for DX ddr_clk + # PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2 + + # Enable Clock Gating for DX ctl_rd_clk + # PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2 + + # Enable Clock Gating for DX ctl_clk + # PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2 + + # Selects the level to which clocks will be stalled when clock gating is e + # nabled. + # PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0 + + # Loopback Mode + # PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0 + + # Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + # PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0 + + # Loopback DQS Gating + # PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0 + + # Loopback DQS Shift + # PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0 + + # PHY High-Speed Reset + # PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1 + + # PHY FIFO Reset + # PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1 + + # Delay Line Test Start + # PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0 + + # Delay Line Test Mode + # PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0 + + # Reserved. Caution, do not write to this register field. + # PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3 + + # Oscillator Mode Write-Data Delay Line Select + # PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3 + + # Reserved. Caution, do not write to this register field. + # PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3 + + # Oscillator Mode Write-Leveling Delay Line Select + # PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3 + + # Oscillator Mode Division + # PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf + + # Oscillator Enable + # PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0 + + # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + # opback, and Gated Clock Control Register + #(OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU) */ + mask_write 0XFD081400 0xFFFFFFFF 0x2A019FFE + # Register : DX8SL0PLLCR0 @ 0XFD081404

    + + # PLL Bypass + # PSU_DDR_PHY_DX8SL0PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SL0PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SL0PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SL0PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SL0PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SL0PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SL0PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SL0PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SL0PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SL0PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SL0PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SL0PLLCR0_DTC 0x0 + + # DAXT8 0-1 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD081404, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD081404 0xFFFFFFFF 0x01100000 + # Register : DX8SL0DQSCTL @ 0XFD08141C

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25 0x0 + + # Read Path Rise-to-Rise Mode + # PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22 0x0 + + # Write Path Rise-to-Rise Mode + # PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE 0x1 + + # DQS Gate Extension + # PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX 0x0 + + # Low Power PLL Power Down + # PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD 0x1 + + # Low Power I/O Power Down + # PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15 0x0 + + # QS Counter Enable + # PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN 0x1 + + # Unused DQ I/O Mode + # PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10 0x0 + + # Data Slew Rate + # PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3 + + # DQS_N Resistor + # PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0 + + # DQS Resistor + # PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0 + + # DATX8 0-1 DQS Control Register + #(OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U) */ + mask_write 0XFD08141C 0xFFFFFFFF 0x01264300 + # Register : DX8SL0DXCTL2 @ 0XFD08142C

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24 0x0 + + # Configurable Read Data Enable + # PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN 0x0 + + # OX Extension during Post-amble + # PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0 + + # OE Extension during Pre-amble + # PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0 + + # I/O Assisted Gate Select + # PSU_DDR_PHY_DX8SL0DXCTL2_IOAG 0x0 + + # I/O Loopback Select + # PSU_DDR_PHY_DX8SL0DXCTL2_IOLB 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13 0x0 + + # Low Power Wakeup Threshold + # PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH 0xc + + # Read Data Bus Inversion Enable + # PSU_DDR_PHY_DX8SL0DXCTL2_RDBI 0x0 + + # Write Data Bus Inversion Enable + # PSU_DDR_PHY_DX8SL0DXCTL2_WDBI 0x0 + + # PUB Read FIFO Bypass + # PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP 0x0 + + # DATX8 Receive FIFO Read Mode + # PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE 0x0 + + # Disables the Read FIFO Reset + # PSU_DDR_PHY_DX8SL0DXCTL2_DISRST 0x0 + + # Read DQS Gate I/O Loopback + # PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0 + + # DATX8 0-1 DX Control Register 2 + #(OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U) */ + mask_write 0XFD08142C 0xFFFFFFFF 0x00041800 + # Register : DX8SL0IOCR @ 0XFD081430

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31 0x0 + + # PVREF_DAC REFSEL range select + # PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE 0x7 + + # IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + # PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM 0x0 + + # DX IO Mode + # PSU_DDR_PHY_DX8SL0IOCR_DXIOM 0x2 + + # DX IO Transmitter Mode + # PSU_DDR_PHY_DX8SL0IOCR_DXTXM 0x0 + + # DX IO Receiver Mode + # PSU_DDR_PHY_DX8SL0IOCR_DXRXM 0x0 + + # DATX8 0-1 I/O Configuration Register + #(OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U) */ + mask_write 0XFD081430 0xFFFFFFFF 0x70800000 + # Register : DX8SL1OSC @ 0XFD081440

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0 + + # Enable Clock Gating for DX ddr_clk + # PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2 + + # Enable Clock Gating for DX ctl_rd_clk + # PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2 + + # Enable Clock Gating for DX ctl_clk + # PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2 + + # Selects the level to which clocks will be stalled when clock gating is e + # nabled. + # PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0 + + # Loopback Mode + # PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0 + + # Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + # PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0 + + # Loopback DQS Gating + # PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0 + + # Loopback DQS Shift + # PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0 + + # PHY High-Speed Reset + # PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1 + + # PHY FIFO Reset + # PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1 + + # Delay Line Test Start + # PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0 + + # Delay Line Test Mode + # PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0 + + # Reserved. Caution, do not write to this register field. + # PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3 + + # Oscillator Mode Write-Data Delay Line Select + # PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3 + + # Reserved. Caution, do not write to this register field. + # PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3 + + # Oscillator Mode Write-Leveling Delay Line Select + # PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3 + + # Oscillator Mode Division + # PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf + + # Oscillator Enable + # PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0 + + # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + # opback, and Gated Clock Control Register + #(OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU) */ + mask_write 0XFD081440 0xFFFFFFFF 0x2A019FFE + # Register : DX8SL1PLLCR0 @ 0XFD081444

    + + # PLL Bypass + # PSU_DDR_PHY_DX8SL1PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SL1PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SL1PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SL1PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SL1PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SL1PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SL1PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SL1PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SL1PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SL1PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SL1PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SL1PLLCR0_DTC 0x0 + + # DAXT8 0-1 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD081444, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD081444 0xFFFFFFFF 0x01100000 + # Register : DX8SL1DQSCTL @ 0XFD08145C

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25 0x0 + + # Read Path Rise-to-Rise Mode + # PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22 0x0 + + # Write Path Rise-to-Rise Mode + # PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE 0x1 + + # DQS Gate Extension + # PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX 0x0 + + # Low Power PLL Power Down + # PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD 0x1 + + # Low Power I/O Power Down + # PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15 0x0 + + # QS Counter Enable + # PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN 0x1 + + # Unused DQ I/O Mode + # PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10 0x0 + + # Data Slew Rate + # PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3 + + # DQS_N Resistor + # PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0 + + # DQS Resistor + # PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0 + + # DATX8 0-1 DQS Control Register + #(OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U) */ + mask_write 0XFD08145C 0xFFFFFFFF 0x01264300 + # Register : DX8SL1DXCTL2 @ 0XFD08146C

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24 0x0 + + # Configurable Read Data Enable + # PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN 0x0 + + # OX Extension during Post-amble + # PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0 + + # OE Extension during Pre-amble + # PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0 + + # I/O Assisted Gate Select + # PSU_DDR_PHY_DX8SL1DXCTL2_IOAG 0x0 + + # I/O Loopback Select + # PSU_DDR_PHY_DX8SL1DXCTL2_IOLB 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13 0x0 + + # Low Power Wakeup Threshold + # PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH 0xc + + # Read Data Bus Inversion Enable + # PSU_DDR_PHY_DX8SL1DXCTL2_RDBI 0x0 + + # Write Data Bus Inversion Enable + # PSU_DDR_PHY_DX8SL1DXCTL2_WDBI 0x0 + + # PUB Read FIFO Bypass + # PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP 0x0 + + # DATX8 Receive FIFO Read Mode + # PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE 0x0 + + # Disables the Read FIFO Reset + # PSU_DDR_PHY_DX8SL1DXCTL2_DISRST 0x0 + + # Read DQS Gate I/O Loopback + # PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0 + + # DATX8 0-1 DX Control Register 2 + #(OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U) */ + mask_write 0XFD08146C 0xFFFFFFFF 0x00041800 + # Register : DX8SL1IOCR @ 0XFD081470

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31 0x0 + + # PVREF_DAC REFSEL range select + # PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE 0x7 + + # IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + # PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM 0x0 + + # DX IO Mode + # PSU_DDR_PHY_DX8SL1IOCR_DXIOM 0x2 + + # DX IO Transmitter Mode + # PSU_DDR_PHY_DX8SL1IOCR_DXTXM 0x0 + + # DX IO Receiver Mode + # PSU_DDR_PHY_DX8SL1IOCR_DXRXM 0x0 + + # DATX8 0-1 I/O Configuration Register + #(OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U) */ + mask_write 0XFD081470 0xFFFFFFFF 0x70800000 + # Register : DX8SL2OSC @ 0XFD081480

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0 + + # Enable Clock Gating for DX ddr_clk + # PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2 + + # Enable Clock Gating for DX ctl_rd_clk + # PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2 + + # Enable Clock Gating for DX ctl_clk + # PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2 + + # Selects the level to which clocks will be stalled when clock gating is e + # nabled. + # PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0 + + # Loopback Mode + # PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0 + + # Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + # PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0 + + # Loopback DQS Gating + # PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0 + + # Loopback DQS Shift + # PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0 + + # PHY High-Speed Reset + # PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1 + + # PHY FIFO Reset + # PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1 + + # Delay Line Test Start + # PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0 + + # Delay Line Test Mode + # PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0 + + # Reserved. Caution, do not write to this register field. + # PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3 + + # Oscillator Mode Write-Data Delay Line Select + # PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3 + + # Reserved. Caution, do not write to this register field. + # PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3 + + # Oscillator Mode Write-Leveling Delay Line Select + # PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3 + + # Oscillator Mode Division + # PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf + + # Oscillator Enable + # PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0 + + # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + # opback, and Gated Clock Control Register + #(OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU) */ + mask_write 0XFD081480 0xFFFFFFFF 0x2A019FFE + # Register : DX8SL2PLLCR0 @ 0XFD081484

    + + # PLL Bypass + # PSU_DDR_PHY_DX8SL2PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SL2PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SL2PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SL2PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SL2PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SL2PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SL2PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SL2PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SL2PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SL2PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SL2PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SL2PLLCR0_DTC 0x0 + + # DAXT8 0-1 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD081484, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD081484 0xFFFFFFFF 0x01100000 + # Register : DX8SL2DQSCTL @ 0XFD08149C

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0 + + # Read Path Rise-to-Rise Mode + # PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0 + + # Write Path Rise-to-Rise Mode + # PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1 + + # DQS Gate Extension + # PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX 0x0 + + # Low Power PLL Power Down + # PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD 0x1 + + # Low Power I/O Power Down + # PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15 0x0 + + # QS Counter Enable + # PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN 0x1 + + # Unused DQ I/O Mode + # PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10 0x0 + + # Data Slew Rate + # PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3 + + # DQS_N Resistor + # PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0 + + # DQS Resistor + # PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0 + + # DATX8 0-1 DQS Control Register + #(OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U) */ + mask_write 0XFD08149C 0xFFFFFFFF 0x01264300 + # Register : DX8SL2DXCTL2 @ 0XFD0814AC

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24 0x0 + + # Configurable Read Data Enable + # PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN 0x0 + + # OX Extension during Post-amble + # PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0 + + # OE Extension during Pre-amble + # PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0 + + # I/O Assisted Gate Select + # PSU_DDR_PHY_DX8SL2DXCTL2_IOAG 0x0 + + # I/O Loopback Select + # PSU_DDR_PHY_DX8SL2DXCTL2_IOLB 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13 0x0 + + # Low Power Wakeup Threshold + # PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH 0xc + + # Read Data Bus Inversion Enable + # PSU_DDR_PHY_DX8SL2DXCTL2_RDBI 0x0 + + # Write Data Bus Inversion Enable + # PSU_DDR_PHY_DX8SL2DXCTL2_WDBI 0x0 + + # PUB Read FIFO Bypass + # PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP 0x0 + + # DATX8 Receive FIFO Read Mode + # PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE 0x0 + + # Disables the Read FIFO Reset + # PSU_DDR_PHY_DX8SL2DXCTL2_DISRST 0x0 + + # Read DQS Gate I/O Loopback + # PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0 + + # DATX8 0-1 DX Control Register 2 + #(OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U) */ + mask_write 0XFD0814AC 0xFFFFFFFF 0x00041800 + # Register : DX8SL2IOCR @ 0XFD0814B0

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31 0x0 + + # PVREF_DAC REFSEL range select + # PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE 0x7 + + # IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + # PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM 0x0 + + # DX IO Mode + # PSU_DDR_PHY_DX8SL2IOCR_DXIOM 0x2 + + # DX IO Transmitter Mode + # PSU_DDR_PHY_DX8SL2IOCR_DXTXM 0x0 + + # DX IO Receiver Mode + # PSU_DDR_PHY_DX8SL2IOCR_DXRXM 0x0 + + # DATX8 0-1 I/O Configuration Register + #(OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U) */ + mask_write 0XFD0814B0 0xFFFFFFFF 0x70800000 + # Register : DX8SL3OSC @ 0XFD0814C0

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0 + + # Enable Clock Gating for DX ddr_clk + # PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2 + + # Enable Clock Gating for DX ctl_rd_clk + # PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2 + + # Enable Clock Gating for DX ctl_clk + # PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2 + + # Selects the level to which clocks will be stalled when clock gating is e + # nabled. + # PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0 + + # Loopback Mode + # PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0 + + # Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + # PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0 + + # Loopback DQS Gating + # PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0 + + # Loopback DQS Shift + # PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0 + + # PHY High-Speed Reset + # PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1 + + # PHY FIFO Reset + # PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1 + + # Delay Line Test Start + # PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0 + + # Delay Line Test Mode + # PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0 + + # Reserved. Caution, do not write to this register field. + # PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3 + + # Oscillator Mode Write-Data Delay Line Select + # PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3 + + # Reserved. Caution, do not write to this register field. + # PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3 + + # Oscillator Mode Write-Leveling Delay Line Select + # PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3 + + # Oscillator Mode Division + # PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf + + # Oscillator Enable + # PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0 + + # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + # opback, and Gated Clock Control Register + #(OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU) */ + mask_write 0XFD0814C0 0xFFFFFFFF 0x2A019FFE + # Register : DX8SL3PLLCR0 @ 0XFD0814C4

    + + # PLL Bypass + # PSU_DDR_PHY_DX8SL3PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SL3PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SL3PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SL3PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SL3PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SL3PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SL3PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SL3PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SL3PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SL3PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SL3PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SL3PLLCR0_DTC 0x0 + + # DAXT8 0-1 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD0814C4, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD0814C4 0xFFFFFFFF 0x01100000 + # Register : DX8SL3DQSCTL @ 0XFD0814DC

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25 0x0 + + # Read Path Rise-to-Rise Mode + # PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22 0x0 + + # Write Path Rise-to-Rise Mode + # PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE 0x1 + + # DQS Gate Extension + # PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX 0x0 + + # Low Power PLL Power Down + # PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD 0x1 + + # Low Power I/O Power Down + # PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15 0x0 + + # QS Counter Enable + # PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN 0x1 + + # Unused DQ I/O Mode + # PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10 0x0 + + # Data Slew Rate + # PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3 + + # DQS_N Resistor + # PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0 + + # DQS Resistor + # PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0 + + # DATX8 0-1 DQS Control Register + #(OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U) */ + mask_write 0XFD0814DC 0xFFFFFFFF 0x01264300 + # Register : DX8SL3DXCTL2 @ 0XFD0814EC

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24 0x0 + + # Configurable Read Data Enable + # PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN 0x0 + + # OX Extension during Post-amble + # PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0 + + # OE Extension during Pre-amble + # PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0 + + # I/O Assisted Gate Select + # PSU_DDR_PHY_DX8SL3DXCTL2_IOAG 0x0 + + # I/O Loopback Select + # PSU_DDR_PHY_DX8SL3DXCTL2_IOLB 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13 0x0 + + # Low Power Wakeup Threshold + # PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH 0xc + + # Read Data Bus Inversion Enable + # PSU_DDR_PHY_DX8SL3DXCTL2_RDBI 0x0 + + # Write Data Bus Inversion Enable + # PSU_DDR_PHY_DX8SL3DXCTL2_WDBI 0x0 + + # PUB Read FIFO Bypass + # PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP 0x0 + + # DATX8 Receive FIFO Read Mode + # PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE 0x0 + + # Disables the Read FIFO Reset + # PSU_DDR_PHY_DX8SL3DXCTL2_DISRST 0x0 + + # Read DQS Gate I/O Loopback + # PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0 + + # DATX8 0-1 DX Control Register 2 + #(OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U) */ + mask_write 0XFD0814EC 0xFFFFFFFF 0x00041800 + # Register : DX8SL3IOCR @ 0XFD0814F0

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31 0x0 + + # PVREF_DAC REFSEL range select + # PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE 0x7 + + # IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + # PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM 0x0 + + # DX IO Mode + # PSU_DDR_PHY_DX8SL3IOCR_DXIOM 0x2 + + # DX IO Transmitter Mode + # PSU_DDR_PHY_DX8SL3IOCR_DXTXM 0x0 + + # DX IO Receiver Mode + # PSU_DDR_PHY_DX8SL3IOCR_DXRXM 0x0 + + # DATX8 0-1 I/O Configuration Register + #(OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U) */ + mask_write 0XFD0814F0 0xFFFFFFFF 0x70800000 + # Register : DX8SL4OSC @ 0XFD081500

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0 + + # Enable Clock Gating for DX ddr_clk + # PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x1 + + # Enable Clock Gating for DX ctl_rd_clk + # PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x1 + + # Enable Clock Gating for DX ctl_clk + # PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x1 + + # Selects the level to which clocks will be stalled when clock gating is e + # nabled. + # PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0 + + # Loopback Mode + # PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0 + + # Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + # PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0 + + # Loopback DQS Gating + # PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0 + + # Loopback DQS Shift + # PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0 + + # PHY High-Speed Reset + # PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1 + + # PHY FIFO Reset + # PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1 + + # Delay Line Test Start + # PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0 + + # Delay Line Test Mode + # PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0 + + # Reserved. Caution, do not write to this register field. + # PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3 + + # Oscillator Mode Write-Data Delay Line Select + # PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3 + + # Reserved. Caution, do not write to this register field. + # PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3 + + # Oscillator Mode Write-Leveling Delay Line Select + # PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3 + + # Oscillator Mode Division + # PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf + + # Oscillator Enable + # PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0 + + # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + # opback, and Gated Clock Control Register + #(OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x15019FFEU) */ + mask_write 0XFD081500 0xFFFFFFFF 0x15019FFE + # Register : DX8SL4PLLCR0 @ 0XFD081504

    + + # PLL Bypass + # PSU_DDR_PHY_DX8SL4PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SL4PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SL4PLLCR0_PLLPD 0x1 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SL4PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SL4PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SL4PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SL4PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SL4PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SL4PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SL4PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SL4PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SL4PLLCR0_DTC 0x0 + + # DAXT8 0-1 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD081504, 0xFFFFFFFFU ,0x21100000U) */ + mask_write 0XFD081504 0xFFFFFFFF 0x21100000 + # Register : DX8SL4DQSCTL @ 0XFD08151C

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25 0x0 + + # Read Path Rise-to-Rise Mode + # PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22 0x0 + + # Write Path Rise-to-Rise Mode + # PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE 0x1 + + # DQS Gate Extension + # PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX 0x0 + + # Low Power PLL Power Down + # PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD 0x1 + + # Low Power I/O Power Down + # PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15 0x0 + + # QS Counter Enable + # PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN 0x1 + + # Unused DQ I/O Mode + # PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10 0x0 + + # Data Slew Rate + # PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3 + + # DQS_N Resistor + # PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0 + + # DQS Resistor + # PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0 + + # DATX8 0-1 DQS Control Register + #(OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01266300U) */ + mask_write 0XFD08151C 0xFFFFFFFF 0x01266300 + # Register : DX8SL4DXCTL2 @ 0XFD08152C

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24 0x0 + + # Configurable Read Data Enable + # PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN 0x0 + + # OX Extension during Post-amble + # PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0 + + # OE Extension during Pre-amble + # PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0 + + # I/O Assisted Gate Select + # PSU_DDR_PHY_DX8SL4DXCTL2_IOAG 0x0 + + # I/O Loopback Select + # PSU_DDR_PHY_DX8SL4DXCTL2_IOLB 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13 0x0 + + # Low Power Wakeup Threshold + # PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH 0xc + + # Read Data Bus Inversion Enable + # PSU_DDR_PHY_DX8SL4DXCTL2_RDBI 0x0 + + # Write Data Bus Inversion Enable + # PSU_DDR_PHY_DX8SL4DXCTL2_WDBI 0x0 + + # PUB Read FIFO Bypass + # PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP 0x0 + + # DATX8 Receive FIFO Read Mode + # PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE 0x0 + + # Disables the Read FIFO Reset + # PSU_DDR_PHY_DX8SL4DXCTL2_DISRST 0x0 + + # Read DQS Gate I/O Loopback + # PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0 + + # DATX8 0-1 DX Control Register 2 + #(OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U) */ + mask_write 0XFD08152C 0xFFFFFFFF 0x00041800 + # Register : DX8SL4IOCR @ 0XFD081530

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31 0x0 + + # PVREF_DAC REFSEL range select + # PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE 0x7 + + # IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + # PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM 0x0 + + # DX IO Mode + # PSU_DDR_PHY_DX8SL4IOCR_DXIOM 0x1 + + # DX IO Transmitter Mode + # PSU_DDR_PHY_DX8SL4IOCR_DXTXM 0x0 + + # DX IO Receiver Mode + # PSU_DDR_PHY_DX8SL4IOCR_DXRXM 0x0 + + # DATX8 0-1 I/O Configuration Register + #(OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70400000U) */ + mask_write 0XFD081530 0xFFFFFFFF 0x70400000 + # Register : DX8SLbDQSCTL @ 0XFD0817DC

    + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25 0x0 + + # Read Path Rise-to-Rise Mode + # PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22 0x0 + + # Write Path Rise-to-Rise Mode + # PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE 0x1 + + # DQS Gate Extension + # PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX 0x0 + + # Low Power PLL Power Down + # PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD 0x1 + + # Low Power I/O Power Down + # PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD 0x1 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15 0x0 + + # QS Counter Enable + # PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN 0x1 + + # Unused DQ I/O Mode + # PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10 0x0 + + # Data Slew Rate + # PSU_DDR_PHY_DX8SLBDQSCTL_DXSR 0x3 + + # DQS# Resistor + # PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES 0xc + + # DQS Resistor + # PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES 0x4 + + # DATX8 0-8 DQS Control Register + #(OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U) */ + mask_write 0XFD0817DC 0xFFFFFFFF 0x012643C4 +} + +set psu_ddr_qos_init_data { + # : AFI INTERCONNECT QOS CONFIGURATION + # Register : AFIFM_RDQoS @ 0XFD360008

    + + # Sets the level of the QoS field to be used for the read channel 4'b0000: + # Lowest Priority' ' '4'b1111: Highest Priority + # PSU_AFIFM0_AFIFM_RDQOS_VALUE 0 + + # QoS Read Channel Register + #(OFFSET, MASK, VALUE) (0XFD360008, 0x0000000FU ,0x00000000U) */ + mask_write 0XFD360008 0x0000000F 0x00000000 + # Register : AFIFM_WRQoS @ 0XFD36001C

    + + # Sets the level of the QoS field to be used for the write channel 4'b0000 + # : Lowest Priority' ' '4'b1111: Highest Priority + # PSU_AFIFM0_AFIFM_WRQOS_VALUE 0 + + # QoS Write Channel Register + #(OFFSET, MASK, VALUE) (0XFD36001C, 0x0000000FU ,0x00000000U) */ + mask_write 0XFD36001C 0x0000000F 0x00000000 + # Register : AFIFM_RDQoS @ 0XFD370008

    + + # Sets the level of the QoS field to be used for the read channel 4'b0000: + # Lowest Priority' ' '4'b1111: Highest Priority + # PSU_AFIFM1_AFIFM_RDQOS_VALUE 0 + + # QoS Read Channel Register + #(OFFSET, MASK, VALUE) (0XFD370008, 0x0000000FU ,0x00000000U) */ + mask_write 0XFD370008 0x0000000F 0x00000000 + # Register : AFIFM_WRQoS @ 0XFD37001C

    + + # Sets the level of the QoS field to be used for the write channel 4'b0000 + # : Lowest Priority' ' '4'b1111: Highest Priority + # PSU_AFIFM1_AFIFM_WRQOS_VALUE 0 + + # QoS Write Channel Register + #(OFFSET, MASK, VALUE) (0XFD37001C, 0x0000000FU ,0x00000000U) */ + mask_write 0XFD37001C 0x0000000F 0x00000000 + # Register : AFIFM_RDQoS @ 0XFD380008

    + + # Sets the level of the QoS field to be used for the read channel 4'b0000: + # Lowest Priority' ' '4'b1111: Highest Priority + # PSU_AFIFM2_AFIFM_RDQOS_VALUE 0 + + # QoS Read Channel Register + #(OFFSET, MASK, VALUE) (0XFD380008, 0x0000000FU ,0x00000000U) */ + mask_write 0XFD380008 0x0000000F 0x00000000 + # Register : AFIFM_WRQoS @ 0XFD38001C

    + + # Sets the level of the QoS field to be used for the write channel 4'b0000 + # : Lowest Priority' ' '4'b1111: Highest Priority + # PSU_AFIFM2_AFIFM_WRQOS_VALUE 0 + + # QoS Write Channel Register + #(OFFSET, MASK, VALUE) (0XFD38001C, 0x0000000FU ,0x00000000U) */ + mask_write 0XFD38001C 0x0000000F 0x00000000 + # Register : AFIFM_RDQoS @ 0XFD390008

    + + # Sets the level of the QoS field to be used for the read channel 4'b0000: + # Lowest Priority' ' '4'b1111: Highest Priority + # PSU_AFIFM3_AFIFM_RDQOS_VALUE 0 + + # QoS Read Channel Register + #(OFFSET, MASK, VALUE) (0XFD390008, 0x0000000FU ,0x00000000U) */ + mask_write 0XFD390008 0x0000000F 0x00000000 + # Register : AFIFM_WRQoS @ 0XFD39001C

    + + # Sets the level of the QoS field to be used for the write channel 4'b0000 + # : Lowest Priority' ' '4'b1111: Highest Priority + # PSU_AFIFM3_AFIFM_WRQOS_VALUE 0 + + # QoS Write Channel Register + #(OFFSET, MASK, VALUE) (0XFD39001C, 0x0000000FU ,0x00000000U) */ + mask_write 0XFD39001C 0x0000000F 0x00000000 + # Register : AFIFM_RDQoS @ 0XFD3A0008

    + + # Sets the level of the QoS field to be used for the read channel 4'b0000: + # Lowest Priority' ' '4'b1111: Highest Priority + # PSU_AFIFM4_AFIFM_RDQOS_VALUE 0 + + # QoS Read Channel Register + #(OFFSET, MASK, VALUE) (0XFD3A0008, 0x0000000FU ,0x00000000U) */ + mask_write 0XFD3A0008 0x0000000F 0x00000000 + # Register : AFIFM_WRQoS @ 0XFD3A001C

    + + # Sets the level of the QoS field to be used for the write channel 4'b0000 + # : Lowest Priority' ' '4'b1111: Highest Priority + # PSU_AFIFM4_AFIFM_WRQOS_VALUE 0 + + # QoS Write Channel Register + #(OFFSET, MASK, VALUE) (0XFD3A001C, 0x0000000FU ,0x00000000U) */ + mask_write 0XFD3A001C 0x0000000F 0x00000000 + # Register : AFIFM_RDQoS @ 0XFD3B0008

    + + # Sets the level of the QoS field to be used for the read channel 4'b0000: + # Lowest Priority' ' '4'b1111: Highest Priority + # PSU_AFIFM5_AFIFM_RDQOS_VALUE 0 + + # QoS Read Channel Register + #(OFFSET, MASK, VALUE) (0XFD3B0008, 0x0000000FU ,0x00000000U) */ + mask_write 0XFD3B0008 0x0000000F 0x00000000 + # Register : AFIFM_WRQoS @ 0XFD3B001C

    + + # Sets the level of the QoS field to be used for the write channel 4'b0000 + # : Lowest Priority' ' '4'b1111: Highest Priority + # PSU_AFIFM5_AFIFM_WRQOS_VALUE 0 + + # QoS Write Channel Register + #(OFFSET, MASK, VALUE) (0XFD3B001C, 0x0000000FU ,0x00000000U) */ + mask_write 0XFD3B001C 0x0000000F 0x00000000 + # Register : AFIFM_RDQoS @ 0XFF9B0008

    + + # Sets the level of the QoS field to be used for the read channel 4'b0000: + # Lowest Priority' ' '4'b1111: Highest Priority + # PSU_AFIFM6_AFIFM_RDQOS_VALUE 0 + + # QoS Read Channel Register + #(OFFSET, MASK, VALUE) (0XFF9B0008, 0x0000000FU ,0x00000000U) */ + mask_write 0XFF9B0008 0x0000000F 0x00000000 + # Register : AFIFM_WRQoS @ 0XFF9B001C

    + + # Sets the level of the QoS field to be used for the write channel 4'b0000 + # : Lowest Priority' ' '4'b1111: Highest Priority + # PSU_AFIFM6_AFIFM_WRQOS_VALUE 0 + + # QoS Write Channel Register + #(OFFSET, MASK, VALUE) (0XFF9B001C, 0x0000000FU ,0x00000000U) */ + mask_write 0XFF9B001C 0x0000000F 0x00000000 +} + +set psu_mio_init_data { + # : MIO PROGRAMMING + # Register : MIO_PIN_0 @ 0XFF180000

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- + # (QSPI Clock) + # PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0 + # ]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + # TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + # lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out + # put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + # lk- (Trace Port Clock) + # PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0 + + # Configures MIO Pin 0 peripheral interface mapping. S + #(OFFSET, MASK, VALUE) (0XFF180000, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180000 0x000000FE 0x00000002 + # Register : MIO_PIN_1 @ 0XFF180004

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q + # SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) + # PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1 + # ]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + # TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou + # tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + # receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + # Signal) + # PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0 + + # Configures MIO Pin 1 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180004, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180004 0x000000FE 0x00000002 + # Register : MIO_PIN_2 @ 0XFF180008

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI + # Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) + # PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2 + # ]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + # TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I + # nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + # rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0 + + # Configures MIO Pin 2 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180008, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180008 0x000000FE 0x00000002 + # Register : MIO_PIN_3 @ 0XFF18000C

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI + # Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) + # PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3 + # ]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + # TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + # , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- + # (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + # output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0 + + # Configures MIO Pin 3 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF18000C, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF18000C 0x000000FE 0x00000002 + # Register : MIO_PIN_4 @ 0XFF180010

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- ( + # QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) + # PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4 + # ]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + # tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + # 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc + # k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + # utput, tracedq[2]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0 + + # Configures MIO Pin 4 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180010, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180010 0x000000FE 0x00000002 + # Register : MIO_PIN_5 @ 0XFF180014

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- + # (QSPI Slave Select) + # PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5 + # ]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + # atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + # spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC + # Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + # trace, Output, tracedq[3]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0 + + # Configures MIO Pin 5 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180014, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180014 0x000000FE 0x00000002 + # Register : MIO_PIN_6 @ 0XFF180018

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l + # pbk- (QSPI Clock to be fed-back) + # PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6 + # ]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + # ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s + # pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT + # C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, + # Output, tracedq[4]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0 + + # Configures MIO Pin 6 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180018, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180018 0x000000FE 0x00000002 + # Register : MIO_PIN_7 @ 0XFF18001C

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_ + # upper- (QSPI Slave Select upper) + # PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7 + # ]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + # Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma + # ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua + # 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t + # racedq[5]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0 + + # Configures MIO Pin 7 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF18001C, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF18001C 0x000000FE 0x00000002 + # Register : MIO_PIN_8 @ 0XFF180020

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0 + # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D + # atabus) + # PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8 + # ]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + # tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste + # r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_ + # txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra + # ce Port Databus) + # PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0 + + # Configures MIO Pin 8 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180020, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180020 0x000000FE 0x00000002 + # Register : MIO_PIN_9 @ 0XFF180024

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1 + # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D + # atabus) + # PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + # ND chip enable) + # PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9 + # ]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + # atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S + # elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, + # Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA + # RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data + # bus) + # PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0 + + # Configures MIO Pin 9 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180024, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180024 0x000000FE 0x00000002 + # Register : MIO_PIN_10 @ 0XFF180028

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2 + # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D + # atabus) + # PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + # AND Ready/Busy) + # PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[ + # 10]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + # i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + # t, tracedq[8]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0 + + # Configures MIO Pin 10 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180028, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180028 0x000000FE 0x00000002 + # Register : MIO_PIN_11 @ 0XFF18002C

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3 + # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D + # atabus) + # PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + # AND Ready/Busy) + # PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[ + # 11]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + # 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + # tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0 + + # Configures MIO Pin 11 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF18002C, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF18002C 0x000000FE 0x00000002 + # Register : MIO_PIN_12 @ 0XFF180030

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_ + # upper- (QSPI Upper Clock) + # PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + # ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) + # PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[ + # 12]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT + # AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_ + # sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O + # utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace + # dq[10]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0 + + # Configures MIO Pin 12 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180030, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180030 0x000000FE 0x00000002 + # Register : MIO_PIN_13 @ 0XFF180034

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA + # ND chip enable) + # PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, + # test_scan_out[13]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA + # G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, + # Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR + # T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data + # bus) + # PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0 + + # Configures MIO Pin 13 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180034, 0x000000FEU ,0x00000000U) */ + mask_write 0XFF180034 0x000000FE 0x00000000 + # Register : MIO_PIN_14 @ 0XFF180038

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND + # Command Latch Enable) + # PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, + # test_scan_out[14]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT + # AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, + # Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver + # serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2 + + # Configures MIO Pin 14 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180038, 0x000000FEU ,0x00000040U) */ + mask_write 0XFF180038 0x000000FE 0x00000040 + # Register : MIO_PIN_15 @ 0XFF18003C

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND + # Address Latch Enable) + # PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, + # test_scan_out[15]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT + # AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp + # ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou + # t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria + # l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2 + + # Configures MIO Pin 15 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF18003C, 0x000000FEU ,0x00000040U) */ + mask_write 0XFF18003C 0x000000FE 0x00000040 + # Register : MIO_PIN_16 @ 0XFF180040

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus) + # PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, + # test_scan_out[16]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + # pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + # ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + # Output, tracedq[14]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2 + + # Configures MIO Pin 16 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180040, 0x000000FEU ,0x00000040U) */ + mask_write 0XFF180040 0x000000FE 0x00000040 + # Register : MIO_PIN_17 @ 0XFF180044

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus) + # PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, + # test_scan_out[17]- (Test Scan Port) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + # = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + # TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + # 7= trace, Output, tracedq[15]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2 + + # Configures MIO Pin 17 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180044, 0x000000FEU ,0x00000040U) */ + mask_write 0XFF180044 0x000000FE 0x00000040 + # Register : MIO_PIN_18 @ 0XFF180048

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus) + # PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, + # test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + # Ext Tamper) + # PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + # i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6 + + # Configures MIO Pin 18 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180048, 0x000000FEU ,0x000000C0U) */ + mask_write 0XFF180048 0x000000FE 0x000000C0 + # Register : MIO_PIN_19 @ 0XFF18004C

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus) + # PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, + # test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + # Ext Tamper) + # PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + # Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= + # ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6 + + # Configures MIO Pin 19 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF18004C, 0x000000FEU ,0x000000C0U) */ + mask_write 0XFF18004C 0x000000FE 0x000000C0 + # Register : MIO_PIN_20 @ 0XFF180050

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus) + # PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, + # test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + # Ext Tamper) + # PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + # ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua + # 1_txd- (UART transmitter serial output) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6 + + # Configures MIO Pin 20 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180050, 0x000000FEU ,0x000000C0U) */ + mask_write 0XFF180050 0x000000FE 0x000000C0 + # Register : MIO_PIN_21 @ 0XFF180054

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus) + # PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + # mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes + # t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t + # est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E + # xt Tamper) + # PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + # Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc + # 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- ( + # UART receiver serial input) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6 + + # Configures MIO Pin 21 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180054, 0x000000FEU ,0x000000C0U) */ + mask_write 0XFF180054 0x000000FE 0x000000C0 + # Register : MIO_PIN_22 @ 0XFF180058

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN + # D Write Enable) + # PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + # (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = + # test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c + # su_ext_tamper- (CSU Ext Tamper) + # PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + # spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + # TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + # sed + # PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0 + + # Configures MIO Pin 22 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180058, 0x000000FEU ,0x00000000U) */ + mask_write 0XFF180058 0x000000FE 0x00000000 + # Register : MIO_PIN_23 @ 0XFF18005C

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus) + # PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + # (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po + # rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp + # ut, csu_ext_tamper- (CSU Ext Tamper) + # PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + # 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + # tput) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0 + + # Configures MIO Pin 23 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF18005C, 0x000000FEU ,0x00000000U) */ + mask_write 0XFF18005C 0x000000FE 0x00000000 + # Register : MIO_PIN_24 @ 0XFF180060

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus) + # PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + # card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test + # Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= + # csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T + # TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N + # ot Used + # PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1 + + # Configures MIO Pin 24 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180060, 0x000000FEU ,0x00000020U) */ + mask_write 0XFF180060 0x000000FE 0x00000020 + # Register : MIO_PIN_25 @ 0XFF180064

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN + # D Read Enable) + # PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + # rd write protect from connector) 2= test_scan, Input, test_scan_in[25]- + # (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port + # ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0 + + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou + # t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in + # put) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1 + + # Configures MIO Pin 25 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180064, 0x000000FEU ,0x00000020U) */ + mask_write 0XFF180064 0x000000FE 0x00000020 + # Register : MIO_PIN_26 @ 0XFF180068

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + # clk- (TX RGMII clock) + # PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + # ND chip enable) + # PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta + # mper- (CSU Ext Tamper) + # PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + # TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl + # k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + # t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + # Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0 + + # Configures MIO Pin 26 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U) */ + mask_write 0XFF180068 0x000000FE 0x00000000 + # Register : MIO_PIN_27 @ 0XFF18006C

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + # [0]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + # AND Ready/Busy) + # PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + # ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + # PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + # TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + # utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + # T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + # atabus) + # PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0 + + # Configures MIO Pin 27 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U) */ + mask_write 0XFF18006C 0x000000FE 0x00000018 + # Register : MIO_PIN_28 @ 0XFF180070

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + # [1]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + # AND Ready/Busy) + # PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + # lug_detect- (Dp Aux Hot Plug) + # PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + # G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + # Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + # er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0 + + # Configures MIO Pin 28 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U) */ + mask_write 0XFF180070 0x000000FE 0x00000018 + # Register : MIO_PIN_29 @ 0XFF180074

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + # [2]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) + # PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + # ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + # PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + # TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, + # spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + # (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + # ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0 + + # Configures MIO Pin 29 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U) */ + mask_write 0XFF180074 0x000000FE 0x00000018 + # Register : MIO_PIN_30 @ 0XFF180078

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + # [3]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) + # PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + # lug_detect- (Dp Aux Hot Plug) + # PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + # ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0 + # , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock + # ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, + # tracedq[8]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0 + + # Configures MIO Pin 30 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U) */ + mask_write 0XFF180078 0x000000FE 0x00000018 + # Register : MIO_PIN_31 @ 0XFF18007C

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + # ctl- (TX RGMII control) + # PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) + # PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta + # mper- (CSU Ext Tamper) + # PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + # Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + # spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT + # C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp + # ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0 + + # Configures MIO Pin 31 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF18007C, 0x000000FEU ,0x00000000U) */ + mask_write 0XFF18007C 0x000000FE 0x00000000 + # Register : MIO_PIN_32 @ 0XFF180080

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + # lk- (RX RGMII clock) + # PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + # ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) + # PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM + # U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc + # an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t + # amper- (CSU Ext Tamper) + # PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + # tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + # spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T + # TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t + # race, Output, tracedq[10]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0 + + # Configures MIO Pin 32 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180080, 0x000000FEU ,0x00000008U) */ + mask_write 0XFF180080 0x000000FE 0x00000008 + # Register : MIO_PIN_33 @ 0XFF180084

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + # 0]- (RX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) + # PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM + # U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc + # an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t + # amper- (CSU Ext Tamper) + # PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + # atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas + # ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1 + # , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq + # [11]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0 + + # Configures MIO Pin 33 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180084, 0x000000FEU ,0x00000008U) */ + mask_write 0XFF180084 0x000000FE 0x00000008 + # Register : MIO_PIN_38 @ 0XFF180098

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + # clk- (TX RGMII clock) + # PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + # (SDSDIO clock) 2= Not Used 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA + # G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s + # clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In + # put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- + # (Trace Port Clock) + # PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0 + + # Configures MIO Pin 38 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180098, 0x000000FEU ,0x00000000U) */ + mask_write 0XFF180098 0x000000FE 0x00000000 + # Register : MIO_PIN_39 @ 0XFF18009C

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + # [0]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + # card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b + # us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 2 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT + # AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, + # Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U + # ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port + # Control Signal) + # PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0 + + # Configures MIO Pin 39 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF18009C 0x000000FE 0x00000010 + # Register : MIO_PIN_40 @ 0XFF1800A0

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + # [1]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + # mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1 + # , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[ + # 5]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 2 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ + # TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3 + # , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi + # tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0 + + # Configures MIO Pin 40 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800A0 0x000000FE 0x00000010 + # Register : MIO_PIN_41 @ 0XFF1800A4

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + # [2]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[6]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 2 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA + # G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu + # t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out + # - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp + # ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0 + + # Configures MIO Pin 41 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800A4 0x000000FE 0x00000010 + # Register : MIO_PIN_42 @ 0XFF1800A8

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + # [3]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[7]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 2 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp + # i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + # t, tracedq[2]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0 + + # Configures MIO Pin 42 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800A8 0x000000FE 0x00000010 + # Register : MIO_PIN_43 @ 0XFF1800AC

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + # ctl- (TX RGMII control) + # PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + # d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 2 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) + # 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + # tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0 + + # Configures MIO Pin 43 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800AC 0x000000FE 0x00000010 + # Register : MIO_PIN_44 @ 0XFF1800B0

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + # lk- (RX RGMII clock) + # PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + # d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4 + # = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- + # (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + # Not Used + # PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0 + + # Configures MIO Pin 44 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800B0, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800B0 0x000000FE 0x00000010 + # Register : MIO_PIN_45 @ 0XFF1800B4

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + # 0]- (RX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + # d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M + # aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u + # a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0 + + # Configures MIO Pin 45 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800B4, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800B4 0x000000FE 0x00000010 + # Register : MIO_PIN_46 @ 0XFF1800B8

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + # 1]- (RX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[0]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast + # er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + # rxd- (UART receiver serial input) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0 + + # Configures MIO Pin 46 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800B8, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800B8 0x000000FE 0x00000010 + # Register : MIO_PIN_47 @ 0XFF1800BC

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + # 2]- (RX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[1]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste + # r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt + # c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + # (UART transmitter serial output) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0 + + # Configures MIO Pin 47 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800BC, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800BC 0x000000FE 0x00000010 + # Register : MIO_PIN_48 @ 0XFF1800C0

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + # 3]- (RX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[2]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + # pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + # ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us + # ed + # PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0 + + # Configures MIO Pin 48 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800C0, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800C0 0x000000FE 0x00000010 + # Register : MIO_PIN_49 @ 0XFF1800C4

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + # tl- (RX RGMII control ) + # PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + # (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd + # 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + # = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + # TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + # 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0 + + # Configures MIO Pin 49 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800C4, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800C4 0x000000FE 0x00000010 + # Register : MIO_PIN_50 @ 0XFF1800C8

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + # (TSU clock) + # PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + # rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind + # icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= + # ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece + # iver serial input) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0 + + # Configures MIO Pin 50 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800C8, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800C8 0x000000FE 0x00000010 + # Register : MIO_PIN_51 @ 0XFF1800CC

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + # (TSU clock) + # PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi + # o1_clk_out- (SDSDIO clock) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2 + + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat + # a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa + # ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter + # serial output) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0 + + # Configures MIO Pin 51 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800CC, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800CC 0x000000FE 0x00000010 + # Register : MIO_PIN_52 @ 0XFF1800D0

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + # clk- (TX RGMII clock) + # PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i + # n- (ULPI Clock) + # PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used + # PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + # TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + # lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out + # put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + # lk- (Trace Port Clock) + # PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0 + + # Configures MIO Pin 52 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000004U) */ + mask_write 0XFF1800D0 0x000000FE 0x00000004 + # Register : MIO_PIN_53 @ 0XFF1800D4

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + # [0]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- + # (Data bus direction control) + # PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used + # PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + # TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou + # tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + # receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + # Signal) + # PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0 + + # Configures MIO Pin 53 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000004U) */ + mask_write 0XFF1800D4 0x000000FE 0x00000004 + # Register : MIO_PIN_54 @ 0XFF1800D8

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + # [1]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used + # PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + # TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I + # nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + # rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0 + + # Configures MIO Pin 54 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000004U) */ + mask_write 0XFF1800D8 0x000000FE 0x00000004 + # Register : MIO_PIN_55 @ 0XFF1800DC

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + # [2]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- + # (Data flow control signal from the PHY) + # PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used + # PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + # TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + # , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- + # (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + # output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0 + + # Configures MIO Pin 55 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000004U) */ + mask_write 0XFF1800DC 0x000000FE 0x00000004 + # Register : MIO_PIN_56 @ 0XFF1800E0

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + # [3]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used + # PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + # tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + # 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc + # k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + # utput, tracedq[2]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0 + + # Configures MIO Pin 56 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000004U) */ + mask_write 0XFF1800E0 0x000000FE 0x00000004 + # Register : MIO_PIN_57 @ 0XFF1800E4

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + # ctl- (TX RGMII control) + # PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used + # PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + # atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + # spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC + # Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + # trace, Output, tracedq[3]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0 + + # Configures MIO Pin 57 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000004U) */ + mask_write 0XFF1800E4 0x000000FE 0x00000004 + # Register : MIO_PIN_58 @ 0XFF1800E8

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + # lk- (RX RGMII clock) + # PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- + # (Asserted to end or interrupt transfers) + # PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used + # PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + # TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl + # k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + # t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + # Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0 + + # Configures MIO Pin 58 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000004U) */ + mask_write 0XFF1800E8 0x000000FE 0x00000004 + # Register : MIO_PIN_59 @ 0XFF1800EC

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + # 0]- (RX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used + # PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + # TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + # utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + # T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + # atabus) + # PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0 + + # Configures MIO Pin 59 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000004U) */ + mask_write 0XFF1800EC 0x000000FE 0x00000004 + # Register : MIO_PIN_60 @ 0XFF1800F0

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + # 1]- (RX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used + # PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + # G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + # Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + # er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0 + + # Configures MIO Pin 60 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000004U) */ + mask_write 0XFF1800F0 0x000000FE 0x00000004 + # Register : MIO_PIN_61 @ 0XFF1800F4

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + # 2]- (RX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used + # PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + # TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, + # spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + # (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + # ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0 + + # Configures MIO Pin 61 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000004U) */ + mask_write 0XFF1800F4 0x000000FE 0x00000004 + # Register : MIO_PIN_62 @ 0XFF1800F8

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + # 3]- (RX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used + # PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + # i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo + # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + # t, tracedq[8]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0 + + # Configures MIO Pin 62 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000004U) */ + mask_write 0XFF1800F8 0x000000FE 0x00000004 + # Register : MIO_PIN_63 @ 0XFF1800FC

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + # tl- (RX RGMII control ) + # PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used + # PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + # 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + # tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0 + + # Configures MIO Pin 63 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000004U) */ + mask_write 0XFF1800FC 0x000000FE 0x00000004 + # Register : MIO_PIN_64 @ 0XFF180100

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + # clk- (TX RGMII clock) + # PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i + # n- (ULPI Clock) + # PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + # (SDSDIO clock) 2= Not Used 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4 + # = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- + # (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + # trace, Output, tracedq[10]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0 + + # Configures MIO Pin 64 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180100, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180100 0x000000FE 0x00000002 + # Register : MIO_PIN_65 @ 0XFF180104

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + # [0]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- + # (Data bus direction control) + # PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + # card detect from connector) 2= Not Used 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M + # aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u + # a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace + # dq[11]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0 + + # Configures MIO Pin 65 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180104, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180104 0x000000FE 0x00000002 + # Register : MIO_PIN_66 @ 0XFF180108

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + # [1]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + # mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not + # Used 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast + # er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + # rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace + # Port Databus) + # PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0 + + # Configures MIO Pin 66 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180108, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180108 0x000000FE 0x00000002 + # Register : MIO_PIN_67 @ 0XFF18010C

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + # [2]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- + # (Data flow control signal from the PHY) + # PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N + # ot Used 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste + # r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt + # c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + # (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace + # Port Databus) + # PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0 + + # Configures MIO Pin 67 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF18010C, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF18010C 0x000000FE 0x00000002 + # Register : MIO_PIN_68 @ 0XFF180110

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + # [3]- (TX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N + # ot Used 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + # pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + # ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + # Output, tracedq[14]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0 + + # Configures MIO Pin 68 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180110, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180110 0x000000FE 0x00000002 + # Register : MIO_PIN_69 @ 0XFF180114

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + # ctl- (TX RGMII control) + # PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + # d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + # = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + # TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + # 7= trace, Output, tracedq[15]- (Trace Port Databus) + # PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0 + + # Configures MIO Pin 69 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180114, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180114 0x000000FE 0x00000002 + # Register : MIO_PIN_70 @ 0XFF180118

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + # lk- (RX RGMII clock) + # PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- + # (Asserted to end or interrupt transfers) + # PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + # d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + # spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + # TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + # sed + # PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0 + + # Configures MIO Pin 70 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180118, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180118 0x000000FE 0x00000002 + # Register : MIO_PIN_71 @ 0XFF18011C

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + # 0]- (RX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[0]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + # Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= + # ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0 + + # Configures MIO Pin 71 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF18011C, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF18011C 0x000000FE 0x00000002 + # Register : MIO_PIN_72 @ 0XFF180120

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + # 1]- (RX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[1]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + # ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri + # al output) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0 + + # Configures MIO Pin 72 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180120, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180120 0x000000FE 0x00000002 + # Register : MIO_PIN_73 @ 0XFF180124

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + # 2]- (RX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[2]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + # Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not + # Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0 + + # Configures MIO Pin 73 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180124, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180124 0x000000FE 0x00000002 + # Register : MIO_PIN_74 @ 0XFF180128

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + # 3]- (RX RGMII data) + # PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[3]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + # i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- ( + # UART receiver serial input) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0 + + # Configures MIO Pin 74 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180128, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF180128 0x000000FE 0x00000002 + # Register : MIO_PIN_75 @ 0XFF18012C

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + # tl- (RX RGMII control ) + # PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data + # bus) + # PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + # (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1 + # , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + # 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t + # xd- (UART transmitter serial output) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0 + + # Configures MIO Pin 75 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF18012C, 0x000000FEU ,0x00000002U) */ + mask_write 0XFF18012C 0x000000FE 0x00000002 + # Register : MIO_PIN_76 @ 0XFF180130

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_76_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + # rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO + # clock) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI + # O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2 + # _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6 + + # Configures MIO Pin 76 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180130, 0x000000FEU ,0x000000C0U) */ + mask_write 0XFF180130 0x000000FE 0x000000C0 + # Register : MIO_PIN_77 @ 0XFF180134

    + + # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_77_L0_SEL 0 + + # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + # PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0 + + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio + # 1_cd_n- (SD card detect from connector) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0 + + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M + # DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, + # gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5 + # = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou + # t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp + # ut, gem3_mdio_out- (MDIO Data) 7= Not Used + # PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6 + + # Configures MIO Pin 77 peripheral interface mapping + #(OFFSET, MASK, VALUE) (0XFF180134, 0x000000FEU ,0x000000C0U) */ + mask_write 0XFF180134 0x000000FE 0x000000C0 + # Register : MIO_MST_TRI0 @ 0XFF180204

    + + # Master Tri-state Enable for pin 0, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI 0 + + # Master Tri-state Enable for pin 1, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI 0 + + # Master Tri-state Enable for pin 2, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI 0 + + # Master Tri-state Enable for pin 3, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI 0 + + # Master Tri-state Enable for pin 4, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI 0 + + # Master Tri-state Enable for pin 5, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI 0 + + # Master Tri-state Enable for pin 6, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI 0 + + # Master Tri-state Enable for pin 7, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI 0 + + # Master Tri-state Enable for pin 8, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI 0 + + # Master Tri-state Enable for pin 9, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI 0 + + # Master Tri-state Enable for pin 10, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI 0 + + # Master Tri-state Enable for pin 11, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI 0 + + # Master Tri-state Enable for pin 12, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI 0 + + # Master Tri-state Enable for pin 13, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI 0 + + # Master Tri-state Enable for pin 14, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI 0 + + # Master Tri-state Enable for pin 15, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI 0 + + # Master Tri-state Enable for pin 16, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI 0 + + # Master Tri-state Enable for pin 17, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI 0 + + # Master Tri-state Enable for pin 18, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI 1 + + # Master Tri-state Enable for pin 19, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI 0 + + # Master Tri-state Enable for pin 20, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI 0 + + # Master Tri-state Enable for pin 21, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI 1 + + # Master Tri-state Enable for pin 22, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI 0 + + # Master Tri-state Enable for pin 23, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI 0 + + # Master Tri-state Enable for pin 24, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI 0 + + # Master Tri-state Enable for pin 25, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1 + + # Master Tri-state Enable for pin 26, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0 + + # Master Tri-state Enable for pin 27, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0 + + # Master Tri-state Enable for pin 28, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1 + + # Master Tri-state Enable for pin 29, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0 + + # Master Tri-state Enable for pin 30, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1 + + # Master Tri-state Enable for pin 31, active high + # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0 + + # MIO pin Tri-state Enables, 31:0 + #(OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U) */ + mask_write 0XFF180204 0xFFFFFFFF 0x52240000 + # Register : MIO_MST_TRI1 @ 0XFF180208

    + + # Master Tri-state Enable for pin 32, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI 0 + + # Master Tri-state Enable for pin 33, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI 0 + + # Master Tri-state Enable for pin 34, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI 0 + + # Master Tri-state Enable for pin 35, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI 0 + + # Master Tri-state Enable for pin 36, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI 0 + + # Master Tri-state Enable for pin 37, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI 0 + + # Master Tri-state Enable for pin 38, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI 0 + + # Master Tri-state Enable for pin 39, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI 0 + + # Master Tri-state Enable for pin 40, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI 0 + + # Master Tri-state Enable for pin 41, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI 0 + + # Master Tri-state Enable for pin 42, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI 0 + + # Master Tri-state Enable for pin 43, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI 0 + + # Master Tri-state Enable for pin 44, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI 1 + + # Master Tri-state Enable for pin 45, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI 1 + + # Master Tri-state Enable for pin 46, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI 0 + + # Master Tri-state Enable for pin 47, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI 0 + + # Master Tri-state Enable for pin 48, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI 0 + + # Master Tri-state Enable for pin 49, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI 0 + + # Master Tri-state Enable for pin 50, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI 0 + + # Master Tri-state Enable for pin 51, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0 + + # Master Tri-state Enable for pin 52, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 1 + + # Master Tri-state Enable for pin 53, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 1 + + # Master Tri-state Enable for pin 54, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0 + + # Master Tri-state Enable for pin 55, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 1 + + # Master Tri-state Enable for pin 56, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0 + + # Master Tri-state Enable for pin 57, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0 + + # Master Tri-state Enable for pin 58, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0 + + # Master Tri-state Enable for pin 59, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0 + + # Master Tri-state Enable for pin 60, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0 + + # Master Tri-state Enable for pin 61, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0 + + # Master Tri-state Enable for pin 62, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0 + + # Master Tri-state Enable for pin 63, active high + # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0 + + # MIO pin Tri-state Enables, 63:32 + #(OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00B03000U) */ + mask_write 0XFF180208 0xFFFFFFFF 0x00B03000 + # Register : MIO_MST_TRI2 @ 0XFF18020C

    + + # Master Tri-state Enable for pin 64, active high + # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI 0 + + # Master Tri-state Enable for pin 65, active high + # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI 0 + + # Master Tri-state Enable for pin 66, active high + # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI 0 + + # Master Tri-state Enable for pin 67, active high + # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI 0 + + # Master Tri-state Enable for pin 68, active high + # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI 0 + + # Master Tri-state Enable for pin 69, active high + # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI 0 + + # Master Tri-state Enable for pin 70, active high + # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI 1 + + # Master Tri-state Enable for pin 71, active high + # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI 1 + + # Master Tri-state Enable for pin 72, active high + # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI 1 + + # Master Tri-state Enable for pin 73, active high + # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI 1 + + # Master Tri-state Enable for pin 74, active high + # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI 1 + + # Master Tri-state Enable for pin 75, active high + # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI 1 + + # Master Tri-state Enable for pin 76, active high + # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI 0 + + # Master Tri-state Enable for pin 77, active high + # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI 0 + + # MIO pin Tri-state Enables, 77:64 + #(OFFSET, MASK, VALUE) (0XFF18020C, 0x00003FFFU ,0x00000FC0U) */ + mask_write 0XFF18020C 0x00003FFF 0x00000FC0 + # Register : bank0_ctrl0 @ 0XFF180138

    + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25 1 + + # Drive0 control to MIO Bank 0 - control MIO[25:0] + #(OFFSET, MASK, VALUE) (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU) */ + mask_write 0XFF180138 0x03FFFFFF 0x03FFFFFF + # Register : bank0_ctrl1 @ 0XFF18013C

    + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25 1 + + # Drive1 control to MIO Bank 0 - control MIO[25:0] + #(OFFSET, MASK, VALUE) (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU) */ + mask_write 0XFF18013C 0x03FFFFFF 0x03FFFFFF + # Register : bank0_ctrl3 @ 0XFF180140

    + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0 0 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19 0 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20 0 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25 1 + + # Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0] + #(OFFSET, MASK, VALUE) (0XFF180140, 0x03FFFFFFU ,0x02E7EF1EU) */ + mask_write 0XFF180140 0x03FFFFFF 0x02E7EF1E + # Register : bank0_ctrl4 @ 0XFF180144

    + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + # When mio_bank0_pull_enable is set, this selects pull up or pull down for + # MIO Bank 0 - control MIO[25:0] + #(OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU) */ + mask_write 0XFF180144 0x03FFFFFF 0x03FFFFFF + # Register : bank0_ctrl5 @ 0XFF180148

    + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1 + + # When set, this enables mio_bank0_pullupdown to selects pull up or pull d + # own for MIO Bank 0 - control MIO[25:0] + #(OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU) */ + mask_write 0XFF180148 0x03FFFFFF 0x03FFFFFF + # Register : bank0_ctrl6 @ 0XFF18014C

    + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[0]. + # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 + + # Slew rate control to MIO Bank 0 - control MIO[25:0] + #(OFFSET, MASK, VALUE) (0XFF18014C, 0x03FFFFFFU ,0x01DBFFFFU) */ + mask_write 0XFF18014C 0x03FFFFFF 0x01DBFFFF + # Register : bank1_ctrl0 @ 0XFF180154

    + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25 1 + + # Drive0 control to MIO Bank 1 - control MIO[51:26] + #(OFFSET, MASK, VALUE) (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU) */ + mask_write 0XFF180154 0x03FFFFFF 0x03FFFFFF + # Register : bank1_ctrl1 @ 0XFF180158

    + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25 1 + + # Drive1 control to MIO Bank 1 - control MIO[51:26] + #(OFFSET, MASK, VALUE) (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU) */ + mask_write 0XFF180158 0x03FFFFFF 0x03FFFFFF + # Register : bank1_ctrl3 @ 0XFF18015C

    + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1 0 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3 0 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8 0 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9 0 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10 0 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11 0 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25 0 + + # Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26] + #(OFFSET, MASK, VALUE) (0XFF18015C, 0x03FFFFFFU ,0x01FDF015U) */ + mask_write 0XFF18015C 0x03FFFFFF 0x01FDF015 + # Register : bank1_ctrl4 @ 0XFF180160

    + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + # When mio_bank1_pull_enable is set, this selects pull up or pull down for + # MIO Bank 1 - control MIO[51:26] + #(OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU) */ + mask_write 0XFF180160 0x03FFFFFF 0x03FFFFFF + # Register : bank1_ctrl5 @ 0XFF180164

    + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1 + + # When set, this enables mio_bank1_pullupdown to selects pull up or pull d + # own for MIO Bank 1 - control MIO[51:26] + #(OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU) */ + mask_write 0XFF180164 0x03FFFFFF 0x03FFFFFF + # Register : bank1_ctrl6 @ 0XFF180168

    + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[26]. + # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25 1 + + # Slew rate control to MIO Bank 1 - control MIO[51:26] + #(OFFSET, MASK, VALUE) (0XFF180168, 0x03FFFFFFU ,0x03F3FFEBU) */ + mask_write 0XFF180168 0x03FFFFFF 0x03F3FFEB + # Register : bank2_ctrl0 @ 0XFF180170

    + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25 1 + + # Drive0 control to MIO Bank 2 - control MIO[77:52] + #(OFFSET, MASK, VALUE) (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU) */ + mask_write 0XFF180170 0x03FFFFFF 0x03FFFFFF + # Register : bank2_ctrl1 @ 0XFF180174

    + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25 1 + + # Drive1 control to MIO Bank 2 - control MIO[77:52] + #(OFFSET, MASK, VALUE) (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU) */ + mask_write 0XFF180174 0x03FFFFFF 0x03FFFFFF + # Register : bank2_ctrl3 @ 0XFF180178

    + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25 1 + + # Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52] + #(OFFSET, MASK, VALUE) (0XFF180178, 0x03FFFFFFU ,0x02FC0FBFU) */ + mask_write 0XFF180178 0x03FFFFFF 0x02FC0FBF + # Register : bank2_ctrl4 @ 0XFF18017C

    + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + # When mio_bank2_pull_enable is set, this selects pull up or pull down for + # MIO Bank 2 - control MIO[77:52] + #(OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU) */ + mask_write 0XFF18017C 0x03FFFFFF 0x03FFFFFF + # Register : bank2_ctrl5 @ 0XFF180180

    + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1 + + # When set, this enables mio_bank2_pullupdown to selects pull up or pull d + # own for MIO Bank 2 - control MIO[77:52] + #(OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU) */ + mask_write 0XFF180180 0x03FFFFFF 0x03FFFFFF + # Register : bank2_ctrl6 @ 0XFF180184

    + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24 1 + + # Each bit applies to a single IO. Bit 0 for MIO[52]. + # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25 1 + + # Slew rate control to MIO Bank 2 - control MIO[77:52] + #(OFFSET, MASK, VALUE) (0XFF180184, 0x03FFFFFFU ,0x0303FFF4U) */ + mask_write 0XFF180184 0x03FFFFFF 0x0303FFF4 + # : LOOPBACK + # Register : MIO_LOOPBACK @ 0XFF180200

    + + # I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 + # = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs + # . + # PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0 + + # CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 + # = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. + # PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0 + + # UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. + # 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 + # inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD + # and RI not used. + # PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0 + + # SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 + # = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs + # . The other SPI core will appear on the LS Slave Select. + # PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0 + + # Loopback function within MIO + #(OFFSET, MASK, VALUE) (0XFF180200, 0x0000000FU ,0x00000000U) */ + mask_write 0XFF180200 0x0000000F 0x00000000 +} + +set psu_peripherals_pre_init_data { + # : SYSMON CLOCK PRESET TO IOPLL AT 1500 MHZ FROM PBR TO MAKE AMS CLOCK UNDER RANGE + # Register : AMS_REF_CTRL @ 0XFF5E0108

    + + # 6 bit divider + # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 1 + + # 6 bit divider + # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 35 + + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 2 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_AMS_REF_CTRL_CLKACT 1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01012302U) */ + mask_write 0XFF5E0108 0x013F3F07 0x01012302 + # : PUT QSPI IN RESET STATE + # Register : RST_LPD_IOU2 @ 0XFF5E0238

    + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 1 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000001U) */ + mask_write 0XFF5E0238 0x00000001 0x00000001 +} + +set psu_peripherals_init_data { + # : COHERENCY + # : FPD RESET + # Register : RST_FPD_TOP @ 0XFD1A0100

    + + # PCIE config reset + # PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0 + + # PCIE control block level reset + # PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0 + + # PCIE bridge block level reset (AXI interface) + # PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0 + + # Display Port block level reset (includes DPDMA) + # PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0 + + # FPD WDT reset + # PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET 0 + + # GDMA block level reset + # PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET 0 + + # Pixel Processor (submodule of GPU) block level reset + # PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET 0 + + # Pixel Processor (submodule of GPU) block level reset + # PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET 0 + + # GPU block level reset + # PSU_CRF_APB_RST_FPD_TOP_GPU_RESET 0 + + # GT block level reset + # PSU_CRF_APB_RST_FPD_TOP_GT_RESET 0 + + # Sata block level reset + # PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0 + + # FPD Block level software controlled reset + #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U) */ + mask_write 0XFD1A0100 0x000F807E 0x00000000 + # : RESET BLOCKS + # : TIMESTAMP + # Register : RST_LPD_IOU2 @ 0XFF5E0238

    + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0 + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_IOU_CC_RESET 0 + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_ADMA_RESET 0 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x001A0000U ,0x00000000U) */ + mask_write 0XFF5E0238 0x001A0000 0x00000000 + # Register : RST_LPD_TOP @ 0XFF5E023C

    + + # Reset entire full power domain. + # PSU_CRL_APB_RST_LPD_TOP_FPD_RESET 0 + + # LPD SWDT + # PSU_CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET 0 + + # Sysmonitor reset + # PSU_CRL_APB_RST_LPD_TOP_SYSMON_RESET 0 + + # Real Time Clock reset + # PSU_CRL_APB_RST_LPD_TOP_RTC_RESET 0 + + # APM reset + # PSU_CRL_APB_RST_LPD_TOP_APM_RESET 0 + + # IPI reset + # PSU_CRL_APB_RST_LPD_TOP_IPI_RESET 0 + + # reset entire RPU power island + # PSU_CRL_APB_RST_LPD_TOP_RPU_PGE_RESET 0 + + # reset ocm + # PSU_CRL_APB_RST_LPD_TOP_OCM_RESET 0 + + # Software control register for the LPD block. + #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x0093C018U ,0x00000000U) */ + mask_write 0XFF5E023C 0x0093C018 0x00000000 + # : ENET + # Register : RST_LPD_IOU0 @ 0XFF5E0230

    + + # GEM 3 reset + # PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0 + + # Software controlled reset for the GEMs + #(OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) */ + mask_write 0XFF5E0230 0x00000008 0x00000000 + # : QSPI + # Register : RST_LPD_IOU2 @ 0XFF5E0238

    + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) */ + mask_write 0XFF5E0238 0x00000001 0x00000000 + # : QSPI TAP DELAY + # Register : IOU_TAPDLY_BYPASS @ 0XFF180390

    + + # 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa + # ss the Tap delay on the Rx clock signal of LQSPI + # PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 0 + + # IOU tap delay bypass for the LQSPI and NAND controllers + #(OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000000U) */ + mask_write 0XFF180390 0x00000004 0x00000000 + # : NAND + # : USB RESET + # Register : RST_LPD_TOP @ 0XFF5E023C

    + + # USB 0 reset for control registers + # PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0 + + # Software control register for the LPD block. + #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) */ + mask_write 0XFF5E023C 0x00000400 0x00000000 + # : SD + # Register : RST_LPD_IOU2 @ 0XFF5E0238

    + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U) */ + mask_write 0XFF5E0238 0x00000040 0x00000000 + # Register : CTRL_REG_SD @ 0XFF180310

    + + # SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled + # PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL 0 + + # SD eMMC selection + #(OFFSET, MASK, VALUE) (0XFF180310, 0x00008000U ,0x00000000U) */ + mask_write 0XFF180310 0x00008000 0x00000000 + # Register : SD_CONFIG_REG2 @ 0XFF180320

    + + # Should be set based on the final product usage 00 - Removable SCard Slot + # 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved + # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0 + + # 8-bit Support for Embedded Device 1: The Core supports 8-bit Interface 0 + # : Supports only 4-bit SD Interface + # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_8BIT 1 + + # 1.8V Support 1: 1.8V supported 0: 1.8V not supported support + # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 1 + + # 3.0V Support 1: 3.0V supported 0: 3.0V not supported support + # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0 + + # 3.3V Support 1: 3.3V supported 0: 3.3V not supported support + # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1 + + # SD Config Register 2 + #(OFFSET, MASK, VALUE) (0XFF180320, 0x33840000U ,0x02840000U) */ + mask_write 0XFF180320 0x33840000 0x02840000 + # : SD1 BASE CLOCK + # Register : SD_CONFIG_REG1 @ 0XFF18031C

    + + # Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. + # PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc8 + + # Configures the Number of Taps (Phases) of the rxclk_in that is supported + # . + # PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT 0x28 + + # SD Config Register 1 + #(OFFSET, MASK, VALUE) (0XFF18031C, 0x7FFE0000U ,0x64500000U) */ + mask_write 0XFF18031C 0x7FFE0000 0x64500000 + # Register : SD_DLL_CTRL @ 0XFF180358

    + + # Reserved. + # PSU_IOU_SLCR_SD_DLL_CTRL_RESERVED 1 + + # SDIO status register + #(OFFSET, MASK, VALUE) (0XFF180358, 0x00000008U ,0x00000008U) */ + mask_write 0XFF180358 0x00000008 0x00000008 + # : SD1 RETUNER + # Register : SD_CONFIG_REG3 @ 0XFF180324

    + + # This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S + # etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other + # source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n + # = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved + # PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0 + + # SD Config Register 3 + #(OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U) */ + mask_write 0XFF180324 0x03C00000 0x00000000 + # : CAN + # Register : RST_LPD_IOU2 @ 0XFF5E0238

    + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U) */ + mask_write 0XFF5E0238 0x00000100 0x00000000 + # : I2C + # Register : RST_LPD_IOU2 @ 0XFF5E0238

    + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET 0 + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U) */ + mask_write 0XFF5E0238 0x00000600 0x00000000 + # : SWDT + # Register : RST_LPD_IOU2 @ 0XFF5E0238

    + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U) */ + mask_write 0XFF5E0238 0x00008000 0x00000000 + # : SPI + # : TTC + # Register : RST_LPD_IOU2 @ 0XFF5E0238

    + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET 0 + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET 0 + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET 0 + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U) */ + mask_write 0XFF5E0238 0x00007800 0x00000000 + # : UART + # Register : RST_LPD_IOU2 @ 0XFF5E0238

    + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET 0 + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U) */ + mask_write 0XFF5E0238 0x00000006 0x00000000 + # : UART BAUD RATE + # Register : Baud_rate_divider_reg0 @ 0XFF000034

    + + # Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate + # PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV 0x6 + + # Baud Rate Divider Register + #(OFFSET, MASK, VALUE) (0XFF000034, 0x000000FFU ,0x00000006U) */ + mask_write 0XFF000034 0x000000FF 0x00000006 + # Register : Baud_rate_gen_reg0 @ 0XFF000018

    + + # Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + # bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + # PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x7c + + # Baud Rate Generator Register. + #(OFFSET, MASK, VALUE) (0XFF000018, 0x0000FFFFU ,0x0000007CU) */ + mask_write 0XFF000018 0x0000FFFF 0x0000007C + # Register : Control_reg0 @ 0XFF000000

    + + # Stop transmitter break: 0: no affect 1: stop transmission of the break a + # fter a minimum of one character length and transmit a high level during + # 12 bit periods. It can be set regardless of the value of STTBRK. + # PSU_UART0_CONTROL_REG0_STPBRK 0x0 + + # Start transmitter break: 0: no affect 1: start to transmit a break after + # the characters currently present in the FIFO and the transmit shift reg + # ister have been transmitted. It can only be set if STPBRK (Stop transmit + # ter break) is not high. + # PSU_UART0_CONTROL_REG0_STTBRK 0x0 + + # Restart receiver timeout counter: 1: receiver timeout counter is restart + # ed. This bit is self clearing once the restart has completed. + # PSU_UART0_CONTROL_REG0_RSTTO 0x0 + + # Transmit disable: 0: enable transmitter 1: disable transmitter + # PSU_UART0_CONTROL_REG0_TXDIS 0x0 + + # Transmit enable: 0: disable transmitter 1: enable transmitter, provided + # the TXDIS field is set to 0. + # PSU_UART0_CONTROL_REG0_TXEN 0x1 + + # Receive disable: 0: enable 1: disable, regardless of the value of RXEN + # PSU_UART0_CONTROL_REG0_RXDIS 0x0 + + # Receive enable: 0: disable 1: enable When set to one, the receiver logic + # is enabled, provided the RXDIS field is set to zero. + # PSU_UART0_CONTROL_REG0_RXEN 0x1 + + # Software reset for Tx data path: 0: no affect 1: transmitter logic is re + # set and all pending transmitter data is discarded This bit is self clear + # ing once the reset has completed. + # PSU_UART0_CONTROL_REG0_TXRES 0x1 + + # Software reset for Rx data path: 0: no affect 1: receiver logic is reset + # and all pending receiver data is discarded. This bit is self clearing o + # nce the reset has completed. + # PSU_UART0_CONTROL_REG0_RXRES 0x1 + + # UART Control Register + #(OFFSET, MASK, VALUE) (0XFF000000, 0x000001FFU ,0x00000017U) */ + mask_write 0XFF000000 0x000001FF 0x00000017 + # Register : mode_reg0 @ 0XFF000004

    + + # Channel mode: Defines the mode of operation of the UART. 00: normal 01: + # automatic echo 10: local loopback 11: remote loopback + # PSU_UART0_MODE_REG0_CHMODE 0x0 + + # Number of stop bits: Defines the number of stop bits to detect on receiv + # e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + # op bits 11: reserved + # PSU_UART0_MODE_REG0_NBSTOP 0x0 + + # Parity type select: Defines the expected parity to check on receive and + # the parity to generate on transmit. 000: even parity 001: odd parity 010 + # : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + # ty + # PSU_UART0_MODE_REG0_PAR 0x4 + + # Character length select: Defines the number of bits in each character. 1 + # 1: 6 bits 10: 7 bits 0x: 8 bits + # PSU_UART0_MODE_REG0_CHRL 0x0 + + # Clock source select: This field defines whether a pre-scalar of 8 is app + # lied to the baud rate generator input clock. 0: clock source is uart_ref + # _clk 1: clock source is uart_ref_clk/8 + # PSU_UART0_MODE_REG0_CLKS 0x0 + + # UART Mode Register + #(OFFSET, MASK, VALUE) (0XFF000004, 0x000003FFU ,0x00000020U) */ + mask_write 0XFF000004 0x000003FF 0x00000020 + # Register : Baud_rate_divider_reg0 @ 0XFF010034

    + + # Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate + # PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV 0x6 + + # Baud Rate Divider Register + #(OFFSET, MASK, VALUE) (0XFF010034, 0x000000FFU ,0x00000006U) */ + mask_write 0XFF010034 0x000000FF 0x00000006 + # Register : Baud_rate_gen_reg0 @ 0XFF010018

    + + # Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + # bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + # PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x7c + + # Baud Rate Generator Register. + #(OFFSET, MASK, VALUE) (0XFF010018, 0x0000FFFFU ,0x0000007CU) */ + mask_write 0XFF010018 0x0000FFFF 0x0000007C + # Register : Control_reg0 @ 0XFF010000

    + + # Stop transmitter break: 0: no affect 1: stop transmission of the break a + # fter a minimum of one character length and transmit a high level during + # 12 bit periods. It can be set regardless of the value of STTBRK. + # PSU_UART1_CONTROL_REG0_STPBRK 0x0 + + # Start transmitter break: 0: no affect 1: start to transmit a break after + # the characters currently present in the FIFO and the transmit shift reg + # ister have been transmitted. It can only be set if STPBRK (Stop transmit + # ter break) is not high. + # PSU_UART1_CONTROL_REG0_STTBRK 0x0 + + # Restart receiver timeout counter: 1: receiver timeout counter is restart + # ed. This bit is self clearing once the restart has completed. + # PSU_UART1_CONTROL_REG0_RSTTO 0x0 + + # Transmit disable: 0: enable transmitter 1: disable transmitter + # PSU_UART1_CONTROL_REG0_TXDIS 0x0 + + # Transmit enable: 0: disable transmitter 1: enable transmitter, provided + # the TXDIS field is set to 0. + # PSU_UART1_CONTROL_REG0_TXEN 0x1 + + # Receive disable: 0: enable 1: disable, regardless of the value of RXEN + # PSU_UART1_CONTROL_REG0_RXDIS 0x0 + + # Receive enable: 0: disable 1: enable When set to one, the receiver logic + # is enabled, provided the RXDIS field is set to zero. + # PSU_UART1_CONTROL_REG0_RXEN 0x1 + + # Software reset for Tx data path: 0: no affect 1: transmitter logic is re + # set and all pending transmitter data is discarded This bit is self clear + # ing once the reset has completed. + # PSU_UART1_CONTROL_REG0_TXRES 0x1 + + # Software reset for Rx data path: 0: no affect 1: receiver logic is reset + # and all pending receiver data is discarded. This bit is self clearing o + # nce the reset has completed. + # PSU_UART1_CONTROL_REG0_RXRES 0x1 + + # UART Control Register + #(OFFSET, MASK, VALUE) (0XFF010000, 0x000001FFU ,0x00000017U) */ + mask_write 0XFF010000 0x000001FF 0x00000017 + # Register : mode_reg0 @ 0XFF010004

    + + # Channel mode: Defines the mode of operation of the UART. 00: normal 01: + # automatic echo 10: local loopback 11: remote loopback + # PSU_UART1_MODE_REG0_CHMODE 0x0 + + # Number of stop bits: Defines the number of stop bits to detect on receiv + # e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + # op bits 11: reserved + # PSU_UART1_MODE_REG0_NBSTOP 0x0 + + # Parity type select: Defines the expected parity to check on receive and + # the parity to generate on transmit. 000: even parity 001: odd parity 010 + # : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + # ty + # PSU_UART1_MODE_REG0_PAR 0x4 + + # Character length select: Defines the number of bits in each character. 1 + # 1: 6 bits 10: 7 bits 0x: 8 bits + # PSU_UART1_MODE_REG0_CHRL 0x0 + + # Clock source select: This field defines whether a pre-scalar of 8 is app + # lied to the baud rate generator input clock. 0: clock source is uart_ref + # _clk 1: clock source is uart_ref_clk/8 + # PSU_UART1_MODE_REG0_CLKS 0x0 + + # UART Mode Register + #(OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U) */ + mask_write 0XFF010004 0x000003FF 0x00000020 + # : GPIO + # Register : RST_LPD_IOU2 @ 0XFF5E0238

    + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_GPIO_RESET 0 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00040000U ,0x00000000U) */ + mask_write 0XFF5E0238 0x00040000 0x00000000 + # : ADMA TZ + # Register : slcr_adma @ 0XFF4B0024

    + + # TrustZone Classification for ADMA + # PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0XFF + + # RPU TrustZone settings + #(OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) */ + mask_write 0XFF4B0024 0x000000FF 0x000000FF + # : CSU TAMPERING + # : CSU TAMPER STATUS + # Register : tamper_status @ 0XFFCA5000

    + + # CSU regsiter + # PSU_CSU_TAMPER_STATUS_TAMPER_0 0 + + # External MIO + # PSU_CSU_TAMPER_STATUS_TAMPER_1 0 + + # JTAG toggle detect + # PSU_CSU_TAMPER_STATUS_TAMPER_2 0 + + # PL SEU error + # PSU_CSU_TAMPER_STATUS_TAMPER_3 0 + + # AMS over temperature alarm for LPD + # PSU_CSU_TAMPER_STATUS_TAMPER_4 0 + + # AMS over temperature alarm for APU + # PSU_CSU_TAMPER_STATUS_TAMPER_5 0 + + # AMS voltage alarm for VCCPINT_FPD + # PSU_CSU_TAMPER_STATUS_TAMPER_6 0 + + # AMS voltage alarm for VCCPINT_LPD + # PSU_CSU_TAMPER_STATUS_TAMPER_7 0 + + # AMS voltage alarm for VCCPAUX + # PSU_CSU_TAMPER_STATUS_TAMPER_8 0 + + # AMS voltage alarm for DDRPHY + # PSU_CSU_TAMPER_STATUS_TAMPER_9 0 + + # AMS voltage alarm for PSIO bank 0/1/2 + # PSU_CSU_TAMPER_STATUS_TAMPER_10 0 + + # AMS voltage alarm for PSIO bank 3 (dedicated pins) + # PSU_CSU_TAMPER_STATUS_TAMPER_11 0 + + # AMS voltaage alarm for GT + # PSU_CSU_TAMPER_STATUS_TAMPER_12 0 + + # Tamper Response Status + #(OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U) */ + mask_write 0XFFCA5000 0x00001FFF 0x00000000 + # : CSU TAMPER RESPONSE + # : CPU QOS DEFAULT + # Register : ACE_CTRL @ 0XFD5C0060

    + + # Set ACE outgoing AWQOS value + # PSU_APU_ACE_CTRL_AWQOS 0X0 + + # Set ACE outgoing ARQOS value + # PSU_APU_ACE_CTRL_ARQOS 0X0 + + # ACE Control Register + #(OFFSET, MASK, VALUE) (0XFD5C0060, 0x000F000FU ,0x00000000U) */ + mask_write 0XFD5C0060 0x000F000F 0x00000000 + # : ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE + # Register : CONTROL @ 0XFFA60040

    + + # Enables the RTC. By writing a 0 to this bit, RTC will be powered off and + # the only module that potentially draws current from the battery will be + # BBRAM. The value read through this bit does not necessarily reflect whe + # ther RTC is enabled or not. It is expected that RTC is enabled every tim + # e it is being configured. If RTC is not used in the design, FSBL will di + # sable it by writing a 0 to this bit. + # PSU_RTC_CONTROL_BATTERY_DISABLE 0X1 + + # This register controls various functionalities within the RTC + #(OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U) */ + mask_write 0XFFA60040 0x80000000 0x80000000 + # : TIMESTAMP COUNTER + # Register : base_frequency_ID_register @ 0XFF260020

    + + # Frequency in number of ticks per second. Valid range from 10 MHz to 100 + # MHz. + # PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5dd18 + + # Program this register to match the clock frequency of the timestamp gene + # rator, in ticks per second. For example, for a 50 MHz clock, program 0x0 + # 2FAF080. This register is not accessible to the read-only programming in + # terface. + #(OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5DD18U) */ + mask_write 0XFF260020 0xFFFFFFFF 0x05F5DD18 + # Register : counter_control_register @ 0XFF260000

    + + # Enable 0: The counter is disabled and not incrementing. 1: The counter i + # s enabled and is incrementing. + # PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1 + + # Controls the counter increments. This register is not accessible to the + # read-only programming interface. + #(OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U) */ + mask_write 0XFF260000 0x00000001 0x00000001 + # : TTC SRC SELECT + # : USB RESET + # : USB RESET WITH BOOT PIN MODE + # : BOOT PIN HIGH + # Register : BOOT_PIN_CTRL @ 0XFF5E0250

    + + # Value driven onto the mode pins, when out_en = 1 + # PSU_CRL_APB_BOOT_PIN_CTRL_OUT_VAL 0X2 + + # When 0, the pins will be inputs from the board to the PS. When 1, the PS + # will drive these pins + # PSU_CRL_APB_BOOT_PIN_CTRL_OUT_EN 0X2 + + # Used to control the mode pins after boot. + #(OFFSET, MASK, VALUE) (0XFF5E0250, 0x00000F0FU ,0x00000202U) */ + mask_write 0XFF5E0250 0x00000F0F 0x00000202 + # : ADD 1US DELAY + mask_delay 0x00000000 1 + # : BOOT PIN LOW + # Register : BOOT_PIN_CTRL @ 0XFF5E0250

    + + # Value driven onto the mode pins, when out_en = 1 + # PSU_CRL_APB_BOOT_PIN_CTRL_OUT_VAL 0X0 + + # When 0, the pins will be inputs from the board to the PS. When 1, the PS + # will drive these pins + # PSU_CRL_APB_BOOT_PIN_CTRL_OUT_EN 0X2 + + # Used to control the mode pins after boot. + #(OFFSET, MASK, VALUE) (0XFF5E0250, 0x00000F0FU ,0x00000002U) */ + mask_write 0XFF5E0250 0x00000F0F 0x00000002 + # : ADD 5US DELAY + mask_delay 0x00000000 5 + # : BOOT PIN HIGH + # Register : BOOT_PIN_CTRL @ 0XFF5E0250

    + + # Value driven onto the mode pins, when out_en = 1 + # PSU_CRL_APB_BOOT_PIN_CTRL_OUT_VAL 0X2 + + # When 0, the pins will be inputs from the board to the PS. When 1, the PS + # will drive these pins + # PSU_CRL_APB_BOOT_PIN_CTRL_OUT_EN 0X2 + + # Used to control the mode pins after boot. + #(OFFSET, MASK, VALUE) (0XFF5E0250, 0x00000F0FU ,0x00000202U) */ + mask_write 0XFF5E0250 0x00000F0F 0x00000202 + # : PCIE RESET + # : DIR MODE BANK 0 + # : DIR MODE BANK 1 + # Register : DIRM_1 @ 0XFF0A0244

    + + # Operation is the same as DIRM_0[DIRECTION_0] + # PSU_GPIO_DIRM_1_DIRECTION_1 0x20 + + # Direction mode (GPIO Bank1, MIO) + #(OFFSET, MASK, VALUE) (0XFF0A0244, 0x03FFFFFFU ,0x00000020U) */ + mask_write 0XFF0A0244 0x03FFFFFF 0x00000020 + # : DIR MODE BANK 2 + # : OUTPUT ENABLE BANK 0 + # : OUTPUT ENABLE BANK 1 + # Register : OEN_1 @ 0XFF0A0248

    + + # Operation is the same as OEN_0[OP_ENABLE_0] + # PSU_GPIO_OEN_1_OP_ENABLE_1 0x20 + + # Output enable (GPIO Bank1, MIO) + #(OFFSET, MASK, VALUE) (0XFF0A0248, 0x03FFFFFFU ,0x00000020U) */ + mask_write 0XFF0A0248 0x03FFFFFF 0x00000020 + # : OUTPUT ENABLE BANK 2 + # : MASK_DATA_0_LSW LOW BANK [15:0] + # : MASK_DATA_0_MSW LOW BANK [25:16] + # : MASK_DATA_1_LSW LOW BANK [41:26] + # Register : MASK_DATA_1_LSW @ 0XFF0A0008

    + + # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + # Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + # Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + #(OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) */ + mask_write 0XFF0A0008 0xFFFFFFFF 0xFFDF0020 + # : MASK_DATA_1_MSW HIGH BANK [51:42] + # : MASK_DATA_1_LSW HIGH BANK [67:52] + # : MASK_DATA_1_LSW HIGH BANK [77:68] + # : ADD 1US DELAY + mask_delay 0x00000000 1 + # : MASK_DATA_0_LSW LOW BANK [15:0] + # : MASK_DATA_0_MSW LOW BANK [25:16] + # : MASK_DATA_1_LSW LOW BANK [41:26] + # Register : MASK_DATA_1_LSW @ 0XFF0A0008

    + + # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + # Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x0 + + # Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + #(OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0000U) */ + mask_write 0XFF0A0008 0xFFFFFFFF 0xFFDF0000 + # : MASK_DATA_1_MSW HIGH BANK [51:42] + # : MASK_DATA_1_LSW HIGH BANK [67:52] + # : MASK_DATA_1_LSW HIGH BANK [77:68] + # : ADD 5US DELAY + mask_delay 0x00000000 5 + # : GPIO POLARITY INITIALIZATION + # Register : DIRM_1 @ 0XFF0A0244

    + + # Operation is the same as DIRM_0[DIRECTION_0] + # PSU_GPIO_DIRM_1_DIRECTION_1 0x20 + + # Direction mode (GPIO Bank1, MIO) + #(OFFSET, MASK, VALUE) (0XFF0A0244, 0x03FFFFFFU ,0x00000020U) */ + mask_write 0XFF0A0244 0x03FFFFFF 0x00000020 + # Register : OEN_1 @ 0XFF0A0248

    + + # Operation is the same as OEN_0[OP_ENABLE_0] + # PSU_GPIO_OEN_1_OP_ENABLE_1 0x20 + + # Output enable (GPIO Bank1, MIO) + #(OFFSET, MASK, VALUE) (0XFF0A0248, 0x03FFFFFFU ,0x00000020U) */ + mask_write 0XFF0A0248 0x03FFFFFF 0x00000020 + # Register : MASK_DATA_1_LSW @ 0XFF0A0008

    + + # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + # Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x0 + + # Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + #(OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0000U) */ + mask_write 0XFF0A0008 0xFFFFFFFF 0xFFDF0000 +} + +set psu_post_config_data { + # : POST_CONFIG +} + +set psu_peripherals_powerdwn_data { + # : POWER DOWN REQUEST INTERRUPT ENABLE + # : POWER DOWN TRIGGER +} + +set psu_lpd_xppu_data { + # : MASTER ID LIST + # : APERTURE PERMISIION LIST + # : APERTURE NAME: UART0, START ADDRESS: FF000000, END ADDRESS: FF00FFFF + # : APERTURE NAME: UART1, START ADDRESS: FF010000, END ADDRESS: FF01FFFF + # : APERTURE NAME: I2C0, START ADDRESS: FF020000, END ADDRESS: FF02FFFF + # : APERTURE NAME: I2C1, START ADDRESS: FF030000, END ADDRESS: FF03FFFF + # : APERTURE NAME: SPI0, START ADDRESS: FF040000, END ADDRESS: FF04FFFF + # : APERTURE NAME: SPI1, START ADDRESS: FF050000, END ADDRESS: FF05FFFF + # : APERTURE NAME: CAN0, START ADDRESS: FF060000, END ADDRESS: FF06FFFF + # : APERTURE NAME: CAN1, START ADDRESS: FF070000, END ADDRESS: FF07FFFF + # : APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09FFFF + # : APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09FFFF + # : APERTURE NAME: GPIO, START ADDRESS: FF0A0000, END ADDRESS: FF0AFFFF + # : APERTURE NAME: GEM0, START ADDRESS: FF0B0000, END ADDRESS: FF0BFFFF + # : APERTURE NAME: GEM1, START ADDRESS: FF0C0000, END ADDRESS: FF0CFFFF + # : APERTURE NAME: GEM2, START ADDRESS: FF0D0000, END ADDRESS: FF0DFFFF + # : APERTURE NAME: GEM3, START ADDRESS: FF0E0000, END ADDRESS: FF0EFFFF + # : APERTURE NAME: QSPI, START ADDRESS: FF0F0000, END ADDRESS: FF0FFFFF + # : APERTURE NAME: NAND, START ADDRESS: FF100000, END ADDRESS: FF10FFFF + # : APERTURE NAME: TTC0, START ADDRESS: FF110000, END ADDRESS: FF11FFFF + # : APERTURE NAME: TTC1, START ADDRESS: FF120000, END ADDRESS: FF12FFFF + # : APERTURE NAME: TTC2, START ADDRESS: FF130000, END ADDRESS: FF13FFFF + # : APERTURE NAME: TTC3, START ADDRESS: FF140000, END ADDRESS: FF14FFFF + # : APERTURE NAME: SWDT, START ADDRESS: FF150000, END ADDRESS: FF15FFFF + # : APERTURE NAME: SD0, START ADDRESS: FF160000, END ADDRESS: FF16FFFF + # : APERTURE NAME: SD1, START ADDRESS: FF170000, END ADDRESS: FF17FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SECURE_SLCR, START ADDRESS: FF240000, END ADDRESS: FF24FFFF + # : APERTURE NAME: IOU_SCNTR, START ADDRESS: FF250000, END ADDRESS: FF25FFFF + # : APERTURE NAME: IOU_SCNTRS, START ADDRESS: FF260000, END ADDRESS: FF26FFFF + # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF + # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF + # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF + # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF + # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF + # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF + # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF + # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF + # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: LPD_UNUSED_1, START ADDRESS: FF400000, END ADDRESS: FF40FFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF + # : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF + # : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: OCM_SLCR, START ADDRESS: FF960000, END ADDRESS: FF96FFFF + # : APERTURE NAME: LPD_UNUSED_4, START ADDRESS: FF970000, END ADDRESS: FF97FFFF + # : APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + # : APERTURE NAME: RPU, START ADDRESS: FF9A0000, END ADDRESS: FF9AFFFF + # : APERTURE NAME: AFIFM6, START ADDRESS: FF9B0000, END ADDRESS: FF9BFFFF + # : APERTURE NAME: LPD_XPPU_SINK, START ADDRESS: FF9C0000, END ADDRESS: FF9CFFFF + # : APERTURE NAME: USB3_0, START ADDRESS: FF9D0000, END ADDRESS: FF9DFFFF + # : APERTURE NAME: USB3_1, START ADDRESS: FF9E0000, END ADDRESS: FF9EFFFF + # : APERTURE NAME: LPD_UNUSED_5, START ADDRESS: FF9F0000, END ADDRESS: FF9FFFFF + # : APERTURE NAME: APM0, START ADDRESS: FFA00000, END ADDRESS: FFA0FFFF + # : APERTURE NAME: APM1, START ADDRESS: FFA10000, END ADDRESS: FFA1FFFF + # : APERTURE NAME: APM_INTC_IOU, START ADDRESS: FFA20000, END ADDRESS: FFA2FFFF + # : APERTURE NAME: APM_FPD_LPD, START ADDRESS: FFA30000, END ADDRESS: FFA3FFFF + # : APERTURE NAME: LPD_UNUSED_6, START ADDRESS: FFA40000, END ADDRESS: FFA4FFFF + # : APERTURE NAME: AMS, START ADDRESS: FFA50000, END ADDRESS: FFA5FFFF + # : APERTURE NAME: RTC, START ADDRESS: FFA60000, END ADDRESS: FFA6FFFF + # : APERTURE NAME: OCM_XMPU_CFG, START ADDRESS: FFA70000, END ADDRESS: FFA7FFFF + # : APERTURE NAME: ADMA_0, START ADDRESS: FFA80000, END ADDRESS: FFA8FFFF + # : APERTURE NAME: ADMA_1, START ADDRESS: FFA90000, END ADDRESS: FFA9FFFF + # : APERTURE NAME: ADMA_2, START ADDRESS: FFAA0000, END ADDRESS: FFAAFFFF + # : APERTURE NAME: ADMA_3, START ADDRESS: FFAB0000, END ADDRESS: FFABFFFF + # : APERTURE NAME: ADMA_4, START ADDRESS: FFAC0000, END ADDRESS: FFACFFFF + # : APERTURE NAME: ADMA_5, START ADDRESS: FFAD0000, END ADDRESS: FFADFFFF + # : APERTURE NAME: ADMA_6, START ADDRESS: FFAE0000, END ADDRESS: FFAEFFFF + # : APERTURE NAME: ADMA_7, START ADDRESS: FFAF0000, END ADDRESS: FFAFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + # : APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + # : APERTURE NAME: CSU_LOCAL, START ADDRESS: FFC20000, END ADDRESS: FFC2FFFF + # : APERTURE NAME: PUF, START ADDRESS: FFC30000, END ADDRESS: FFC3FFFF + # : APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + # : APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + # : APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7FFFF + # : APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7FFFF + # : APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + # : APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + # : APERTURE NAME: CSU, START ADDRESS: FFCA0000, END ADDRESS: FFCAFFFF + # : APERTURE NAME: CSU_WDT, START ADDRESS: FFCB0000, END ADDRESS: FFCBFFFF + # : APERTURE NAME: EFUSE, START ADDRESS: FFCC0000, END ADDRESS: FFCCFFFF + # : APERTURE NAME: BBRAM, START ADDRESS: FFCD0000, END ADDRESS: FFCDFFFF + # : APERTURE NAME: RSA_CORE, START ADDRESS: FFCE0000, END ADDRESS: FFCEFFFF + # : APERTURE NAME: MBISTJTAG, START ADDRESS: FFCF0000, END ADDRESS: FFCFFFFF + # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + # : APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5FFFF + # : APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5FFFF + # : APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + # : APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF + # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF + # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF + # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF + # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + # : APERTURE NAME: R5_0_ATCM, START ADDRESS: FFE00000, END ADDRESS: FFE0FFFF + # : APERTURE NAME: R5_0_ATCM_LOCKSTEP, START ADDRESS: FFE10000, END ADDRESS: FFE1FFFF + # : APERTURE NAME: R5_0_BTCM, START ADDRESS: FFE20000, END ADDRESS: FFE2FFFF + # : APERTURE NAME: R5_0_BTCM_LOCKSTEP, START ADDRESS: FFE30000, END ADDRESS: FFE3FFFF + # : APERTURE NAME: R5_0_INSTRUCTION_CACHE, START ADDRESS: FFE40000, END ADDRESS: FFE4FFFF + # : APERTURE NAME: R5_0_DATA_CACHE, START ADDRESS: FFE50000, END ADDRESS: FFE5FFFF + # : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF + # : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF + # : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF + # : APERTURE NAME: R5_1_ATCM_, START ADDRESS: FFE90000, END ADDRESS: FFE9FFFF + # : APERTURE NAME: RPU_UNUSED_10, START ADDRESS: FFEA0000, END ADDRESS: FFEAFFFF + # : APERTURE NAME: R5_1_BTCM_, START ADDRESS: FFEB0000, END ADDRESS: FFEBFFFF + # : APERTURE NAME: R5_1_INSTRUCTION_CACHE, START ADDRESS: FFEC0000, END ADDRESS: FFECFFFF + # : APERTURE NAME: R5_1_DATA_CACHE, START ADDRESS: FFED0000, END ADDRESS: FFEDFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF + # : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF + # : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IOU_GPV, START ADDRESS: FE000000, END ADDRESS: FE0FFFFF + # : APERTURE NAME: LPD_GPV, START ADDRESS: FE100000, END ADDRESS: FE1FFFFF + # : APERTURE NAME: USB3_0_XHCI, START ADDRESS: FE200000, END ADDRESS: FE2FFFFF + # : APERTURE NAME: USB3_1_XHCI, START ADDRESS: FE300000, END ADDRESS: FE3FFFFF + # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF + # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF + # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF + # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: QSPI_LINEAR_ADDRESS, START ADDRESS: C0000000, END ADDRESS: DFFFFFFF + # : XPPU CONTROL +} + +set psu_ddr_xmpu0_data { + # : DDR XMPU0 +} + +set psu_ddr_xmpu1_data { + # : DDR XMPU1 +} + +set psu_ddr_xmpu2_data { + # : DDR XMPU2 +} + +set psu_ddr_xmpu3_data { + # : DDR XMPU3 +} + +set psu_ddr_xmpu4_data { + # : DDR XMPU4 +} + +set psu_ddr_xmpu5_data { + # : DDR XMPU5 +} + +set psu_ocm_xmpu_data { + # : OCM XMPU +} + +set psu_fpd_xmpu_data { + # : FPD XMPU +} + +set psu_protection_lock_data { + # : LOCKING PROTECTION MODULE + # : XPPU LOCK + # : APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + # : XMPU LOCK + # : LOCK OCM XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK FPD XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER +} + +set psu_apply_master_tz { + # : RPU + # : DP TZ + # Register : slcr_dpdma @ 0XFD690040

    + + # TrustZone classification for DisplayPort DMA + # PSU_FPD_SLCR_SECURE_SLCR_DPDMA_TZ 1 + + # DPDMA TrustZone Settings + #(OFFSET, MASK, VALUE) (0XFD690040, 0x00000001U ,0x00000001U) */ + mask_write 0XFD690040 0x00000001 0x00000001 + # : SATA TZ + # : PCIE TZ + # Register : slcr_pcie @ 0XFD690030

    + + # TrustZone classification for DMA Channel 0 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0 1 + + # TrustZone classification for DMA Channel 1 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1 1 + + # TrustZone classification for DMA Channel 2 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2 1 + + # TrustZone classification for DMA Channel 3 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3 1 + + # TrustZone classification for Ingress Address Translation 0 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0 1 + + # TrustZone classification for Ingress Address Translation 1 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1 1 + + # TrustZone classification for Ingress Address Translation 2 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2 1 + + # TrustZone classification for Ingress Address Translation 3 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3 1 + + # TrustZone classification for Ingress Address Translation 4 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4 1 + + # TrustZone classification for Ingress Address Translation 5 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5 1 + + # TrustZone classification for Ingress Address Translation 6 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6 1 + + # TrustZone classification for Ingress Address Translation 7 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7 1 + + # TrustZone classification for Egress Address Translation 0 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0 1 + + # TrustZone classification for Egress Address Translation 1 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1 1 + + # TrustZone classification for Egress Address Translation 2 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2 1 + + # TrustZone classification for Egress Address Translation 3 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3 1 + + # TrustZone classification for Egress Address Translation 4 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4 1 + + # TrustZone classification for Egress Address Translation 5 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5 1 + + # TrustZone classification for Egress Address Translation 6 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6 1 + + # TrustZone classification for Egress Address Translation 7 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7 1 + + # TrustZone classification for DMA Registers + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS 1 + + # TrustZone classification for MSIx Table + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE 1 + + # TrustZone classification for MSIx PBA + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA 1 + + # TrustZone classification for ECAM + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM 1 + + # TrustZone classification for Bridge Common Registers + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS 1 + + # PCIe TrustZone settings. This register may only be modified during bootu + # p (while PCIe block is disabled) + #(OFFSET, MASK, VALUE) (0XFD690030, 0x01FFFFFFU ,0x01FFFFFFU) */ + mask_write 0XFD690030 0x01FFFFFF 0x01FFFFFF + # : USB TZ + # Register : slcr_usb @ 0XFF4B0034

    + + # TrustZone Classification for USB3_0 + # PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0 1 + + # TrustZone Classification for USB3_1 + # PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1 1 + + # USB3 TrustZone settings + #(OFFSET, MASK, VALUE) (0XFF4B0034, 0x00000003U ,0x00000003U) */ + mask_write 0XFF4B0034 0x00000003 0x00000003 + # : SD TZ + # Register : IOU_AXI_RPRTCN @ 0XFF240004

    + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT 2 + + # AXI read protection type selection + #(OFFSET, MASK, VALUE) (0XFF240004, 0x003F0000U ,0x00120000U) */ + mask_write 0XFF240004 0x003F0000 0x00120000 + # Register : IOU_AXI_WPRTCN @ 0XFF240000

    + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT 2 + + # AXI write protection type selection + #(OFFSET, MASK, VALUE) (0XFF240000, 0x003F0000U ,0x00120000U) */ + mask_write 0XFF240000 0x003F0000 0x00120000 + # : GEM TZ + # Register : IOU_AXI_RPRTCN @ 0XFF240004

    + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT 2 + + # AXI read protection type selection + #(OFFSET, MASK, VALUE) (0XFF240004, 0x00000FFFU ,0x00000492U) */ + mask_write 0XFF240004 0x00000FFF 0x00000492 + # Register : IOU_AXI_WPRTCN @ 0XFF240000

    + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT 2 + + # AXI write protection type selection + #(OFFSET, MASK, VALUE) (0XFF240000, 0x00000FFFU ,0x00000492U) */ + mask_write 0XFF240000 0x00000FFF 0x00000492 + # : QSPI TZ + # Register : IOU_AXI_WPRTCN @ 0XFF240000

    + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT 2 + + # AXI write protection type selection + #(OFFSET, MASK, VALUE) (0XFF240000, 0x0E000000U ,0x04000000U) */ + mask_write 0XFF240000 0x0E000000 0x04000000 + # : NAND TZ + # Register : IOU_AXI_RPRTCN @ 0XFF240004

    + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT 2 + + # AXI read protection type selection + #(OFFSET, MASK, VALUE) (0XFF240004, 0x01C00000U ,0x00800000U) */ + mask_write 0XFF240004 0x01C00000 0x00800000 + # Register : IOU_AXI_WPRTCN @ 0XFF240000

    + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT 2 + + # AXI write protection type selection + #(OFFSET, MASK, VALUE) (0XFF240000, 0x01C00000U ,0x00800000U) */ + mask_write 0XFF240000 0x01C00000 0x00800000 + # : DMA TZ + # Register : slcr_adma @ 0XFF4B0024

    + + # TrustZone Classification for ADMA + # PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0xFF + + # RPU TrustZone settings + #(OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) */ + mask_write 0XFF4B0024 0x000000FF 0x000000FF + # Register : slcr_gdma @ 0XFD690050

    + + # TrustZone Classification for GDMA + # PSU_FPD_SLCR_SECURE_SLCR_GDMA_TZ 0xFF + + # GDMA Trustzone Settings + #(OFFSET, MASK, VALUE) (0XFD690050, 0x000000FFU ,0x000000FFU) */ + mask_write 0XFD690050 0x000000FF 0x000000FF +} + +set psu_serdes_init_data { + # : SERDES INITIALIZATION + # : GT REFERENCE CLOCK SOURCE SELECTION + # Register : PLL_REF_SEL0 @ 0XFD410000

    + + # PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + # eserved + # PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD + + # PLL0 Reference Selection Register + #(OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU) */ + mask_write 0XFD410000 0x0000001F 0x0000000D + # Register : PLL_REF_SEL1 @ 0XFD410004

    + + # PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + # eserved + # PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9 + + # PLL1 Reference Selection Register + #(OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U) */ + mask_write 0XFD410004 0x0000001F 0x00000009 + # Register : PLL_REF_SEL2 @ 0XFD410008

    + + # PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + # eserved + # PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8 + + # PLL2 Reference Selection Register + #(OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U) */ + mask_write 0XFD410008 0x0000001F 0x00000008 + # Register : PLL_REF_SEL3 @ 0XFD41000C

    + + # PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + # eserved + # PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF + + # PLL3 Reference Selection Register + #(OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU) */ + mask_write 0XFD41000C 0x0000001F 0x0000000F + # : GT REFERENCE CLOCK FREQUENCY SELECTION + # Register : L0_L0_REF_CLK_SEL @ 0XFD402860

    + + # Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp + # ut. Set to 0 to select lane0 ref clock mux output. + # PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1 + + # Lane0 Ref Clock Selection Register + #(OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U) */ + mask_write 0XFD402860 0x00000080 0x00000080 + # Register : L0_L1_REF_CLK_SEL @ 0XFD402864

    + + # Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp + # ut. Set to 0 to select lane1 ref clock mux output. + # PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0 + + # Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli + # cer output from ref clock network + # PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1 + + # Lane1 Ref Clock Selection Register + #(OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U) */ + mask_write 0XFD402864 0x00000088 0x00000008 + # Register : L0_L2_REF_CLK_SEL @ 0XFD402868

    + + # Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp + # ut. Set to 0 to select lane2 ref clock mux output. + # PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1 + + # Lane2 Ref Clock Selection Register + #(OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U) */ + mask_write 0XFD402868 0x00000080 0x00000080 + # Register : L0_L3_REF_CLK_SEL @ 0XFD40286C

    + + # Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp + # ut. Set to 0 to select lane3 ref clock mux output. + # PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0 + + # Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli + # cer output from ref clock network + # PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1 + + # Lane3 Ref Clock Selection Register + #(OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U) */ + mask_write 0XFD40286C 0x00000082 0x00000002 + # : ENABLE SPREAD SPECTRUM + # Register : L2_TM_PLL_DIG_37 @ 0XFD40A094

    + + # Enable/Disable coarse code satureation limiting logic + # PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1 + + # Test mode register 37 + #(OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U) */ + mask_write 0XFD40A094 0x00000010 0x00000010 + # Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368

    + + # Spread Spectrum No of Steps [7:0] + # PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38 + + # Spread Spectrum No of Steps bits 7:0 + #(OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U) */ + mask_write 0XFD40A368 0x000000FF 0x00000038 + # Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C

    + + # Spread Spectrum No of Steps [10:8] + # PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03 + + # Spread Spectrum No of Steps bits 10:8 + #(OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U) */ + mask_write 0XFD40A36C 0x00000007 0x00000003 + # Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368

    + + # Spread Spectrum No of Steps [7:0] + # PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0 + + # Spread Spectrum No of Steps bits 7:0 + #(OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U) */ + mask_write 0XFD40E368 0x000000FF 0x000000E0 + # Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C

    + + # Spread Spectrum No of Steps [10:8] + # PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 + + # Spread Spectrum No of Steps bits 10:8 + #(OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U) */ + mask_write 0XFD40E36C 0x00000007 0x00000003 + # Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368

    + + # Spread Spectrum No of Steps [7:0] + # PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58 + + # Spread Spectrum No of Steps bits 7:0 + #(OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U) */ + mask_write 0XFD406368 0x000000FF 0x00000058 + # Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C

    + + # Spread Spectrum No of Steps [10:8] + # PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 + + # Spread Spectrum No of Steps bits 10:8 + #(OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U) */ + mask_write 0XFD40636C 0x00000007 0x00000003 + # Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370

    + + # Step Size for Spread Spectrum [7:0] + # PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C + + # Step Size for Spread Spectrum LSB + #(OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU) */ + mask_write 0XFD406370 0x000000FF 0x0000007C + # Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374

    + + # Step Size for Spread Spectrum [15:8] + # PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33 + + # Step Size for Spread Spectrum 1 + #(OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U) */ + mask_write 0XFD406374 0x000000FF 0x00000033 + # Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378

    + + # Step Size for Spread Spectrum [23:16] + # PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 + + # Step Size for Spread Spectrum 2 + #(OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U) */ + mask_write 0XFD406378 0x000000FF 0x00000002 + # Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C

    + + # Step Size for Spread Spectrum [25:24] + # PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 + + # Enable/Disable test mode force on SS step size + # PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + # Enable/Disable test mode force on SS no of steps + # PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + # Enable force on enable Spread Spectrum + #(OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U) */ + mask_write 0XFD40637C 0x00000033 0x00000030 + # Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370

    + + # Step Size for Spread Spectrum [7:0] + # PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4 + + # Step Size for Spread Spectrum LSB + #(OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U) */ + mask_write 0XFD40A370 0x000000FF 0x000000F4 + # Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374

    + + # Step Size for Spread Spectrum [15:8] + # PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31 + + # Step Size for Spread Spectrum 1 + #(OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U) */ + mask_write 0XFD40A374 0x000000FF 0x00000031 + # Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378

    + + # Step Size for Spread Spectrum [23:16] + # PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 + + # Step Size for Spread Spectrum 2 + #(OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U) */ + mask_write 0XFD40A378 0x000000FF 0x00000002 + # Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C

    + + # Step Size for Spread Spectrum [25:24] + # PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 + + # Enable/Disable test mode force on SS step size + # PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + # Enable/Disable test mode force on SS no of steps + # PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + # Enable force on enable Spread Spectrum + #(OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U) */ + mask_write 0XFD40A37C 0x00000033 0x00000030 + # Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370

    + + # Step Size for Spread Spectrum [7:0] + # PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9 + + # Step Size for Spread Spectrum LSB + #(OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U) */ + mask_write 0XFD40E370 0x000000FF 0x000000C9 + # Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374

    + + # Step Size for Spread Spectrum [15:8] + # PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2 + + # Step Size for Spread Spectrum 1 + #(OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U) */ + mask_write 0XFD40E374 0x000000FF 0x000000D2 + # Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378

    + + # Step Size for Spread Spectrum [23:16] + # PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1 + + # Step Size for Spread Spectrum 2 + #(OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U) */ + mask_write 0XFD40E378 0x000000FF 0x00000001 + # Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C

    + + # Step Size for Spread Spectrum [25:24] + # PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 + + # Enable/Disable test mode force on SS step size + # PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + # Enable/Disable test mode force on SS no of steps + # PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + # Enable test mode forcing on enable Spread Spectrum + # PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1 + + # Enable force on enable Spread Spectrum + #(OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U) */ + mask_write 0XFD40E37C 0x000000B3 0x000000B0 + # Register : L2_TM_DIG_6 @ 0XFD40906C

    + + # Bypass Descrambler + # PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1 + + # Enable Bypass for <1> TM_DIG_CTRL_6 + # PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 + + # Data path test modes in decoder and descram + #(OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U) */ + mask_write 0XFD40906C 0x00000003 0x00000003 + # Register : L2_TX_DIG_TM_61 @ 0XFD4080F4

    + + # Bypass scrambler signal + # PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1 + + # Enable/disable scrambler bypass signal + # PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 + + # MPHY PLL Gear and bypass scrambler + #(OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U) */ + mask_write 0XFD4080F4 0x00000003 0x00000003 + # Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360

    + + # Enable test mode force on fractional mode enable + # PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1 + + # Fractional feedback division control and fractional value for feedback d + # ivision bits 26:24 + #(OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U) */ + mask_write 0XFD40E360 0x00000040 0x00000040 + # Register : L3_TM_DIG_6 @ 0XFD40D06C

    + + # Bypass 8b10b decoder + # PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1 + + # Enable Bypass for <3> TM_DIG_CTRL_6 + # PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1 + + # Bypass Descrambler + # PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1 + + # Enable Bypass for <1> TM_DIG_CTRL_6 + # PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 + + # Data path test modes in decoder and descram + #(OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU) */ + mask_write 0XFD40D06C 0x0000000F 0x0000000F + # Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4

    + + # Enable/disable encoder bypass signal + # PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1 + + # Bypass scrambler signal + # PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1 + + # Enable/disable scrambler bypass signal + # PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 + + # MPHY PLL Gear and bypass scrambler + #(OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU) */ + mask_write 0XFD40C0F4 0x0000000B 0x0000000B + # : ENABLE CHICKEN BIT FOR PCIE AND USB + # Register : L0_TM_AUX_0 @ 0XFD4010CC

    + + # Spare- not used + # PSU_SERDES_L0_TM_AUX_0_BIT_2 1 + + # Spare registers + #(OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U) */ + mask_write 0XFD4010CC 0x00000020 0x00000020 + # Register : L2_TM_AUX_0 @ 0XFD4090CC

    + + # Spare- not used + # PSU_SERDES_L2_TM_AUX_0_BIT_2 1 + + # Spare registers + #(OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U) */ + mask_write 0XFD4090CC 0x00000020 0x00000020 + # : ENABLING EYE SURF + # Register : L0_TM_DIG_8 @ 0XFD401074

    + + # Enable Eye Surf + # PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1 + + # Test modes for Elastic buffer and enabling Eye Surf + #(OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U) */ + mask_write 0XFD401074 0x00000010 0x00000010 + # Register : L1_TM_DIG_8 @ 0XFD405074

    + + # Enable Eye Surf + # PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1 + + # Test modes for Elastic buffer and enabling Eye Surf + #(OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U) */ + mask_write 0XFD405074 0x00000010 0x00000010 + # Register : L2_TM_DIG_8 @ 0XFD409074

    + + # Enable Eye Surf + # PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1 + + # Test modes for Elastic buffer and enabling Eye Surf + #(OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U) */ + mask_write 0XFD409074 0x00000010 0x00000010 + # Register : L3_TM_DIG_8 @ 0XFD40D074

    + + # Enable Eye Surf + # PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1 + + # Test modes for Elastic buffer and enabling Eye Surf + #(OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U) */ + mask_write 0XFD40D074 0x00000010 0x00000010 + # : ILL SETTINGS FOR GAIN AND LOCK SETTINGS + # Register : L0_TM_MISC2 @ 0XFD40189C

    + + # ILL calib counts BYPASSED with calcode bits + # PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + # sampler cal + #(OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U) */ + mask_write 0XFD40189C 0x00000080 0x00000080 + # Register : L0_TM_IQ_ILL1 @ 0XFD4018F8

    + + # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + # USB3 : SS + # PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64 + + # iqpi cal code + #(OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U) */ + mask_write 0XFD4018F8 0x000000FF 0x00000064 + # Register : L0_TM_IQ_ILL2 @ 0XFD4018FC

    + + # IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + # PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64 + + # iqpi cal code + #(OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U) */ + mask_write 0XFD4018FC 0x000000FF 0x00000064 + # Register : L0_TM_ILL12 @ 0XFD401990

    + + # G1A pll ctr bypass value + # PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11 + + # ill pll counter values + #(OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U) */ + mask_write 0XFD401990 0x000000FF 0x00000011 + # Register : L0_TM_E_ILL1 @ 0XFD401924

    + + # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + # SB3 : SS + # PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4 + + # epi cal code + #(OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U) */ + mask_write 0XFD401924 0x000000FF 0x00000004 + # Register : L0_TM_E_ILL2 @ 0XFD401928

    + + # E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + # PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE + + # epi cal code + #(OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU) */ + mask_write 0XFD401928 0x000000FF 0x000000FE + # Register : L0_TM_IQ_ILL3 @ 0XFD401900

    + + # IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + # PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64 + + # iqpi cal code + #(OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U) */ + mask_write 0XFD401900 0x000000FF 0x00000064 + # Register : L0_TM_E_ILL3 @ 0XFD40192C

    + + # E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + # PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 + + # epi cal code + #(OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U) */ + mask_write 0XFD40192C 0x000000FF 0x00000000 + # Register : L0_TM_ILL8 @ 0XFD401980

    + + # ILL calibration code change wait time + # PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + # ILL cal routine control + #(OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU) */ + mask_write 0XFD401980 0x000000FF 0x000000FF + # Register : L0_TM_IQ_ILL8 @ 0XFD401914

    + + # IQ ILL polytrim bypass value + # PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + # iqpi polytrim + #(OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U) */ + mask_write 0XFD401914 0x000000FF 0x000000F7 + # Register : L0_TM_IQ_ILL9 @ 0XFD401918

    + + # bypass IQ polytrim + # PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + # enables for lf,constant gm trim and polytirm + #(OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U) */ + mask_write 0XFD401918 0x00000001 0x00000001 + # Register : L0_TM_E_ILL8 @ 0XFD401940

    + + # E ILL polytrim bypass value + # PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + # epi polytrim + #(OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U) */ + mask_write 0XFD401940 0x000000FF 0x000000F7 + # Register : L0_TM_E_ILL9 @ 0XFD401944

    + + # bypass E polytrim + # PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + # enables for lf,constant gm trim and polytirm + #(OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U) */ + mask_write 0XFD401944 0x00000001 0x00000001 + # Register : L0_TM_ILL13 @ 0XFD401994

    + + # ILL cal idle val refcnt + # PSU_SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + # ill cal idle value count + #(OFFSET, MASK, VALUE) (0XFD401994, 0x00000007U ,0x00000007U) */ + mask_write 0XFD401994 0x00000007 0x00000007 + # Register : L1_TM_ILL13 @ 0XFD405994

    + + # ILL cal idle val refcnt + # PSU_SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + # ill cal idle value count + #(OFFSET, MASK, VALUE) (0XFD405994, 0x00000007U ,0x00000007U) */ + mask_write 0XFD405994 0x00000007 0x00000007 + # Register : L2_TM_MISC2 @ 0XFD40989C

    + + # ILL calib counts BYPASSED with calcode bits + # PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + # sampler cal + #(OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U) */ + mask_write 0XFD40989C 0x00000080 0x00000080 + # Register : L2_TM_IQ_ILL1 @ 0XFD4098F8

    + + # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + # USB3 : SS + # PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A + + # iqpi cal code + #(OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU) */ + mask_write 0XFD4098F8 0x000000FF 0x0000001A + # Register : L2_TM_IQ_ILL2 @ 0XFD4098FC

    + + # IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + # PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A + + # iqpi cal code + #(OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU) */ + mask_write 0XFD4098FC 0x000000FF 0x0000001A + # Register : L2_TM_ILL12 @ 0XFD409990

    + + # G1A pll ctr bypass value + # PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10 + + # ill pll counter values + #(OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U) */ + mask_write 0XFD409990 0x000000FF 0x00000010 + # Register : L2_TM_E_ILL1 @ 0XFD409924

    + + # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + # SB3 : SS + # PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE + + # epi cal code + #(OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU) */ + mask_write 0XFD409924 0x000000FF 0x000000FE + # Register : L2_TM_E_ILL2 @ 0XFD409928

    + + # E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + # PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0 + + # epi cal code + #(OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U) */ + mask_write 0XFD409928 0x000000FF 0x00000000 + # Register : L2_TM_IQ_ILL3 @ 0XFD409900

    + + # IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + # PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A + + # iqpi cal code + #(OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU) */ + mask_write 0XFD409900 0x000000FF 0x0000001A + # Register : L2_TM_E_ILL3 @ 0XFD40992C

    + + # E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + # PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 + + # epi cal code + #(OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U) */ + mask_write 0XFD40992C 0x000000FF 0x00000000 + # Register : L2_TM_ILL8 @ 0XFD409980

    + + # ILL calibration code change wait time + # PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + # ILL cal routine control + #(OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU) */ + mask_write 0XFD409980 0x000000FF 0x000000FF + # Register : L2_TM_IQ_ILL8 @ 0XFD409914

    + + # IQ ILL polytrim bypass value + # PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + # iqpi polytrim + #(OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U) */ + mask_write 0XFD409914 0x000000FF 0x000000F7 + # Register : L2_TM_IQ_ILL9 @ 0XFD409918

    + + # bypass IQ polytrim + # PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + # enables for lf,constant gm trim and polytirm + #(OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U) */ + mask_write 0XFD409918 0x00000001 0x00000001 + # Register : L2_TM_E_ILL8 @ 0XFD409940

    + + # E ILL polytrim bypass value + # PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + # epi polytrim + #(OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U) */ + mask_write 0XFD409940 0x000000FF 0x000000F7 + # Register : L2_TM_E_ILL9 @ 0XFD409944

    + + # bypass E polytrim + # PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + # enables for lf,constant gm trim and polytirm + #(OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U) */ + mask_write 0XFD409944 0x00000001 0x00000001 + # Register : L2_TM_ILL13 @ 0XFD409994

    + + # ILL cal idle val refcnt + # PSU_SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + # ill cal idle value count + #(OFFSET, MASK, VALUE) (0XFD409994, 0x00000007U ,0x00000007U) */ + mask_write 0XFD409994 0x00000007 0x00000007 + # Register : L3_TM_MISC2 @ 0XFD40D89C

    + + # ILL calib counts BYPASSED with calcode bits + # PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + # sampler cal + #(OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U) */ + mask_write 0XFD40D89C 0x00000080 0x00000080 + # Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8

    + + # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + # USB3 : SS + # PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D + + # iqpi cal code + #(OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU) */ + mask_write 0XFD40D8F8 0x000000FF 0x0000007D + # Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC

    + + # IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + # PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D + + # iqpi cal code + #(OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU) */ + mask_write 0XFD40D8FC 0x000000FF 0x0000007D + # Register : L3_TM_ILL12 @ 0XFD40D990

    + + # G1A pll ctr bypass value + # PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1 + + # ill pll counter values + #(OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U) */ + mask_write 0XFD40D990 0x000000FF 0x00000001 + # Register : L3_TM_E_ILL1 @ 0XFD40D924

    + + # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + # SB3 : SS + # PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C + + # epi cal code + #(OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU) */ + mask_write 0XFD40D924 0x000000FF 0x0000009C + # Register : L3_TM_E_ILL2 @ 0XFD40D928

    + + # E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + # PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39 + + # epi cal code + #(OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U) */ + mask_write 0XFD40D928 0x000000FF 0x00000039 + # Register : L3_TM_ILL11 @ 0XFD40D98C

    + + # G2A_PCIe1 PLL ctr bypass value + # PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2 + + # ill pll counter values + #(OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U) */ + mask_write 0XFD40D98C 0x000000F0 0x00000020 + # Register : L3_TM_IQ_ILL3 @ 0XFD40D900

    + + # IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + # PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D + + # iqpi cal code + #(OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU) */ + mask_write 0XFD40D900 0x000000FF 0x0000007D + # Register : L3_TM_E_ILL3 @ 0XFD40D92C

    + + # E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + # PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64 + + # epi cal code + #(OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U) */ + mask_write 0XFD40D92C 0x000000FF 0x00000064 + # Register : L3_TM_ILL8 @ 0XFD40D980

    + + # ILL calibration code change wait time + # PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + # ILL cal routine control + #(OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU) */ + mask_write 0XFD40D980 0x000000FF 0x000000FF + # Register : L3_TM_IQ_ILL8 @ 0XFD40D914

    + + # IQ ILL polytrim bypass value + # PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + # iqpi polytrim + #(OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U) */ + mask_write 0XFD40D914 0x000000FF 0x000000F7 + # Register : L3_TM_IQ_ILL9 @ 0XFD40D918

    + + # bypass IQ polytrim + # PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + # enables for lf,constant gm trim and polytirm + #(OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U) */ + mask_write 0XFD40D918 0x00000001 0x00000001 + # Register : L3_TM_E_ILL8 @ 0XFD40D940

    + + # E ILL polytrim bypass value + # PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + # epi polytrim + #(OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U) */ + mask_write 0XFD40D940 0x000000FF 0x000000F7 + # Register : L3_TM_E_ILL9 @ 0XFD40D944

    + + # bypass E polytrim + # PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + # enables for lf,constant gm trim and polytirm + #(OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U) */ + mask_write 0XFD40D944 0x00000001 0x00000001 + # Register : L3_TM_ILL13 @ 0XFD40D994

    + + # ILL cal idle val refcnt + # PSU_SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + # ill cal idle value count + #(OFFSET, MASK, VALUE) (0XFD40D994, 0x00000007U ,0x00000007U) */ + mask_write 0XFD40D994 0x00000007 0x00000007 + # : SYMBOL LOCK AND WAIT + # Register : L0_TM_DIG_10 @ 0XFD40107C

    + + # CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + # PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + # test control for changing cdr lock wait time + #(OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x00000001U) */ + mask_write 0XFD40107C 0x0000000F 0x00000001 + # Register : L1_TM_DIG_10 @ 0XFD40507C

    + + # CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + # PSU_SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + # test control for changing cdr lock wait time + #(OFFSET, MASK, VALUE) (0XFD40507C, 0x0000000FU ,0x00000001U) */ + mask_write 0XFD40507C 0x0000000F 0x00000001 + # Register : L2_TM_DIG_10 @ 0XFD40907C

    + + # CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + # PSU_SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + # test control for changing cdr lock wait time + #(OFFSET, MASK, VALUE) (0XFD40907C, 0x0000000FU ,0x00000001U) */ + mask_write 0XFD40907C 0x0000000F 0x00000001 + # Register : L3_TM_DIG_10 @ 0XFD40D07C

    + + # CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + # PSU_SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + # test control for changing cdr lock wait time + #(OFFSET, MASK, VALUE) (0XFD40D07C, 0x0000000FU ,0x00000001U) */ + mask_write 0XFD40D07C 0x0000000F 0x00000001 + # : SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG + # Register : L0_TM_RST_DLY @ 0XFD4019A4

    + + # Delay apb reset by specified amount + # PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF + + # reset delay for apb reset w.r.t pso of hsrx + #(OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU) */ + mask_write 0XFD4019A4 0x000000FF 0x000000FF + # Register : L0_TM_ANA_BYP_15 @ 0XFD401038

    + + # Enable Bypass for <7> of TM_ANA_BYPS_15 + # PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + # Bypass control for pcs-pma interface. EQ supplies, main master supply an + # d ps for samp c2c + #(OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U) */ + mask_write 0XFD401038 0x00000040 0x00000040 + # Register : L0_TM_ANA_BYP_12 @ 0XFD40102C

    + + # Enable Bypass for <7> of TM_ANA_BYPS_12 + # PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + # ble controls + #(OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U) */ + mask_write 0XFD40102C 0x00000040 0x00000040 + # Register : L1_TM_RST_DLY @ 0XFD4059A4

    + + # Delay apb reset by specified amount + # PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF + + # reset delay for apb reset w.r.t pso of hsrx + #(OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU) */ + mask_write 0XFD4059A4 0x000000FF 0x000000FF + # Register : L1_TM_ANA_BYP_15 @ 0XFD405038

    + + # Enable Bypass for <7> of TM_ANA_BYPS_15 + # PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + # Bypass control for pcs-pma interface. EQ supplies, main master supply an + # d ps for samp c2c + #(OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U) */ + mask_write 0XFD405038 0x00000040 0x00000040 + # Register : L1_TM_ANA_BYP_12 @ 0XFD40502C

    + + # Enable Bypass for <7> of TM_ANA_BYPS_12 + # PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + # ble controls + #(OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U) */ + mask_write 0XFD40502C 0x00000040 0x00000040 + # Register : L2_TM_RST_DLY @ 0XFD4099A4

    + + # Delay apb reset by specified amount + # PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF + + # reset delay for apb reset w.r.t pso of hsrx + #(OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU) */ + mask_write 0XFD4099A4 0x000000FF 0x000000FF + # Register : L2_TM_ANA_BYP_15 @ 0XFD409038

    + + # Enable Bypass for <7> of TM_ANA_BYPS_15 + # PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + # Bypass control for pcs-pma interface. EQ supplies, main master supply an + # d ps for samp c2c + #(OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U) */ + mask_write 0XFD409038 0x00000040 0x00000040 + # Register : L2_TM_ANA_BYP_12 @ 0XFD40902C

    + + # Enable Bypass for <7> of TM_ANA_BYPS_12 + # PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + # ble controls + #(OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U) */ + mask_write 0XFD40902C 0x00000040 0x00000040 + # Register : L3_TM_RST_DLY @ 0XFD40D9A4

    + + # Delay apb reset by specified amount + # PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF + + # reset delay for apb reset w.r.t pso of hsrx + #(OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU) */ + mask_write 0XFD40D9A4 0x000000FF 0x000000FF + # Register : L3_TM_ANA_BYP_15 @ 0XFD40D038

    + + # Enable Bypass for <7> of TM_ANA_BYPS_15 + # PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + # Bypass control for pcs-pma interface. EQ supplies, main master supply an + # d ps for samp c2c + #(OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U) */ + mask_write 0XFD40D038 0x00000040 0x00000040 + # Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C

    + + # Enable Bypass for <7> of TM_ANA_BYPS_12 + # PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + # ble controls + #(OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U) */ + mask_write 0XFD40D02C 0x00000040 0x00000040 + # : DISABLE FPL/FFL + # Register : L0_TM_MISC3 @ 0XFD4019AC

    + + # CDR fast phase lock control + # PSU_SERDES_L0_TM_MISC3_CDR_EN_FPL 0x0 + + # CDR fast frequency lock control + # PSU_SERDES_L0_TM_MISC3_CDR_EN_FFL 0x0 + + # debug bus selection bit, cdr fast phase and freq controls + #(OFFSET, MASK, VALUE) (0XFD4019AC, 0x00000003U ,0x00000000U) */ + mask_write 0XFD4019AC 0x00000003 0x00000000 + # Register : L1_TM_MISC3 @ 0XFD4059AC

    + + # CDR fast phase lock control + # PSU_SERDES_L1_TM_MISC3_CDR_EN_FPL 0x0 + + # CDR fast frequency lock control + # PSU_SERDES_L1_TM_MISC3_CDR_EN_FFL 0x0 + + # debug bus selection bit, cdr fast phase and freq controls + #(OFFSET, MASK, VALUE) (0XFD4059AC, 0x00000003U ,0x00000000U) */ + mask_write 0XFD4059AC 0x00000003 0x00000000 + # Register : L2_TM_MISC3 @ 0XFD4099AC

    + + # CDR fast phase lock control + # PSU_SERDES_L2_TM_MISC3_CDR_EN_FPL 0x0 + + # CDR fast frequency lock control + # PSU_SERDES_L2_TM_MISC3_CDR_EN_FFL 0x0 + + # debug bus selection bit, cdr fast phase and freq controls + #(OFFSET, MASK, VALUE) (0XFD4099AC, 0x00000003U ,0x00000000U) */ + mask_write 0XFD4099AC 0x00000003 0x00000000 + # Register : L3_TM_MISC3 @ 0XFD40D9AC

    + + # CDR fast phase lock control + # PSU_SERDES_L3_TM_MISC3_CDR_EN_FPL 0x0 + + # CDR fast frequency lock control + # PSU_SERDES_L3_TM_MISC3_CDR_EN_FFL 0x0 + + # debug bus selection bit, cdr fast phase and freq controls + #(OFFSET, MASK, VALUE) (0XFD40D9AC, 0x00000003U ,0x00000000U) */ + mask_write 0XFD40D9AC 0x00000003 0x00000000 + # : DISABLE DYNAMIC OFFSET CALIBRATION + # Register : L0_TM_EQ11 @ 0XFD401978

    + + # Force EQ offset correction algo off if not forced on + # PSU_SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + # eq dynamic offset correction + #(OFFSET, MASK, VALUE) (0XFD401978, 0x00000010U ,0x00000010U) */ + mask_write 0XFD401978 0x00000010 0x00000010 + # Register : L1_TM_EQ11 @ 0XFD405978

    + + # Force EQ offset correction algo off if not forced on + # PSU_SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + # eq dynamic offset correction + #(OFFSET, MASK, VALUE) (0XFD405978, 0x00000010U ,0x00000010U) */ + mask_write 0XFD405978 0x00000010 0x00000010 + # Register : L2_TM_EQ11 @ 0XFD409978

    + + # Force EQ offset correction algo off if not forced on + # PSU_SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + # eq dynamic offset correction + #(OFFSET, MASK, VALUE) (0XFD409978, 0x00000010U ,0x00000010U) */ + mask_write 0XFD409978 0x00000010 0x00000010 + # Register : L3_TM_EQ11 @ 0XFD40D978

    + + # Force EQ offset correction algo off if not forced on + # PSU_SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + # eq dynamic offset correction + #(OFFSET, MASK, VALUE) (0XFD40D978, 0x00000010U ,0x00000010U) */ + mask_write 0XFD40D978 0x00000010 0x00000010 + # : SERDES ILL CALIB + # : DISABLE ECO FOR PCIE + # Register : eco_0 @ 0XFD3D001C

    + + # For future use + # PSU_SIOU_ECO_0_FIELD 0x1 + + # ECO Register for future use + #(OFFSET, MASK, VALUE) (0XFD3D001C, 0xFFFFFFFFU ,0x00000001U) */ + mask_write 0XFD3D001C 0xFFFFFFFF 0x00000001 + # : GT LANE SETTINGS + # Register : ICM_CFG0 @ 0XFD410010

    + + # Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, + # 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused + # PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1 + + # Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + # 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused + # PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4 + + # ICM Configuration Register 0 + #(OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U) */ + mask_write 0XFD410010 0x00000077 0x00000041 + # Register : ICM_CFG1 @ 0XFD410014

    + + # Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + # 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused + # PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3 + + # Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, + # 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused + # PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2 + + # ICM Configuration Register 1 + #(OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U) */ + mask_write 0XFD410014 0x00000077 0x00000023 + # : CHECKING PLL LOCK + # : ENABLE SERIAL DATA MUX DEEMPH + # Register : L1_TXPMD_TM_45 @ 0XFD404CB4

    + + # Enable/disable DP post2 path + # PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1 + + # Override enable/disable of DP post2 path + # PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1 + + # Override enable/disable of DP post1 path + # PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1 + + # Enable/disable DP main path + # PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1 + + # Override enable/disable of DP main path + # PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1 + + # Post or pre or main DP path selection + #(OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U) */ + mask_write 0XFD404CB4 0x00000037 0x00000037 + # Register : L1_TX_ANA_TM_118 @ 0XFD4041D8

    + + # Test register force for enabling/disablign TX deemphasis bits <17:0> + # PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 + + # Enable Override of TX deemphasis + #(OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U) */ + mask_write 0XFD4041D8 0x00000001 0x00000001 + # Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8

    + + # Test register force for enabling/disablign TX deemphasis bits <17:0> + # PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 + + # Enable Override of TX deemphasis + #(OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U) */ + mask_write 0XFD40C1D8 0x00000001 0x00000001 + # : CDR AND RX EQUALIZATION SETTINGS + # Register : L3_TM_CDR5 @ 0XFD40DC14

    + + # FPHL FSM accumulate cycles + # PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7 + + # FFL Phase0 int gain aka 2ol SD update rate + # PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6 + + # Fast phase lock controls -- FSM accumulator cycle control and phase 0 in + # t gain control. + #(OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U) */ + mask_write 0XFD40DC14 0x000000FF 0x000000E6 + # Register : L3_TM_CDR16 @ 0XFD40DC40

    + + # FFL Phase0 prop gain aka 1ol SD update rate + # PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC + + # Fast phase lock controls -- phase 0 prop gain + #(OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU) */ + mask_write 0XFD40DC40 0x0000001F 0x0000000C + # Register : L3_TM_EQ0 @ 0XFD40D94C

    + + # EQ stg 2 controls BYPASSED + # PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1 + + # eq stg1 and stg2 controls + #(OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U) */ + mask_write 0XFD40D94C 0x00000020 0x00000020 + # Register : L3_TM_EQ1 @ 0XFD40D950

    + + # EQ STG2 RL PROG + # PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2 + + # EQ stg 2 preamp mode val + # PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1 + + # eq stg1 and stg2 controls + #(OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U) */ + mask_write 0XFD40D950 0x00000007 0x00000006 + # : GEM SERDES SETTINGS + # : ENABLE PRE EMPHAIS AND VOLTAGE SWING + # Register : L1_TXPMD_TM_48 @ 0XFD404CC0

    + + # Margining factor value + # PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0 + + # Margining factor + #(OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U) */ + mask_write 0XFD404CC0 0x0000001F 0x00000000 + # Register : L1_TX_ANA_TM_18 @ 0XFD404048

    + + # pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + # phasis, Others: reserved + # PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0 + + # Override for PIPE TX de-emphasis + #(OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U) */ + mask_write 0XFD404048 0x000000FF 0x00000000 + # Register : L3_TX_ANA_TM_18 @ 0XFD40C048

    + + # pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + # phasis, Others: reserved + # PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1 + + # Override for PIPE TX de-emphasis + #(OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U) */ + mask_write 0XFD40C048 0x000000FF 0x00000001 +} + +set psu_resetout_init_data { + # : TAKING SERDES PERIPHERAL OUT OF RESET RESET + # : PUTTING USB0 IN RESET + # Register : RST_LPD_TOP @ 0XFF5E023C

    + + # USB 0 reset for control registers + # PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0 + + # Software control register for the LPD block. + #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) */ + mask_write 0XFF5E023C 0x00000400 0x00000000 + # : USB0 PIPE POWER PRESENT + # Register : fpd_power_prsnt @ 0XFF9D0080

    + + # This bit is used to choose between PIPE power present and 1'b1 + # PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1 + + # fpd_power_prsnt + #(OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) */ + mask_write 0XFF9D0080 0x00000001 0x00000001 + # Register : fpd_pipe_clk @ 0XFF9D007C

    + + # This bit is used to choose between PIPE clock coming from SerDes and the + # suspend clk + # PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0 + + # fpd_pipe_clk + #(OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) */ + mask_write 0XFF9D007C 0x00000001 0x00000000 + # : HIBERREST + # Register : RST_LPD_TOP @ 0XFF5E023C

    + + # USB 0 sleep circuit reset + # PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0 + + # USB 0 reset + # PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0 + + # Software control register for the LPD block. + #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U) */ + mask_write 0XFF5E023C 0x00000140 0x00000000 + # : PUTTING GEM0 IN RESET + # Register : RST_LPD_IOU0 @ 0XFF5E0230

    + + # GEM 3 reset + # PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0 + + # Software controlled reset for the GEMs + #(OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) */ + mask_write 0XFF5E0230 0x00000008 0x00000000 + # : PUTTING SATA IN RESET + # Register : sata_misc_ctrl @ 0XFD3D0100

    + + # Sata PM clock control select + # PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3 + + # Misc Contorls for SATA.This register may only be modified during bootup + # (while SATA block is disabled) + #(OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U) */ + mask_write 0XFD3D0100 0x00000003 0x00000003 + # Register : RST_FPD_TOP @ 0XFD1A0100

    + + # Sata block level reset + # PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0 + + # FPD Block level software controlled reset + #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U) */ + mask_write 0XFD1A0100 0x00000002 0x00000000 + # : PUTTING PCIE CFG AND BRIDGE IN RESET + # Register : RST_FPD_TOP @ 0XFD1A0100

    + + # PCIE config reset + # PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0 + + # PCIE bridge block level reset (AXI interface) + # PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0 + + # FPD Block level software controlled reset + #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U) */ + mask_write 0XFD1A0100 0x000C0000 0x00000000 + # : PUTTING DP IN RESET + # Register : RST_FPD_TOP @ 0XFD1A0100

    + + # Display Port block level reset (includes DPDMA) + # PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0 + + # FPD Block level software controlled reset + #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U) */ + mask_write 0XFD1A0100 0x00010000 0x00000000 + # Register : DP_PHY_RESET @ 0XFD4A0200

    + + # Set to '1' to hold the GT in reset. Clear to release. + # PSU_DP_DP_PHY_RESET_GT_RESET 0X0 + + # Reset the transmitter PHY. + #(OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U) */ + mask_write 0XFD4A0200 0x00000002 0x00000000 + # Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

    + + # Two bits per lane. When set to 11, moves the GT to power down mode. When + # set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + # lane 1 + # PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0 + + # Control PHY Power down + #(OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U) */ + mask_write 0XFD4A0238 0x0000000F 0x00000000 + # : USB0 GFLADJ + # Register : GUSB2PHYCFG @ 0XFE20C200

    + + # USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc + # ks. Specifies the response time for a MAC request to the Packet FIFO Con + # troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th + # e required values for the minimum SoC bus frequency of 60 MHz. USB turna + # round time is a critical certification criteria when using long cables a + # nd five hub levels. The required values for this field: - 4'h5: When the + # MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit + # UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim + # e is not critical, this field can be set to a larger value. Note: This f + # ield is valid only in device mode. + # PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9 + + # Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP + # I Transceiver Select signal (for HS) and the assertion of the TxValid si + # gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima + # tely 2.5 us) is introduced from the time when the Transceiver Select is + # set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the + # chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you + # enable the hibernation feature when the device core comes out of power- + # off, you must re-initialize this bit with the appropriate value because + # the core does not save and restore this bit value during hibernation. - + # This bit is valid only in device mode. + # PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0 + + # Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use + # s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th + # e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert + # ion from the core is not transferred to the external PHY. - 1'b1: utmi_s + # leep_n and utmi_l1_suspend_n assertion from the core is transferred to t + # he external PHY. Note: This bit must be set high for Port0 if PHY is use + # d. Note: In Device mode - Before issuing any device endpoint command whe + # n operating in 2.0 speeds, disable this bit and enable it after the comm + # and completes. Without disabling this bit, if a command is issued when t + # he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of + # f, the command will not get completed. + # PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0 + + # USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T + # he application uses this bit to select a high-speed PHY or a full-speed + # transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a + # lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans + # ceiver. This bit is always 1, with Write Only access. If both interface + # types are selected in coreConsultant (that is, parameters' values are no + # t zero), the application uses this bit to select the active interface is + # active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv + # er is not supported. This bit always reads as 1'b0. + # PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0 + + # Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend + # mode if Suspend conditions are valid. For DRD/OTG configurations, it is + # recommended that this bit is set to 0 during coreConsultant configurati + # on. If it is set to 1, then the application must clear this bit after po + # wer-on reset. Application needs to set it to 1 after the core initializa + # tion completes. For all other configurations, this bit can be set to 1 d + # uring core configuration. Note: - In host mode, on reset, this bit is se + # t to 1. Software can override this bit after reset. - In device mode, be + # fore issuing any device endpoint command when operating in 2.0 speeds, d + # isable this bit and enable it after the command completes. If you issue + # a command without disabling this bit when the device is in L2 state and + # if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c + # ompleted. + # PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0x1 + + # Full-Speed Serial Interface Select (FSIntf) The application uses this bi + # t to select a unidirectional or bidirectional USB 1.1 full-speed serial + # transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in + # terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir + # ectional full-speed serial interface. This bit is set to 0 with Read Onl + # y access. Note: USB 1.1 full-speed serial interface is not supported. Th + # is bit always reads as 1'b0. + # PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0 + + # ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se + # lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int + # erface This bit is writable only if UTMI+ and ULPI is specified for High + # -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_ + # INTERFACE = 3). Otherwise, this bit is read-only and the value depends o + # n the interface selected through DWC_USB3_HSPHY_INTERFACE. + # PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1 + + # PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi + # t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte + # rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en + # abled 2.0 ports must have the same clock frequency as Port0 clock freque + # ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge + # ther for different ports at the same time (that is, all the ports must b + # e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If + # any of the USB 2.0 ports is selected as ULPI port for operation, then a + # ll the USB 2.0 ports must be operating at 60 MHz. + # PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0 + + # HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat + # ed by the application in this field, is multiplied by a bit-time factor; + # this factor is added to the high-speed/full-speed interpacket timeout d + # uration in the core to account for additional delays introduced by the P + # HY. This may be required, since the delay introduced by the PHY in gener + # ating the linestate condition may vary among PHYs. The USB standard time + # out value for high-speed operation is 736 to 816 (inclusive) bit times. + # The USB standard timeout value for full-speed operation is 16 to 18 (inc + # lusive) bit times. The application must program this field based on the + # speed of connection. The number of bit times added per PHY clock are: Hi + # gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P + # HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0. + # 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc + # k = 0.25 bit times + # PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7 + + # ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive + # 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char + # ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl + # y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3) + # PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV 0x1 + + # Global USB2 PHY Configuration Register The application must program this + # register before starting any transactions on either the SoC bus or the + # USB. In Device-only configurations, only one register is needed. In Host + # mode, per-port registers are implemented. + #(OFFSET, MASK, VALUE) (0XFE20C200, 0x00023FFFU ,0x00022457U) */ + mask_write 0XFE20C200 0x00023FFF 0x00022457 + # Register : GFLADJ @ 0XFE20C630

    + + # This field indicates the frame length adjustment to be applied when SOF/ + # ITP counter is running on the ref_clk. This register value is used to ad + # just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i + # nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must + # be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t + # o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows: + # FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe + # riod)) * ref_clk_period where - the ref_clk_period_integer is the intege + # r value of the ref_clk period got by truncating the decimal (fractional) + # value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c + # lk_period is the ref_clk period including the fractional value. Examples + # : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA + # DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin + # g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE + # RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2 + # 0.8333 = 5208 (ignoring the fractional value) + # PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0 + + # Global Frame Length Adjustment Register This register provides options f + # or the software to control the core behavior with respect to SOF (Start + # of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer + # functionality. It provides an option to override the fladj_30mhz_reg sid + # eband signal. In addition, it enables running SOF or ITP frame timer cou + # nters completely from the ref_clk. This facilitates hardware LPM in host + # mode with the SOF or ITP counters being run from the ref_clk signal. + #(OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) */ + mask_write 0XFE20C630 0x003FFF00 0x00000000 + # Register : GUCTL1 @ 0XFE20C11C

    + + # When this bit is set to '0', termsel, xcvrsel will become 0 during end o + # f resume while the opmode will become 0 once controller completes end of + # resume and enters U0 state (2 separate commandswill be issued). When th + # is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during + # end of resume itself (only 1 command will be issued) + # PSU_USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY 0x1 + + # Reserved + # PSU_USB3_0_XHCI_GUCTL1_RESERVED_9 0x1 + + # Global User Control Register 1 + #(OFFSET, MASK, VALUE) (0XFE20C11C, 0x00000600U ,0x00000600U) */ + mask_write 0XFE20C11C 0x00000600 0x00000600 + # Register : GUCTL @ 0XFE20C12C

    + + # Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th + # e Auto Retry feature. For IN transfers (non-isochronous) that encounter + # data packets with CRC errors or internal overrun scenarios, the auto ret + # ry feature causes the Host core to reply to the device with a non-termin + # ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N + # umP != 0). If the Auto Retry feature is disabled (default), the core wil + # l respond with a terminating retry ACK (that is, an ACK transaction pack + # et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut + # o Retry Enabled Note: This bit is also applicable to the device mode. + # PSU_USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN 0x1 + + # Global User Control Register: This register provides a few options for t + # he software to control the core behavior in the Host mode. Most of the o + # ptions are used to improve host inter-operability with different devices + # . + #(OFFSET, MASK, VALUE) (0XFE20C12C, 0x00004000U ,0x00004000U) */ + mask_write 0XFE20C12C 0x00004000 0x00004000 + # : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON. + # Register : ATTR_25 @ 0XFD480064

    + + # If TRUE Completion Timeout Disable is supported. This is required to be + # TRUE for Endpoint and either setting allowed for Root ports. Drives Devi + # ce Capability 2 [4]; EP=0x0001; RP=0x0001 + # PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1 + + # ATTR_25 + #(OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U) */ + mask_write 0XFD480064 0x00000200 0x00000200 + # : PCIE SETTINGS + # Register : ATTR_7 @ 0XFD48001C

    + + # Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + # to be implemented, set to 32'h00000000. Bits are defined as follows: Me + # mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + # 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + # for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + # here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + # n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + # set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + # AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + # EP=0x0004; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0 + + # ATTR_7 + #(OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U) */ + mask_write 0XFD48001C 0x0000FFFF 0x00000000 + # Register : ATTR_8 @ 0XFD480020

    + + # Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + # to be implemented, set to 32'h00000000. Bits are defined as follows: Me + # mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + # 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + # for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + # here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + # n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + # set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + # AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + # EP=0xFFF0; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0 + + # ATTR_8 + #(OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U) */ + mask_write 0XFD480020 0x0000FFFF 0x00000000 + # Register : ATTR_9 @ 0XFD480024

    + + # Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + # 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + # R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + # ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + # ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + # e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + # [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + # 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + # in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + # o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + # to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + # o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0 + + # ATTR_9 + #(OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U) */ + mask_write 0XFD480024 0x0000FFFF 0x00000000 + # Register : ATTR_10 @ 0XFD480028

    + + # Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + # 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + # R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + # ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + # ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + # e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + # [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + # 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + # in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + # o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + # to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + # o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0 + + # ATTR_10 + #(OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U) */ + mask_write 0XFD480028 0x0000FFFF 0x00000000 + # Register : ATTR_11 @ 0XFD48002C

    + + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + # R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR1 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + # F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + # pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + # 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + # es.; EP=0x0004; RP=0xFFFF + # PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF + + # ATTR_11 + #(OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU) */ + mask_write 0XFD48002C 0x0000FFFF 0x0000FFFF + # Register : ATTR_12 @ 0XFD480030

    + + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + # R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR1 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + # F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + # pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + # 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + # es.; EP=0xFFF0; RP=0x00FF + # PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF + + # ATTR_12 + #(OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU) */ + mask_write 0XFD480030 0x0000FFFF 0x000000FF + # Register : ATTR_13 @ 0XFD480034

    + + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + # R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR2 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + # 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + # egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + # t decode For an endpoint, bits are defined as follows: Memory Space BAR + # (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + # pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + # 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + # ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + # ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + # ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + # bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + # in bytes.; EP=0xFFFF; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0 + + # ATTR_13 + #(OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U) */ + mask_write 0XFD480034 0x0000FFFF 0x00000000 + # Register : ATTR_14 @ 0XFD480038

    + + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + # R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR2 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + # 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + # egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + # t decode For an endpoint, bits are defined as follows: Memory Space BAR + # (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + # pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + # 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + # ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + # ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + # ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + # bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + # in bytes.; EP=0xFFFF; RP=0xFFFF + # PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF + + # ATTR_14 + #(OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU) */ + mask_write 0XFD480038 0x0000FFFF 0x0000FFFF + # Register : ATTR_15 @ 0XFD48003C

    + + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + # R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR3 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + # 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + # pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + # 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + # es.; EP=0x0004; RP=0xFFF0 + # PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0 + + # ATTR_15 + #(OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U) */ + mask_write 0XFD48003C 0x0000FFFF 0x0000FFF0 + # Register : ATTR_16 @ 0XFD480040

    + + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + # R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR3 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + # 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + # pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + # 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + # es.; EP=0xFFF0; RP=0xFFF0 + # PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0 + + # ATTR_16 + #(OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U) */ + mask_write 0XFD480040 0x0000FFFF 0x0000FFF0 + # Register : ATTR_17 @ 0XFD480044

    + + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + # R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR4 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + # 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + # = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + # refetchable Memory Limit/Base implemented For an endpoint, bits are defi + # ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + # e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + # lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + # or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + # aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + # [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + # permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + # ; RP=0xFFF1 + # PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1 + + # ATTR_17 + #(OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U) */ + mask_write 0XFD480044 0x0000FFFF 0x0000FFF1 + # Register : ATTR_18 @ 0XFD480048

    + + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + # R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR4 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + # 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + # = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + # refetchable Memory Limit/Base implemented For an endpoint, bits are defi + # ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + # e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + # lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + # or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + # aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + # [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + # permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + # ; RP=0xFFF1 + # PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1 + + # ATTR_18 + #(OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U) */ + mask_write 0XFD480048 0x0000FFFF 0x0000FFF1 + # Register : ATTR_27 @ 0XFD48006C

    + + # Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1 + # - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa + # bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo + # rted; EP=0x0001; RP=0x0001 + # PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1 + + # Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca + # n withstand on transitions from L1 state to L0 (if L1 state supported). + # Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to + # 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For + # Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0 + + # ATTR_27 + #(OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U) */ + mask_write 0XFD48006C 0x00000738 0x00000100 + # Register : ATTR_50 @ 0XFD4800C8

    + + # Identifies the type of device/port as follows: 0000b PCI Express Endpoin + # t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P + # CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110 + # b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X + # Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre + # ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM + # _FACING settings.; EP=0x0000; RP=0x0004 + # PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4 + + # PCIe Capability's Next Capability Offset pointer to the next item in the + # capabilities list, or 00h if this is the final capability.; EP=0x009C; + # RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0 + + # ATTR_50 + #(OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U) */ + mask_write 0XFD4800C8 0x0000FFF0 0x00000040 + # Register : ATTR_105 @ 0XFD4801A4

    + + # Number of credits that should be advertised for Completion data received + # on Virtual Channel 0. The bytes advertised must be less than or equal t + # o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD + # PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD + + # ATTR_105 + #(OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU) */ + mask_write 0XFD4801A4 0x000007FF 0x000000CD + # Register : ATTR_106 @ 0XFD4801A8

    + + # Number of credits that should be advertised for Completion headers recei + # ved on Virtual Channel 0. The sum of the posted, non posted, and complet + # ion header credits must be <= 80; EP=0x0048; RP=0x0024 + # PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24 + + # Number of credits that should be advertised for Non-Posted headers recei + # ved on Virtual Channel 0. The number of non posted data credits advertis + # ed by the block is equal to the number of non posted header credits. The + # sum of the posted, non posted, and completion header credits must be <= + # 80; EP=0x0004; RP=0x000C + # PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC + + # ATTR_106 + #(OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U) */ + mask_write 0XFD4801A8 0x00003FFF 0x00000624 + # Register : ATTR_107 @ 0XFD4801AC

    + + # Number of credits that should be advertised for Non-Posted data received + # on Virtual Channel 0. The number of non posted data credits advertised + # by the block is equal to two times the number of non posted header credi + # ts if atomic operations are supported or is equal to the number of non p + # osted header credits if atomic operations are not supported. The bytes a + # dvertised must be less than or equal to the bram bytes available. See VC + # 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 + # PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18 + + # ATTR_107 + #(OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U) */ + mask_write 0XFD4801AC 0x000007FF 0x00000018 + # Register : ATTR_108 @ 0XFD4801B0

    + + # Number of credits that should be advertised for Posted data received on + # Virtual Channel 0. The bytes advertised must be less than or equal to th + # e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 + # PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5 + + # ATTR_108 + #(OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U) */ + mask_write 0XFD4801B0 0x000007FF 0x000000B5 + # Register : ATTR_109 @ 0XFD4801B4

    + + # Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_ + # n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0 + + # Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim + # TRUE == trim.; EP=0x0001; RP=0x0001 + # PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1 + + # Enables ECRC check on received TLP's 0 == don't check 1 == always check + # 3 == check if enabled by ECRC check enable bit of AER cap structure; EP= + # 0x0003; RP=0x0003 + # PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3 + + # Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). + # Calculated from max payload size supported and the number of brams conf + # igured for transmit; EP=0x001C; RP=0x001C + # PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c + + # Number of credits that should be advertised for Posted headers received + # on Virtual Channel 0. The sum of the posted, non posted, and completion + # header credits must be <= 80; EP=0x0004; RP=0x0020 + # PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20 + + # ATTR_109 + #(OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U) */ + mask_write 0XFD4801B4 0x0000FFFF 0x00007E20 + # Register : ATTR_34 @ 0XFD480088

    + + # Specifies values to be transferred to Header Type register. Bit 7 should + # be set to '0' indicating single-function device. Bit 0 identifies heade + # r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; + # RP=0x0001 + # PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1 + + # ATTR_34 + #(OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U) */ + mask_write 0XFD480088 0x000000FF 0x00000001 + # Register : ATTR_53 @ 0XFD4800D4

    + + # PM Capability's Next Capability Offset pointer to the next item in the c + # apabilities list, or 00h if this is the final capability.; EP=0x0048; RP + # =0x0060 + # PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60 + + # ATTR_53 + #(OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U) */ + mask_write 0XFD4800D4 0x000000FF 0x00000060 + # Register : ATTR_41 @ 0XFD4800A4

    + + # MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont + # rol Register[8]. When set, adds Mask and Pending Dword to Cap structure; + # EP=0x0000; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0 + + # Indicates that the MSI structures exists. If this is FALSE, then the MSI + # structure cannot be accessed via either the link or the management port + # .; EP=0x0001; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 + + # MSI Capability's Next Capability Offset pointer to the next item in the + # capabilities list, or 00h if this is the final capability.; EP=0x0060; R + # P=0x0000 + # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0 + + # Indicates that the MSI structures exists. If this is FALSE, then the MSI + # structure cannot be accessed via either the link or the management port + # .; EP=0x0001; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 + + # ATTR_41 + #(OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U) */ + mask_write 0XFD4800A4 0x000003FF 0x00000000 + # Register : ATTR_97 @ 0XFD480184

    + + # Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b + # x4, 001000b x8.; EP=0x0004; RP=0x0004 + # PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1 + + # Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1 + # ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004 + # PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1 + + # ATTR_97 + #(OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U) */ + mask_write 0XFD480184 0x00000FFF 0x00000041 + # Register : ATTR_100 @ 0XFD480190

    + + # TRUE specifies upstream-facing port. FALSE specifies downstream-facing p + # ort.; EP=0x0001; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0 + + # ATTR_100 + #(OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U) */ + mask_write 0XFD480190 0x00000040 0x00000000 + # Register : ATTR_101 @ 0XFD480194

    + + # Enable the routing of message TLPs to the user through the TRN RX interf + # ace. A bit value of 1 enables routing of the message TLP to the user. Me + # ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 + # - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I + # NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit + # 10 PME_Turn_Off; EP=0x0000; RP=0x07FF + # PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF + + # Disable BAR filtering. Does not change the behavior of the bar hit outpu + # ts; EP=0x0000; RP=0x0001 + # PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1 + + # ATTR_101 + #(OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U) */ + mask_write 0XFD480194 0x0000FFE2 0x0000FFE2 + # Register : ATTR_37 @ 0XFD480094

    + + # Link Bandwidth notification capability. Indicates support for the link b + # andwidth notification status and interrupt mechanism. Required for Root. + # ; EP=0x0000; RP=0x0001 + # PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1 + + # Maximum Link Speed. Valid settings are: 0001b [2.5 GT/s], 0010b [5.0 GT/ + # s and 2.5 GT/s].; EP=0x0002; RP=0x0002 + # PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_MAX_LINK_SPEED 0x2 + + # Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op + # tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001 + # ; RP=0x0001 + # PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1 + + # ATTR_37 + #(OFFSET, MASK, VALUE) (0XFD480094, 0x00007E00U ,0x00004A00U) */ + mask_write 0XFD480094 0x00007E00 0x00004A00 + # Register : ATTR_93 @ 0XFD480174

    + + # Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value + # (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU + # NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1 + + # Sets a user-defined timeout for the Replay Timer to force cause the retr + # ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_ + # REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att + # ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.; + # EP=0x0000; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000 + + # ATTR_93 + #(OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U) */ + mask_write 0XFD480174 0x0000FFFF 0x00009000 + # Register : ID @ 0XFD480200

    + + # Device ID for the the PCIe Cap Structure Device ID field + # PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd011 + + # Vendor ID for the PCIe Cap Structure Vendor ID field + # PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee + + # ID + #(OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED011U) */ + mask_write 0XFD480200 0xFFFFFFFF 0x10EED011 + # Register : SUBSYS_ID @ 0XFD480204

    + + # Subsystem ID for the the PCIe Cap Structure Subsystem ID field + # PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7 + + # Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field + # PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee + + # SUBSYS_ID + #(OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U) */ + mask_write 0XFD480204 0xFFFFFFFF 0x10EE0007 + # Register : REV_ID @ 0XFD480208

    + + # Revision ID for the the PCIe Cap Structure + # PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0 + + # REV_ID + #(OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U) */ + mask_write 0XFD480208 0x000000FF 0x00000000 + # Register : ATTR_24 @ 0XFD480060

    + + # Code identifying basic function, subclass and applicable programming int + # erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000 + # PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x8000 + + # ATTR_24 + #(OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00008000U) */ + mask_write 0XFD480060 0x0000FFFF 0x00008000 + # Register : ATTR_25 @ 0XFD480064

    + + # Code identifying basic function, subclass and applicable programming int + # erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006 + # PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6 + + # INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] + # to be hardwired to 0.; EP=0x0001; RP=0x0001 + # PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0 + + # ATTR_25 + #(OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U) */ + mask_write 0XFD480064 0x000001FF 0x00000006 + # Register : ATTR_4 @ 0XFD480010

    + + # Indicates that the AER structures exists. If this is FALSE, then the AER + # structure cannot be accessed via either the link or the management port + # , and AER will be considered to not be present for error management task + # s (such as what types of error messages are sent if an error is detected + # ).; EP=0x0001; RP=0x0001 + # PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 + + # Indicates that the AER structures exists. If this is FALSE, then the AER + # structure cannot be accessed via either the link or the management port + # , and AER will be considered to not be present for error management task + # s (such as what types of error messages are sent if an error is detected + # ).; EP=0x0001; RP=0x0001 + # PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 + + # ATTR_4 + #(OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U) */ + mask_write 0XFD480010 0x00001000 0x00000000 + # Register : ATTR_89 @ 0XFD480164

    + + # VSEC's Next Capability Offset pointer to the next item in the capabiliti + # es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140 + # PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0 + + # ATTR_89 + #(OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U) */ + mask_write 0XFD480164 0x00001FFE 0x00000000 + # Register : ATTR_79 @ 0XFD48013C

    + + # CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the + # Root Capabilities register.; EP=0x0000; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1 + + # ATTR_79 + #(OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U) */ + mask_write 0XFD48013C 0x00000020 0x00000020 + # Register : ATTR_43 @ 0XFD4800AC

    + + # Indicates that the MSIX structures exists. If this is FALSE, then the MS + # IX structure cannot be accessed via either the link or the management po + # rt.; EP=0x0001; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0 + + # ATTR_43 + #(OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U) */ + mask_write 0XFD4800AC 0x00000100 0x00000000 + # Register : ATTR_48 @ 0XFD4800C0

    + + # MSI-X Table Size. This value is transferred to the MSI-X Message Control + # [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does + # not implement the table; that must be implemented in user logic.; EP=0x0 + # 003; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0 + + # ATTR_48 + #(OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U) */ + mask_write 0XFD4800C0 0x000007FF 0x00000000 + # Register : ATTR_46 @ 0XFD4800B8

    + + # MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + # field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0 + + # ATTR_46 + #(OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U) */ + mask_write 0XFD4800B8 0x0000FFFF 0x00000000 + # Register : ATTR_47 @ 0XFD4800BC

    + + # MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + # field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0 + + # ATTR_47 + #(OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U) */ + mask_write 0XFD4800BC 0x00001FFF 0x00000000 + # Register : ATTR_44 @ 0XFD4800B0

    + + # MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + # A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0 + + # ATTR_44 + #(OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U) */ + mask_write 0XFD4800B0 0x0000FFFF 0x00000000 + # Register : ATTR_45 @ 0XFD4800B4

    + + # MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + # A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0 + + # ATTR_45 + #(OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U) */ + mask_write 0XFD4800B4 0x0000FFF8 0x00000000 + # Register : CB @ 0XFD48031C

    + + # DT837748 Enable + # PSU_PCIE_ATTRIB_CB_CB1 0x0 + + # ECO Register 1 + #(OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U) */ + mask_write 0XFD48031C 0x00000002 0x00000000 + # Register : ATTR_35 @ 0XFD48008C

    + + # Active State PM Support. Indicates the level of active state power manag + # ement supported by the selected PCI Express Link, encoded as follows: 0 + # Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte + # d.; EP=0x0001; RP=0x0001 + # PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0 + + # Data Link Layer Link Active status notification is supported. This is op + # tional for Upstream ports.; EP=0x0000; RP=0x0000 + # PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP 1 + + # ATTR_35 + #(OFFSET, MASK, VALUE) (0XFD48008C, 0x0000B000U ,0x00008000U) */ + mask_write 0XFD48008C 0x0000B000 0x00008000 + # : PUTTING PCIE CONTROL IN RESET + # Register : RST_FPD_TOP @ 0XFD1A0100

    + + # PCIE control block level reset + # PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0 + + # FPD Block level software controlled reset + #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U) */ + mask_write 0XFD1A0100 0x00020000 0x00000000 + # : PCIE GPIO RESET + # : MASK_DATA_0_LSW LOW BANK [15:0] + # : MASK_DATA_0_MSW LOW BANK [25:16] + # : MASK_DATA_1_LSW LOW BANK [41:26] + # Register : MASK_DATA_1_LSW @ 0XFF0A0008

    + + # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + # Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + # Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + #(OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) */ + mask_write 0XFF0A0008 0xFFFFFFFF 0xFFDF0020 + # : MASK_DATA_1_MSW HIGH BANK [51:42] + # : MASK_DATA_1_LSW HIGH BANK [67:52] + # : MASK_DATA_1_LSW HIGH BANK [77:68] + # : CHECK PLL LOCK FOR LANE0 + # Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4

    + + # Status Read value of PLL Lock + # PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + mask_poll 0XFD4023E4 0x00000010 + # : CHECK PLL LOCK FOR LANE1 + # Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4

    + + # Status Read value of PLL Lock + # PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + mask_poll 0XFD4063E4 0x00000010 + # : CHECK PLL LOCK FOR LANE2 + # Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4

    + + # Status Read value of PLL Lock + # PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + mask_poll 0XFD40A3E4 0x00000010 + # : CHECK PLL LOCK FOR LANE3 + # Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4

    + + # Status Read value of PLL Lock + # PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + mask_poll 0XFD40E3E4 0x00000010 + # : SATA AHCI VENDOR SETTING + # Register : PP2C @ 0XFD0C00AC

    + + # CIBGMN: COMINIT Burst Gap Minimum. + # PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18 + + # CIBGMX: COMINIT Burst Gap Maximum. + # PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40 + + # CIBGN: COMINIT Burst Gap Nominal. + # PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18 + + # CINMP: COMINIT Negate Minimum Period. + # PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28 + + # PP2C - Port Phy2Cfg Register. This register controls the configuration o + # f the Phy Control OOB timing for the COMINIT parameters for either Port + # 0 or Port 1. The Port configured is controlled by the value programmed i + # nto the Port Config Register. + #(OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U) */ + mask_write 0XFD0C00AC 0xFFFFFFFF 0x28184018 + # Register : PP3C @ 0XFD0C00B0

    + + # CWBGMN: COMWAKE Burst Gap Minimum. + # PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06 + + # CWBGMX: COMWAKE Burst Gap Maximum. + # PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14 + + # CWBGN: COMWAKE Burst Gap Nominal. + # PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08 + + # CWNMP: COMWAKE Negate Minimum Period. + # PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E + + # PP3C - Port Phy3CfgRegister. This register controls the configuration of + # the Phy Control OOB timing for the COMWAKE parameters for either Port 0 + # or Port 1. The Port configured is controlled by the value programmed in + # to the Port Config Register. + #(OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U) */ + mask_write 0XFD0C00B0 0xFFFFFFFF 0x0E081406 + # Register : PP4C @ 0XFD0C00B4

    + + # BMX: COM Burst Maximum. + # PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13 + + # BNM: COM Burst Nominal. + # PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08 + + # SFD: Signal Failure Detection, if the signal detection de-asserts for a + # time greater than this then the OOB detector will determine this is a li + # ne idle and cause the PhyInit state machine to exit the Phy Ready State. + # A value of zero disables the Signal Failure Detector. The value is base + # d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving + # a nominal time of 500ns based on a 150MHz PMCLK. + # PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A + + # PTST: Partial to Slumber timer value, specific delay the controller shou + # ld apply while in partial before entering slumber. The value is bases on + # the system clock divided by 128, total delay = (Sys Clock Period) * PTS + # T * 128 + # PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06 + + # PP4C - Port Phy4Cfg Register. This register controls the configuration o + # f the Phy Control Burst timing for the COM parameters for either Port 0 + # or Port 1. The Port configured is controlled by the value programmed int + # o the Port Config Register. + #(OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U) */ + mask_write 0XFD0C00B4 0xFFFFFFFF 0x064A0813 + # Register : PP5C @ 0XFD0C00B8

    + + # RIT: Retry Interval Timer. The calculated value divided by two, the lowe + # r digit of precision is not needed. + # PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4 + + # RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev + # ice will transmit at a fixed rate ALIGNp after OOB has completed, for a + # fast SERDES it is suggested that this value be 54.2us / 4 + # PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF + + # PP5C - Port Phy5Cfg Register. This register controls the configuration o + # f the Phy Control Retry Interval timing for either Port 0 or Port 1. The + # Port configured is controlled by the value programmed into the Port Con + # fig Register. + #(OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U) */ + mask_write 0XFD0C00B8 0xFFFFFFFF 0x3FFC96A4 +} + +set psu_resetin_init_data { + # : PUTTING SERDES PERIPHERAL IN RESET + # : PUTTING USB0 IN RESET + # Register : RST_LPD_TOP @ 0XFF5E023C

    + + # USB 0 reset for control registers + # PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X1 + + # USB 0 sleep circuit reset + # PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X1 + + # USB 0 reset + # PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X1 + + # Software control register for the LPD block. + #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000540U) */ + mask_write 0XFF5E023C 0x00000540 0x00000540 + # : PUTTING GEM0 IN RESET + # Register : RST_LPD_IOU0 @ 0XFF5E0230

    + + # GEM 3 reset + # PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X1 + + # Software controlled reset for the GEMs + #(OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000008U) */ + mask_write 0XFF5E0230 0x00000008 0x00000008 + # : PUTTING SATA IN RESET + # Register : RST_FPD_TOP @ 0XFD1A0100

    + + # Sata block level reset + # PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X1 + + # FPD Block level software controlled reset + #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000002U) */ + mask_write 0XFD1A0100 0x00000002 0x00000002 + # : PUTTING PCIE IN RESET + # Register : RST_FPD_TOP @ 0XFD1A0100

    + + # PCIE config reset + # PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1 + + # PCIE control block level reset + # PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1 + + # PCIE bridge block level reset (AXI interface) + # PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1 + + # FPD Block level software controlled reset + #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U) */ + mask_write 0XFD1A0100 0x000E0000 0x000E0000 + # : PUTTING DP IN RESET + # Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

    + + # Two bits per lane. When set to 11, moves the GT to power down mode. When + # set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + # lane 1 + # PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA + + # Control PHY Power down + #(OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x0000000AU) */ + mask_write 0XFD4A0238 0x0000000F 0x0000000A + # Register : DP_PHY_RESET @ 0XFD4A0200

    + + # Set to '1' to hold the GT in reset. Clear to release. + # PSU_DP_DP_PHY_RESET_GT_RESET 0X1 + + # Reset the transmitter PHY. + #(OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000002U) */ + mask_write 0XFD4A0200 0x00000002 0x00000002 + # Register : RST_FPD_TOP @ 0XFD1A0100

    + + # Display Port block level reset (includes DPDMA) + # PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X1 + + # FPD Block level software controlled reset + #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00010000U) */ + mask_write 0XFD1A0100 0x00010000 0x00010000 +} + +set psu_ps_pl_isolation_removal_data { + # : PS-PL POWER UP REQUEST + # Register : REQ_PWRUP_INT_EN @ 0XFFD80118

    + + # Power-up Request Interrupt Enable for PL + # PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1 + + # Power-up Request Interrupt Enable Register. Writing a 1 to this location + # will unmask the interrupt. + #(OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U) */ + mask_write 0XFFD80118 0x00800000 0x00800000 + # Register : REQ_PWRUP_TRIG @ 0XFFD80120

    + + # Power-up Request Trigger for PL + # PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1 + + # Power-up Request Trigger Register. A write of one to this location will + # generate a power-up request to the PMU. + #(OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U) */ + mask_write 0XFFD80120 0x00800000 0x00800000 + # : POLL ON PL POWER STATUS + # Register : REQ_PWRUP_STATUS @ 0XFFD80110

    + + # Power-up Request Status for PL + # PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL 1 + mask_poll 0XFFD80110 0x00800000 0x00000000 +} + +set psu_afi_config { + # : AFI RESET + # Register : RST_FPD_TOP @ 0XFD1A0100

    + + # AF_FM0 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM0_RESET 0 + + # AF_FM1 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM1_RESET 0 + + # AF_FM2 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM2_RESET 0 + + # AF_FM3 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM3_RESET 0 + + # AF_FM4 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM4_RESET 0 + + # AF_FM5 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM5_RESET 0 + + # FPD Block level software controlled reset + #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00001F80U ,0x00000000U) */ + mask_write 0XFD1A0100 0x00001F80 0x00000000 + # Register : RST_LPD_TOP @ 0XFF5E023C

    + + # AFI FM 6 + # PSU_CRL_APB_RST_LPD_TOP_AFI_FM6_RESET 0 + + # Software control register for the LPD block. + #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00080000U ,0x00000000U) */ + mask_write 0XFF5E023C 0x00080000 0x00000000 + # : AFIFM INTERFACE WIDTH + # Register : afi_fs @ 0XFF419000

    + + # Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit + # AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + # width 11: reserved + # PSU_LPD_SLCR_AFI_FS_DW_SS2_SEL 0x2 + + # afi fs SLCR control register. Do not change the bits durin + #(OFFSET, MASK, VALUE) (0XFF419000, 0x00000300U ,0x00000200U) */ + mask_write 0XFF419000 0x00000300 0x00000200 + # Register : AFIFM_RDCTRL @ 0XFD380000

    + + # Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b + # 10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128-bit enabled + # PSU_AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH 0x0 + + # Read Channel Control Register + #(OFFSET, MASK, VALUE) (0XFD380000, 0x00000003U ,0x00000000U) */ + mask_write 0XFD380000 0x00000003 0x00000000 + # Register : AFIFM_WRCTRL @ 0XFD380014

    + + # Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2' + # b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128-bit enabled + # PSU_AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH 0x0 + + # Write Channel Control Register + #(OFFSET, MASK, VALUE) (0XFD380014, 0x00000003U ,0x00000000U) */ + mask_write 0XFD380014 0x00000003 0x00000000 +} + +set psu_ps_pl_reset_config_data { + # : PS PL RESET SEQUENCE + # : FABRIC RESET USING EMIO + # Register : MASK_DATA_5_MSW @ 0XFF0A002C

    + + # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + # PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW 0x8000 + + # Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits) + #(OFFSET, MASK, VALUE) (0XFF0A002C, 0xFFFF0000U ,0x80000000U) */ + mask_write 0XFF0A002C 0xFFFF0000 0x80000000 + # Register : DIRM_5 @ 0XFF0A0344

    + + # Operation is the same as DIRM_0[DIRECTION_0] + # PSU_GPIO_DIRM_5_DIRECTION_5 0x80000000 + + # Direction mode (GPIO Bank5, EMIO) + #(OFFSET, MASK, VALUE) (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U) */ + mask_write 0XFF0A0344 0xFFFFFFFF 0x80000000 + # Register : OEN_5 @ 0XFF0A0348

    + + # Operation is the same as OEN_0[OP_ENABLE_0] + # PSU_GPIO_OEN_5_OP_ENABLE_5 0x80000000 + + # Output enable (GPIO Bank5, EMIO) + #(OFFSET, MASK, VALUE) (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U) */ + mask_write 0XFF0A0348 0xFFFFFFFF 0x80000000 + # Register : DATA_5 @ 0XFF0A0054

    + + # Output Data + # PSU_GPIO_DATA_5_DATA_5 0x80000000 + + # Output Data (GPIO Bank5, EMIO) + #(OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) */ + mask_write 0XFF0A0054 0xFFFFFFFF 0x80000000 + mask_delay 0x00000000 1 + # : FABRIC RESET USING DATA_5 TOGGLE + # Register : DATA_5 @ 0XFF0A0054

    + + # Output Data + # PSU_GPIO_DATA_5_DATA_5 0X00000000 + + # Output Data (GPIO Bank5, EMIO) + #(OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFF0A0054 0xFFFFFFFF 0x00000000 + mask_delay 0x00000000 1 + # : FABRIC RESET USING DATA_5 TOGGLE + # Register : DATA_5 @ 0XFF0A0054

    + + # Output Data + # PSU_GPIO_DATA_5_DATA_5 0x80000000 + + # Output Data (GPIO Bank5, EMIO) + #(OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) */ + mask_write 0XFF0A0054 0xFFFFFFFF 0x80000000 +} + +proc psu_init {} { + # save current mode + set saved_mode [configparams force-mem-accesses] + # force accesses + configparams force-mem-accesses 1 + variable psu_mio_init_data + variable psu_peripherals_pre_init_data + variable psu_pll_init_data + variable psu_clock_init_data + variable psu_ddr_init_data + variable psu_peripherals_init_data + variable psu_resetin_init_data + variable psu_resetout_init_data + variable psu_serdes_init_data + variable psu_resetin_init_data + variable psu_peripherals_powerdwn_data + variable psu_afi_config + variable psu_ddr_qos_init_data + + init_ps [subst {$psu_mio_init_data $psu_peripherals_pre_init_data $psu_pll_init_data $psu_clock_init_data $psu_ddr_init_data }] + psu_ddr_phybringup_data + init_ps [subst {$psu_peripherals_init_data $psu_resetin_init_data }] + init_serdes + init_ps [subst {$psu_serdes_init_data $psu_resetout_init_data }] + init_peripheral + init_ps [subst {$psu_peripherals_powerdwn_data }] + init_ps [subst {$psu_afi_config }] + init_ps [subst {$psu_ddr_qos_init_data}] + # restore original mode + configparams force-mem-accesses $saved_mode +} + +proc psu_post_config {} { + variable psu_post_config_data + init_ps [subst {$psu_post_config_data}] +} + +proc psu_ps_pl_reset_config {} { + variable psu_ps_pl_reset_config_data + init_ps [subst {$psu_ps_pl_reset_config_data}] +} + +proc psu_ps_pl_isolation_removal {} { + variable psu_ps_pl_isolation_removal_data + init_ps [subst {$psu_ps_pl_isolation_removal_data}] +} + + +proc mask_read { addr mask } { + set curval "0x[string range [mrd -force $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + return $maskedval +} + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd -force $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd -force $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 1000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + +proc psu_mask_write { addr mask value } { + set curval "0x[string range [mrd -force $addr] end-8 end]" + set curval [expr {$curval & ~($mask)}] + set maskedval [expr {$value & $mask}] + set maskedval [expr {$curval | $maskedval}] + mwr -force $addr $maskedval +} + +proc serdes_fixcal_code {} { + + set MaskStatus 1 + array set match_pmos_code {} + array set match_nmos_code {} + array set match_ical_code {} + array set match_rcal_code {} + set p_code 0 + set n_code 0 + set i_code 0 + set r_code 0 + set repeat_count 0 + set L3_TM_CALIB_DIG20 0 + set L3_TM_CALIB_DIG19 0 + set L3_TM_CALIB_DIG18 0 + set L3_TM_CALIB_DIG16 0 + set L3_TM_CALIB_DIG15 0 + set L3_TM_CALIB_DIG14 0 + + set rdata 0 + + set rdata [mask_read 0XFD40289C 0xFFFFFFFF] + set rdata [expr $rdata & ~0x03 ] + set rdata [expr $rdata | 0x1] + mask_write 0XFD40289C 0xFFFFFFFF $rdata + #check supply good status before starting AFE sequencing + set count 1 + while 1 { + set rdata [mask_read 0xFD402B1C 0xFFFFFFFF] + set count [ expr { $count + 1 } ] + if { [expr $rdata & 0x0000000E] == 0x0000000E } { + break; + } + if { $count == 1000 } { + break; + } + } + + + for {set i 0} {$i<23 } {incr i } { + set match_pmos_code($i) 0; + set match_nmos_code($i) 0; + } + + for {set i 0} {$i<7} {incr i} { + set match_ical_code($i) 0; + set match_rcal_code($i) 0; + } + + while 1 { + #Clear ICM_CFG value + mask_write 0xFD410010 0xFFFFFFFF 0x00000000 + mask_write 0xFD410014 0xFFFFFFFF 0x00000000 + + #Set ICM_CFG value + #This will trigger recalibration of all stages + mask_write 0xFD410010 0xFFFFFFFF 0x00000001 + mask_write 0xFD410014 0xFFFFFFFF 0x00000000; + + #is calibration done? polling on L3_CALIB_DONE_STATUS + mask_poll 0xFD40EF14 0x2; + + #PMOS code + set p_code [mask_read 0xFD40EF18 0xFFFFFFFF]; + #NMOS code + set n_code [mask_read 0xFD40EF1C 0xFFFFFFFF]; + #ICAL code + set i_code [mask_read 0xFD40EF24 0xFFFFFFFF]; + #RX code + set r_code [mask_read 0xFD40EF28 0xFFFFFFFF]; + + + #xil_printf("#SERDES initialization VALUES NMOS = 0x%x, PMOS = 0x%x, ICAL = 0x%x, RCAL = 0x%x\n\r", p_code, n_code, i_code, r_code); + #PMOS code in acceptable range + if {($p_code >= 0x26) && ($p_code <= 0x3C)} { + set index [expr $p_code - 0x26] + set value $match_pmos_code($index) + incr value + set match_pmos_code($index) $value; + } + #NMOS code in acceptable range + if {($n_code >= 0x26) && ($n_code <= 0x3C)} { + set index [expr $n_code - 0x26] + set value $match_nmos_code($index) + incr value + set match_nmos_code($index) $value; + } + #PMOS code in acceptable range + if {($i_code >= 0xC) && ($i_code <= 0x12)} { + + set index [expr $i_code - 0xC] + set value $match_ical_code($index) + incr value + set match_ical_code($index) $value; + + } + #NMOS code in acceptable range + if {($r_code >= 0x6) && ($r_code <= 0xC)} { + set index [expr $r_code - 0x6] + set value $match_rcal_code($index) + incr value + set match_rcal_code($index) $value; + } + + incr repeat_count + if {$repeat_count > 10} { + break + } + } + + + + #find the valid code which resulted in maximum times in 10 iterations + for {set i 0 } {$i < 23} {incr i} { + + if {$match_pmos_code($i) >= $match_pmos_code(0) } { + set match_pmos_code(0) $match_pmos_code($i) + set p_code [expr 0x26 + $i] + } + if {$match_nmos_code($i) >= $match_nmos_code(0)} { + + set match_nmos_code(0) $match_nmos_code($i) + set n_code [expr 0x26 + $i]; + } + } + + for {set $i 0} {$i<7} {incr i} { + if {$match_ical_code($i) >= $match_ical_code(0)} { + set match_ical_code(0) $match_ical_code($i) + set i_code [expr 0xC + $i] + } + if {$match_rcal_code($i) >= $match_rcal_code(0)} { + set match_rcal_code(0) $match_rcal_code($i) + set r_code [expr 0x6 + $i] + } + } + #xil_printf("#SERDES initialization PASSED NMOS = 0x%x, PMOS = 0x%x, ICAL = 0x%x, RCAL = 0x%x\n\r", p_code, n_code, i_code, r_code); + #L3_TM_CALIB_DIG20[3] PSW MSB Override + #L3_TM_CALIB_DIG20[2:0] PSW Code [4:2] + #read DIG20 + set L3_TM_CALIB_DIG20 [mask_read 0xFD40EC50 0xFFFFFFF0]; + set L3_TM_CALIB_DIG20 [expr $L3_TM_CALIB_DIG20 | 0x8 | (($p_code>>2)&0x7)] + + + #L3_TM_CALIB_DIG19[7:6] PSW Code [1:0] + #L3_TM_CALIB_DIG19[5] PSW Override + #L3_TM_CALIB_DIG19[2] NSW MSB Override + #L3_TM_CALIB_DIG19[1:0] NSW Code [4:3] + #read DIG19 + set L3_TM_CALIB_DIG19 [mask_read 0xFD40EC4C 0xFFFFFF18] + set L3_TM_CALIB_DIG19 [expr $L3_TM_CALIB_DIG19 | (($p_code&0x3)<<6) | 0x20 | 0x4 | (($n_code>>3)&0x3)] + + #L3_TM_CALIB_DIG18[7:5] NSW Code [2:0] + #L3_TM_CALIB_DIG18[4] NSW Override + #read DIG18 + set L3_TM_CALIB_DIG18 [mask_read 0xFD40EC48 0xFFFFFF0F] + set L3_TM_CALIB_DIG18 [expr $L3_TM_CALIB_DIG18 | (($n_code&0x7)<<5) | 0x10] + + + #L3_TM_CALIB_DIG16[2:0] RX Code [3:1] + #read DIG16 + set L3_TM_CALIB_DIG16 [mask_read 0xFD40EC40 0xFFFFFFF8] + set L3_TM_CALIB_DIG16 [expr $L3_TM_CALIB_DIG16 | (($r_code>>1)&0x7)] + + #L3_TM_CALIB_DIG15[7] RX Code [0] + #L3_TM_CALIB_DIG15[6] RX CODE Override + #L3_TM_CALIB_DIG15[3] ICAL MSB Override + #L3_TM_CALIB_DIG15[2:0] ICAL Code [3:1] + #read DIG15 + set L3_TM_CALIB_DIG15 [mask_read 0xFD40EC3C 0xFFFFFF30] + set L3_TM_CALIB_DIG15 [expr $L3_TM_CALIB_DIG15 | (($r_code&0x1)<<7) | 0x40 | 0x8 | (($i_code>>1)&0x7)] + + #L3_TM_CALIB_DIG14[7] ICAL Code [0] + #L3_TM_CALIB_DIG14[6] ICAL Override + #read DIG14 + set L3_TM_CALIB_DIG14 [mask_read 0xFD40EC38 0xFFFFFF3F] + set L3_TM_CALIB_DIG14 [expr $L3_TM_CALIB_DIG14 | (($i_code&0x1)<<7) | 0x40] + + #Forces the calibration values + mask_write 0xFD40EC50 0xFFFFFFFF $L3_TM_CALIB_DIG20 + mask_write 0xFD40EC4C 0xFFFFFFFF $L3_TM_CALIB_DIG19 + mask_write 0xFD40EC48 0xFFFFFFFF $L3_TM_CALIB_DIG18 + mask_write 0xFD40EC40 0xFFFFFFFF $L3_TM_CALIB_DIG16 + mask_write 0xFD40EC3C 0xFFFFFFFF $L3_TM_CALIB_DIG15 + mask_write 0xFD40EC38 0xFFFFFFFF $L3_TM_CALIB_DIG14 + + + return $MaskStatus; + } +proc serdes_enb_coarse_saturation {} { + #/* + # * Enable PLL Coarse Code saturation Logic + # */ + mask_write 0xFD402094 0xFFFFFFFF 0x00000010 + mask_write 0xFD406094 0xFFFFFFFF 0x00000010 + mask_write 0xFD40A094 0xFFFFFFFF 0x00000010 + mask_write 0xFD40E094 0xFFFFFFFF 0x00000010 + +} + +proc init_serdes {} { + serdes_fixcal_code + serdes_enb_coarse_saturation + +} + +proc poll { addr mask data} { + set curval "0x[string range [mrd -force $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count 1 + while { $maskedval != $data } { + set curval "0x[string range [mrd -force $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + +proc init_peripheral {} { +#SMMU_REG Interrrupt Enable: Followig register need to be written all the time to properly catch SMMU messages. + mask_write 0xFD5F0018 0x8000001F 0x8000001F +} +proc psu_init_xppu_aper_ram {} { + +} + + +proc psu_lpd_protection {} { +} + +proc psu_ddr_protection {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable psu_ddr_xmpu0_data + variable psu_ddr_xmpu1_data + variable psu_ddr_xmpu2_data + variable psu_ddr_xmpu3_data + variable psu_ddr_xmpu4_data + variable psu_ddr_xmpu5_data + init_ps [subst {$psu_ddr_xmpu0_data $psu_ddr_xmpu1_data $psu_ddr_xmpu2_data $psu_ddr_xmpu3_data $psu_ddr_xmpu4_data $psu_ddr_xmpu5_data}] + + configparams force-mem-accesses $saved_mode +} + +proc psu_ocm_protection {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable psu_ocm_xmpu_data + init_ps [subst {$psu_ocm_xmpu_data }] + + configparams force-mem-accesses $saved_mode +} + +proc psu_fpd_protection {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable psu_fpd_xmpu_data + init_ps [subst {$psu_fpd_xmpu_data }] + + configparams force-mem-accesses $saved_mode +} + +proc psu_protection_lock {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable psu_protection_lock_data + init_ps [subst {$psu_protection_lock_data }] + + configparams force-mem-accesses $saved_mode +} + +proc psu_protection {} { + variable psu_apply_master_tz + init_ps [subst {$psu_apply_master_tz }] + psu_ddr_protection + psu_ocm_protection + psu_fpd_protection + psu_lpd_protection +} + +proc psu_ddr_phybringup_data {} { +mwr -force 0xFD080004 0x00040073 + +poll 0xFD080030 0x0000000F 0x0000000F + psu_mask_write 0xFD080004 0x00000001 0x00000001 +#poll for PHY initialization to complete +poll 0xFD080030 0x000000FF 0x0000001F + + psu_mask_write 0xFD070010 0x00000008 0x00000008 + psu_mask_write 0xFD0701B0 0x00000001 0x00000001 + psu_mask_write 0xFD070010 0x00000030 0x00000010 + psu_mask_write 0xFD070010 0x00000001 0x00000000 + psu_mask_write 0xFD070010 0x0000F000 0x00006000 + psu_mask_write 0xFD070014 0x0003FFFF 0x00000819 + psu_mask_write 0xFD070010 0x80000000 0x80000000 +poll 0xFD070018 0x00000001 0 + psu_mask_write 0xFD070010 0x00000030 0x00000010 + psu_mask_write 0xFD070010 0x00000001 0x00000000 + psu_mask_write 0xFD070010 0x0000F000 0x00006000 + psu_mask_write 0xFD070014 0x0003FFFF 0x00000899 + psu_mask_write 0xFD070010 0x80000000 0x80000000 +poll 0xFD070018 0x00000001 0 + psu_mask_write 0xFD070010 0x00000030 0x00000010 + psu_mask_write 0xFD070010 0x00000001 0x00000000 + psu_mask_write 0xFD070010 0x0000F000 0x00006000 + psu_mask_write 0xFD070014 0x0003FFFF 0x00000819 + psu_mask_write 0xFD070010 0x80000000 0x80000000 +poll 0xFD070018 0x00000001 0 + psu_mask_write 0xFD070010 0x00000008 0x00000000 +mwr -force 0xFD0701B0 0x00000001 +mwr -force 0xFD070320 0x00000001 +#//poll for DDR initialization to complete +poll 0xFD070004 0x0000000F 0x00000001 + + psu_mask_write 0xFD080014 0x00000040 0x00000040 +#Dummy reads before PHY training starts +mrd -force 0xFD070004 + #//dummy reads +mrd -force 0xFD070004 + #//dummy reads +mrd -force 0xFD070004 + #//dummy reads +mrd -force 0xFD070004 + #//dummy reads +mrd -force 0xFD070004 + #//dummy reads +mrd -force 0xFD070004 + #//dummy reads +psu_mask_write 0xFD080004 0xFFFFFFFF 0x0004FE01 + #trigger PHY training +poll 0xFD080030 0x00000FFF 0x00000FFF + + #Poll PUB_PGSR0 for Trng complete + + + # Run Vref training in static read mode +mwr -force 0xFD080200 0x100091C7 +mwr -force 0xFD080018 0x00F01EEF + psu_mask_write 0xFD08142C 0x00000030 0x00000030 + psu_mask_write 0xFD08146C 0x00000030 0x00000030 + psu_mask_write 0xFD0814AC 0x00000030 0x00000030 + psu_mask_write 0xFD0814EC 0x00000030 0x00000030 + psu_mask_write 0xFD08152C 0x00000030 0x00000030 +psu_mask_write 0xFD080004 0xFFFFFFFF 0x00060001 + + #trigger VreFPHY training +poll 0xFD080030 0x00004001 0x00004001 + + #//Poll PUB_PGSR0 for Trng complete +mwr -force 0xFD080200 0x800091C7 +mwr -force 0xFD080018 0x00F122E7 + psu_mask_write 0xFD08142C 0x00000030 0x00000000 + psu_mask_write 0xFD08146C 0x00000030 0x00000000 + psu_mask_write 0xFD0814AC 0x00000030 0x00000000 + psu_mask_write 0xFD0814EC 0x00000030 0x00000000 + psu_mask_write 0xFD08152C 0x00000030 0x00000000 +psu_mask_write 0xFD080004 0xFFFFFFFF 0x0000C001 + + #trigger VreFPHY training +poll 0xFD080030 0x00000C01 0x00000C01 + + #//Poll PUB_PGSR0 for Trng complete +mwr -force 0xFD070180 0x01000040 +mwr -force 0xFD070060 0x00000000 + psu_mask_write 0xFD080014 0x00000040 0x00000000 + + +} + diff --git a/Petalinux/project-spec/hw-description/psu_init_gpl.c b/Petalinux/project-spec/hw-description/psu_init_gpl.c new file mode 100644 index 0000000..a379ee3 --- /dev/null +++ b/Petalinux/project-spec/hw-description/psu_init_gpl.c @@ -0,0 +1,23833 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ + +#include +#include +#include "psu_init_gpl.h" +#define DPLL_CFG_LOCK_DLY 63 +#define DPLL_CFG_LOCK_CNT 625 +#define DPLL_CFG_LFHF 3 +#define DPLL_CFG_CP 3 +#define DPLL_CFG_RES 2 + +static int mask_pollOnValue(u32 add, u32 mask, u32 value); + +static int mask_poll(u32 add, u32 mask); + +static void mask_delay(u32 delay); + +static u32 mask_read(u32 add, u32 mask); + +static int serdes_rst_seq (u32 lane3_protocol, u32 lane3_rate, u32 lane2_protocol, u32 lane2_rate, u32 lane1_protocol, u32 lane1_rate, u32 lane0_protocol, u32 lane0_rate); + +static int serdes_bist_static_settings(u32 lane_active); + +static int serdes_bist_run(u32 lane_active); + +static int serdes_bist_result(u32 lane_active); + +static int serdes_illcalib_pcie_gen1 (u32 lane3_protocol, u32 lane3_rate, u32 lane2_protocol, u32 lane2_rate, u32 lane1_protocol, u32 lane1_rate, u32 lane0_protocol, u32 lane0_rate, u32 gen2_calib); + +static int serdes_illcalib (u32 lane3_protocol, u32 lane3_rate, u32 lane2_protocol, u32 lane2_rate, u32 lane1_protocol, u32 lane1_rate, u32 lane0_protocol, u32 lane0_rate); + +static +void PSU_Mask_Write(unsigned long offset, unsigned long mask, + unsigned long val) +{ + unsigned long RegVal = 0x0; + + RegVal = Xil_In32(offset); + RegVal &= ~(mask); + RegVal |= (val & mask); + Xil_Out32(offset, RegVal); +} + +static +void prog_reg(unsigned long addr, unsigned long mask, + unsigned long shift, + unsigned long value) +{ + int rdata = 0; + + rdata = Xil_In32(addr); + rdata = rdata & (~mask); + rdata = rdata | (value << shift); + Xil_Out32(addr, rdata); + } + +unsigned long psu_pll_init_data(void) +{ + /* + * RPLL INIT + */ + /* + * Register : RPLL_CFG @ 0XFF5E0034 + + * PLL loop filter resistor control + * PSU_CRL_APB_RPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRL_APB_RPLL_CFG_CP 0x4 + + * PLL loop filter high frequency capacitor control + * PSU_CRL_APB_RPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C82U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRL_APB_RPLL_CTRL_FBDIV 0x5a + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRL_APB_RPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00015A00U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_RPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_RPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_RPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFF5E0040 + + * RPLL is locked + * PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U) + */ + mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000002U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_RPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048 + + * Divisor value for this clock. + * PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the LPD, but used in the F + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRL_APB_RPLL_TO_FPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * RPLL FRAC CFG + */ + /* + * SYSMON CLOCK PRESET TO RPLL AGAIN TO AVOID GLITCH WHEN NEXT IOPLL WILL B + * E PUT IN BYPASS MODE + */ + /* + * Register : AMS_REF_CTRL @ 0XFF5E0108 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 1 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 35 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_AMS_REF_CTRL_CLKACT 1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01012300U) + */ + PSU_Mask_Write(CRL_APB_AMS_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01012300U); +/*##################################################################### */ + + /* + * IOPLL INIT + */ + /* + * Register : IOPLL_CFG @ 0XFF5E0024 + + * PLL loop filter resistor control + * PSU_CRL_APB_IOPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRL_APB_IOPLL_CFG_CP 0x4 + + * PLL loop filter high frequency capacitor control + * PSU_CRL_APB_IOPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E4B0C82U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x5a + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRL_APB_IOPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00015A00U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_IOPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_IOPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_IOPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFF5E0040 + + * IOPLL is locked + * PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000001U ,0x00000001U) + */ + mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000001U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_IOPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044 + + * Divisor value for this clock. + * PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the LPD, but used in the F + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * IOPLL FRAC CFG + */ + /* + * APU_PLL INIT + */ + /* + * Register : APLL_CFG @ 0XFD1A0024 + + * PLL loop filter resistor control + * PSU_CRF_APB_APLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_APLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_APLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U) + */ + PSU_Mask_Write(CRF_APB_APLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_APLL_CTRL_FBDIV 0x48 + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_APLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014800U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00717F00U, 0x00014800U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_APLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_APLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_APLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * APLL is locked + * PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000001U ,0x00000001U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000001U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_APLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : APLL_TO_LPD_CTRL @ 0XFD1A0048 + + * Divisor value for this clock. + * PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRF_APB_APLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * APLL FRAC CFG + */ + /* + * DDR_PLL INIT + */ + /* + * Register : DPLL_CFG @ 0XFD1A0030 + + * PLL loop filter resistor control + * PSU_CRF_APB_DPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_DPLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_DPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40 + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_DPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00717F00U, 0x00014000U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_DPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_DPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_DPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * DPLL is locked + * PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000002U ,0x00000002U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000002U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_DPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C + + * Divisor value for this clock. + * PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x2 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DPLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000200U); +/*##################################################################### */ + + /* + * DPLL FRAC CFG + */ + /* + * VIDEO_PLL INIT + */ + /* + * Register : VPLL_CFG @ 0XFD1A003C + + * PLL loop filter resistor control + * PSU_CRF_APB_VPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_VPLL_CFG_CP 0x4 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_VPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E4B0C82U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_VPLL_CTRL_FBDIV 0x5a + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_VPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00015A00U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_VPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_VPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_VPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * VPLL is locked + * PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000004U ,0x00000004U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000004U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_VPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050 + + * Divisor value for this clock. + * PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRF_APB_VPLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * VIDEO FRAC CFG + */ + + return 1; +} +unsigned long psu_clock_init_data(void) +{ + /* + * CLOCK CONTROL SLCR REGISTER + */ + /* + * Register : GEM3_REF_CTRL @ 0XFF5E005C + + * Clock active for the RX channel + * PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) + */ + PSU_Mask_Write(CRL_APB_GEM3_REF_CTRL_OFFSET, + 0x063F3F07U, 0x06010C00U); +/*##################################################################### */ + + /* + * Register : GEM_TSU_REF_CTRL @ 0XFF5E0100 + + * 6 bit divider + * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x0 + + * 6 bit divider + * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010600U) + */ + PSU_Mask_Write(CRL_APB_GEM_TSU_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010600U); +/*##################################################################### */ + + /* + * Register : USB0_BUS_REF_CTRL @ 0XFF5E0060 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U) + */ + PSU_Mask_Write(CRL_APB_USB0_BUS_REF_CTRL_OFFSET, + 0x023F3F07U, 0x02010600U); +/*##################################################################### */ + + /* + * Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0x3 + + * 6 bit divider + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x19 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x02031900U) + */ + PSU_Mask_Write(CRL_APB_USB3_DUAL_REF_CTRL_OFFSET, + 0x023F3F07U, 0x02031900U); +/*##################################################################### */ + + /* + * Register : QSPI_REF_CTRL @ 0XFF5E0068 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0x5 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010500U) + */ + PSU_Mask_Write(CRL_APB_QSPI_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010500U); +/*##################################################################### */ + + /* + * Register : SDIO1_REF_CTRL @ 0XFF5E0070 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x8 + + * 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010800U) + */ + PSU_Mask_Write(CRL_APB_SDIO1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010800U); +/*##################################################################### */ + + /* + * Register : SDIO_CLK_CTRL @ 0XFF18030C + + * MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO + * [51] 1: MIO [76] + * PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0 + + * SoC Debug Clock Control + * (OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_SDIO_CLK_CTRL_OFFSET, + 0x00020000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : UART0_REF_CTRL @ 0XFF5E0074 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_UART0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : UART1_REF_CTRL @ 0XFF5E0078 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_UART1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : I2C0_REF_CTRL @ 0XFF5E0120 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_I2C0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : I2C1_REF_CTRL @ 0XFF5E0124 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_I2C1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : CAN1_REF_CTRL @ 0XFF5E0088 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_CAN1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : CPU_R5_CTRL @ 0XFF5E0090 + + * Turing this off will shut down the OCM, some parts of the APM, and preve + * nt transactions going from the FPD to the LPD and could lead to system h + * ang + * PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_CPU_R5_CTRL_OFFSET, 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : IOU_SWITCH_CTRL @ 0XFF5E009C + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U) + */ + PSU_Mask_Write(CRL_APB_IOU_SWITCH_CTRL_OFFSET, + 0x01003F07U, 0x01000602U); +/*##################################################################### */ + + /* + * Register : PCAP_CTRL @ 0XFF5E00A4 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x8 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000800U) + */ + PSU_Mask_Write(CRL_APB_PCAP_CTRL_OFFSET, 0x01003F07U, 0x01000800U); +/*##################################################################### */ + + /* + * Register : LPD_SWITCH_CTRL @ 0XFF5E00A8 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_LPD_SWITCH_CTRL_OFFSET, + 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : LPD_LSBUS_CTRL @ 0XFF5E00AC + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U) + */ + PSU_Mask_Write(CRL_APB_LPD_LSBUS_CTRL_OFFSET, + 0x01003F07U, 0x01000F02U); +/*##################################################################### */ + + /* + * Register : DBG_LPD_CTRL @ 0XFF5E00B0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U) + */ + PSU_Mask_Write(CRL_APB_DBG_LPD_CTRL_OFFSET, + 0x01003F07U, 0x01000602U); +/*##################################################################### */ + + /* + * Register : ADMA_REF_CTRL @ 0XFF5E00B8 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_ADMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : PL0_REF_CTRL @ 0XFF5E00C0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xc + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010C02U) + */ + PSU_Mask_Write(CRL_APB_PL0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010C02U); +/*##################################################################### */ + + /* + * Register : PL1_REF_CTRL @ 0XFF5E00C4 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_PL1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_PL1_REF_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00C4, 0x013F3F07U ,0x01010F02U) + */ + PSU_Mask_Write(CRL_APB_PL1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F02U); +/*##################################################################### */ + + /* + * Register : AMS_REF_CTRL @ 0XFF5E0108 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1e + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011E02U) + */ + PSU_Mask_Write(CRL_APB_AMS_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01011E02U); +/*##################################################################### */ + + /* + * Register : DLL_REF_CTRL @ 0XFF5E0104 + + * 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an + * issue, but designers must be aware.) + * PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_DLL_REF_CTRL_OFFSET, + 0x00000007U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128 + + * 6 bit divider + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf + + * 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may + * only be toggled after 4 cycles of the old clock and 4 cycles of the new + * clock. This is not usually an issue, but designers must be aware.) + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U) + */ + PSU_Mask_Write(CRL_APB_TIMESTAMP_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000F00U); +/*##################################################################### */ + + /* + * Register : SATA_REF_CTRL @ 0XFD1A00A0 + + * 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_SATA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : PCIE_REF_CTRL @ 0XFD1A00B4 + + * 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only + * be toggled after 4 cycles of the old clock and 4 cycles of the new cloc + * k. This is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_PCIE_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070 + + * 6 bit divider + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x5 + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010500U) + */ + PSU_Mask_Write(CRF_APB_DP_VIDEO_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010500U); +/*##################################################################### */ + + /* + * Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074 + + * 6 bit divider + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0x14 + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01011403U) + */ + PSU_Mask_Write(CRF_APB_DP_AUDIO_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01011403U); +/*##################################################################### */ + + /* + * Register : DP_STC_REF_CTRL @ 0XFD1A007C + + * 6 bit divider + * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0x13 + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg + * led after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01011303U) + */ + PSU_Mask_Write(CRF_APB_DP_STC_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01011303U); +/*##################################################################### */ + + /* + * Register : ACPU_CTRL @ 0XFD1A0060 + + * 6 bit divider + * PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1 + + * 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock. For the half spee + * d APU Clock + * PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1 + + * Clock active signal. Switch to 0 to disable the clock. For the full spee + * d ACPUX Clock. This will shut off the high speed clock to the entire APU + * PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U) + */ + PSU_Mask_Write(CRF_APB_ACPU_CTRL_OFFSET, 0x03003F07U, 0x03000100U); +/*##################################################################### */ + + /* + * Register : DBG_FPD_CTRL @ 0XFD1A0068 + + * 6 bit divider + * PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2 + + * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_DBG_FPD_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DDR_CTRL @ 0XFD1A0080 + + * 6 bit divider + * PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2 + + * 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an i + * ssue, but designers must be aware.) + * PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DDR_CTRL_OFFSET, 0x00003F07U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : GPU_REF_CTRL @ 0XFD1A0084 + + * 6 bit divider + * PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1 + + * 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock, which will stop c + * lock for GPU (and both Pixel Processors). + * PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1 + + * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor + * PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1 + + * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor + * PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U) + */ + PSU_Mask_Write(CRF_APB_GPU_REF_CTRL_OFFSET, + 0x07003F07U, 0x07000100U); +/*##################################################################### */ + + /* + * Register : GDMA_REF_CTRL @ 0XFD1A00B8 + + * 6 bit divider + * PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_GDMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DPDMA_REF_CTRL @ 0XFD1A00BC + + * 6 bit divider + * PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_DPDMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0 + + * 6 bit divider + * PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000203U) + */ + PSU_Mask_Write(CRF_APB_TOPSW_MAIN_CTRL_OFFSET, + 0x01003F07U, 0x01000203U); +/*##################################################################### */ + + /* + * Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4 + + * 6 bit divider + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5 + + * 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U) + */ + PSU_Mask_Write(CRF_APB_TOPSW_LSBUS_CTRL_OFFSET, + 0x01003F07U, 0x01000502U); +/*##################################################################### */ + + /* + * Register : DBG_TSTMP_CTRL @ 0XFD1A00F8 + + * 6 bit divider + * PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2 + + * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DBG_TSTMP_CTRL_OFFSET, + 0x00003F07U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : IOU_TTC_APB_CLK @ 0XFF180380 + + * 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se + * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5 + * clock for the APB interface of TTC0 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se + * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5 + * clock for the APB interface of TTC1 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se + * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5 + * clock for the APB interface of TTC2 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se + * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5 + * clock for the APB interface of TTC3 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0 + + * TTC APB clock select + * (OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_IOU_TTC_APB_CLK_OFFSET, + 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : WDT_CLK_SEL @ 0XFD610100 + + * System watchdog timer clock source selection: 0: Internal APB clock 1: E + * xternal (PL clock via EMIO or Pinout clock via MIO) + * PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(FPD_SLCR_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : WDT_CLK_SEL @ 0XFF180300 + + * System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock from PL via EMIO, or from pinout via MIO + * PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050 + + * System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock pss_ref_clk + * PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_ddr_init_data(void) +{ + /* + * DDR INITIALIZATION + */ + /* + * DDR CONTROLLER RESET + */ + /* + * Register : RST_DDR_SS @ 0XFD1A0108 + + * DDR block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1 + + * DDR sub system block level reset + * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MSTR @ 0XFD070000 + + * Indicates the configuration of the device used in the system. - 00 - x4 + * device - 01 - x8 device - 10 - x16 device - 11 - x32 device + * PSU_DDRC_MSTR_DEVICE_CONFIG 0x2 + + * Choose which registers are used. - 0 - Original registers - 1 - Shadow r + * egisters + * PSU_DDRC_MSTR_FREQUENCY_MODE 0x0 + + * Only present for multi-rank configurations. Each bit represents one rank + * . For two-rank configurations, only bits[25:24] are present. - 1 - popul + * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow + * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others - + * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran + * k - 0011 - Two ranks - 1111 - Four ranks + * PSU_DDRC_MSTR_ACTIVE_RANKS 0x1 + + * SDRAM burst length used: - 0001 - Burst length of 2 (only supported for + * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur + * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other + * values are reserved. This controls the burst size used to access the SDR + * AM. This must match the burst length mode register setting in the SDRAM. + * (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) + * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH + * is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 + * PSU_DDRC_MSTR_BURST_RDWR 0x4 + + * Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low + * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for + * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC + * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi + * s bit must be set to '0'. + * PSU_DDRC_MSTR_DLL_OFF_MODE 0x0 + + * Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full + * DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter + * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is + * only supported when the SDRAM bus width is a multiple of 16, and quarter + * bus width mode is only supported when the SDRAM bus width is a multiple + * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid + * th refers to DQ bus width (excluding any ECC width). + * PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0 + + * 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D + * RAM in normal mode (1N). This register can be changed, only when the Con + * troller is in self-refresh mode. This signal must be set the same value + * as MR3 bit A3. Note: Geardown mode is not supported if the configuration + * parameter MEMC_CMD_RTN2IDLE is set + * PSU_DDRC_MSTR_GEARDOWN_MODE 0x0 + + * If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin + * g, all command signals (except chip select) are held for 2 clocks on the + * SDRAM bus. Chip select is asserted on the second cycle of the command N + * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti + * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i + * s set Note: 2T timing is not supported in DDR4 geardown mode. + * PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0 + + * When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci + * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full + * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer + * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is + * disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl + * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported + * , and this bit must be set to '0' + * PSU_DDRC_MSTR_BURSTCHOP 0x0 + + * Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d + * evice in use Present only in designs configured to support LPDDR4. + * PSU_DDRC_MSTR_LPDDR4 0x0 + + * Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device + * in use Present only in designs configured to support DDR4. + * PSU_DDRC_MSTR_DDR4 0x1 + + * Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d + * evice in use Present only in designs configured to support LPDDR3. + * PSU_DDRC_MSTR_LPDDR3 0x0 + + * Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d + * evice in use Present only in designs configured to support LPDDR2. + * PSU_DDRC_MSTR_LPDDR2 0x0 + + * Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de + * vice in use Only present in designs that support DDR3. + * PSU_DDRC_MSTR_DDR3 0x0 + + * Master Register + * (OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x81040010U) + */ + PSU_Mask_Write(DDRC_MSTR_OFFSET, 0xE30FBE3DU, 0x81040010U); +/*##################################################################### */ + + /* + * Register : MRCTRL0 @ 0XFD070010 + + * Setting this register bit to 1 triggers a mode register read or write op + * eration. When the MR operation is complete, the uMCTL2 automatically cle + * ars this bit. The other register fields of this register must be written + * in a separate APB transaction, before setting this mr_wr bit. It is rec + * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper + * ating modes. + * PSU_DDRC_MRCTRL0_MR_WR 0x0 + + * Address of the mode register that is to be written to. - 0000 - MR0 - 00 + * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR + * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data + * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als + * o used for writing to control words of RDIMMs. In that case, it correspo + * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[ + * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a + * s the bit[2:0] must be set to an appropriate value which is considered b + * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R + * DIMMs. + * PSU_DDRC_MRCTRL0_MR_ADDR 0x0 + + * Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire + * d to access all ranks, so all bits should be set to 1. However, for mult + * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess + * ary to access ranks individually. Examples (assume uMCTL2 is configured + * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x + * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran + * ks 0, 1, 2 and 3 + * PSU_DDRC_MRCTRL0_MR_RANK 0x3 + + * Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b + * efore automatic SDRAM initialization routine or not. For DDR4, this bit + * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init + * ialization. For LPDDR4, this bit can be used to program additional mode + * registers before automatic SDRAM initialization if necessary. Note: This + * must be cleared to 0 after completing Software operation. Otherwise, SD + * RAM initialization routine will not re-start. - 0 - Software interventio + * n is not allowed - 1 - Software intervention is allowed + * PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0 + + * Indicates whether the mode register operation is MRS in PDA mode or not + * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode + * PSU_DDRC_MRCTRL0_PDA_EN 0x0 + + * Indicates whether the mode register operation is MRS or WR/RD for MPR (o + * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR + * PSU_DDRC_MRCTRL0_MPR_EN 0x0 + + * Indicates whether the mode register operation is read or write. Only use + * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read + * PSU_DDRC_MRCTRL0_MR_TYPE 0x0 + + * Mode Register Read/Write Control Register 0. Note: Do not enable more th + * an one of the following fields simultaneously: - sw_init_int - pda_en - + * mpr_en + * (OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U) + */ + PSU_Mask_Write(DDRC_MRCTRL0_OFFSET, 0x8000F03FU, 0x00000030U); +/*##################################################################### */ + + /* + * Register : DERATEEN @ 0XFD070020 + + * Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us + * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d + * esigns configured to support LPDDR4. The required number of cycles for d + * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p + * eriod, and rounding up the next integer. + * PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x2 + + * Derate byte Present only in designs configured to support LPDDR2/LPDDR3/ + * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma + * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. + * PSU_DDRC_DERATEEN_DERATE_BYTE 0x0 + + * Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl + * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all + * LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ + * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8 + * 75 ns is less than a core_ddrc_core_clk period or not. + * PSU_DDRC_DERATEEN_DERATE_VALUE 0x0 + + * Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin + * g parameter derating is enabled using MR4 read value. Present only in de + * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set + * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. + * PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0 + + * Temperature Derate Enable Register + * (OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000200U) + */ + PSU_Mask_Write(DDRC_DERATEEN_OFFSET, 0x000003F3U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : DERATEINT @ 0XFD070024 + + * Interval between two MR4 reads, used to derate the timing parameters. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r + * egister must not be set to zero + * PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000 + + * Temperature Derate Interval Register + * (OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U) + */ + PSU_Mask_Write(DDRC_DERATEINT_OFFSET, 0xFFFFFFFFU, 0x00800000U); +/*##################################################################### */ + + /* + * Register : PWRCTL @ 0XFD070030 + + * Self refresh state is an intermediate state to enter to Self refresh pow + * er down state or exit Self refresh power down state for LPDDR4. This reg + * ister controls transition from the Self refresh state. - 1 - Prohibit tr + * ansition from Self refresh state - 0 - Allow transition from Self refres + * h state + * PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0 + + * A value of 1 to this register causes system to move to Self Refresh stat + * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa + * re Entry to Self Refresh - 0 - Software Exit from Self Refresh + * PSU_DDRC_PWRCTL_SELFREF_SW 0x0 + + * When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode + * when the transaction store is empty. This register must be reset to '0' + * to bring uMCTL2 out of maximum power saving mode. Present only in desig + * ns configured to support DDR4. For non-DDR4, this register should not be + * set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if + * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r + * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRCTL_MPSM_EN 0x0 + + * Enable the assertion of dfi_dram_clk_disable whenever a clock is not req + * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. + * Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only + * be asserted in Self Refresh. In DDR4, can be asserted in following: - i + * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca + * n be asserted in following: - in Self Refresh - in Power Down - in Deep + * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse + * rted in following: - in Self Refresh Power Down - in Power Down - during + * Normal operation (Clock Stop) + * PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0 + + * When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the + * transaction store is empty. This register must be reset to '0' to bring + * uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM + * initialization on deep power-down exit. Present only in designs configu + * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD + * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0 + + * If true then the uMCTL2 goes into power-down after a programmable number + * of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_ + * x32). This register bit may be re-programmed during the course of normal + * operation. + * PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0 + + * If true then the uMCTL2 puts the SDRAM into Self Refresh after a program + * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG. + * selfref_to_x32)'. This register bit may be re-programmed during the cour + * se of normal operation. + * PSU_DDRC_PWRCTL_SELFREF_EN 0x0 + + * Low Power Control Register + * (OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PWRCTL_OFFSET, 0x0000007FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PWRTMG @ 0XFD070034 + + * After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_ + * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40 + + * Minimum deep power-down time. For mDDR, value from the JEDEC specificati + * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL + * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE + * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i + * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + * ONLY. + * PSU_DDRC_PWRTMG_T_DPD_X4096 0x84 + + * After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_ + * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10 + + * Low Power Timing Register + * (OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U) + */ + PSU_Mask_Write(DDRC_PWRTMG_OFFSET, 0x00FFFF1FU, 0x00408410U); +/*##################################################################### */ + + /* + * Register : RFSHCTL0 @ 0XFD070050 + + * Threshold value in number of clock cycles before the critical refresh or + * page timer expires. A critical refresh is to be issued before this thre + * shold is reached. It is recommended that this not be changed from the de + * fault value, currently shown as 0x2. It must always be less than interna + * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u + * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i + * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n + * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo + * cks. + * PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2 + + * If the refresh timer (tRFCnom, also known as tREFI) has expired at least + * once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then + * a speculative refresh may be performed. A speculative refresh is a refr + * esh performed at a time when refresh would be useful, but before it is a + * bsolutely required. When the SDRAM bus is idle for a period of time dete + * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired + * at least once since the last refresh, then a speculative refresh is per + * formed. Speculative refreshes continues successively until there are no + * refreshes pending or until new reads or writes are issued to the uMCTL2. + * FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10 + + * The programmed value + 1 is the number of refresh timeouts that is allow + * ed to accumulate before traffic is blocked and the refreshes are forced + * to execute. Closing pages to perform a refresh is a one-time penalty tha + * t must be paid for each group of refreshes. Therefore, performing refres + * hes in a burst reduces the per-refresh penalty of these page closings. H + * igher numbers for RFSHCTL.refresh_burst slightly increases utilization; + * lower numbers decreases the worst-case latency associated with refreshes + * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh + * For information on burst refresh feature refer to section 3.9 of DDR2 J + * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe + * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF + * I cycles using the burst refresh feature. In DDR4 mode, according to Fin + * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre + * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda + * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens + * ure that tRFCmax is not violated due to a PHY-initiated update occurring + * shortly before a refresh burst was due. In this situation, the refresh + * burst will be delayed until the PHY-initiated update is complete. + * PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0 + + * - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + * traffic to flow to other banks. Per bank refresh is not supported by all + * LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4 + * PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0 + + * Refresh Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U) + */ + PSU_Mask_Write(DDRC_RFSHCTL0_OFFSET, 0x00F1F1F4U, 0x00210000U); +/*##################################################################### */ + + /* + * Register : RFSHCTL1 @ 0XFD070054 + + * Refresh timer start for rank 1 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32 0x0 + + * Refresh timer start for rank 0 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32 0x0 + + * Refresh Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD070054, 0x0FFF0FFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_RFSHCTL1_OFFSET, 0x0FFF0FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RFSHCTL3 @ 0XFD070060 + + * Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix + * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11 + * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No + * te: The on-the-fly modes is not supported in this version of the uMCTL2. + * Note: This must be set up while the Controller is in reset or while the + * Controller is in self-refresh mode. Changing this during normal operati + * on is not allowed. Making this a dynamic register will be supported in f + * uture version of the uMCTL2. + * PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0 + + * Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + * the refresh register(s) have been updated. The value is automatically up + * dated when exiting reset, so it does not need to be toggled initially. + * PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0 + + * When '1', disable auto-refresh generated by the uMCTL2. When auto-refres + * h is disabled, the SoC core must generate refreshes using the registers + * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a + * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1 + * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 + * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d + * isable auto-refresh is not supported, and this bit must be set to '0'. T + * his register field is changeable on the fly. + * PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1 + + * Refresh Control Register 3 + * (OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_RFSHCTL3_OFFSET, 0x00000073U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : RFSHTMG @ 0XFD070064 + + * tREFI: Average time interval between refreshes per rank (Specification: + * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, + * LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre + * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE + * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + * register should be set to tREFIpb For configurations with MEMC_FREQ_RAT + * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val + * ue is different depending on the refresh mode. The user should program t + * he appropriate value from the spec based on the value programmed in the + * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea + * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th + * an 0x1. Unit: Multiples of 32 clocks. + * PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x81 + + * Used only when LPDDR3 memory type is connected. Should only be changed w + * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r + * equired by some LPDDR3 devices which comply with earlier versions of the + * LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 + * - tREFBW parameter used + * PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1 + + * tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F + * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t + * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro + * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using + * all-bank refreshes, the tRFCmin value in the above equations is equal to + * tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq + * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above + * equations is different depending on the refresh mode (fixed 1X,2X,4X) an + * d the device density. The user should program the appropriate value from + * the spec based on the 'refresh_mode' and the device density that is use + * d. Unit: Clocks. + * PSU_DDRC_RFSHTMG_T_RFC_MIN 0xbb + + * Refresh Timing Register + * (OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x008180BBU) + */ + PSU_Mask_Write(DDRC_RFSHTMG_OFFSET, 0x0FFF83FFU, 0x008180BBU); +/*##################################################################### */ + + /* + * Register : ECCCFG0 @ 0XFD070070 + + * Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U + * SE_RMW is defined + * PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1 + + * ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov + * er 1 beat - all other settings are reserved for future use + * PSU_DDRC_ECCCFG0_ECC_MODE 0x0 + + * ECC Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U) + */ + PSU_Mask_Write(DDRC_ECCCFG0_OFFSET, 0x00000017U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : ECCCFG1 @ 0XFD070074 + + * Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da + * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat + * a_poison_en=1 + * PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0 + + * Enable ECC data poisoning - introduces ECC errors on writes to address s + * pecified by the ECCPOISONADDR0/1 registers + * PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0 + + * ECC Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_ECCCFG1_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CRCPARCTL1 @ 0XFD0700C4 + + * The maximum number of DFI PHY clock cycles allowed from the assertion of + * the dfi_rddata_en signal to the assertion of each of the corresponding + * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing + * parameter tphy_rdlat. Refer to PHY specification for correct value. This + * value it only used for detecting read data timeout when DDR4 retry is e + * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: + * - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r + * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 + * : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d + * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ + * rdlat < 'd114 Unit: DFI Clocks + * PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10 + + * After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa + * re has an option to read the mode registers in the DRAM before the hardw + * are begins the retry process - 1: Wait for software to read/write the mo + * de registers before hardware begins the retry. After software is done wi + * th its operations, it will clear the alert interrupt register bit - 0: H + * ardware can begin the retry right away after the dfi_alert_n pulse goes + * away. The value on this register is valid only when retry is enabled (PA + * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t + * he software doesn't clear the interrupt register after handling the pari + * ty/CRC error, then the hardware will not begin the retry process and the + * system will hang. In the case of Parity/CRC error, there are two possib + * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten + * t parity' mode register bit is NOT set: the commands sent during retry a + * nd normal operation are executed without parity checking. The value in t + * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent + * parity' mode register bit is SET: Parity checking is done for commands s + * ent during retry and normal operation. If multiple errors occur before M + * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don' + * t care'. + * PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1 + + * - 1: Enable command retry mechanism in case of C/A Parity or CRC error - + * 0: Disable command retry mechanism when C/A Parity or CRC features are + * enabled. Note that retry functionality is not supported if burst chop is + * enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF + * SHCTL3.dis_auto_refresh = 1) + * PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0 + + * CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no + * t includes DM signal Present only in designs configured to support DDR4. + * PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0 + + * CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio + * n of CRC The setting of this register should match the CRC mode register + * setting in the DRAM. + * PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0 + + * C/A Parity enable register - 1: Enable generation of C/A parity and dete + * ction of C/A parity error - 0: Disable generation of C/A parity and disa + * ble detection of C/A parity error If RCD's parity error detection or SDR + * AM's parity detection is enabled, this register should be 1. + * PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0 + + * CRC Parity Control Register1 + * (OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U) + */ + PSU_Mask_Write(DDRC_CRCPARCTL1_OFFSET, 0x3F000391U, 0x10000200U); +/*##################################################################### */ + + /* + * Register : CRCPARCTL2 @ 0XFD0700C8 + + * Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M + * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT + * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i + * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. + * PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40 + + * Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX + * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW + * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille + * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. + * PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5 + + * Indicates the maximum duration in number of DRAM clock cycles for which + * a command should be held in the Command Retry FIFO before it is popped o + * ut. Every location in the Command Retry FIFO has an associated down coun + * ting timer that will use this register as the start value. The down coun + * ting starts when a command is loaded into the FIFO. The timer counts dow + * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe + * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err + * or occurs before the counter reaches zero. The counter is reset to 0, af + * ter all the commands in the FIFO are retried. Recommended(minimum) value + * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten + * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable + * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R + * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be + * in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n + * ) should be considered. Note 3: Use the worst case(longer) value for PHY + * Latencies/Board delay Note 4: The Recommended values are minimum value + * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max + * value can be set to this register is defined below: - MEMC_BURST_LENGTH + * == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 + * Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b + * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod + * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C + * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC= + * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 + * Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full + * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod + * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC + * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF + * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma + * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal + * . + * PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f + + * CRC Parity Control Register2 + * (OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU) + */ + PSU_Mask_Write(DDRC_CRCPARCTL2_OFFSET, 0x01FF1F3FU, 0x0040051FU); +/*##################################################################### */ + + /* + * Register : INIT0 @ 0XFD0700D0 + + * If lower bit is enabled the SDRAM initialization routine is skipped. The + * upper bit decides what state the controller starts up in when reset is + * removed - 00 - SDRAM Intialization routine is run after power-up - 01 - + * SDRAM Intialization routine is skipped after power-up. Controller starts + * up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p + * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ + * ation routine is run after power-up. Note: The only 2'b00 is supported f + * or LPDDR4 in this version of the uMCTL2. + * PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0 + + * Cycles to wait after driving CKE high to start the SDRAM initialization + * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req + * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD + * R3 typically requires this to be programmed for a delay of 200 us. LPDDR + * 4 typically requires this to be programmed for a delay of 2 us. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi + * ded by 2, and round it up to next integer value. + * PSU_DDRC_INIT0_POST_CKE_X1024 0x2 + + * Cycles to wait after reset before driving CKE high to start the SDRAM in + * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi + * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD + * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati + * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by + * 2, and round it up to next integer value. + * PSU_DDRC_INIT0_PRE_CKE_X1024 0x106 + + * SDRAM Initialization Register 0 + * (OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U) + */ + PSU_Mask_Write(DDRC_INIT0_OFFSET, 0xC3FF0FFFU, 0x00020106U); +/*##################################################################### */ + + /* + * Register : INIT1 @ 0XFD0700D4 + + * Number of cycles to assert SDRAM reset signal during init sequence. This + * is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo + * r use with a DDR PHY, this should be set to a minimum of 1 + * PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2 + + * Cycles to wait after completing the SDRAM initialization sequence before + * starting the dynamic scheduler. Unit: Counts of a global timer that pul + * ses every 32 clock cycles. There is no known specific requirement for th + * is; it may be set to zero. + * PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0 + + * Wait period before driving the OCD complete command to SDRAM. Unit: Coun + * ts of a global timer that pulses every 32 clock cycles. There is no know + * n specific requirement for this; it may be set to zero. + * PSU_DDRC_INIT1_PRE_OCD_X32 0x0 + + * SDRAM Initialization Register 1 + * (OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U) + */ + PSU_Mask_Write(DDRC_INIT1_OFFSET, 0x01FF7F0FU, 0x00020000U); +/*##################################################################### */ + + /* + * Register : INIT2 @ 0XFD0700D8 + + * Idle time after the reset command, tINIT4. Present only in designs confi + * gured to support LPDDR2. Unit: 32 clock cycles. + * PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23 + + * Time to wait after the first CKE high, tINIT2. Present only in designs c + * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t + * ypically requires 5 x tCK delay. + * PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5 + + * SDRAM Initialization Register 2 + * (OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U) + */ + PSU_Mask_Write(DDRC_INIT2_OFFSET, 0x0000FF0FU, 0x00002305U); +/*##################################################################### */ + + /* + * Register : INIT3 @ 0XFD0700DC + + * DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he + * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value + * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP + * DDR3/LPDDR4 - Value to write to MR1 register + * PSU_DDRC_INIT3_MR 0x730 + + * DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti + * ng in this register is ignored. The uMCTL2 sets those bits appropriately + * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu + * ation mode training is enabled, this bit is set appropriately by the uMC + * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/ + * LPDDR3/LPDDR4 - Value to write to MR2 register + * PSU_DDRC_INIT3_EMR 0x301 + + * SDRAM Initialization Register 3 + * (OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x07300301U) + */ + PSU_Mask_Write(DDRC_INIT3_OFFSET, 0xFFFFFFFFU, 0x07300301U); +/*##################################################################### */ + + /* + * Register : INIT4 @ 0XFD0700E0 + + * DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 + * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus + * ed + * PSU_DDRC_INIT4_EMR2 0x20 + + * DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 + * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis + * ter + * PSU_DDRC_INIT4_EMR3 0x200 + + * SDRAM Initialization Register 4 + * (OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U) + */ + PSU_Mask_Write(DDRC_INIT4_OFFSET, 0xFFFFFFFFU, 0x00200200U); +/*##################################################################### */ + + /* + * Register : INIT5 @ 0XFD0700E4 + + * ZQ initial calibration, tZQINIT. Present only in designs configured to s + * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica + * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir + * es 1 us. + * PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21 + + * Maximum duration of the auto initialization, tINIT5. Present only in des + * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir + * es 10 us. + * PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4 + + * SDRAM Initialization Register 5 + * (OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U) + */ + PSU_Mask_Write(DDRC_INIT5_OFFSET, 0x00FF03FFU, 0x00210004U); +/*##################################################################### */ + + /* + * Register : INIT6 @ 0XFD0700E8 + + * DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT6_MR4 0x0 + + * DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT6_MR5 0x6c0 + + * SDRAM Initialization Register 6 + * (OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U) + */ + PSU_Mask_Write(DDRC_INIT6_OFFSET, 0xFFFFFFFFU, 0x000006C0U); +/*##################################################################### */ + + /* + * Register : INIT7 @ 0XFD0700EC + + * DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT7_MR6 0x819 + + * SDRAM Initialization Register 7 + * (OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U) + */ + PSU_Mask_Write(DDRC_INIT7_OFFSET, 0xFFFF0000U, 0x08190000U); +/*##################################################################### */ + + /* + * Register : DIMMCTL @ 0XFD0700F0 + + * Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r + * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp + * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. + * PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0 + + * Enable for BG1 bit of MRS command. BG1 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have BG1 are attached and + * both the CA parity and the Output Inversion are enabled, this must be s + * et to 0, so that the calculation of CA parity will not include BG1 bit. + * Note: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. If address mirroring is enab + * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En + * abled - 0 - Disabled + * PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1 + + * Enable for A17 bit of MRS command. A17 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have A17 are attached and + * the Output Inversion are enabled, this must be set to 0, so that the ca + * lculation of CA parity will not include A17 bit. Note: This has no effec + * t on the address of any other memory accesses, or of software-driven mod + * e register accesses. - 1 - Enabled - 0 - Disabled + * PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0 + + * Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM + * M implements the Output Inversion feature by default, which means that t + * he following address, bank address and bank group bits of B-side DRAMs a + * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en + * sures that, for mode register accesses generated by the uMCTL2 during th + * e automatic initialization routine and enabling of a particular DDR4 fea + * ture, separate A-side and B-side mode register accesses are generated. F + * or B-side mode register accesses, these bits are inverted within the uMC + * TL2 to compensate for this RDIMM inversion. Note: This has no effect on + * the address of any other memory accesses, or of software-driven mode reg + * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - + * Do not implement output inversion for B-side DRAMs. + * PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0 + + * Address Mirroring Enable (for multi-rank UDIMM implementations and multi + * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement + * address mirroring for odd ranks, which means that the following address + * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, + * A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t + * his bit ensures that, for mode register accesses during the automatic in + * itialization routine, these bits are swapped within the uMCTL2 to compen + * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial + * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th + * e automatic MRS access to enable/disable of a particular DDR4 feature. N + * ote: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. This is not supported for mDD + * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 + * output of MRS for the odd ranks is same as BG0 because BG1 is invalid, + * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran + * ks, implement address mirroring for MRS commands to during initializatio + * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp + * lements address mirroring) - 0 - Do not implement address mirroring + * PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0 + + * Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM + * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 + * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of + * software driven MR commands (via MRCTRL0/MRCTRL1), where software is re + * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se + * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma + * nds to even and odd ranks seperately - 0 - Do not stagger accesses + * PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0 + + * DIMM Control Register + * (OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U) + */ + PSU_Mask_Write(DDRC_DIMMCTL_OFFSET, 0x0000003FU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : RANKCTL @ 0XFD0700F4 + + * Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive writes to differ + * ent ranks. This is used to switch the delays in the PHY to match the ran + * k requirements. This value should consider both PHY requirement and ODT + * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v + * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by + * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas + * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc + * reased by 1. - ODT requirement: The value programmed in this register ta + * kes care of the ODT switch off timing requirement when switching ranks d + * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 + * For configurations with MEMC_FREQ_RATIO=1, program this to the larger o + * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_ + * RATIO=2, program this to the larger value divided by two and round it up + * to the next integer. + * PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6 + + * Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive reads to differe + * nt ranks. This is used to switch the delays in the PHY to match the rank + * requirements. This value should consider both PHY requirement and ODT r + * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va + * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), + * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only + * ), should be increased by 1. - ODT requirement: The value programmed in + * this register takes care of the ODT switch off timing requirement when s + * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, + * program this to the larger of PHY requirement or ODT requirement. For co + * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di + * vided by two and round it up to the next integer. + * PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6 + + * Only present for multi-rank configurations. Background: Reads to the sam + * e rank can be performed back-to-back. Reads to different ranks require a + * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is + * to avoid possible data bus contention as well as to give PHY enough tim + * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus + * access on a cycle-by-cycle basis; therefore after a read is scheduled, + * there are few clock cycles (determined by the value on RANKCTL.diff_rank + * _rd_gap register) in which only reads from the same rank are eligible to + * be scheduled. This prevents reads from other ranks from having fair acc + * ess to the data bus. This parameter represents the maximum number of rea + * ds that can be scheduled consecutively to the same rank. After this numb + * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by + * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig + * her numbers increase bandwidth utilization, lower numbers increase fairn + * ess. This feature can be DISABLED by setting this register to 0. When se + * t to 0, the Controller will stay on the same rank as long as commands ar + * e available for it. Minimum programmable value is 0 (feature disabled) a + * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY. + * PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf + + * Rank Control Register + * (OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU) + */ + PSU_Mask_Write(DDRC_RANKCTL_OFFSET, 0x00000FFFU, 0x0000066FU); +/*##################################################################### */ + + /* + * Register : DRAMTMG0 @ 0XFD070100 + + * Minimum time between write and precharge to same bank. Unit: Clocks Spec + * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks + * @400MHz and less for lower frequencies where: - WL = write latency - BL + * = burst length. This must match the value programmed in the BL bit of t + * he mode register to the SDRAM. BST (burst terminate) is not supported at + * present. - tWR = Write recovery time. This comes directly from the SDRA + * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p + * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the + * above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT + * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u + * p to the next integer value. + * PSU_DDRC_DRAMTMG0_WR2PRE 0x11 + + * tFAW Valid only when 8 or more banks(or banks x bank groups) are present + * . In 8-bank design, at most 4 banks must be activated in a rolling windo + * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se + * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + * Unit: Clocks + * PSU_DDRC_DRAMTMG0_T_FAW 0x10 + + * tRAS(max): Maximum time between activate and precharge to same bank. Thi + * s is the maximum time that a page can be kept open Minimum value of this + * register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO + * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of + * 1024 clocks. + * PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24 + + * tRAS(min): Minimum time between activate and precharge to the same bank. + * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA + * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T + * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th + * e next integer value. Unit: Clocks + * PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12 + + * SDRAM Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x11102412U) + */ + PSU_Mask_Write(DDRC_DRAMTMG0_OFFSET, 0x7F3F7F3FU, 0x11102412U); +/*##################################################################### */ + + /* + * Register : DRAMTMG1 @ 0XFD070104 + + * tXP: Minimum time after power-down exit to any operation. For DDR3, this + * should be programmed to tXPDLL if slow powerdown exit is selected in MR + * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it + * up to the next integer value. Units: Clocks + * PSU_DDRC_DRAMTMG1_T_XP 0x4 + + * tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL + * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi + * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 + * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t + * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) + * - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_ + * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi + * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo + * ve value by 2 and round it up to the next integer value. Unit: Clocks. + * PSU_DDRC_DRAMTMG1_RD2PRE 0x4 + + * tRC: Minimum time between activates to same bank. For configurations wit + * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege + * r value. Unit: Clocks. + * PSU_DDRC_DRAMTMG1_T_RC 0x1a + + * SDRAM Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x0004041AU) + */ + PSU_Mask_Write(DDRC_DRAMTMG1_OFFSET, 0x001F1F7FU, 0x0004041AU); +/*##################################################################### */ + + /* + * Register : DRAMTMG2 @ 0XFD070108 + + * Set to WL Time from write command to write data on SDRAM interface. This + * must be set to WL. For mDDR, it should normally be set to 1. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use a valu + * e of WL + 1 to compensate for the extra cycle of latency through the RDI + * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate + * d using the above equation by 2, and round it up to next integer. This r + * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING + * is set), as the DFI read and write latencies defined in DFITMG0 and DFI + * TMG1 are sufficient for those protocols Unit: clocks + * PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7 + + * Set to RL Time from read command to read data on SDRAM interface. This m + * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma + * t be necessary to use a value of RL + 1 to compensate for the extra cycl + * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2 + * , divide the value calculated using the above equation by 2, and round i + * t up to next integer. This register field is not required for DDR2 and D + * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie + * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit + * : clocks + * PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8 + + * DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L + * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di + * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL + * LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL + * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write + * command. Include time for bus turnaround and all per-bank, per-rank, an + * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b + * urst length. This must match the value programmed in the BL bit of the m + * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL + * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = + * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d + * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should + * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal + * culated using the above equation by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG2_RD2WR 0x6 + + * DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu + * m time from write command to read command for same bank group. In others + * , minimum time from write command to read command. Includes time for bus + * turnaround, recovery times, and all per-bank, per-rank, and global cons + * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la + * tency - BL = burst length. This must match the value programmed in the B + * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea + * d command delay for same bank group. This comes directly from the SDRAM + * specification. - tWTR = internal write to read command delay. This comes + * directly from the SDRAM specification. Add one extra cycle for LPDDR2/L + * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid + * e the value calculated using the above equation by 2, and round it up to + * next integer. + * PSU_DDRC_DRAMTMG2_WR2RD 0xd + + * SDRAM Timing Register 2 + * (OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060DU) + */ + PSU_Mask_Write(DDRC_DRAMTMG2_OFFSET, 0x3F3F3F3FU, 0x0708060DU); +/*##################################################################### */ + + /* + * Register : DRAMTMG3 @ 0XFD07010C + + * Time to wait after a mode register write or read (MRW or MRR). Present o + * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty + * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD + * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist + * er is used for the time from a MRW/MRR to all other commands. For LDPDR3 + * , this register is used for the time from a MRW/MRR to a MRW/MRR. + * PSU_DDRC_DRAMTMG3_T_MRW 0x5 + + * tMRD: Cycles to wait after a mode register write or read. Depending on t + * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com + * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim + * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2, + * program this to (tMRD/2) and round it up to the next integer value. If + * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. + * PSU_DDRC_DRAMTMG3_T_MRD 0x4 + + * tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com + * mand and following non-load mode command. If C/A parity for DDR4 is used + * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or + * tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if + * using RDIMM, depending on the PHY, it may be necessary to use a value of + * tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a + * pplied to mode register writes by the RDIMM chip. + * PSU_DDRC_DRAMTMG3_T_MOD 0xc + + * SDRAM Timing Register 3 + * (OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU) + */ + PSU_Mask_Write(DDRC_DRAMTMG3_OFFSET, 0x3FF3F3FFU, 0x0050400CU); +/*##################################################################### */ + + /* + * Register : DRAMTMG4 @ 0XFD070110 + + * tRCD - tAL: Minimum time from activate to read or write command to same + * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD + * - tAL)/2) and round it up to the next integer value. Minimum value allow + * ed for this register is 1, which implies minimum (tRCD - tAL) value to b + * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. + * PSU_DDRC_DRAMTMG4_T_RCD 0x8 + + * DDR4: tCCD_L: This is the minimum time between two reads or two writes f + * or same bank group. Others: tCCD: This is the minimum time between two r + * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t + * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U + * nit: clocks. + * PSU_DDRC_DRAMTMG4_T_CCD 0x3 + + * DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f + * or same bank group. Others: tRRD: Minimum time between activates from ba + * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni + * t: Clocks. + * PSU_DDRC_DRAMTMG4_T_RRD 0x4 + + * tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ + * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM + * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t + * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho + * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. + * PSU_DDRC_DRAMTMG4_T_RP 0x9 + + * SDRAM Timing Register 4 + * (OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030409U) + */ + PSU_Mask_Write(DDRC_DRAMTMG4_OFFSET, 0x1F0F0F1FU, 0x08030409U); +/*##################################################################### */ + + /* + * Register : DRAMTMG5 @ 0XFD070114 + + * This is the time before Self Refresh Exit that CK is maintained as a val + * id clock before issuing SRX. Specifies the clock stable time before SRX. + * Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK + * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKSRX 0x6 + + * This is the time after Self Refresh Down Entry that CK is maintained as + * a valid clock. Specifies the clock disable delay after SRE. Recommended + * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 + * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations + * with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw + * o and round it up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKSRE 0x6 + + * Minimum CKE low width for Self refresh or Self refresh power down entry + * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF + * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: + * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ + * _RATIO=2, program this to recommended value divided by two and round it + * up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKESR 0x4 + + * Minimum number of cycles of CKE HIGH/LOW during power-down and self refr + * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP + * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/ + * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration + * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and + * round it up to the next integer value. Unit: Clocks. + * PSU_DDRC_DRAMTMG5_T_CKE 0x3 + + * SDRAM Timing Register 5 + * (OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U) + */ + PSU_Mask_Write(DDRC_DRAMTMG5_OFFSET, 0x0F0F3F1FU, 0x06060403U); +/*##################################################################### */ + + /* + * Register : DRAMTMG6 @ 0XFD070118 + + * This is the time after Deep Power Down Entry that CK is maintained as a + * valid clock. Specifies the clock disable delay after DPDE. Recommended s + * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. This is only present for designs supporting mDDR + * or LPDDR2/LPDDR3 devices. + * PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1 + + * This is the time before Deep Power Down Exit that CK is maintained as a + * valid clock before issuing DPDX. Specifies the clock stable time before + * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config + * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid + * ed by two and round it up to next integer. This is only present for desi + * gns supporting mDDR or LPDDR2 devices. + * PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1 + + * This is the time before Clock Stop Exit that CK is maintained as a valid + * clock before issuing Clock Stop Exit. Specifies the clock stable time b + * efore next command after Clock Stop Exit. Recommended settings: - mDDR: + * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio + * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by + * two and round it up to next integer. This is only present for designs su + * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG6_T_CKCSX 0x4 + + * SDRAM Timing Register 6 + * (OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U) + */ + PSU_Mask_Write(DDRC_DRAMTMG6_OFFSET, 0x0F0F000FU, 0x01010004U); +/*##################################################################### */ + + /* + * Register : DRAMTMG7 @ 0XFD07011C + + * This is the time after Power Down Entry that CK is maintained as a valid + * clock. Specifies the clock disable delay after PDE. Recommended setting + * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration + * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t + * wo and round it up to next integer. This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG7_T_CKPDE 0x6 + + * This is the time before Power Down Exit that CK is maintained as a valid + * clock before issuing PDX. Specifies the clock stable time before PDX. R + * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c + * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value + * divided by two and round it up to next integer. This is only present for + * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG7_T_CKPDX 0x6 + + * SDRAM Timing Register 7 + * (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U) + */ + PSU_Mask_Write(DDRC_DRAMTMG7_OFFSET, 0x00000F0FU, 0x00000606U); +/*##################################################################### */ + + /* + * Register : DRAMTMG8 @ 0XFD070120 + + * tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and + * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this + * to the above value divided by 2 and round up to next integer value. Unit + * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com + * mands. Note: Ensure this is less than or equal to t_xs_x32. + * PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x4 + + * tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S + * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th + * is to the above value divided by 2 and round up to next integer value. U + * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to + * t_xs_x32. + * PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x4 + + * tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config + * urations with MEMC_FREQ_RATIO=2, program this to the above value divided + * by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + * PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd + + * tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi + * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide + * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + * PSU_DDRC_DRAMTMG8_T_XS_X32 0x7 + + * SDRAM Timing Register 8 + * (OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x04040D07U) + */ + PSU_Mask_Write(DDRC_DRAMTMG8_OFFSET, 0x7F7F7F7FU, 0x04040D07U); +/*##################################################################### */ + + /* + * Register : DRAMTMG9 @ 0XFD070124 + + * DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o + * nly with MEMC_FREQ_RATIO=2 + * PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0 + + * tCCD_S: This is the minimum time between two reads or two writes for dif + * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m + * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2 + * , program this to (tCCD_S/2) and round it up to the next integer value. + * Present only in designs configured to support DDR4. Unit: clocks. + * PSU_DDRC_DRAMTMG9_T_CCD_S 0x2 + + * tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif + * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th + * is to (tRRD_S/2) and round it up to the next integer value. Present only + * in designs configured to support DDR4. Unit: Clocks. + * PSU_DDRC_DRAMTMG9_T_RRD_S 0x3 + + * CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command + * for different bank group. Includes time for bus turnaround, recovery ti + * mes, and all per-bank, per-rank, and global constraints. Present only in + * designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr + * ite latency - PL = Parity latency - BL = burst length. This must match t + * he value programmed in the BL bit of the mode register to the SDRAM - tW + * TR_S = internal write to read command delay for different bank group. Th + * is comes directly from the SDRAM specification. For configurations with + * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation + * by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG9_WR2RD_S 0xb + + * SDRAM Timing Register 9 + * (OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002030BU) + */ + PSU_Mask_Write(DDRC_DRAMTMG9_OFFSET, 0x40070F3FU, 0x0002030BU); +/*##################################################################### */ + + /* + * Register : DRAMTMG11 @ 0XFD07012C + + * tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL + * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2 + * ) and round it up to the next integer value. Present only in designs con + * figured to support DDR4. Unit: Multiples of 32 clocks. + * PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x12 + + * tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For + * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2 + * )+1. Present only in designs configured to support DDR4. Unit: clocks. + * PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7 + + * tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_ + * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int + * eger value. Present only in designs configured to support DDR4. Unit: Cl + * ocks. + * PSU_DDRC_DRAMTMG11_T_MPX_S 0x1 + + * tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i + * n designs configured to support DDR4. Unit: Clocks. For configurations w + * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat + * ion by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG11_T_CKMPE 0xe + + * SDRAM Timing Register 11 + * (OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x1207010EU) + */ + PSU_Mask_Write(DDRC_DRAMTMG11_OFFSET, 0x7F1F031FU, 0x1207010EU); +/*##################################################################### */ + + /* + * Register : DRAMTMG12 @ 0XFD070130 + + * tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg + * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr + * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu + * e. + * PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2 + + * tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat + * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u + * p to next integer value. + * PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6 + + * tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2) + * and round it up to next integer value. + * PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8 + + * SDRAM Timing Register 12 + * (OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U) + */ + PSU_Mask_Write(DDRC_DRAMTMG12_OFFSET, 0x00030F1FU, 0x00020608U); +/*##################################################################### */ + + /* + * Register : ZQCTL0 @ 0XFD070180 + + * - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg + * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration + * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati + * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre + * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1 + + * - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres + * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 + * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio + * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i + * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present + * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0 + + * - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC + * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co + * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share + * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR + * 3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0 + + * - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. + * Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com + * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4 + * mode. This is only present for designs supporting DDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0 + + * tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe + * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St + * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO + * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int + * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th + * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t + * o the next integer value. Unit: Clock cycles. This is only present for d + * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100 + + * tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of + * NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command + * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t + * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy + * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP + * DDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40 + + * ZQ Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U) + */ + PSU_Mask_Write(DDRC_ZQCTL0_OFFSET, 0xF7FF03FFU, 0x81000040U); +/*##################################################################### */ + + /* + * Register : ZQCTL1 @ 0XFD070184 + + * tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati + * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_ + * RATIO=2, program this to tZQReset/2 and round it up to the next integer + * value. Unit: Clock cycles. This is only present for designs supporting L + * PDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20 + + * Average interval to wait between automatically issuing ZQCS (ZQ calibrat + * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR + * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles + * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 + * /LPDDR4 devices. + * PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x196e5 + + * ZQ Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x020196E5U) + */ + PSU_Mask_Write(DDRC_ZQCTL1_OFFSET, 0x3FFFFFFFU, 0x020196E5U); +/*##################################################################### */ + + /* + * Register : DFITMG0 @ 0XFD070190 + + * Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. + * PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4 + + * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. + * PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1 + + * Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks + * PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb + + * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. + * PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1 + + * Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks + * PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2 + + * Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. + * PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb + + * DFI Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU) + */ + PSU_Mask_Write(DDRC_DFITMG0_OFFSET, 0x1FBFBF3FU, 0x048B820BU); +/*##################################################################### */ + + /* + * Register : DFITMG1 @ 0XFD070194 + + * Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated command is driven. This field is used + * for CAL mode, should be set to '0' or the value which matches the CAL mo + * de register setting in the DRAM. If the PHY can add the latency for CAL + * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 + * PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0 + + * Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated dfi_parity_in signal is driven. + * PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0 + + * Specifies the number of DFI clocks between when the dfi_wrdata_en signal + * is asserted and when the corresponding write data transfer is completed + * on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d + * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set + * to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI + * 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va + * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_ + * RATIO=2, divide PHY's value by 2 and round up to next integer. If using + * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks + * PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3 + + * Specifies the number of DFI clock cycles from the assertion of the dfi_d + * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev + * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock + * and the memory clock are not phase aligned, this timing parameter should + * be rounded up to the next integer value. + * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3 + + * Specifies the number of DFI clock cycles from the de-assertion of the df + * i_dram_clk_disable signal on the DFI until the first valid rising edge o + * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the + * DFI clock and the memory clock are not phase aligned, this timing param + * eter should be rounded up to the next integer value. + * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4 + + * DFI Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U) + */ + PSU_Mask_Write(DDRC_DFITMG1_OFFSET, 0xF31F0F0FU, 0x00030304U); +/*##################################################################### */ + + /* + * Register : DFILPCFG0 @ 0XFD070198 + + * Setting for DFI's tlp_resp time. Same value is used for both Power Down, + * Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s + * pecification onwards, recommends using a fixed value of 7 always. + * PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7 + + * Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente + * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 + * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5 + * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - + * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553 + * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T + * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices + * . + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0 + + * Enables DFI Low Power interface handshaking during Deep Power Down Entry + * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3 devices. + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0 + + * Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered + * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc + * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 + * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 + * - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c + * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0 + + * Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex + * it. - 0 - Disabled - 1 - Enabled + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1 + + * Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle + * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy + * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - + * 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc + * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0 + + * Enables DFI Low Power interface handshaking during Power Down Entry/Exit + * . - 0 - Disabled - 1 - Enabled + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1 + + * DFI Low Power Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U) + */ + PSU_Mask_Write(DDRC_DFILPCFG0_OFFSET, 0x0FF1F1F1U, 0x07000101U); +/*##################################################################### */ + + /* + * Register : DFILPCFG1 @ 0XFD07019C + + * Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is + * entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 + * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x + * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl + * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - + * 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi + * ted This is only present for designs supporting DDR4 devices. + * PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2 + + * Enables DFI Low Power interface handshaking during Maximum Power Saving + * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d + * esigns supporting DDR4 devices. + * PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1 + + * DFI Low Power Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U) + */ + PSU_Mask_Write(DDRC_DFILPCFG1_OFFSET, 0x000000F1U, 0x00000021U); +/*##################################################################### */ + + /* + * Register : DFIUPD0 @ 0XFD0701A0 + + * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc + * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. + * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD 0x0 + + * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * following a self-refresh exit. The core must issue the dfi_ctrlupd_req + * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct + * rlupd_req after exiting self-refresh. + * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX 0x0 + + * Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si + * gnal can assert. Lowest value to assign to this variable is 0x40. Unit: + * Clocks + * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MAX 0x40 + + * Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si + * gnal must be asserted. The uMCTL2 expects the PHY to respond within this + * time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup + * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this + * variable is 0x3. Unit: Clocks + * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MIN 0x3 + + * DFI Update Register 0 + * (OFFSET, MASK, VALUE) (0XFD0701A0, 0xC3FF03FFU ,0x00400003U) + */ + PSU_Mask_Write(DDRC_DFIUPD0_OFFSET, 0xC3FF03FFU, 0x00400003U); +/*##################################################################### */ + + /* + * Register : DFIUPD1 @ 0XFD0701A4 + + * This is the minimum amount of time between uMCTL2 initiated DFI update r + * equests (which is executed whenever the uMCTL2 is idle). Set this number + * higher to reduce the frequency of update requests, which can have a sma + * ll impact on the latency of the first read request when the uMCTL2 is id + * le. Unit: 1024 clocks + * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0xc8 + + * This is the maximum amount of time between uMCTL2 initiated DFI update r + * equests. This timer resets with each update request; when the timer expi + * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd + * _ackx is received. PHY can use this idle time to recalibrate the delay l + * ines to the DLLs. The DFI controller update is also used to reset PHY FI + * FO pointers in case of data capture errors. Updates are required to main + * tain calibration over PVT, but frequent updates may impact performance. + * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must + * be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl + * ocks + * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xff + + * DFI Update Register 1 + * (OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x00C800FFU) + */ + PSU_Mask_Write(DDRC_DFIUPD1_OFFSET, 0x00FF00FFU, 0x00C800FFU); +/*##################################################################### */ + + /* + * Register : DFIMISC @ 0XFD0701B0 + + * Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal + * s are active low - 1: Signals are active high + * PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0 + + * DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. + * - 1 - PHY implements DBI functionality. Present only in designs configu + * red to support DDR4 and LPDDR4. + * PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0 + + * PHY initialization complete enable signal. When asserted the dfi_init_co + * mplete signal can be used to trigger SDRAM initialisation + * PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0 + + * DFI Miscellaneous Control Register + * (OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DFIMISC_OFFSET, 0x00000007U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DFITMG2 @ 0XFD0701B4 + + * >Number of clocks between when a read command is sent on the DFI control + * interface and when the associated dfi_rddata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe + * cification for correct value. + * PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9 + + * Number of clocks between when a write command is sent on the DFI control + * interface and when the associated dfi_wrdata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe + * cification for correct value. + * PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x9 + + * DFI Timing Register 2 + * (OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000909U) + */ + PSU_Mask_Write(DDRC_DFITMG2_OFFSET, 0x00003F3FU, 0x00000909U); +/*##################################################################### */ + + /* + * Register : DBICTL @ 0XFD0701C0 + + * Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D + * BI is enabled. This signal must be set the same value as DRAM's mode reg + * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b + * e set to 0. - LPDDR4: MR3[6] + * PSU_DDRC_DBICTL_RD_DBI_EN 0x0 + + * Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ + * e DBI is enabled. This signal must be set the same value as DRAM's mode + * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus + * t be set to 0. - LPDDR4: MR3[7] + * PSU_DDRC_DBICTL_WR_DBI_EN 0x0 + + * DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi + * s signal must be set the same logical value as DRAM's mode register. - D + * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th + * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13 + * [5] which is opposite polarity from this signal + * PSU_DDRC_DBICTL_DM_EN 0x1 + + * DM/DBI Control Register + * (OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_DBICTL_OFFSET, 0x00000007U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : ADDRMAP0 @ 0XFD070200 + + * Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t + * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, r + * ank address bit 0 is set to 0. + * PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f + + * Address Map Register 0 + * (OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP0_OFFSET, 0x0000001FU, 0x0000001FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP1 @ 0XFD070204 + + * Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t + * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, ba + * nk address bit 2 is set to 0. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f + + * Selects the HIF address bits used as bank address bit 1. Valid Range: 0 + * to 30 Internal Base: 3 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0x9 + + * Selects the HIF address bits used as bank address bit 0. Valid Range: 0 + * to 30 Internal Base: 2 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0x9 + + * Address Map Register 1 + * (OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0909U) + */ + PSU_Mask_Write(DDRC_ADDRMAP1_OFFSET, 0x001F1F1FU, 0x001F0909U); +/*##################################################################### */ + + /* + * Register : ADDRMAP2 @ 0XFD070208 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base + * : 5 The selected HIF address bit is determined by adding the internal ba + * se to the value of this field. If set to 15, this column address bit is + * set to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x1 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: + * 4 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x1 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1 + * 6, it is required to program this to 0, hence register does not exist in + * this case. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x1 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 + * or 16, it is required to program this to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0 + + * Address Map Register 2 + * (OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x01010100U) + */ + PSU_Mask_Write(DDRC_ADDRMAP2_OFFSET, 0x0F0F0F0FU, 0x01010100U); +/*##################################################################### */ + + /* + * Register : ADDRMAP3 @ 0XFD07020C + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: + * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/ + * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + * HIF address bit is determined by adding the internal base to the value o + * f this field. If set to 15, this column address bit is set to 0. Note: P + * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo + * r indicating auto-precharge, and hence no source address bit can be mapp + * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit + * for auto-precharge in the CA bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x1 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 + * to 7, and 15 Internal Base: 8 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi + * cation, column address bit 10 is reserved for indicating auto-precharge, + * and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA + * bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x1 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: + * 7 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x1 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: + * 6 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x1 + + * Address Map Register 3 + * (OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x01010101U) + */ + PSU_Mask_Write(DDRC_ADDRMAP3_OFFSET, 0x0F0F0F0FU, 0x01010101U); +/*##################################################################### */ + + /* + * Register : ADDRMAP4 @ 0XFD070210 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m + * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un + * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, + * and 15 Internal Base: 11 The selected HIF address bit is determined by + * adding the internal base to the value of this field. If set to 15, this + * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio + * n, column address bit 10 is reserved for indicating auto-precharge, and + * hence no source address bit can be mapped to column address bit 10. In L + * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus + * and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the + * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) + * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied + * to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + * address bit is determined by adding the internal base to the value of t + * his field. If set to 15, this column address bit is set to 0. Note: Per + * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i + * ndicating auto-precharge, and hence no source address bit can be mapped + * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + * auto-precharge in the CA bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf + + * Address Map Register 4 + * (OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP4_OFFSET, 0x00000F0FU, 0x00000F0FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP5 @ 0XFD070214 + + * Selects the HIF address bit used as row address bit 11. Valid Range: 0 t + * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 11 is set to 0. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x7 + + * Selects the HIF address bits used as row address bits 2 to 10. Valid Ran + * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row + * address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro + * w address bit 10) The selected HIF address bit for each of the row addre + * ss bits is determined by adding the internal base to the value of this f + * ield. When value 15 is used the values of row address bits 2 to 10 are d + * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf + + * Selects the HIF address bits used as row address bit 1. Valid Range: 0 t + * o 11 Internal Base: 7 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x7 + + * Selects the HIF address bits used as row address bit 0. Valid Range: 0 t + * o 11 Internal Base: 6 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x7 + + * Address Map Register 5 + * (OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x070F0707U) + */ + PSU_Mask_Write(DDRC_ADDRMAP5_OFFSET, 0x0F0F0F0FU, 0x070F0707U); +/*##################################################################### */ + + /* + * Register : ADDRMAP6 @ 0XFD070218 + + * Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 + * - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]= + * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. + * All addresses are valid Present only in designs configured to support L + * PDDR3. + * PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0 + + * Selects the HIF address bit used as row address bit 15. Valid Range: 0 t + * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 15 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0x7 + + * Selects the HIF address bit used as row address bit 14. Valid Range: 0 t + * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 14 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x7 + + * Selects the HIF address bit used as row address bit 13. Valid Range: 0 t + * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 13 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x7 + + * Selects the HIF address bit used as row address bit 12. Valid Range: 0 t + * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 12 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x7 + + * Address Map Register 6 + * (OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x07070707U) + */ + PSU_Mask_Write(DDRC_ADDRMAP6_OFFSET, 0x8F0F0F0FU, 0x07070707U); +/*##################################################################### */ + + /* + * Register : ADDRMAP7 @ 0XFD07021C + + * Selects the HIF address bit used as row address bit 17. Valid Range: 0 t + * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 17 is set to 0. + * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf + + * Selects the HIF address bit used as row address bit 16. Valid Range: 0 t + * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 16 is set to 0. + * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf + + * Address Map Register 7 + * (OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP7_OFFSET, 0x00000F0FU, 0x00000F0FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP8 @ 0XFD070220 + + * Selects the HIF address bits used as bank group address bit 1. Valid Ran + * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea + * ch of the bank group address bits is determined by adding the internal b + * ase to the value of this field. If set to 31, bank group address bit 1 i + * s set to 0. + * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x1f + + * Selects the HIF address bits used as bank group address bit 0. Valid Ran + * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th + * e bank group address bits is determined by adding the internal base to t + * he value of this field. + * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x1 + + * Address Map Register 8 + * (OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00001F01U) + */ + PSU_Mask_Write(DDRC_ADDRMAP8_OFFSET, 0x00001F1FU, 0x00001F01U); +/*##################################################################### */ + + /* + * Register : ADDRMAP9 @ 0XFD070224 + + * Selects the HIF address bits used as row address bit 5. Valid Range: 0 t + * o 11 Internal Base: 11 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x7 + + * Selects the HIF address bits used as row address bit 4. Valid Range: 0 t + * o 11 Internal Base: 10 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x7 + + * Selects the HIF address bits used as row address bit 3. Valid Range: 0 t + * o 11 Internal Base: 9 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x7 + + * Selects the HIF address bits used as row address bit 2. Valid Range: 0 t + * o 11 Internal Base: 8 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x7 + + * Address Map Register 9 + * (OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x07070707U) + */ + PSU_Mask_Write(DDRC_ADDRMAP9_OFFSET, 0x0F0F0F0FU, 0x07070707U); +/*##################################################################### */ + + /* + * Register : ADDRMAP10 @ 0XFD070228 + + * Selects the HIF address bits used as row address bit 9. Valid Range: 0 t + * o 11 Internal Base: 15 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x7 + + * Selects the HIF address bits used as row address bit 8. Valid Range: 0 t + * o 11 Internal Base: 14 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x7 + + * Selects the HIF address bits used as row address bit 7. Valid Range: 0 t + * o 11 Internal Base: 13 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x7 + + * Selects the HIF address bits used as row address bit 6. Valid Range: 0 t + * o 11 Internal Base: 12 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x7 + + * Address Map Register 10 + * (OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x07070707U) + */ + PSU_Mask_Write(DDRC_ADDRMAP10_OFFSET, 0x0F0F0F0FU, 0x07070707U); +/*##################################################################### */ + + /* + * Register : ADDRMAP11 @ 0XFD07022C + + * Selects the HIF address bits used as row address bit 10. Valid Range: 0 + * to 11 Internal Base: 16 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of + * this field. This register field is used only when ADDRMAP5.addrmap_row_b + * 2_10 is set to value 15. + * PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x7 + + * Address Map Register 11 + * (OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000007U) + */ + PSU_Mask_Write(DDRC_ADDRMAP11_OFFSET, 0x0000000FU, 0x00000007U); +/*##################################################################### */ + + /* + * Register : ODTCFG @ 0XFD070240 + + * Cycles to hold ODT for a write command. The minimum supported value is 2 + * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800 + * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D + * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR + * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 ( + * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6 + + * The delay, in clock cycles, from issuing a write command to setting ODT + * values associated with that command. ODT setting must remain constant fo + * r the entire time that DQS is driven by the uMCTL2. Recommended values: + * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + + * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo + * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust + * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) + * PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0 + + * Cycles to hold ODT for a read command. The minimum supported value is 2. + * Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - + * BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 + * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p + * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + + * RU(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6 + + * The delay, in clock cycles, from issuing a read command to setting ODT v + * alues associated with that command. ODT setting must remain constant for + * the entire time that DQS is driven by the uMCTL2. Recommended values: D + * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL + * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C + * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat + * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK + * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre + * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su + * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R + * U(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0 + + * ODT Configuration Register + * (OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U) + */ + PSU_Mask_Write(DDRC_ODTCFG_OFFSET, 0x0F1F0F7CU, 0x06000600U); +/*##################################################################### */ + + /* + * Register : ODTMAP @ 0XFD070244 + + * Indicates which remote ODTs must be turned on during a read from rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. Present only in configurations that have 2 or more + * ranks + * PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a write to rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. Present only in configurations that have 2 or more r + * anks + * PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a read from rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. + * PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a write to rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. + * PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1 + + * ODT/Rank Map Register + * (OFFSET, MASK, VALUE) (0XFD070244, 0x00003333U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_ODTMAP_OFFSET, 0x00003333U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : SCHED @ 0XFD070250 + + * When the preferred transaction store is empty for these many clock cycle + * s, switch to the alternate transaction store if it is non-empty. The rea + * d transaction store (both high and low priority) is the default preferre + * d transaction store and the write transaction store is the alternative s + * tore. When prefer write over read is set this is reversed. 0x0 is a lega + * l value for this register. When set to 0x0, the transaction store switch + * ing will happen immediately when the switching conditions become true. F + * OR PERFORMANCE ONLY + * PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1 + + * UNUSED + * PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0 + + * Number of entries in the low priority transaction store is this value + + * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent + * ries available for the high priority transaction store. Setting this to + * maximum value allocates all entries to low priority transaction store. S + * etting this to 0 allocates 1 entry to low priority transaction store and + * the rest to high priority transaction store. Note: In ECC configuration + * s, the numbers of write and low priority read credits issued is one less + * than in the non-ECC case. One entry each is reserved in the write and l + * ow-priority read CAMs for storing the RMW requests arising out of single + * bit error correction RMW operation. + * PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20 + + * If true, bank is kept open only while there are page hit transactions av + * ailable in the CAM to that bank. The last read or write command in the C + * AM with a bank and page hit will be executed with auto-precharge if SCHE + * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos + * e_timer is set to 0, explicit precharge (and not auto-precharge) may be + * issued in some cases where there is a mode switch between Write and Read + * or between LPR and HPR. The Read and Write commands that are executed a + * s part of the ECC scrub requests are also executed without auto-precharg + * e. If false, the bank remains open until there is a need to close it (to + * open a different page, or for page timeout or refresh timeout) - also k + * nown as open page policy. The open page policy can be overridden by sett + * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + * The pageclose feature provids a midway between Open and Close page polic + * ies. FOR PERFORMANCE ONLY. + * PSU_DDRC_SCHED_PAGECLOSE 0x0 + + * If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. + * PSU_DDRC_SCHED_PREFER_WRITE 0x0 + + * Active low signal. When asserted ('0'), all incoming transactions are fo + * rced to low priority. This implies that all High Priority Read (HPR) and + * Variable Priority Read commands (VPR) will be treated as Low Priority R + * ead (LPR) commands. On the write side, all Variable Priority Write (VPW) + * commands will be treated as Normal Priority Write (NPW) commands. Forci + * ng the incoming transactions to low priority implicitly turns off Bypass + * path for read commands. FOR PERFORMANCE ONLY. + * PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1 + + * Scheduler Control Register + * (OFFSET, MASK, VALUE) (0XFD070250, 0x7FFF3F07U ,0x01002001U) + */ + PSU_Mask_Write(DDRC_SCHED_OFFSET, 0x7FFF3F07U, 0x01002001U); +/*##################################################################### */ + + /* + * Register : PERFLPR1 @ 0XFD070264 + + * Number of transactions that are serviced once the LPR queue goes critica + * l is the smaller of: - (a) This number - (b) Number of transactions avai + * lable. Unit: Transaction. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8 + + * Number of clocks that the LPR queue can be starved before it goes critic + * al. The minimum valid functional value for this register is 0x1. Program + * ming it to 0x0 will disable the starvation functionality; during normal + * operation, this function should not be disabled as it will cause excessi + * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40 + + * Low Priority Read CAM Register 1 + * (OFFSET, MASK, VALUE) (0XFD070264, 0xFF00FFFFU ,0x08000040U) + */ + PSU_Mask_Write(DDRC_PERFLPR1_OFFSET, 0xFF00FFFFU, 0x08000040U); +/*##################################################################### */ + + /* + * Register : PERFWR1 @ 0XFD07026C + + * Number of transactions that are serviced once the WR queue goes critical + * is the smaller of: - (a) This number - (b) Number of transactions avail + * able. Unit: Transaction. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8 + + * Number of clocks that the WR queue can be starved before it goes critica + * l. The minimum valid functional value for this register is 0x1. Programm + * ing it to 0x0 will disable the starvation functionality; during normal o + * peration, this function should not be disabled as it will cause excessiv + * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40 + + * Write CAM Register 1 + * (OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U) + */ + PSU_Mask_Write(DDRC_PERFWR1_OFFSET, 0xFF00FFFFU, 0x08000040U); +/*##################################################################### */ + + /* + * Register : DQMAP0 @ 0XFD070280 + + * DQ nibble map for DQ bits [12-15] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15 0x0 + + * DQ nibble map for DQ bits [8-11] Present only in designs configured to s + * upport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11 0x0 + + * DQ nibble map for DQ bits [4-7] Present only in designs configured to su + * pport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7 0x0 + + * DQ nibble map for DQ bits [0-3] Present only in designs configured to su + * pport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3 0x0 + + * DQ Map Register 0 + * (OFFSET, MASK, VALUE) (0XFD070280, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP0_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP1 @ 0XFD070284 + + * DQ nibble map for DQ bits [28-31] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31 0x0 + + * DQ nibble map for DQ bits [24-27] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27 0x0 + + * DQ nibble map for DQ bits [20-23] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23 0x0 + + * DQ nibble map for DQ bits [16-19] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19 0x0 + + * DQ Map Register 1 + * (OFFSET, MASK, VALUE) (0XFD070284, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP1_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP2 @ 0XFD070288 + + * DQ nibble map for DQ bits [44-47] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47 0x0 + + * DQ nibble map for DQ bits [40-43] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43 0x0 + + * DQ nibble map for DQ bits [36-39] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39 0x0 + + * DQ nibble map for DQ bits [32-35] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35 0x0 + + * DQ Map Register 2 + * (OFFSET, MASK, VALUE) (0XFD070288, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP3 @ 0XFD07028C + + * DQ nibble map for DQ bits [60-63] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63 0x0 + + * DQ nibble map for DQ bits [56-59] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59 0x0 + + * DQ nibble map for DQ bits [52-55] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55 0x0 + + * DQ nibble map for DQ bits [48-51] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51 0x0 + + * DQ Map Register 3 + * (OFFSET, MASK, VALUE) (0XFD07028C, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP3_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP4 @ 0XFD070290 + + * DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf + * igured to support DDR4. + * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7 0x0 + + * DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf + * igured to support DDR4. + * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3 0x0 + + * DQ Map Register 4 + * (OFFSET, MASK, VALUE) (0XFD070290, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP4_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP5 @ 0XFD070294 + + * All even ranks have the same DQ mapping controled by DQMAP0-4 register a + * s rank 0. This register provides DQ swap function for all odd ranks to s + * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b + * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba + * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs + * configured to support DDR4. + * PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1 + + * DQ Map Register 5 + * (OFFSET, MASK, VALUE) (0XFD070294, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_DQMAP5_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : DBG0 @ 0XFD070300 + + * When this is set to '0', auto-precharge is disabled for the flushed comm + * and in a collision case. Collision cases are write followed by read to s + * ame address, read followed by write to same address, or write followed b + * y write to same address with DBG0.dis_wc bit = 1 (where same address com + * parisons exclude the two address bits representing critical word). FOR D + * EBUG ONLY. + * PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0 + + * When 1, disable write combine. FOR DEBUG ONLY + * PSU_DDRC_DBG0_DIS_WC 0x0 + + * Debug Register 0 + * (OFFSET, MASK, VALUE) (0XFD070300, 0x00000011U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DBG0_OFFSET, 0x00000011U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DBGCMD @ 0XFD07030C + + * Setting this register bit to 1 allows refresh and ZQCS commands to be tr + * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD. + * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore + * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and + * ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor + * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no + * function, and are ignored by the uMCTL2 logic. This register is static, + * and may only be changed when the DDRC reset signal, core_ddrc_rstn, is + * asserted (0). + * PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct + * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit + * is automatically cleared. This operation must only be performed when DF + * IUPD0.dis_auto_ctrlupd=1. + * PSU_DDRC_DBGCMD_CTRLUPD 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS ( + * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi + * s request is stored in the uMCTL2, the bit is automatically cleared. Thi + * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom + * mended NOT to set this register bit if in Init operating mode. This regi + * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown + * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo + * de. + * PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be + * set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. + * PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be + * set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. + * PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0 + + * Command Debug Register + * (OFFSET, MASK, VALUE) (0XFD07030C, 0x80000033U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DBGCMD_OFFSET, 0x80000033U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SWCTL @ 0XFD070320 + + * Enable quasi-dynamic register programming outside reset. Program registe + * r to 0 to enable quasi-dynamic programming. Set back register to 1 once + * programming is done. + * PSU_DDRC_SWCTL_SW_DONE 0x0 + + * Software register programming control enable + * (OFFSET, MASK, VALUE) (0XFD070320, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SWCTL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCCFG @ 0XFD070400 + + * Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand + * s every AXI burst into multiple HIF commands, using the memory burst len + * gth as a unit. If set to 1, then XPI will use half of the memory burst l + * ength as a unit. This applies to both reads and writes. When MSTR.data_b + * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i + * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d + * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd + * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali + * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT + * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an + * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST + * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs + * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR + * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared + * -AC is enabled + * PSU_DDRC_PCCFG_BL_EXP_MODE 0x0 + + * Page match four limit. If set to 1, limits the number of consecutive sam + * e page DDRC transactions that can be granted by the Port Arbiter to four + * when Page Match feature is enabled. If set to 0, there is no limit impo + * sed on number of consecutive same page DDRC transactions. + * PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0 + + * If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l + * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw + * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_ + * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a + * t DDRC are driven to 1b'0. + * PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1 + + * Port Common Configuration Register + * (OFFSET, MASK, VALUE) (0XFD070400, 0x00000111U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCCFG_OFFSET, 0x00000111U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGR_0 @ 0XFD070404 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070404, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_0_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_0 @ 0XFD070408 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_0_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_0 @ 0XFD070490 + + * Enables port n. + * PSU_DDRC_PCTRL_0_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070490, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_0_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_0 @ 0XFD070494 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070494, 0x0033000FU ,0x0020000BU) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_0_OFFSET, 0x0033000FU, 0x0020000BU); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_0 @ 0XFD070498 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070498, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_0_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_1 @ 0XFD0704B4 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD0704B4, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_1_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_1 @ 0XFD0704B8 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_1_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_1 @ 0XFD070540 + + * Enables port n. + * PSU_DDRC_PCTRL_1_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070540, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_1_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_1 @ 0XFD070544 + + * This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0 + + * Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070544, 0x03330F0FU ,0x02000B03U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_1_OFFSET, 0x03330F0FU, 0x02000B03U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_1 @ 0XFD070548 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070548, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_1_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_2 @ 0XFD070564 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070564, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_2_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_2 @ 0XFD070568 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_2_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_2 @ 0XFD0705F0 + + * Enables port n. + * PSU_DDRC_PCTRL_2_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD0705F0, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_2_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_2 @ 0XFD0705F4 + + * This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0 + + * Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0705F4, 0x03330F0FU ,0x02000B03U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_2_OFFSET, 0x03330F0FU, 0x02000B03U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_2 @ 0XFD0705F8 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0705F8, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_2_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_3 @ 0XFD070614 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070614, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_3_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_3 @ 0XFD070618 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_3_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_3 @ 0XFD0706A0 + + * Enables port n. + * PSU_DDRC_PCTRL_3_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD0706A0, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_3_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_3 @ 0XFD0706A4 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0706A4, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_3_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_3 @ 0XFD0706A8 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0706A8, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_3_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_3 @ 0XFD0706AC + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0706AC, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_3_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_3 @ 0XFD0706B0 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0706B0, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_3_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGR_4 @ 0XFD0706C4 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_4_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_4 @ 0XFD0706C8 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_4_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_4 @ 0XFD070750 + + * Enables port n. + * PSU_DDRC_PCTRL_4_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070750, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_4_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_4 @ 0XFD070754 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070754, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_4_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_4 @ 0XFD070758 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070758, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_4_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_4 @ 0XFD07075C + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD07075C, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_4_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_4 @ 0XFD070760 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070760, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_4_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGR_5 @ 0XFD070774 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070774, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_5_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_5 @ 0XFD070778 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_5_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_5 @ 0XFD070800 + + * Enables port n. + * PSU_DDRC_PCTRL_5_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070800, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_5_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_5 @ 0XFD070804 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070804, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_5_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_5 @ 0XFD070808 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070808, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_5_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_5 @ 0XFD07080C + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD07080C, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_5_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_5 @ 0XFD070810 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070810, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_5_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : SARBASE0 @ 0XFD070F04 + + * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + * PSU_DDRC_SARBASE0_BASE_ADDR 0x0 + + * SAR Base Address Register n + * (OFFSET, MASK, VALUE) (0XFD070F04, 0x000001FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SARBASE0_OFFSET, 0x000001FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SARSIZE0 @ 0XFD070F08 + + * Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. + * PSU_DDRC_SARSIZE0_NBLOCKS 0x0 + + * SAR Size Register n + * (OFFSET, MASK, VALUE) (0XFD070F08, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SARSIZE0_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SARBASE1 @ 0XFD070F0C + + * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + * PSU_DDRC_SARBASE1_BASE_ADDR 0x10 + + * SAR Base Address Register n + * (OFFSET, MASK, VALUE) (0XFD070F0C, 0x000001FFU ,0x00000010U) + */ + PSU_Mask_Write(DDRC_SARBASE1_OFFSET, 0x000001FFU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : SARSIZE1 @ 0XFD070F10 + + * Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. + * PSU_DDRC_SARSIZE1_NBLOCKS 0xf + + * SAR Size Register n + * (OFFSET, MASK, VALUE) (0XFD070F10, 0x000000FFU ,0x0000000FU) + */ + PSU_Mask_Write(DDRC_SARSIZE1_OFFSET, 0x000000FFU, 0x0000000FU); +/*##################################################################### */ + + /* + * Register : DFITMG0_SHADOW @ 0XFD072190 + + * Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. + * PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7 + + * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. + * PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1 + + * Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks + * PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2 + + * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. + * PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1 + + * Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks + * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0 + + * Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. + * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2 + + * DFI Timing Shadow Register 0 + * (OFFSET, MASK, VALUE) (0XFD072190, 0x1FBFBF3FU ,0x07828002U) + */ + PSU_Mask_Write(DDRC_DFITMG0_SHADOW_OFFSET, 0x1FBFBF3FU, 0x07828002U); +/*##################################################################### */ + + /* + * DDR CONTROLLER RESET + */ + /* + * Register : RST_DDR_SS @ 0XFD1A0108 + + * DDR block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0 + + * APM block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_APM_RESET 0X0 + + * DDR sub system block level reset + * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x0000000CU ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x0000000CU, 0x00000000U); +/*##################################################################### */ + + /* + * DDR PHY + */ + /* + * Register : PGCR0 @ 0XFD080010 + + * Address Copy + * PSU_DDR_PHY_PGCR0_ADCP 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_30_27 0x0 + + * PHY FIFO Reset + * PSU_DDR_PHY_PGCR0_PHYFRST 0x1 + + * Oscillator Mode Address/Command Delay Line Select + * PSU_DDR_PHY_PGCR0_OSCACDL 0x3 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_23_19 0x0 + + * Digital Test Output Select + * PSU_DDR_PHY_PGCR0_DTOSEL 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_13 0x0 + + * Oscillator Mode Division + * PSU_DDR_PHY_PGCR0_OSCDIV 0xf + + * Oscillator Enable + * PSU_DDR_PHY_PGCR0_OSCEN 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_7_0 0x0 + + * PHY General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080010, 0xFFFFFFFFU ,0x07001E00U) + */ + PSU_Mask_Write(DDR_PHY_PGCR0_OFFSET, 0xFFFFFFFFU, 0x07001E00U); +/*##################################################################### */ + + /* + * Register : PGCR2 @ 0XFD080018 + + * Clear Training Status Registers + * PSU_DDR_PHY_PGCR2_CLRTSTAT 0x0 + + * Clear Impedance Calibration + * PSU_DDR_PHY_PGCR2_CLRZCAL 0x0 + + * Clear Parity Error + * PSU_DDR_PHY_PGCR2_CLRPERR 0x0 + + * Initialization Complete Pin Configuration + * PSU_DDR_PHY_PGCR2_ICPC 0x0 + + * Data Training PUB Mode Exit Timer + * PSU_DDR_PHY_PGCR2_DTPMXTMR 0xf + + * Initialization Bypass + * PSU_DDR_PHY_PGCR2_INITFSMBYP 0x0 + + * PLL FSM Bypass + * PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0 + + * Refresh Period + * PSU_DDR_PHY_PGCR2_TREFPRD 0x10010 + + * PHY General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10010U) + */ + PSU_Mask_Write(DDR_PHY_PGCR2_OFFSET, 0xFFFFFFFFU, 0x00F10010U); +/*##################################################################### */ + + /* + * Register : PGCR3 @ 0XFD08001C + + * CKN Enable + * PSU_DDR_PHY_PGCR3_CKNEN 0x55 + + * CK Enable + * PSU_DDR_PHY_PGCR3_CKEN 0xaa + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR3_RESERVED_15 0x0 + + * Enable Clock Gating for AC [0] ctl_rd_clk + * PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2 + + * Enable Clock Gating for AC [0] ddr_clk + * PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2 + + * Enable Clock Gating for AC [0] ctl_clk + * PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR3_RESERVED_8 0x0 + + * Controls DDL Bypass Modes + * PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2 + + * IO Loop-Back Select + * PSU_DDR_PHY_PGCR3_IOLB 0x0 + + * AC Receive FIFO Read Mode + * PSU_DDR_PHY_PGCR3_RDMODE 0x0 + + * Read FIFO Reset Disable + * PSU_DDR_PHY_PGCR3_DISRST 0x0 + + * Clock Level when Clock Gating + * PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0 + + * PHY General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U) + */ + PSU_Mask_Write(DDR_PHY_PGCR3_OFFSET, 0xFFFFFFFFU, 0x55AA5480U); +/*##################################################################### */ + + /* + * Register : PGCR5 @ 0XFD080024 + + * Frequency B Ratio Term + * PSU_DDR_PHY_PGCR5_FRQBT 0x1 + + * Frequency A Ratio Term + * PSU_DDR_PHY_PGCR5_FRQAT 0x1 + + * DFI Disconnect Time Period + * PSU_DDR_PHY_PGCR5_DISCNPERIOD 0x0 + + * Receiver bias core side control + * PSU_DDR_PHY_PGCR5_VREF_RBCTRL 0xf + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR5_RESERVED_3 0x0 + + * Internal VREF generator REFSEL ragne select + * PSU_DDR_PHY_PGCR5_DXREFISELRANGE 0x1 + + * DDL Page Read Write select + * PSU_DDR_PHY_PGCR5_DDLPGACT 0x0 + + * DDL Page Read Write select + * PSU_DDR_PHY_PGCR5_DDLPGRW 0x0 + + * PHY General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080024, 0xFFFFFFFFU ,0x010100F4U) + */ + PSU_Mask_Write(DDR_PHY_PGCR5_OFFSET, 0xFFFFFFFFU, 0x010100F4U); +/*##################################################################### */ + + /* + * Register : PTR0 @ 0XFD080040 + + * PLL Power-Down Time + * PSU_DDR_PHY_PTR0_TPLLPD 0x216 + + * PLL Gear Shift Time + * PSU_DDR_PHY_PTR0_TPLLGS 0x856 + + * PHY Reset Time + * PSU_DDR_PHY_PTR0_TPHYRST 0x10 + + * PHY Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x42C21590U) + */ + PSU_Mask_Write(DDR_PHY_PTR0_OFFSET, 0xFFFFFFFFU, 0x42C21590U); +/*##################################################################### */ + + /* + * Register : PTR1 @ 0XFD080044 + + * PLL Lock Time + * PSU_DDR_PHY_PTR1_TPLLLOCK 0xd055 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0 + + * PLL Reset Time + * PSU_DDR_PHY_PTR1_TPLLRST 0x12c0 + + * PHY Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0xD05512C0U) + */ + PSU_Mask_Write(DDR_PHY_PTR1_OFFSET, 0xFFFFFFFFU, 0xD05512C0U); +/*##################################################################### */ + + /* + * Register : PLLCR0 @ 0XFD080068 + + * PLL Bypass + * PSU_DDR_PHY_PLLCR0_PLLBYP 0x0 + + * PLL Reset + * PSU_DDR_PHY_PLLCR0_PLLRST 0x0 + + * PLL Power Down + * PSU_DDR_PHY_PLLCR0_PLLPD 0x0 + + * Reference Stop Mode + * PSU_DDR_PHY_PLLCR0_RSTOPM 0x0 + + * PLL Frequency Select + * PSU_DDR_PHY_PLLCR0_FRQSEL 0x1 + + * Relock Mode + * PSU_DDR_PHY_PLLCR0_RLOCKM 0x0 + + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_PLLCR0_CPPC 0x8 + + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_PLLCR0_CPIC 0x0 + + * Gear Shift + * PSU_DDR_PHY_PLLCR0_GSHIFT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PLLCR0_RESERVED_11_9 0x0 + + * Analog Test Enable + * PSU_DDR_PHY_PLLCR0_ATOEN 0x0 + + * Analog Test Control + * PSU_DDR_PHY_PLLCR0_ATC 0x0 + + * Digital Test Control + * PSU_DDR_PHY_PLLCR0_DTC 0x0 + + * PLL Control Register 0 (Type B PLL Only) + * (OFFSET, MASK, VALUE) (0XFD080068, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_PLLCR0_OFFSET, 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ + + /* + * Register : DSGCR @ 0XFD080090 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0 + + * When RDBI enabled, this bit is used to select RDBI CL calculation, if it + * is 1b1, calculation will use RDBICL, otherwise use default calculation. + * PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0 + + * When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v + * alue. + * PSU_DDR_PHY_DSGCR_RDBICL 0x2 + + * PHY Impedance Update Enable + * PSU_DDR_PHY_DSGCR_PHYZUEN 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_22 0x0 + + * SDRAM Reset Output Enable + * PSU_DDR_PHY_DSGCR_RSTOE 0x1 + + * Single Data Rate Mode + * PSU_DDR_PHY_DSGCR_SDRMODE 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_18 0x0 + + * ATO Analog Test Enable + * PSU_DDR_PHY_DSGCR_ATOAE 0x0 + + * DTO Output Enable + * PSU_DDR_PHY_DSGCR_DTOOE 0x0 + + * DTO I/O Mode + * PSU_DDR_PHY_DSGCR_DTOIOM 0x0 + + * DTO Power Down Receiver + * PSU_DDR_PHY_DSGCR_DTOPDR 0x1 + + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_13 0x0 + + * DTO On-Die Termination + * PSU_DDR_PHY_DSGCR_DTOODT 0x0 + + * PHY Update Acknowledge Delay + * PSU_DDR_PHY_DSGCR_PUAD 0x5 + + * Controller Update Acknowledge Enable + * PSU_DDR_PHY_DSGCR_CUAEN 0x1 + + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_4_3 0x0 + + * Controller Impedance Update Enable + * PSU_DDR_PHY_DSGCR_CTLZUEN 0x0 + + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_1 0x0 + + * PHY Update Request Enable + * PSU_DDR_PHY_DSGCR_PUREN 0x1 + + * DDR System General Configuration Register + * (OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04161U) + */ + PSU_Mask_Write(DDR_PHY_DSGCR_OFFSET, 0xFFFFFFFFU, 0x02A04161U); +/*##################################################################### */ + + /* + * Register : GPR0 @ 0XFD0800C0 + + * General Purpose Register 0 + * PSU_DDR_PHY_GPR0_GPR0 0x0 + + * General Purpose Register 0 + * (OFFSET, MASK, VALUE) (0XFD0800C0, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_GPR0_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : GPR1 @ 0XFD0800C4 + + * General Purpose Register 1 + * PSU_DDR_PHY_GPR1_GPR1 0xe3 + + * General Purpose Register 1 + * (OFFSET, MASK, VALUE) (0XFD0800C4, 0xFFFFFFFFU ,0x000000E3U) + */ + PSU_Mask_Write(DDR_PHY_GPR1_OFFSET, 0xFFFFFFFFU, 0x000000E3U); +/*##################################################################### */ + + /* + * Register : DCR @ 0XFD080100 + + * DDR4 Gear Down Timing. + * PSU_DDR_PHY_DCR_GEARDN 0x0 + + * Un-used Bank Group + * PSU_DDR_PHY_DCR_UBG 0x0 + + * Un-buffered DIMM Address Mirroring + * PSU_DDR_PHY_DCR_UDIMM 0x0 + + * DDR 2T Timing + * PSU_DDR_PHY_DCR_DDR2T 0x0 + + * No Simultaneous Rank Access + * PSU_DDR_PHY_DCR_NOSRA 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DCR_RESERVED_26_18 0x0 + + * Byte Mask + * PSU_DDR_PHY_DCR_BYTEMASK 0x1 + + * DDR Type + * PSU_DDR_PHY_DCR_DDRTYPE 0x0 + + * Multi-Purpose Register (MPR) DQ (DDR3 Only) + * PSU_DDR_PHY_DCR_MPRDQ 0x0 + + * Primary DQ (DDR3 Only) + * PSU_DDR_PHY_DCR_PDQ 0x0 + + * DDR 8-Bank + * PSU_DDR_PHY_DCR_DDR8BNK 0x1 + + * DDR Mode + * PSU_DDR_PHY_DCR_DDRMD 0x4 + + * DRAM Configuration Register + * (OFFSET, MASK, VALUE) (0XFD080100, 0xFFFFFFFFU ,0x0800040CU) + */ + PSU_Mask_Write(DDR_PHY_DCR_OFFSET, 0xFFFFFFFFU, 0x0800040CU); +/*##################################################################### */ + + /* + * Register : DTPR0 @ 0XFD080110 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_31_29 0x0 + + * Activate to activate command delay (different banks) + * PSU_DDR_PHY_DTPR0_TRRD 0x7 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_23 0x0 + + * Activate to precharge command delay + * PSU_DDR_PHY_DTPR0_TRAS 0x24 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_15 0x0 + + * Precharge command period + * PSU_DDR_PHY_DTPR0_TRP 0xf + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0 + + * Internal read to precharge command delay + * PSU_DDR_PHY_DTPR0_TRTP 0x8 + + * DRAM Timing Parameters Register 0 + * (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x07240F08U) + */ + PSU_Mask_Write(DDR_PHY_DTPR0_OFFSET, 0xFFFFFFFFU, 0x07240F08U); +/*##################################################################### */ + + /* + * Register : DTPR1 @ 0XFD080114 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_31 0x0 + + * Minimum delay from when write leveling mode is programmed to the first D + * QS/DQS# rising edge. + * PSU_DDR_PHY_DTPR1_TWLMRD 0x28 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_23 0x0 + + * 4-bank activate period + * PSU_DDR_PHY_DTPR1_TFAW 0x20 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0 + + * Load mode update delay (DDR4 and DDR3 only) + * PSU_DDR_PHY_DTPR1_TMOD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0 + + * Load mode cycle time + * PSU_DDR_PHY_DTPR1_TMRD 0x8 + + * DRAM Timing Parameters Register 1 + * (OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28200008U) + */ + PSU_Mask_Write(DDR_PHY_DTPR1_OFFSET, 0xFFFFFFFFU, 0x28200008U); +/*##################################################################### */ + + /* + * Register : DTPR2 @ 0XFD080118 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_31_29 0x0 + + * Read to Write command delay. Valid values are + * PSU_DDR_PHY_DTPR2_TRTW 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_27_25 0x0 + + * Read to ODT delay (DDR3 only) + * PSU_DDR_PHY_DTPR2_TRTODT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0 + + * CKE minimum pulse width + * PSU_DDR_PHY_DTPR2_TCKE 0xf + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0 + + * Self refresh exit delay + * PSU_DDR_PHY_DTPR2_TXS 0x300 + + * DRAM Timing Parameters Register 2 + * (OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x000F0300U) + */ + PSU_Mask_Write(DDR_PHY_DTPR2_OFFSET, 0xFFFFFFFFU, 0x000F0300U); +/*##################################################################### */ + + /* + * Register : DTPR3 @ 0XFD08011C + + * ODT turn-off delay extension + * PSU_DDR_PHY_DTPR3_TOFDX 0x4 + + * Read to read and write to write command delay + * PSU_DDR_PHY_DTPR3_TCCD 0x0 + + * DLL locking time + * PSU_DDR_PHY_DTPR3_TDLLK 0x300 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR3_RESERVED_15_12 0x0 + + * Maximum DQS output access time from CK/CK# (LPDDR2/3 only) + * PSU_DDR_PHY_DTPR3_TDQSCKMAX 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0 + + * DQS output access time from CK/CK# (LPDDR2/3 only) + * PSU_DDR_PHY_DTPR3_TDQSCK 0x0 + + * DRAM Timing Parameters Register 3 + * (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U) + */ + PSU_Mask_Write(DDR_PHY_DTPR3_OFFSET, 0xFFFFFFFFU, 0x83000800U); +/*##################################################################### */ + + /* + * Register : DTPR4 @ 0XFD080120 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_31_30 0x0 + + * ODT turn-on/turn-off delays (DDR2 only) + * PSU_DDR_PHY_DTPR4_TAOND_TAOFD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_27_26 0x0 + + * Refresh-to-Refresh + * PSU_DDR_PHY_DTPR4_TRFC 0x176 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_15_14 0x0 + + * Write leveling output delay + * PSU_DDR_PHY_DTPR4_TWLO 0x2b + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0 + + * Power down exit delay + * PSU_DDR_PHY_DTPR4_TXP 0x7 + + * DRAM Timing Parameters Register 4 + * (OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01762B07U) + */ + PSU_Mask_Write(DDR_PHY_DTPR4_OFFSET, 0xFFFFFFFFU, 0x01762B07U); +/*##################################################################### */ + + /* + * Register : DTPR5 @ 0XFD080124 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0 + + * Activate to activate command delay (same bank) + * PSU_DDR_PHY_DTPR5_TRC 0x33 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_15 0x0 + + * Activate to read or write delay + * PSU_DDR_PHY_DTPR5_TRCD 0xf + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0 + + * Internal write to read command delay + * PSU_DDR_PHY_DTPR5_TWTR 0x8 + + * DRAM Timing Parameters Register 5 + * (OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00330F08U) + */ + PSU_Mask_Write(DDR_PHY_DTPR5_OFFSET, 0xFFFFFFFFU, 0x00330F08U); +/*##################################################################### */ + + /* + * Register : DTPR6 @ 0XFD080128 + + * PUB Write Latency Enable + * PSU_DDR_PHY_DTPR6_PUBWLEN 0x0 + + * PUB Read Latency Enable + * PSU_DDR_PHY_DTPR6_PUBRLEN 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR6_RESERVED_29_14 0x0 + + * Write Latency + * PSU_DDR_PHY_DTPR6_PUBWL 0xe + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR6_RESERVED_7_6 0x0 + + * Read Latency + * PSU_DDR_PHY_DTPR6_PUBRL 0xf + + * DRAM Timing Parameters Register 6 + * (OFFSET, MASK, VALUE) (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU) + */ + PSU_Mask_Write(DDR_PHY_DTPR6_OFFSET, 0xFFFFFFFFU, 0x00000E0FU); +/*##################################################################### */ + + /* + * Register : RDIMMGCR0 @ 0XFD080140 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_31 0x0 + + * RDMIMM Quad CS Enable + * PSU_DDR_PHY_RDIMMGCR0_QCSEN 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28 0x0 + + * RDIMM Outputs I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24 0x0 + + * ERROUT# Output Enable + * PSU_DDR_PHY_RDIMMGCR0_ERROUTOE 0x0 + + * ERROUT# I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM 0x1 + + * ERROUT# Power Down Receiver + * PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_20 0x0 + + * ERROUT# On-Die Termination + * PSU_DDR_PHY_RDIMMGCR0_ERROUTODT 0x0 + + * Load Reduced DIMM + * PSU_DDR_PHY_RDIMMGCR0_LRDIMM 0x0 + + * PAR_IN I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_PARINIOM 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD 0x0 + + * Rank Mirror Enable. + * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN 0x2 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_3 0x0 + + * Stop on Parity Error + * PSU_DDR_PHY_RDIMMGCR0_SOPERR 0x0 + + * Parity Error No Registering + * PSU_DDR_PHY_RDIMMGCR0_ERRNOREG 0x0 + + * Registered DIMM + * PSU_DDR_PHY_RDIMMGCR0_RDIMM 0x0 + + * RDIMM General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080140, 0xFFFFFFFFU ,0x08400020U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMGCR0_OFFSET, 0xFFFFFFFFU, 0x08400020U); +/*##################################################################### */ + + /* + * Register : RDIMMGCR1 @ 0XFD080144 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29 0x0 + + * Address [17] B-side Inversion Disable + * PSU_DDR_PHY_RDIMMGCR1_A17BID 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_27 0x0 + + * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_23 0x0 + + * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_19 0x0 + + * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14 0x0 + + * Stabilization time + * PSU_DDR_PHY_RDIMMGCR1_TBCSTAB 0xc80 + + * RDIMM General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMGCR1_OFFSET, 0xFFFFFFFFU, 0x00000C80U); +/*##################################################################### */ + + /* + * Register : RDIMMCR0 @ 0XFD080150 + + * DDR4/DDR3 Control Word 7 + * PSU_DDR_PHY_RDIMMCR0_RC7 0x0 + + * DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR0_RC6 0x0 + + * DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC5 0x0 + + * DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control + * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont + * rol Word) + * PSU_DDR_PHY_RDIMMCR0_RC4 0x0 + + * DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo + * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri + * cs Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC3 0x0 + + * DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 + * (Timing Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC2 0x0 + + * DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC1 0x0 + + * DDR4/DDR3 Control Word 0 (Global Features Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC0 0x0 + + * RDIMM Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMCR0_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RDIMMCR1 @ 0XFD080154 + + * Control Word 15 + * PSU_DDR_PHY_RDIMMCR1_RC15 0x0 + + * DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC14 0x0 + + * DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC13 0x0 + + * DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC12 0x0 + + * DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo + * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC11 0x0 + + * DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC10 0x2 + + * DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC9 0x0 + + * DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con + * trol Word 8 (Additional Input Bus Termination Setting Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC8 0x0 + + * RDIMM Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD080154, 0xFFFFFFFFU ,0x00000200U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMCR1_OFFSET, 0xFFFFFFFFU, 0x00000200U); +/*##################################################################### */ + + /* + * Register : MR0 @ 0XFD080180 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR0_RESERVED_31_8 0x6 + + * CA Terminating Rank + * PSU_DDR_PHY_MR0_CATR 0x0 + + * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. + * PSU_DDR_PHY_MR0_RSVD_6_5 0x1 + + * Built-in Self-Test for RZQ + * PSU_DDR_PHY_MR0_RZQI 0x2 + + * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. + * PSU_DDR_PHY_MR0_RSVD_2_0 0x0 + + * LPDDR4 Mode Register 0 + * (OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000630U) + */ + PSU_Mask_Write(DDR_PHY_MR0_OFFSET, 0xFFFFFFFFU, 0x00000630U); +/*##################################################################### */ + + /* + * Register : MR1 @ 0XFD080184 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR1_RESERVED_31_8 0x3 + + * Read Postamble Length + * PSU_DDR_PHY_MR1_RDPST 0x0 + + * Write-recovery for auto-precharge command + * PSU_DDR_PHY_MR1_NWR 0x0 + + * Read Preamble Length + * PSU_DDR_PHY_MR1_RDPRE 0x0 + + * Write Preamble Length + * PSU_DDR_PHY_MR1_WRPRE 0x0 + + * Burst Length + * PSU_DDR_PHY_MR1_BL 0x1 + + * LPDDR4 Mode Register 1 + * (OFFSET, MASK, VALUE) (0XFD080184, 0xFFFFFFFFU ,0x00000301U) + */ + PSU_Mask_Write(DDR_PHY_MR1_OFFSET, 0xFFFFFFFFU, 0x00000301U); +/*##################################################################### */ + + /* + * Register : MR2 @ 0XFD080188 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR2_RESERVED_31_8 0x0 + + * Write Leveling + * PSU_DDR_PHY_MR2_WRL 0x0 + + * Write Latency Set + * PSU_DDR_PHY_MR2_WLS 0x0 + + * Write Latency + * PSU_DDR_PHY_MR2_WL 0x4 + + * Read Latency + * PSU_DDR_PHY_MR2_RL 0x0 + + * LPDDR4 Mode Register 2 + * (OFFSET, MASK, VALUE) (0XFD080188, 0xFFFFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(DDR_PHY_MR2_OFFSET, 0xFFFFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MR3 @ 0XFD08018C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR3_RESERVED_31_8 0x2 + + * DBI-Write Enable + * PSU_DDR_PHY_MR3_DBIWR 0x0 + + * DBI-Read Enable + * PSU_DDR_PHY_MR3_DBIRD 0x0 + + * Pull-down Drive Strength + * PSU_DDR_PHY_MR3_PDDS 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR3_RSVD 0x0 + + * Write Postamble Length + * PSU_DDR_PHY_MR3_WRPST 0x0 + + * Pull-up Calibration Point + * PSU_DDR_PHY_MR3_PUCAL 0x0 + + * LPDDR4 Mode Register 3 + * (OFFSET, MASK, VALUE) (0XFD08018C, 0xFFFFFFFFU ,0x00000200U) + */ + PSU_Mask_Write(DDR_PHY_MR3_OFFSET, 0xFFFFFFFFU, 0x00000200U); +/*##################################################################### */ + + /* + * Register : MR4 @ 0XFD080190 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR4_RESERVED_31_16 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR4_RSVD_15_13 0x0 + + * Write Preamble + * PSU_DDR_PHY_MR4_WRP 0x0 + + * Read Preamble + * PSU_DDR_PHY_MR4_RDP 0x0 + + * Read Preamble Training Mode + * PSU_DDR_PHY_MR4_RPTM 0x0 + + * Self Refresh Abort + * PSU_DDR_PHY_MR4_SRA 0x0 + + * CS to Command Latency Mode + * PSU_DDR_PHY_MR4_CS2CMDL 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR4_RSVD1 0x0 + + * Internal VREF Monitor + * PSU_DDR_PHY_MR4_IVM 0x0 + + * Temperature Controlled Refresh Mode + * PSU_DDR_PHY_MR4_TCRM 0x0 + + * Temperature Controlled Refresh Range + * PSU_DDR_PHY_MR4_TCRR 0x0 + + * Maximum Power Down Mode + * PSU_DDR_PHY_MR4_MPDM 0x0 + + * This is a JEDEC reserved bit and is recommended by JEDEC to be programme + * d to 0x0. + * PSU_DDR_PHY_MR4_RSVD_0 0x0 + + * DDR4 Mode Register 4 + * (OFFSET, MASK, VALUE) (0XFD080190, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR4_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MR5 @ 0XFD080194 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR5_RESERVED_31_16 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR5_RSVD 0x0 + + * Read DBI + * PSU_DDR_PHY_MR5_RDBI 0x0 + + * Write DBI + * PSU_DDR_PHY_MR5_WDBI 0x0 + + * Data Mask + * PSU_DDR_PHY_MR5_DM 0x1 + + * CA Parity Persistent Error + * PSU_DDR_PHY_MR5_CAPPE 0x1 + + * RTT_PARK + * PSU_DDR_PHY_MR5_RTTPARK 0x3 + + * ODT Input Buffer during Power Down mode + * PSU_DDR_PHY_MR5_ODTIBPD 0x0 + + * C/A Parity Error Status + * PSU_DDR_PHY_MR5_CAPES 0x0 + + * CRC Error Clear + * PSU_DDR_PHY_MR5_CRCEC 0x0 + + * C/A Parity Latency Mode + * PSU_DDR_PHY_MR5_CAPM 0x0 + + * DDR4 Mode Register 5 + * (OFFSET, MASK, VALUE) (0XFD080194, 0xFFFFFFFFU ,0x000006C0U) + */ + PSU_Mask_Write(DDR_PHY_MR5_OFFSET, 0xFFFFFFFFU, 0x000006C0U); +/*##################################################################### */ + + /* + * Register : MR6 @ 0XFD080198 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR6_RESERVED_31_16 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR6_RSVD_15_13 0x0 + + * CAS_n to CAS_n command delay for same bank group (tCCD_L) + * PSU_DDR_PHY_MR6_TCCDL 0x2 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR6_RSVD_9_8 0x0 + + * VrefDQ Training Enable + * PSU_DDR_PHY_MR6_VDDQTEN 0x0 + + * VrefDQ Training Range + * PSU_DDR_PHY_MR6_VDQTRG 0x0 + + * VrefDQ Training Values + * PSU_DDR_PHY_MR6_VDQTVAL 0x19 + + * DDR4 Mode Register 6 + * (OFFSET, MASK, VALUE) (0XFD080198, 0xFFFFFFFFU ,0x00000819U) + */ + PSU_Mask_Write(DDR_PHY_MR6_OFFSET, 0xFFFFFFFFU, 0x00000819U); +/*##################################################################### */ + + /* + * Register : MR11 @ 0XFD0801AC + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR11_RESERVED_31_8 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR11_RSVD 0x0 + + * Power Down Control + * PSU_DDR_PHY_MR11_PDCTL 0x0 + + * DQ Bus Receiver On-Die-Termination + * PSU_DDR_PHY_MR11_DQODT 0x0 + + * LPDDR4 Mode Register 11 + * (OFFSET, MASK, VALUE) (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR11_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MR12 @ 0XFD0801B0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR12_RESERVED_31_8 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR12_RSVD 0x0 + + * VREF_CA Range Select. + * PSU_DDR_PHY_MR12_VR_CA 0x1 + + * Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. + * PSU_DDR_PHY_MR12_VREF_CA 0xd + + * LPDDR4 Mode Register 12 + * (OFFSET, MASK, VALUE) (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU) + */ + PSU_Mask_Write(DDR_PHY_MR12_OFFSET, 0xFFFFFFFFU, 0x0000004DU); +/*##################################################################### */ + + /* + * Register : MR13 @ 0XFD0801B4 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR13_RESERVED_31_8 0x0 + + * Frequency Set Point Operation Mode + * PSU_DDR_PHY_MR13_FSPOP 0x0 + + * Frequency Set Point Write Enable + * PSU_DDR_PHY_MR13_FSPWR 0x0 + + * Data Mask Enable + * PSU_DDR_PHY_MR13_DMD 0x0 + + * Refresh Rate Option + * PSU_DDR_PHY_MR13_RRO 0x0 + + * VREF Current Generator + * PSU_DDR_PHY_MR13_VRCG 0x1 + + * VREF Output + * PSU_DDR_PHY_MR13_VRO 0x0 + + * Read Preamble Training Mode + * PSU_DDR_PHY_MR13_RPT 0x0 + + * Command Bus Training + * PSU_DDR_PHY_MR13_CBT 0x0 + + * LPDDR4 Mode Register 13 + * (OFFSET, MASK, VALUE) (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U) + */ + PSU_Mask_Write(DDR_PHY_MR13_OFFSET, 0xFFFFFFFFU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MR14 @ 0XFD0801B8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR14_RESERVED_31_8 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR14_RSVD 0x0 + + * VREFDQ Range Selects. + * PSU_DDR_PHY_MR14_VR_DQ 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR14_VREF_DQ 0xd + + * LPDDR4 Mode Register 14 + * (OFFSET, MASK, VALUE) (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU) + */ + PSU_Mask_Write(DDR_PHY_MR14_OFFSET, 0xFFFFFFFFU, 0x0000004DU); +/*##################################################################### */ + + /* + * Register : MR22 @ 0XFD0801D8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR22_RESERVED_31_8 0x0 + + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR22_RSVD 0x0 + + * CA ODT termination disable. + * PSU_DDR_PHY_MR22_ODTD_CA 0x0 + + * ODT CS override. + * PSU_DDR_PHY_MR22_ODTE_CS 0x0 + + * ODT CK override. + * PSU_DDR_PHY_MR22_ODTE_CK 0x0 + + * Controller ODT value for VOH calibration. + * PSU_DDR_PHY_MR22_CODT 0x0 + + * LPDDR4 Mode Register 22 + * (OFFSET, MASK, VALUE) (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR22_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DTCR0 @ 0XFD080200 + + * Refresh During Training + * PSU_DDR_PHY_DTCR0_RFSHDT 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0 + + * Data Training Debug Rank Select + * PSU_DDR_PHY_DTCR0_DTDRS 0x0 + + * Data Training with Early/Extended Gate + * PSU_DDR_PHY_DTCR0_DTEXG 0x0 + + * Data Training Extended Write DQS + * PSU_DDR_PHY_DTCR0_DTEXD 0x0 + + * Data Training Debug Step + * PSU_DDR_PHY_DTCR0_DTDSTP 0x0 + + * Data Training Debug Enable + * PSU_DDR_PHY_DTCR0_DTDEN 0x0 + + * Data Training Debug Byte Select + * PSU_DDR_PHY_DTCR0_DTDBS 0x0 + + * Data Training read DBI deskewing configuration + * PSU_DDR_PHY_DTCR0_DTRDBITR 0x2 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_13 0x0 + + * Data Training Write Bit Deskew Data Mask + * PSU_DDR_PHY_DTCR0_DTWBDDM 0x1 + + * Refreshes Issued During Entry to Training + * PSU_DDR_PHY_DTCR0_RFSHEN 0x1 + + * Data Training Compare Data + * PSU_DDR_PHY_DTCR0_DTCMPD 0x1 + + * Data Training Using MPR + * PSU_DDR_PHY_DTCR0_DTMPR 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_5_4 0x0 + + * Data Training Repeat Number + * PSU_DDR_PHY_DTCR0_DTRPTN 0x7 + + * Data Training Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U) + */ + PSU_Mask_Write(DDR_PHY_DTCR0_OFFSET, 0xFFFFFFFFU, 0x800091C7U); +/*##################################################################### */ + + /* + * Register : DTCR1 @ 0XFD080204 + + * Rank Enable. + * PSU_DDR_PHY_DTCR1_RANKEN_RSVD 0x0 + + * Rank Enable. + * PSU_DDR_PHY_DTCR1_RANKEN 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_15_14 0x0 + + * Data Training Rank + * PSU_DDR_PHY_DTCR1_DTRANK 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_11 0x0 + + * Read Leveling Gate Sampling Difference + * PSU_DDR_PHY_DTCR1_RDLVLGDIFF 0x2 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_7 0x0 + + * Read Leveling Gate Shift + * PSU_DDR_PHY_DTCR1_RDLVLGS 0x3 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_3 0x0 + + * Read Preamble Training enable + * PSU_DDR_PHY_DTCR1_RDPRMVL_TRN 0x1 + + * Read Leveling Enable + * PSU_DDR_PHY_DTCR1_RDLVLEN 0x1 + + * Basic Gate Training Enable + * PSU_DDR_PHY_DTCR1_BSTEN 0x0 + + * Data Training Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080204, 0xFFFFFFFFU ,0x00010236U) + */ + PSU_Mask_Write(DDR_PHY_DTCR1_OFFSET, 0xFFFFFFFFU, 0x00010236U); +/*##################################################################### */ + + /* + * Register : CATR0 @ 0XFD080240 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0 + + * Minimum time (in terms of number of dram clocks) between two consectuve + * CA calibration command + * PSU_DDR_PHY_CATR0_CACD 0x14 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0 + + * Minimum time (in terms of number of dram clocks) PUB should wait before + * sampling the CA response after Calibration command has been sent to the + * memory + * PSU_DDR_PHY_CATR0_CAADR 0x10 + + * CA_1 Response Byte Lane 1 + * PSU_DDR_PHY_CATR0_CA1BYTE1 0x5 + + * CA_1 Response Byte Lane 0 + * PSU_DDR_PHY_CATR0_CA1BYTE0 0x4 + + * CA Training Register 0 + * (OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) + */ + PSU_Mask_Write(DDR_PHY_CATR0_OFFSET, 0xFFFFFFFFU, 0x00141054U); +/*##################################################################### */ + + /* + * Register : DQSDR0 @ 0XFD080250 + + * Number of delay taps by which the DQS gate LCDL will be updated when DQS + * drift is detected + * PSU_DDR_PHY_DQSDR0_DFTDLY 0x0 + + * Drift Impedance Update + * PSU_DDR_PHY_DQSDR0_DFTZQUP 0x0 + + * Drift DDL Update + * PSU_DDR_PHY_DQSDR0_DFTDDLUP 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DQSDR0_RESERVED_25_22 0x0 + + * Drift Read Spacing + * PSU_DDR_PHY_DQSDR0_DFTRDSPC 0x0 + + * Drift Back-to-Back Reads + * PSU_DDR_PHY_DQSDR0_DFTB2BRD 0x8 + + * Drift Idle Reads + * PSU_DDR_PHY_DQSDR0_DFTIDLRD 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DQSDR0_RESERVED_11_8 0x0 + + * Gate Pulse Enable + * PSU_DDR_PHY_DQSDR0_DFTGPULSE 0x0 + + * DQS Drift Update Mode + * PSU_DDR_PHY_DQSDR0_DFTUPMODE 0x0 + + * DQS Drift Detection Mode + * PSU_DDR_PHY_DQSDR0_DFTDTMODE 0x0 + + * DQS Drift Detection Enable + * PSU_DDR_PHY_DQSDR0_DFTDTEN 0x0 + + * DQS Drift Register 0 + * (OFFSET, MASK, VALUE) (0XFD080250, 0xFFFFFFFFU ,0x00088000U) + */ + PSU_Mask_Write(DDR_PHY_DQSDR0_OFFSET, 0xFFFFFFFFU, 0x00088000U); +/*##################################################################### */ + + /* + * Register : BISTLSR @ 0XFD080414 + + * LFSR seed for pseudo-random BIST patterns + * PSU_DDR_PHY_BISTLSR_SEED 0x12341000 + + * BIST LFSR Seed Register + * (OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U) + */ + PSU_Mask_Write(DDR_PHY_BISTLSR_OFFSET, 0xFFFFFFFFU, 0x12341000U); +/*##################################################################### */ + + /* + * Register : RIOCR5 @ 0XFD0804F4 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RIOCR5_RESERVED_31_16 0x0 + + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD 0x0 + + * SDRAM On-die Termination Output Enable (OE) Mode Selection. + * PSU_DDR_PHY_RIOCR5_ODTOEMODE 0x5 + + * Rank I/O Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U) + */ + PSU_Mask_Write(DDR_PHY_RIOCR5_OFFSET, 0xFFFFFFFFU, 0x00000005U); +/*##################################################################### */ + + /* + * Register : ACIOCR0 @ 0XFD080500 + + * Address/Command Slew Rate (D3F I/O Only) + * PSU_DDR_PHY_ACIOCR0_ACSR 0x0 + + * SDRAM Reset I/O Mode + * PSU_DDR_PHY_ACIOCR0_RSTIOM 0x1 + + * SDRAM Reset Power Down Receiver + * PSU_DDR_PHY_ACIOCR0_RSTPDR 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_27 0x0 + + * SDRAM Reset On-Die Termination + * PSU_DDR_PHY_ACIOCR0_RSTODT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_25_10 0x0 + + * CK Duty Cycle Correction + * PSU_DDR_PHY_ACIOCR0_CKDCC 0x0 + + * AC Power Down Receiver Mode + * PSU_DDR_PHY_ACIOCR0_ACPDRMODE 0x2 + + * AC On-die Termination Mode + * PSU_DDR_PHY_ACIOCR0_ACODTMODE 0x2 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_1 0x0 + + * Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. + * PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL 0x0 + + * AC I/O Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080500, 0xFFFFFFFFU ,0x30000028U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR0_OFFSET, 0xFFFFFFFFU, 0x30000028U); +/*##################################################################### */ + + /* + * Register : ACIOCR2 @ 0XFD080508 + + * Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL + * slice + * PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0 + + * Clock gating for Output Enable D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0 0x0 + + * Clock gating for Power Down Receiver D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0 0x0 + + * Clock gating for Termination Enable D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0 0x0 + + * Clock gating for CK# D slices [1:0] + * PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0 0x2 + + * Clock gating for CK D slices [1:0] + * PSU_DDR_PHY_ACIOCR2_CKCLKGATE0 0x2 + + * Clock gating for AC D slices [23:0] + * PSU_DDR_PHY_ACIOCR2_ACCLKGATE0 0x0 + + * AC I/O Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080508, 0xFFFFFFFFU ,0x0A000000U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR2_OFFSET, 0xFFFFFFFFU, 0x0A000000U); +/*##################################################################### */ + + /* + * Register : ACIOCR3 @ 0XFD08050C + + * SDRAM Parity Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_PAROEMODE 0x0 + + * SDRAM Bank Group Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_BGOEMODE 0x0 + + * SDRAM Bank Address Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_BAOEMODE 0x0 + + * SDRAM A[17] Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_A17OEMODE 0x0 + + * SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_A16OEMODE 0x0 + + * SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) + * PSU_DDR_PHY_ACIOCR3_ACTOEMODE 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR3_RESERVED_15_8 0x0 + + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD 0x0 + + * SDRAM CK Output Enable (OE) Mode Selection. + * PSU_DDR_PHY_ACIOCR3_CKOEMODE 0x9 + + * AC I/O Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08050C, 0xFFFFFFFFU ,0x00000009U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR3_OFFSET, 0xFFFFFFFFU, 0x00000009U); +/*##################################################################### */ + + /* + * Register : ACIOCR4 @ 0XFD080510 + + * Clock gating for AC LB slices and loopback read valid slices + * PSU_DDR_PHY_ACIOCR4_LBCLKGATE 0x0 + + * Clock gating for Output Enable D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1 0x0 + + * Clock gating for Power Down Receiver D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1 0x0 + + * Clock gating for Termination Enable D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1 0x0 + + * Clock gating for CK# D slices [3:2] + * PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1 0x2 + + * Clock gating for CK D slices [3:2] + * PSU_DDR_PHY_ACIOCR4_CKCLKGATE1 0x2 + + * Clock gating for AC D slices [47:24] + * PSU_DDR_PHY_ACIOCR4_ACCLKGATE1 0x0 + + * AC I/O Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080510, 0xFFFFFFFFU ,0x0A000000U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR4_OFFSET, 0xFFFFFFFFU, 0x0A000000U); +/*##################################################################### */ + + /* + * Register : IOVCR0 @ 0XFD080520 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_IOVCR0_RESERVED_31_29 0x0 + + * Address/command lane VREF Pad Enable + * PSU_DDR_PHY_IOVCR0_ACREFPEN 0x0 + + * Address/command lane Internal VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFEEN 0x0 + + * Address/command lane Single-End VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFSEN 0x1 + + * Address/command lane Internal VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFIEN 0x1 + + * External VREF generato REFSEL range select + * PSU_DDR_PHY_IOVCR0_ACREFESELRANGE 0x0 + + * Address/command lane External VREF Select + * PSU_DDR_PHY_IOVCR0_ACREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE 0x1 + + * Address/command lane Single-End VREF Select + * PSU_DDR_PHY_IOVCR0_ACREFSSEL 0x30 + + * Internal VREF generator REFSEL ragne select + * PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1 + + * REFSEL Control for internal AC IOs + * PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x4e + + * IO VREF Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0CEU) + */ + PSU_Mask_Write(DDR_PHY_IOVCR0_OFFSET, 0xFFFFFFFFU, 0x0300B0CEU); +/*##################################################################### */ + + /* + * Register : VTCR0 @ 0XFD080528 + + * Number of ctl_clk required to meet (> 150ns) timing requirements during + * DRAM DQ VREF training + * PSU_DDR_PHY_VTCR0_TVREF 0x7 + + * DRM DQ VREF training Enable + * PSU_DDR_PHY_VTCR0_DVEN 0x1 + + * Per Device Addressability Enable + * PSU_DDR_PHY_VTCR0_PDAEN 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR0_RESERVED_26 0x0 + + * VREF Word Count + * PSU_DDR_PHY_VTCR0_VWCR 0x4 + + * DRAM DQ VREF step size used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVSS 0x0 + + * Maximum VREF limit value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVMAX 0x32 + + * Minimum VREF limit value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVMIN 0x0 + + * Initial DRAM DQ VREF value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVINIT 0x19 + + * VREF Training Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080528, 0xFFFFFFFFU ,0xF9032019U) + */ + PSU_Mask_Write(DDR_PHY_VTCR0_OFFSET, 0xFFFFFFFFU, 0xF9032019U); +/*##################################################################### */ + + /* + * Register : VTCR1 @ 0XFD08052C + + * Host VREF step size used during VREF training. The register value of N i + * ndicates step size of (N+1) + * PSU_DDR_PHY_VTCR1_HVSS 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_27 0x0 + + * Maximum VREF limit value used during DRAM VREF training. + * PSU_DDR_PHY_VTCR1_HVMAX 0x7f + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_19 0x0 + + * Minimum VREF limit value used during DRAM VREF training. + * PSU_DDR_PHY_VTCR1_HVMIN 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_11 0x0 + + * Static Host Vref Rank Value + * PSU_DDR_PHY_VTCR1_SHRNK 0x0 + + * Static Host Vref Rank Enable + * PSU_DDR_PHY_VTCR1_SHREN 0x1 + + * Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir + * ements during Host IO VREF training + * PSU_DDR_PHY_VTCR1_TVREFIO 0x7 + + * Eye LCDL Offset value for VREF training + * PSU_DDR_PHY_VTCR1_EOFF 0x0 + + * Number of LCDL Eye points for which VREF training is repeated + * PSU_DDR_PHY_VTCR1_ENUM 0x0 + + * HOST (IO) internal VREF training Enable + * PSU_DDR_PHY_VTCR1_HVEN 0x1 + + * Host IO Type Control + * PSU_DDR_PHY_VTCR1_HVIO 0x1 + + * VREF Training Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U) + */ + PSU_Mask_Write(DDR_PHY_VTCR1_OFFSET, 0xFFFFFFFFU, 0x07F001E3U); +/*##################################################################### */ + + /* + * Register : ACBDLR1 @ 0XFD080544 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0 + + * Delay select for the BDL on Parity. + * PSU_DDR_PHY_ACBDLR1_PARBD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0 + + * Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn + * ected to WE. + * PSU_DDR_PHY_ACBDLR1_A16BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0 + + * Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi + * s pin is connected to CAS. + * PSU_DDR_PHY_ACBDLR1_A17BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0 + + * Delay select for the BDL on ACTN. + * PSU_DDR_PHY_ACBDLR1_ACTBD 0x0 + + * AC Bit Delay Line Register 1 + * (OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR1_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ACBDLR2 @ 0XFD080548 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0 + + * Delay select for the BDL on BG[1]. + * PSU_DDR_PHY_ACBDLR2_BG1BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0 + + * Delay select for the BDL on BG[0]. + * PSU_DDR_PHY_ACBDLR2_BG0BD 0x0 + + * Reser.ved Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0 + + * Delay select for the BDL on BA[1]. + * PSU_DDR_PHY_ACBDLR2_BA1BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0 + + * Delay select for the BDL on BA[0]. + * PSU_DDR_PHY_ACBDLR2_BA0BD 0x0 + + * AC Bit Delay Line Register 2 + * (OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ACBDLR6 @ 0XFD080558 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0 + + * Delay select for the BDL on Address A[3]. + * PSU_DDR_PHY_ACBDLR6_A03BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0 + + * Delay select for the BDL on Address A[2]. + * PSU_DDR_PHY_ACBDLR6_A02BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0 + + * Delay select for the BDL on Address A[1]. + * PSU_DDR_PHY_ACBDLR6_A01BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0 + + * Delay select for the BDL on Address A[0]. + * PSU_DDR_PHY_ACBDLR6_A00BD 0x0 + + * AC Bit Delay Line Register 6 + * (OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR6_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ACBDLR7 @ 0XFD08055C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0 + + * Delay select for the BDL on Address A[7]. + * PSU_DDR_PHY_ACBDLR7_A07BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0 + + * Delay select for the BDL on Address A[6]. + * PSU_DDR_PHY_ACBDLR7_A06BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_15_14 0x0 + + * Delay select for the BDL on Address A[5]. + * PSU_DDR_PHY_ACBDLR7_A05BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_7_6 0x0 + + * Delay select for the BDL on Address A[4]. + * PSU_DDR_PHY_ACBDLR7_A04BD 0x0 + + * AC Bit Delay Line Register 7 + * (OFFSET, MASK, VALUE) (0XFD08055C, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR7_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ACBDLR8 @ 0XFD080560 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_31_30 0x0 + + * Delay select for the BDL on Address A[11]. + * PSU_DDR_PHY_ACBDLR8_A11BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_23_22 0x0 + + * Delay select for the BDL on Address A[10]. + * PSU_DDR_PHY_ACBDLR8_A10BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_15_14 0x0 + + * Delay select for the BDL on Address A[9]. + * PSU_DDR_PHY_ACBDLR8_A09BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_7_6 0x0 + + * Delay select for the BDL on Address A[8]. + * PSU_DDR_PHY_ACBDLR8_A08BD 0x0 + + * AC Bit Delay Line Register 8 + * (OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR8_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ACBDLR9 @ 0XFD080564 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0 + + * Delay select for the BDL on Address A[15]. + * PSU_DDR_PHY_ACBDLR9_A15BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0 + + * Delay select for the BDL on Address A[14]. + * PSU_DDR_PHY_ACBDLR9_A14BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0 + + * Delay select for the BDL on Address A[13]. + * PSU_DDR_PHY_ACBDLR9_A13BD 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0 + + * Delay select for the BDL on Address A[12]. + * PSU_DDR_PHY_ACBDLR9_A12BD 0x0 + + * AC Bit Delay Line Register 9 + * (OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR9_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ZQCR @ 0XFD080680 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0 + + * ZQ VREF Range + * PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0 + + * Programmable Wait for Frequency B + * PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11 + + * Programmable Wait for Frequency A + * PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x15 + + * ZQ VREF Pad Enable + * PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0 + + * ZQ Internal VREF Enable + * PSU_DDR_PHY_ZQCR_ZQREFIEN 0x1 + + * Choice of termination mode + * PSU_DDR_PHY_ZQCR_ODT_MODE 0x1 + + * Force ZCAL VT update + * PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE 0x0 + + * IO VT Drift Limit + * PSU_DDR_PHY_ZQCR_IODLMT 0x2 + + * Averaging algorithm enable, if set, enables averaging algorithm + * PSU_DDR_PHY_ZQCR_AVGEN 0x1 + + * Maximum number of averaging rounds to be used by averaging algorithm + * PSU_DDR_PHY_ZQCR_AVGMAX 0x2 + + * ZQ Calibration Type + * PSU_DDR_PHY_ZQCR_ZCALT 0x0 + + * ZQ Power Down + * PSU_DDR_PHY_ZQCR_ZQPD 0x0 + + * ZQ Impedance Control Register + * (OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008AAA58U) + */ + PSU_Mask_Write(DDR_PHY_ZQCR_OFFSET, 0xFFFFFFFFU, 0x008AAA58U); +/*##################################################################### */ + + /* + * Register : ZQ0PR0 @ 0XFD080684 + + * Pull-down drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN 0x0 + + * Pull-up drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN 0x0 + + * Pull-down termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN 0x0 + + * Pull-up termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN 0x0 + + * Calibration segment bypass + * PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0 + + * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB + * PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0 + + * Termination adjustment + * PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST 0x0 + + * Pulldown drive strength adjustment + * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST 0x0 + + * Pullup drive strength adjustment + * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST 0x0 + + * DRAM Impedance Divide Ratio + * PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7 + + * HOST Impedance Divide Ratio + * PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x9 + + * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) + * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd + + * Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) + * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd + + * ZQ n Impedance Control Program Register 0 + * (OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000079DDU) + */ + PSU_Mask_Write(DDR_PHY_ZQ0PR0_OFFSET, 0xFFFFFFFFU, 0x000079DDU); +/*##################################################################### */ + + /* + * Register : ZQ0OR0 @ 0XFD080694 + + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26 0x0 + + * Override value for the pull-up output impedance + * PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD 0x1e1 + + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10 0x0 + + * Override value for the pull-down output impedance + * PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD 0x210 + + * ZQ n Impedance Control Override Data Register 0 + * (OFFSET, MASK, VALUE) (0XFD080694, 0xFFFFFFFFU ,0x01E10210U) + */ + PSU_Mask_Write(DDR_PHY_ZQ0OR0_OFFSET, 0xFFFFFFFFU, 0x01E10210U); +/*##################################################################### */ + + /* + * Register : ZQ0OR1 @ 0XFD080698 + + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26 0x0 + + * Override value for the pull-up termination + * PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD 0x1e1 + + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10 0x0 + + * Override value for the pull-down termination + * PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD 0x0 + + * ZQ n Impedance Control Override Data Register 1 + * (OFFSET, MASK, VALUE) (0XFD080698, 0xFFFFFFFFU ,0x01E10000U) + */ + PSU_Mask_Write(DDR_PHY_ZQ0OR1_OFFSET, 0xFFFFFFFFU, 0x01E10000U); +/*##################################################################### */ + + /* + * Register : ZQ1PR0 @ 0XFD0806A4 + + * Pull-down drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN 0x0 + + * Pull-up drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN 0x0 + + * Pull-down termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN 0x0 + + * Pull-up termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN 0x0 + + * Calibration segment bypass + * PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0 + + * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB + * PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0 + + * Termination adjustment + * PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST 0x0 + + * Pulldown drive strength adjustment + * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST 0x1 + + * Pullup drive strength adjustment + * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST 0x0 + + * DRAM Impedance Divide Ratio + * PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT 0x7 + + * HOST Impedance Divide Ratio + * PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb + + * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) + * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd + + * Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) + * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb + + * ZQ n Impedance Control Program Register 0 + * (OFFSET, MASK, VALUE) (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU) + */ + PSU_Mask_Write(DDR_PHY_ZQ1PR0_OFFSET, 0xFFFFFFFFU, 0x00087BDBU); +/*##################################################################### */ + + /* + * Register : DX0GCR0 @ 0XFD080700 + + * Calibration Bypass + * PSU_DDR_PHY_DX0GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX0GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX0GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX0GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX0GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX0GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX0GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX0GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX0GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX0GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080700, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX0GCR1 @ 0XFD080704 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX0GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX0GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX0GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX0GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX0GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX0GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX0GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX0GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX0GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX0GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080704, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX0GCR3 @ 0XFD08070C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX0GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX0GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX0GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX0GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX0GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX0GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX0GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX0GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX0GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX0GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX0GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX0GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX0GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX0GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX0GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX0GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX0GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX0GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08070C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX0GCR4 @ 0XFD080710 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX0GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX0GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX0GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX0GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX0GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX0GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX0GCR4_DXREFIEN 0xf + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX0GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ + + /* + * Register : DX0GCR5 @ 0XFD080714 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX0GCR6 @ 0XFD080718 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX1GCR0 @ 0XFD080800 + + * Calibration Bypass + * PSU_DDR_PHY_DX1GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX1GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX1GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX1GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX1GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX1GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX1GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX1GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX1GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX1GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080800, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX1GCR1 @ 0XFD080804 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX1GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX1GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX1GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX1GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX1GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX1GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX1GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX1GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX1GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX1GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080804, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX1GCR3 @ 0XFD08080C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX1GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX1GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX1GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX1GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX1GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX1GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX1GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX1GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX1GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX1GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX1GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX1GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX1GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX1GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX1GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX1GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX1GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX1GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08080C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX1GCR4 @ 0XFD080810 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX1GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX1GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX1GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX1GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX1GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX1GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX1GCR4_DXREFIEN 0xf + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX1GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ + + /* + * Register : DX1GCR5 @ 0XFD080814 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX1GCR6 @ 0XFD080818 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX2GCR0 @ 0XFD080900 + + * Calibration Bypass + * PSU_DDR_PHY_DX2GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX2GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX2GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX2GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX2GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX2GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX2GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX2GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX2GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX2GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080900, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX2GCR1 @ 0XFD080904 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX2GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX2GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX2GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX2GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX2GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX2GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX2GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX2GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX2GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX2GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX2GCR3 @ 0XFD08090C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX2GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX2GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX2GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX2GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX2GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX2GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX2GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX2GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX2GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX2GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX2GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX2GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX2GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX2GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX2GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX2GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX2GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX2GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08090C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX2GCR4 @ 0XFD080910 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX2GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX2GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX2GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX2GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX2GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX2GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX2GCR4_DXREFIEN 0x1 + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX2GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080910, 0xFFFFFFFFU ,0x0E00B004U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B004U); +/*##################################################################### */ + + /* + * Register : DX2GCR5 @ 0XFD080914 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX2GCR6 @ 0XFD080918 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX3GCR0 @ 0XFD080A00 + + * Calibration Bypass + * PSU_DDR_PHY_DX3GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX3GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX3GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX3GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX3GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX3GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX3GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX3GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX3GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX3GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080A00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX3GCR1 @ 0XFD080A04 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX3GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX3GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX3GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX3GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX3GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX3GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX3GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX3GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX3GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX3GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX3GCR3 @ 0XFD080A0C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX3GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX3GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX3GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX3GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX3GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX3GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX3GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX3GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX3GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX3GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX3GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX3GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX3GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX3GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX3GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX3GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX3GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX3GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD080A0C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX3GCR4 @ 0XFD080A10 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX3GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX3GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX3GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX3GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX3GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX3GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX3GCR4_DXREFIEN 0x1 + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX3GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080A10, 0xFFFFFFFFU ,0x0E00B004U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B004U); +/*##################################################################### */ + + /* + * Register : DX3GCR5 @ 0XFD080A14 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX3GCR6 @ 0XFD080A18 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX4GCR0 @ 0XFD080B00 + + * Calibration Bypass + * PSU_DDR_PHY_DX4GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX4GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX4GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX4GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX4GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX4GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX4GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX4GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX4GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX4GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080B00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX4GCR1 @ 0XFD080B04 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX4GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX4GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX4GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX4GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX4GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX4GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX4GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX4GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX4GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX4GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX4GCR2 @ 0XFD080B08 + + * Enables the OE mode values for DQ[7:0] + * PSU_DDR_PHY_DX4GCR2_DXOEMODE 0x0 + + * Enables the TE (ODT) mode values for DQ[7:0] + * PSU_DDR_PHY_DX4GCR2_DXTEMODE 0x0 + + * DATX8 n General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080B08, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DX4GCR3 @ 0XFD080B0C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX4GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX4GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX4GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX4GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX4GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX4GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX4GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX4GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX4GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX4GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX4GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX4GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX4GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX4GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX4GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX4GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX4GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX4GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD080B0C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX4GCR4 @ 0XFD080B10 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX4GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX4GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX4GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX4GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX4GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX4GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX4GCR4_DXREFIEN 0x1 + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX4GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080B10, 0xFFFFFFFFU ,0x0E00B004U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B004U); +/*##################################################################### */ + + /* + * Register : DX4GCR5 @ 0XFD080B14 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX4GCR6 @ 0XFD080B18 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX5GCR0 @ 0XFD080C00 + + * Calibration Bypass + * PSU_DDR_PHY_DX5GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX5GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX5GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX5GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX5GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX5GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX5GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX5GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX5GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX5GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080C00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX5GCR1 @ 0XFD080C04 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX5GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX5GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX5GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX5GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX5GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX5GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX5GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX5GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX5GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX5GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX5GCR2 @ 0XFD080C08 + + * Enables the OE mode values for DQ[7:0] + * PSU_DDR_PHY_DX5GCR2_DXOEMODE 0x0 + + * Enables the TE (ODT) mode values for DQ[7:0] + * PSU_DDR_PHY_DX5GCR2_DXTEMODE 0x0 + + * DATX8 n General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080C08, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DX5GCR3 @ 0XFD080C0C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX5GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX5GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX5GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX5GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX5GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX5GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX5GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX5GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX5GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX5GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX5GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX5GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX5GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX5GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX5GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX5GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX5GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX5GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD080C0C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX5GCR4 @ 0XFD080C10 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX5GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX5GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX5GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX5GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX5GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX5GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX5GCR4_DXREFIEN 0xf + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX5GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ + + /* + * Register : DX5GCR5 @ 0XFD080C14 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX5GCR6 @ 0XFD080C18 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX6GCR0 @ 0XFD080D00 + + * Calibration Bypass + * PSU_DDR_PHY_DX6GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX6GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX6GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX6GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX6GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX6GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX6GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX6GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX6GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX6GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080D00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX6GCR1 @ 0XFD080D04 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX6GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX6GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX6GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX6GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX6GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX6GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX6GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX6GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX6GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX6GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX6GCR2 @ 0XFD080D08 + + * Enables the OE mode values for DQ[7:0] + * PSU_DDR_PHY_DX6GCR2_DXOEMODE 0x0 + + * Enables the TE (ODT) mode values for DQ[7:0] + * PSU_DDR_PHY_DX6GCR2_DXTEMODE 0x0 + + * DATX8 n General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080D08, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DX6GCR3 @ 0XFD080D0C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX6GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX6GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX6GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX6GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX6GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX6GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX6GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX6GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX6GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX6GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX6GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX6GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX6GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX6GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX6GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX6GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX6GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX6GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD080D0C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX6GCR4 @ 0XFD080D10 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX6GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX6GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX6GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX6GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX6GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX6GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX6GCR4_DXREFIEN 0x1 + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX6GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080D10, 0xFFFFFFFFU ,0x0E00B004U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B004U); +/*##################################################################### */ + + /* + * Register : DX6GCR5 @ 0XFD080D14 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX6GCR6 @ 0XFD080D18 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX7GCR0 @ 0XFD080E00 + + * Calibration Bypass + * PSU_DDR_PHY_DX7GCR0_CALBYP 0x0 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX7GCR0_MDLEN 0x1 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX7GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX7GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSNSEPDR 0x0 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSSEPDR 0x0 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX7GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX7GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX7GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX7GCR0_DQSRPD 0x0 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSGPDR 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX7GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX7GCR0_DQSGOE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080E00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ + + /* + * Register : DX7GCR1 @ 0XFD080E04 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX7GCR1_DXPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX7GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX7GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX7GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX7GCR1_OEEN 0x1 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX7GCR1_PDREN 0x1 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX7GCR1_TEEN 0x1 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX7GCR1_DSEN 0x1 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX7GCR1_DMEN 0x1 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX7GCR1_DQEN 0xff + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ + + /* + * Register : DX7GCR2 @ 0XFD080E08 + + * Enables the OE mode values for DQ[7:0] + * PSU_DDR_PHY_DX7GCR2_DXOEMODE 0x0 + + * Enables the TE (ODT) mode values for DQ[7:0] + * PSU_DDR_PHY_DX7GCR2_DXTEMODE 0x0 + + * DATX8 n General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080E08, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DX7GCR3 @ 0XFD080E0C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX7GCR3_RDBVT 0x1 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX7GCR3_WDBVT 0x1 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX7GCR3_RGLVT 0x1 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX7GCR3_RDLVT 0x1 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX7GCR3_WDLVT 0x1 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX7GCR3_WLLVT 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX7GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX7GCR3_DSNOEMODE 0x0 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX7GCR3_DSNTEMODE 0x0 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX7GCR3_DSNPDRMODE 0x0 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX7GCR3_DMOEMODE 0x0 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX7GCR3_DMTEMODE 0x0 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX7GCR3_DMPDRMODE 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX7GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX7GCR3_DSOEMODE 0x0 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX7GCR3_DSTEMODE 0x0 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX7GCR3_DSPDRMODE 0x2 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX7GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD080E0C, 0xFFFFFFFFU ,0x3F000008U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR3_OFFSET, 0xFFFFFFFFU, 0x3F000008U); +/*##################################################################### */ + + /* + * Register : DX7GCR4 @ 0XFD080E10 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX7GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX7GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX7GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX7GCR4_DXREFSEN 0x1 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX7GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX7GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX7GCR4_DXREFIEN 0xf + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX7GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ + + /* + * Register : DX7GCR5 @ 0XFD080E14 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX7GCR6 @ 0XFD080E18 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX8GCR0 @ 0XFD080F00 + + * Calibration Bypass + * PSU_DDR_PHY_DX8GCR0_CALBYP 0x1 + + * Master Delay Line Enable + * PSU_DDR_PHY_DX8GCR0_MDLEN 0x0 + + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX8GCR0_CODTSHFT 0x0 + + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0 + + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX8GCR0_RDDLY 0x8 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_19_14 0x0 + + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSNSEPDR 0x1 + + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSSEPDR 0x1 + + * RTT On Additive Latency + * PSU_DDR_PHY_DX8GCR0_RTTOAL 0x0 + + * RTT Output Hold + * PSU_DDR_PHY_DX8GCR0_RTTOH 0x3 + + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX8GCR0_CPDRSHFT 0x0 + + * DQSR Power Down + * PSU_DDR_PHY_DX8GCR0_DQSRPD 0x1 + + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSGPDR 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_4 0x0 + + * DQSG On-Die Termination + * PSU_DDR_PHY_DX8GCR0_DQSGODT 0x0 + + * DQSG Output Enable + * PSU_DDR_PHY_DX8GCR0_DQSGOE 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080F00, 0xFFFFFFFFU ,0x80803660U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR0_OFFSET, 0xFFFFFFFFU, 0x80803660U); +/*##################################################################### */ + + /* + * Register : DX8GCR1 @ 0XFD080F04 + + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX8GCR1_DXPDRMODE 0x5555 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX8GCR1_RESERVED_15 0x0 + + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX8GCR1_QSNSEL 0x1 + + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX8GCR1_QSSEL 0x1 + + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX8GCR1_OEEN 0x0 + + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX8GCR1_PDREN 0x0 + + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX8GCR1_TEEN 0x0 + + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX8GCR1_DSEN 0x0 + + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX8GCR1_DMEN 0x0 + + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX8GCR1_DQEN 0x0 + + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080F04, 0xFFFFFFFFU ,0x55556000U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR1_OFFSET, 0xFFFFFFFFU, 0x55556000U); +/*##################################################################### */ + + /* + * Register : DX8GCR2 @ 0XFD080F08 + + * Enables the OE mode values for DQ[7:0] + * PSU_DDR_PHY_DX8GCR2_DXOEMODE 0xaaaa + + * Enables the TE (ODT) mode values for DQ[7:0] + * PSU_DDR_PHY_DX8GCR2_DXTEMODE 0xaaaa + + * DATX8 n General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080F08, 0xFFFFFFFFU ,0xAAAAAAAAU) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR2_OFFSET, 0xFFFFFFFFU, 0xAAAAAAAAU); +/*##################################################################### */ + + /* + * Register : DX8GCR3 @ 0XFD080F0C + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR3_RESERVED_31_30 0x0 + + * Read Data BDL VT Compensation + * PSU_DDR_PHY_DX8GCR3_RDBVT 0x0 + + * Write Data BDL VT Compensation + * PSU_DDR_PHY_DX8GCR3_WDBVT 0x0 + + * Read DQS Gating LCDL Delay VT Compensation + * PSU_DDR_PHY_DX8GCR3_RGLVT 0x0 + + * Read DQS LCDL Delay VT Compensation + * PSU_DDR_PHY_DX8GCR3_RDLVT 0x0 + + * Write DQ LCDL Delay VT Compensation + * PSU_DDR_PHY_DX8GCR3_WDLVT 0x0 + + * Write Leveling LCDL Delay VT Compensation + * PSU_DDR_PHY_DX8GCR3_WLLVT 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX8GCR3_RESERVED_23_22 0x0 + + * Enables the OE mode for DQs + * PSU_DDR_PHY_DX8GCR3_DSNOEMODE 0x2 + + * Enables the TE mode for DQS + * PSU_DDR_PHY_DX8GCR3_DSNTEMODE 0x2 + + * Enables the PDR mode for DQS + * PSU_DDR_PHY_DX8GCR3_DSNPDRMODE 0x1 + + * Enables the OE mode values for DM. + * PSU_DDR_PHY_DX8GCR3_DMOEMODE 0x2 + + * Enables the TE mode values for DM. + * PSU_DDR_PHY_DX8GCR3_DMTEMODE 0x2 + + * Enables the PDR mode values for DM. + * PSU_DDR_PHY_DX8GCR3_DMPDRMODE 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX8GCR3_RESERVED_9_8 0x0 + + * Enables the OE mode values for DQS. + * PSU_DDR_PHY_DX8GCR3_DSOEMODE 0x2 + + * Enables the TE mode values for DQS. + * PSU_DDR_PHY_DX8GCR3_DSTEMODE 0x2 + + * Enables the PDR mode values for DQS. + * PSU_DDR_PHY_DX8GCR3_DSPDRMODE 0x1 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX8GCR3_RESERVED_1_0 0x0 + + * DATX8 n General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD080F0C, 0xFFFFFFFFU ,0x0029A4A4U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR3_OFFSET, 0xFFFFFFFFU, 0x0029A4A4U); +/*##################################################################### */ + + /* + * Register : DX8GCR4 @ 0XFD080F10 + + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX8GCR4_RESERVED_31_29 0x0 + + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX8GCR4_DXREFPEN 0x0 + + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX8GCR4_DXREFEEN 0x3 + + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX8GCR4_DXREFSEN 0x0 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR4_RESERVED_24 0x0 + + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE 0x0 + + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX8GCR4_DXREFESEL 0x0 + + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE 0x1 + + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX8GCR4_DXREFSSEL 0x30 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR4_RESERVED_7_6 0x0 + + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX8GCR4_DXREFIEN 0x0 + + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX8GCR4_DXREFIMON 0x0 + + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080F10, 0xFFFFFFFFU ,0x0C00B000U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR4_OFFSET, 0xFFFFFFFFU, 0x0C00B000U); +/*##################################################################### */ + + /* + * Register : DX8GCR5 @ 0XFD080F14 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_31 0x0 + + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_23 0x0 + + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0 + + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0 + + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55 + + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ + + /* + * Register : DX8GCR6 @ 0XFD080F18 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_31_30 0x0 + + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR3 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_23_22 0x0 + + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR2 0x9 + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_15_14 0x0 + + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR1 0x2b + + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_7_6 0x0 + + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR0 0x2b + + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ + + /* + * Register : DX8SL0OSC @ 0XFD081400 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0 + + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2 + + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2 + + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2 + + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0 + + * Loopback Mode + * PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0 + + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0 + + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0 + + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0 + + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1 + + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1 + + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0 + + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3 + + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3 + + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3 + + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf + + * Oscillator Enable + * PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0 + + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ + + /* + * Register : DX8SL0PLLCR0 @ 0XFD081404 + + * PLL Bypass + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLBYP 0x0 + + * PLL Reset + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLRST 0x0 + + * PLL Power Down + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLPD 0x0 + + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL0PLLCR0_RSTOPM 0x0 + + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL0PLLCR0_FRQSEL 0x1 + + * Relock Mode + * PSU_DDR_PHY_DX8SL0PLLCR0_RLOCKM 0x0 + + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL0PLLCR0_CPPC 0x8 + + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL0PLLCR0_CPIC 0x0 + + * Gear Shift + * PSU_DDR_PHY_DX8SL0PLLCR0_GSHIFT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9 0x0 + + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL0PLLCR0_ATOEN 0x0 + + * Analog Test Control + * PSU_DDR_PHY_DX8SL0PLLCR0_ATC 0x0 + + * Digital Test Control + * PSU_DDR_PHY_DX8SL0PLLCR0_DTC 0x0 + + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081404, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ + + /* + * Register : DX8SL0DQSCTL @ 0XFD08141C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25 0x0 + + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22 0x0 + + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE 0x1 + + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX 0x0 + + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD 0x1 + + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15 0x0 + + * QS Counter Enable + * PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN 0x1 + + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10 0x0 + + * Data Slew Rate + * PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3 + + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0 + + * DQS Resistor + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0 + + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ + + /* + * Register : DX8SL0DXCTL2 @ 0XFD08142C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24 0x0 + + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN 0x0 + + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0 + + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0 + + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL0DXCTL2_IOAG 0x0 + + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL0DXCTL2_IOLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13 0x0 + + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH 0xc + + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_RDBI 0x0 + + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_WDBI 0x0 + + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP 0x0 + + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE 0x0 + + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL0DXCTL2_DISRST 0x0 + + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0 + + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ + + /* + * Register : DX8SL0IOCR @ 0XFD081430 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31 0x0 + + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE 0x7 + + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM 0x0 + + * DX IO Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXIOM 0x2 + + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXTXM 0x0 + + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXRXM 0x0 + + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ + + /* + * Register : DX8SL1OSC @ 0XFD081440 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0 + + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2 + + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2 + + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2 + + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0 + + * Loopback Mode + * PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0 + + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0 + + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0 + + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0 + + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1 + + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1 + + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0 + + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3 + + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3 + + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3 + + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf + + * Oscillator Enable + * PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0 + + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ + + /* + * Register : DX8SL1PLLCR0 @ 0XFD081444 + + * PLL Bypass + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLBYP 0x0 + + * PLL Reset + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLRST 0x0 + + * PLL Power Down + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLPD 0x0 + + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL1PLLCR0_RSTOPM 0x0 + + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL1PLLCR0_FRQSEL 0x1 + + * Relock Mode + * PSU_DDR_PHY_DX8SL1PLLCR0_RLOCKM 0x0 + + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL1PLLCR0_CPPC 0x8 + + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL1PLLCR0_CPIC 0x0 + + * Gear Shift + * PSU_DDR_PHY_DX8SL1PLLCR0_GSHIFT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9 0x0 + + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL1PLLCR0_ATOEN 0x0 + + * Analog Test Control + * PSU_DDR_PHY_DX8SL1PLLCR0_ATC 0x0 + + * Digital Test Control + * PSU_DDR_PHY_DX8SL1PLLCR0_DTC 0x0 + + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081444, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ + + /* + * Register : DX8SL1DQSCTL @ 0XFD08145C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25 0x0 + + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22 0x0 + + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE 0x1 + + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX 0x0 + + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD 0x1 + + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15 0x0 + + * QS Counter Enable + * PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN 0x1 + + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10 0x0 + + * Data Slew Rate + * PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3 + + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0 + + * DQS Resistor + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0 + + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ + + /* + * Register : DX8SL1DXCTL2 @ 0XFD08146C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24 0x0 + + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN 0x0 + + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0 + + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0 + + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL1DXCTL2_IOAG 0x0 + + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL1DXCTL2_IOLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13 0x0 + + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH 0xc + + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_RDBI 0x0 + + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_WDBI 0x0 + + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP 0x0 + + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE 0x0 + + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL1DXCTL2_DISRST 0x0 + + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0 + + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ + + /* + * Register : DX8SL1IOCR @ 0XFD081470 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31 0x0 + + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE 0x7 + + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM 0x0 + + * DX IO Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXIOM 0x2 + + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXTXM 0x0 + + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXRXM 0x0 + + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ + + /* + * Register : DX8SL2OSC @ 0XFD081480 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0 + + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2 + + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2 + + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2 + + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0 + + * Loopback Mode + * PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0 + + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0 + + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0 + + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0 + + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1 + + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1 + + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0 + + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3 + + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3 + + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3 + + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf + + * Oscillator Enable + * PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0 + + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ + + /* + * Register : DX8SL2PLLCR0 @ 0XFD081484 + + * PLL Bypass + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLBYP 0x0 + + * PLL Reset + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLRST 0x0 + + * PLL Power Down + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLPD 0x0 + + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL2PLLCR0_RSTOPM 0x0 + + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL2PLLCR0_FRQSEL 0x1 + + * Relock Mode + * PSU_DDR_PHY_DX8SL2PLLCR0_RLOCKM 0x0 + + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL2PLLCR0_CPPC 0x8 + + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL2PLLCR0_CPIC 0x0 + + * Gear Shift + * PSU_DDR_PHY_DX8SL2PLLCR0_GSHIFT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9 0x0 + + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL2PLLCR0_ATOEN 0x0 + + * Analog Test Control + * PSU_DDR_PHY_DX8SL2PLLCR0_ATC 0x0 + + * Digital Test Control + * PSU_DDR_PHY_DX8SL2PLLCR0_DTC 0x0 + + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081484, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ + + /* + * Register : DX8SL2DQSCTL @ 0XFD08149C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0 + + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0 + + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1 + + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX 0x0 + + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD 0x1 + + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15 0x0 + + * QS Counter Enable + * PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN 0x1 + + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10 0x0 + + * Data Slew Rate + * PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3 + + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0 + + * DQS Resistor + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0 + + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ + + /* + * Register : DX8SL2DXCTL2 @ 0XFD0814AC + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24 0x0 + + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN 0x0 + + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0 + + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0 + + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL2DXCTL2_IOAG 0x0 + + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL2DXCTL2_IOLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13 0x0 + + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH 0xc + + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_RDBI 0x0 + + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_WDBI 0x0 + + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP 0x0 + + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE 0x0 + + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL2DXCTL2_DISRST 0x0 + + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0 + + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ + + /* + * Register : DX8SL2IOCR @ 0XFD0814B0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31 0x0 + + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE 0x7 + + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM 0x0 + + * DX IO Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXIOM 0x2 + + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXTXM 0x0 + + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXRXM 0x0 + + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ + + /* + * Register : DX8SL3OSC @ 0XFD0814C0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0 + + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2 + + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2 + + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2 + + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0 + + * Loopback Mode + * PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0 + + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0 + + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0 + + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0 + + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1 + + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1 + + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0 + + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3 + + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3 + + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3 + + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf + + * Oscillator Enable + * PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0 + + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ + + /* + * Register : DX8SL3PLLCR0 @ 0XFD0814C4 + + * PLL Bypass + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLBYP 0x0 + + * PLL Reset + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLRST 0x0 + + * PLL Power Down + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLPD 0x0 + + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL3PLLCR0_RSTOPM 0x0 + + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL3PLLCR0_FRQSEL 0x1 + + * Relock Mode + * PSU_DDR_PHY_DX8SL3PLLCR0_RLOCKM 0x0 + + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL3PLLCR0_CPPC 0x8 + + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL3PLLCR0_CPIC 0x0 + + * Gear Shift + * PSU_DDR_PHY_DX8SL3PLLCR0_GSHIFT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9 0x0 + + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL3PLLCR0_ATOEN 0x0 + + * Analog Test Control + * PSU_DDR_PHY_DX8SL3PLLCR0_ATC 0x0 + + * Digital Test Control + * PSU_DDR_PHY_DX8SL3PLLCR0_DTC 0x0 + + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD0814C4, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ + + /* + * Register : DX8SL3DQSCTL @ 0XFD0814DC + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25 0x0 + + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22 0x0 + + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE 0x1 + + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX 0x0 + + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD 0x1 + + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15 0x0 + + * QS Counter Enable + * PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN 0x1 + + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10 0x0 + + * Data Slew Rate + * PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3 + + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0 + + * DQS Resistor + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0 + + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ + + /* + * Register : DX8SL3DXCTL2 @ 0XFD0814EC + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24 0x0 + + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN 0x0 + + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0 + + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0 + + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL3DXCTL2_IOAG 0x0 + + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL3DXCTL2_IOLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13 0x0 + + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH 0xc + + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_RDBI 0x0 + + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_WDBI 0x0 + + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP 0x0 + + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE 0x0 + + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL3DXCTL2_DISRST 0x0 + + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0 + + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ + + /* + * Register : DX8SL3IOCR @ 0XFD0814F0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31 0x0 + + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE 0x7 + + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM 0x0 + + * DX IO Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXIOM 0x2 + + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXTXM 0x0 + + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXRXM 0x0 + + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ + + /* + * Register : DX8SL4OSC @ 0XFD081500 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0 + + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x1 + + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x1 + + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x1 + + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0 + + * Loopback Mode + * PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0 + + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0 + + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0 + + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0 + + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1 + + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1 + + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0 + + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3 + + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3 + + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3 + + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3 + + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf + + * Oscillator Enable + * PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0 + + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x15019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4OSC_OFFSET, 0xFFFFFFFFU, 0x15019FFEU); +/*##################################################################### */ + + /* + * Register : DX8SL4PLLCR0 @ 0XFD081504 + + * PLL Bypass + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLBYP 0x0 + + * PLL Reset + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLRST 0x0 + + * PLL Power Down + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLPD 0x1 + + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL4PLLCR0_RSTOPM 0x0 + + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL4PLLCR0_FRQSEL 0x1 + + * Relock Mode + * PSU_DDR_PHY_DX8SL4PLLCR0_RLOCKM 0x0 + + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL4PLLCR0_CPPC 0x8 + + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL4PLLCR0_CPIC 0x0 + + * Gear Shift + * PSU_DDR_PHY_DX8SL4PLLCR0_GSHIFT 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9 0x0 + + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL4PLLCR0_ATOEN 0x0 + + * Analog Test Control + * PSU_DDR_PHY_DX8SL4PLLCR0_ATC 0x0 + + * Digital Test Control + * PSU_DDR_PHY_DX8SL4PLLCR0_DTC 0x0 + + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081504, 0xFFFFFFFFU ,0x21100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x21100000U); +/*##################################################################### */ + + /* + * Register : DX8SL4DQSCTL @ 0XFD08151C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25 0x0 + + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22 0x0 + + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE 0x1 + + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX 0x0 + + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD 0x1 + + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15 0x0 + + * QS Counter Enable + * PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN 0x1 + + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10 0x0 + + * Data Slew Rate + * PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3 + + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0 + + * DQS Resistor + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0 + + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01266300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01266300U); +/*##################################################################### */ + + /* + * Register : DX8SL4DXCTL2 @ 0XFD08152C + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24 0x0 + + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN 0x0 + + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0 + + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0 + + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL4DXCTL2_IOAG 0x0 + + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL4DXCTL2_IOLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13 0x0 + + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH 0xc + + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_RDBI 0x0 + + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_WDBI 0x0 + + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP 0x0 + + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE 0x0 + + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL4DXCTL2_DISRST 0x0 + + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0 + + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ + + /* + * Register : DX8SL4IOCR @ 0XFD081530 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31 0x0 + + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE 0x7 + + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM 0x0 + + * DX IO Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXIOM 0x1 + + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXTXM 0x0 + + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXRXM 0x0 + + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70400000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4IOCR_OFFSET, 0xFFFFFFFFU, 0x70400000U); +/*##################################################################### */ + + /* + * Register : DX8SLbDQSCTL @ 0XFD0817DC + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25 0x0 + + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22 0x0 + + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE 0x1 + + * DQS Gate Extension + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX 0x0 + + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD 0x1 + + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD 0x1 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15 0x0 + + * QS Counter Enable + * PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN 0x1 + + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM 0x0 + + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10 0x0 + + * Data Slew Rate + * PSU_DDR_PHY_DX8SLBDQSCTL_DXSR 0x3 + + * DQS# Resistor + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES 0xc + + * DQS Resistor + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES 0x4 + + * DATX8 0-8 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U) + */ + PSU_Mask_Write(DDR_PHY_DX8SLBDQSCTL_OFFSET, + 0xFFFFFFFFU, 0x012643C4U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_ddr_qos_init_data(void) +{ + /* + * AFI INTERCONNECT QOS CONFIGURATION + */ + /* + * Register : AFIFM_RDQoS @ 0XFD360008 + + * Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM0_AFIFM_RDQOS_VALUE 0 + + * QoS Read Channel Register + * (OFFSET, MASK, VALUE) (0XFD360008, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM0_AFIFM_RDQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRQoS @ 0XFD36001C + + * Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM0_AFIFM_WRQOS_VALUE 0 + + * QoS Write Channel Register + * (OFFSET, MASK, VALUE) (0XFD36001C, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM0_AFIFM_WRQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_RDQoS @ 0XFD370008 + + * Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM1_AFIFM_RDQOS_VALUE 0 + + * QoS Read Channel Register + * (OFFSET, MASK, VALUE) (0XFD370008, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM1_AFIFM_RDQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRQoS @ 0XFD37001C + + * Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM1_AFIFM_WRQOS_VALUE 0 + + * QoS Write Channel Register + * (OFFSET, MASK, VALUE) (0XFD37001C, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM1_AFIFM_WRQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_RDQoS @ 0XFD380008 + + * Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM2_AFIFM_RDQOS_VALUE 0 + + * QoS Read Channel Register + * (OFFSET, MASK, VALUE) (0XFD380008, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM2_AFIFM_RDQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRQoS @ 0XFD38001C + + * Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM2_AFIFM_WRQOS_VALUE 0 + + * QoS Write Channel Register + * (OFFSET, MASK, VALUE) (0XFD38001C, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM2_AFIFM_WRQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_RDQoS @ 0XFD390008 + + * Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM3_AFIFM_RDQOS_VALUE 0 + + * QoS Read Channel Register + * (OFFSET, MASK, VALUE) (0XFD390008, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM3_AFIFM_RDQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRQoS @ 0XFD39001C + + * Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM3_AFIFM_WRQOS_VALUE 0 + + * QoS Write Channel Register + * (OFFSET, MASK, VALUE) (0XFD39001C, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM3_AFIFM_WRQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_RDQoS @ 0XFD3A0008 + + * Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM4_AFIFM_RDQOS_VALUE 0 + + * QoS Read Channel Register + * (OFFSET, MASK, VALUE) (0XFD3A0008, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM4_AFIFM_RDQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRQoS @ 0XFD3A001C + + * Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM4_AFIFM_WRQOS_VALUE 0 + + * QoS Write Channel Register + * (OFFSET, MASK, VALUE) (0XFD3A001C, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM4_AFIFM_WRQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_RDQoS @ 0XFD3B0008 + + * Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM5_AFIFM_RDQOS_VALUE 0 + + * QoS Read Channel Register + * (OFFSET, MASK, VALUE) (0XFD3B0008, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM5_AFIFM_RDQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRQoS @ 0XFD3B001C + + * Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM5_AFIFM_WRQOS_VALUE 0 + + * QoS Write Channel Register + * (OFFSET, MASK, VALUE) (0XFD3B001C, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM5_AFIFM_WRQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_RDQoS @ 0XFF9B0008 + + * Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM6_AFIFM_RDQOS_VALUE 0 + + * QoS Read Channel Register + * (OFFSET, MASK, VALUE) (0XFF9B0008, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM6_AFIFM_RDQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRQoS @ 0XFF9B001C + + * Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority + * PSU_AFIFM6_AFIFM_WRQOS_VALUE 0 + + * QoS Write Channel Register + * (OFFSET, MASK, VALUE) (0XFF9B001C, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(AFIFM6_AFIFM_WRQOS_OFFSET, 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_mio_init_data(void) +{ + /* + * MIO PROGRAMMING + */ + /* + * Register : MIO_PIN_0 @ 0XFF180000 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- + * (QSPI Clock) + * PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0 + + * Configures MIO Pin 0 peripheral interface mapping. S + * (OFFSET, MASK, VALUE) (0XFF180000, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_0_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_1 @ 0XFF180004 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q + * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou + * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) + * PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0 + + * Configures MIO Pin 1 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180004, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_1_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_2 @ 0XFF180008 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI + * Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I + * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0 + + * Configures MIO Pin 2 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180008, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_2_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_3 @ 0XFF18000C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI + * Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0 + + * Configures MIO Pin 3 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18000C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_3_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_4 @ 0XFF180010 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- ( + * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0 + + * Configures MIO Pin 4 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180010, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_4_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_5 @ 0XFF180014 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- + * (QSPI Slave Select) + * PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0 + + * Configures MIO Pin 5 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180014, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_5_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_6 @ 0XFF180018 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l + * pbk- (QSPI Clock to be fed-back) + * PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s + * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT + * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, + * Output, tracedq[4]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0 + + * Configures MIO Pin 6 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180018, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_6_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_7 @ 0XFF18001C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_ + * upper- (QSPI Slave Select upper) + * PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma + * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua + * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t + * racedq[5]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0 + + * Configures MIO Pin 7 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18001C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_7_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_8 @ 0XFF180020 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste + * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_ + * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra + * ce Port Databus) + * PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0 + + * Configures MIO Pin 8 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180020, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_8_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_9 @ 0XFF180024 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S + * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, + * Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA + * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data + * bus) + * PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0 + + * Configures MIO Pin 9 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180024, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_9_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_10 @ 0XFF180028 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 10]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0 + + * Configures MIO Pin 10 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180028, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_10_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_11 @ 0XFF18002C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 11]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0 + + * Configures MIO Pin 11 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18002C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_11_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_12 @ 0XFF180030 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_ + * upper- (QSPI Upper Clock) + * PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) + * PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 12]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT + * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_ + * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O + * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace + * dq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0 + + * Configures MIO Pin 12 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180030, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_12_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_13 @ 0XFF180034 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, + * test_scan_out[13]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA + * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, + * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR + * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data + * bus) + * PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0 + + * Configures MIO Pin 13 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180034, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_13_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_14 @ 0XFF180038 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND + * Command Latch Enable) + * PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, + * test_scan_out[14]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT + * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, + * Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver + * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2 + + * Configures MIO Pin 14 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180038, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_14_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_15 @ 0XFF18003C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND + * Address Latch Enable) + * PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, + * test_scan_out[15]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT + * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp + * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou + * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria + * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2 + + * Configures MIO Pin 15 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18003C, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_15_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_16 @ 0XFF180040 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, + * test_scan_out[16]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2 + + * Configures MIO Pin 16 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180040, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_16_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_17 @ 0XFF180044 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, + * test_scan_out[17]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2 + + * Configures MIO Pin 17 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180044, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_17_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_18 @ 0XFF180048 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, + * test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6 + + * Configures MIO Pin 18 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180048, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_18_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_19 @ 0XFF18004C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, + * test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6 + + * Configures MIO Pin 19 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18004C, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_19_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_20 @ 0XFF180050 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, + * test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua + * 1_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6 + + * Configures MIO Pin 20 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180050, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_20_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_21 @ 0XFF180054 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes + * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t + * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E + * xt Tamper) + * PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc + * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- ( + * UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6 + + * Configures MIO Pin 21 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180054, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_21_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_22 @ 0XFF180058 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN + * D Write Enable) + * PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = + * test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c + * su_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed + * PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0 + + * Configures MIO Pin 22 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180058, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_22_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_23 @ 0XFF18005C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po + * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp + * ut, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0 + + * Configures MIO Pin 23 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18005C, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_23_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_24 @ 0XFF180060 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test + * Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= + * csu, Input, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N + * ot Used + * PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1 + + * Configures MIO Pin 24 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180060, 0x000000FEU ,0x00000020U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_24_OFFSET, 0x000000FEU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_25 @ 0XFF180064 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN + * D Read Enable) + * PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]- + * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port + * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou + * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in + * put) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1 + + * Configures MIO Pin 25 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180064, 0x000000FEU ,0x00000020U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_25_OFFSET, 0x000000FEU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_26 @ 0XFF180068 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0 + + * Configures MIO Pin 26 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_26_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_27 @ 0XFF18006C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0 + + * Configures MIO Pin 27 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_27_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_28 @ 0XFF180070 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0 + + * Configures MIO Pin 28 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_28_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_29 @ 0XFF180074 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, + * spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0 + + * Configures MIO Pin 29 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_29_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_30 @ 0XFF180078 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0 + * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock + * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, + * tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0 + + * Configures MIO Pin 30 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_30_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_31 @ 0XFF18007C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT + * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp + * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0 + + * Configures MIO Pin 31 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18007C, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_31_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_32 @ 0XFF180080 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) + * PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t + * race, Output, tracedq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0 + + * Configures MIO Pin 32 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180080, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_32_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_33 @ 0XFF180084 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas + * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1 + * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq + * [11]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0 + + * Configures MIO Pin 33 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180084, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_33_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_38 @ 0XFF180098 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA + * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s + * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In + * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- + * (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0 + + * Configures MIO Pin 38 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180098, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_38_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_39 @ 0XFF18009C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b + * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT + * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, + * Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U + * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port + * Control Signal) + * PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0 + + * Configures MIO Pin 39 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_39_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_40 @ 0XFF1800A0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1 + * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[ + * 5]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ + * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3 + * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi + * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0 + + * Configures MIO Pin 40 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_40_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_41 @ 0XFF1800A4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[6]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA + * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu + * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out + * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp + * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0 + + * Configures MIO Pin 41 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_41_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_42 @ 0XFF1800A8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[7]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp + * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0 + + * Configures MIO Pin 42 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_42_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_43 @ 0XFF1800AC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) + * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0 + + * Configures MIO Pin 43 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_43_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_44 @ 0XFF1800B0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4 + * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0 + + * Configures MIO Pin 44 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_44_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_45 @ 0XFF1800B4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0 + + * Configures MIO Pin 45 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_45_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_46 @ 0XFF1800B8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0 + + * Configures MIO Pin 46 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_46_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_47 @ 0XFF1800BC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste + * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt + * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0 + + * Configures MIO Pin 47 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800BC, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_47_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_48 @ 0XFF1800C0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us + * ed + * PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0 + + * Configures MIO Pin 48 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_48_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_49 @ 0XFF1800C4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd + * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0 + + * Configures MIO Pin 49 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_49_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_50 @ 0XFF1800C8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) + * PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind + * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= + * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece + * iver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0 + + * Configures MIO Pin 50 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_50_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_51 @ 0XFF1800CC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) + * PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi + * o1_clk_out- (SDSDIO clock) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat + * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa + * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter + * serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0 + + * Configures MIO Pin 51 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800CC, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_51_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_52 @ 0XFF1800D0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i + * n- (ULPI Clock) + * PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0 + + * Configures MIO Pin 52 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_52_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_53 @ 0XFF1800D4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- + * (Data bus direction control) + * PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou + * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) + * PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0 + + * Configures MIO Pin 53 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_53_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_54 @ 0XFF1800D8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I + * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0 + + * Configures MIO Pin 54 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_54_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_55 @ 0XFF1800DC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- + * (Data flow control signal from the PHY) + * PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0 + + * Configures MIO Pin 55 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_55_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_56 @ 0XFF1800E0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0 + + * Configures MIO Pin 56 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_56_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_57 @ 0XFF1800E4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0 + + * Configures MIO Pin 57 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_57_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_58 @ 0XFF1800E8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- + * (Asserted to end or interrupt transfers) + * PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0 + + * Configures MIO Pin 58 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_58_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_59 @ 0XFF1800EC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0 + + * Configures MIO Pin 59 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_59_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_60 @ 0XFF1800F0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0 + + * Configures MIO Pin 60 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_60_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_61 @ 0XFF1800F4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, + * spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0 + + * Configures MIO Pin 61 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_61_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_62 @ 0XFF1800F8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0 + + * Configures MIO Pin 62 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_62_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_63 @ 0XFF1800FC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0 + + * Configures MIO Pin 63 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_63_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_64 @ 0XFF180100 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i + * n- (ULPI Clock) + * PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4 + * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * trace, Output, tracedq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0 + + * Configures MIO Pin 64 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180100, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_64_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_65 @ 0XFF180104 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- + * (Data bus direction control) + * PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace + * dq[11]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0 + + * Configures MIO Pin 65 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180104, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_65_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_66 @ 0XFF180108 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not + * Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace + * Port Databus) + * PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0 + + * Configures MIO Pin 66 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180108, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_66_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_67 @ 0XFF18010C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- + * (Data flow control signal from the PHY) + * PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N + * ot Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste + * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt + * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace + * Port Databus) + * PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0 + + * Configures MIO Pin 67 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18010C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_67_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_68 @ 0XFF180110 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N + * ot Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0 + + * Configures MIO Pin 68 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180110, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_68_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_69 @ 0XFF180114 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0 + + * Configures MIO Pin 69 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180114, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_69_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_70 @ 0XFF180118 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- + * (Asserted to end or interrupt transfers) + * PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed + * PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0 + + * Configures MIO Pin 70 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180118, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_70_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_71 @ 0XFF18011C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0 + + * Configures MIO Pin 71 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18011C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_71_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_72 @ 0XFF180120 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri + * al output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0 + + * Configures MIO Pin 72 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180120, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_72_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_73 @ 0XFF180124 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not + * Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0 + + * Configures MIO Pin 73 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180124, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_73_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_74 @ 0XFF180128 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[3]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- ( + * UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0 + + * Configures MIO Pin 74 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180128, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_74_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_75 @ 0XFF18012C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1 + * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t + * xd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0 + + * Configures MIO Pin 75 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18012C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_75_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_76 @ 0XFF180130 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO + * clock) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI + * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2 + * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6 + + * Configures MIO Pin 76 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180130, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_76_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_77 @ 0XFF180134 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio + * 1_cd_n- (SD card detect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M + * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, + * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5 + * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou + * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp + * ut, gem3_mdio_out- (MDIO Data) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6 + + * Configures MIO Pin 77 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180134, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_77_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_MST_TRI0 @ 0XFF180204 + + * Master Tri-state Enable for pin 0, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI 0 + + * Master Tri-state Enable for pin 1, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI 0 + + * Master Tri-state Enable for pin 2, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI 0 + + * Master Tri-state Enable for pin 3, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI 0 + + * Master Tri-state Enable for pin 4, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI 0 + + * Master Tri-state Enable for pin 5, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI 0 + + * Master Tri-state Enable for pin 6, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI 0 + + * Master Tri-state Enable for pin 7, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI 0 + + * Master Tri-state Enable for pin 8, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI 0 + + * Master Tri-state Enable for pin 9, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI 0 + + * Master Tri-state Enable for pin 10, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI 0 + + * Master Tri-state Enable for pin 11, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI 0 + + * Master Tri-state Enable for pin 12, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI 0 + + * Master Tri-state Enable for pin 13, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI 0 + + * Master Tri-state Enable for pin 14, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI 0 + + * Master Tri-state Enable for pin 15, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI 0 + + * Master Tri-state Enable for pin 16, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI 0 + + * Master Tri-state Enable for pin 17, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI 0 + + * Master Tri-state Enable for pin 18, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI 1 + + * Master Tri-state Enable for pin 19, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI 0 + + * Master Tri-state Enable for pin 20, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI 0 + + * Master Tri-state Enable for pin 21, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI 1 + + * Master Tri-state Enable for pin 22, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI 0 + + * Master Tri-state Enable for pin 23, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI 0 + + * Master Tri-state Enable for pin 24, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI 0 + + * Master Tri-state Enable for pin 25, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1 + + * Master Tri-state Enable for pin 26, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0 + + * Master Tri-state Enable for pin 27, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0 + + * Master Tri-state Enable for pin 28, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1 + + * Master Tri-state Enable for pin 29, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0 + + * Master Tri-state Enable for pin 30, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1 + + * Master Tri-state Enable for pin 31, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0 + + * MIO pin Tri-state Enables, 31:0 + * (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI0_OFFSET, + 0xFFFFFFFFU, 0x52240000U); +/*##################################################################### */ + + /* + * Register : MIO_MST_TRI1 @ 0XFF180208 + + * Master Tri-state Enable for pin 32, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI 0 + + * Master Tri-state Enable for pin 33, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI 0 + + * Master Tri-state Enable for pin 34, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI 0 + + * Master Tri-state Enable for pin 35, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI 0 + + * Master Tri-state Enable for pin 36, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI 0 + + * Master Tri-state Enable for pin 37, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI 0 + + * Master Tri-state Enable for pin 38, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI 0 + + * Master Tri-state Enable for pin 39, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI 0 + + * Master Tri-state Enable for pin 40, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI 0 + + * Master Tri-state Enable for pin 41, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI 0 + + * Master Tri-state Enable for pin 42, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI 0 + + * Master Tri-state Enable for pin 43, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI 0 + + * Master Tri-state Enable for pin 44, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI 1 + + * Master Tri-state Enable for pin 45, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI 1 + + * Master Tri-state Enable for pin 46, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI 0 + + * Master Tri-state Enable for pin 47, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI 0 + + * Master Tri-state Enable for pin 48, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI 0 + + * Master Tri-state Enable for pin 49, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI 0 + + * Master Tri-state Enable for pin 50, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI 0 + + * Master Tri-state Enable for pin 51, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0 + + * Master Tri-state Enable for pin 52, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 1 + + * Master Tri-state Enable for pin 53, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 1 + + * Master Tri-state Enable for pin 54, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0 + + * Master Tri-state Enable for pin 55, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 1 + + * Master Tri-state Enable for pin 56, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0 + + * Master Tri-state Enable for pin 57, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0 + + * Master Tri-state Enable for pin 58, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0 + + * Master Tri-state Enable for pin 59, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0 + + * Master Tri-state Enable for pin 60, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0 + + * Master Tri-state Enable for pin 61, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0 + + * Master Tri-state Enable for pin 62, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0 + + * Master Tri-state Enable for pin 63, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0 + + * MIO pin Tri-state Enables, 63:32 + * (OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00B03000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI1_OFFSET, + 0xFFFFFFFFU, 0x00B03000U); +/*##################################################################### */ + + /* + * Register : MIO_MST_TRI2 @ 0XFF18020C + + * Master Tri-state Enable for pin 64, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI 0 + + * Master Tri-state Enable for pin 65, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI 0 + + * Master Tri-state Enable for pin 66, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI 0 + + * Master Tri-state Enable for pin 67, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI 0 + + * Master Tri-state Enable for pin 68, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI 0 + + * Master Tri-state Enable for pin 69, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI 0 + + * Master Tri-state Enable for pin 70, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI 1 + + * Master Tri-state Enable for pin 71, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI 1 + + * Master Tri-state Enable for pin 72, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI 1 + + * Master Tri-state Enable for pin 73, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI 1 + + * Master Tri-state Enable for pin 74, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI 1 + + * Master Tri-state Enable for pin 75, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI 1 + + * Master Tri-state Enable for pin 76, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI 0 + + * Master Tri-state Enable for pin 77, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI 0 + + * MIO pin Tri-state Enables, 77:64 + * (OFFSET, MASK, VALUE) (0XFF18020C, 0x00003FFFU ,0x00000FC0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI2_OFFSET, + 0x00003FFFU, 0x00000FC0U); +/*##################################################################### */ + + /* + * Register : bank0_ctrl0 @ 0XFF180138 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25 1 + + * Drive0 control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl1 @ 0XFF18013C + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl3 @ 0XFF180140 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25 1 + + * Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180140, 0x03FFFFFFU ,0x02E7EF1EU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL3_OFFSET, + 0x03FFFFFFU, 0x02E7EF1EU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl4 @ 0XFF180144 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank0_pull_enable is set, this selects pull up or pull down for + * MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl5 @ 0XFF180148 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank0_pullupdown to selects pull up or pull d + * own for MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl6 @ 0XFF18014C + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 + + * Slew rate control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF18014C, 0x03FFFFFFU ,0x01DBFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL6_OFFSET, + 0x03FFFFFFU, 0x01DBFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl0 @ 0XFF180154 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25 1 + + * Drive0 control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl1 @ 0XFF180158 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl3 @ 0XFF18015C + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25 0 + + * Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF18015C, 0x03FFFFFFU ,0x01FDF015U) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL3_OFFSET, + 0x03FFFFFFU, 0x01FDF015U); +/*##################################################################### */ + + /* + * Register : bank1_ctrl4 @ 0XFF180160 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank1_pull_enable is set, this selects pull up or pull down for + * MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl5 @ 0XFF180164 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank1_pullupdown to selects pull up or pull d + * own for MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl6 @ 0XFF180168 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25 1 + + * Slew rate control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180168, 0x03FFFFFFU ,0x03F3FFEBU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL6_OFFSET, + 0x03FFFFFFU, 0x03F3FFEBU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl0 @ 0XFF180170 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25 1 + + * Drive0 control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl1 @ 0XFF180174 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl3 @ 0XFF180178 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25 1 + + * Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180178, 0x03FFFFFFU ,0x02FC0FBFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL3_OFFSET, + 0x03FFFFFFU, 0x02FC0FBFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl4 @ 0XFF18017C + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank2_pull_enable is set, this selects pull up or pull down for + * MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl5 @ 0XFF180180 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank2_pullupdown to selects pull up or pull d + * own for MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl6 @ 0XFF180184 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25 1 + + * Slew rate control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180184, 0x03FFFFFFU ,0x0303FFF4U) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL6_OFFSET, + 0x03FFFFFFU, 0x0303FFF4U); +/*##################################################################### */ + + /* + * LOOPBACK + */ + /* + * Register : MIO_LOOPBACK @ 0XFF180200 + + * I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 + * = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs + * . + * PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0 + + * CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 + * = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. + * PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0 + + * UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. + * 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 + * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD + * and RI not used. + * PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0 + + * SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 + * = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs + * . The other SPI core will appear on the LS Slave Select. + * PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0 + + * Loopback function within MIO + * (OFFSET, MASK, VALUE) (0XFF180200, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_LOOPBACK_OFFSET, + 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_peripherals_pre_init_data(void) +{ + /* + * SYSMON CLOCK PRESET TO IOPLL AT 1500 MHZ FROM PBR TO MAKE AMS CLOCK UNDE + * R RANGE + */ + /* + * Register : AMS_REF_CTRL @ 0XFF5E0108 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 1 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 35 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 2 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_AMS_REF_CTRL_CLKACT 1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01012302U) + */ + PSU_Mask_Write(CRL_APB_AMS_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01012302U); +/*##################################################################### */ + + /* + * PUT QSPI IN RESET STATE + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 1 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_peripherals_init_data(void) +{ + /* + * COHERENCY + */ + /* + * FPD RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0 + + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0 + + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0 + + * FPD WDT reset + * PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET 0 + + * GDMA block level reset + * PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET 0 + + * Pixel Processor (submodule of GPU) block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET 0 + + * Pixel Processor (submodule of GPU) block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET 0 + + * GPU block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_RESET 0 + + * GT block level reset + * PSU_CRF_APB_RST_FPD_TOP_GT_RESET 0 + + * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000F807EU, 0x00000000U); +/*##################################################################### */ + + /* + * RESET BLOCKS + */ + /* + * TIMESTAMP + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_IOU_CC_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_ADMA_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x001A0000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x001A0000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * Reset entire full power domain. + * PSU_CRL_APB_RST_LPD_TOP_FPD_RESET 0 + + * LPD SWDT + * PSU_CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET 0 + + * Sysmonitor reset + * PSU_CRL_APB_RST_LPD_TOP_SYSMON_RESET 0 + + * Real Time Clock reset + * PSU_CRL_APB_RST_LPD_TOP_RTC_RESET 0 + + * APM reset + * PSU_CRL_APB_RST_LPD_TOP_APM_RESET 0 + + * IPI reset + * PSU_CRL_APB_RST_LPD_TOP_IPI_RESET 0 + + * reset entire RPU power island + * PSU_CRL_APB_RST_LPD_TOP_RPU_PGE_RESET 0 + + * reset ocm + * PSU_CRL_APB_RST_LPD_TOP_OCM_RESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x0093C018U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x0093C018U, 0x00000000U); +/*##################################################################### */ + + /* + * ENET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 + + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0 + + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * QSPI + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * QSPI TAP DELAY + */ + /* + * Register : IOU_TAPDLY_BYPASS @ 0XFF180390 + + * 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa + * ss the Tap delay on the Rx clock signal of LQSPI + * PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 0 + + * IOU tap delay bypass for the LQSPI and NAND controllers + * (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET, + 0x00000004U, 0x00000000U); +/*##################################################################### */ + + /* + * NAND + */ + /* + * USB RESET + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000400U, 0x00000000U); +/*##################################################################### */ + + /* + * SD + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000040U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CTRL_REG_SD @ 0XFF180310 + + * SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled + * PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL 0 + + * SD eMMC selection + * (OFFSET, MASK, VALUE) (0XFF180310, 0x00008000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_CTRL_REG_SD_OFFSET, + 0x00008000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SD_CONFIG_REG2 @ 0XFF180320 + + * Should be set based on the final product usage 00 - Removable SCard Slot + * 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0 + + * 8-bit Support for Embedded Device 1: The Core supports 8-bit Interface 0 + * : Supports only 4-bit SD Interface + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_8BIT 1 + + * 1.8V Support 1: 1.8V supported 0: 1.8V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 1 + + * 3.0V Support 1: 3.0V supported 0: 3.0V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0 + + * 3.3V Support 1: 3.3V supported 0: 3.3V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1 + + * SD Config Register 2 + * (OFFSET, MASK, VALUE) (0XFF180320, 0x33840000U ,0x02840000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG2_OFFSET, + 0x33840000U, 0x02840000U); +/*##################################################################### */ + + /* + * SD1 BASE CLOCK + */ + /* + * Register : SD_CONFIG_REG1 @ 0XFF18031C + + * Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. + * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc8 + + * Configures the Number of Taps (Phases) of the rxclk_in that is supported + * . + * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT 0x28 + + * SD Config Register 1 + * (OFFSET, MASK, VALUE) (0XFF18031C, 0x7FFE0000U ,0x64500000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG1_OFFSET, + 0x7FFE0000U, 0x64500000U); +/*##################################################################### */ + + /* + * Register : SD_DLL_CTRL @ 0XFF180358 + + * Reserved. + * PSU_IOU_SLCR_SD_DLL_CTRL_RESERVED 1 + + * SDIO status register + * (OFFSET, MASK, VALUE) (0XFF180358, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_SD_DLL_CTRL_OFFSET, + 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * SD1 RETUNER + */ + /* + * Register : SD_CONFIG_REG3 @ 0XFF180324 + + * This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S + * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other + * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n + * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved + * PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0 + + * SD Config Register 3 + * (OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG3_OFFSET, + 0x03C00000U, 0x00000000U); +/*##################################################################### */ + + /* + * CAN + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000100U, 0x00000000U); +/*##################################################################### */ + + /* + * I2C + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000600U, 0x00000000U); +/*##################################################################### */ + + /* + * SWDT + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00008000U, 0x00000000U); +/*##################################################################### */ + + /* + * SPI + */ + /* + * TTC + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00007800U, 0x00000000U); +/*##################################################################### */ + + /* + * UART + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000006U, 0x00000000U); +/*##################################################################### */ + + /* + * UART BAUD RATE + */ + /* + * Register : Baud_rate_divider_reg0 @ 0XFF000034 + + * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate + * PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV 0x6 + + * Baud Rate Divider Register + * (OFFSET, MASK, VALUE) (0XFF000034, 0x000000FFU ,0x00000006U) + */ + PSU_Mask_Write(UART0_BAUD_RATE_DIVIDER_REG0_OFFSET, + 0x000000FFU, 0x00000006U); +/*##################################################################### */ + + /* + * Register : Baud_rate_gen_reg0 @ 0XFF000018 + + * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + * PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x7c + + * Baud Rate Generator Register. + * (OFFSET, MASK, VALUE) (0XFF000018, 0x0000FFFFU ,0x0000007CU) + */ + PSU_Mask_Write(UART0_BAUD_RATE_GEN_REG0_OFFSET, + 0x0000FFFFU, 0x0000007CU); +/*##################################################################### */ + + /* + * Register : Control_reg0 @ 0XFF000000 + + * Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. + * PSU_UART0_CONTROL_REG0_STPBRK 0x0 + + * Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. + * PSU_UART0_CONTROL_REG0_STTBRK 0x0 + + * Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. + * PSU_UART0_CONTROL_REG0_RSTTO 0x0 + + * Transmit disable: 0: enable transmitter 1: disable transmitter + * PSU_UART0_CONTROL_REG0_TXDIS 0x0 + + * Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. + * PSU_UART0_CONTROL_REG0_TXEN 0x1 + + * Receive disable: 0: enable 1: disable, regardless of the value of RXEN + * PSU_UART0_CONTROL_REG0_RXDIS 0x0 + + * Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. + * PSU_UART0_CONTROL_REG0_RXEN 0x1 + + * Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. + * PSU_UART0_CONTROL_REG0_TXRES 0x1 + + * Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. + * PSU_UART0_CONTROL_REG0_RXRES 0x1 + + * UART Control Register + * (OFFSET, MASK, VALUE) (0XFF000000, 0x000001FFU ,0x00000017U) + */ + PSU_Mask_Write(UART0_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U); +/*##################################################################### */ + + /* + * Register : mode_reg0 @ 0XFF000004 + + * Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback + * PSU_UART0_MODE_REG0_CHMODE 0x0 + + * Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved + * PSU_UART0_MODE_REG0_NBSTOP 0x0 + + * Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty + * PSU_UART0_MODE_REG0_PAR 0x4 + + * Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits + * PSU_UART0_MODE_REG0_CHRL 0x0 + + * Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 + * PSU_UART0_MODE_REG0_CLKS 0x0 + + * UART Mode Register + * (OFFSET, MASK, VALUE) (0XFF000004, 0x000003FFU ,0x00000020U) + */ + PSU_Mask_Write(UART0_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : Baud_rate_divider_reg0 @ 0XFF010034 + + * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate + * PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV 0x6 + + * Baud Rate Divider Register + * (OFFSET, MASK, VALUE) (0XFF010034, 0x000000FFU ,0x00000006U) + */ + PSU_Mask_Write(UART1_BAUD_RATE_DIVIDER_REG0_OFFSET, + 0x000000FFU, 0x00000006U); +/*##################################################################### */ + + /* + * Register : Baud_rate_gen_reg0 @ 0XFF010018 + + * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + * PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x7c + + * Baud Rate Generator Register. + * (OFFSET, MASK, VALUE) (0XFF010018, 0x0000FFFFU ,0x0000007CU) + */ + PSU_Mask_Write(UART1_BAUD_RATE_GEN_REG0_OFFSET, + 0x0000FFFFU, 0x0000007CU); +/*##################################################################### */ + + /* + * Register : Control_reg0 @ 0XFF010000 + + * Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. + * PSU_UART1_CONTROL_REG0_STPBRK 0x0 + + * Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. + * PSU_UART1_CONTROL_REG0_STTBRK 0x0 + + * Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. + * PSU_UART1_CONTROL_REG0_RSTTO 0x0 + + * Transmit disable: 0: enable transmitter 1: disable transmitter + * PSU_UART1_CONTROL_REG0_TXDIS 0x0 + + * Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. + * PSU_UART1_CONTROL_REG0_TXEN 0x1 + + * Receive disable: 0: enable 1: disable, regardless of the value of RXEN + * PSU_UART1_CONTROL_REG0_RXDIS 0x0 + + * Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. + * PSU_UART1_CONTROL_REG0_RXEN 0x1 + + * Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. + * PSU_UART1_CONTROL_REG0_TXRES 0x1 + + * Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. + * PSU_UART1_CONTROL_REG0_RXRES 0x1 + + * UART Control Register + * (OFFSET, MASK, VALUE) (0XFF010000, 0x000001FFU ,0x00000017U) + */ + PSU_Mask_Write(UART1_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U); +/*##################################################################### */ + + /* + * Register : mode_reg0 @ 0XFF010004 + + * Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback + * PSU_UART1_MODE_REG0_CHMODE 0x0 + + * Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved + * PSU_UART1_MODE_REG0_NBSTOP 0x0 + + * Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty + * PSU_UART1_MODE_REG0_PAR 0x4 + + * Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits + * PSU_UART1_MODE_REG0_CHRL 0x0 + + * Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 + * PSU_UART1_MODE_REG0_CLKS 0x0 + + * UART Mode Register + * (OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U) + */ + PSU_Mask_Write(UART1_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U); +/*##################################################################### */ + + /* + * GPIO + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_GPIO_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00040000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00040000U, 0x00000000U); +/*##################################################################### */ + + /* + * ADMA TZ + */ + /* + * Register : slcr_adma @ 0XFF4B0024 + + * TrustZone Classification for ADMA + * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0XFF + + * RPU TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * CSU TAMPERING + */ + /* + * CSU TAMPER STATUS + */ + /* + * Register : tamper_status @ 0XFFCA5000 + + * CSU regsiter + * PSU_CSU_TAMPER_STATUS_TAMPER_0 0 + + * External MIO + * PSU_CSU_TAMPER_STATUS_TAMPER_1 0 + + * JTAG toggle detect + * PSU_CSU_TAMPER_STATUS_TAMPER_2 0 + + * PL SEU error + * PSU_CSU_TAMPER_STATUS_TAMPER_3 0 + + * AMS over temperature alarm for LPD + * PSU_CSU_TAMPER_STATUS_TAMPER_4 0 + + * AMS over temperature alarm for APU + * PSU_CSU_TAMPER_STATUS_TAMPER_5 0 + + * AMS voltage alarm for VCCPINT_FPD + * PSU_CSU_TAMPER_STATUS_TAMPER_6 0 + + * AMS voltage alarm for VCCPINT_LPD + * PSU_CSU_TAMPER_STATUS_TAMPER_7 0 + + * AMS voltage alarm for VCCPAUX + * PSU_CSU_TAMPER_STATUS_TAMPER_8 0 + + * AMS voltage alarm for DDRPHY + * PSU_CSU_TAMPER_STATUS_TAMPER_9 0 + + * AMS voltage alarm for PSIO bank 0/1/2 + * PSU_CSU_TAMPER_STATUS_TAMPER_10 0 + + * AMS voltage alarm for PSIO bank 3 (dedicated pins) + * PSU_CSU_TAMPER_STATUS_TAMPER_11 0 + + * AMS voltaage alarm for GT + * PSU_CSU_TAMPER_STATUS_TAMPER_12 0 + + * Tamper Response Status + * (OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U) + */ + PSU_Mask_Write(CSU_TAMPER_STATUS_OFFSET, 0x00001FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * CSU TAMPER RESPONSE + */ + /* + * CPU QOS DEFAULT + */ + /* + * Register : ACE_CTRL @ 0XFD5C0060 + + * Set ACE outgoing AWQOS value + * PSU_APU_ACE_CTRL_AWQOS 0X0 + + * Set ACE outgoing ARQOS value + * PSU_APU_ACE_CTRL_ARQOS 0X0 + + * ACE Control Register + * (OFFSET, MASK, VALUE) (0XFD5C0060, 0x000F000FU ,0x00000000U) + */ + PSU_Mask_Write(APU_ACE_CTRL_OFFSET, 0x000F000FU, 0x00000000U); +/*##################################################################### */ + + /* + * ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE + */ + /* + * Register : CONTROL @ 0XFFA60040 + + * Enables the RTC. By writing a 0 to this bit, RTC will be powered off and + * the only module that potentially draws current from the battery will be + * BBRAM. The value read through this bit does not necessarily reflect whe + * ther RTC is enabled or not. It is expected that RTC is enabled every tim + * e it is being configured. If RTC is not used in the design, FSBL will di + * sable it by writing a 0 to this bit. + * PSU_RTC_CONTROL_BATTERY_DISABLE 0X1 + + * This register controls various functionalities within the RTC + * (OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U) + */ + PSU_Mask_Write(RTC_CONTROL_OFFSET, 0x80000000U, 0x80000000U); +/*##################################################################### */ + + /* + * TIMESTAMP COUNTER + */ + /* + * Register : base_frequency_ID_register @ 0XFF260020 + + * Frequency in number of ticks per second. Valid range from 10 MHz to 100 + * MHz. + * PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5dd18 + + * Program this register to match the clock frequency of the timestamp gene + * rator, in ticks per second. For example, for a 50 MHz clock, program 0x0 + * 2FAF080. This register is not accessible to the read-only programming in + * terface. + * (OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5DD18U) + */ + PSU_Mask_Write(IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET, + 0xFFFFFFFFU, 0x05F5DD18U); +/*##################################################################### */ + + /* + * Register : counter_control_register @ 0XFF260000 + + * Enable 0: The counter is disabled and not incrementing. 1: The counter i + * s enabled and is incrementing. + * PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1 + + * Controls the counter increments. This register is not accessible to the + * read-only programming interface. + * (OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * TTC SRC SELECT + */ + /* + * USB RESET + */ + /* + * USB RESET WITH BOOT PIN MODE + */ + /* + * BOOT PIN HIGH + */ + /* + * Register : BOOT_PIN_CTRL @ 0XFF5E0250 + + * Value driven onto the mode pins, when out_en = 1 + * PSU_CRL_APB_BOOT_PIN_CTRL_OUT_VAL 0X2 + + * When 0, the pins will be inputs from the board to the PS. When 1, the PS + * will drive these pins + * PSU_CRL_APB_BOOT_PIN_CTRL_OUT_EN 0X2 + + * Used to control the mode pins after boot. + * (OFFSET, MASK, VALUE) (0XFF5E0250, 0x00000F0FU ,0x00000202U) + */ + PSU_Mask_Write(CRL_APB_BOOT_PIN_CTRL_OFFSET, + 0x00000F0FU, 0x00000202U); +/*##################################################################### */ + + /* + * ADD 1US DELAY + */ + mask_delay(1); + +/*##################################################################### */ + + /* + * BOOT PIN LOW + */ + /* + * Register : BOOT_PIN_CTRL @ 0XFF5E0250 + + * Value driven onto the mode pins, when out_en = 1 + * PSU_CRL_APB_BOOT_PIN_CTRL_OUT_VAL 0X0 + + * When 0, the pins will be inputs from the board to the PS. When 1, the PS + * will drive these pins + * PSU_CRL_APB_BOOT_PIN_CTRL_OUT_EN 0X2 + + * Used to control the mode pins after boot. + * (OFFSET, MASK, VALUE) (0XFF5E0250, 0x00000F0FU ,0x00000002U) + */ + PSU_Mask_Write(CRL_APB_BOOT_PIN_CTRL_OFFSET, + 0x00000F0FU, 0x00000002U); +/*##################################################################### */ + + /* + * ADD 5US DELAY + */ + mask_delay(5); + +/*##################################################################### */ + + /* + * BOOT PIN HIGH + */ + /* + * Register : BOOT_PIN_CTRL @ 0XFF5E0250 + + * Value driven onto the mode pins, when out_en = 1 + * PSU_CRL_APB_BOOT_PIN_CTRL_OUT_VAL 0X2 + + * When 0, the pins will be inputs from the board to the PS. When 1, the PS + * will drive these pins + * PSU_CRL_APB_BOOT_PIN_CTRL_OUT_EN 0X2 + + * Used to control the mode pins after boot. + * (OFFSET, MASK, VALUE) (0XFF5E0250, 0x00000F0FU ,0x00000202U) + */ + PSU_Mask_Write(CRL_APB_BOOT_PIN_CTRL_OFFSET, + 0x00000F0FU, 0x00000202U); +/*##################################################################### */ + + /* + * PCIE RESET + */ + /* + * DIR MODE BANK 0 + */ + /* + * DIR MODE BANK 1 + */ + /* + * Register : DIRM_1 @ 0XFF0A0244 + + * Operation is the same as DIRM_0[DIRECTION_0] + * PSU_GPIO_DIRM_1_DIRECTION_1 0x20 + + * Direction mode (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0244, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_DIRM_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * DIR MODE BANK 2 + */ + /* + * OUTPUT ENABLE BANK 0 + */ + /* + * OUTPUT ENABLE BANK 1 + */ + /* + * Register : OEN_1 @ 0XFF0A0248 + + * Operation is the same as OEN_0[OP_ENABLE_0] + * PSU_GPIO_OEN_1_OP_ENABLE_1 0x20 + + * Output enable (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0248, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_OEN_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * OUTPUT ENABLE BANK 2 + */ + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0020U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * ADD 1US DELAY + */ + mask_delay(1); + +/*##################################################################### */ + + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x0 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0000U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0000U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * ADD 5US DELAY + */ + mask_delay(5); + +/*##################################################################### */ + + /* + * GPIO POLARITY INITIALIZATION + */ + /* + * Register : DIRM_1 @ 0XFF0A0244 + + * Operation is the same as DIRM_0[DIRECTION_0] + * PSU_GPIO_DIRM_1_DIRECTION_1 0x20 + + * Direction mode (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0244, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_DIRM_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : OEN_1 @ 0XFF0A0248 + + * Operation is the same as OEN_0[OP_ENABLE_0] + * PSU_GPIO_OEN_1_OP_ENABLE_1 0x20 + + * Output enable (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0248, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_OEN_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x0 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0000U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0000U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_post_config_data(void) +{ + /* + * POST_CONFIG + */ + + return 1; +} +unsigned long psu_peripherals_powerdwn_data(void) +{ + /* + * POWER DOWN REQUEST INTERRUPT ENABLE + */ + /* + * POWER DOWN TRIGGER + */ + + return 1; +} +unsigned long psu_lpd_xppu_data(void) +{ + /* + * MASTER ID LIST + */ + /* + * APERTURE PERMISIION LIST + */ + /* + * APERTURE NAME: UART0, START ADDRESS: FF000000, END ADDRESS: FF00FFFF + */ + /* + * APERTURE NAME: UART1, START ADDRESS: FF010000, END ADDRESS: FF01FFFF + */ + /* + * APERTURE NAME: I2C0, START ADDRESS: FF020000, END ADDRESS: FF02FFFF + */ + /* + * APERTURE NAME: I2C1, START ADDRESS: FF030000, END ADDRESS: FF03FFFF + */ + /* + * APERTURE NAME: SPI0, START ADDRESS: FF040000, END ADDRESS: FF04FFFF + */ + /* + * APERTURE NAME: SPI1, START ADDRESS: FF050000, END ADDRESS: FF05FFFF + */ + /* + * APERTURE NAME: CAN0, START ADDRESS: FF060000, END ADDRESS: FF06FFFF + */ + /* + * APERTURE NAME: CAN1, START ADDRESS: FF070000, END ADDRESS: FF07FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09 + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09 + * FFFF + */ + /* + * APERTURE NAME: GPIO, START ADDRESS: FF0A0000, END ADDRESS: FF0AFFFF + */ + /* + * APERTURE NAME: GEM0, START ADDRESS: FF0B0000, END ADDRESS: FF0BFFFF + */ + /* + * APERTURE NAME: GEM1, START ADDRESS: FF0C0000, END ADDRESS: FF0CFFFF + */ + /* + * APERTURE NAME: GEM2, START ADDRESS: FF0D0000, END ADDRESS: FF0DFFFF + */ + /* + * APERTURE NAME: GEM3, START ADDRESS: FF0E0000, END ADDRESS: FF0EFFFF + */ + /* + * APERTURE NAME: QSPI, START ADDRESS: FF0F0000, END ADDRESS: FF0FFFFF + */ + /* + * APERTURE NAME: NAND, START ADDRESS: FF100000, END ADDRESS: FF10FFFF + */ + /* + * APERTURE NAME: TTC0, START ADDRESS: FF110000, END ADDRESS: FF11FFFF + */ + /* + * APERTURE NAME: TTC1, START ADDRESS: FF120000, END ADDRESS: FF12FFFF + */ + /* + * APERTURE NAME: TTC2, START ADDRESS: FF130000, END ADDRESS: FF13FFFF + */ + /* + * APERTURE NAME: TTC3, START ADDRESS: FF140000, END ADDRESS: FF14FFFF + */ + /* + * APERTURE NAME: SWDT, START ADDRESS: FF150000, END ADDRESS: FF15FFFF + */ + /* + * APERTURE NAME: SD0, START ADDRESS: FF160000, END ADDRESS: FF16FFFF + */ + /* + * APERTURE NAME: SD1, START ADDRESS: FF170000, END ADDRESS: FF17FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SECURE_SLCR, START ADDRESS: FF240000, END ADDRESS: FF + * 24FFFF + */ + /* + * APERTURE NAME: IOU_SCNTR, START ADDRESS: FF250000, END ADDRESS: FF25FFFF + */ + /* + * APERTURE NAME: IOU_SCNTRS, START ADDRESS: FF260000, END ADDRESS: FF26FFF + * F + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_1, START ADDRESS: FF400000, END ADDRESS: FF40F + * FFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: OCM_SLCR, START ADDRESS: FF960000, END ADDRESS: FF96FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_4, START ADDRESS: FF970000, END ADDRESS: FF97F + * FFF + */ + /* + * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + */ + /* + * APERTURE NAME: RPU, START ADDRESS: FF9A0000, END ADDRESS: FF9AFFFF + */ + /* + * APERTURE NAME: AFIFM6, START ADDRESS: FF9B0000, END ADDRESS: FF9BFFFF + */ + /* + * APERTURE NAME: LPD_XPPU_SINK, START ADDRESS: FF9C0000, END ADDRESS: FF9C + * FFFF + */ + /* + * APERTURE NAME: USB3_0, START ADDRESS: FF9D0000, END ADDRESS: FF9DFFFF + */ + /* + * APERTURE NAME: USB3_1, START ADDRESS: FF9E0000, END ADDRESS: FF9EFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_5, START ADDRESS: FF9F0000, END ADDRESS: FF9FF + * FFF + */ + /* + * APERTURE NAME: APM0, START ADDRESS: FFA00000, END ADDRESS: FFA0FFFF + */ + /* + * APERTURE NAME: APM1, START ADDRESS: FFA10000, END ADDRESS: FFA1FFFF + */ + /* + * APERTURE NAME: APM_INTC_IOU, START ADDRESS: FFA20000, END ADDRESS: FFA2F + * FFF + */ + /* + * APERTURE NAME: APM_FPD_LPD, START ADDRESS: FFA30000, END ADDRESS: FFA3FF + * FF + */ + /* + * APERTURE NAME: LPD_UNUSED_6, START ADDRESS: FFA40000, END ADDRESS: FFA4F + * FFF + */ + /* + * APERTURE NAME: AMS, START ADDRESS: FFA50000, END ADDRESS: FFA5FFFF + */ + /* + * APERTURE NAME: RTC, START ADDRESS: FFA60000, END ADDRESS: FFA6FFFF + */ + /* + * APERTURE NAME: OCM_XMPU_CFG, START ADDRESS: FFA70000, END ADDRESS: FFA7F + * FFF + */ + /* + * APERTURE NAME: ADMA_0, START ADDRESS: FFA80000, END ADDRESS: FFA8FFFF + */ + /* + * APERTURE NAME: ADMA_1, START ADDRESS: FFA90000, END ADDRESS: FFA9FFFF + */ + /* + * APERTURE NAME: ADMA_2, START ADDRESS: FFAA0000, END ADDRESS: FFAAFFFF + */ + /* + * APERTURE NAME: ADMA_3, START ADDRESS: FFAB0000, END ADDRESS: FFABFFFF + */ + /* + * APERTURE NAME: ADMA_4, START ADDRESS: FFAC0000, END ADDRESS: FFACFFFF + */ + /* + * APERTURE NAME: ADMA_5, START ADDRESS: FFAD0000, END ADDRESS: FFADFFFF + */ + /* + * APERTURE NAME: ADMA_6, START ADDRESS: FFAE0000, END ADDRESS: FFAEFFFF + */ + /* + * APERTURE NAME: ADMA_7, START ADDRESS: FFAF0000, END ADDRESS: FFAFFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + */ + /* + * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + */ + /* + * APERTURE NAME: CSU_LOCAL, START ADDRESS: FFC20000, END ADDRESS: FFC2FFFF + */ + /* + * APERTURE NAME: PUF, START ADDRESS: FFC30000, END ADDRESS: FFC3FFFF + */ + /* + * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + */ + /* + * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + */ + /* + * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F + * FFF + */ + /* + * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F + * FFF + */ + /* + * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + */ + /* + * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + */ + /* + * APERTURE NAME: CSU, START ADDRESS: FFCA0000, END ADDRESS: FFCAFFFF + */ + /* + * APERTURE NAME: CSU_WDT, START ADDRESS: FFCB0000, END ADDRESS: FFCBFFFF + */ + /* + * APERTURE NAME: EFUSE, START ADDRESS: FFCC0000, END ADDRESS: FFCCFFFF + */ + /* + * APERTURE NAME: BBRAM, START ADDRESS: FFCD0000, END ADDRESS: FFCDFFFF + */ + /* + * APERTURE NAME: RSA_CORE, START ADDRESS: FFCE0000, END ADDRESS: FFCEFFFF + */ + /* + * APERTURE NAME: MBISTJTAG, START ADDRESS: FFCF0000, END ADDRESS: FFCFFFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F + * FFF + */ + /* + * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F + * FFF + */ + /* + * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + */ + /* + * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: R5_0_ATCM, START ADDRESS: FFE00000, END ADDRESS: FFE0FFFF + */ + /* + * APERTURE NAME: R5_0_ATCM_LOCKSTEP, START ADDRESS: FFE10000, END ADDRESS: + * FFE1FFFF + */ + /* + * APERTURE NAME: R5_0_BTCM, START ADDRESS: FFE20000, END ADDRESS: FFE2FFFF + */ + /* + * APERTURE NAME: R5_0_BTCM_LOCKSTEP, START ADDRESS: FFE30000, END ADDRESS: + * FFE3FFFF + */ + /* + * APERTURE NAME: R5_0_INSTRUCTION_CACHE, START ADDRESS: FFE40000, END ADDR + * ESS: FFE4FFFF + */ + /* + * APERTURE NAME: R5_0_DATA_CACHE, START ADDRESS: FFE50000, END ADDRESS: FF + * E5FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: R5_1_ATCM_, START ADDRESS: FFE90000, END ADDRESS: FFE9FFF + * F + */ + /* + * APERTURE NAME: RPU_UNUSED_10, START ADDRESS: FFEA0000, END ADDRESS: FFEA + * FFFF + */ + /* + * APERTURE NAME: R5_1_BTCM_, START ADDRESS: FFEB0000, END ADDRESS: FFEBFFF + * F + */ + /* + * APERTURE NAME: R5_1_INSTRUCTION_CACHE, START ADDRESS: FFEC0000, END ADDR + * ESS: FFECFFFF + */ + /* + * APERTURE NAME: R5_1_DATA_CACHE, START ADDRESS: FFED0000, END ADDRESS: FF + * EDFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IOU_GPV, START ADDRESS: FE000000, END ADDRESS: FE0FFFFF + */ + /* + * APERTURE NAME: LPD_GPV, START ADDRESS: FE100000, END ADDRESS: FE1FFFFF + */ + /* + * APERTURE NAME: USB3_0_XHCI, START ADDRESS: FE200000, END ADDRESS: FE2FFF + * FF + */ + /* + * APERTURE NAME: USB3_1_XHCI, START ADDRESS: FE300000, END ADDRESS: FE3FFF + * FF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: QSPI_LINEAR_ADDRESS, START ADDRESS: C0000000, END ADDRESS + * : DFFFFFFF + */ + /* + * XPPU CONTROL + */ + + return 1; +} +unsigned long psu_ddr_xmpu0_data(void) +{ + /* + * DDR XMPU0 + */ + + return 1; +} +unsigned long psu_ddr_xmpu1_data(void) +{ + /* + * DDR XMPU1 + */ + + return 1; +} +unsigned long psu_ddr_xmpu2_data(void) +{ + /* + * DDR XMPU2 + */ + + return 1; +} +unsigned long psu_ddr_xmpu3_data(void) +{ + /* + * DDR XMPU3 + */ + + return 1; +} +unsigned long psu_ddr_xmpu4_data(void) +{ + /* + * DDR XMPU4 + */ + + return 1; +} +unsigned long psu_ddr_xmpu5_data(void) +{ + /* + * DDR XMPU5 + */ + + return 1; +} +unsigned long psu_ocm_xmpu_data(void) +{ + /* + * OCM XMPU + */ + + return 1; +} +unsigned long psu_fpd_xmpu_data(void) +{ + /* + * FPD XMPU + */ + + return 1; +} +unsigned long psu_protection_lock_data(void) +{ + /* + * LOCKING PROTECTION MODULE + */ + /* + * XPPU LOCK + */ + /* + * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + */ + /* + * XMPU LOCK + */ + /* + * LOCK OCM XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK FPD XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + + return 1; +} +unsigned long psu_apply_master_tz(void) +{ + /* + * RPU + */ + /* + * DP TZ + */ + /* + * Register : slcr_dpdma @ 0XFD690040 + + * TrustZone classification for DisplayPort DMA + * PSU_FPD_SLCR_SECURE_SLCR_DPDMA_TZ 1 + + * DPDMA TrustZone Settings + * (OFFSET, MASK, VALUE) (0XFD690040, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * SATA TZ + */ + /* + * PCIE TZ + */ + /* + * Register : slcr_pcie @ 0XFD690030 + + * TrustZone classification for DMA Channel 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0 1 + + * TrustZone classification for DMA Channel 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1 1 + + * TrustZone classification for DMA Channel 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2 1 + + * TrustZone classification for DMA Channel 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3 1 + + * TrustZone classification for Ingress Address Translation 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0 1 + + * TrustZone classification for Ingress Address Translation 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1 1 + + * TrustZone classification for Ingress Address Translation 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2 1 + + * TrustZone classification for Ingress Address Translation 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3 1 + + * TrustZone classification for Ingress Address Translation 4 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4 1 + + * TrustZone classification for Ingress Address Translation 5 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5 1 + + * TrustZone classification for Ingress Address Translation 6 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6 1 + + * TrustZone classification for Ingress Address Translation 7 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7 1 + + * TrustZone classification for Egress Address Translation 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0 1 + + * TrustZone classification for Egress Address Translation 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1 1 + + * TrustZone classification for Egress Address Translation 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2 1 + + * TrustZone classification for Egress Address Translation 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3 1 + + * TrustZone classification for Egress Address Translation 4 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4 1 + + * TrustZone classification for Egress Address Translation 5 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5 1 + + * TrustZone classification for Egress Address Translation 6 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6 1 + + * TrustZone classification for Egress Address Translation 7 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7 1 + + * TrustZone classification for DMA Registers + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS 1 + + * TrustZone classification for MSIx Table + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE 1 + + * TrustZone classification for MSIx PBA + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA 1 + + * TrustZone classification for ECAM + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM 1 + + * TrustZone classification for Bridge Common Registers + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS 1 + + * PCIe TrustZone settings. This register may only be modified during bootu + * p (while PCIe block is disabled) + * (OFFSET, MASK, VALUE) (0XFD690030, 0x01FFFFFFU ,0x01FFFFFFU) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_PCIE_OFFSET, + 0x01FFFFFFU, 0x01FFFFFFU); +/*##################################################################### */ + + /* + * USB TZ + */ + /* + * Register : slcr_usb @ 0XFF4B0034 + + * TrustZone Classification for USB3_0 + * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0 1 + + * TrustZone Classification for USB3_1 + * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1 1 + + * USB3 TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0034, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_USB_OFFSET, + 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * SD TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x003F0000U ,0x00120000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x003F0000U, 0x00120000U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x003F0000U ,0x00120000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x003F0000U, 0x00120000U); +/*##################################################################### */ + + /* + * GEM TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x00000FFFU ,0x00000492U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x00000FFFU, 0x00000492U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x00000FFFU ,0x00000492U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x00000FFFU, 0x00000492U); +/*##################################################################### */ + + /* + * QSPI TZ + */ + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x0E000000U ,0x04000000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x0E000000U, 0x04000000U); +/*##################################################################### */ + + /* + * NAND TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x01C00000U ,0x00800000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x01C00000U, 0x00800000U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x01C00000U ,0x00800000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x01C00000U, 0x00800000U); +/*##################################################################### */ + + /* + * DMA TZ + */ + /* + * Register : slcr_adma @ 0XFF4B0024 + + * TrustZone Classification for ADMA + * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0xFF + + * RPU TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : slcr_gdma @ 0XFD690050 + + * TrustZone Classification for GDMA + * PSU_FPD_SLCR_SECURE_SLCR_GDMA_TZ 0xFF + + * GDMA Trustzone Settings + * (OFFSET, MASK, VALUE) (0XFD690050, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_GDMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_serdes_init_data(void) +{ + /* + * SERDES INITIALIZATION + */ + /* + * GT REFERENCE CLOCK SOURCE SELECTION + */ + /* + * Register : PLL_REF_SEL0 @ 0XFD410000 + + * PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD + + * PLL0 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL0_OFFSET, 0x0000001FU, 0x0000000DU); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL1 @ 0XFD410004 + + * PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9 + + * PLL1 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL1_OFFSET, 0x0000001FU, 0x00000009U); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL2 @ 0XFD410008 + + * PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8 + + * PLL2 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL2_OFFSET, 0x0000001FU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL3 @ 0XFD41000C + + * PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF + + * PLL3 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL3_OFFSET, 0x0000001FU, 0x0000000FU); +/*##################################################################### */ + + /* + * GT REFERENCE CLOCK FREQUENCY SELECTION + */ + /* + * Register : L0_L0_REF_CLK_SEL @ 0XFD402860 + + * Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp + * ut. Set to 0 to select lane0 ref clock mux output. + * PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1 + + * Lane0 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_L0_REF_CLK_SEL_OFFSET, + 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_L1_REF_CLK_SEL @ 0XFD402864 + + * Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane1 ref clock mux output. + * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0 + + * Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli + * cer output from ref clock network + * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1 + + * Lane1 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U) + */ + PSU_Mask_Write(SERDES_L0_L1_REF_CLK_SEL_OFFSET, + 0x00000088U, 0x00000008U); +/*##################################################################### */ + + /* + * Register : L0_L2_REF_CLK_SEL @ 0XFD402868 + + * Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane2 ref clock mux output. + * PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1 + + * Lane2 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_L2_REF_CLK_SEL_OFFSET, + 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_L3_REF_CLK_SEL @ 0XFD40286C + + * Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp + * ut. Set to 0 to select lane3 ref clock mux output. + * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0 + + * Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli + * cer output from ref clock network + * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1 + + * Lane3 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L0_L3_REF_CLK_SEL_OFFSET, + 0x00000082U, 0x00000002U); +/*##################################################################### */ + + /* + * ENABLE SPREAD SPECTRUM + */ + /* + * Register : L2_TM_PLL_DIG_37 @ 0XFD40A094 + + * Enable/Disable coarse code satureation limiting logic + * PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1 + + * Test mode register 37 + * (OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_PLL_DIG_37_OFFSET, + 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x00000038U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x000000E0U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x00000058U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x0000007CU); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374 + + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33 + + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x00000033U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378 + + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 + + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C + + * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 + + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x00000033U, 0x00000030U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4 + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x000000F4U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374 + + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31 + + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x00000031U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378 + + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 + + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C + + * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 + + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x00000033U, 0x00000030U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9 + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x000000C9U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374 + + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2 + + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x000000D2U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378 + + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1 + + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C + + * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 + + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable test mode forcing on enable Spread Spectrum + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1 + + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x000000B3U, 0x000000B0U); +/*##################################################################### */ + + /* + * Register : L2_TM_DIG_6 @ 0XFD40906C + + * Bypass Descrambler + * PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1 + + * Enable Bypass for <1> TM_DIG_CTRL_6 + * PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 + + * Data path test modes in decoder and descram + * (OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_6_OFFSET, 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L2_TX_DIG_TM_61 @ 0XFD4080F4 + + * Bypass scrambler signal + * PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1 + + * Enable/disable scrambler bypass signal + * PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 + + * MPHY PLL Gear and bypass scrambler + * (OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_TX_DIG_TM_61_OFFSET, + 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360 + + * Enable test mode force on fractional mode enable + * PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1 + + * Fractional feedback division control and fractional value for feedback d + * ivision bits 26:24 + * (OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L3_TM_DIG_6 @ 0XFD40D06C + + * Bypass 8b10b decoder + * PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1 + + * Enable Bypass for <3> TM_DIG_CTRL_6 + * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1 + + * Bypass Descrambler + * PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1 + + * Enable Bypass for <1> TM_DIG_CTRL_6 + * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 + + * Data path test modes in decoder and descram + * (OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_6_OFFSET, 0x0000000FU, 0x0000000FU); +/*##################################################################### */ + + /* + * Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4 + + * Enable/disable encoder bypass signal + * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1 + + * Bypass scrambler signal + * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1 + + * Enable/disable scrambler bypass signal + * PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 + + * MPHY PLL Gear and bypass scrambler + * (OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU) + */ + PSU_Mask_Write(SERDES_L3_TX_DIG_TM_61_OFFSET, + 0x0000000BU, 0x0000000BU); +/*##################################################################### */ + + /* + * ENABLE CHICKEN BIT FOR PCIE AND USB + */ + /* + * Register : L0_TM_AUX_0 @ 0XFD4010CC + + * Spare- not used + * PSU_SERDES_L0_TM_AUX_0_BIT_2 1 + + * Spare registers + * (OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L0_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L2_TM_AUX_0 @ 0XFD4090CC + + * Spare- not used + * PSU_SERDES_L2_TM_AUX_0_BIT_2 1 + + * Spare registers + * (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L2_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * ENABLING EYE SURF + */ + /* + * Register : L0_TM_DIG_8 @ 0XFD401074 + + * Enable Eye Surf + * PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L0_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L1_TM_DIG_8 @ 0XFD405074 + + * Enable Eye Surf + * PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L1_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_DIG_8 @ 0XFD409074 + + * Enable Eye Surf + * PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L3_TM_DIG_8 @ 0XFD40D074 + + * Enable Eye Surf + * PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * ILL SETTINGS FOR GAIN AND LOCK SETTINGS + */ + /* + * Register : L0_TM_MISC2 @ 0XFD40189C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL1 @ 0XFD4018F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL2 @ 0XFD4018FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL12 @ 0XFD401990 + + * G1A pll ctr bypass value + * PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL12_OFFSET, 0x000000FFU, 0x00000011U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL1 @ 0XFD401924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL1_OFFSET, 0x000000FFU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL2 @ 0XFD401928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL2_OFFSET, 0x000000FFU, 0x000000FEU); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL3 @ 0XFD401900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL3 @ 0XFD40192C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL8 @ 0XFD401980 + + * ILL calibration code change wait time + * PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL8 @ 0XFD401914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL9 @ 0XFD401918 + + * bypass IQ polytrim + * PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL8 @ 0XFD401940 + + * E ILL polytrim bypass value + * PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL9 @ 0XFD401944 + + * bypass E polytrim + * PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL13 @ 0XFD401994 + + * ILL cal idle val refcnt + * PSU_SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD401994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L1_TM_ILL13 @ 0XFD405994 + + * ILL cal idle val refcnt + * PSU_SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD405994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L1_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L2_TM_MISC2 @ 0XFD40989C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L2_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL1 @ 0XFD4098F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL2 @ 0XFD4098FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL12 @ 0XFD409990 + + * G1A pll ctr bypass value + * PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL12_OFFSET, 0x000000FFU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL1 @ 0XFD409924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL1_OFFSET, 0x000000FFU, 0x000000FEU); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL2 @ 0XFD409928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL3 @ 0XFD409900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL3 @ 0XFD40992C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL8 @ 0XFD409980 + + * ILL calibration code change wait time + * PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL8 @ 0XFD409914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL9 @ 0XFD409918 + + * bypass IQ polytrim + * PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL8 @ 0XFD409940 + + * E ILL polytrim bypass value + * PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL9 @ 0XFD409944 + + * bypass E polytrim + * PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL13 @ 0XFD409994 + + * ILL cal idle val refcnt + * PSU_SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD409994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L3_TM_MISC2 @ 0XFD40D89C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L3_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL12 @ 0XFD40D990 + + * G1A pll ctr bypass value + * PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL12_OFFSET, 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL1 @ 0XFD40D924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL1_OFFSET, 0x000000FFU, 0x0000009CU); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL2 @ 0XFD40D928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000039U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL11 @ 0XFD40D98C + + * G2A_PCIe1 PLL ctr bypass value + * PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL11_OFFSET, 0x000000F0U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL3 @ 0XFD40D900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL3 @ 0XFD40D92C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL8 @ 0XFD40D980 + + * ILL calibration code change wait time + * PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL8 @ 0XFD40D914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL9 @ 0XFD40D918 + + * bypass IQ polytrim + * PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL8 @ 0XFD40D940 + + * E ILL polytrim bypass value + * PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL9 @ 0XFD40D944 + + * bypass E polytrim + * PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL13 @ 0XFD40D994 + + * ILL cal idle val refcnt + * PSU_SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD40D994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * SYMBOL LOCK AND WAIT + */ + /* + * Register : L0_TM_DIG_10 @ 0XFD40107C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L1_TM_DIG_10 @ 0XFD40507C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40507C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L1_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_DIG_10 @ 0XFD40907C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40907C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_DIG_10 @ 0XFD40D07C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40D07C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG + */ + /* + * Register : L0_TM_RST_DLY @ 0XFD4019A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L0_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L0_TM_ANA_BYP_15 @ 0XFD401038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L0_TM_ANA_BYP_12 @ 0XFD40102C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L1_TM_RST_DLY @ 0XFD4059A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L1_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L1_TM_ANA_BYP_15 @ 0XFD405038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L1_TM_ANA_BYP_12 @ 0XFD40502C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L2_TM_RST_DLY @ 0XFD4099A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L2_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L2_TM_ANA_BYP_15 @ 0XFD409038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L2_TM_ANA_BYP_12 @ 0XFD40902C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L3_TM_RST_DLY @ 0XFD40D9A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L3_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L3_TM_ANA_BYP_15 @ 0XFD40D038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * DISABLE FPL/FFL + */ + /* + * Register : L0_TM_MISC3 @ 0XFD4019AC + + * CDR fast phase lock control + * PSU_SERDES_L0_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L0_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4019AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L0_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L1_TM_MISC3 @ 0XFD4059AC + + * CDR fast phase lock control + * PSU_SERDES_L1_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L1_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4059AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_MISC3 @ 0XFD4099AC + + * CDR fast phase lock control + * PSU_SERDES_L2_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L2_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4099AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L3_TM_MISC3 @ 0XFD40D9AC + + * CDR fast phase lock control + * PSU_SERDES_L3_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L3_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD40D9AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L3_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * DISABLE DYNAMIC OFFSET CALIBRATION + */ + /* + * Register : L0_TM_EQ11 @ 0XFD401978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD401978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L0_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L1_TM_EQ11 @ 0XFD405978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD405978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L1_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_EQ11 @ 0XFD409978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD409978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ11 @ 0XFD40D978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD40D978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * SERDES ILL CALIB + */ + serdes_illcalib(2,3,3,0,4,0,1,1); + +/*##################################################################### */ + + /* + * DISABLE ECO FOR PCIE + */ + /* + * Register : eco_0 @ 0XFD3D001C + + * For future use + * PSU_SIOU_ECO_0_FIELD 0x1 + + * ECO Register for future use + * (OFFSET, MASK, VALUE) (0XFD3D001C, 0xFFFFFFFFU ,0x00000001U) + */ + PSU_Mask_Write(SIOU_ECO_0_OFFSET, 0xFFFFFFFFU, 0x00000001U); +/*##################################################################### */ + + /* + * GT LANE SETTINGS + */ + /* + * Register : ICM_CFG0 @ 0XFD410010 + + * Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1 + + * Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4 + + * ICM Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U) + */ + PSU_Mask_Write(SERDES_ICM_CFG0_OFFSET, 0x00000077U, 0x00000041U); +/*##################################################################### */ + + /* + * Register : ICM_CFG1 @ 0XFD410014 + + * Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3 + + * Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, + * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2 + + * ICM Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U) + */ + PSU_Mask_Write(SERDES_ICM_CFG1_OFFSET, 0x00000077U, 0x00000023U); +/*##################################################################### */ + + /* + * CHECKING PLL LOCK + */ + /* + * ENABLE SERIAL DATA MUX DEEMPH + */ + /* + * Register : L1_TXPMD_TM_45 @ 0XFD404CB4 + + * Enable/disable DP post2 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1 + + * Override enable/disable of DP post2 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1 + + * Override enable/disable of DP post1 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1 + + * Enable/disable DP main path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1 + + * Override enable/disable of DP main path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1 + + * Post or pre or main DP path selection + * (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U) + */ + PSU_Mask_Write(SERDES_L1_TXPMD_TM_45_OFFSET, + 0x00000037U, 0x00000037U); +/*##################################################################### */ + + /* + * Register : L1_TX_ANA_TM_118 @ 0XFD4041D8 + + * Test register force for enabling/disablign TX deemphasis bits <17:0> + * PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 + + * Enable Override of TX deemphasis + * (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L1_TX_ANA_TM_118_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8 + + * Test register force for enabling/disablign TX deemphasis bits <17:0> + * PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 + + * Enable Override of TX deemphasis + * (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TX_ANA_TM_118_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * CDR AND RX EQUALIZATION SETTINGS + */ + /* + * Register : L3_TM_CDR5 @ 0XFD40DC14 + + * FPHL FSM accumulate cycles + * PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7 + + * FFL Phase0 int gain aka 2ol SD update rate + * PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6 + + * Fast phase lock controls -- FSM accumulator cycle control and phase 0 in + * t gain control. + * (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U) + */ + PSU_Mask_Write(SERDES_L3_TM_CDR5_OFFSET, 0x000000FFU, 0x000000E6U); +/*##################################################################### */ + + /* + * Register : L3_TM_CDR16 @ 0XFD40DC40 + + * FFL Phase0 prop gain aka 1ol SD update rate + * PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC + + * Fast phase lock controls -- phase 0 prop gain + * (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU) + */ + PSU_Mask_Write(SERDES_L3_TM_CDR16_OFFSET, 0x0000001FU, 0x0000000CU); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ0 @ 0XFD40D94C + + * EQ stg 2 controls BYPASSED + * PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1 + + * eq stg1 and stg2 controls + * (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ1 @ 0XFD40D950 + + * EQ STG2 RL PROG + * PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2 + + * EQ stg 2 preamp mode val + * PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1 + + * eq stg1 and stg2 controls + * (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ1_OFFSET, 0x00000007U, 0x00000006U); +/*##################################################################### */ + + /* + * GEM SERDES SETTINGS + */ + /* + * ENABLE PRE EMPHAIS AND VOLTAGE SWING + */ + /* + * Register : L1_TXPMD_TM_48 @ 0XFD404CC0 + + * Margining factor value + * PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0 + + * Margining factor + * (OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TXPMD_TM_48_OFFSET, + 0x0000001FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L1_TX_ANA_TM_18 @ 0XFD404048 + + * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved + * PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0 + + * Override for PIPE TX de-emphasis + * (OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TX_ANA_TM_18_OFFSET, + 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L3_TX_ANA_TM_18 @ 0XFD40C048 + + * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved + * PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1 + + * Override for PIPE TX de-emphasis + * (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TX_ANA_TM_18_OFFSET, + 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_resetout_init_data(void) +{ + /* + * TAKING SERDES PERIPHERAL OUT OF RESET RESET + */ + /* + * PUTTING USB0 IN RESET + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000400U, 0x00000000U); +/*##################################################################### */ + + /* + * USB0 PIPE POWER PRESENT + */ + /* + * Register : fpd_power_prsnt @ 0XFF9D0080 + + * This bit is used to choose between PIPE power present and 1'b1 + * PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1 + + * fpd_power_prsnt + * (OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(USB3_0_FPD_POWER_PRSNT_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : fpd_pipe_clk @ 0XFF9D007C + + * This bit is used to choose between PIPE clock coming from SerDes and the + * suspend clk + * PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0 + + * fpd_pipe_clk + * (OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(USB3_0_FPD_PIPE_CLK_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * HIBERREST + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0 + + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000140U, 0x00000000U); +/*##################################################################### */ + + /* + * PUTTING GEM0 IN RESET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 + + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0 + + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * PUTTING SATA IN RESET + */ + /* + * Register : sata_misc_ctrl @ 0XFD3D0100 + + * Sata PM clock control select + * PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3 + + * Misc Contorls for SATA.This register may only be modified during bootup + * (while SATA block is disabled) + * (OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SIOU_SATA_MISC_CTRL_OFFSET, 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ + + /* + * PUTTING PCIE CFG AND BRIDGE IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0 + + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000C0000U, 0x00000000U); +/*##################################################################### */ + + /* + * PUTTING DP IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DP_PHY_RESET @ 0XFD4A0200 + + * Set to '1' to hold the GT in reset. Clear to release. + * PSU_DP_DP_PHY_RESET_GT_RESET 0X0 + + * Reset the transmitter PHY. + * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238 + + * Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 + * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0 + + * Control PHY Power down + * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET, + 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + /* + * USB0 GFLADJ + */ + /* + * Register : GUSB2PHYCFG @ 0XFE20C200 + + * USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc + * ks. Specifies the response time for a MAC request to the Packet FIFO Con + * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th + * e required values for the minimum SoC bus frequency of 60 MHz. USB turna + * round time is a critical certification criteria when using long cables a + * nd five hub levels. The required values for this field: - 4'h5: When the + * MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit + * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim + * e is not critical, this field can be set to a larger value. Note: This f + * ield is valid only in device mode. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9 + + * Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP + * I Transceiver Select signal (for HS) and the assertion of the TxValid si + * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima + * tely 2.5 us) is introduced from the time when the Transceiver Select is + * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the + * chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you + * enable the hibernation feature when the device core comes out of power- + * off, you must re-initialize this bit with the appropriate value because + * the core does not save and restore this bit value during hibernation. - + * This bit is valid only in device mode. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0 + + * Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use + * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th + * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert + * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s + * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t + * he external PHY. Note: This bit must be set high for Port0 if PHY is use + * d. Note: In Device mode - Before issuing any device endpoint command whe + * n operating in 2.0 speeds, disable this bit and enable it after the comm + * and completes. Without disabling this bit, if a command is issued when t + * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of + * f, the command will not get completed. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0 + + * USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T + * he application uses this bit to select a high-speed PHY or a full-speed + * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a + * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans + * ceiver. This bit is always 1, with Write Only access. If both interface + * types are selected in coreConsultant (that is, parameters' values are no + * t zero), the application uses this bit to select the active interface is + * active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv + * er is not supported. This bit always reads as 1'b0. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0 + + * Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend + * mode if Suspend conditions are valid. For DRD/OTG configurations, it is + * recommended that this bit is set to 0 during coreConsultant configurati + * on. If it is set to 1, then the application must clear this bit after po + * wer-on reset. Application needs to set it to 1 after the core initializa + * tion completes. For all other configurations, this bit can be set to 1 d + * uring core configuration. Note: - In host mode, on reset, this bit is se + * t to 1. Software can override this bit after reset. - In device mode, be + * fore issuing any device endpoint command when operating in 2.0 speeds, d + * isable this bit and enable it after the command completes. If you issue + * a command without disabling this bit when the device is in L2 state and + * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c + * ompleted. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0x1 + + * Full-Speed Serial Interface Select (FSIntf) The application uses this bi + * t to select a unidirectional or bidirectional USB 1.1 full-speed serial + * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in + * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir + * ectional full-speed serial interface. This bit is set to 0 with Read Onl + * y access. Note: USB 1.1 full-speed serial interface is not supported. Th + * is bit always reads as 1'b0. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0 + + * ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se + * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int + * erface This bit is writable only if UTMI+ and ULPI is specified for High + * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_ + * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o + * n the interface selected through DWC_USB3_HSPHY_INTERFACE. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1 + + * PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi + * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte + * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en + * abled 2.0 ports must have the same clock frequency as Port0 clock freque + * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge + * ther for different ports at the same time (that is, all the ports must b + * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If + * any of the USB 2.0 ports is selected as ULPI port for operation, then a + * ll the USB 2.0 ports must be operating at 60 MHz. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0 + + * HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat + * ed by the application in this field, is multiplied by a bit-time factor; + * this factor is added to the high-speed/full-speed interpacket timeout d + * uration in the core to account for additional delays introduced by the P + * HY. This may be required, since the delay introduced by the PHY in gener + * ating the linestate condition may vary among PHYs. The USB standard time + * out value for high-speed operation is 736 to 816 (inclusive) bit times. + * The USB standard timeout value for full-speed operation is 16 to 18 (inc + * lusive) bit times. The application must program this field based on the + * speed of connection. The number of bit times added per PHY clock are: Hi + * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P + * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0. + * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc + * k = 0.25 bit times + * PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7 + + * ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive + * 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char + * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl + * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3) + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV 0x1 + + * Global USB2 PHY Configuration Register The application must program this + * register before starting any transactions on either the SoC bus or the + * USB. In Device-only configurations, only one register is needed. In Host + * mode, per-port registers are implemented. + * (OFFSET, MASK, VALUE) (0XFE20C200, 0x00023FFFU ,0x00022457U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUSB2PHYCFG_OFFSET, + 0x00023FFFU, 0x00022457U); +/*##################################################################### */ + + /* + * Register : GFLADJ @ 0XFE20C630 + + * This field indicates the frame length adjustment to be applied when SOF/ + * ITP counter is running on the ref_clk. This register value is used to ad + * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i + * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must + * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t + * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows: + * FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe + * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege + * r value of the ref_clk period got by truncating the decimal (fractional) + * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c + * lk_period is the ref_clk period including the fractional value. Examples + * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA + * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin + * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE + * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2 + * 0.8333 = 5208 (ignoring the fractional value) + * PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0 + + * Global Frame Length Adjustment Register This register provides options f + * or the software to control the core behavior with respect to SOF (Start + * of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer + * functionality. It provides an option to override the fladj_30mhz_reg sid + * eband signal. In addition, it enables running SOF or ITP frame timer cou + * nters completely from the ref_clk. This facilitates hardware LPM in host + * mode with the SOF or ITP counters being run from the ref_clk signal. + * (OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) + */ + PSU_Mask_Write(USB3_0_XHCI_GFLADJ_OFFSET, 0x003FFF00U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : GUCTL1 @ 0XFE20C11C + + * When this bit is set to '0', termsel, xcvrsel will become 0 during end o + * f resume while the opmode will become 0 once controller completes end of + * resume and enters U0 state (2 separate commandswill be issued). When th + * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during + * end of resume itself (only 1 command will be issued) + * PSU_USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY 0x1 + + * Reserved + * PSU_USB3_0_XHCI_GUCTL1_RESERVED_9 0x1 + + * Global User Control Register 1 + * (OFFSET, MASK, VALUE) (0XFE20C11C, 0x00000600U ,0x00000600U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUCTL1_OFFSET, 0x00000600U, 0x00000600U); +/*##################################################################### */ + + /* + * Register : GUCTL @ 0XFE20C12C + + * Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th + * e Auto Retry feature. For IN transfers (non-isochronous) that encounter + * data packets with CRC errors or internal overrun scenarios, the auto ret + * ry feature causes the Host core to reply to the device with a non-termin + * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N + * umP != 0). If the Auto Retry feature is disabled (default), the core wil + * l respond with a terminating retry ACK (that is, an ACK transaction pack + * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut + * o Retry Enabled Note: This bit is also applicable to the device mode. + * PSU_USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN 0x1 + + * Global User Control Register: This register provides a few options for t + * he software to control the core behavior in the Host mode. Most of the o + * ptions are used to improve host inter-operability with different devices + * . + * (OFFSET, MASK, VALUE) (0XFE20C12C, 0x00004000U ,0x00004000U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUCTL_OFFSET, 0x00004000U, 0x00004000U); +/*##################################################################### */ + + /* + * UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCO + * RRECT RESET VALUES IN SILICON. + */ + /* + * Register : ATTR_25 @ 0XFD480064 + + * If TRUE Completion Timeout Disable is supported. This is required to be + * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi + * ce Capability 2 [4]; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1 + + * ATTR_25 + * (OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x00000200U, 0x00000200U); +/*##################################################################### */ + + /* + * PCIE SETTINGS + */ + /* + * Register : ATTR_7 @ 0XFD48001C + + * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0x0004; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0 + + * ATTR_7 + * (OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_7_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_8 @ 0XFD480020 + + * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0xFFF0; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0 + + * ATTR_8 + * (OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_8_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_9 @ 0XFD480024 + + * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0 + + * ATTR_9 + * (OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_9_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_10 @ 0XFD480028 + + * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0 + + * ATTR_10 + * (OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_10_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_11 @ 0XFD48002C + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFFF + * PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF + + * ATTR_11 + * (OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_11_OFFSET, 0x0000FFFFU, 0x0000FFFFU); +/*##################################################################### */ + + /* + * Register : ATTR_12 @ 0XFD480030 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0x00FF + * PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF + + * ATTR_12 + * (OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_12_OFFSET, 0x0000FFFFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : ATTR_13 @ 0XFD480034 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0 + + * ATTR_13 + * (OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_13_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_14 @ 0XFD480038 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0xFFFF + * PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF + + * ATTR_14 + * (OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_14_OFFSET, 0x0000FFFFU, 0x0000FFFFU); +/*##################################################################### */ + + /* + * Register : ATTR_15 @ 0XFD48003C + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFF0 + * PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0 + + * ATTR_15 + * (OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_15_OFFSET, 0x0000FFFFU, 0x0000FFF0U); +/*##################################################################### */ + + /* + * Register : ATTR_16 @ 0XFD480040 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0xFFF0 + * PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0 + + * ATTR_16 + * (OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_16_OFFSET, 0x0000FFFFU, 0x0000FFF0U); +/*##################################################################### */ + + /* + * Register : ATTR_17 @ 0XFD480044 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 + * PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1 + + * ATTR_17 + * (OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_17_OFFSET, 0x0000FFFFU, 0x0000FFF1U); +/*##################################################################### */ + + /* + * Register : ATTR_18 @ 0XFD480048 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 + * PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1 + + * ATTR_18 + * (OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_18_OFFSET, 0x0000FFFFU, 0x0000FFF1U); +/*##################################################################### */ + + /* + * Register : ATTR_27 @ 0XFD48006C + + * Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1 + * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa + * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo + * rted; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1 + + * Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca + * n withstand on transitions from L1 state to L0 (if L1 state supported). + * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to + * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For + * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0 + + * ATTR_27 + * (OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_27_OFFSET, 0x00000738U, 0x00000100U); +/*##################################################################### */ + + /* + * Register : ATTR_50 @ 0XFD4800C8 + + * Identifies the type of device/port as follows: 0000b PCI Express Endpoin + * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P + * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110 + * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X + * Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre + * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM + * _FACING settings.; EP=0x0000; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4 + + * PCIe Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x009C; + * RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0 + + * ATTR_50 + * (OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_50_OFFSET, 0x0000FFF0U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : ATTR_105 @ 0XFD4801A4 + + * Number of credits that should be advertised for Completion data received + * on Virtual Channel 0. The bytes advertised must be less than or equal t + * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD + * PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD + + * ATTR_105 + * (OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_105_OFFSET, + 0x000007FFU, 0x000000CDU); +/*##################################################################### */ + + /* + * Register : ATTR_106 @ 0XFD4801A8 + + * Number of credits that should be advertised for Completion headers recei + * ved on Virtual Channel 0. The sum of the posted, non posted, and complet + * ion header credits must be <= 80; EP=0x0048; RP=0x0024 + * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24 + + * Number of credits that should be advertised for Non-Posted headers recei + * ved on Virtual Channel 0. The number of non posted data credits advertis + * ed by the block is equal to the number of non posted header credits. The + * sum of the posted, non posted, and completion header credits must be <= + * 80; EP=0x0004; RP=0x000C + * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC + + * ATTR_106 + * (OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_106_OFFSET, + 0x00003FFFU, 0x00000624U); +/*##################################################################### */ + + /* + * Register : ATTR_107 @ 0XFD4801AC + + * Number of credits that should be advertised for Non-Posted data received + * on Virtual Channel 0. The number of non posted data credits advertised + * by the block is equal to two times the number of non posted header credi + * ts if atomic operations are supported or is equal to the number of non p + * osted header credits if atomic operations are not supported. The bytes a + * dvertised must be less than or equal to the bram bytes available. See VC + * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 + * PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18 + + * ATTR_107 + * (OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_107_OFFSET, + 0x000007FFU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : ATTR_108 @ 0XFD4801B0 + + * Number of credits that should be advertised for Posted data received on + * Virtual Channel 0. The bytes advertised must be less than or equal to th + * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 + * PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5 + + * ATTR_108 + * (OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_108_OFFSET, + 0x000007FFU, 0x000000B5U); +/*##################################################################### */ + + /* + * Register : ATTR_109 @ 0XFD4801B4 + + * Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_ + * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0 + + * Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim + * TRUE == trim.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1 + + * Enables ECRC check on received TLP's 0 == don't check 1 == always check + * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP= + * 0x0003; RP=0x0003 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3 + + * Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). + * Calculated from max payload size supported and the number of brams conf + * igured for transmit; EP=0x001C; RP=0x001C + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c + + * Number of credits that should be advertised for Posted headers received + * on Virtual Channel 0. The sum of the posted, non posted, and completion + * header credits must be <= 80; EP=0x0004; RP=0x0020 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20 + + * ATTR_109 + * (OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_109_OFFSET, + 0x0000FFFFU, 0x00007E20U); +/*##################################################################### */ + + /* + * Register : ATTR_34 @ 0XFD480088 + + * Specifies values to be transferred to Header Type register. Bit 7 should + * be set to '0' indicating single-function device. Bit 0 identifies heade + * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; + * RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1 + + * ATTR_34 + * (OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_34_OFFSET, 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : ATTR_53 @ 0XFD4800D4 + + * PM Capability's Next Capability Offset pointer to the next item in the c + * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP + * =0x0060 + * PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60 + + * ATTR_53 + * (OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_53_OFFSET, 0x000000FFU, 0x00000060U); +/*##################################################################### */ + + /* + * Register : ATTR_41 @ 0XFD4800A4 + + * MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont + * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure; + * EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0 + + * Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 + + * MSI Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x0060; R + * P=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0 + + * Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 + + * ATTR_41 + * (OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_41_OFFSET, 0x000003FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_97 @ 0XFD480184 + + * Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b + * x4, 001000b x8.; EP=0x0004; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1 + + * Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1 + * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1 + + * ATTR_97 + * (OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_97_OFFSET, 0x00000FFFU, 0x00000041U); +/*##################################################################### */ + + /* + * Register : ATTR_100 @ 0XFD480190 + + * TRUE specifies upstream-facing port. FALSE specifies downstream-facing p + * ort.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0 + + * ATTR_100 + * (OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_100_OFFSET, + 0x00000040U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_101 @ 0XFD480194 + + * Enable the routing of message TLPs to the user through the TRN RX interf + * ace. A bit value of 1 enables routing of the message TLP to the user. Me + * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 + * - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I + * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit + * 10 PME_Turn_Off; EP=0x0000; RP=0x07FF + * PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF + + * Disable BAR filtering. Does not change the behavior of the bar hit outpu + * ts; EP=0x0000; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1 + + * ATTR_101 + * (OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_101_OFFSET, + 0x0000FFE2U, 0x0000FFE2U); +/*##################################################################### */ + + /* + * Register : ATTR_37 @ 0XFD480094 + + * Link Bandwidth notification capability. Indicates support for the link b + * andwidth notification status and interrupt mechanism. Required for Root. + * ; EP=0x0000; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1 + + * Maximum Link Speed. Valid settings are: 0001b [2.5 GT/s], 0010b [5.0 GT/ + * s and 2.5 GT/s].; EP=0x0002; RP=0x0002 + * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_MAX_LINK_SPEED 0x2 + + * Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op + * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001 + * ; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1 + + * ATTR_37 + * (OFFSET, MASK, VALUE) (0XFD480094, 0x00007E00U ,0x00004A00U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_37_OFFSET, 0x00007E00U, 0x00004A00U); +/*##################################################################### */ + + /* + * Register : ATTR_93 @ 0XFD480174 + + * Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value + * (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU + * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1 + + * Sets a user-defined timeout for the Replay Timer to force cause the retr + * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_ + * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att + * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.; + * EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000 + + * ATTR_93 + * (OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_93_OFFSET, 0x0000FFFFU, 0x00009000U); +/*##################################################################### */ + + /* + * Register : ID @ 0XFD480200 + + * Device ID for the the PCIe Cap Structure Device ID field + * PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd011 + + * Vendor ID for the PCIe Cap Structure Vendor ID field + * PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee + + * ID + * (OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED011U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ID_OFFSET, 0xFFFFFFFFU, 0x10EED011U); +/*##################################################################### */ + + /* + * Register : SUBSYS_ID @ 0XFD480204 + + * Subsystem ID for the the PCIe Cap Structure Subsystem ID field + * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7 + + * Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field + * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee + + * SUBSYS_ID + * (OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U) + */ + PSU_Mask_Write(PCIE_ATTRIB_SUBSYS_ID_OFFSET, + 0xFFFFFFFFU, 0x10EE0007U); +/*##################################################################### */ + + /* + * Register : REV_ID @ 0XFD480208 + + * Revision ID for the the PCIe Cap Structure + * PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0 + + * REV_ID + * (OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_REV_ID_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_24 @ 0XFD480060 + + * Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000 + * PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x8000 + + * ATTR_24 + * (OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00008000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_24_OFFSET, 0x0000FFFFU, 0x00008000U); +/*##################################################################### */ + + /* + * Register : ATTR_25 @ 0XFD480064 + + * Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6 + + * INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] + * to be hardwired to 0.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0 + + * ATTR_25 + * (OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x000001FFU, 0x00000006U); +/*##################################################################### */ + + /* + * Register : ATTR_4 @ 0XFD480010 + + * Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 + + * Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 + + * ATTR_4 + * (OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_4_OFFSET, 0x00001000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_89 @ 0XFD480164 + + * VSEC's Next Capability Offset pointer to the next item in the capabiliti + * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140 + * PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0 + + * ATTR_89 + * (OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_89_OFFSET, 0x00001FFEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_79 @ 0XFD48013C + + * CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the + * Root Capabilities register.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1 + + * ATTR_79 + * (OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_79_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : ATTR_43 @ 0XFD4800AC + + * Indicates that the MSIX structures exists. If this is FALSE, then the MS + * IX structure cannot be accessed via either the link or the management po + * rt.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0 + + * ATTR_43 + * (OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_43_OFFSET, 0x00000100U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_48 @ 0XFD4800C0 + + * MSI-X Table Size. This value is transferred to the MSI-X Message Control + * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does + * not implement the table; that must be implemented in user logic.; EP=0x0 + * 003; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0 + + * ATTR_48 + * (OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_48_OFFSET, 0x000007FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_46 @ 0XFD4800B8 + + * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0 + + * ATTR_46 + * (OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_46_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_47 @ 0XFD4800BC + + * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0 + + * ATTR_47 + * (OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_47_OFFSET, 0x00001FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_44 @ 0XFD4800B0 + + * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0 + + * ATTR_44 + * (OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_44_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_45 @ 0XFD4800B4 + + * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0 + + * ATTR_45 + * (OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_45_OFFSET, 0x0000FFF8U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CB @ 0XFD48031C + + * DT837748 Enable + * PSU_PCIE_ATTRIB_CB_CB1 0x0 + + * ECO Register 1 + * (OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_CB_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_35 @ 0XFD48008C + + * Active State PM Support. Indicates the level of active state power manag + * ement supported by the selected PCI Express Link, encoded as follows: 0 + * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte + * d.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0 + + * Data Link Layer Link Active status notification is supported. This is op + * tional for Upstream ports.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP 1 + + * ATTR_35 + * (OFFSET, MASK, VALUE) (0XFD48008C, 0x0000B000U ,0x00008000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_35_OFFSET, 0x0000B000U, 0x00008000U); +/*##################################################################### */ + + /* + * PUTTING PCIE CONTROL IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00020000U, 0x00000000U); +/*##################################################################### */ + + /* + * PCIE GPIO RESET + */ + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0020U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * CHECK PLL LOCK FOR LANE0 + */ + /* + * Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE1 + */ + /* + * Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE2 + */ + /* + * Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE3 + */ + /* + * Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * SATA AHCI VENDOR SETTING + */ + /* + * Register : PP2C @ 0XFD0C00AC + + * CIBGMN: COMINIT Burst Gap Minimum. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18 + + * CIBGMX: COMINIT Burst Gap Maximum. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40 + + * CIBGN: COMINIT Burst Gap Nominal. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18 + + * CINMP: COMINIT Negate Minimum Period. + * PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28 + + * PP2C - Port Phy2Cfg Register. This register controls the configuration o + * f the Phy Control OOB timing for the COMINIT parameters for either Port + * 0 or Port 1. The Port configured is controlled by the value programmed i + * nto the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP2C_OFFSET, + 0xFFFFFFFFU, 0x28184018U); +/*##################################################################### */ + + /* + * Register : PP3C @ 0XFD0C00B0 + + * CWBGMN: COMWAKE Burst Gap Minimum. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06 + + * CWBGMX: COMWAKE Burst Gap Maximum. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14 + + * CWBGN: COMWAKE Burst Gap Nominal. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08 + + * CWNMP: COMWAKE Negate Minimum Period. + * PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E + + * PP3C - Port Phy3CfgRegister. This register controls the configuration of + * the Phy Control OOB timing for the COMWAKE parameters for either Port 0 + * or Port 1. The Port configured is controlled by the value programmed in + * to the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP3C_OFFSET, + 0xFFFFFFFFU, 0x0E081406U); +/*##################################################################### */ + + /* + * Register : PP4C @ 0XFD0C00B4 + + * BMX: COM Burst Maximum. + * PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13 + + * BNM: COM Burst Nominal. + * PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08 + + * SFD: Signal Failure Detection, if the signal detection de-asserts for a + * time greater than this then the OOB detector will determine this is a li + * ne idle and cause the PhyInit state machine to exit the Phy Ready State. + * A value of zero disables the Signal Failure Detector. The value is base + * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving + * a nominal time of 500ns based on a 150MHz PMCLK. + * PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A + + * PTST: Partial to Slumber timer value, specific delay the controller shou + * ld apply while in partial before entering slumber. The value is bases on + * the system clock divided by 128, total delay = (Sys Clock Period) * PTS + * T * 128 + * PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06 + + * PP4C - Port Phy4Cfg Register. This register controls the configuration o + * f the Phy Control Burst timing for the COM parameters for either Port 0 + * or Port 1. The Port configured is controlled by the value programmed int + * o the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP4C_OFFSET, + 0xFFFFFFFFU, 0x064A0813U); +/*##################################################################### */ + + /* + * Register : PP5C @ 0XFD0C00B8 + + * RIT: Retry Interval Timer. The calculated value divided by two, the lowe + * r digit of precision is not needed. + * PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4 + + * RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev + * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a + * fast SERDES it is suggested that this value be 54.2us / 4 + * PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF + + * PP5C - Port Phy5Cfg Register. This register controls the configuration o + * f the Phy Control Retry Interval timing for either Port 0 or Port 1. The + * Port configured is controlled by the value programmed into the Port Con + * fig Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP5C_OFFSET, + 0xFFFFFFFFU, 0x3FFC96A4U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_resetin_init_data(void) +{ + /* + * PUTTING SERDES PERIPHERAL IN RESET + */ + /* + * PUTTING USB0 IN RESET + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X1 + + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X1 + + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X1 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000540U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000540U, 0x00000540U); +/*##################################################################### */ + + /* + * PUTTING GEM0 IN RESET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 + + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X1 + + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * PUTTING SATA IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X1 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000002U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000002U); +/*##################################################################### */ + + /* + * PUTTING PCIE IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1 + + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000E0000U, 0x000E0000U); +/*##################################################################### */ + + /* + * PUTTING DP IN RESET + */ + /* + * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238 + + * Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 + * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA + + * Control PHY Power down + * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x0000000AU) + */ + PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET, + 0x0000000FU, 0x0000000AU); +/*##################################################################### */ + + /* + * Register : DP_PHY_RESET @ 0XFD4A0200 + + * Set to '1' to hold the GT in reset. Clear to release. + * PSU_DP_DP_PHY_RESET_GT_RESET 0X1 + + * Reset the transmitter PHY. + * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000002U) + */ + PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000002U); +/*##################################################################### */ + + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X1 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00010000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00010000U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_ps_pl_isolation_removal_data(void) +{ + /* + * PS-PL POWER UP REQUEST + */ + /* + * Register : REQ_PWRUP_INT_EN @ 0XFFD80118 + + * Power-up Request Interrupt Enable for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1 + + * Power-up Request Interrupt Enable Register. Writing a 1 to this location + * will unmask the interrupt. + * (OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U) + */ + PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET, + 0x00800000U, 0x00800000U); +/*##################################################################### */ + + /* + * Register : REQ_PWRUP_TRIG @ 0XFFD80120 + + * Power-up Request Trigger for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1 + + * Power-up Request Trigger Register. A write of one to this location will + * generate a power-up request to the PMU. + * (OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U) + */ + PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET, + 0x00800000U, 0x00800000U); +/*##################################################################### */ + + /* + * POLL ON PL POWER STATUS + */ + /* + * Register : REQ_PWRUP_STATUS @ 0XFFD80110 + + * Power-up Request Status for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL 1 + * (OFFSET, MASK, VALUE) (0XFFD80110, 0x00800000U ,0x00000000U) + */ + mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET, + 0x00800000U, 0x00000000U); + +/*##################################################################### */ + + + return 1; +} +unsigned long psu_afi_config(void) +{ + /* + * AFI RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * AF_FM0 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM0_RESET 0 + + * AF_FM1 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM1_RESET 0 + + * AF_FM2 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM2_RESET 0 + + * AF_FM3 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM3_RESET 0 + + * AF_FM4 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM4_RESET 0 + + * AF_FM5 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM5_RESET 0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00001F80U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00001F80U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * AFI FM 6 + * PSU_CRL_APB_RST_LPD_TOP_AFI_FM6_RESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00080000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00080000U, 0x00000000U); +/*##################################################################### */ + + /* + * AFIFM INTERFACE WIDTH + */ + /* + * Register : afi_fs @ 0XFF419000 + + * Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved + * PSU_LPD_SLCR_AFI_FS_DW_SS2_SEL 0x2 + + * afi fs SLCR control register. Do not change the bits durin + * (OFFSET, MASK, VALUE) (0XFF419000, 0x00000300U ,0x00000200U) + */ + PSU_Mask_Write(LPD_SLCR_AFI_FS_OFFSET, 0x00000300U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : AFIFM_RDCTRL @ 0XFD380000 + + * Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b + * 10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128-bit enabled + * PSU_AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH 0x0 + + * Read Channel Control Register + * (OFFSET, MASK, VALUE) (0XFD380000, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(AFIFM2_AFIFM_RDCTRL_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : AFIFM_WRCTRL @ 0XFD380014 + + * Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2' + * b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128-bit enabled + * PSU_AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH 0x0 + + * Write Channel Control Register + * (OFFSET, MASK, VALUE) (0XFD380014, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(AFIFM2_AFIFM_WRCTRL_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_ps_pl_reset_config_data(void) +{ + /* + * PS PL RESET SEQUENCE + */ + /* + * FABRIC RESET USING EMIO + */ + /* + * Register : MASK_DATA_5_MSW @ 0XFF0A002C + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW 0x8000 + + * Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A002C, 0xFFFF0000U ,0x80000000U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_5_MSW_OFFSET, + 0xFFFF0000U, 0x80000000U); +/*##################################################################### */ + + /* + * Register : DIRM_5 @ 0XFF0A0344 + + * Operation is the same as DIRM_0[DIRECTION_0] + * PSU_GPIO_DIRM_5_DIRECTION_5 0x80000000 + + * Direction mode (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DIRM_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + /* + * Register : OEN_5 @ 0XFF0A0348 + + * Operation is the same as OEN_0[OP_ENABLE_0] + * PSU_GPIO_OEN_5_OP_ENABLE_5 0x80000000 + + * Output enable (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_OEN_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + /* + * Register : DATA_5 @ 0XFF0A0054 + + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0x80000000 + + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + mask_delay(1); + +/*##################################################################### */ + + /* + * FABRIC RESET USING DATA_5 TOGGLE + */ + /* + * Register : DATA_5 @ 0XFF0A0054 + + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0X00000000 + + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + mask_delay(1); + +/*##################################################################### */ + + /* + * FABRIC RESET USING DATA_5 TOGGLE + */ + /* + * Register : DATA_5 @ 0XFF0A0054 + + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0x80000000 + + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + + return 1; +} + +unsigned long psu_ddr_phybringup_data(void) +{ + + + unsigned int regval = 0; + + unsigned int pll_retry = 10; + + unsigned int pll_locked = 0; + + + while ((pll_retry > 0) && (!pll_locked)) { + + Xil_Out32(0xFD080004, 0x00040010);/*PIR*/ + Xil_Out32(0xFD080004, 0x00040011);/*PIR*/ + + while ((Xil_In32(0xFD080030) & 0x1) != 1) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31;/*PGSR0*/ + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16;/*DX0GSR0*/ + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16 ; /*DX2GSR0*/ + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16;/*DX4GSR0*/ + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16;/*DX6GSR0*/ + pll_retry--; + } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | + (pll_retry << 16));/*GPR0*/ + if(!pll_locked) + return(0); + + Xil_Out32(0xFD080004U, 0x00040063U); + /* PHY BRINGUP SEQ */ + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + /* poll for PHY initialization to complete */ + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >>18); + if(regval != 0) { + return(0); + } + +/* Run Vref training in static read mode*/ + Xil_Out32(0xFD080200U, 0x100091C7U); + int cur_R006_tREFPRD; + + cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + + Xil_Out32(0xFD080004, 0x00060001); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while ((regval & 0x80004001) != 0x80004001) { + /*PUB_PGSR0*/ + regval = Xil_In32(0xFD080030); + } + +/* Vref training is complete*/ +/* Check if any training errors then exit*/ + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >>18); + if(regval != 0) { + return(0); + } + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); +/*Vref training is complete, disabling static read mode*/ + Xil_Out32(0xFD080200U, 0x800091C7U); + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + + + Xil_Out32(0xFD080004, 0x0000C001); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while ((regval & 0x80000C01) != 0x80000C01) { + /*PUB_PGSR0*/ + regval = Xil_In32(0xFD080030); + } + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + +return 1; +} + +/** + * CRL_APB Base Address + */ +#define CRL_APB_BASEADDR 0XFF5E0000U +#define CRL_APB_RST_LPD_IOU0 ((CRL_APB_BASEADDR) + 0X00000230U) +#define CRL_APB_RST_LPD_IOU1 ((CRL_APB_BASEADDR) + 0X00000234U) +#define CRL_APB_RST_LPD_IOU2 ((CRL_APB_BASEADDR) + 0X00000238U) +#define CRL_APB_RST_LPD_TOP ((CRL_APB_BASEADDR) + 0X0000023CU) +#define CRL_APB_IOU_SWITCH_CTRL ((CRL_APB_BASEADDR) + 0X0000009CU) + +/** + * CRF_APB Base Address + */ +#define CRF_APB_BASEADDR 0XFD1A0000U + +#define CRF_APB_RST_FPD_TOP ((CRF_APB_BASEADDR) + 0X00000100U) +#define CRF_APB_GPU_REF_CTRL ((CRF_APB_BASEADDR) + 0X00000084U) +#define CRF_APB_RST_DDR_SS ((CRF_APB_BASEADDR) + 0X00000108U) +#define PSU_MASK_POLL_TIME 1100000 + +/** + * * Register: CRF_APB_DPLL_CTRL + */ +#define CRF_APB_DPLL_CTRL ((CRF_APB_BASEADDR) + 0X0000002C) + + +#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_DPLL_CTRL_DIV2_WIDTH 1 + +#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_DPLL_CTRL_FBDIV_WIDTH 7 + +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_WIDTH 1 + +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_WIDTH 1 + +/** + * * Register: CRF_APB_DPLL_CFG + */ +#define CRF_APB_DPLL_CFG ((CRF_APB_BASEADDR) + 0X00000030) + +#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_DPLL_CFG_LOCK_DLY_WIDTH 7 + +#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_DPLL_CFG_LOCK_CNT_WIDTH 10 + +#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_DPLL_CFG_LFHF_WIDTH 2 + +#define CRF_APB_DPLL_CFG_CP_SHIFT 5 +#define CRF_APB_DPLL_CFG_CP_WIDTH 4 + +#define CRF_APB_DPLL_CFG_RES_SHIFT 0 +#define CRF_APB_DPLL_CFG_RES_WIDTH 4 + +/** + * Register: CRF_APB_PLL_STATUS + */ +#define CRF_APB_PLL_STATUS ((CRF_APB_BASEADDR) + 0X00000044) + + +static int mask_pollOnValue(u32 add, u32 mask, u32 value) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; + int i = 0; + + while ((*addr & mask) != value) { + if (i == PSU_MASK_POLL_TIME) + return 0; + i++; + } + return 1; +} + +static int mask_poll(u32 add, u32 mask) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; + int i = 0; + + while (!(*addr & mask)) { + if (i == PSU_MASK_POLL_TIME) + return 0; + i++; + } + return 1; +} + +static void mask_delay(u32 delay) +{ + usleep(delay); +} + +static u32 mask_read(u32 add, u32 mask) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; + u32 val = (*addr & mask); + return val; +} + +//Kishore -- ILL calibration code begins +//ILL calibration code begins +#define SERDES_L0_TM_PLL_DIG_33 0XFD402084 +#define SERDES_L1_TM_PLL_DIG_33 0XFD406084 +#define SERDES_L2_TM_PLL_DIG_33 0XFD40A084 +#define SERDES_L3_TM_PLL_DIG_33 0XFD40E084 + +#define SERDES_L0_TM_ANA_BYP_4 0XFD401010 +#define SERDES_L1_TM_ANA_BYP_4 0XFD405010 +#define SERDES_L2_TM_ANA_BYP_4 0XFD409010 +#define SERDES_L3_TM_ANA_BYP_4 0XFD40D010 + +#define SERDES_L0_TM_ANA_BYP_7 0XFD401018 +#define SERDES_L1_TM_ANA_BYP_7 0XFD405018 +#define SERDES_L2_TM_ANA_BYP_7 0XFD409018 +#define SERDES_L3_TM_ANA_BYP_7 0XFD40D018 + +#define SERDES_L0_TM_E_ILL7 0XFD40193C +#define SERDES_L1_TM_E_ILL7 0XFD40593C +#define SERDES_L2_TM_E_ILL7 0XFD40993C +#define SERDES_L3_TM_E_ILL7 0XFD40D93C + +#define SERDES_L0_TM_IQ_ILL7 0XFD401910 +#define SERDES_L1_TM_IQ_ILL7 0XFD405910 +#define SERDES_L2_TM_IQ_ILL7 0XFD409910 +#define SERDES_L3_TM_IQ_ILL7 0XFD40D910 + +#define SERDES_L0_TX_DIG_TM_61 0XFD4000F4 +#define SERDES_L1_TX_DIG_TM_61 0XFD4040F4 +#define SERDES_L2_TX_DIG_TM_61 0XFD4080F4 +#define SERDES_L3_TX_DIG_TM_61 0XFD40C0F4 + +#define SERDES_L0_TM_DIG_6 0XFD40106C +#define SERDES_L1_TM_DIG_6 0XFD40506C +#define SERDES_L2_TM_DIG_6 0XFD40906C +#define SERDES_L3_TM_DIG_6 0XFD40D06C + +#define SERDES_L0_TM_IQ_ILL1 0XFD4018F8 +#define SERDES_L0_TM_IQ_ILL2 0XFD4018FC +#define SERDES_L0_TM_ILL11 0XFD40198C +#define SERDES_L0_TM_ILL12 0XFD401990 +#define SERDES_L0_TM_E_ILL1 0XFD401924 +#define SERDES_L0_TM_E_ILL2 0XFD401928 +#define SERDES_L0_TM_IQ_ILL3 0XFD401900 +#define SERDES_L0_TM_E_ILL3 0XFD40192C +#define SERDES_L0_TM_ILL8 0XFD401980 +#define SERDES_L0_TM_IQ_ILL8 0XFD401914 +#define SERDES_L0_TM_IQ_ILL9 0XFD401918 +#define SERDES_L0_TM_E_ILL8 0XFD401940 +#define SERDES_L0_TM_E_ILL9 0XFD401944 +#define SERDES_L0_TM_ILL13 0XFD401994 +#define SERDES_L1_TM_MISC2 0XFD40589C +#define SERDES_L1_TM_IQ_ILL1 0XFD4058F8 +#define SERDES_L1_TM_IQ_ILL2 0XFD4058FC +#define SERDES_L1_TM_ILL11 0XFD40598C +#define SERDES_L1_TM_ILL12 0XFD405990 +#define SERDES_L1_TM_E_ILL1 0XFD405924 +#define SERDES_L1_TM_E_ILL2 0XFD405928 +#define SERDES_L1_TM_IQ_ILL3 0XFD405900 +#define SERDES_L1_TM_E_ILL3 0XFD40592C +#define SERDES_L1_TM_ILL8 0XFD405980 +#define SERDES_L1_TM_IQ_ILL8 0XFD405914 +#define SERDES_L1_TM_IQ_ILL9 0XFD405918 +#define SERDES_L1_TM_E_ILL8 0XFD405940 +#define SERDES_L1_TM_E_ILL9 0XFD405944 +#define SERDES_L1_TM_ILL13 0XFD405994 +#define SERDES_L2_TM_MISC2 0XFD40989C +#define SERDES_L2_TM_IQ_ILL1 0XFD4098F8 +#define SERDES_L2_TM_IQ_ILL2 0XFD4098FC +#define SERDES_L2_TM_ILL11 0XFD40998C +#define SERDES_L2_TM_ILL12 0XFD409990 +#define SERDES_L2_TM_E_ILL1 0XFD409924 +#define SERDES_L2_TM_E_ILL2 0XFD409928 +#define SERDES_L2_TM_IQ_ILL3 0XFD409900 +#define SERDES_L2_TM_E_ILL3 0XFD40992C +#define SERDES_L2_TM_ILL8 0XFD409980 +#define SERDES_L2_TM_IQ_ILL8 0XFD409914 +#define SERDES_L2_TM_IQ_ILL9 0XFD409918 +#define SERDES_L2_TM_E_ILL8 0XFD409940 +#define SERDES_L2_TM_E_ILL9 0XFD409944 +#define SERDES_L2_TM_ILL13 0XFD409994 +#define SERDES_L3_TM_MISC2 0XFD40D89C +#define SERDES_L3_TM_IQ_ILL1 0XFD40D8F8 +#define SERDES_L3_TM_IQ_ILL2 0XFD40D8FC +#define SERDES_L3_TM_ILL11 0XFD40D98C +#define SERDES_L3_TM_ILL12 0XFD40D990 +#define SERDES_L3_TM_E_ILL1 0XFD40D924 +#define SERDES_L3_TM_E_ILL2 0XFD40D928 +#define SERDES_L3_TM_IQ_ILL3 0XFD40D900 +#define SERDES_L3_TM_E_ILL3 0XFD40D92C +#define SERDES_L3_TM_ILL8 0XFD40D980 +#define SERDES_L3_TM_IQ_ILL8 0XFD40D914 +#define SERDES_L3_TM_IQ_ILL9 0XFD40D918 +#define SERDES_L3_TM_E_ILL8 0XFD40D940 +#define SERDES_L3_TM_E_ILL9 0XFD40D944 +#define SERDES_L3_TM_ILL13 0XFD40D994 +#undef SERDES_UPHY_SPARE0 +#define SERDES_UPHY_SPARE0 0XFD410098 +#undef SERDES_UPHY_SPARE1 +#define SERDES_UPHY_SPARE1 0XFD41009C +#undef SERDES_UPHY_SPARE2 +#define SERDES_UPHY_SPARE2 0XFD4100A0 +#undef SERDES_UPHY_SPARE3 +#define SERDES_UPHY_SPARE3 0XFD4100A4 + +#define SERDES_L0_PLL_FBDIV_FRAC_3_MSB 0xFD402360 +#define SERDES_L1_PLL_FBDIV_FRAC_3_MSB 0xFD406360 +#define SERDES_L2_PLL_FBDIV_FRAC_3_MSB 0xFD40A360 +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB 0xFD40E360 + +#define SERDES_L0_PLL_STATUS_READ_1 0XFD4023E4 +#define SERDES_L0_TM_MISC_ST_0 0XFD401AC8 +#define SERDES_L1_PLL_STATUS_READ_1 0XFD4063E4 +#define SERDES_L1_TM_MISC_ST_0 0XFD405AC8 +#define SERDES_L2_PLL_STATUS_READ_1 0XFD40A3E4 +#define SERDES_L2_TM_MISC_ST_0 0XFD409AC8 +#define SERDES_L3_PLL_STATUS_READ_1 0XFD40E3E4 +#define SERDES_L3_TM_MISC_ST_0 0XFD40DAC8 + +#define SERDES_L0_BIST_CTRL_1 0xFD403004 +#define SERDES_L0_BIST_CTRL_2 0xFD403008 +#define SERDES_L0_BIST_RUN_LEN_L 0xFD40300C +#define SERDES_L0_BIST_ERR_INJ_POINT_L 0xFD403010 +#define SERDES_L0_BIST_RUNLEN_ERR_INJ_H 0xFD403014 +#define SERDES_L0_BIST_IDLE_TIME 0xFD403018 +#define SERDES_L0_BIST_MARKER_L 0xFD40301C +#define SERDES_L0_BIST_IDLE_CHAR_L 0xFD403020 +#define SERDES_L0_BIST_MARKER_IDLE_H 0xFD403024 +#define SERDES_L0_BIST_LOW_PULSE_TIME 0xFD403028 +#define SERDES_L0_BIST_TOTAL_PULSE_TIME 0xFD40302C +#define SERDES_L0_BIST_TEST_PAT_1 0xFD403030 +#define SERDES_L0_BIST_TEST_PAT_2 0xFD403034 +#define SERDES_L0_BIST_TEST_PAT_3 0xFD403038 +#define SERDES_L0_BIST_TEST_PAT_4 0xFD40303C +#define SERDES_L0_BIST_TEST_PAT_MSBS 0xFD403040 +#define SERDES_L0_BIST_PKT_NUM 0xFD403044 +#define SERDES_L0_BIST_FRM_IDLE_TIME 0xFD403048 +#define SERDES_L0_BIST_PKT_CTR_L 0xFD40304C +#define SERDES_L0_BIST_PKT_CTR_H 0xFD403050 +#define SERDES_L0_BIST_ERR_CTR_L 0xFD403054 +#define SERDES_L0_BIST_ERR_CTR_H 0xFD403058 +#define SERDES_L0_BIST_FILLER_OUT 0xFD403068 +#define SERDES_L0_BIST_FORCE_MK_RST 0xFD40306C + +#define SERDES_L1_BIST_CTRL_1 0xFD407004 +#define SERDES_L1_BIST_CTRL_2 0xFD407008 +#define SERDES_L1_BIST_RUN_LEN_L 0xFD40700C +#define SERDES_L1_BIST_ERR_INJ_POINT_L 0xFD407010 +#define SERDES_L1_BIST_RUNLEN_ERR_INJ_H 0xFD407014 +#define SERDES_L1_BIST_IDLE_TIME 0xFD407018 +#define SERDES_L1_BIST_MARKER_L 0xFD40701C +#define SERDES_L1_BIST_IDLE_CHAR_L 0xFD407020 +#define SERDES_L1_BIST_MARKER_IDLE_H 0xFD407024 +#define SERDES_L1_BIST_LOW_PULSE_TIME 0xFD407028 +#define SERDES_L1_BIST_TOTAL_PULSE_TIME 0xFD40702C +#define SERDES_L1_BIST_TEST_PAT_1 0xFD407030 +#define SERDES_L1_BIST_TEST_PAT_2 0xFD407034 +#define SERDES_L1_BIST_TEST_PAT_3 0xFD407038 +#define SERDES_L1_BIST_TEST_PAT_4 0xFD40703C +#define SERDES_L1_BIST_TEST_PAT_MSBS 0xFD407040 +#define SERDES_L1_BIST_PKT_NUM 0xFD407044 +#define SERDES_L1_BIST_FRM_IDLE_TIME 0xFD407048 +#define SERDES_L1_BIST_PKT_CTR_L 0xFD40704C +#define SERDES_L1_BIST_PKT_CTR_H 0xFD407050 +#define SERDES_L1_BIST_ERR_CTR_L 0xFD407054 +#define SERDES_L1_BIST_ERR_CTR_H 0xFD407058 +#define SERDES_L1_BIST_FILLER_OUT 0xFD407068 +#define SERDES_L1_BIST_FORCE_MK_RST 0xFD40706C + +#define SERDES_L2_BIST_CTRL_1 0xFD40B004 +#define SERDES_L2_BIST_CTRL_2 0xFD40B008 +#define SERDES_L2_BIST_RUN_LEN_L 0xFD40B00C +#define SERDES_L2_BIST_ERR_INJ_POINT_L 0xFD40B010 +#define SERDES_L2_BIST_RUNLEN_ERR_INJ_H 0xFD40B014 +#define SERDES_L2_BIST_IDLE_TIME 0xFD40B018 +#define SERDES_L2_BIST_MARKER_L 0xFD40B01C +#define SERDES_L2_BIST_IDLE_CHAR_L 0xFD40B020 +#define SERDES_L2_BIST_MARKER_IDLE_H 0xFD40B024 +#define SERDES_L2_BIST_LOW_PULSE_TIME 0xFD40B028 +#define SERDES_L2_BIST_TOTAL_PULSE_TIME 0xFD40B02C +#define SERDES_L2_BIST_TEST_PAT_1 0xFD40B030 +#define SERDES_L2_BIST_TEST_PAT_2 0xFD40B034 +#define SERDES_L2_BIST_TEST_PAT_3 0xFD40B038 +#define SERDES_L2_BIST_TEST_PAT_4 0xFD40B03C +#define SERDES_L2_BIST_TEST_PAT_MSBS 0xFD40B040 +#define SERDES_L2_BIST_PKT_NUM 0xFD40B044 +#define SERDES_L2_BIST_FRM_IDLE_TIME 0xFD40B048 +#define SERDES_L2_BIST_PKT_CTR_L 0xFD40B04C +#define SERDES_L2_BIST_PKT_CTR_H 0xFD40B050 +#define SERDES_L2_BIST_ERR_CTR_L 0xFD40B054 +#define SERDES_L2_BIST_ERR_CTR_H 0xFD40B058 +#define SERDES_L2_BIST_FILLER_OUT 0xFD40B068 +#define SERDES_L2_BIST_FORCE_MK_RST 0xFD40B06C + +#define SERDES_L3_BIST_CTRL_1 0xFD40F004 +#define SERDES_L3_BIST_CTRL_2 0xFD40F008 +#define SERDES_L3_BIST_RUN_LEN_L 0xFD40F00C +#define SERDES_L3_BIST_ERR_INJ_POINT_L 0xFD40F010 +#define SERDES_L3_BIST_RUNLEN_ERR_INJ_H 0xFD40F014 +#define SERDES_L3_BIST_IDLE_TIME 0xFD40F018 +#define SERDES_L3_BIST_MARKER_L 0xFD40F01C +#define SERDES_L3_BIST_IDLE_CHAR_L 0xFD40F020 +#define SERDES_L3_BIST_MARKER_IDLE_H 0xFD40F024 +#define SERDES_L3_BIST_LOW_PULSE_TIME 0xFD40F028 +#define SERDES_L3_BIST_TOTAL_PULSE_TIME 0xFD40F02C +#define SERDES_L3_BIST_TEST_PAT_1 0xFD40F030 +#define SERDES_L3_BIST_TEST_PAT_2 0xFD40F034 +#define SERDES_L3_BIST_TEST_PAT_3 0xFD40F038 +#define SERDES_L3_BIST_TEST_PAT_4 0xFD40F03C +#define SERDES_L3_BIST_TEST_PAT_MSBS 0xFD40F040 +#define SERDES_L3_BIST_PKT_NUM 0xFD40F044 +#define SERDES_L3_BIST_FRM_IDLE_TIME 0xFD40F048 +#define SERDES_L3_BIST_PKT_CTR_L 0xFD40F04C +#define SERDES_L3_BIST_PKT_CTR_H 0xFD40F050 +#define SERDES_L3_BIST_ERR_CTR_L 0xFD40F054 +#define SERDES_L3_BIST_ERR_CTR_H 0xFD40F058 +#define SERDES_L3_BIST_FILLER_OUT 0xFD40F068 +#define SERDES_L3_BIST_FORCE_MK_RST 0xFD40F06C + +#define SERDES_TX_PROT_BUS_WIDTH 0xFD410040 +#define SERDES_RX_PROT_BUS_WIDTH 0xFD410044 +#define SERDES_LPBK_CTRL0 0xFD410038 +#define SERDES_LPBK_CTRL1 0xFD41003C +#define SERDES_L0_TM_DIG_22 0xFD4010AC +#define SERDES_L1_TM_DIG_22 0xFD4050AC +#define SERDES_L2_TM_DIG_22 0xFD4090AC +#define SERDES_L3_TM_DIG_22 0xFD40D0AC +#define SERDES_L0_DATA_BUS_WID 0xFD403060 +#define SERDES_L1_DATA_BUS_WID 0xFD407060 +#define SERDES_L2_DATA_BUS_WID 0xFD40B060 +#define SERDES_L3_DATA_BUS_WID 0xFD40F060 +#define SERDES_L0_TX_ANA_TM_3 0XFD40000C +#define SERDES_L1_TX_ANA_TM_3 0XFD40400C +#define SERDES_L2_TX_ANA_TM_3 0XFD40800C +#define SERDES_L3_TX_ANA_TM_3 0XFD40C00C + +#undef SERDES_PLL_REF_SEL0_OFFSET +#define SERDES_PLL_REF_SEL0_OFFSET 0xFD410000 +#undef SERDES_PLL_REF_SEL1_OFFSET +#define SERDES_PLL_REF_SEL1_OFFSET 0xFD410004 +#undef SERDES_PLL_REF_SEL2_OFFSET +#define SERDES_PLL_REF_SEL2_OFFSET 0xFD410008 +#undef SERDES_PLL_REF_SEL3_OFFSET +#define SERDES_PLL_REF_SEL3_OFFSET 0xFD41000C +#undef SERDES_ICM_CFG0_OFFSET +#define SERDES_ICM_CFG0_OFFSET 0xFD410010 +#undef SERDES_ICM_CFG1_OFFSET +#define SERDES_ICM_CFG1_OFFSET 0xFD410014 + +static int serdes_rst_seq (u32 lane3_protocol, u32 lane3_rate, u32 lane2_protocol, u32 lane2_rate, u32 lane1_protocol, u32 lane1_rate, u32 lane0_protocol, u32 lane0_rate) +{ + Xil_Out32(SERDES_UPHY_SPARE0, 0x00000000); + Xil_Out32(SERDES_L0_TM_ANA_BYP_4, 0x00000040); + Xil_Out32(SERDES_L1_TM_ANA_BYP_4, 0x00000040); + Xil_Out32(SERDES_L2_TM_ANA_BYP_4, 0x00000040); + Xil_Out32(SERDES_L3_TM_ANA_BYP_4, 0x00000040); + Xil_Out32(SERDES_L0_TM_PLL_DIG_33, 0x00000080); + Xil_Out32(SERDES_L1_TM_PLL_DIG_33, 0x00000080); + Xil_Out32(SERDES_L2_TM_PLL_DIG_33, 0x00000080); + Xil_Out32(SERDES_L3_TM_PLL_DIG_33, 0x00000080); + Xil_Out32(SERDES_UPHY_SPARE0, 0x00000004); + mask_delay(50); + if (lane0_rate == 1) Xil_Out32(SERDES_UPHY_SPARE0, 0x0000000E); + Xil_Out32(SERDES_UPHY_SPARE0, 0x00000006); + if (lane0_rate == 1) { + Xil_Out32(SERDES_L0_TX_ANA_TM_3, 0x00000004); + Xil_Out32(SERDES_L1_TX_ANA_TM_3, 0x00000004); + Xil_Out32(SERDES_L2_TX_ANA_TM_3, 0x00000004); + Xil_Out32(SERDES_L3_TX_ANA_TM_3, 0x00000004); + Xil_Out32(SERDES_UPHY_SPARE0, 0x00000007); + mask_delay (400); + Xil_Out32(SERDES_L0_TX_ANA_TM_3, 0x0000000C); + Xil_Out32(SERDES_L1_TX_ANA_TM_3, 0x0000000C); + Xil_Out32(SERDES_L2_TX_ANA_TM_3, 0x0000000C); + Xil_Out32(SERDES_L3_TX_ANA_TM_3, 0x0000000C); + mask_delay (15); + Xil_Out32(SERDES_UPHY_SPARE0, 0x0000000F); + mask_delay (100); + } + if (lane0_protocol != 0) mask_poll(SERDES_L0_PLL_STATUS_READ_1, 0x00000010U); + if (lane1_protocol != 0) mask_poll(SERDES_L1_PLL_STATUS_READ_1, 0x00000010U); + if (lane2_protocol != 0) mask_poll(SERDES_L2_PLL_STATUS_READ_1, 0x00000010U); + if (lane3_protocol != 0) mask_poll(SERDES_L3_PLL_STATUS_READ_1, 0x00000010U); + mask_delay(50); + Xil_Out32(SERDES_L0_TM_ANA_BYP_4, 0x000000C0); + Xil_Out32(SERDES_L1_TM_ANA_BYP_4, 0x000000C0); + Xil_Out32(SERDES_L2_TM_ANA_BYP_4, 0x000000C0); + Xil_Out32(SERDES_L3_TM_ANA_BYP_4, 0x000000C0); + Xil_Out32(SERDES_L0_TM_ANA_BYP_4, 0x00000080); + Xil_Out32(SERDES_L1_TM_ANA_BYP_4, 0x00000080); + Xil_Out32(SERDES_L2_TM_ANA_BYP_4, 0x00000080); + Xil_Out32(SERDES_L3_TM_ANA_BYP_4, 0x00000080); + + Xil_Out32(SERDES_L0_TM_PLL_DIG_33 , 0x000000C0); + Xil_Out32(SERDES_L1_TM_PLL_DIG_33 , 0x000000C0); + Xil_Out32(SERDES_L2_TM_PLL_DIG_33 , 0x000000C0); + Xil_Out32(SERDES_L3_TM_PLL_DIG_33 , 0x000000C0); + mask_delay(50); + Xil_Out32(SERDES_L0_TM_PLL_DIG_33 , 0x00000080); + Xil_Out32(SERDES_L1_TM_PLL_DIG_33 , 0x00000080); + Xil_Out32(SERDES_L2_TM_PLL_DIG_33 , 0x00000080); + Xil_Out32(SERDES_L3_TM_PLL_DIG_33 , 0x00000080); + mask_delay(50); + Xil_Out32(SERDES_L0_TM_ANA_BYP_4, 0x00000000); + Xil_Out32(SERDES_L1_TM_ANA_BYP_4, 0x00000000); + Xil_Out32(SERDES_L2_TM_ANA_BYP_4, 0x00000000); + Xil_Out32(SERDES_L3_TM_ANA_BYP_4, 0x00000000); + Xil_Out32(SERDES_L0_TM_PLL_DIG_33 , 0x00000000); + Xil_Out32(SERDES_L1_TM_PLL_DIG_33 , 0x00000000); + Xil_Out32(SERDES_L2_TM_PLL_DIG_33 , 0x00000000); + Xil_Out32(SERDES_L3_TM_PLL_DIG_33 , 0x00000000); + mask_delay(500); + return 1; +} + + +static int serdes_bist_static_settings(u32 lane_active) +{ + if (lane_active == 0) + { + Xil_Out32(SERDES_L0_BIST_CTRL_1, (Xil_In32(SERDES_L0_BIST_CTRL_1) & 0xFFFFFF1F)); + Xil_Out32(SERDES_L0_BIST_FILLER_OUT, 0x1 ); + Xil_Out32(SERDES_L0_BIST_FORCE_MK_RST, 0x1 ); + Xil_Out32(SERDES_L0_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L0_BIST_CTRL_2, 0x0); + Xil_Out32(SERDES_L0_BIST_RUN_LEN_L, 0xF4); + Xil_Out32(SERDES_L0_BIST_ERR_INJ_POINT_L, 0x0); + Xil_Out32(SERDES_L0_BIST_RUNLEN_ERR_INJ_H, 0x0); + Xil_Out32(SERDES_L0_BIST_IDLE_TIME,0x00); + Xil_Out32(SERDES_L0_BIST_MARKER_L, 0xFB); + Xil_Out32(SERDES_L0_BIST_IDLE_CHAR_L, 0xFF); + Xil_Out32(SERDES_L0_BIST_MARKER_IDLE_H, 0x0); + Xil_Out32(SERDES_L0_BIST_LOW_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L0_BIST_TOTAL_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_1, 0x4A); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_2, 0x4A); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_3, 0x4A); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_4, 0x4A); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_MSBS, 0x0); + Xil_Out32(SERDES_L0_BIST_PKT_NUM, 0x14); + Xil_Out32(SERDES_L0_BIST_FRM_IDLE_TIME,0x02); + Xil_Out32(SERDES_L0_BIST_CTRL_1, (Xil_In32(SERDES_L0_BIST_CTRL_1) & 0xFFFFFF1F)); + } + if (lane_active == 1) + { + Xil_Out32(SERDES_L1_BIST_CTRL_1, (Xil_In32(SERDES_L1_BIST_CTRL_1) & 0xFFFFFF1F)); + Xil_Out32(SERDES_L1_BIST_FILLER_OUT, 0x1 ); + Xil_Out32(SERDES_L1_BIST_FORCE_MK_RST, 0x1 ); + Xil_Out32(SERDES_L1_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L1_BIST_CTRL_2, 0x0); + Xil_Out32(SERDES_L1_BIST_RUN_LEN_L, 0xF4); + Xil_Out32(SERDES_L1_BIST_ERR_INJ_POINT_L, 0x0); + Xil_Out32(SERDES_L1_BIST_RUNLEN_ERR_INJ_H, 0x0); + Xil_Out32(SERDES_L1_BIST_IDLE_TIME,0x00); + Xil_Out32(SERDES_L1_BIST_MARKER_L, 0xFB); + Xil_Out32(SERDES_L1_BIST_IDLE_CHAR_L, 0xFF); + Xil_Out32(SERDES_L1_BIST_MARKER_IDLE_H, 0x0); + Xil_Out32(SERDES_L1_BIST_LOW_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L1_BIST_TOTAL_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_1, 0x4A); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_2, 0x4A); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_3, 0x4A); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_4, 0x4A); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_MSBS, 0x0); + Xil_Out32(SERDES_L1_BIST_PKT_NUM, 0x14); + Xil_Out32(SERDES_L1_BIST_FRM_IDLE_TIME,0x02); + Xil_Out32(SERDES_L1_BIST_CTRL_1, (Xil_In32(SERDES_L1_BIST_CTRL_1) & 0xFFFFFF1F)); + } + + if (lane_active == 2) + { + Xil_Out32(SERDES_L2_BIST_CTRL_1, (Xil_In32(SERDES_L2_BIST_CTRL_1) & 0xFFFFFF1F)); + Xil_Out32(SERDES_L2_BIST_FILLER_OUT, 0x1 ); + Xil_Out32(SERDES_L2_BIST_FORCE_MK_RST, 0x1 ); + Xil_Out32(SERDES_L2_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L2_BIST_CTRL_2, 0x0); + Xil_Out32(SERDES_L2_BIST_RUN_LEN_L, 0xF4); + Xil_Out32(SERDES_L2_BIST_ERR_INJ_POINT_L, 0x0); + Xil_Out32(SERDES_L2_BIST_RUNLEN_ERR_INJ_H, 0x0); + Xil_Out32(SERDES_L2_BIST_IDLE_TIME,0x00); + Xil_Out32(SERDES_L2_BIST_MARKER_L, 0xFB); + Xil_Out32(SERDES_L2_BIST_IDLE_CHAR_L, 0xFF); + Xil_Out32(SERDES_L2_BIST_MARKER_IDLE_H, 0x0); + Xil_Out32(SERDES_L2_BIST_LOW_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L2_BIST_TOTAL_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_1, 0x4A); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_2, 0x4A); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_3, 0x4A); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_4, 0x4A); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_MSBS, 0x0); + Xil_Out32(SERDES_L2_BIST_PKT_NUM, 0x14); + Xil_Out32(SERDES_L2_BIST_FRM_IDLE_TIME,0x02); + Xil_Out32(SERDES_L2_BIST_CTRL_1, (Xil_In32(SERDES_L2_BIST_CTRL_1) & 0xFFFFFF1F)); + } + + if (lane_active == 3) + { + Xil_Out32(SERDES_L3_BIST_CTRL_1, (Xil_In32(SERDES_L3_BIST_CTRL_1) & 0xFFFFFF1F)); + Xil_Out32(SERDES_L3_BIST_FILLER_OUT, 0x1 ); + Xil_Out32(SERDES_L3_BIST_FORCE_MK_RST, 0x1 ); + Xil_Out32(SERDES_L3_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L3_BIST_CTRL_2, 0x0); + Xil_Out32(SERDES_L3_BIST_RUN_LEN_L, 0xF4); + Xil_Out32(SERDES_L3_BIST_ERR_INJ_POINT_L, 0x0); + Xil_Out32(SERDES_L3_BIST_RUNLEN_ERR_INJ_H, 0x0); + Xil_Out32(SERDES_L3_BIST_IDLE_TIME,0x00); + Xil_Out32(SERDES_L3_BIST_MARKER_L, 0xFB); + Xil_Out32(SERDES_L3_BIST_IDLE_CHAR_L, 0xFF); + Xil_Out32(SERDES_L3_BIST_MARKER_IDLE_H, 0x0); + Xil_Out32(SERDES_L3_BIST_LOW_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L3_BIST_TOTAL_PULSE_TIME, 0x00); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_1, 0x4A); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_2, 0x4A); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_3, 0x4A); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_4, 0x4A); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_MSBS, 0x0); + Xil_Out32(SERDES_L3_BIST_PKT_NUM, 0x14); + Xil_Out32(SERDES_L3_BIST_FRM_IDLE_TIME,0x02); + Xil_Out32(SERDES_L3_BIST_CTRL_1, (Xil_In32(SERDES_L3_BIST_CTRL_1) & 0xFFFFFF1F)); + } + return (1); +} + +static int serdes_bist_run(u32 lane_active) +{ + if (lane_active == 0) { + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x00000003U, 0x00000000U); + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x00000003U, 0x00000000U); + PSU_Mask_Write(SERDES_LPBK_CTRL0, 0x00000007U, 0x00000001U); + Xil_Out32(SERDES_L0_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L0_BIST_CTRL_1,(Xil_In32(SERDES_L0_BIST_CTRL_1) | 0x1)); + } + if (lane_active == 1) { + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x0000000CU, 0x00000000U); + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x0000000CU, 0x00000000U); + PSU_Mask_Write(SERDES_LPBK_CTRL0, 0x00000070U, 0x00000010U); + Xil_Out32(SERDES_L1_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L1_BIST_CTRL_1,(Xil_In32(SERDES_L1_BIST_CTRL_1) | 0x1)); + } + if (lane_active == 2) { + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x00000030U, 0x00000000U); + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x00000030U, 0x00000000U); + PSU_Mask_Write(SERDES_LPBK_CTRL1, 0x00000007U, 0x00000001U); + Xil_Out32(SERDES_L2_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L2_BIST_CTRL_1,(Xil_In32(SERDES_L2_BIST_CTRL_1) | 0x1)); + } + if (lane_active == 3) { + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x000000C0U, 0x00000000U); + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x000000C0U, 0x00000000U); + PSU_Mask_Write(SERDES_LPBK_CTRL1, 0x00000070U, 0x00000010U); + Xil_Out32(SERDES_L3_TM_DIG_22, 0x0020); + Xil_Out32(SERDES_L3_BIST_CTRL_1,(Xil_In32(SERDES_L3_BIST_CTRL_1) | 0x1)); + } + mask_delay(100); + return (1); +} + +static int serdes_bist_result(u32 lane_active) +{ + u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0; + if (lane_active == 0) { + pkt_cnt_l0 = Xil_In32(SERDES_L0_BIST_PKT_CTR_L); + pkt_cnt_h0 = Xil_In32(SERDES_L0_BIST_PKT_CTR_H); + err_cnt_l0 = Xil_In32(SERDES_L0_BIST_ERR_CTR_L); + err_cnt_h0 = Xil_In32(SERDES_L0_BIST_ERR_CTR_H); + } + if (lane_active == 1) { + pkt_cnt_l0 = Xil_In32(SERDES_L1_BIST_PKT_CTR_L); + pkt_cnt_h0 = Xil_In32(SERDES_L1_BIST_PKT_CTR_H); + err_cnt_l0 = Xil_In32(SERDES_L1_BIST_ERR_CTR_L); + err_cnt_h0 = Xil_In32(SERDES_L1_BIST_ERR_CTR_H); + } + if (lane_active == 2) { + pkt_cnt_l0 = Xil_In32(SERDES_L2_BIST_PKT_CTR_L); + pkt_cnt_h0 = Xil_In32(SERDES_L2_BIST_PKT_CTR_H); + err_cnt_l0 = Xil_In32(SERDES_L2_BIST_ERR_CTR_L); + err_cnt_h0 = Xil_In32(SERDES_L2_BIST_ERR_CTR_H); + } + if (lane_active == 3) { + pkt_cnt_l0 = Xil_In32(SERDES_L3_BIST_PKT_CTR_L); + pkt_cnt_h0 = Xil_In32(SERDES_L3_BIST_PKT_CTR_H); + err_cnt_l0 = Xil_In32(SERDES_L3_BIST_ERR_CTR_L); + err_cnt_h0 = Xil_In32(SERDES_L3_BIST_ERR_CTR_H); + } + if (lane_active == 0) Xil_Out32(SERDES_L0_BIST_CTRL_1,0x0); + if (lane_active == 1) Xil_Out32(SERDES_L1_BIST_CTRL_1,0x0); + if (lane_active == 2) Xil_Out32(SERDES_L2_BIST_CTRL_1,0x0); + if (lane_active == 3) Xil_Out32(SERDES_L3_BIST_CTRL_1,0x0); + if((err_cnt_l0 > 0) || (err_cnt_h0 > 0) || ((pkt_cnt_l0 == 0) && (pkt_cnt_h0 == 0))) + return (0); + return (1); +} + +static int serdes_illcalib_pcie_gen1 (u32 lane3_protocol, u32 lane3_rate, u32 lane2_protocol, u32 lane2_rate, u32 lane1_protocol, u32 lane1_rate, u32 lane0_protocol, u32 lane0_rate, u32 gen2_calib) +{ + u64 tempbistresult; + u32 currbistresult[4]; + u32 prevbistresult[4]; + u32 itercount = 0; + u32 ill12_val[4], ill1_val[4]; + u32 loop=0; + u32 iterresult[8]; + u32 meancount[4]; + u32 bistpasscount[4]; + u32 meancountalt[4]; + u32 meancountalt_bistpasscount[4]; + u32 lane0_active; + u32 lane1_active; + u32 lane2_active; + u32 lane3_active; + + lane0_active = (lane0_protocol == 1); + lane1_active = (lane1_protocol == 1); + lane2_active = (lane2_protocol == 1); + lane3_active = (lane3_protocol == 1); + for (loop=0; loop<=3; loop++) + { + iterresult[loop] = 0; + iterresult[loop+4] = 0; + meancountalt[loop] = 0; + meancountalt_bistpasscount[loop]=0; + meancount[loop] = 0; + prevbistresult[loop] = 0; + bistpasscount[loop] = 0; + } + itercount = 0; + if (lane0_active) serdes_bist_static_settings(0); + if (lane1_active) serdes_bist_static_settings(1); + if (lane2_active) serdes_bist_static_settings(2); + if (lane3_active) serdes_bist_static_settings(3); + do + { + if (gen2_calib != 1) + { + if (lane0_active == 1) ill1_val[0] = ((0x04 + itercount*8) % 0x100); + if (lane0_active == 1) ill12_val[0] = ((0x04 + itercount*8) >= 0x100) ? 0x10 : 0x00; + if (lane1_active == 1) ill1_val[1] = ((0x04 + itercount*8) % 0x100); + if (lane1_active == 1) ill12_val[1] = ((0x04 + itercount*8) >= 0x100) ? 0x10 : 0x00; + if (lane2_active == 1) ill1_val[2] = ((0x04 + itercount*8) % 0x100); + if (lane2_active == 1) ill12_val[2] = ((0x04 + itercount*8) >= 0x100) ? 0x10 : 0x00; + if (lane3_active == 1) ill1_val[3] = ((0x04 + itercount*8) % 0x100); + if (lane3_active == 1) ill12_val[3] = ((0x04 + itercount*8) >= 0x100) ? 0x10 : 0x00; + + if (lane0_active == 1) Xil_Out32(SERDES_L0_TM_E_ILL1,ill1_val[0]); + if (lane0_active == 1) PSU_Mask_Write(SERDES_L0_TM_ILL12, 0x000000F0U, ill12_val[0]); + if (lane1_active == 1) Xil_Out32(SERDES_L1_TM_E_ILL1,ill1_val[1]); + if (lane1_active == 1) PSU_Mask_Write(SERDES_L1_TM_ILL12, 0x000000F0U, ill12_val[1]); + if (lane2_active == 1) Xil_Out32(SERDES_L2_TM_E_ILL1,ill1_val[2]); + if (lane2_active == 1) PSU_Mask_Write(SERDES_L2_TM_ILL12, 0x000000F0U, ill12_val[2]); + if (lane3_active == 1) Xil_Out32(SERDES_L3_TM_E_ILL1,ill1_val[3]); + if (lane3_active == 1) PSU_Mask_Write(SERDES_L3_TM_ILL12, 0x000000F0U, ill12_val[3]); + } + if (gen2_calib == 1) + { + if (lane0_active == 1) ill1_val[0] = ((0x104 + itercount*8) % 0x100); + if (lane0_active == 1) ill12_val[0] = ((0x104 + itercount*8) >= 0x200) ? 0x02 : 0x01; + if (lane1_active == 1) ill1_val[1] = ((0x104 + itercount*8) % 0x100); + if (lane1_active == 1) ill12_val[1] = ((0x104 + itercount*8) >= 0x200) ? 0x02 : 0x01; + if (lane2_active == 1) ill1_val[2] = ((0x104 + itercount*8) % 0x100); + if (lane2_active == 1) ill12_val[2] = ((0x104 + itercount*8) >= 0x200) ? 0x02 : 0x01; + if (lane3_active == 1) ill1_val[3] = ((0x104 + itercount*8) % 0x100); + if (lane3_active == 1) ill12_val[3] = ((0x104 + itercount*8) >= 0x200) ? 0x02 : 0x01; + + if (lane0_active == 1) Xil_Out32(SERDES_L0_TM_E_ILL2,ill1_val[0]); + if (lane0_active == 1) PSU_Mask_Write(SERDES_L0_TM_ILL12, 0x0000000FU, ill12_val[0]); + if (lane1_active == 1) Xil_Out32(SERDES_L1_TM_E_ILL2,ill1_val[1]); + if (lane1_active == 1) PSU_Mask_Write(SERDES_L1_TM_ILL12, 0x0000000FU, ill12_val[1]); + if (lane2_active == 1) Xil_Out32(SERDES_L2_TM_E_ILL2,ill1_val[2]); + if (lane2_active == 1) PSU_Mask_Write(SERDES_L2_TM_ILL12, 0x0000000FU, ill12_val[2]); + if (lane3_active == 1) Xil_Out32(SERDES_L3_TM_E_ILL2,ill1_val[3]); + if (lane3_active == 1) PSU_Mask_Write(SERDES_L3_TM_ILL12, 0x0000000FU, ill12_val[3]); + } + + if (lane0_active == 1) PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_7, 0x00000030U, 0x00000010U); + if (lane1_active == 1) PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_7, 0x00000030U, 0x00000010U); + if (lane2_active == 1) PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_7, 0x00000030U, 0x00000010U); + if (lane3_active == 1) PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_7, 0x00000030U, 0x00000010U); + if (lane0_active == 1) currbistresult[0] = 0; + if (lane1_active == 1) currbistresult[1] = 0; + if (lane2_active == 1) currbistresult[2] = 0; + if (lane3_active == 1) currbistresult[3] = 0; + serdes_rst_seq (lane3_protocol, lane3_rate, lane2_protocol, lane2_rate, lane1_protocol, lane1_rate, lane0_protocol, lane0_rate); + if (lane3_active == 1) serdes_bist_run(3); + if (lane2_active == 1) serdes_bist_run(2); + if (lane1_active == 1) serdes_bist_run(1); + if (lane0_active == 1) serdes_bist_run(0); + tempbistresult = 0; + if (lane3_active == 1) tempbistresult = tempbistresult | serdes_bist_result(3); + tempbistresult = tempbistresult << 1; + if (lane2_active == 1) tempbistresult = tempbistresult | serdes_bist_result(2); + tempbistresult = tempbistresult << 1; + if (lane1_active == 1) tempbistresult = tempbistresult | serdes_bist_result(1); + tempbistresult = tempbistresult << 1; + if (lane0_active == 1) tempbistresult = tempbistresult | serdes_bist_result(0); + Xil_Out32(SERDES_UPHY_SPARE0, 0x0); + Xil_Out32(SERDES_UPHY_SPARE0, 0x2); + + if (itercount < 32) { + iterresult[0] = ((iterresult[0]<<1) | ((tempbistresult&0x1)==0x1)); + iterresult[1] = ((iterresult[1]<<1) | ((tempbistresult&0x2)==0x2)); + iterresult[2] = ((iterresult[2]<<1) | ((tempbistresult&0x4)==0x4)); + iterresult[3] = ((iterresult[3]<<1) | ((tempbistresult&0x8)==0x8)); + } else { + iterresult[4] = ((iterresult[4]<<1) | ((tempbistresult&0x1)==0x1)); + iterresult[5] = ((iterresult[5]<<1) | ((tempbistresult&0x2)==0x2)); + iterresult[6] = ((iterresult[6]<<1) | ((tempbistresult&0x4)==0x4)); + iterresult[7] = ((iterresult[7]<<1) | ((tempbistresult&0x8)==0x8)); + } + currbistresult[0] = currbistresult[0] | ((tempbistresult&0x1)==1); + currbistresult[1] = currbistresult[1] | ((tempbistresult&0x2)==0x2); + currbistresult[2] = currbistresult[2] | ((tempbistresult&0x4)==0x4); + currbistresult[3] = currbistresult[3] | ((tempbistresult&0x8)==0x8); + + for (loop=0; loop<=3; loop++) + { + if ((currbistresult[loop]==1) && (prevbistresult[loop]==1)) + bistpasscount[loop] = bistpasscount[loop]+1; + if ((bistpasscount[loop]<4) && (currbistresult[loop]==0) && (itercount>2)) + { + if (meancountalt_bistpasscount[loop] < bistpasscount[loop]) + { + meancountalt_bistpasscount[loop] = bistpasscount[loop]; + meancountalt[loop] = ((itercount-1)-((bistpasscount[loop]+1)/2)); + } + bistpasscount[loop] = 0; + } + if ((meancount[loop]==0) && (bistpasscount[loop]>=4) && ((currbistresult[loop]==0)||(itercount == 63)) && (prevbistresult[loop]==1)) + meancount[loop] = (itercount-1)-((bistpasscount[loop]+1)/2); + prevbistresult[loop] = currbistresult[loop]; + } + }while(++itercount<64); + + for (loop=0; loop<=3; loop++) + { + if ((lane0_active == 0) && (loop == 0)) continue; + if ((lane1_active == 0) && (loop == 1)) continue; + if ((lane2_active == 0) && (loop == 2)) continue; + if ((lane3_active == 0) && (loop == 3)) continue; + + if (meancount[loop] == 0) + meancount[loop] = meancountalt[loop]; + + + if (gen2_calib != 1) + { + ill1_val[loop] = ((0x04 + meancount[loop]*8) % 0x100); + ill12_val[loop] = ((0x04 + meancount[loop]*8) >= 0x100) ? 0x10 : 0x00; + /*Xil_Out32(0xFFFE0000+loop*4,iterresult[loop]); + Xil_Out32(0xFFFE0010+loop*4,iterresult[loop+4]); + Xil_Out32(0xFFFE0020+loop*4,bistpasscount[loop]); + Xil_Out32(0xFFFE0030+loop*4,meancount[loop]);*/ + } + if (gen2_calib == 1) + { + ill1_val[loop] = ((0x104 + meancount[loop]*8) % 0x100); + ill12_val[loop] = ((0x104 + meancount[loop]*8) >= 0x200) ? 0x02 : 0x01; + /*Xil_Out32(0xFFFE0040+loop*4,iterresult[loop]); + Xil_Out32(0xFFFE0050+loop*4,iterresult[loop+4]); + Xil_Out32(0xFFFE0060+loop*4,bistpasscount[loop]); + Xil_Out32(0xFFFE0070+loop*4,meancount[loop]);*/ + } + } + if (gen2_calib != 1) + { + if (lane0_active == 1) Xil_Out32(SERDES_L0_TM_E_ILL1,ill1_val[0]); + if (lane0_active == 1) PSU_Mask_Write(SERDES_L0_TM_ILL12, 0x000000F0U, ill12_val[0]); + if (lane1_active == 1) Xil_Out32(SERDES_L1_TM_E_ILL1,ill1_val[1]); + if (lane1_active == 1) PSU_Mask_Write(SERDES_L1_TM_ILL12, 0x000000F0U, ill12_val[1]); + if (lane2_active == 1) Xil_Out32(SERDES_L2_TM_E_ILL1,ill1_val[2]); + if (lane2_active == 1) PSU_Mask_Write(SERDES_L2_TM_ILL12, 0x000000F0U, ill12_val[2]); + if (lane3_active == 1) Xil_Out32(SERDES_L3_TM_E_ILL1,ill1_val[3]); + if (lane3_active == 1) PSU_Mask_Write(SERDES_L3_TM_ILL12, 0x000000F0U, ill12_val[3]); + } + if (gen2_calib == 1) + { + if (lane0_active == 1) Xil_Out32(SERDES_L0_TM_E_ILL2,ill1_val[0]); + if (lane0_active == 1) PSU_Mask_Write(SERDES_L0_TM_ILL12, 0x0000000FU, ill12_val[0]); + if (lane1_active == 1) Xil_Out32(SERDES_L1_TM_E_ILL2,ill1_val[1]); + if (lane1_active == 1) PSU_Mask_Write(SERDES_L1_TM_ILL12, 0x0000000FU, ill12_val[1]); + if (lane2_active == 1) Xil_Out32(SERDES_L2_TM_E_ILL2,ill1_val[2]); + if (lane2_active == 1) PSU_Mask_Write(SERDES_L2_TM_ILL12, 0x0000000FU, ill12_val[2]); + if (lane3_active == 1) Xil_Out32(SERDES_L3_TM_E_ILL2,ill1_val[3]); + if (lane3_active == 1) PSU_Mask_Write(SERDES_L3_TM_ILL12, 0x0000000FU, ill12_val[3]); + } + + + if (lane0_active == 1) PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_7, 0x00000030U, 0x00000000U); + if (lane1_active == 1) PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_7, 0x00000030U, 0x00000000U); + if (lane2_active == 1) PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_7, 0x00000030U, 0x00000000U); + if (lane3_active == 1) PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_7, 0x00000030U, 0x00000000U); + + Xil_Out32(SERDES_UPHY_SPARE0,0); + if (lane0_active == 1) + { + Xil_Out32(SERDES_L0_BIST_CTRL_1,0); + Xil_Out32(SERDES_L0_BIST_CTRL_2,0); + Xil_Out32(SERDES_L0_BIST_RUN_LEN_L,0); + Xil_Out32(SERDES_L0_BIST_ERR_INJ_POINT_L,0); + Xil_Out32(SERDES_L0_BIST_RUNLEN_ERR_INJ_H,0); + Xil_Out32(SERDES_L0_BIST_IDLE_TIME,0); + Xil_Out32(SERDES_L0_BIST_MARKER_L,0); + Xil_Out32(SERDES_L0_BIST_IDLE_CHAR_L,0); + Xil_Out32(SERDES_L0_BIST_MARKER_IDLE_H,0); + Xil_Out32(SERDES_L0_BIST_LOW_PULSE_TIME,0); + Xil_Out32(SERDES_L0_BIST_TOTAL_PULSE_TIME,0); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_1,0); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_2,0); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_3,0); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_4,0); + Xil_Out32(SERDES_L0_BIST_TEST_PAT_MSBS,0); + Xil_Out32(SERDES_L0_BIST_PKT_NUM,0); + Xil_Out32(SERDES_L0_BIST_FRM_IDLE_TIME,0); + Xil_Out32(SERDES_L0_BIST_PKT_CTR_L,0); + Xil_Out32(SERDES_L0_BIST_PKT_CTR_H,0); + Xil_Out32(SERDES_L0_BIST_ERR_CTR_L,0); + Xil_Out32(SERDES_L0_BIST_ERR_CTR_H,0); + Xil_Out32(SERDES_L0_BIST_FILLER_OUT,1); + Xil_Out32(SERDES_L0_BIST_FORCE_MK_RST,0); + Xil_Out32(SERDES_L0_TM_DIG_22,0); + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x00000003U, 0x00000001U); + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x00000003U, 0x00000001U); + PSU_Mask_Write(SERDES_LPBK_CTRL0, 0x00000007U, 0x00000000U); + } + if (lane1_active == 1) + { + Xil_Out32(SERDES_L1_BIST_CTRL_1,0); + Xil_Out32(SERDES_L1_BIST_CTRL_2,0); + Xil_Out32(SERDES_L1_BIST_RUN_LEN_L,0); + Xil_Out32(SERDES_L1_BIST_ERR_INJ_POINT_L,0); + Xil_Out32(SERDES_L1_BIST_RUNLEN_ERR_INJ_H,0); + Xil_Out32(SERDES_L1_BIST_IDLE_TIME,0); + Xil_Out32(SERDES_L1_BIST_MARKER_L,0); + Xil_Out32(SERDES_L1_BIST_IDLE_CHAR_L,0); + Xil_Out32(SERDES_L1_BIST_MARKER_IDLE_H,0); + Xil_Out32(SERDES_L1_BIST_LOW_PULSE_TIME,0); + Xil_Out32(SERDES_L1_BIST_TOTAL_PULSE_TIME,0); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_1,0); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_2,0); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_3,0); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_4,0); + Xil_Out32(SERDES_L1_BIST_TEST_PAT_MSBS,0); + Xil_Out32(SERDES_L1_BIST_PKT_NUM,0); + Xil_Out32(SERDES_L1_BIST_FRM_IDLE_TIME,0); + Xil_Out32(SERDES_L1_BIST_PKT_CTR_L,0); + Xil_Out32(SERDES_L1_BIST_PKT_CTR_H,0); + Xil_Out32(SERDES_L1_BIST_ERR_CTR_L,0); + Xil_Out32(SERDES_L1_BIST_ERR_CTR_H,0); + Xil_Out32(SERDES_L1_BIST_FILLER_OUT,1); + Xil_Out32(SERDES_L1_BIST_FORCE_MK_RST,0); + Xil_Out32(SERDES_L1_TM_DIG_22,0); + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x0000000CU, 0x00000004U); + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x0000000CU, 0x00000004U); + PSU_Mask_Write(SERDES_LPBK_CTRL0, 0x00000070U, 0x00000000U); + } + if (lane2_active == 1) + { + Xil_Out32(SERDES_L2_BIST_CTRL_1,0); + Xil_Out32(SERDES_L2_BIST_CTRL_2,0); + Xil_Out32(SERDES_L2_BIST_RUN_LEN_L,0); + Xil_Out32(SERDES_L2_BIST_ERR_INJ_POINT_L,0); + Xil_Out32(SERDES_L2_BIST_RUNLEN_ERR_INJ_H,0); + Xil_Out32(SERDES_L2_BIST_IDLE_TIME,0); + Xil_Out32(SERDES_L2_BIST_MARKER_L,0); + Xil_Out32(SERDES_L2_BIST_IDLE_CHAR_L,0); + Xil_Out32(SERDES_L2_BIST_MARKER_IDLE_H,0); + Xil_Out32(SERDES_L2_BIST_LOW_PULSE_TIME,0); + Xil_Out32(SERDES_L2_BIST_TOTAL_PULSE_TIME,0); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_1,0); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_2,0); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_3,0); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_4,0); + Xil_Out32(SERDES_L2_BIST_TEST_PAT_MSBS,0); + Xil_Out32(SERDES_L2_BIST_PKT_NUM,0); + Xil_Out32(SERDES_L2_BIST_FRM_IDLE_TIME,0); + Xil_Out32(SERDES_L2_BIST_PKT_CTR_L,0); + Xil_Out32(SERDES_L2_BIST_PKT_CTR_H,0); + Xil_Out32(SERDES_L2_BIST_ERR_CTR_L,0); + Xil_Out32(SERDES_L2_BIST_ERR_CTR_H,0); + Xil_Out32(SERDES_L2_BIST_FILLER_OUT,1); + Xil_Out32(SERDES_L2_BIST_FORCE_MK_RST,0); + Xil_Out32(SERDES_L2_TM_DIG_22,0); + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x00000030U, 0x00000010U); + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x00000030U, 0x00000010U); + PSU_Mask_Write(SERDES_LPBK_CTRL1, 0x00000007U, 0x00000000U); + } + if (lane3_active == 1) + { + Xil_Out32(SERDES_L3_BIST_CTRL_1,0); + Xil_Out32(SERDES_L3_BIST_CTRL_2,0); + Xil_Out32(SERDES_L3_BIST_RUN_LEN_L,0); + Xil_Out32(SERDES_L3_BIST_ERR_INJ_POINT_L,0); + Xil_Out32(SERDES_L3_BIST_RUNLEN_ERR_INJ_H,0); + Xil_Out32(SERDES_L3_BIST_IDLE_TIME,0); + Xil_Out32(SERDES_L3_BIST_MARKER_L,0); + Xil_Out32(SERDES_L3_BIST_IDLE_CHAR_L,0); + Xil_Out32(SERDES_L3_BIST_MARKER_IDLE_H,0); + Xil_Out32(SERDES_L3_BIST_LOW_PULSE_TIME,0); + Xil_Out32(SERDES_L3_BIST_TOTAL_PULSE_TIME,0); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_1,0); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_2,0); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_3,0); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_4,0); + Xil_Out32(SERDES_L3_BIST_TEST_PAT_MSBS,0); + Xil_Out32(SERDES_L3_BIST_PKT_NUM,0); + Xil_Out32(SERDES_L3_BIST_FRM_IDLE_TIME,0); + Xil_Out32(SERDES_L3_BIST_PKT_CTR_L,0); + Xil_Out32(SERDES_L3_BIST_PKT_CTR_H,0); + Xil_Out32(SERDES_L3_BIST_ERR_CTR_L,0); + Xil_Out32(SERDES_L3_BIST_ERR_CTR_H,0); + Xil_Out32(SERDES_L3_BIST_FILLER_OUT,1); + Xil_Out32(SERDES_L3_BIST_FORCE_MK_RST,0); + Xil_Out32(SERDES_L3_TM_DIG_22,0); + PSU_Mask_Write(SERDES_RX_PROT_BUS_WIDTH, 0x000000C0U, 0x00000040U); + PSU_Mask_Write(SERDES_TX_PROT_BUS_WIDTH, 0x000000C0U, 0x00000040U); + PSU_Mask_Write(SERDES_LPBK_CTRL1, 0x00000070U, 0x00000000U); + } + return 1; +} + +static int serdes_illcalib (u32 lane3_protocol, u32 lane3_rate, u32 lane2_protocol, u32 lane2_rate, u32 lane1_protocol, u32 lane1_rate, u32 lane0_protocol, u32 lane0_rate) +//Protocol values +//pcie = 1; sata = 2; usb = 3; dp = 4; sgmii = 5 +//Rate values +//pcie_gen1 = 0; pcie_gen2 = 1; +//sata_gen1 = 1; sata_gen2 = 2; sata_gen3 = 3; +//usb = 0; sgmii = 0; DP = 0; +{ + unsigned int rdata=0; + unsigned int sata_gen2=1; + unsigned int temp_ill12=0; + unsigned int temp_PLL_REF_SEL_OFFSET; + unsigned int temp_TM_IQ_ILL1; + unsigned int temp_TM_E_ILL1; + unsigned int temp_tx_dig_tm_61; + unsigned int temp_tm_dig_6; + unsigned int temp_pll_fbdiv_frac_3_msb_offset; + + if ((lane0_protocol == 2)||(lane0_protocol == 1)) + { + Xil_Out32(SERDES_L0_TM_IQ_ILL7, 0xF3); + Xil_Out32(SERDES_L0_TM_E_ILL7, 0xF3); + Xil_Out32(SERDES_L0_TM_IQ_ILL8,0xF3); + Xil_Out32(SERDES_L0_TM_E_ILL8,0xF3); + } + if ((lane1_protocol == 2)||(lane1_protocol == 1)) + { + Xil_Out32(SERDES_L1_TM_IQ_ILL7, 0xF3); + Xil_Out32(SERDES_L1_TM_E_ILL7, 0xF3); + Xil_Out32(SERDES_L1_TM_IQ_ILL8,0xF3); + Xil_Out32(SERDES_L1_TM_E_ILL8,0xF3); + } + if ((lane2_protocol == 2)||(lane2_protocol == 1)) + { + Xil_Out32(SERDES_L2_TM_IQ_ILL7, 0xF3); + Xil_Out32(SERDES_L2_TM_E_ILL7, 0xF3); + Xil_Out32(SERDES_L2_TM_IQ_ILL8,0xF3); + Xil_Out32(SERDES_L2_TM_E_ILL8,0xF3); + } + if ((lane3_protocol == 2)||(lane3_protocol == 1)) + { + Xil_Out32(SERDES_L3_TM_IQ_ILL7, 0xF3); + Xil_Out32(SERDES_L3_TM_E_ILL7, 0xF3); + Xil_Out32(SERDES_L3_TM_IQ_ILL8,0xF3); + Xil_Out32(SERDES_L3_TM_E_ILL8,0xF3); + } + + if (sata_gen2 == 1) + { + if (lane0_protocol == 2) + { + temp_pll_fbdiv_frac_3_msb_offset=Xil_In32(SERDES_L0_PLL_FBDIV_FRAC_3_MSB); + Xil_Out32(SERDES_L0_PLL_FBDIV_FRAC_3_MSB,0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(SERDES_PLL_REF_SEL0_OFFSET); + PSU_Mask_Write(SERDES_PLL_REF_SEL0_OFFSET, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(SERDES_L0_TM_IQ_ILL1); + temp_TM_E_ILL1 = Xil_In32(SERDES_L0_TM_E_ILL1); + Xil_Out32(SERDES_L0_TM_IQ_ILL1,0x78); + temp_tx_dig_tm_61 = Xil_In32(SERDES_L0_TX_DIG_TM_61); + temp_tm_dig_6 = Xil_In32(SERDES_L0_TM_DIG_6); + PSU_Mask_Write(SERDES_L0_TX_DIG_TM_61, 0x0000000BU, 0x00000000U); + PSU_Mask_Write(SERDES_L0_TM_DIG_6, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(SERDES_L0_TM_ILL12) & 0xF0; + + serdes_illcalib_pcie_gen1 (0, 0, 0, 0, 0, 0, 1, 0, 0); + + Xil_Out32(SERDES_L0_PLL_FBDIV_FRAC_3_MSB,temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(SERDES_PLL_REF_SEL3_OFFSET, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(SERDES_L0_TM_IQ_ILL1,temp_TM_IQ_ILL1); + Xil_Out32(SERDES_L0_TX_DIG_TM_61, temp_tx_dig_tm_61); + Xil_Out32(SERDES_L0_TM_DIG_6, temp_tm_dig_6); + Xil_Out32(SERDES_L0_TM_E_ILL2, Xil_In32(SERDES_L0_TM_E_ILL1)); + temp_ill12 = temp_ill12 | (Xil_In32(SERDES_L0_TM_ILL12)>>4 & 0xF); + Xil_Out32(SERDES_L0_TM_ILL12, temp_ill12); + Xil_Out32(SERDES_L0_TM_E_ILL1, temp_TM_E_ILL1); + } + if (lane1_protocol == 2) + { + temp_pll_fbdiv_frac_3_msb_offset=Xil_In32(SERDES_L1_PLL_FBDIV_FRAC_3_MSB); + Xil_Out32(SERDES_L1_PLL_FBDIV_FRAC_3_MSB,0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(SERDES_PLL_REF_SEL1_OFFSET); + PSU_Mask_Write(SERDES_PLL_REF_SEL1_OFFSET, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(SERDES_L1_TM_IQ_ILL1); + temp_TM_E_ILL1 = Xil_In32(SERDES_L1_TM_E_ILL1); + Xil_Out32(SERDES_L1_TM_IQ_ILL1,0x78); + temp_tx_dig_tm_61 = Xil_In32(SERDES_L1_TX_DIG_TM_61); + temp_tm_dig_6 = Xil_In32(SERDES_L1_TM_DIG_6); + PSU_Mask_Write(SERDES_L1_TX_DIG_TM_61, 0x0000000BU, 0x00000000U); + PSU_Mask_Write(SERDES_L1_TM_DIG_6, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(SERDES_L1_TM_ILL12) & 0xF0; + + serdes_illcalib_pcie_gen1 (0, 0, 0, 0, 1, 0, 0, 0, 0); + + Xil_Out32(SERDES_L1_PLL_FBDIV_FRAC_3_MSB,temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(SERDES_PLL_REF_SEL3_OFFSET, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(SERDES_L1_TM_IQ_ILL1,temp_TM_IQ_ILL1); + Xil_Out32(SERDES_L1_TX_DIG_TM_61, temp_tx_dig_tm_61); + Xil_Out32(SERDES_L1_TM_DIG_6, temp_tm_dig_6); + Xil_Out32(SERDES_L1_TM_E_ILL2, Xil_In32(SERDES_L1_TM_E_ILL1)); + temp_ill12 = temp_ill12 | (Xil_In32(SERDES_L1_TM_ILL12)>>4 & 0xF); + Xil_Out32(SERDES_L1_TM_ILL12, temp_ill12); + Xil_Out32(SERDES_L1_TM_E_ILL1, temp_TM_E_ILL1); + } + if (lane2_protocol == 2) + { + temp_pll_fbdiv_frac_3_msb_offset=Xil_In32(SERDES_L2_PLL_FBDIV_FRAC_3_MSB); + Xil_Out32(SERDES_L2_PLL_FBDIV_FRAC_3_MSB,0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(SERDES_PLL_REF_SEL2_OFFSET); + PSU_Mask_Write(SERDES_PLL_REF_SEL2_OFFSET, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(SERDES_L2_TM_IQ_ILL1); + temp_TM_E_ILL1 = Xil_In32(SERDES_L2_TM_E_ILL1); + Xil_Out32(SERDES_L2_TM_IQ_ILL1,0x78); + temp_tx_dig_tm_61 = Xil_In32(SERDES_L2_TX_DIG_TM_61); + temp_tm_dig_6 = Xil_In32(SERDES_L2_TM_DIG_6); + PSU_Mask_Write(SERDES_L2_TX_DIG_TM_61, 0x0000000BU, 0x00000000U); + PSU_Mask_Write(SERDES_L2_TM_DIG_6, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(SERDES_L2_TM_ILL12) & 0xF0; + + serdes_illcalib_pcie_gen1 (0, 0, 1, 0, 0, 0, 0, 0, 0); + + Xil_Out32(SERDES_L2_PLL_FBDIV_FRAC_3_MSB,temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(SERDES_PLL_REF_SEL3_OFFSET, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(SERDES_L2_TM_IQ_ILL1,temp_TM_IQ_ILL1); + Xil_Out32(SERDES_L2_TX_DIG_TM_61, temp_tx_dig_tm_61); + Xil_Out32(SERDES_L2_TM_DIG_6, temp_tm_dig_6); + Xil_Out32(SERDES_L2_TM_E_ILL2, Xil_In32(SERDES_L2_TM_E_ILL1)); + temp_ill12 = temp_ill12 | (Xil_In32(SERDES_L2_TM_ILL12)>>4 & 0xF); + Xil_Out32(SERDES_L2_TM_ILL12, temp_ill12); + Xil_Out32(SERDES_L2_TM_E_ILL1, temp_TM_E_ILL1); + } + if (lane3_protocol == 2) + { + temp_pll_fbdiv_frac_3_msb_offset=Xil_In32(SERDES_L3_PLL_FBDIV_FRAC_3_MSB); + Xil_Out32(SERDES_L3_PLL_FBDIV_FRAC_3_MSB,0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(SERDES_PLL_REF_SEL3_OFFSET); + PSU_Mask_Write(SERDES_PLL_REF_SEL3_OFFSET, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(SERDES_L3_TM_IQ_ILL1); + temp_TM_E_ILL1 = Xil_In32(SERDES_L3_TM_E_ILL1); + Xil_Out32(SERDES_L3_TM_IQ_ILL1,0x78); + temp_tx_dig_tm_61 = Xil_In32(SERDES_L3_TX_DIG_TM_61); + temp_tm_dig_6 = Xil_In32(SERDES_L3_TM_DIG_6); + PSU_Mask_Write(SERDES_L3_TX_DIG_TM_61, 0x0000000BU, 0x00000000U); + PSU_Mask_Write(SERDES_L3_TM_DIG_6, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(SERDES_L3_TM_ILL12) & 0xF0; + + serdes_illcalib_pcie_gen1 (1, 0, 0, 0, 0, 0, 0, 0, 0); + + Xil_Out32(SERDES_L3_PLL_FBDIV_FRAC_3_MSB,temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(SERDES_PLL_REF_SEL3_OFFSET, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(SERDES_L3_TM_IQ_ILL1,temp_TM_IQ_ILL1); + Xil_Out32(SERDES_L3_TX_DIG_TM_61, temp_tx_dig_tm_61); + Xil_Out32(SERDES_L3_TM_DIG_6, temp_tm_dig_6); + Xil_Out32(SERDES_L3_TM_E_ILL2, Xil_In32(SERDES_L3_TM_E_ILL1)); + temp_ill12 = temp_ill12 | (Xil_In32(SERDES_L3_TM_ILL12)>>4 & 0xF); + Xil_Out32(SERDES_L3_TM_ILL12, temp_ill12); + Xil_Out32(SERDES_L3_TM_E_ILL1, temp_TM_E_ILL1); + } + rdata = Xil_In32(SERDES_UPHY_SPARE0); + rdata = (rdata & 0xDF); + Xil_Out32(SERDES_UPHY_SPARE0,rdata); + } + + if ((lane0_protocol == 2)&&(lane0_rate == 3)) + { + PSU_Mask_Write(SERDES_L0_TM_ILL11, 0x000000F0U, 0x00000020U); + PSU_Mask_Write(SERDES_L0_TM_E_ILL3, 0x000000FFU, 0x00000094U); + } + if ((lane1_protocol == 2)&&(lane1_rate == 3)) + { + PSU_Mask_Write(SERDES_L1_TM_ILL11, 0x000000F0U, 0x00000020U); + PSU_Mask_Write(SERDES_L1_TM_E_ILL3, 0x000000FFU, 0x00000094U); + } + if ((lane2_protocol == 2)&&(lane2_rate == 3)) + { + PSU_Mask_Write(SERDES_L2_TM_ILL11, 0x000000F0U, 0x00000020U); + PSU_Mask_Write(SERDES_L2_TM_E_ILL3, 0x000000FFU, 0x00000094U); + } + if ((lane3_protocol == 2)&&(lane3_rate == 3)) + { + PSU_Mask_Write(SERDES_L3_TM_ILL11, 0x000000F0U, 0x00000020U); + PSU_Mask_Write(SERDES_L3_TM_E_ILL3, 0x000000FFU, 0x00000094U); + } + + //PCIe settings + //If lane-0 is PCIe, we need to run pcie dynamic search on all active pcie lanes + //and reset sequence on all active lanes + if (lane0_protocol == 1) + { + if (lane0_rate == 0) + { + serdes_illcalib_pcie_gen1 (lane3_protocol, lane3_rate, lane2_protocol, lane2_rate, lane1_protocol, lane1_rate, lane0_protocol, 0, 0); + } + else + { + serdes_illcalib_pcie_gen1 (lane3_protocol, lane3_rate, lane2_protocol, lane2_rate, lane1_protocol, lane1_rate, lane0_protocol, 0, 0); + serdes_illcalib_pcie_gen1 (lane3_protocol, lane3_rate, lane2_protocol, lane2_rate, lane1_protocol, lane1_rate, lane0_protocol, lane0_rate, 1); + } + } + + //USB3 settings + if (lane0_protocol == 3) Xil_Out32(SERDES_L0_TM_IQ_ILL8,0xF3); + if (lane0_protocol == 3) Xil_Out32(SERDES_L0_TM_E_ILL8,0xF3); + if (lane0_protocol == 3) Xil_Out32(SERDES_L0_TM_ILL12,0x20); + if (lane0_protocol == 3) Xil_Out32(SERDES_L0_TM_E_ILL1,0x37); + + if (lane1_protocol == 3) Xil_Out32(SERDES_L1_TM_IQ_ILL8,0xF3); + if (lane1_protocol == 3) Xil_Out32(SERDES_L1_TM_E_ILL8,0xF3); + if (lane1_protocol == 3) Xil_Out32(SERDES_L1_TM_ILL12,0x20); + if (lane1_protocol == 3) Xil_Out32(SERDES_L1_TM_E_ILL1,0x37); + + if (lane2_protocol == 3) Xil_Out32(SERDES_L2_TM_IQ_ILL8,0xF3); + if (lane2_protocol == 3) Xil_Out32(SERDES_L2_TM_E_ILL8,0xF3); + if (lane2_protocol == 3) Xil_Out32(SERDES_L2_TM_ILL12,0x20); + if (lane2_protocol == 3) Xil_Out32(SERDES_L2_TM_E_ILL1,0x37); + + if (lane3_protocol == 3) Xil_Out32(SERDES_L3_TM_IQ_ILL8,0xF3); + if (lane3_protocol == 3) Xil_Out32(SERDES_L3_TM_E_ILL8,0xF3); + if (lane3_protocol == 3) Xil_Out32(SERDES_L3_TM_ILL12,0x20); + if (lane3_protocol == 3) Xil_Out32(SERDES_L3_TM_E_ILL1,0x37); + + return 1; +} + + +//Kishore -- ILL calibration code ends + +/*Following SERDES programming sequences that a user need to follow to work + * around the known limitation with SERDES. These sequences should done + * before STEP 1 and STEP 2 as described in previous section. These + * programming steps are *required for current silicon version and are + * likely to undergo further changes with subsequent silicon versions. + */ + + +static int serdes_enb_coarse_saturation(void) +{ + /*Enable PLL Coarse Code saturation Logic*/ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +int serdes_fixcal_code(void) +{ + int MaskStatus = 1; + + unsigned int rdata = 0; + + /*The valid codes are from 0x26 to 0x3C. + *There are 23 valid codes in total. + */ + /*Each element of array stands for count of occurence of valid code.*/ + unsigned int match_pmos_code[23]; + /*Each element of array stands for count of occurence of valid code.*/ + /*The valid codes are from 0xC to 0x12. + *There are 7 valid codes in total. + */ + unsigned int match_nmos_code[23]; + /*Each element of array stands for count of occurence of valid code.*/ + /*The valid codes are from 0x6 to 0xC. + * There are 7 valid codes in total. + */ + unsigned int match_ical_code[7]; + /*Each element of array stands for count of occurence of valid code.*/ + unsigned int match_rcal_code[7]; + + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + + int i = 0; + + rdata = Xil_In32(0XFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0XFD40289C, rdata); + // check supply good status before starting AFE sequencing + int count = 0; + do + { + if (count == PSU_MASK_POLL_TIME) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + }while((rdata&0x0000000E) !=0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + + do { + /*Clear ICM_CFG value*/ + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + /*Set ICM_CFG value*/ + /*This will trigger recalibration of all stages*/ + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + /*is calibration done? polling on L3_CALIB_DONE_STATUS*/ + MaskStatus = mask_poll(0xFD40EF14, 0x2); + if (MaskStatus == 0) { + /*failure here is because of calibration done timeout*/ + xil_printf("#SERDES initialization timed out\n\r"); + return MaskStatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);/*PMOS code*/ + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);/*NMOS code*/ + /*m_code = mask_read(0xFD40EF20, 0xFFFFFFFF)*/;/*MPHY code*/ + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);/*ICAL code*/ + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);/*RX code*/ + /*u_code = mask_read(0xFD40EF2C, 0xFFFFFFFF)*/;/*USB2 code*/ + + /*PMOS code in acceptable range*/ + if ((p_code >= 0x26) && (p_code <= 0x3C)) + match_pmos_code[p_code - 0x26] += 1; + + /*NMOS code in acceptable range*/ + if ((n_code >= 0x26) && (n_code <= 0x3C)) + match_nmos_code[n_code - 0x26] += 1; + + /*PMOS code in acceptable range*/ + if ((i_code >= 0xC) && (i_code <= 0x12)) + match_ical_code[i_code - 0xC] += 1; + + /*NMOS code in acceptable range*/ + if ((r_code >= 0x6) && (r_code <= 0xC)) + match_rcal_code[r_code - 0x6] += 1; + + + } while (repeat_count++ < 10); + + /*find the valid code which resulted in maximum times in 10 iterations*/ + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + /*L3_TM_CALIB_DIG20[3] PSW MSB Override*/ + /*L3_TM_CALIB_DIG20[2:0] PSW Code [4:2]*/ + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);/*read DIG20*/ + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + + /*L3_TM_CALIB_DIG19[7:6] PSW Code [1:0]*/ + /*L3_TM_CALIB_DIG19[5] PSW Override*/ + /*L3_TM_CALIB_DIG19[2] NSW MSB Override*/ + /*L3_TM_CALIB_DIG19[1:0] NSW Code [4:3]*/ + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);/*read DIG19*/ + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + /*L3_TM_CALIB_DIG18[7:5] NSW Code [2:0]*/ + /*L3_TM_CALIB_DIG18[4] NSW Override*/ + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);/*read DIG18*/ + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + + /*L3_TM_CALIB_DIG16[2:0] RX Code [3:1]*/ + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);/*read DIG16*/ + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + /*L3_TM_CALIB_DIG15[7] RX Code [0]*/ + /*L3_TM_CALIB_DIG15[6] RX CODE Override*/ + /*L3_TM_CALIB_DIG15[3] ICAL MSB Override*/ + /*L3_TM_CALIB_DIG15[2:0] ICAL Code [3:1]*/ + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);/*read DIG15*/ + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + /*L3_TM_CALIB_DIG14[7] ICAL Code [0]*/ + /*L3_TM_CALIB_DIG14[6] ICAL Override*/ + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);/*read DIG14*/ + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + /*Forces the calibration values*/ + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return MaskStatus; + +} +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + + +static void init_peripheral(void) +{ +/*SMMU_REG Interrrupt Enable: Followig register need to be written all the time to properly catch SMMU messages.*/ + PSU_Mask_Write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +static int psu_init_xppu_aper_ram(void) +{ + + return 0; +} + +int psu_lpd_protection(void) +{ + psu_init_xppu_aper_ram(); + return 0; +} + +int psu_ddr_protection(void) +{ + psu_ddr_xmpu0_data(); + psu_ddr_xmpu1_data(); + psu_ddr_xmpu2_data(); + psu_ddr_xmpu3_data(); + psu_ddr_xmpu4_data(); + psu_ddr_xmpu5_data(); + return 0; +} +int psu_ocm_protection(void) +{ + psu_ocm_xmpu_data(); + return 0; +} + +int psu_fpd_protection(void) +{ + psu_fpd_xmpu_data(); + return 0; +} + +int psu_protection_lock(void) +{ + psu_protection_lock_data(); + return 0; +} + +int psu_protection(void) +{ + psu_apply_master_tz(); + psu_ddr_protection(); + psu_ocm_protection(); + psu_fpd_protection(); + psu_lpd_protection(); + return 0; +} + +int +psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_peripherals_pre_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_peripherals_powerdwn_data(); + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) + return 1; + return 0; +} + +int psu_init_ddr_self_refresh(void) { + + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_peripherals_pre_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_peripherals_powerdwn_data(); + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) + return 1; + return 0; + + +} + + diff --git a/Petalinux/project-spec/hw-description/psu_init_gpl.h b/Petalinux/project-spec/hw-description/psu_init_gpl.h new file mode 100644 index 0000000..3511543 --- /dev/null +++ b/Petalinux/project-spec/hw-description/psu_init_gpl.h @@ -0,0 +1,38633 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file psu_init_gpl.h +* +* This file is automatically generated +* +*****************************************************************************/ + + +#undef CRL_APB_RPLL_CFG_OFFSET +#define CRL_APB_RPLL_CFG_OFFSET 0XFF5E0034 +#undef CRL_APB_RPLL_CTRL_OFFSET +#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 +#undef CRL_APB_RPLL_CTRL_OFFSET +#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 +#undef CRL_APB_RPLL_CTRL_OFFSET +#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 +#undef CRL_APB_RPLL_CTRL_OFFSET +#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 +#undef CRL_APB_RPLL_CTRL_OFFSET +#define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 +#undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET +#define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 0XFF5E0048 +#undef CRL_APB_AMS_REF_CTRL_OFFSET +#define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108 +#undef CRL_APB_IOPLL_CFG_OFFSET +#define CRL_APB_IOPLL_CFG_OFFSET 0XFF5E0024 +#undef CRL_APB_IOPLL_CTRL_OFFSET +#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 +#undef CRL_APB_IOPLL_CTRL_OFFSET +#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 +#undef CRL_APB_IOPLL_CTRL_OFFSET +#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 +#undef CRL_APB_IOPLL_CTRL_OFFSET +#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 +#undef CRL_APB_IOPLL_CTRL_OFFSET +#define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 +#undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET +#define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 0XFF5E0044 +#undef CRF_APB_APLL_CFG_OFFSET +#define CRF_APB_APLL_CFG_OFFSET 0XFD1A0024 +#undef CRF_APB_APLL_CTRL_OFFSET +#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 +#undef CRF_APB_APLL_CTRL_OFFSET +#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 +#undef CRF_APB_APLL_CTRL_OFFSET +#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 +#undef CRF_APB_APLL_CTRL_OFFSET +#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 +#undef CRF_APB_APLL_CTRL_OFFSET +#define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 +#undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET +#define CRF_APB_APLL_TO_LPD_CTRL_OFFSET 0XFD1A0048 +#undef CRF_APB_DPLL_CFG_OFFSET +#define CRF_APB_DPLL_CFG_OFFSET 0XFD1A0030 +#undef CRF_APB_DPLL_CTRL_OFFSET +#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C +#undef CRF_APB_DPLL_CTRL_OFFSET +#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C +#undef CRF_APB_DPLL_CTRL_OFFSET +#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C +#undef CRF_APB_DPLL_CTRL_OFFSET +#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C +#undef CRF_APB_DPLL_CTRL_OFFSET +#define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C +#undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET +#define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 0XFD1A004C +#undef CRF_APB_VPLL_CFG_OFFSET +#define CRF_APB_VPLL_CFG_OFFSET 0XFD1A003C +#undef CRF_APB_VPLL_CTRL_OFFSET +#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 +#undef CRF_APB_VPLL_CTRL_OFFSET +#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 +#undef CRF_APB_VPLL_CTRL_OFFSET +#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 +#undef CRF_APB_VPLL_CTRL_OFFSET +#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 +#undef CRF_APB_VPLL_CTRL_OFFSET +#define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 +#undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET +#define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 0XFD1A0050 + +/* +* PLL loop filter resistor control +*/ +#undef CRL_APB_RPLL_CFG_RES_DEFVAL +#undef CRL_APB_RPLL_CFG_RES_SHIFT +#undef CRL_APB_RPLL_CFG_RES_MASK +#define CRL_APB_RPLL_CFG_RES_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_RES_SHIFT 0 +#define CRL_APB_RPLL_CFG_RES_MASK 0x0000000FU + +/* +* PLL charge pump control +*/ +#undef CRL_APB_RPLL_CFG_CP_DEFVAL +#undef CRL_APB_RPLL_CFG_CP_SHIFT +#undef CRL_APB_RPLL_CFG_CP_MASK +#define CRL_APB_RPLL_CFG_CP_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_CP_SHIFT 5 +#define CRL_APB_RPLL_CFG_CP_MASK 0x000001E0U + +/* +* PLL loop filter high frequency capacitor control +*/ +#undef CRL_APB_RPLL_CFG_LFHF_DEFVAL +#undef CRL_APB_RPLL_CFG_LFHF_SHIFT +#undef CRL_APB_RPLL_CFG_LFHF_MASK +#define CRL_APB_RPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LFHF_SHIFT 10 +#define CRL_APB_RPLL_CFG_LFHF_MASK 0x00000C00U + +/* +* Lock circuit counter setting +*/ +#undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL +#undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT +#undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK +#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK 0x007FE000U + +/* +* Lock circuit configuration settings for lock windowsize +*/ +#undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL +#undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT +#undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK +#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK 0xFE000000U + +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ +#undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL +#undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT +#undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK +#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK 0x00700000U + +/* +* The integer portion of the feedback divider to the PLL +*/ +#undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL +#undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT +#undef CRL_APB_RPLL_CTRL_FBDIV_MASK +#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8 +#define CRL_APB_RPLL_CTRL_FBDIV_MASK 0x00007F00U + +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ +#undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL +#undef CRL_APB_RPLL_CTRL_DIV2_SHIFT +#undef CRL_APB_RPLL_CTRL_DIV2_MASK +#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16 +#define CRL_APB_RPLL_CTRL_DIV2_MASK 0x00010000U + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL +#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT +#undef CRL_APB_RPLL_CTRL_BYPASS_MASK +#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL +#undef CRL_APB_RPLL_CTRL_RESET_SHIFT +#undef CRL_APB_RPLL_CTRL_RESET_MASK +#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL +#undef CRL_APB_RPLL_CTRL_RESET_SHIFT +#undef CRL_APB_RPLL_CTRL_RESET_MASK +#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U + +/* +* RPLL is locked +*/ +#undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL +#undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT +#undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK +#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 0x00000018 +#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1 +#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 0x00000002U +#define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040 + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL +#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT +#undef CRL_APB_RPLL_CTRL_BYPASS_MASK +#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Divisor value for this clock. +*/ +#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 6 bit divider +*/ +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK +#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK +#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* PLL loop filter resistor control +*/ +#undef CRL_APB_IOPLL_CFG_RES_DEFVAL +#undef CRL_APB_IOPLL_CFG_RES_SHIFT +#undef CRL_APB_IOPLL_CFG_RES_MASK +#define CRL_APB_IOPLL_CFG_RES_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_RES_SHIFT 0 +#define CRL_APB_IOPLL_CFG_RES_MASK 0x0000000FU + +/* +* PLL charge pump control +*/ +#undef CRL_APB_IOPLL_CFG_CP_DEFVAL +#undef CRL_APB_IOPLL_CFG_CP_SHIFT +#undef CRL_APB_IOPLL_CFG_CP_MASK +#define CRL_APB_IOPLL_CFG_CP_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_CP_SHIFT 5 +#define CRL_APB_IOPLL_CFG_CP_MASK 0x000001E0U + +/* +* PLL loop filter high frequency capacitor control +*/ +#undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL +#undef CRL_APB_IOPLL_CFG_LFHF_SHIFT +#undef CRL_APB_IOPLL_CFG_LFHF_MASK +#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10 +#define CRL_APB_IOPLL_CFG_LFHF_MASK 0x00000C00U + +/* +* Lock circuit counter setting +*/ +#undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL +#undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT +#undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK +#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 0x007FE000U + +/* +* Lock circuit configuration settings for lock windowsize +*/ +#undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL +#undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT +#undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK +#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 0xFE000000U + +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ +#undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL +#undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT +#undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK +#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 0x00700000U + +/* +* The integer portion of the feedback divider to the PLL +*/ +#undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL +#undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT +#undef CRL_APB_IOPLL_CTRL_FBDIV_MASK +#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8 +#define CRL_APB_IOPLL_CTRL_FBDIV_MASK 0x00007F00U + +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ +#undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL +#undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT +#undef CRL_APB_IOPLL_CTRL_DIV2_MASK +#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16 +#define CRL_APB_IOPLL_CTRL_DIV2_MASK 0x00010000U + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL +#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT +#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK +#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL +#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT +#undef CRL_APB_IOPLL_CTRL_RESET_MASK +#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL +#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT +#undef CRL_APB_IOPLL_CTRL_RESET_MASK +#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U + +/* +* IOPLL is locked +*/ +#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL +#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT +#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 0x00000018 +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0 +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 0x00000001U +#define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040 + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL +#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT +#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK +#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Divisor value for this clock. +*/ +#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* PLL loop filter resistor control +*/ +#undef CRF_APB_APLL_CFG_RES_DEFVAL +#undef CRF_APB_APLL_CFG_RES_SHIFT +#undef CRF_APB_APLL_CFG_RES_MASK +#define CRF_APB_APLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_RES_SHIFT 0 +#define CRF_APB_APLL_CFG_RES_MASK 0x0000000FU + +/* +* PLL charge pump control +*/ +#undef CRF_APB_APLL_CFG_CP_DEFVAL +#undef CRF_APB_APLL_CFG_CP_SHIFT +#undef CRF_APB_APLL_CFG_CP_MASK +#define CRF_APB_APLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_CP_SHIFT 5 +#define CRF_APB_APLL_CFG_CP_MASK 0x000001E0U + +/* +* PLL loop filter high frequency capacitor control +*/ +#undef CRF_APB_APLL_CFG_LFHF_DEFVAL +#undef CRF_APB_APLL_CFG_LFHF_SHIFT +#undef CRF_APB_APLL_CFG_LFHF_MASK +#define CRF_APB_APLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_APLL_CFG_LFHF_MASK 0x00000C00U + +/* +* Lock circuit counter setting +*/ +#undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL +#undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT +#undef CRF_APB_APLL_CFG_LOCK_CNT_MASK +#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_APLL_CFG_LOCK_CNT_MASK 0x007FE000U + +/* +* Lock circuit configuration settings for lock windowsize +*/ +#undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL +#undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT +#undef CRF_APB_APLL_CFG_LOCK_DLY_MASK +#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_APLL_CFG_LOCK_DLY_MASK 0xFE000000U + +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ +#undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL +#undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT +#undef CRF_APB_APLL_CTRL_PRE_SRC_MASK +#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_APLL_CTRL_PRE_SRC_MASK 0x00700000U + +/* +* The integer portion of the feedback divider to the PLL +*/ +#undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL +#undef CRF_APB_APLL_CTRL_FBDIV_SHIFT +#undef CRF_APB_APLL_CTRL_FBDIV_MASK +#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_APLL_CTRL_FBDIV_MASK 0x00007F00U + +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ +#undef CRF_APB_APLL_CTRL_DIV2_DEFVAL +#undef CRF_APB_APLL_CTRL_DIV2_SHIFT +#undef CRF_APB_APLL_CTRL_DIV2_MASK +#define CRF_APB_APLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_APLL_CTRL_DIV2_MASK 0x00010000U + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL +#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT +#undef CRF_APB_APLL_CTRL_BYPASS_MASK +#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRF_APB_APLL_CTRL_RESET_DEFVAL +#undef CRF_APB_APLL_CTRL_RESET_SHIFT +#undef CRF_APB_APLL_CTRL_RESET_MASK +#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRF_APB_APLL_CTRL_RESET_DEFVAL +#undef CRF_APB_APLL_CTRL_RESET_SHIFT +#undef CRF_APB_APLL_CTRL_RESET_MASK +#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U + +/* +* APLL is locked +*/ +#undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL +#undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT +#undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK +#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0 +#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK 0x00000001U +#define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL +#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT +#undef CRF_APB_APLL_CTRL_BYPASS_MASK +#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Divisor value for this clock. +*/ +#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* PLL loop filter resistor control +*/ +#undef CRF_APB_DPLL_CFG_RES_DEFVAL +#undef CRF_APB_DPLL_CFG_RES_SHIFT +#undef CRF_APB_DPLL_CFG_RES_MASK +#define CRF_APB_DPLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_RES_SHIFT 0 +#define CRF_APB_DPLL_CFG_RES_MASK 0x0000000FU + +/* +* PLL charge pump control +*/ +#undef CRF_APB_DPLL_CFG_CP_DEFVAL +#undef CRF_APB_DPLL_CFG_CP_SHIFT +#undef CRF_APB_DPLL_CFG_CP_MASK +#define CRF_APB_DPLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_CP_SHIFT 5 +#define CRF_APB_DPLL_CFG_CP_MASK 0x000001E0U + +/* +* PLL loop filter high frequency capacitor control +*/ +#undef CRF_APB_DPLL_CFG_LFHF_DEFVAL +#undef CRF_APB_DPLL_CFG_LFHF_SHIFT +#undef CRF_APB_DPLL_CFG_LFHF_MASK +#define CRF_APB_DPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_DPLL_CFG_LFHF_MASK 0x00000C00U + +/* +* Lock circuit counter setting +*/ +#undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL +#undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT +#undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK +#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK 0x007FE000U + +/* +* Lock circuit configuration settings for lock windowsize +*/ +#undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL +#undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT +#undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK +#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK 0xFE000000U + +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ +#undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL +#undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT +#undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK +#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK 0x00700000U + +/* +* The integer portion of the feedback divider to the PLL +*/ +#undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL +#undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT +#undef CRF_APB_DPLL_CTRL_FBDIV_MASK +#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_DPLL_CTRL_FBDIV_MASK 0x00007F00U + +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ +#undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL +#undef CRF_APB_DPLL_CTRL_DIV2_SHIFT +#undef CRF_APB_DPLL_CTRL_DIV2_MASK +#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_DPLL_CTRL_DIV2_MASK 0x00010000U + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL +#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT +#undef CRF_APB_DPLL_CTRL_BYPASS_MASK +#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL +#undef CRF_APB_DPLL_CTRL_RESET_SHIFT +#undef CRF_APB_DPLL_CTRL_RESET_MASK +#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL +#undef CRF_APB_DPLL_CTRL_RESET_SHIFT +#undef CRF_APB_DPLL_CTRL_RESET_MASK +#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U + +/* +* DPLL is locked +*/ +#undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL +#undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT +#undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK +#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1 +#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 0x00000002U +#define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL +#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT +#undef CRF_APB_DPLL_CTRL_BYPASS_MASK +#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Divisor value for this clock. +*/ +#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* PLL loop filter resistor control +*/ +#undef CRF_APB_VPLL_CFG_RES_DEFVAL +#undef CRF_APB_VPLL_CFG_RES_SHIFT +#undef CRF_APB_VPLL_CFG_RES_MASK +#define CRF_APB_VPLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_RES_SHIFT 0 +#define CRF_APB_VPLL_CFG_RES_MASK 0x0000000FU + +/* +* PLL charge pump control +*/ +#undef CRF_APB_VPLL_CFG_CP_DEFVAL +#undef CRF_APB_VPLL_CFG_CP_SHIFT +#undef CRF_APB_VPLL_CFG_CP_MASK +#define CRF_APB_VPLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_CP_SHIFT 5 +#define CRF_APB_VPLL_CFG_CP_MASK 0x000001E0U + +/* +* PLL loop filter high frequency capacitor control +*/ +#undef CRF_APB_VPLL_CFG_LFHF_DEFVAL +#undef CRF_APB_VPLL_CFG_LFHF_SHIFT +#undef CRF_APB_VPLL_CFG_LFHF_MASK +#define CRF_APB_VPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_VPLL_CFG_LFHF_MASK 0x00000C00U + +/* +* Lock circuit counter setting +*/ +#undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL +#undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT +#undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK +#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK 0x007FE000U + +/* +* Lock circuit configuration settings for lock windowsize +*/ +#undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL +#undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT +#undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK +#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK 0xFE000000U + +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ +#undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL +#undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT +#undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK +#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK 0x00700000U + +/* +* The integer portion of the feedback divider to the PLL +*/ +#undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL +#undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT +#undef CRF_APB_VPLL_CTRL_FBDIV_MASK +#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_VPLL_CTRL_FBDIV_MASK 0x00007F00U + +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ +#undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL +#undef CRF_APB_VPLL_CTRL_DIV2_SHIFT +#undef CRF_APB_VPLL_CTRL_DIV2_MASK +#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_VPLL_CTRL_DIV2_MASK 0x00010000U + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL +#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT +#undef CRF_APB_VPLL_CTRL_BYPASS_MASK +#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL +#undef CRF_APB_VPLL_CTRL_RESET_SHIFT +#undef CRF_APB_VPLL_CTRL_RESET_MASK +#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U + +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ +#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL +#undef CRF_APB_VPLL_CTRL_RESET_SHIFT +#undef CRF_APB_VPLL_CTRL_RESET_MASK +#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U + +/* +* VPLL is locked +*/ +#undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL +#undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT +#undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK +#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2 +#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 0x00000004U +#define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 + +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ +#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL +#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT +#undef CRF_APB_VPLL_CTRL_BYPASS_MASK +#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U + +/* +* Divisor value for this clock. +*/ +#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U +#undef CRL_APB_GEM3_REF_CTRL_OFFSET +#define CRL_APB_GEM3_REF_CTRL_OFFSET 0XFF5E005C +#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET +#define CRL_APB_GEM_TSU_REF_CTRL_OFFSET 0XFF5E0100 +#undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET +#define CRL_APB_USB0_BUS_REF_CTRL_OFFSET 0XFF5E0060 +#undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET +#define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 0XFF5E004C +#undef CRL_APB_QSPI_REF_CTRL_OFFSET +#define CRL_APB_QSPI_REF_CTRL_OFFSET 0XFF5E0068 +#undef CRL_APB_SDIO1_REF_CTRL_OFFSET +#define CRL_APB_SDIO1_REF_CTRL_OFFSET 0XFF5E0070 +#undef IOU_SLCR_SDIO_CLK_CTRL_OFFSET +#define IOU_SLCR_SDIO_CLK_CTRL_OFFSET 0XFF18030C +#undef CRL_APB_UART0_REF_CTRL_OFFSET +#define CRL_APB_UART0_REF_CTRL_OFFSET 0XFF5E0074 +#undef CRL_APB_UART1_REF_CTRL_OFFSET +#define CRL_APB_UART1_REF_CTRL_OFFSET 0XFF5E0078 +#undef CRL_APB_I2C0_REF_CTRL_OFFSET +#define CRL_APB_I2C0_REF_CTRL_OFFSET 0XFF5E0120 +#undef CRL_APB_I2C1_REF_CTRL_OFFSET +#define CRL_APB_I2C1_REF_CTRL_OFFSET 0XFF5E0124 +#undef CRL_APB_CAN1_REF_CTRL_OFFSET +#define CRL_APB_CAN1_REF_CTRL_OFFSET 0XFF5E0088 +#undef CRL_APB_CPU_R5_CTRL_OFFSET +#define CRL_APB_CPU_R5_CTRL_OFFSET 0XFF5E0090 +#undef CRL_APB_IOU_SWITCH_CTRL_OFFSET +#define CRL_APB_IOU_SWITCH_CTRL_OFFSET 0XFF5E009C +#undef CRL_APB_PCAP_CTRL_OFFSET +#define CRL_APB_PCAP_CTRL_OFFSET 0XFF5E00A4 +#undef CRL_APB_LPD_SWITCH_CTRL_OFFSET +#define CRL_APB_LPD_SWITCH_CTRL_OFFSET 0XFF5E00A8 +#undef CRL_APB_LPD_LSBUS_CTRL_OFFSET +#define CRL_APB_LPD_LSBUS_CTRL_OFFSET 0XFF5E00AC +#undef CRL_APB_DBG_LPD_CTRL_OFFSET +#define CRL_APB_DBG_LPD_CTRL_OFFSET 0XFF5E00B0 +#undef CRL_APB_ADMA_REF_CTRL_OFFSET +#define CRL_APB_ADMA_REF_CTRL_OFFSET 0XFF5E00B8 +#undef CRL_APB_PL0_REF_CTRL_OFFSET +#define CRL_APB_PL0_REF_CTRL_OFFSET 0XFF5E00C0 +#undef CRL_APB_PL1_REF_CTRL_OFFSET +#define CRL_APB_PL1_REF_CTRL_OFFSET 0XFF5E00C4 +#undef CRL_APB_AMS_REF_CTRL_OFFSET +#define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108 +#undef CRL_APB_DLL_REF_CTRL_OFFSET +#define CRL_APB_DLL_REF_CTRL_OFFSET 0XFF5E0104 +#undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET +#define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 0XFF5E0128 +#undef CRF_APB_SATA_REF_CTRL_OFFSET +#define CRF_APB_SATA_REF_CTRL_OFFSET 0XFD1A00A0 +#undef CRF_APB_PCIE_REF_CTRL_OFFSET +#define CRF_APB_PCIE_REF_CTRL_OFFSET 0XFD1A00B4 +#undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET +#define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 0XFD1A0070 +#undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET +#define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET 0XFD1A0074 +#undef CRF_APB_DP_STC_REF_CTRL_OFFSET +#define CRF_APB_DP_STC_REF_CTRL_OFFSET 0XFD1A007C +#undef CRF_APB_ACPU_CTRL_OFFSET +#define CRF_APB_ACPU_CTRL_OFFSET 0XFD1A0060 +#undef CRF_APB_DBG_FPD_CTRL_OFFSET +#define CRF_APB_DBG_FPD_CTRL_OFFSET 0XFD1A0068 +#undef CRF_APB_DDR_CTRL_OFFSET +#define CRF_APB_DDR_CTRL_OFFSET 0XFD1A0080 +#undef CRF_APB_GPU_REF_CTRL_OFFSET +#define CRF_APB_GPU_REF_CTRL_OFFSET 0XFD1A0084 +#undef CRF_APB_GDMA_REF_CTRL_OFFSET +#define CRF_APB_GDMA_REF_CTRL_OFFSET 0XFD1A00B8 +#undef CRF_APB_DPDMA_REF_CTRL_OFFSET +#define CRF_APB_DPDMA_REF_CTRL_OFFSET 0XFD1A00BC +#undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET +#define CRF_APB_TOPSW_MAIN_CTRL_OFFSET 0XFD1A00C0 +#undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET +#define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 0XFD1A00C4 +#undef CRF_APB_DBG_TSTMP_CTRL_OFFSET +#define CRF_APB_DBG_TSTMP_CTRL_OFFSET 0XFD1A00F8 +#undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET +#define IOU_SLCR_IOU_TTC_APB_CLK_OFFSET 0XFF180380 +#undef FPD_SLCR_WDT_CLK_SEL_OFFSET +#define FPD_SLCR_WDT_CLK_SEL_OFFSET 0XFD610100 +#undef IOU_SLCR_WDT_CLK_SEL_OFFSET +#define IOU_SLCR_WDT_CLK_SEL_OFFSET 0XFF180300 +#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 0XFF410050 + +/* +* Clock active for the RX channel +*/ +#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL +#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT +#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26 +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 0x04000000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK +#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 0x02000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 0x02000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 0x02000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK +#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO + * [51] 1: MIO [76] +*/ +#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL +#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT +#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17 +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK +#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK +#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK +#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK +#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK +#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK +#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK +#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Turing this off will shut down the OCM, some parts of the APM, and preve + * nt transactions going from the FPD to the LPD and could lead to system h + * ang +*/ +#undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL +#undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT +#undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK +#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT +#undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK +#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL +#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT +#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT +#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL +#undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT +#undef CRL_APB_PCAP_CTRL_CLKACT_MASK +#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PCAP_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK +#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT +#undef CRL_APB_PCAP_CTRL_SRCSEL_MASK +#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PCAP_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL +#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT +#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT +#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL +#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT +#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT +#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL +#undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT +#undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK +#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT +#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK +#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK +#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK +#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_PL1_REF_CTRL_CLKACT_MASK +#define CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PL1_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_PL1_REF_CTRL_SRCSEL_MASK +#define CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 6 bit divider +*/ +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK +#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK +#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an + * issue, but designers must be aware.) +*/ +#undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK +#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 0x00000000 +#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 6 bit divider +*/ +#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may + * only be toggled after 4 cycles of the old clock and 4 cycles of the new + * clock. This is not usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK +#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK +#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only + * be toggled after 4 cycles of the old clock and 4 cycles of the new cloc + * k. This is not usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK +#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL +#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT +#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) +*/ +#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL +#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT +#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) +*/ +#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL +#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT +#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg + * led after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK +#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT +#undef CRF_APB_ACPU_CTRL_SRCSEL_MASK +#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_ACPU_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock. For the half spee + * d APU Clock +*/ +#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL +#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT +#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25 +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 0x02000000U + +/* +* Clock active signal. Switch to 0 to disable the clock. For the full spee + * d ACPUX Clock. This will shut off the high speed clock to the entire APU +*/ +#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL +#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT +#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24 +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT +#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL +#undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT +#undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK +#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DDR_CTRL_DIVISOR0_MASK +#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DDR_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an i + * ssue, but designers must be aware.) +*/ +#undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT +#undef CRF_APB_DDR_CTRL_SRCSEL_MASK +#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DDR_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 6 bit divider +*/ +#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK +#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock, which will stop c + * lock for GPU (and both Pixel Processors). +*/ +#undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK +#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor +*/ +#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL +#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT +#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25 +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 0x02000000U + +/* +* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor +*/ +#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL +#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT +#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26 +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 0x04000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK +#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT +#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL +#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT +#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT +#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL +#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT +#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT +#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL +#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT +#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U + +/* +* 6 bit divider +*/ +#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL +#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT +#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 0x00000A00 +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ +#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL +#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT +#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 0x00000A00 +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se + * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5 + * clock for the APB interface of TTC0 +*/ +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 0 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003U + +/* +* 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se + * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5 + * clock for the APB interface of TTC1 +*/ +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 2 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000CU + +/* +* 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se + * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5 + * clock for the APB interface of TTC2 +*/ +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 4 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030U + +/* +* 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se + * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5 + * clock for the APB interface of TTC3 +*/ +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT +#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 6 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 0x000000C0U + +/* +* System watchdog timer clock source selection: 0: Internal APB clock 1: E + * xternal (PL clock via EMIO or Pinout clock via MIO) +*/ +#undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL +#undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT +#undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK +#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 +#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U + +/* +* System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock from PL via EMIO, or from pinout via MIO +*/ +#undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL +#undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT +#undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK +#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 +#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U + +/* +* System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock pss_ref_clk +*/ +#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL +#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT +#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0 +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 0x00000001U +#undef CRF_APB_RST_DDR_SS_OFFSET +#define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108 +#undef DDRC_MSTR_OFFSET +#define DDRC_MSTR_OFFSET 0XFD070000 +#undef DDRC_MRCTRL0_OFFSET +#define DDRC_MRCTRL0_OFFSET 0XFD070010 +#undef DDRC_DERATEEN_OFFSET +#define DDRC_DERATEEN_OFFSET 0XFD070020 +#undef DDRC_DERATEINT_OFFSET +#define DDRC_DERATEINT_OFFSET 0XFD070024 +#undef DDRC_PWRCTL_OFFSET +#define DDRC_PWRCTL_OFFSET 0XFD070030 +#undef DDRC_PWRTMG_OFFSET +#define DDRC_PWRTMG_OFFSET 0XFD070034 +#undef DDRC_RFSHCTL0_OFFSET +#define DDRC_RFSHCTL0_OFFSET 0XFD070050 +#undef DDRC_RFSHCTL1_OFFSET +#define DDRC_RFSHCTL1_OFFSET 0XFD070054 +#undef DDRC_RFSHCTL3_OFFSET +#define DDRC_RFSHCTL3_OFFSET 0XFD070060 +#undef DDRC_RFSHTMG_OFFSET +#define DDRC_RFSHTMG_OFFSET 0XFD070064 +#undef DDRC_ECCCFG0_OFFSET +#define DDRC_ECCCFG0_OFFSET 0XFD070070 +#undef DDRC_ECCCFG1_OFFSET +#define DDRC_ECCCFG1_OFFSET 0XFD070074 +#undef DDRC_CRCPARCTL1_OFFSET +#define DDRC_CRCPARCTL1_OFFSET 0XFD0700C4 +#undef DDRC_CRCPARCTL2_OFFSET +#define DDRC_CRCPARCTL2_OFFSET 0XFD0700C8 +#undef DDRC_INIT0_OFFSET +#define DDRC_INIT0_OFFSET 0XFD0700D0 +#undef DDRC_INIT1_OFFSET +#define DDRC_INIT1_OFFSET 0XFD0700D4 +#undef DDRC_INIT2_OFFSET +#define DDRC_INIT2_OFFSET 0XFD0700D8 +#undef DDRC_INIT3_OFFSET +#define DDRC_INIT3_OFFSET 0XFD0700DC +#undef DDRC_INIT4_OFFSET +#define DDRC_INIT4_OFFSET 0XFD0700E0 +#undef DDRC_INIT5_OFFSET +#define DDRC_INIT5_OFFSET 0XFD0700E4 +#undef DDRC_INIT6_OFFSET +#define DDRC_INIT6_OFFSET 0XFD0700E8 +#undef DDRC_INIT7_OFFSET +#define DDRC_INIT7_OFFSET 0XFD0700EC +#undef DDRC_DIMMCTL_OFFSET +#define DDRC_DIMMCTL_OFFSET 0XFD0700F0 +#undef DDRC_RANKCTL_OFFSET +#define DDRC_RANKCTL_OFFSET 0XFD0700F4 +#undef DDRC_DRAMTMG0_OFFSET +#define DDRC_DRAMTMG0_OFFSET 0XFD070100 +#undef DDRC_DRAMTMG1_OFFSET +#define DDRC_DRAMTMG1_OFFSET 0XFD070104 +#undef DDRC_DRAMTMG2_OFFSET +#define DDRC_DRAMTMG2_OFFSET 0XFD070108 +#undef DDRC_DRAMTMG3_OFFSET +#define DDRC_DRAMTMG3_OFFSET 0XFD07010C +#undef DDRC_DRAMTMG4_OFFSET +#define DDRC_DRAMTMG4_OFFSET 0XFD070110 +#undef DDRC_DRAMTMG5_OFFSET +#define DDRC_DRAMTMG5_OFFSET 0XFD070114 +#undef DDRC_DRAMTMG6_OFFSET +#define DDRC_DRAMTMG6_OFFSET 0XFD070118 +#undef DDRC_DRAMTMG7_OFFSET +#define DDRC_DRAMTMG7_OFFSET 0XFD07011C +#undef DDRC_DRAMTMG8_OFFSET +#define DDRC_DRAMTMG8_OFFSET 0XFD070120 +#undef DDRC_DRAMTMG9_OFFSET +#define DDRC_DRAMTMG9_OFFSET 0XFD070124 +#undef DDRC_DRAMTMG11_OFFSET +#define DDRC_DRAMTMG11_OFFSET 0XFD07012C +#undef DDRC_DRAMTMG12_OFFSET +#define DDRC_DRAMTMG12_OFFSET 0XFD070130 +#undef DDRC_ZQCTL0_OFFSET +#define DDRC_ZQCTL0_OFFSET 0XFD070180 +#undef DDRC_ZQCTL1_OFFSET +#define DDRC_ZQCTL1_OFFSET 0XFD070184 +#undef DDRC_DFITMG0_OFFSET +#define DDRC_DFITMG0_OFFSET 0XFD070190 +#undef DDRC_DFITMG1_OFFSET +#define DDRC_DFITMG1_OFFSET 0XFD070194 +#undef DDRC_DFILPCFG0_OFFSET +#define DDRC_DFILPCFG0_OFFSET 0XFD070198 +#undef DDRC_DFILPCFG1_OFFSET +#define DDRC_DFILPCFG1_OFFSET 0XFD07019C +#undef DDRC_DFIUPD0_OFFSET +#define DDRC_DFIUPD0_OFFSET 0XFD0701A0 +#undef DDRC_DFIUPD1_OFFSET +#define DDRC_DFIUPD1_OFFSET 0XFD0701A4 +#undef DDRC_DFIMISC_OFFSET +#define DDRC_DFIMISC_OFFSET 0XFD0701B0 +#undef DDRC_DFITMG2_OFFSET +#define DDRC_DFITMG2_OFFSET 0XFD0701B4 +#undef DDRC_DBICTL_OFFSET +#define DDRC_DBICTL_OFFSET 0XFD0701C0 +#undef DDRC_ADDRMAP0_OFFSET +#define DDRC_ADDRMAP0_OFFSET 0XFD070200 +#undef DDRC_ADDRMAP1_OFFSET +#define DDRC_ADDRMAP1_OFFSET 0XFD070204 +#undef DDRC_ADDRMAP2_OFFSET +#define DDRC_ADDRMAP2_OFFSET 0XFD070208 +#undef DDRC_ADDRMAP3_OFFSET +#define DDRC_ADDRMAP3_OFFSET 0XFD07020C +#undef DDRC_ADDRMAP4_OFFSET +#define DDRC_ADDRMAP4_OFFSET 0XFD070210 +#undef DDRC_ADDRMAP5_OFFSET +#define DDRC_ADDRMAP5_OFFSET 0XFD070214 +#undef DDRC_ADDRMAP6_OFFSET +#define DDRC_ADDRMAP6_OFFSET 0XFD070218 +#undef DDRC_ADDRMAP7_OFFSET +#define DDRC_ADDRMAP7_OFFSET 0XFD07021C +#undef DDRC_ADDRMAP8_OFFSET +#define DDRC_ADDRMAP8_OFFSET 0XFD070220 +#undef DDRC_ADDRMAP9_OFFSET +#define DDRC_ADDRMAP9_OFFSET 0XFD070224 +#undef DDRC_ADDRMAP10_OFFSET +#define DDRC_ADDRMAP10_OFFSET 0XFD070228 +#undef DDRC_ADDRMAP11_OFFSET +#define DDRC_ADDRMAP11_OFFSET 0XFD07022C +#undef DDRC_ODTCFG_OFFSET +#define DDRC_ODTCFG_OFFSET 0XFD070240 +#undef DDRC_ODTMAP_OFFSET +#define DDRC_ODTMAP_OFFSET 0XFD070244 +#undef DDRC_SCHED_OFFSET +#define DDRC_SCHED_OFFSET 0XFD070250 +#undef DDRC_PERFLPR1_OFFSET +#define DDRC_PERFLPR1_OFFSET 0XFD070264 +#undef DDRC_PERFWR1_OFFSET +#define DDRC_PERFWR1_OFFSET 0XFD07026C +#undef DDRC_DQMAP0_OFFSET +#define DDRC_DQMAP0_OFFSET 0XFD070280 +#undef DDRC_DQMAP1_OFFSET +#define DDRC_DQMAP1_OFFSET 0XFD070284 +#undef DDRC_DQMAP2_OFFSET +#define DDRC_DQMAP2_OFFSET 0XFD070288 +#undef DDRC_DQMAP3_OFFSET +#define DDRC_DQMAP3_OFFSET 0XFD07028C +#undef DDRC_DQMAP4_OFFSET +#define DDRC_DQMAP4_OFFSET 0XFD070290 +#undef DDRC_DQMAP5_OFFSET +#define DDRC_DQMAP5_OFFSET 0XFD070294 +#undef DDRC_DBG0_OFFSET +#define DDRC_DBG0_OFFSET 0XFD070300 +#undef DDRC_DBGCMD_OFFSET +#define DDRC_DBGCMD_OFFSET 0XFD07030C +#undef DDRC_SWCTL_OFFSET +#define DDRC_SWCTL_OFFSET 0XFD070320 +#undef DDRC_PCCFG_OFFSET +#define DDRC_PCCFG_OFFSET 0XFD070400 +#undef DDRC_PCFGR_0_OFFSET +#define DDRC_PCFGR_0_OFFSET 0XFD070404 +#undef DDRC_PCFGW_0_OFFSET +#define DDRC_PCFGW_0_OFFSET 0XFD070408 +#undef DDRC_PCTRL_0_OFFSET +#define DDRC_PCTRL_0_OFFSET 0XFD070490 +#undef DDRC_PCFGQOS0_0_OFFSET +#define DDRC_PCFGQOS0_0_OFFSET 0XFD070494 +#undef DDRC_PCFGQOS1_0_OFFSET +#define DDRC_PCFGQOS1_0_OFFSET 0XFD070498 +#undef DDRC_PCFGR_1_OFFSET +#define DDRC_PCFGR_1_OFFSET 0XFD0704B4 +#undef DDRC_PCFGW_1_OFFSET +#define DDRC_PCFGW_1_OFFSET 0XFD0704B8 +#undef DDRC_PCTRL_1_OFFSET +#define DDRC_PCTRL_1_OFFSET 0XFD070540 +#undef DDRC_PCFGQOS0_1_OFFSET +#define DDRC_PCFGQOS0_1_OFFSET 0XFD070544 +#undef DDRC_PCFGQOS1_1_OFFSET +#define DDRC_PCFGQOS1_1_OFFSET 0XFD070548 +#undef DDRC_PCFGR_2_OFFSET +#define DDRC_PCFGR_2_OFFSET 0XFD070564 +#undef DDRC_PCFGW_2_OFFSET +#define DDRC_PCFGW_2_OFFSET 0XFD070568 +#undef DDRC_PCTRL_2_OFFSET +#define DDRC_PCTRL_2_OFFSET 0XFD0705F0 +#undef DDRC_PCFGQOS0_2_OFFSET +#define DDRC_PCFGQOS0_2_OFFSET 0XFD0705F4 +#undef DDRC_PCFGQOS1_2_OFFSET +#define DDRC_PCFGQOS1_2_OFFSET 0XFD0705F8 +#undef DDRC_PCFGR_3_OFFSET +#define DDRC_PCFGR_3_OFFSET 0XFD070614 +#undef DDRC_PCFGW_3_OFFSET +#define DDRC_PCFGW_3_OFFSET 0XFD070618 +#undef DDRC_PCTRL_3_OFFSET +#define DDRC_PCTRL_3_OFFSET 0XFD0706A0 +#undef DDRC_PCFGQOS0_3_OFFSET +#define DDRC_PCFGQOS0_3_OFFSET 0XFD0706A4 +#undef DDRC_PCFGQOS1_3_OFFSET +#define DDRC_PCFGQOS1_3_OFFSET 0XFD0706A8 +#undef DDRC_PCFGWQOS0_3_OFFSET +#define DDRC_PCFGWQOS0_3_OFFSET 0XFD0706AC +#undef DDRC_PCFGWQOS1_3_OFFSET +#define DDRC_PCFGWQOS1_3_OFFSET 0XFD0706B0 +#undef DDRC_PCFGR_4_OFFSET +#define DDRC_PCFGR_4_OFFSET 0XFD0706C4 +#undef DDRC_PCFGW_4_OFFSET +#define DDRC_PCFGW_4_OFFSET 0XFD0706C8 +#undef DDRC_PCTRL_4_OFFSET +#define DDRC_PCTRL_4_OFFSET 0XFD070750 +#undef DDRC_PCFGQOS0_4_OFFSET +#define DDRC_PCFGQOS0_4_OFFSET 0XFD070754 +#undef DDRC_PCFGQOS1_4_OFFSET +#define DDRC_PCFGQOS1_4_OFFSET 0XFD070758 +#undef DDRC_PCFGWQOS0_4_OFFSET +#define DDRC_PCFGWQOS0_4_OFFSET 0XFD07075C +#undef DDRC_PCFGWQOS1_4_OFFSET +#define DDRC_PCFGWQOS1_4_OFFSET 0XFD070760 +#undef DDRC_PCFGR_5_OFFSET +#define DDRC_PCFGR_5_OFFSET 0XFD070774 +#undef DDRC_PCFGW_5_OFFSET +#define DDRC_PCFGW_5_OFFSET 0XFD070778 +#undef DDRC_PCTRL_5_OFFSET +#define DDRC_PCTRL_5_OFFSET 0XFD070800 +#undef DDRC_PCFGQOS0_5_OFFSET +#define DDRC_PCFGQOS0_5_OFFSET 0XFD070804 +#undef DDRC_PCFGQOS1_5_OFFSET +#define DDRC_PCFGQOS1_5_OFFSET 0XFD070808 +#undef DDRC_PCFGWQOS0_5_OFFSET +#define DDRC_PCFGWQOS0_5_OFFSET 0XFD07080C +#undef DDRC_PCFGWQOS1_5_OFFSET +#define DDRC_PCFGWQOS1_5_OFFSET 0XFD070810 +#undef DDRC_SARBASE0_OFFSET +#define DDRC_SARBASE0_OFFSET 0XFD070F04 +#undef DDRC_SARSIZE0_OFFSET +#define DDRC_SARSIZE0_OFFSET 0XFD070F08 +#undef DDRC_SARBASE1_OFFSET +#define DDRC_SARBASE1_OFFSET 0XFD070F0C +#undef DDRC_SARSIZE1_OFFSET +#define DDRC_SARSIZE1_OFFSET 0XFD070F10 +#undef DDRC_DFITMG0_SHADOW_OFFSET +#define DDRC_DFITMG0_SHADOW_OFFSET 0XFD072190 +#undef CRF_APB_RST_DDR_SS_OFFSET +#define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108 +#undef DDR_PHY_PGCR0_OFFSET +#define DDR_PHY_PGCR0_OFFSET 0XFD080010 +#undef DDR_PHY_PGCR2_OFFSET +#define DDR_PHY_PGCR2_OFFSET 0XFD080018 +#undef DDR_PHY_PGCR3_OFFSET +#define DDR_PHY_PGCR3_OFFSET 0XFD08001C +#undef DDR_PHY_PGCR5_OFFSET +#define DDR_PHY_PGCR5_OFFSET 0XFD080024 +#undef DDR_PHY_PTR0_OFFSET +#define DDR_PHY_PTR0_OFFSET 0XFD080040 +#undef DDR_PHY_PTR1_OFFSET +#define DDR_PHY_PTR1_OFFSET 0XFD080044 +#undef DDR_PHY_PLLCR0_OFFSET +#define DDR_PHY_PLLCR0_OFFSET 0XFD080068 +#undef DDR_PHY_DSGCR_OFFSET +#define DDR_PHY_DSGCR_OFFSET 0XFD080090 +#undef DDR_PHY_GPR0_OFFSET +#define DDR_PHY_GPR0_OFFSET 0XFD0800C0 +#undef DDR_PHY_GPR1_OFFSET +#define DDR_PHY_GPR1_OFFSET 0XFD0800C4 +#undef DDR_PHY_DCR_OFFSET +#define DDR_PHY_DCR_OFFSET 0XFD080100 +#undef DDR_PHY_DTPR0_OFFSET +#define DDR_PHY_DTPR0_OFFSET 0XFD080110 +#undef DDR_PHY_DTPR1_OFFSET +#define DDR_PHY_DTPR1_OFFSET 0XFD080114 +#undef DDR_PHY_DTPR2_OFFSET +#define DDR_PHY_DTPR2_OFFSET 0XFD080118 +#undef DDR_PHY_DTPR3_OFFSET +#define DDR_PHY_DTPR3_OFFSET 0XFD08011C +#undef DDR_PHY_DTPR4_OFFSET +#define DDR_PHY_DTPR4_OFFSET 0XFD080120 +#undef DDR_PHY_DTPR5_OFFSET +#define DDR_PHY_DTPR5_OFFSET 0XFD080124 +#undef DDR_PHY_DTPR6_OFFSET +#define DDR_PHY_DTPR6_OFFSET 0XFD080128 +#undef DDR_PHY_RDIMMGCR0_OFFSET +#define DDR_PHY_RDIMMGCR0_OFFSET 0XFD080140 +#undef DDR_PHY_RDIMMGCR1_OFFSET +#define DDR_PHY_RDIMMGCR1_OFFSET 0XFD080144 +#undef DDR_PHY_RDIMMCR0_OFFSET +#define DDR_PHY_RDIMMCR0_OFFSET 0XFD080150 +#undef DDR_PHY_RDIMMCR1_OFFSET +#define DDR_PHY_RDIMMCR1_OFFSET 0XFD080154 +#undef DDR_PHY_MR0_OFFSET +#define DDR_PHY_MR0_OFFSET 0XFD080180 +#undef DDR_PHY_MR1_OFFSET +#define DDR_PHY_MR1_OFFSET 0XFD080184 +#undef DDR_PHY_MR2_OFFSET +#define DDR_PHY_MR2_OFFSET 0XFD080188 +#undef DDR_PHY_MR3_OFFSET +#define DDR_PHY_MR3_OFFSET 0XFD08018C +#undef DDR_PHY_MR4_OFFSET +#define DDR_PHY_MR4_OFFSET 0XFD080190 +#undef DDR_PHY_MR5_OFFSET +#define DDR_PHY_MR5_OFFSET 0XFD080194 +#undef DDR_PHY_MR6_OFFSET +#define DDR_PHY_MR6_OFFSET 0XFD080198 +#undef DDR_PHY_MR11_OFFSET +#define DDR_PHY_MR11_OFFSET 0XFD0801AC +#undef DDR_PHY_MR12_OFFSET +#define DDR_PHY_MR12_OFFSET 0XFD0801B0 +#undef DDR_PHY_MR13_OFFSET +#define DDR_PHY_MR13_OFFSET 0XFD0801B4 +#undef DDR_PHY_MR14_OFFSET +#define DDR_PHY_MR14_OFFSET 0XFD0801B8 +#undef DDR_PHY_MR22_OFFSET +#define DDR_PHY_MR22_OFFSET 0XFD0801D8 +#undef DDR_PHY_DTCR0_OFFSET +#define DDR_PHY_DTCR0_OFFSET 0XFD080200 +#undef DDR_PHY_DTCR1_OFFSET +#define DDR_PHY_DTCR1_OFFSET 0XFD080204 +#undef DDR_PHY_CATR0_OFFSET +#define DDR_PHY_CATR0_OFFSET 0XFD080240 +#undef DDR_PHY_DQSDR0_OFFSET +#define DDR_PHY_DQSDR0_OFFSET 0XFD080250 +#undef DDR_PHY_BISTLSR_OFFSET +#define DDR_PHY_BISTLSR_OFFSET 0XFD080414 +#undef DDR_PHY_RIOCR5_OFFSET +#define DDR_PHY_RIOCR5_OFFSET 0XFD0804F4 +#undef DDR_PHY_ACIOCR0_OFFSET +#define DDR_PHY_ACIOCR0_OFFSET 0XFD080500 +#undef DDR_PHY_ACIOCR2_OFFSET +#define DDR_PHY_ACIOCR2_OFFSET 0XFD080508 +#undef DDR_PHY_ACIOCR3_OFFSET +#define DDR_PHY_ACIOCR3_OFFSET 0XFD08050C +#undef DDR_PHY_ACIOCR4_OFFSET +#define DDR_PHY_ACIOCR4_OFFSET 0XFD080510 +#undef DDR_PHY_IOVCR0_OFFSET +#define DDR_PHY_IOVCR0_OFFSET 0XFD080520 +#undef DDR_PHY_VTCR0_OFFSET +#define DDR_PHY_VTCR0_OFFSET 0XFD080528 +#undef DDR_PHY_VTCR1_OFFSET +#define DDR_PHY_VTCR1_OFFSET 0XFD08052C +#undef DDR_PHY_ACBDLR1_OFFSET +#define DDR_PHY_ACBDLR1_OFFSET 0XFD080544 +#undef DDR_PHY_ACBDLR2_OFFSET +#define DDR_PHY_ACBDLR2_OFFSET 0XFD080548 +#undef DDR_PHY_ACBDLR6_OFFSET +#define DDR_PHY_ACBDLR6_OFFSET 0XFD080558 +#undef DDR_PHY_ACBDLR7_OFFSET +#define DDR_PHY_ACBDLR7_OFFSET 0XFD08055C +#undef DDR_PHY_ACBDLR8_OFFSET +#define DDR_PHY_ACBDLR8_OFFSET 0XFD080560 +#undef DDR_PHY_ACBDLR9_OFFSET +#define DDR_PHY_ACBDLR9_OFFSET 0XFD080564 +#undef DDR_PHY_ZQCR_OFFSET +#define DDR_PHY_ZQCR_OFFSET 0XFD080680 +#undef DDR_PHY_ZQ0PR0_OFFSET +#define DDR_PHY_ZQ0PR0_OFFSET 0XFD080684 +#undef DDR_PHY_ZQ0OR0_OFFSET +#define DDR_PHY_ZQ0OR0_OFFSET 0XFD080694 +#undef DDR_PHY_ZQ0OR1_OFFSET +#define DDR_PHY_ZQ0OR1_OFFSET 0XFD080698 +#undef DDR_PHY_ZQ1PR0_OFFSET +#define DDR_PHY_ZQ1PR0_OFFSET 0XFD0806A4 +#undef DDR_PHY_DX0GCR0_OFFSET +#define DDR_PHY_DX0GCR0_OFFSET 0XFD080700 +#undef DDR_PHY_DX0GCR1_OFFSET +#define DDR_PHY_DX0GCR1_OFFSET 0XFD080704 +#undef DDR_PHY_DX0GCR3_OFFSET +#define DDR_PHY_DX0GCR3_OFFSET 0XFD08070C +#undef DDR_PHY_DX0GCR4_OFFSET +#define DDR_PHY_DX0GCR4_OFFSET 0XFD080710 +#undef DDR_PHY_DX0GCR5_OFFSET +#define DDR_PHY_DX0GCR5_OFFSET 0XFD080714 +#undef DDR_PHY_DX0GCR6_OFFSET +#define DDR_PHY_DX0GCR6_OFFSET 0XFD080718 +#undef DDR_PHY_DX1GCR0_OFFSET +#define DDR_PHY_DX1GCR0_OFFSET 0XFD080800 +#undef DDR_PHY_DX1GCR1_OFFSET +#define DDR_PHY_DX1GCR1_OFFSET 0XFD080804 +#undef DDR_PHY_DX1GCR3_OFFSET +#define DDR_PHY_DX1GCR3_OFFSET 0XFD08080C +#undef DDR_PHY_DX1GCR4_OFFSET +#define DDR_PHY_DX1GCR4_OFFSET 0XFD080810 +#undef DDR_PHY_DX1GCR5_OFFSET +#define DDR_PHY_DX1GCR5_OFFSET 0XFD080814 +#undef DDR_PHY_DX1GCR6_OFFSET +#define DDR_PHY_DX1GCR6_OFFSET 0XFD080818 +#undef DDR_PHY_DX2GCR0_OFFSET +#define DDR_PHY_DX2GCR0_OFFSET 0XFD080900 +#undef DDR_PHY_DX2GCR1_OFFSET +#define DDR_PHY_DX2GCR1_OFFSET 0XFD080904 +#undef DDR_PHY_DX2GCR3_OFFSET +#define DDR_PHY_DX2GCR3_OFFSET 0XFD08090C +#undef DDR_PHY_DX2GCR4_OFFSET +#define DDR_PHY_DX2GCR4_OFFSET 0XFD080910 +#undef DDR_PHY_DX2GCR5_OFFSET +#define DDR_PHY_DX2GCR5_OFFSET 0XFD080914 +#undef DDR_PHY_DX2GCR6_OFFSET +#define DDR_PHY_DX2GCR6_OFFSET 0XFD080918 +#undef DDR_PHY_DX3GCR0_OFFSET +#define DDR_PHY_DX3GCR0_OFFSET 0XFD080A00 +#undef DDR_PHY_DX3GCR1_OFFSET +#define DDR_PHY_DX3GCR1_OFFSET 0XFD080A04 +#undef DDR_PHY_DX3GCR3_OFFSET +#define DDR_PHY_DX3GCR3_OFFSET 0XFD080A0C +#undef DDR_PHY_DX3GCR4_OFFSET +#define DDR_PHY_DX3GCR4_OFFSET 0XFD080A10 +#undef DDR_PHY_DX3GCR5_OFFSET +#define DDR_PHY_DX3GCR5_OFFSET 0XFD080A14 +#undef DDR_PHY_DX3GCR6_OFFSET +#define DDR_PHY_DX3GCR6_OFFSET 0XFD080A18 +#undef DDR_PHY_DX4GCR0_OFFSET +#define DDR_PHY_DX4GCR0_OFFSET 0XFD080B00 +#undef DDR_PHY_DX4GCR1_OFFSET +#define DDR_PHY_DX4GCR1_OFFSET 0XFD080B04 +#undef DDR_PHY_DX4GCR2_OFFSET +#define DDR_PHY_DX4GCR2_OFFSET 0XFD080B08 +#undef DDR_PHY_DX4GCR3_OFFSET +#define DDR_PHY_DX4GCR3_OFFSET 0XFD080B0C +#undef DDR_PHY_DX4GCR4_OFFSET +#define DDR_PHY_DX4GCR4_OFFSET 0XFD080B10 +#undef DDR_PHY_DX4GCR5_OFFSET +#define DDR_PHY_DX4GCR5_OFFSET 0XFD080B14 +#undef DDR_PHY_DX4GCR6_OFFSET +#define DDR_PHY_DX4GCR6_OFFSET 0XFD080B18 +#undef DDR_PHY_DX5GCR0_OFFSET +#define DDR_PHY_DX5GCR0_OFFSET 0XFD080C00 +#undef DDR_PHY_DX5GCR1_OFFSET +#define DDR_PHY_DX5GCR1_OFFSET 0XFD080C04 +#undef DDR_PHY_DX5GCR2_OFFSET +#define DDR_PHY_DX5GCR2_OFFSET 0XFD080C08 +#undef DDR_PHY_DX5GCR3_OFFSET +#define DDR_PHY_DX5GCR3_OFFSET 0XFD080C0C +#undef DDR_PHY_DX5GCR4_OFFSET +#define DDR_PHY_DX5GCR4_OFFSET 0XFD080C10 +#undef DDR_PHY_DX5GCR5_OFFSET +#define DDR_PHY_DX5GCR5_OFFSET 0XFD080C14 +#undef DDR_PHY_DX5GCR6_OFFSET +#define DDR_PHY_DX5GCR6_OFFSET 0XFD080C18 +#undef DDR_PHY_DX6GCR0_OFFSET +#define DDR_PHY_DX6GCR0_OFFSET 0XFD080D00 +#undef DDR_PHY_DX6GCR1_OFFSET +#define DDR_PHY_DX6GCR1_OFFSET 0XFD080D04 +#undef DDR_PHY_DX6GCR2_OFFSET +#define DDR_PHY_DX6GCR2_OFFSET 0XFD080D08 +#undef DDR_PHY_DX6GCR3_OFFSET +#define DDR_PHY_DX6GCR3_OFFSET 0XFD080D0C +#undef DDR_PHY_DX6GCR4_OFFSET +#define DDR_PHY_DX6GCR4_OFFSET 0XFD080D10 +#undef DDR_PHY_DX6GCR5_OFFSET +#define DDR_PHY_DX6GCR5_OFFSET 0XFD080D14 +#undef DDR_PHY_DX6GCR6_OFFSET +#define DDR_PHY_DX6GCR6_OFFSET 0XFD080D18 +#undef DDR_PHY_DX7GCR0_OFFSET +#define DDR_PHY_DX7GCR0_OFFSET 0XFD080E00 +#undef DDR_PHY_DX7GCR1_OFFSET +#define DDR_PHY_DX7GCR1_OFFSET 0XFD080E04 +#undef DDR_PHY_DX7GCR2_OFFSET +#define DDR_PHY_DX7GCR2_OFFSET 0XFD080E08 +#undef DDR_PHY_DX7GCR3_OFFSET +#define DDR_PHY_DX7GCR3_OFFSET 0XFD080E0C +#undef DDR_PHY_DX7GCR4_OFFSET +#define DDR_PHY_DX7GCR4_OFFSET 0XFD080E10 +#undef DDR_PHY_DX7GCR5_OFFSET +#define DDR_PHY_DX7GCR5_OFFSET 0XFD080E14 +#undef DDR_PHY_DX7GCR6_OFFSET +#define DDR_PHY_DX7GCR6_OFFSET 0XFD080E18 +#undef DDR_PHY_DX8GCR0_OFFSET +#define DDR_PHY_DX8GCR0_OFFSET 0XFD080F00 +#undef DDR_PHY_DX8GCR1_OFFSET +#define DDR_PHY_DX8GCR1_OFFSET 0XFD080F04 +#undef DDR_PHY_DX8GCR2_OFFSET +#define DDR_PHY_DX8GCR2_OFFSET 0XFD080F08 +#undef DDR_PHY_DX8GCR3_OFFSET +#define DDR_PHY_DX8GCR3_OFFSET 0XFD080F0C +#undef DDR_PHY_DX8GCR4_OFFSET +#define DDR_PHY_DX8GCR4_OFFSET 0XFD080F10 +#undef DDR_PHY_DX8GCR5_OFFSET +#define DDR_PHY_DX8GCR5_OFFSET 0XFD080F14 +#undef DDR_PHY_DX8GCR6_OFFSET +#define DDR_PHY_DX8GCR6_OFFSET 0XFD080F18 +#undef DDR_PHY_DX8SL0OSC_OFFSET +#define DDR_PHY_DX8SL0OSC_OFFSET 0XFD081400 +#undef DDR_PHY_DX8SL0PLLCR0_OFFSET +#define DDR_PHY_DX8SL0PLLCR0_OFFSET 0XFD081404 +#undef DDR_PHY_DX8SL0DQSCTL_OFFSET +#define DDR_PHY_DX8SL0DQSCTL_OFFSET 0XFD08141C +#undef DDR_PHY_DX8SL0DXCTL2_OFFSET +#define DDR_PHY_DX8SL0DXCTL2_OFFSET 0XFD08142C +#undef DDR_PHY_DX8SL0IOCR_OFFSET +#define DDR_PHY_DX8SL0IOCR_OFFSET 0XFD081430 +#undef DDR_PHY_DX8SL1OSC_OFFSET +#define DDR_PHY_DX8SL1OSC_OFFSET 0XFD081440 +#undef DDR_PHY_DX8SL1PLLCR0_OFFSET +#define DDR_PHY_DX8SL1PLLCR0_OFFSET 0XFD081444 +#undef DDR_PHY_DX8SL1DQSCTL_OFFSET +#define DDR_PHY_DX8SL1DQSCTL_OFFSET 0XFD08145C +#undef DDR_PHY_DX8SL1DXCTL2_OFFSET +#define DDR_PHY_DX8SL1DXCTL2_OFFSET 0XFD08146C +#undef DDR_PHY_DX8SL1IOCR_OFFSET +#define DDR_PHY_DX8SL1IOCR_OFFSET 0XFD081470 +#undef DDR_PHY_DX8SL2OSC_OFFSET +#define DDR_PHY_DX8SL2OSC_OFFSET 0XFD081480 +#undef DDR_PHY_DX8SL2PLLCR0_OFFSET +#define DDR_PHY_DX8SL2PLLCR0_OFFSET 0XFD081484 +#undef DDR_PHY_DX8SL2DQSCTL_OFFSET +#define DDR_PHY_DX8SL2DQSCTL_OFFSET 0XFD08149C +#undef DDR_PHY_DX8SL2DXCTL2_OFFSET +#define DDR_PHY_DX8SL2DXCTL2_OFFSET 0XFD0814AC +#undef DDR_PHY_DX8SL2IOCR_OFFSET +#define DDR_PHY_DX8SL2IOCR_OFFSET 0XFD0814B0 +#undef DDR_PHY_DX8SL3OSC_OFFSET +#define DDR_PHY_DX8SL3OSC_OFFSET 0XFD0814C0 +#undef DDR_PHY_DX8SL3PLLCR0_OFFSET +#define DDR_PHY_DX8SL3PLLCR0_OFFSET 0XFD0814C4 +#undef DDR_PHY_DX8SL3DQSCTL_OFFSET +#define DDR_PHY_DX8SL3DQSCTL_OFFSET 0XFD0814DC +#undef DDR_PHY_DX8SL3DXCTL2_OFFSET +#define DDR_PHY_DX8SL3DXCTL2_OFFSET 0XFD0814EC +#undef DDR_PHY_DX8SL3IOCR_OFFSET +#define DDR_PHY_DX8SL3IOCR_OFFSET 0XFD0814F0 +#undef DDR_PHY_DX8SL4OSC_OFFSET +#define DDR_PHY_DX8SL4OSC_OFFSET 0XFD081500 +#undef DDR_PHY_DX8SL4PLLCR0_OFFSET +#define DDR_PHY_DX8SL4PLLCR0_OFFSET 0XFD081504 +#undef DDR_PHY_DX8SL4DQSCTL_OFFSET +#define DDR_PHY_DX8SL4DQSCTL_OFFSET 0XFD08151C +#undef DDR_PHY_DX8SL4DXCTL2_OFFSET +#define DDR_PHY_DX8SL4DXCTL2_OFFSET 0XFD08152C +#undef DDR_PHY_DX8SL4IOCR_OFFSET +#define DDR_PHY_DX8SL4IOCR_OFFSET 0XFD081530 +#undef DDR_PHY_DX8SLBDQSCTL_OFFSET +#define DDR_PHY_DX8SLBDQSCTL_OFFSET 0XFD0817DC + +/* +* DDR block level reset inside of the DDR Sub System +*/ +#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL +#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT +#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK +#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 +#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U + +/* +* Indicates the configuration of the device used in the system. - 00 - x4 + * device - 01 - x8 device - 10 - x16 device - 11 - x32 device +*/ +#undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL +#undef DDRC_MSTR_DEVICE_CONFIG_SHIFT +#undef DDRC_MSTR_DEVICE_CONFIG_MASK +#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL 0x03040001 +#define DDRC_MSTR_DEVICE_CONFIG_SHIFT 30 +#define DDRC_MSTR_DEVICE_CONFIG_MASK 0xC0000000U + +/* +* Choose which registers are used. - 0 - Original registers - 1 - Shadow r + * egisters +*/ +#undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL +#undef DDRC_MSTR_FREQUENCY_MODE_SHIFT +#undef DDRC_MSTR_FREQUENCY_MODE_MASK +#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_FREQUENCY_MODE_SHIFT 29 +#define DDRC_MSTR_FREQUENCY_MODE_MASK 0x20000000U + +/* +* Only present for multi-rank configurations. Each bit represents one rank + * . For two-rank configurations, only bits[25:24] are present. - 1 - popul + * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow + * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others - + * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran + * k - 0011 - Two ranks - 1111 - Four ranks +*/ +#undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL +#undef DDRC_MSTR_ACTIVE_RANKS_SHIFT +#undef DDRC_MSTR_ACTIVE_RANKS_MASK +#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL 0x03040001 +#define DDRC_MSTR_ACTIVE_RANKS_SHIFT 24 +#define DDRC_MSTR_ACTIVE_RANKS_MASK 0x03000000U + +/* +* SDRAM burst length used: - 0001 - Burst length of 2 (only supported for + * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur + * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other + * values are reserved. This controls the burst size used to access the SDR + * AM. This must match the burst length mode register setting in the SDRAM. + * (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) + * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH + * is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 +*/ +#undef DDRC_MSTR_BURST_RDWR_DEFVAL +#undef DDRC_MSTR_BURST_RDWR_SHIFT +#undef DDRC_MSTR_BURST_RDWR_MASK +#define DDRC_MSTR_BURST_RDWR_DEFVAL 0x03040001 +#define DDRC_MSTR_BURST_RDWR_SHIFT 16 +#define DDRC_MSTR_BURST_RDWR_MASK 0x000F0000U + +/* +* Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low + * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for + * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC + * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi + * s bit must be set to '0'. +*/ +#undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL +#undef DDRC_MSTR_DLL_OFF_MODE_SHIFT +#undef DDRC_MSTR_DLL_OFF_MODE_MASK +#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_DLL_OFF_MODE_SHIFT 15 +#define DDRC_MSTR_DLL_OFF_MODE_MASK 0x00008000U + +/* +* Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full + * DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter + * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is + * only supported when the SDRAM bus width is a multiple of 16, and quarter + * bus width mode is only supported when the SDRAM bus width is a multiple + * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid + * th refers to DQ bus width (excluding any ECC width). +*/ +#undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL +#undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT +#undef DDRC_MSTR_DATA_BUS_WIDTH_MASK +#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 0x03040001 +#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12 +#define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x00003000U + +/* +* 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D + * RAM in normal mode (1N). This register can be changed, only when the Con + * troller is in self-refresh mode. This signal must be set the same value + * as MR3 bit A3. Note: Geardown mode is not supported if the configuration + * parameter MEMC_CMD_RTN2IDLE is set +*/ +#undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL +#undef DDRC_MSTR_GEARDOWN_MODE_SHIFT +#undef DDRC_MSTR_GEARDOWN_MODE_MASK +#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_GEARDOWN_MODE_SHIFT 11 +#define DDRC_MSTR_GEARDOWN_MODE_MASK 0x00000800U + +/* +* If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin + * g, all command signals (except chip select) are held for 2 clocks on the + * SDRAM bus. Chip select is asserted on the second cycle of the command N + * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti + * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i + * s set Note: 2T timing is not supported in DDR4 geardown mode. +*/ +#undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL +#undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT +#undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK +#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 10 +#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK 0x00000400U + +/* +* When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci + * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full + * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer + * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is + * disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl + * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported + * , and this bit must be set to '0' +*/ +#undef DDRC_MSTR_BURSTCHOP_DEFVAL +#undef DDRC_MSTR_BURSTCHOP_SHIFT +#undef DDRC_MSTR_BURSTCHOP_MASK +#define DDRC_MSTR_BURSTCHOP_DEFVAL 0x03040001 +#define DDRC_MSTR_BURSTCHOP_SHIFT 9 +#define DDRC_MSTR_BURSTCHOP_MASK 0x00000200U + +/* +* Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d + * evice in use Present only in designs configured to support LPDDR4. +*/ +#undef DDRC_MSTR_LPDDR4_DEFVAL +#undef DDRC_MSTR_LPDDR4_SHIFT +#undef DDRC_MSTR_LPDDR4_MASK +#define DDRC_MSTR_LPDDR4_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR4_SHIFT 5 +#define DDRC_MSTR_LPDDR4_MASK 0x00000020U + +/* +* Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device + * in use Present only in designs configured to support DDR4. +*/ +#undef DDRC_MSTR_DDR4_DEFVAL +#undef DDRC_MSTR_DDR4_SHIFT +#undef DDRC_MSTR_DDR4_MASK +#define DDRC_MSTR_DDR4_DEFVAL 0x03040001 +#define DDRC_MSTR_DDR4_SHIFT 4 +#define DDRC_MSTR_DDR4_MASK 0x00000010U + +/* +* Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d + * evice in use Present only in designs configured to support LPDDR3. +*/ +#undef DDRC_MSTR_LPDDR3_DEFVAL +#undef DDRC_MSTR_LPDDR3_SHIFT +#undef DDRC_MSTR_LPDDR3_MASK +#define DDRC_MSTR_LPDDR3_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR3_SHIFT 3 +#define DDRC_MSTR_LPDDR3_MASK 0x00000008U + +/* +* Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d + * evice in use Present only in designs configured to support LPDDR2. +*/ +#undef DDRC_MSTR_LPDDR2_DEFVAL +#undef DDRC_MSTR_LPDDR2_SHIFT +#undef DDRC_MSTR_LPDDR2_MASK +#define DDRC_MSTR_LPDDR2_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR2_SHIFT 2 +#define DDRC_MSTR_LPDDR2_MASK 0x00000004U + +/* +* Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de + * vice in use Only present in designs that support DDR3. +*/ +#undef DDRC_MSTR_DDR3_DEFVAL +#undef DDRC_MSTR_DDR3_SHIFT +#undef DDRC_MSTR_DDR3_MASK +#define DDRC_MSTR_DDR3_DEFVAL 0x03040001 +#define DDRC_MSTR_DDR3_SHIFT 0 +#define DDRC_MSTR_DDR3_MASK 0x00000001U + +/* +* Setting this register bit to 1 triggers a mode register read or write op + * eration. When the MR operation is complete, the uMCTL2 automatically cle + * ars this bit. The other register fields of this register must be written + * in a separate APB transaction, before setting this mr_wr bit. It is rec + * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper + * ating modes. +*/ +#undef DDRC_MRCTRL0_MR_WR_DEFVAL +#undef DDRC_MRCTRL0_MR_WR_SHIFT +#undef DDRC_MRCTRL0_MR_WR_MASK +#define DDRC_MRCTRL0_MR_WR_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_WR_SHIFT 31 +#define DDRC_MRCTRL0_MR_WR_MASK 0x80000000U + +/* +* Address of the mode register that is to be written to. - 0000 - MR0 - 00 + * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR + * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data + * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als + * o used for writing to control words of RDIMMs. In that case, it correspo + * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[ + * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a + * s the bit[2:0] must be set to an appropriate value which is considered b + * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R + * DIMMs. +*/ +#undef DDRC_MRCTRL0_MR_ADDR_DEFVAL +#undef DDRC_MRCTRL0_MR_ADDR_SHIFT +#undef DDRC_MRCTRL0_MR_ADDR_MASK +#define DDRC_MRCTRL0_MR_ADDR_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_ADDR_SHIFT 12 +#define DDRC_MRCTRL0_MR_ADDR_MASK 0x0000F000U + +/* +* Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire + * d to access all ranks, so all bits should be set to 1. However, for mult + * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess + * ary to access ranks individually. Examples (assume uMCTL2 is configured + * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x + * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran + * ks 0, 1, 2 and 3 +*/ +#undef DDRC_MRCTRL0_MR_RANK_DEFVAL +#undef DDRC_MRCTRL0_MR_RANK_SHIFT +#undef DDRC_MRCTRL0_MR_RANK_MASK +#define DDRC_MRCTRL0_MR_RANK_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_RANK_SHIFT 4 +#define DDRC_MRCTRL0_MR_RANK_MASK 0x00000030U + +/* +* Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b + * efore automatic SDRAM initialization routine or not. For DDR4, this bit + * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init + * ialization. For LPDDR4, this bit can be used to program additional mode + * registers before automatic SDRAM initialization if necessary. Note: This + * must be cleared to 0 after completing Software operation. Otherwise, SD + * RAM initialization routine will not re-start. - 0 - Software interventio + * n is not allowed - 1 - Software intervention is allowed +*/ +#undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL +#undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT +#undef DDRC_MRCTRL0_SW_INIT_INT_MASK +#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT 3 +#define DDRC_MRCTRL0_SW_INIT_INT_MASK 0x00000008U + +/* +* Indicates whether the mode register operation is MRS in PDA mode or not + * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode +*/ +#undef DDRC_MRCTRL0_PDA_EN_DEFVAL +#undef DDRC_MRCTRL0_PDA_EN_SHIFT +#undef DDRC_MRCTRL0_PDA_EN_MASK +#define DDRC_MRCTRL0_PDA_EN_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_PDA_EN_SHIFT 2 +#define DDRC_MRCTRL0_PDA_EN_MASK 0x00000004U + +/* +* Indicates whether the mode register operation is MRS or WR/RD for MPR (o + * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR +*/ +#undef DDRC_MRCTRL0_MPR_EN_DEFVAL +#undef DDRC_MRCTRL0_MPR_EN_SHIFT +#undef DDRC_MRCTRL0_MPR_EN_MASK +#define DDRC_MRCTRL0_MPR_EN_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MPR_EN_SHIFT 1 +#define DDRC_MRCTRL0_MPR_EN_MASK 0x00000002U + +/* +* Indicates whether the mode register operation is read or write. Only use + * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read +*/ +#undef DDRC_MRCTRL0_MR_TYPE_DEFVAL +#undef DDRC_MRCTRL0_MR_TYPE_SHIFT +#undef DDRC_MRCTRL0_MR_TYPE_MASK +#define DDRC_MRCTRL0_MR_TYPE_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_TYPE_SHIFT 0 +#define DDRC_MRCTRL0_MR_TYPE_MASK 0x00000001U + +/* +* Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us + * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d + * esigns configured to support LPDDR4. The required number of cycles for d + * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p + * eriod, and rounding up the next integer. +*/ +#undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL +#undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT +#undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK +#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 8 +#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK 0x00000300U + +/* +* Derate byte Present only in designs configured to support LPDDR2/LPDDR3/ + * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma + * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. +*/ +#undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL +#undef DDRC_DERATEEN_DERATE_BYTE_SHIFT +#undef DDRC_DERATEEN_DERATE_BYTE_MASK +#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_BYTE_SHIFT 4 +#define DDRC_DERATEEN_DERATE_BYTE_MASK 0x000000F0U + +/* +* Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl + * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all + * LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ + * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8 + * 75 ns is less than a core_ddrc_core_clk period or not. +*/ +#undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL +#undef DDRC_DERATEEN_DERATE_VALUE_SHIFT +#undef DDRC_DERATEEN_DERATE_VALUE_MASK +#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1 +#define DDRC_DERATEEN_DERATE_VALUE_MASK 0x00000002U + +/* +* Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin + * g parameter derating is enabled using MR4 read value. Present only in de + * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set + * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. +*/ +#undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL +#undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT +#undef DDRC_DERATEEN_DERATE_ENABLE_MASK +#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0 +#define DDRC_DERATEEN_DERATE_ENABLE_MASK 0x00000001U + +/* +* Interval between two MR4 reads, used to derate the timing parameters. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r + * egister must not be set to zero +*/ +#undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL +#undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT +#undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK +#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL +#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0 +#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFU + +/* +* Self refresh state is an intermediate state to enter to Self refresh pow + * er down state or exit Self refresh power down state for LPDDR4. This reg + * ister controls transition from the Self refresh state. - 1 - Prohibit tr + * ansition from Self refresh state - 0 - Allow transition from Self refres + * h state +*/ +#undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL +#undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT +#undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK +#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 0x00000000 +#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 6 +#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK 0x00000040U + +/* +* A value of 1 to this register causes system to move to Self Refresh stat + * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa + * re Entry to Self Refresh - 0 - Software Exit from Self Refresh +*/ +#undef DDRC_PWRCTL_SELFREF_SW_DEFVAL +#undef DDRC_PWRCTL_SELFREF_SW_SHIFT +#undef DDRC_PWRCTL_SELFREF_SW_MASK +#define DDRC_PWRCTL_SELFREF_SW_DEFVAL 0x00000000 +#define DDRC_PWRCTL_SELFREF_SW_SHIFT 5 +#define DDRC_PWRCTL_SELFREF_SW_MASK 0x00000020U + +/* +* When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode + * when the transaction store is empty. This register must be reset to '0' + * to bring uMCTL2 out of maximum power saving mode. Present only in desig + * ns configured to support DDR4. For non-DDR4, this register should not be + * set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if + * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r + * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PWRCTL_MPSM_EN_DEFVAL +#undef DDRC_PWRCTL_MPSM_EN_SHIFT +#undef DDRC_PWRCTL_MPSM_EN_MASK +#define DDRC_PWRCTL_MPSM_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_MPSM_EN_SHIFT 4 +#define DDRC_PWRCTL_MPSM_EN_MASK 0x00000010U + +/* +* Enable the assertion of dfi_dram_clk_disable whenever a clock is not req + * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. + * Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only + * be asserted in Self Refresh. In DDR4, can be asserted in following: - i + * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca + * n be asserted in following: - in Self Refresh - in Power Down - in Deep + * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse + * rted in following: - in Self Refresh Power Down - in Power Down - during + * Normal operation (Clock Stop) +*/ +#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL +#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT +#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 0x00000000 +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3 +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x00000008U + +/* +* When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the + * transaction store is empty. This register must be reset to '0' to bring + * uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM + * initialization on deep power-down exit. Present only in designs configu + * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD + * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL +#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT +#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 2 +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 0x00000004U + +/* +* If true then the uMCTL2 goes into power-down after a programmable number + * of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_ + * x32). This register bit may be re-programmed during the course of normal + * operation. +*/ +#undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL +#undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT +#undef DDRC_PWRCTL_POWERDOWN_EN_MASK +#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT 1 +#define DDRC_PWRCTL_POWERDOWN_EN_MASK 0x00000002U + +/* +* If true then the uMCTL2 puts the SDRAM into Self Refresh after a program + * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG. + * selfref_to_x32)'. This register bit may be re-programmed during the cour + * se of normal operation. +*/ +#undef DDRC_PWRCTL_SELFREF_EN_DEFVAL +#undef DDRC_PWRCTL_SELFREF_EN_SHIFT +#undef DDRC_PWRCTL_SELFREF_EN_MASK +#define DDRC_PWRCTL_SELFREF_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_SELFREF_EN_SHIFT 0 +#define DDRC_PWRCTL_SELFREF_EN_MASK 0x00000001U + +/* +* After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_ + * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL +#undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT +#undef DDRC_PWRTMG_SELFREF_TO_X32_MASK +#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 0x00402010 +#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 16 +#define DDRC_PWRTMG_SELFREF_TO_X32_MASK 0x00FF0000U + +/* +* Minimum deep power-down time. For mDDR, value from the JEDEC specificati + * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL + * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE + * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i + * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + * ONLY. +*/ +#undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL +#undef DDRC_PWRTMG_T_DPD_X4096_SHIFT +#undef DDRC_PWRTMG_T_DPD_X4096_MASK +#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL 0x00402010 +#define DDRC_PWRTMG_T_DPD_X4096_SHIFT 8 +#define DDRC_PWRTMG_T_DPD_X4096_MASK 0x0000FF00U + +/* +* After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_ + * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL +#undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT +#undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK +#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 0x00402010 +#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 0 +#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 0x0000001FU + +/* +* Threshold value in number of clock cycles before the critical refresh or + * page timer expires. A critical refresh is to be issued before this thre + * shold is reached. It is recommended that this not be changed from the de + * fault value, currently shown as 0x2. It must always be less than interna + * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u + * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i + * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n + * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo + * cks. +*/ +#undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL +#undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT +#undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK +#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 20 +#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 0x00F00000U + +/* +* If the refresh timer (tRFCnom, also known as tREFI) has expired at least + * once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then + * a speculative refresh may be performed. A speculative refresh is a refr + * esh performed at a time when refresh would be useful, but before it is a + * bsolutely required. When the SDRAM bus is idle for a period of time dete + * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired + * at least once since the last refresh, then a speculative refresh is per + * formed. Speculative refreshes continues successively until there are no + * refreshes pending or until new reads or writes are issued to the uMCTL2. + * FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL +#undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT +#undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK +#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 12 +#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 0x0001F000U + +/* +* The programmed value + 1 is the number of refresh timeouts that is allow + * ed to accumulate before traffic is blocked and the refreshes are forced + * to execute. Closing pages to perform a refresh is a one-time penalty tha + * t must be paid for each group of refreshes. Therefore, performing refres + * hes in a burst reduces the per-refresh penalty of these page closings. H + * igher numbers for RFSHCTL.refresh_burst slightly increases utilization; + * lower numbers decreases the worst-case latency associated with refreshes + * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh + * For information on burst refresh feature refer to section 3.9 of DDR2 J + * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe + * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF + * I cycles using the burst refresh feature. In DDR4 mode, according to Fin + * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre + * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda + * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens + * ure that tRFCmax is not violated due to a PHY-initiated update occurring + * shortly before a refresh burst was due. In this situation, the refresh + * burst will be delayed until the PHY-initiated update is complete. +*/ +#undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL +#undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT +#undef DDRC_RFSHCTL0_REFRESH_BURST_MASK +#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 4 +#define DDRC_RFSHCTL0_REFRESH_BURST_MASK 0x000001F0U + +/* +* - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + * traffic to flow to other banks. Per bank refresh is not supported by all + * LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4 +*/ +#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL +#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT +#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 2 +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 0x00000004U + +/* +* Refresh timer start for rank 1 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL 0x00000000 +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT 16 +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK 0x0FFF0000U + +/* +* Refresh timer start for rank 0 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL 0x00000000 +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT 0 +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK 0x00000FFFU + +/* +* Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix + * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11 + * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No + * te: The on-the-fly modes is not supported in this version of the uMCTL2. + * Note: This must be set up while the Controller is in reset or while the + * Controller is in self-refresh mode. Changing this during normal operati + * on is not allowed. Making this a dynamic register will be supported in f + * uture version of the uMCTL2. +*/ +#undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL +#undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT +#undef DDRC_RFSHCTL3_REFRESH_MODE_MASK +#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 4 +#define DDRC_RFSHCTL3_REFRESH_MODE_MASK 0x00000070U + +/* +* Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + * the refresh register(s) have been updated. The value is automatically up + * dated when exiting reset, so it does not need to be toggled initially. +*/ +#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL +#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT +#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1 +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 0x00000002U + +/* +* When '1', disable auto-refresh generated by the uMCTL2. When auto-refres + * h is disabled, the SoC core must generate refreshes using the registers + * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a + * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1 + * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 + * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d + * isable auto-refresh is not supported, and this bit must be set to '0'. T + * his register field is changeable on the fly. +*/ +#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL +#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT +#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 0 +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 0x00000001U + +/* +* tREFI: Average time interval between refreshes per rank (Specification: + * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, + * LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre + * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE + * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + * register should be set to tREFIpb For configurations with MEMC_FREQ_RAT + * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val + * ue is different depending on the refresh mode. The user should program t + * he appropriate value from the spec based on the value programmed in the + * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea + * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th + * an 0x1. Unit: Multiples of 32 clocks. +*/ +#undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL +#undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT +#undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK +#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16 +#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 0x0FFF0000U + +/* +* Used only when LPDDR3 memory type is connected. Should only be changed w + * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r + * equired by some LPDDR3 devices which comply with earlier versions of the + * LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 + * - tREFBW parameter used +*/ +#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL +#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT +#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 15 +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 0x00008000U + +/* +* tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F + * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t + * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro + * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using + * all-bank refreshes, the tRFCmin value in the above equations is equal to + * tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq + * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above + * equations is different depending on the refresh mode (fixed 1X,2X,4X) an + * d the device density. The user should program the appropriate value from + * the spec based on the 'refresh_mode' and the device density that is use + * d. Unit: Clocks. +*/ +#undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL +#undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT +#undef DDRC_RFSHTMG_T_RFC_MIN_MASK +#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT 0 +#define DDRC_RFSHTMG_T_RFC_MIN_MASK 0x000003FFU + +/* +* Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U + * SE_RMW is defined +*/ +#undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL +#undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT +#undef DDRC_ECCCFG0_DIS_SCRUB_MASK +#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 0x00000000 +#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT 4 +#define DDRC_ECCCFG0_DIS_SCRUB_MASK 0x00000010U + +/* +* ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov + * er 1 beat - all other settings are reserved for future use +*/ +#undef DDRC_ECCCFG0_ECC_MODE_DEFVAL +#undef DDRC_ECCCFG0_ECC_MODE_SHIFT +#undef DDRC_ECCCFG0_ECC_MODE_MASK +#define DDRC_ECCCFG0_ECC_MODE_DEFVAL 0x00000000 +#define DDRC_ECCCFG0_ECC_MODE_SHIFT 0 +#define DDRC_ECCCFG0_ECC_MODE_MASK 0x00000007U + +/* +* Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da + * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat + * a_poison_en=1 +*/ +#undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL +#undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT +#undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK +#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 0x00000000 +#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 1 +#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK 0x00000002U + +/* +* Enable ECC data poisoning - introduces ECC errors on writes to address s + * pecified by the ECCPOISONADDR0/1 registers +*/ +#undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL +#undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT +#undef DDRC_ECCCFG1_DATA_POISON_EN_MASK +#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 0x00000000 +#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 0 +#define DDRC_ECCCFG1_DATA_POISON_EN_MASK 0x00000001U + +/* +* The maximum number of DFI PHY clock cycles allowed from the assertion of + * the dfi_rddata_en signal to the assertion of each of the corresponding + * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing + * parameter tphy_rdlat. Refer to PHY specification for correct value. This + * value it only used for detecting read data timeout when DDR4 retry is e + * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: + * - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r + * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 + * : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d + * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ + * rdlat < 'd114 Unit: DFI Clocks +*/ +#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL +#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT +#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 24 +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 0x3F000000U + +/* +* After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa + * re has an option to read the mode registers in the DRAM before the hardw + * are begins the retry process - 1: Wait for software to read/write the mo + * de registers before hardware begins the retry. After software is done wi + * th its operations, it will clear the alert interrupt register bit - 0: H + * ardware can begin the retry right away after the dfi_alert_n pulse goes + * away. The value on this register is valid only when retry is enabled (PA + * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t + * he software doesn't clear the interrupt register after handling the pari + * ty/CRC error, then the hardware will not begin the retry process and the + * system will hang. In the case of Parity/CRC error, there are two possib + * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten + * t parity' mode register bit is NOT set: the commands sent during retry a + * nd normal operation are executed without parity checking. The value in t + * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent + * parity' mode register bit is SET: Parity checking is done for commands s + * ent during retry and normal operation. If multiple errors occur before M + * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don' + * t care'. +*/ +#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL +#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT +#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 9 +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 0x00000200U + +/* +* - 1: Enable command retry mechanism in case of C/A Parity or CRC error - + * 0: Disable command retry mechanism when C/A Parity or CRC features are + * enabled. Note that retry functionality is not supported if burst chop is + * enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF + * SHCTL3.dis_auto_refresh = 1) +*/ +#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL +#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT +#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 8 +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 0x00000100U + +/* +* CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no + * t includes DM signal Present only in designs configured to support DDR4. +*/ +#undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL +#undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT +#undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK +#define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 7 +#define DDRC_CRCPARCTL1_CRC_INC_DM_MASK 0x00000080U + +/* +* CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio + * n of CRC The setting of this register should match the CRC mode register + * setting in the DRAM. +*/ +#undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL +#undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT +#undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK +#define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 4 +#define DDRC_CRCPARCTL1_CRC_ENABLE_MASK 0x00000010U + +/* +* C/A Parity enable register - 1: Enable generation of C/A parity and dete + * ction of C/A parity error - 0: Disable generation of C/A parity and disa + * ble detection of C/A parity error If RCD's parity error detection or SDR + * AM's parity detection is enabled, this register should be 1. +*/ +#undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL +#undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT +#undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK +#define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 0 +#define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 0x00000001U + +/* +* Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M + * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT + * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i + * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. +*/ +#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL +#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT +#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 16 +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 0x01FF0000U + +/* +* Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX + * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW + * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille + * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. +*/ +#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL +#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT +#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 8 +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 0x00001F00U + +/* +* Indicates the maximum duration in number of DRAM clock cycles for which + * a command should be held in the Command Retry FIFO before it is popped o + * ut. Every location in the Command Retry FIFO has an associated down coun + * ting timer that will use this register as the start value. The down coun + * ting starts when a command is loaded into the FIFO. The timer counts dow + * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe + * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err + * or occurs before the counter reaches zero. The counter is reset to 0, af + * ter all the commands in the FIFO are retried. Recommended(minimum) value + * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten + * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable + * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R + * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be + * in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n + * ) should be considered. Note 3: Use the worst case(longer) value for PHY + * Latencies/Board delay Note 4: The Recommended values are minimum value + * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max + * value can be set to this register is defined below: - MEMC_BURST_LENGTH + * == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 + * Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b + * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod + * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C + * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC= + * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 + * Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full + * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod + * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC + * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF + * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma + * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal + * . +*/ +#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL +#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT +#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 0 +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 0x0000003FU + +/* +* If lower bit is enabled the SDRAM initialization routine is skipped. The + * upper bit decides what state the controller starts up in when reset is + * removed - 00 - SDRAM Intialization routine is run after power-up - 01 - + * SDRAM Intialization routine is skipped after power-up. Controller starts + * up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p + * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ + * ation routine is run after power-up. Note: The only 2'b00 is supported f + * or LPDDR4 in this version of the uMCTL2. +*/ +#undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL +#undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT +#undef DDRC_INIT0_SKIP_DRAM_INIT_MASK +#define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 0x0002004E +#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 30 +#define DDRC_INIT0_SKIP_DRAM_INIT_MASK 0xC0000000U + +/* +* Cycles to wait after driving CKE high to start the SDRAM initialization + * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req + * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD + * R3 typically requires this to be programmed for a delay of 200 us. LPDDR + * 4 typically requires this to be programmed for a delay of 2 us. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi + * ded by 2, and round it up to next integer value. +*/ +#undef DDRC_INIT0_POST_CKE_X1024_DEFVAL +#undef DDRC_INIT0_POST_CKE_X1024_SHIFT +#undef DDRC_INIT0_POST_CKE_X1024_MASK +#define DDRC_INIT0_POST_CKE_X1024_DEFVAL 0x0002004E +#define DDRC_INIT0_POST_CKE_X1024_SHIFT 16 +#define DDRC_INIT0_POST_CKE_X1024_MASK 0x03FF0000U + +/* +* Cycles to wait after reset before driving CKE high to start the SDRAM in + * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi + * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD + * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati + * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by + * 2, and round it up to next integer value. +*/ +#undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL +#undef DDRC_INIT0_PRE_CKE_X1024_SHIFT +#undef DDRC_INIT0_PRE_CKE_X1024_MASK +#define DDRC_INIT0_PRE_CKE_X1024_DEFVAL 0x0002004E +#define DDRC_INIT0_PRE_CKE_X1024_SHIFT 0 +#define DDRC_INIT0_PRE_CKE_X1024_MASK 0x00000FFFU + +/* +* Number of cycles to assert SDRAM reset signal during init sequence. This + * is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo + * r use with a DDR PHY, this should be set to a minimum of 1 +*/ +#undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL +#undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT +#undef DDRC_INIT1_DRAM_RSTN_X1024_MASK +#define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 0x00000000 +#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 16 +#define DDRC_INIT1_DRAM_RSTN_X1024_MASK 0x01FF0000U + +/* +* Cycles to wait after completing the SDRAM initialization sequence before + * starting the dynamic scheduler. Unit: Counts of a global timer that pul + * ses every 32 clock cycles. There is no known specific requirement for th + * is; it may be set to zero. +*/ +#undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL +#undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT +#undef DDRC_INIT1_FINAL_WAIT_X32_MASK +#define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 0x00000000 +#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT 8 +#define DDRC_INIT1_FINAL_WAIT_X32_MASK 0x00007F00U + +/* +* Wait period before driving the OCD complete command to SDRAM. Unit: Coun + * ts of a global timer that pulses every 32 clock cycles. There is no know + * n specific requirement for this; it may be set to zero. +*/ +#undef DDRC_INIT1_PRE_OCD_X32_DEFVAL +#undef DDRC_INIT1_PRE_OCD_X32_SHIFT +#undef DDRC_INIT1_PRE_OCD_X32_MASK +#define DDRC_INIT1_PRE_OCD_X32_DEFVAL 0x00000000 +#define DDRC_INIT1_PRE_OCD_X32_SHIFT 0 +#define DDRC_INIT1_PRE_OCD_X32_MASK 0x0000000FU + +/* +* Idle time after the reset command, tINIT4. Present only in designs confi + * gured to support LPDDR2. Unit: 32 clock cycles. +*/ +#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL +#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT +#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 0x00000D05 +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 8 +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 0x0000FF00U + +/* +* Time to wait after the first CKE high, tINIT2. Present only in designs c + * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t + * ypically requires 5 x tCK delay. +*/ +#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL +#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT +#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 0x00000D05 +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 0 +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 0x0000000FU + +/* +* DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he + * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value + * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP + * DDR3/LPDDR4 - Value to write to MR1 register +*/ +#undef DDRC_INIT3_MR_DEFVAL +#undef DDRC_INIT3_MR_SHIFT +#undef DDRC_INIT3_MR_MASK +#define DDRC_INIT3_MR_DEFVAL 0x00000510 +#define DDRC_INIT3_MR_SHIFT 16 +#define DDRC_INIT3_MR_MASK 0xFFFF0000U + +/* +* DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti + * ng in this register is ignored. The uMCTL2 sets those bits appropriately + * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu + * ation mode training is enabled, this bit is set appropriately by the uMC + * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/ + * LPDDR3/LPDDR4 - Value to write to MR2 register +*/ +#undef DDRC_INIT3_EMR_DEFVAL +#undef DDRC_INIT3_EMR_SHIFT +#undef DDRC_INIT3_EMR_MASK +#define DDRC_INIT3_EMR_DEFVAL 0x00000510 +#define DDRC_INIT3_EMR_SHIFT 0 +#define DDRC_INIT3_EMR_MASK 0x0000FFFFU + +/* +* DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 + * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus + * ed +*/ +#undef DDRC_INIT4_EMR2_DEFVAL +#undef DDRC_INIT4_EMR2_SHIFT +#undef DDRC_INIT4_EMR2_MASK +#define DDRC_INIT4_EMR2_DEFVAL 0x00000000 +#define DDRC_INIT4_EMR2_SHIFT 16 +#define DDRC_INIT4_EMR2_MASK 0xFFFF0000U + +/* +* DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 + * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis + * ter +*/ +#undef DDRC_INIT4_EMR3_DEFVAL +#undef DDRC_INIT4_EMR3_SHIFT +#undef DDRC_INIT4_EMR3_MASK +#define DDRC_INIT4_EMR3_DEFVAL 0x00000000 +#define DDRC_INIT4_EMR3_SHIFT 0 +#define DDRC_INIT4_EMR3_MASK 0x0000FFFFU + +/* +* ZQ initial calibration, tZQINIT. Present only in designs configured to s + * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica + * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir + * es 1 us. +*/ +#undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL +#undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT +#undef DDRC_INIT5_DEV_ZQINIT_X32_MASK +#define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 0x00100004 +#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 16 +#define DDRC_INIT5_DEV_ZQINIT_X32_MASK 0x00FF0000U + +/* +* Maximum duration of the auto initialization, tINIT5. Present only in des + * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir + * es 10 us. +*/ +#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL +#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT +#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 0x00100004 +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 0 +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 0x000003FFU + +/* +* DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs + * only. +*/ +#undef DDRC_INIT6_MR4_DEFVAL +#undef DDRC_INIT6_MR4_SHIFT +#undef DDRC_INIT6_MR4_MASK +#define DDRC_INIT6_MR4_DEFVAL 0x00000000 +#define DDRC_INIT6_MR4_SHIFT 16 +#define DDRC_INIT6_MR4_MASK 0xFFFF0000U + +/* +* DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs + * only. +*/ +#undef DDRC_INIT6_MR5_DEFVAL +#undef DDRC_INIT6_MR5_SHIFT +#undef DDRC_INIT6_MR5_MASK +#define DDRC_INIT6_MR5_DEFVAL 0x00000000 +#define DDRC_INIT6_MR5_SHIFT 0 +#define DDRC_INIT6_MR5_MASK 0x0000FFFFU + +/* +* DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs + * only. +*/ +#undef DDRC_INIT7_MR6_DEFVAL +#undef DDRC_INIT7_MR6_SHIFT +#undef DDRC_INIT7_MR6_MASK +#define DDRC_INIT7_MR6_DEFVAL +#define DDRC_INIT7_MR6_SHIFT 16 +#define DDRC_INIT7_MR6_MASK 0xFFFF0000U + +/* +* Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r + * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp + * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. +*/ +#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL +#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT +#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 5 +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 0x00000020U + +/* +* Enable for BG1 bit of MRS command. BG1 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have BG1 are attached and + * both the CA parity and the Output Inversion are enabled, this must be s + * et to 0, so that the calculation of CA parity will not include BG1 bit. + * Note: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. If address mirroring is enab + * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En + * abled - 0 - Disabled +*/ +#undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL +#undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT +#undef DDRC_DIMMCTL_MRS_BG1_EN_MASK +#define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 4 +#define DDRC_DIMMCTL_MRS_BG1_EN_MASK 0x00000010U + +/* +* Enable for A17 bit of MRS command. A17 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have A17 are attached and + * the Output Inversion are enabled, this must be set to 0, so that the ca + * lculation of CA parity will not include A17 bit. Note: This has no effec + * t on the address of any other memory accesses, or of software-driven mod + * e register accesses. - 1 - Enabled - 0 - Disabled +*/ +#undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL +#undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT +#undef DDRC_DIMMCTL_MRS_A17_EN_MASK +#define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT 3 +#define DDRC_DIMMCTL_MRS_A17_EN_MASK 0x00000008U + +/* +* Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM + * M implements the Output Inversion feature by default, which means that t + * he following address, bank address and bank group bits of B-side DRAMs a + * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en + * sures that, for mode register accesses generated by the uMCTL2 during th + * e automatic initialization routine and enabling of a particular DDR4 fea + * ture, separate A-side and B-side mode register accesses are generated. F + * or B-side mode register accesses, these bits are inverted within the uMC + * TL2 to compensate for this RDIMM inversion. Note: This has no effect on + * the address of any other memory accesses, or of software-driven mode reg + * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - + * Do not implement output inversion for B-side DRAMs. +*/ +#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL +#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT +#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 2 +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 0x00000004U + +/* +* Address Mirroring Enable (for multi-rank UDIMM implementations and multi + * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement + * address mirroring for odd ranks, which means that the following address + * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, + * A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t + * his bit ensures that, for mode register accesses during the automatic in + * itialization routine, these bits are swapped within the uMCTL2 to compen + * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial + * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th + * e automatic MRS access to enable/disable of a particular DDR4 feature. N + * ote: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. This is not supported for mDD + * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 + * output of MRS for the odd ranks is same as BG0 because BG1 is invalid, + * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran + * ks, implement address mirroring for MRS commands to during initializatio + * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp + * lements address mirroring) - 0 - Do not implement address mirroring +*/ +#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL +#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT +#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 1 +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 0x00000002U + +/* +* Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM + * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 + * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of + * software driven MR commands (via MRCTRL0/MRCTRL1), where software is re + * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se + * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma + * nds to even and odd ranks seperately - 0 - Do not stagger accesses +*/ +#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL +#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT +#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 0 +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 0x00000001U + +/* +* Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive writes to differ + * ent ranks. This is used to switch the delays in the PHY to match the ran + * k requirements. This value should consider both PHY requirement and ODT + * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v + * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by + * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas + * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc + * reased by 1. - ODT requirement: The value programmed in this register ta + * kes care of the ODT switch off timing requirement when switching ranks d + * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 + * For configurations with MEMC_FREQ_RATIO=1, program this to the larger o + * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_ + * RATIO=2, program this to the larger value divided by two and round it up + * to the next integer. +*/ +#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL +#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT +#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 0x0000066F +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 8 +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 0x00000F00U + +/* +* Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive reads to differe + * nt ranks. This is used to switch the delays in the PHY to match the rank + * requirements. This value should consider both PHY requirement and ODT r + * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va + * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), + * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only + * ), should be increased by 1. - ODT requirement: The value programmed in + * this register takes care of the ODT switch off timing requirement when s + * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, + * program this to the larger of PHY requirement or ODT requirement. For co + * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di + * vided by two and round it up to the next integer. +*/ +#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL +#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT +#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 0x0000066F +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 4 +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 0x000000F0U + +/* +* Only present for multi-rank configurations. Background: Reads to the sam + * e rank can be performed back-to-back. Reads to different ranks require a + * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is + * to avoid possible data bus contention as well as to give PHY enough tim + * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus + * access on a cycle-by-cycle basis; therefore after a read is scheduled, + * there are few clock cycles (determined by the value on RANKCTL.diff_rank + * _rd_gap register) in which only reads from the same rank are eligible to + * be scheduled. This prevents reads from other ranks from having fair acc + * ess to the data bus. This parameter represents the maximum number of rea + * ds that can be scheduled consecutively to the same rank. After this numb + * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by + * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig + * her numbers increase bandwidth utilization, lower numbers increase fairn + * ess. This feature can be DISABLED by setting this register to 0. When se + * t to 0, the Controller will stay on the same rank as long as commands ar + * e available for it. Minimum programmable value is 0 (feature disabled) a + * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL +#undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT +#undef DDRC_RANKCTL_MAX_RANK_RD_MASK +#define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 0x0000066F +#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT 0 +#define DDRC_RANKCTL_MAX_RANK_RD_MASK 0x0000000FU + +/* +* Minimum time between write and precharge to same bank. Unit: Clocks Spec + * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks + * @400MHz and less for lower frequencies where: - WL = write latency - BL + * = burst length. This must match the value programmed in the BL bit of t + * he mode register to the SDRAM. BST (burst terminate) is not supported at + * present. - tWR = Write recovery time. This comes directly from the SDRA + * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p + * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the + * above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT + * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u + * p to the next integer value. +*/ +#undef DDRC_DRAMTMG0_WR2PRE_DEFVAL +#undef DDRC_DRAMTMG0_WR2PRE_SHIFT +#undef DDRC_DRAMTMG0_WR2PRE_MASK +#define DDRC_DRAMTMG0_WR2PRE_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_WR2PRE_SHIFT 24 +#define DDRC_DRAMTMG0_WR2PRE_MASK 0x7F000000U + +/* +* tFAW Valid only when 8 or more banks(or banks x bank groups) are present + * . In 8-bank design, at most 4 banks must be activated in a rolling windo + * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se + * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + * Unit: Clocks +*/ +#undef DDRC_DRAMTMG0_T_FAW_DEFVAL +#undef DDRC_DRAMTMG0_T_FAW_SHIFT +#undef DDRC_DRAMTMG0_T_FAW_MASK +#define DDRC_DRAMTMG0_T_FAW_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_FAW_SHIFT 16 +#define DDRC_DRAMTMG0_T_FAW_MASK 0x003F0000U + +/* +* tRAS(max): Maximum time between activate and precharge to same bank. Thi + * s is the maximum time that a page can be kept open Minimum value of this + * register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO + * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of + * 1024 clocks. +*/ +#undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL +#undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT +#undef DDRC_DRAMTMG0_T_RAS_MAX_MASK +#define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 8 +#define DDRC_DRAMTMG0_T_RAS_MAX_MASK 0x00007F00U + +/* +* tRAS(min): Minimum time between activate and precharge to the same bank. + * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA + * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T + * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th + * e next integer value. Unit: Clocks +*/ +#undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL +#undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT +#undef DDRC_DRAMTMG0_T_RAS_MIN_MASK +#define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 0 +#define DDRC_DRAMTMG0_T_RAS_MIN_MASK 0x0000003FU + +/* +* tXP: Minimum time after power-down exit to any operation. For DDR3, this + * should be programmed to tXPDLL if slow powerdown exit is selected in MR + * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it + * up to the next integer value. Units: Clocks +*/ +#undef DDRC_DRAMTMG1_T_XP_DEFVAL +#undef DDRC_DRAMTMG1_T_XP_SHIFT +#undef DDRC_DRAMTMG1_T_XP_MASK +#define DDRC_DRAMTMG1_T_XP_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_T_XP_SHIFT 16 +#define DDRC_DRAMTMG1_T_XP_MASK 0x001F0000U + +/* +* tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL + * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi + * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 + * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t + * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) + * - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_ + * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi + * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo + * ve value by 2 and round it up to the next integer value. Unit: Clocks. +*/ +#undef DDRC_DRAMTMG1_RD2PRE_DEFVAL +#undef DDRC_DRAMTMG1_RD2PRE_SHIFT +#undef DDRC_DRAMTMG1_RD2PRE_MASK +#define DDRC_DRAMTMG1_RD2PRE_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_RD2PRE_SHIFT 8 +#define DDRC_DRAMTMG1_RD2PRE_MASK 0x00001F00U + +/* +* tRC: Minimum time between activates to same bank. For configurations wit + * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege + * r value. Unit: Clocks. +*/ +#undef DDRC_DRAMTMG1_T_RC_DEFVAL +#undef DDRC_DRAMTMG1_T_RC_SHIFT +#undef DDRC_DRAMTMG1_T_RC_MASK +#define DDRC_DRAMTMG1_T_RC_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_T_RC_SHIFT 0 +#define DDRC_DRAMTMG1_T_RC_MASK 0x0000007FU + +/* +* Set to WL Time from write command to write data on SDRAM interface. This + * must be set to WL. For mDDR, it should normally be set to 1. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use a valu + * e of WL + 1 to compensate for the extra cycle of latency through the RDI + * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate + * d using the above equation by 2, and round it up to next integer. This r + * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING + * is set), as the DFI read and write latencies defined in DFITMG0 and DFI + * TMG1 are sufficient for those protocols Unit: clocks +*/ +#undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL +#undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT +#undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK +#define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 24 +#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK 0x3F000000U + +/* +* Set to RL Time from read command to read data on SDRAM interface. This m + * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma + * t be necessary to use a value of RL + 1 to compensate for the extra cycl + * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2 + * , divide the value calculated using the above equation by 2, and round i + * t up to next integer. This register field is not required for DDR2 and D + * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie + * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit + * : clocks +*/ +#undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL +#undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT +#undef DDRC_DRAMTMG2_READ_LATENCY_MASK +#define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT 16 +#define DDRC_DRAMTMG2_READ_LATENCY_MASK 0x003F0000U + +/* +* DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L + * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di + * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL + * LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL + * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write + * command. Include time for bus turnaround and all per-bank, per-rank, an + * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b + * urst length. This must match the value programmed in the BL bit of the m + * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL + * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = + * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d + * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should + * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal + * culated using the above equation by 2, and round it up to next integer. +*/ +#undef DDRC_DRAMTMG2_RD2WR_DEFVAL +#undef DDRC_DRAMTMG2_RD2WR_SHIFT +#undef DDRC_DRAMTMG2_RD2WR_MASK +#define DDRC_DRAMTMG2_RD2WR_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_RD2WR_SHIFT 8 +#define DDRC_DRAMTMG2_RD2WR_MASK 0x00003F00U + +/* +* DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu + * m time from write command to read command for same bank group. In others + * , minimum time from write command to read command. Includes time for bus + * turnaround, recovery times, and all per-bank, per-rank, and global cons + * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la + * tency - BL = burst length. This must match the value programmed in the B + * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea + * d command delay for same bank group. This comes directly from the SDRAM + * specification. - tWTR = internal write to read command delay. This comes + * directly from the SDRAM specification. Add one extra cycle for LPDDR2/L + * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid + * e the value calculated using the above equation by 2, and round it up to + * next integer. +*/ +#undef DDRC_DRAMTMG2_WR2RD_DEFVAL +#undef DDRC_DRAMTMG2_WR2RD_SHIFT +#undef DDRC_DRAMTMG2_WR2RD_MASK +#define DDRC_DRAMTMG2_WR2RD_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_WR2RD_SHIFT 0 +#define DDRC_DRAMTMG2_WR2RD_MASK 0x0000003FU + +/* +* Time to wait after a mode register write or read (MRW or MRR). Present o + * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty + * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD + * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist + * er is used for the time from a MRW/MRR to all other commands. For LDPDR3 + * , this register is used for the time from a MRW/MRR to a MRW/MRR. +*/ +#undef DDRC_DRAMTMG3_T_MRW_DEFVAL +#undef DDRC_DRAMTMG3_T_MRW_SHIFT +#undef DDRC_DRAMTMG3_T_MRW_MASK +#define DDRC_DRAMTMG3_T_MRW_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MRW_SHIFT 20 +#define DDRC_DRAMTMG3_T_MRW_MASK 0x3FF00000U + +/* +* tMRD: Cycles to wait after a mode register write or read. Depending on t + * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com + * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim + * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2, + * program this to (tMRD/2) and round it up to the next integer value. If + * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. +*/ +#undef DDRC_DRAMTMG3_T_MRD_DEFVAL +#undef DDRC_DRAMTMG3_T_MRD_SHIFT +#undef DDRC_DRAMTMG3_T_MRD_MASK +#define DDRC_DRAMTMG3_T_MRD_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MRD_SHIFT 12 +#define DDRC_DRAMTMG3_T_MRD_MASK 0x0003F000U + +/* +* tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com + * mand and following non-load mode command. If C/A parity for DDR4 is used + * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or + * tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if + * using RDIMM, depending on the PHY, it may be necessary to use a value of + * tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a + * pplied to mode register writes by the RDIMM chip. +*/ +#undef DDRC_DRAMTMG3_T_MOD_DEFVAL +#undef DDRC_DRAMTMG3_T_MOD_SHIFT +#undef DDRC_DRAMTMG3_T_MOD_MASK +#define DDRC_DRAMTMG3_T_MOD_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MOD_SHIFT 0 +#define DDRC_DRAMTMG3_T_MOD_MASK 0x000003FFU + +/* +* tRCD - tAL: Minimum time from activate to read or write command to same + * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD + * - tAL)/2) and round it up to the next integer value. Minimum value allow + * ed for this register is 1, which implies minimum (tRCD - tAL) value to b + * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. +*/ +#undef DDRC_DRAMTMG4_T_RCD_DEFVAL +#undef DDRC_DRAMTMG4_T_RCD_SHIFT +#undef DDRC_DRAMTMG4_T_RCD_MASK +#define DDRC_DRAMTMG4_T_RCD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RCD_SHIFT 24 +#define DDRC_DRAMTMG4_T_RCD_MASK 0x1F000000U + +/* +* DDR4: tCCD_L: This is the minimum time between two reads or two writes f + * or same bank group. Others: tCCD: This is the minimum time between two r + * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t + * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U + * nit: clocks. +*/ +#undef DDRC_DRAMTMG4_T_CCD_DEFVAL +#undef DDRC_DRAMTMG4_T_CCD_SHIFT +#undef DDRC_DRAMTMG4_T_CCD_MASK +#define DDRC_DRAMTMG4_T_CCD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_CCD_SHIFT 16 +#define DDRC_DRAMTMG4_T_CCD_MASK 0x000F0000U + +/* +* DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f + * or same bank group. Others: tRRD: Minimum time between activates from ba + * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni + * t: Clocks. +*/ +#undef DDRC_DRAMTMG4_T_RRD_DEFVAL +#undef DDRC_DRAMTMG4_T_RRD_SHIFT +#undef DDRC_DRAMTMG4_T_RRD_MASK +#define DDRC_DRAMTMG4_T_RRD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RRD_SHIFT 8 +#define DDRC_DRAMTMG4_T_RRD_MASK 0x00000F00U + +/* +* tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ + * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM + * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t + * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho + * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. +*/ +#undef DDRC_DRAMTMG4_T_RP_DEFVAL +#undef DDRC_DRAMTMG4_T_RP_SHIFT +#undef DDRC_DRAMTMG4_T_RP_MASK +#define DDRC_DRAMTMG4_T_RP_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RP_SHIFT 0 +#define DDRC_DRAMTMG4_T_RP_MASK 0x0000001FU + +/* +* This is the time before Self Refresh Exit that CK is maintained as a val + * id clock before issuing SRX. Specifies the clock stable time before SRX. + * Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK + * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. +*/ +#undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL +#undef DDRC_DRAMTMG5_T_CKSRX_SHIFT +#undef DDRC_DRAMTMG5_T_CKSRX_MASK +#define DDRC_DRAMTMG5_T_CKSRX_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKSRX_SHIFT 24 +#define DDRC_DRAMTMG5_T_CKSRX_MASK 0x0F000000U + +/* +* This is the time after Self Refresh Down Entry that CK is maintained as + * a valid clock. Specifies the clock disable delay after SRE. Recommended + * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 + * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations + * with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw + * o and round it up to next integer. +*/ +#undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL +#undef DDRC_DRAMTMG5_T_CKSRE_SHIFT +#undef DDRC_DRAMTMG5_T_CKSRE_MASK +#define DDRC_DRAMTMG5_T_CKSRE_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKSRE_SHIFT 16 +#define DDRC_DRAMTMG5_T_CKSRE_MASK 0x000F0000U + +/* +* Minimum CKE low width for Self refresh or Self refresh power down entry + * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF + * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: + * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ + * _RATIO=2, program this to recommended value divided by two and round it + * up to next integer. +*/ +#undef DDRC_DRAMTMG5_T_CKESR_DEFVAL +#undef DDRC_DRAMTMG5_T_CKESR_SHIFT +#undef DDRC_DRAMTMG5_T_CKESR_MASK +#define DDRC_DRAMTMG5_T_CKESR_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKESR_SHIFT 8 +#define DDRC_DRAMTMG5_T_CKESR_MASK 0x00003F00U + +/* +* Minimum number of cycles of CKE HIGH/LOW during power-down and self refr + * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP + * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/ + * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration + * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and + * round it up to the next integer value. Unit: Clocks. +*/ +#undef DDRC_DRAMTMG5_T_CKE_DEFVAL +#undef DDRC_DRAMTMG5_T_CKE_SHIFT +#undef DDRC_DRAMTMG5_T_CKE_MASK +#define DDRC_DRAMTMG5_T_CKE_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKE_SHIFT 0 +#define DDRC_DRAMTMG5_T_CKE_MASK 0x0000001FU + +/* +* This is the time after Deep Power Down Entry that CK is maintained as a + * valid clock. Specifies the clock disable delay after DPDE. Recommended s + * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. This is only present for designs supporting mDDR + * or LPDDR2/LPDDR3 devices. +*/ +#undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL +#undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT +#undef DDRC_DRAMTMG6_T_CKDPDE_MASK +#define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT 24 +#define DDRC_DRAMTMG6_T_CKDPDE_MASK 0x0F000000U + +/* +* This is the time before Deep Power Down Exit that CK is maintained as a + * valid clock before issuing DPDX. Specifies the clock stable time before + * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config + * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid + * ed by two and round it up to next integer. This is only present for desi + * gns supporting mDDR or LPDDR2 devices. +*/ +#undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL +#undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT +#undef DDRC_DRAMTMG6_T_CKDPDX_MASK +#define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT 16 +#define DDRC_DRAMTMG6_T_CKDPDX_MASK 0x000F0000U + +/* +* This is the time before Clock Stop Exit that CK is maintained as a valid + * clock before issuing Clock Stop Exit. Specifies the clock stable time b + * efore next command after Clock Stop Exit. Recommended settings: - mDDR: + * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio + * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by + * two and round it up to next integer. This is only present for designs su + * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ +#undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL +#undef DDRC_DRAMTMG6_T_CKCSX_SHIFT +#undef DDRC_DRAMTMG6_T_CKCSX_MASK +#define DDRC_DRAMTMG6_T_CKCSX_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKCSX_SHIFT 0 +#define DDRC_DRAMTMG6_T_CKCSX_MASK 0x0000000FU + +/* +* This is the time after Power Down Entry that CK is maintained as a valid + * clock. Specifies the clock disable delay after PDE. Recommended setting + * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration + * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t + * wo and round it up to next integer. This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ +#undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL +#undef DDRC_DRAMTMG7_T_CKPDE_SHIFT +#undef DDRC_DRAMTMG7_T_CKPDE_MASK +#define DDRC_DRAMTMG7_T_CKPDE_DEFVAL 0x00000202 +#define DDRC_DRAMTMG7_T_CKPDE_SHIFT 8 +#define DDRC_DRAMTMG7_T_CKPDE_MASK 0x00000F00U + +/* +* This is the time before Power Down Exit that CK is maintained as a valid + * clock before issuing PDX. Specifies the clock stable time before PDX. R + * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c + * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value + * divided by two and round it up to next integer. This is only present for + * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ +#undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL +#undef DDRC_DRAMTMG7_T_CKPDX_SHIFT +#undef DDRC_DRAMTMG7_T_CKPDX_MASK +#define DDRC_DRAMTMG7_T_CKPDX_DEFVAL 0x00000202 +#define DDRC_DRAMTMG7_T_CKPDX_SHIFT 0 +#define DDRC_DRAMTMG7_T_CKPDX_MASK 0x0000000FU + +/* +* tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and + * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this + * to the above value divided by 2 and round up to next integer value. Unit + * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com + * mands. Note: Ensure this is less than or equal to t_xs_x32. +*/ +#undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL +#undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT +#undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK +#define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 24 +#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 0x7F000000U + +/* +* tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S + * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th + * is to the above value divided by 2 and round up to next integer value. U + * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to + * t_xs_x32. +*/ +#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL +#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT +#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 16 +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 0x007F0000U + +/* +* tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config + * urations with MEMC_FREQ_RATIO=2, program this to the above value divided + * by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. +*/ +#undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL +#undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT +#undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK +#define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 8 +#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 0x00007F00U + +/* +* tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi + * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide + * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. +*/ +#undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL +#undef DDRC_DRAMTMG8_T_XS_X32_SHIFT +#undef DDRC_DRAMTMG8_T_XS_X32_MASK +#define DDRC_DRAMTMG8_T_XS_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_X32_SHIFT 0 +#define DDRC_DRAMTMG8_T_XS_X32_MASK 0x0000007FU + +/* +* DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o + * nly with MEMC_FREQ_RATIO=2 +*/ +#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL +#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT +#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 30 +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 0x40000000U + +/* +* tCCD_S: This is the minimum time between two reads or two writes for dif + * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m + * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2 + * , program this to (tCCD_S/2) and round it up to the next integer value. + * Present only in designs configured to support DDR4. Unit: clocks. +*/ +#undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL +#undef DDRC_DRAMTMG9_T_CCD_S_SHIFT +#undef DDRC_DRAMTMG9_T_CCD_S_MASK +#define DDRC_DRAMTMG9_T_CCD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_T_CCD_S_SHIFT 16 +#define DDRC_DRAMTMG9_T_CCD_S_MASK 0x00070000U + +/* +* tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif + * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th + * is to (tRRD_S/2) and round it up to the next integer value. Present only + * in designs configured to support DDR4. Unit: Clocks. +*/ +#undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL +#undef DDRC_DRAMTMG9_T_RRD_S_SHIFT +#undef DDRC_DRAMTMG9_T_RRD_S_MASK +#define DDRC_DRAMTMG9_T_RRD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_T_RRD_S_SHIFT 8 +#define DDRC_DRAMTMG9_T_RRD_S_MASK 0x00000F00U + +/* +* CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command + * for different bank group. Includes time for bus turnaround, recovery ti + * mes, and all per-bank, per-rank, and global constraints. Present only in + * designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr + * ite latency - PL = Parity latency - BL = burst length. This must match t + * he value programmed in the BL bit of the mode register to the SDRAM - tW + * TR_S = internal write to read command delay for different bank group. Th + * is comes directly from the SDRAM specification. For configurations with + * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation + * by 2, and round it up to next integer. +*/ +#undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL +#undef DDRC_DRAMTMG9_WR2RD_S_SHIFT +#undef DDRC_DRAMTMG9_WR2RD_S_MASK +#define DDRC_DRAMTMG9_WR2RD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_WR2RD_S_SHIFT 0 +#define DDRC_DRAMTMG9_WR2RD_S_MASK 0x0000003FU + +/* +* tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL + * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2 + * ) and round it up to the next integer value. Present only in designs con + * figured to support DDR4. Unit: Multiples of 32 clocks. +*/ +#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL +#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT +#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 24 +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 0x7F000000U + +/* +* tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For + * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2 + * )+1. Present only in designs configured to support DDR4. Unit: clocks. +*/ +#undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL +#undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT +#undef DDRC_DRAMTMG11_T_MPX_LH_MASK +#define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT 16 +#define DDRC_DRAMTMG11_T_MPX_LH_MASK 0x001F0000U + +/* +* tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_ + * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int + * eger value. Present only in designs configured to support DDR4. Unit: Cl + * ocks. +*/ +#undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL +#undef DDRC_DRAMTMG11_T_MPX_S_SHIFT +#undef DDRC_DRAMTMG11_T_MPX_S_MASK +#define DDRC_DRAMTMG11_T_MPX_S_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_MPX_S_SHIFT 8 +#define DDRC_DRAMTMG11_T_MPX_S_MASK 0x00000300U + +/* +* tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i + * n designs configured to support DDR4. Unit: Clocks. For configurations w + * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat + * ion by 2, and round it up to next integer. +*/ +#undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL +#undef DDRC_DRAMTMG11_T_CKMPE_SHIFT +#undef DDRC_DRAMTMG11_T_CKMPE_MASK +#define DDRC_DRAMTMG11_T_CKMPE_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_CKMPE_SHIFT 0 +#define DDRC_DRAMTMG11_T_CKMPE_MASK 0x0000001FU + +/* +* tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg + * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr + * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu + * e. +*/ +#undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL +#undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT +#undef DDRC_DRAMTMG12_T_CMDCKE_MASK +#define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT 16 +#define DDRC_DRAMTMG12_T_CMDCKE_MASK 0x00030000U + +/* +* tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat + * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u + * p to next integer value. +*/ +#undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL +#undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT +#undef DDRC_DRAMTMG12_T_CKEHCMD_MASK +#define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 8 +#define DDRC_DRAMTMG12_T_CKEHCMD_MASK 0x00000F00U + +/* +* tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2) + * and round it up to next integer value. +*/ +#undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL +#undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT +#undef DDRC_DRAMTMG12_T_MRD_PDA_MASK +#define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 0 +#define DDRC_DRAMTMG12_T_MRD_PDA_MASK 0x0000001FU + +/* +* - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg + * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration + * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati + * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre + * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ +#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL +#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT +#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 31 +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 0x80000000U + +/* +* - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres + * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 + * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio + * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i + * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present + * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ +#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL +#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT +#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 30 +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 0x40000000U + +/* +* - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC + * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co + * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share + * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR + * 3/LPDDR4 devices. +*/ +#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL +#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT +#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 29 +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 0x20000000U + +/* +* - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. + * Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com + * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4 + * mode. This is only present for designs supporting DDR4 devices. +*/ +#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL +#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT +#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 28 +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 0x10000000U + +/* +* tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe + * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St + * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO + * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int + * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th + * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t + * o the next integer value. Unit: Clock cycles. This is only present for d + * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ +#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL +#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT +#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 16 +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 0x07FF0000U + +/* +* tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of + * NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command + * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t + * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy + * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP + * DDR3/LPDDR4 devices. +*/ +#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL +#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT +#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 0 +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 0x000003FFU + +/* +* tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati + * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_ + * RATIO=2, program this to tZQReset/2 and round it up to the next integer + * value. Unit: Clock cycles. This is only present for designs supporting L + * PDDR2/LPDDR3/LPDDR4 devices. +*/ +#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL +#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT +#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 0x02000100 +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 20 +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 0x3FF00000U + +/* +* Average interval to wait between automatically issuing ZQCS (ZQ calibrat + * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR + * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles + * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 + * /LPDDR4 devices. +*/ +#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL +#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT +#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 0x02000100 +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 0 +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 0x000FFFFFU + +/* +* Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. +*/ +#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL +#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT +#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 24 +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 0x1F000000U + +/* +* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. +*/ +#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL +#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT +#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 23 +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 0x00800000U + +/* +* Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks +*/ +#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL +#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT +#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 16 +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 0x003F0000U + +/* +* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. +*/ +#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL +#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT +#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 15 +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 0x00008000U + +/* +* Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks +*/ +#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL +#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT +#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 8 +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 0x00003F00U + +/* +* Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. +*/ +#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL +#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT +#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 0 +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 0x0000003FU + +/* +* Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated command is driven. This field is used + * for CAL mode, should be set to '0' or the value which matches the CAL mo + * de register setting in the DRAM. If the PHY can add the latency for CAL + * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 +*/ +#undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL +#undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT +#undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK +#define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 28 +#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 0xF0000000U + +/* +* Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated dfi_parity_in signal is driven. +*/ +#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL +#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT +#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 24 +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 0x03000000U + +/* +* Specifies the number of DFI clocks between when the dfi_wrdata_en signal + * is asserted and when the corresponding write data transfer is completed + * on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d + * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set + * to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI + * 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va + * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_ + * RATIO=2, divide PHY's value by 2 and round up to next integer. If using + * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks +*/ +#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL +#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT +#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 16 +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 0x001F0000U + +/* +* Specifies the number of DFI clock cycles from the assertion of the dfi_d + * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev + * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock + * and the memory clock are not phase aligned, this timing parameter should + * be rounded up to the next integer value. +*/ +#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL +#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT +#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 8 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 0x00000F00U + +/* +* Specifies the number of DFI clock cycles from the de-assertion of the df + * i_dram_clk_disable signal on the DFI until the first valid rising edge o + * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the + * DFI clock and the memory clock are not phase aligned, this timing param + * eter should be rounded up to the next integer value. +*/ +#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL +#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT +#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 0 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 0x0000000FU + +/* +* Setting for DFI's tlp_resp time. Same value is used for both Power Down, + * Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s + * pecification onwards, recommends using a fixed value of 7 always. +*/ +#undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL +#undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT +#undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK +#define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 24 +#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 0x0F000000U + +/* +* Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente + * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 + * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5 + * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - + * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553 + * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T + * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices + * . +*/ +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 20 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 0x00F00000U + +/* +* Enables DFI Low Power interface handshaking during Deep Power Down Entry + * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3 devices. +*/ +#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL +#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT +#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 16 +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 0x00010000U + +/* +* Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered + * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc + * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 + * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 + * - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c + * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited +*/ +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 12 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 0x0000F000U + +/* +* Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex + * it. - 0 - Disabled - 1 - Enabled +*/ +#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL +#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT +#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 8 +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 0x00000100U + +/* +* Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle + * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy + * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - + * 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc + * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited +*/ +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT +#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 4 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 0x000000F0U + +/* +* Enables DFI Low Power interface handshaking during Power Down Entry/Exit + * . - 0 - Disabled - 1 - Enabled +*/ +#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL +#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT +#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 0 +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 0x00000001U + +/* +* Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is + * entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 + * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x + * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl + * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - + * 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi + * ted This is only present for designs supporting DDR4 devices. +*/ +#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL +#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT +#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 0x00000000 +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 4 +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 0x000000F0U + +/* +* Enables DFI Low Power interface handshaking during Maximum Power Saving + * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d + * esigns supporting DDR4 devices. +*/ +#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL +#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT +#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 0x00000000 +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 0 +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 0x00000001U + +/* +* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc + * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. +*/ +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT 31 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK 0x80000000U + +/* +* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * following a self-refresh exit. The core must issue the dfi_ctrlupd_req + * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct + * rlupd_req after exiting self-refresh. +*/ +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT 30 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK 0x40000000U + +/* +* Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si + * gnal can assert. Lowest value to assign to this variable is 0x40. Unit: + * Clocks +*/ +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT 16 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK 0x03FF0000U + +/* +* Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si + * gnal must be asserted. The uMCTL2 expects the PHY to respond within this + * time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup + * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this + * variable is 0x3. Unit: Clocks +*/ +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT 0 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK 0x000003FFU + +/* +* This is the minimum amount of time between uMCTL2 initiated DFI update r + * equests (which is executed whenever the uMCTL2 is idle). Set this number + * higher to reduce the frequency of update requests, which can have a sma + * ll impact on the latency of the first read request when the uMCTL2 is id + * le. Unit: 1024 clocks +*/ +#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL +#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT +#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 0x00000000 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 16 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 0x00FF0000U + +/* +* This is the maximum amount of time between uMCTL2 initiated DFI update r + * equests. This timer resets with each update request; when the timer expi + * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd + * _ackx is received. PHY can use this idle time to recalibrate the delay l + * ines to the DLLs. The DFI controller update is also used to reset PHY FI + * FO pointers in case of data capture errors. Updates are required to main + * tain calibration over PVT, but frequent updates may impact performance. + * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must + * be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl + * ocks +*/ +#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL +#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT +#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 0x00000000 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 0 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 0x000000FFU + +/* +* Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal + * s are active low - 1: Signals are active high +*/ +#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL +#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT +#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 0x00000001 +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 2 +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 0x00000004U + +/* +* DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. + * - 1 - PHY implements DBI functionality. Present only in designs configu + * red to support DDR4 and LPDDR4. +*/ +#undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL +#undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT +#undef DDRC_DFIMISC_PHY_DBI_MODE_MASK +#define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 0x00000001 +#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 1 +#define DDRC_DFIMISC_PHY_DBI_MODE_MASK 0x00000002U + +/* +* PHY initialization complete enable signal. When asserted the dfi_init_co + * mplete signal can be used to trigger SDRAM initialisation +*/ +#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL +#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT +#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 0x00000001 +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 0 +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 0x00000001U + +/* +* >Number of clocks between when a read command is sent on the DFI control + * interface and when the associated dfi_rddata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe + * cification for correct value. +*/ +#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL +#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT +#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 0x00000202 +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 8 +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 0x00003F00U + +/* +* Number of clocks between when a write command is sent on the DFI control + * interface and when the associated dfi_wrdata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe + * cification for correct value. +*/ +#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL +#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT +#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 0x00000202 +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 0 +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 0x0000003FU + +/* +* Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D + * BI is enabled. This signal must be set the same value as DRAM's mode reg + * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b + * e set to 0. - LPDDR4: MR3[6] +*/ +#undef DDRC_DBICTL_RD_DBI_EN_DEFVAL +#undef DDRC_DBICTL_RD_DBI_EN_SHIFT +#undef DDRC_DBICTL_RD_DBI_EN_MASK +#define DDRC_DBICTL_RD_DBI_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_RD_DBI_EN_SHIFT 2 +#define DDRC_DBICTL_RD_DBI_EN_MASK 0x00000004U + +/* +* Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ + * e DBI is enabled. This signal must be set the same value as DRAM's mode + * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus + * t be set to 0. - LPDDR4: MR3[7] +*/ +#undef DDRC_DBICTL_WR_DBI_EN_DEFVAL +#undef DDRC_DBICTL_WR_DBI_EN_SHIFT +#undef DDRC_DBICTL_WR_DBI_EN_MASK +#define DDRC_DBICTL_WR_DBI_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_WR_DBI_EN_SHIFT 1 +#define DDRC_DBICTL_WR_DBI_EN_MASK 0x00000002U + +/* +* DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi + * s signal must be set the same logical value as DRAM's mode register. - D + * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th + * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13 + * [5] which is opposite polarity from this signal +*/ +#undef DDRC_DBICTL_DM_EN_DEFVAL +#undef DDRC_DBICTL_DM_EN_SHIFT +#undef DDRC_DBICTL_DM_EN_MASK +#define DDRC_DBICTL_DM_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_DM_EN_SHIFT 0 +#define DDRC_DBICTL_DM_EN_MASK 0x00000001U + +/* +* Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t + * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, r + * ank address bit 0 is set to 0. +*/ +#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL +#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT +#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 0 +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 0x0000001FU + +/* +* Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t + * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, ba + * nk address bit 2 is set to 0. +*/ +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 16 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 0x001F0000U + +/* +* Selects the HIF address bits used as bank address bit 1. Valid Range: 0 + * to 30 Internal Base: 3 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. +*/ +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 8 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 0x00001F00U + +/* +* Selects the HIF address bits used as bank address bit 0. Valid Range: 0 + * to 30 Internal Base: 2 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. +*/ +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT +#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 0 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 0x0000001FU + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base + * : 5 The selected HIF address bit is determined by adding the internal ba + * se to the value of this field. If set to 15, this column address bit is + * set to 0. +*/ +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 24 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 0x0F000000U + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: + * 4 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 16 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 0x000F0000U + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1 + * 6, it is required to program this to 0, hence register does not exist in + * this case. +*/ +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 8 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 0x00000F00U + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 + * or 16, it is required to program this to 0. +*/ +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT +#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 0 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 0x0000000FU + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: + * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/ + * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + * HIF address bit is determined by adding the internal base to the value o + * f this field. If set to 15, this column address bit is set to 0. Note: P + * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo + * r indicating auto-precharge, and hence no source address bit can be mapp + * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit + * for auto-precharge in the CA bus and hence column bit 10 is used. +*/ +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 24 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 0x0F000000U + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 + * to 7, and 15 Internal Base: 8 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi + * cation, column address bit 10 is reserved for indicating auto-precharge, + * and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA + * bus and hence column bit 10 is used. +*/ +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 16 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 0x000F0000U + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: + * 7 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 8 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 0x00000F00U + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: + * 6 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT +#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 0 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 0x0000000FU + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m + * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un + * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, + * and 15 Internal Base: 11 The selected HIF address bit is determined by + * adding the internal base to the value of this field. If set to 15, this + * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio + * n, column address bit 10 is reserved for indicating auto-precharge, and + * hence no source address bit can be mapped to column address bit 10. In L + * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus + * and hence column bit 10 is used. +*/ +#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL +#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT +#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 0x00000000 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 8 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 0x00000F00U + +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the + * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) + * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied + * to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + * address bit is determined by adding the internal base to the value of t + * his field. If set to 15, this column address bit is set to 0. Note: Per + * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i + * ndicating auto-precharge, and hence no source address bit can be mapped + * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + * auto-precharge in the CA bus and hence column bit 10 is used. +*/ +#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL +#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT +#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 0x00000000 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 0 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 0x0000000FU + +/* +* Selects the HIF address bit used as row address bit 11. Valid Range: 0 t + * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 11 is set to 0. +*/ +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 24 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 0x0F000000U + +/* +* Selects the HIF address bits used as row address bits 2 to 10. Valid Ran + * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row + * address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro + * w address bit 10) The selected HIF address bit for each of the row addre + * ss bits is determined by adding the internal base to the value of this f + * ield. When value 15 is used the values of row address bits 2 to 10 are d + * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. +*/ +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 16 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 0x000F0000U + +/* +* Selects the HIF address bits used as row address bit 1. Valid Range: 0 t + * o 11 Internal Base: 7 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. +*/ +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 8 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 0x00000F00U + +/* +* Selects the HIF address bits used as row address bit 0. Valid Range: 0 t + * o 11 Internal Base: 6 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. +*/ +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT +#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 0 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 0x0000000FU + +/* +* Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 + * - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]= + * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. + * All addresses are valid Present only in designs configured to support L + * PDDR3. +*/ +#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL +#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT +#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 31 +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 0x80000000U + +/* +* Selects the HIF address bit used as row address bit 15. Valid Range: 0 t + * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 15 is set to 0. +*/ +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 24 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 0x0F000000U + +/* +* Selects the HIF address bit used as row address bit 14. Valid Range: 0 t + * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 14 is set to 0. +*/ +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 16 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 0x000F0000U + +/* +* Selects the HIF address bit used as row address bit 13. Valid Range: 0 t + * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 13 is set to 0. +*/ +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 8 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 0x00000F00U + +/* +* Selects the HIF address bit used as row address bit 12. Valid Range: 0 t + * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 12 is set to 0. +*/ +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT +#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 0 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 0x0000000FU + +/* +* Selects the HIF address bit used as row address bit 17. Valid Range: 0 t + * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 17 is set to 0. +*/ +#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL +#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT +#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 0x00000000 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 8 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 0x00000F00U + +/* +* Selects the HIF address bit used as row address bit 16. Valid Range: 0 t + * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 16 is set to 0. +*/ +#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL +#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT +#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 0x00000000 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 0 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 0x0000000FU + +/* +* Selects the HIF address bits used as bank group address bit 1. Valid Ran + * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea + * ch of the bank group address bits is determined by adding the internal b + * ase to the value of this field. If set to 31, bank group address bit 1 i + * s set to 0. +*/ +#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL +#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT +#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 8 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 0x00001F00U + +/* +* Selects the HIF address bits used as bank group address bit 0. Valid Ran + * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th + * e bank group address bits is determined by adding the internal base to t + * he value of this field. +*/ +#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL +#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT +#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 0 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 0x0000001FU + +/* +* Selects the HIF address bits used as row address bit 5. Valid Range: 0 t + * o 11 Internal Base: 11 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 24 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 0x0F000000U + +/* +* Selects the HIF address bits used as row address bit 4. Valid Range: 0 t + * o 11 Internal Base: 10 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 16 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 0x000F0000U + +/* +* Selects the HIF address bits used as row address bit 3. Valid Range: 0 t + * o 11 Internal Base: 9 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. +*/ +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 8 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 0x00000F00U + +/* +* Selects the HIF address bits used as row address bit 2. Valid Range: 0 t + * o 11 Internal Base: 8 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. +*/ +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT +#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 0 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 0x0000000FU + +/* +* Selects the HIF address bits used as row address bit 9. Valid Range: 0 t + * o 11 Internal Base: 15 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 24 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 0x0F000000U + +/* +* Selects the HIF address bits used as row address bit 8. Valid Range: 0 t + * o 11 Internal Base: 14 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 16 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 0x000F0000U + +/* +* Selects the HIF address bits used as row address bit 7. Valid Range: 0 t + * o 11 Internal Base: 13 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 8 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 0x00000F00U + +/* +* Selects the HIF address bits used as row address bit 6. Valid Range: 0 t + * o 11 Internal Base: 12 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT +#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 0 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 0x0000000FU + +/* +* Selects the HIF address bits used as row address bit 10. Valid Range: 0 + * to 11 Internal Base: 16 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of + * this field. This register field is used only when ADDRMAP5.addrmap_row_b + * 2_10 is set to value 15. +*/ +#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL +#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT +#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 0 +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 0x0000000FU + +/* +* Cycles to hold ODT for a write command. The minimum supported value is 2 + * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800 + * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D + * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR + * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 ( + * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) +*/ +#undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL +#undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT +#undef DDRC_ODTCFG_WR_ODT_HOLD_MASK +#define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 0x04000400 +#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 24 +#define DDRC_ODTCFG_WR_ODT_HOLD_MASK 0x0F000000U + +/* +* The delay, in clock cycles, from issuing a write command to setting ODT + * values associated with that command. ODT setting must remain constant fo + * r the entire time that DQS is driven by the uMCTL2. Recommended values: + * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + + * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo + * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust + * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) +*/ +#undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL +#undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT +#undef DDRC_ODTCFG_WR_ODT_DELAY_MASK +#define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 0x04000400 +#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 16 +#define DDRC_ODTCFG_WR_ODT_DELAY_MASK 0x001F0000U + +/* +* Cycles to hold ODT for a read command. The minimum supported value is 2. + * Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - + * BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 + * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p + * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + + * RU(tODTon(max)/tCK) +*/ +#undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL +#undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT +#undef DDRC_ODTCFG_RD_ODT_HOLD_MASK +#define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 0x04000400 +#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 8 +#define DDRC_ODTCFG_RD_ODT_HOLD_MASK 0x00000F00U + +/* +* The delay, in clock cycles, from issuing a read command to setting ODT v + * alues associated with that command. ODT setting must remain constant for + * the entire time that DQS is driven by the uMCTL2. Recommended values: D + * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL + * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C + * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat + * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK + * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre + * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su + * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R + * U(tODTon(max)/tCK) +*/ +#undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL +#undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT +#undef DDRC_ODTCFG_RD_ODT_DELAY_MASK +#define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 0x04000400 +#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 2 +#define DDRC_ODTCFG_RD_ODT_DELAY_MASK 0x0000007CU + +/* +* Indicates which remote ODTs must be turned on during a read from rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. Present only in configurations that have 2 or more + * ranks +*/ +#undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL +#undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT +#undef DDRC_ODTMAP_RANK1_RD_ODT_MASK +#define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 12 +#define DDRC_ODTMAP_RANK1_RD_ODT_MASK 0x00003000U + +/* +* Indicates which remote ODTs must be turned on during a write to rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. Present only in configurations that have 2 or more r + * anks +*/ +#undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL +#undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT +#undef DDRC_ODTMAP_RANK1_WR_ODT_MASK +#define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 8 +#define DDRC_ODTMAP_RANK1_WR_ODT_MASK 0x00000300U + +/* +* Indicates which remote ODTs must be turned on during a read from rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. +*/ +#undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL +#undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT +#undef DDRC_ODTMAP_RANK0_RD_ODT_MASK +#define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 4 +#define DDRC_ODTMAP_RANK0_RD_ODT_MASK 0x00000030U + +/* +* Indicates which remote ODTs must be turned on during a write to rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. +*/ +#undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL +#undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT +#undef DDRC_ODTMAP_RANK0_WR_ODT_MASK +#define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 0 +#define DDRC_ODTMAP_RANK0_WR_ODT_MASK 0x00000003U + +/* +* When the preferred transaction store is empty for these many clock cycle + * s, switch to the alternate transaction store if it is non-empty. The rea + * d transaction store (both high and low priority) is the default preferre + * d transaction store and the write transaction store is the alternative s + * tore. When prefer write over read is set this is reversed. 0x0 is a lega + * l value for this register. When set to 0x0, the transaction store switch + * ing will happen immediately when the switching conditions become true. F + * OR PERFORMANCE ONLY +*/ +#undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL +#undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT +#undef DDRC_SCHED_RDWR_IDLE_GAP_MASK +#define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 0x00002005 +#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 24 +#define DDRC_SCHED_RDWR_IDLE_GAP_MASK 0x7F000000U + +/* +* UNUSED +*/ +#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL +#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT +#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 0x00002005 +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 16 +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 0x00FF0000U + +/* +* Number of entries in the low priority transaction store is this value + + * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent + * ries available for the high priority transaction store. Setting this to + * maximum value allocates all entries to low priority transaction store. S + * etting this to 0 allocates 1 entry to low priority transaction store and + * the rest to high priority transaction store. Note: In ECC configuration + * s, the numbers of write and low priority read credits issued is one less + * than in the non-ECC case. One entry each is reserved in the write and l + * ow-priority read CAMs for storing the RMW requests arising out of single + * bit error correction RMW operation. +*/ +#undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL +#undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT +#undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK +#define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 0x00002005 +#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 8 +#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK 0x00003F00U + +/* +* If true, bank is kept open only while there are page hit transactions av + * ailable in the CAM to that bank. The last read or write command in the C + * AM with a bank and page hit will be executed with auto-precharge if SCHE + * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos + * e_timer is set to 0, explicit precharge (and not auto-precharge) may be + * issued in some cases where there is a mode switch between Write and Read + * or between LPR and HPR. The Read and Write commands that are executed a + * s part of the ECC scrub requests are also executed without auto-precharg + * e. If false, the bank remains open until there is a need to close it (to + * open a different page, or for page timeout or refresh timeout) - also k + * nown as open page policy. The open page policy can be overridden by sett + * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + * The pageclose feature provids a midway between Open and Close page polic + * ies. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_SCHED_PAGECLOSE_DEFVAL +#undef DDRC_SCHED_PAGECLOSE_SHIFT +#undef DDRC_SCHED_PAGECLOSE_MASK +#define DDRC_SCHED_PAGECLOSE_DEFVAL 0x00002005 +#define DDRC_SCHED_PAGECLOSE_SHIFT 2 +#define DDRC_SCHED_PAGECLOSE_MASK 0x00000004U + +/* +* If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. +*/ +#undef DDRC_SCHED_PREFER_WRITE_DEFVAL +#undef DDRC_SCHED_PREFER_WRITE_SHIFT +#undef DDRC_SCHED_PREFER_WRITE_MASK +#define DDRC_SCHED_PREFER_WRITE_DEFVAL 0x00002005 +#define DDRC_SCHED_PREFER_WRITE_SHIFT 1 +#define DDRC_SCHED_PREFER_WRITE_MASK 0x00000002U + +/* +* Active low signal. When asserted ('0'), all incoming transactions are fo + * rced to low priority. This implies that all High Priority Read (HPR) and + * Variable Priority Read commands (VPR) will be treated as Low Priority R + * ead (LPR) commands. On the write side, all Variable Priority Write (VPW) + * commands will be treated as Normal Priority Write (NPW) commands. Forci + * ng the incoming transactions to low priority implicitly turns off Bypass + * path for read commands. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL +#undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT +#undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK +#define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 0x00002005 +#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 0 +#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK 0x00000001U + +/* +* Number of transactions that are serviced once the LPR queue goes critica + * l is the smaller of: - (a) This number - (b) Number of transactions avai + * lable. Unit: Transaction. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL +#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT +#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 0x0F00007F +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 24 +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 0xFF000000U + +/* +* Number of clocks that the LPR queue can be starved before it goes critic + * al. The minimum valid functional value for this register is 0x1. Program + * ming it to 0x0 will disable the starvation functionality; during normal + * operation, this function should not be disabled as it will cause excessi + * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL +#undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT +#undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK +#define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 0x0F00007F +#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 0 +#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 0x0000FFFFU + +/* +* Number of transactions that are serviced once the WR queue goes critical + * is the smaller of: - (a) This number - (b) Number of transactions avail + * able. Unit: Transaction. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL +#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT +#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 0x0F00007F +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 24 +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 0xFF000000U + +/* +* Number of clocks that the WR queue can be starved before it goes critica + * l. The minimum valid functional value for this register is 0x1. Programm + * ing it to 0x0 will disable the starvation functionality; during normal o + * peration, this function should not be disabled as it will cause excessiv + * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL +#undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT +#undef DDRC_PERFWR1_W_MAX_STARVE_MASK +#define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 0x0F00007F +#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT 0 +#define DDRC_PERFWR1_W_MAX_STARVE_MASK 0x0000FFFFU + +/* +* DQ nibble map for DQ bits [12-15] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT 24 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [8-11] Present only in designs configured to s + * upport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT 16 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [4-7] Present only in designs configured to su + * pport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT 8 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [0-3] Present only in designs configured to su + * pport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT 0 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [28-31] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT 24 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [24-27] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT 16 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [20-23] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT 8 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [16-19] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT 0 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [44-47] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT 24 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [40-43] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT 16 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [36-39] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT 8 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [32-35] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT 0 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [60-63] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT 24 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [56-59] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT 16 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [52-55] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT 8 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [48-51] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT 0 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK 0x000000FFU + +/* +* DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf + * igured to support DDR4. +*/ +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL 0x00000000 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT 8 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK 0x0000FF00U + +/* +* DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf + * igured to support DDR4. +*/ +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL 0x00000000 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT 0 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK 0x000000FFU + +/* +* All even ranks have the same DQ mapping controled by DQMAP0-4 register a + * s rank 0. This register provides DQ swap function for all odd ranks to s + * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b + * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba + * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs + * configured to support DDR4. +*/ +#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL +#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT +#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 0 +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 0x00000001U + +/* +* When this is set to '0', auto-precharge is disabled for the flushed comm + * and in a collision case. Collision cases are write followed by read to s + * ame address, read followed by write to same address, or write followed b + * y write to same address with DBG0.dis_wc bit = 1 (where same address com + * parisons exclude the two address bits representing critical word). FOR D + * EBUG ONLY. +*/ +#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL +#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT +#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 0x00000000 +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 4 +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 0x00000010U + +/* +* When 1, disable write combine. FOR DEBUG ONLY +*/ +#undef DDRC_DBG0_DIS_WC_DEFVAL +#undef DDRC_DBG0_DIS_WC_SHIFT +#undef DDRC_DBG0_DIS_WC_MASK +#define DDRC_DBG0_DIS_WC_DEFVAL 0x00000000 +#define DDRC_DBG0_DIS_WC_SHIFT 0 +#define DDRC_DBG0_DIS_WC_MASK 0x00000001U + +/* +* Setting this register bit to 1 allows refresh and ZQCS commands to be tr + * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD. + * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore + * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and + * ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor + * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no + * function, and are ignored by the uMCTL2 logic. This register is static, + * and may only be changed when the DDRC reset signal, core_ddrc_rstn, is + * asserted (0). +*/ +#undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL +#undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT +#undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK +#define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 0x00000000 +#define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 31 +#define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 0x80000000U + +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct + * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit + * is automatically cleared. This operation must only be performed when DF + * IUPD0.dis_auto_ctrlupd=1. +*/ +#undef DDRC_DBGCMD_CTRLUPD_DEFVAL +#undef DDRC_DBGCMD_CTRLUPD_SHIFT +#undef DDRC_DBGCMD_CTRLUPD_MASK +#define DDRC_DBGCMD_CTRLUPD_DEFVAL 0x00000000 +#define DDRC_DBGCMD_CTRLUPD_SHIFT 5 +#define DDRC_DBGCMD_CTRLUPD_MASK 0x00000020U + +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS ( + * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi + * s request is stored in the uMCTL2, the bit is automatically cleared. Thi + * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom + * mended NOT to set this register bit if in Init operating mode. This regi + * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown + * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo + * de. +*/ +#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL +#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT +#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 0x00000000 +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 4 +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 0x00000010U + +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be + * set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. +*/ +#undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL +#undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT +#undef DDRC_DBGCMD_RANK1_REFRESH_MASK +#define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 0x00000000 +#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT 1 +#define DDRC_DBGCMD_RANK1_REFRESH_MASK 0x00000002U + +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be + * set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. +*/ +#undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL +#undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT +#undef DDRC_DBGCMD_RANK0_REFRESH_MASK +#define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 0x00000000 +#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT 0 +#define DDRC_DBGCMD_RANK0_REFRESH_MASK 0x00000001U + +/* +* Enable quasi-dynamic register programming outside reset. Program registe + * r to 0 to enable quasi-dynamic programming. Set back register to 1 once + * programming is done. +*/ +#undef DDRC_SWCTL_SW_DONE_DEFVAL +#undef DDRC_SWCTL_SW_DONE_SHIFT +#undef DDRC_SWCTL_SW_DONE_MASK +#define DDRC_SWCTL_SW_DONE_DEFVAL +#define DDRC_SWCTL_SW_DONE_SHIFT 0 +#define DDRC_SWCTL_SW_DONE_MASK 0x00000001U + +/* +* Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand + * s every AXI burst into multiple HIF commands, using the memory burst len + * gth as a unit. If set to 1, then XPI will use half of the memory burst l + * ength as a unit. This applies to both reads and writes. When MSTR.data_b + * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i + * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d + * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd + * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali + * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT + * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an + * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST + * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs + * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR + * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared + * -AC is enabled +*/ +#undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL +#undef DDRC_PCCFG_BL_EXP_MODE_SHIFT +#undef DDRC_PCCFG_BL_EXP_MODE_MASK +#define DDRC_PCCFG_BL_EXP_MODE_DEFVAL 0x00000000 +#define DDRC_PCCFG_BL_EXP_MODE_SHIFT 8 +#define DDRC_PCCFG_BL_EXP_MODE_MASK 0x00000100U + +/* +* Page match four limit. If set to 1, limits the number of consecutive sam + * e page DDRC transactions that can be granted by the Port Arbiter to four + * when Page Match feature is enabled. If set to 0, there is no limit impo + * sed on number of consecutive same page DDRC transactions. +*/ +#undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL +#undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT +#undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK +#define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 0x00000000 +#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 4 +#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 0x00000010U + +/* +* If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l + * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw + * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_ + * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a + * t DDRC are driven to 1b'0. +*/ +#undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL +#undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT +#undef DDRC_PCCFG_GO2CRITICAL_EN_MASK +#define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 0x00000000 +#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 0 +#define DDRC_PCCFG_GO2CRITICAL_EN_MASK 0x00000001U + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ +#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the read channel of the port. +*/ +#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ +#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 0x000003FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ +#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the write channel of the port. +*/ +#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ +#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 0x000003FFU + +/* +* Enables port n. +*/ +#undef DDRC_PCTRL_0_PORT_EN_DEFVAL +#undef DDRC_PCTRL_0_PORT_EN_SHIFT +#undef DDRC_PCTRL_0_PORT_EN_MASK +#define DDRC_PCTRL_0_PORT_EN_DEFVAL +#define DDRC_PCTRL_0_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_0_PORT_EN_MASK 0x00000001U + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL +#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT +#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 0x0000000FU + +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ +#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL +#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT +#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U + +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ +#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL +#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT +#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ +#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the read channel of the port. +*/ +#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ +#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 0x000003FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ +#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the write channel of the port. +*/ +#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ +#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 0x000003FFU + +/* +* Enables port n. +*/ +#undef DDRC_PCTRL_1_PORT_EN_DEFVAL +#undef DDRC_PCTRL_1_PORT_EN_SHIFT +#undef DDRC_PCTRL_1_PORT_EN_MASK +#define DDRC_PCTRL_1_PORT_EN_DEFVAL +#define DDRC_PCTRL_1_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_1_PORT_EN_MASK 0x00000001U + +/* +* This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. +*/ +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 24 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 0x03000000U + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL +#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT +#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 8 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 0x00000F00U + +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL +#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT +#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 0x0000000FU + +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ +#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL +#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT +#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U + +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ +#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL +#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT +#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ +#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the read channel of the port. +*/ +#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ +#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 0x000003FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ +#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the write channel of the port. +*/ +#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ +#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 0x000003FFU + +/* +* Enables port n. +*/ +#undef DDRC_PCTRL_2_PORT_EN_DEFVAL +#undef DDRC_PCTRL_2_PORT_EN_SHIFT +#undef DDRC_PCTRL_2_PORT_EN_MASK +#define DDRC_PCTRL_2_PORT_EN_DEFVAL +#define DDRC_PCTRL_2_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_2_PORT_EN_MASK 0x00000001U + +/* +* This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. +*/ +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 24 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 0x03000000U + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL +#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT +#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 8 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 0x00000F00U + +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL +#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT +#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 0x0000000FU + +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ +#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL +#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT +#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U + +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ +#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL +#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT +#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ +#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the read channel of the port. +*/ +#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ +#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 0x000003FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ +#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the write channel of the port. +*/ +#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ +#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 0x000003FFU + +/* +* Enables port n. +*/ +#undef DDRC_PCTRL_3_PORT_EN_DEFVAL +#undef DDRC_PCTRL_3_PORT_EN_SHIFT +#undef DDRC_PCTRL_3_PORT_EN_MASK +#define DDRC_PCTRL_3_PORT_EN_DEFVAL +#define DDRC_PCTRL_3_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_3_PORT_EN_MASK 0x00000001U + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL +#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT +#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 0x0000000FU + +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ +#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL +#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT +#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U + +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ +#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL +#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT +#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT +#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 0x0000000FU + +/* +* Specifies the timeout value for write transactions. +*/ +#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL +#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT +#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 0x000007FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ +#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the read channel of the port. +*/ +#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ +#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 0x000003FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ +#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the write channel of the port. +*/ +#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ +#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 0x000003FFU + +/* +* Enables port n. +*/ +#undef DDRC_PCTRL_4_PORT_EN_DEFVAL +#undef DDRC_PCTRL_4_PORT_EN_SHIFT +#undef DDRC_PCTRL_4_PORT_EN_MASK +#define DDRC_PCTRL_4_PORT_EN_DEFVAL +#define DDRC_PCTRL_4_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_4_PORT_EN_MASK 0x00000001U + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL +#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT +#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 0x0000000FU + +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ +#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL +#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT +#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U + +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ +#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL +#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT +#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT +#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 0x0000000FU + +/* +* Specifies the timeout value for write transactions. +*/ +#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL +#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT +#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 0x000007FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ +#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the read channel of the port. +*/ +#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ +#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 0x000003FFU + +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ +#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL +#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT +#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U + +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ +#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL +#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT +#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 0x00002000U + +/* +* If set to 1, enables aging function for the write channel of the port. +*/ +#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL +#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT +#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 0x00001000U + +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ +#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL +#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT +#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 0x000003FFU + +/* +* Enables port n. +*/ +#undef DDRC_PCTRL_5_PORT_EN_DEFVAL +#undef DDRC_PCTRL_5_PORT_EN_SHIFT +#undef DDRC_PCTRL_5_PORT_EN_MASK +#define DDRC_PCTRL_5_PORT_EN_DEFVAL +#define DDRC_PCTRL_5_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_5_PORT_EN_MASK 0x00000001U + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ +#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ +#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL +#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT +#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 0x0000000FU + +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ +#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL +#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT +#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U + +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ +#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL +#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT +#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU + +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 0x00300000U + +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 0x00030000U + +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT +#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 0x0000000FU + +/* +* Specifies the timeout value for write transactions. +*/ +#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL +#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT +#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 0x000007FFU + +/* +* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). +*/ +#undef DDRC_SARBASE0_BASE_ADDR_DEFVAL +#undef DDRC_SARBASE0_BASE_ADDR_SHIFT +#undef DDRC_SARBASE0_BASE_ADDR_MASK +#define DDRC_SARBASE0_BASE_ADDR_DEFVAL +#define DDRC_SARBASE0_BASE_ADDR_SHIFT 0 +#define DDRC_SARBASE0_BASE_ADDR_MASK 0x000001FFU + +/* +* Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. +*/ +#undef DDRC_SARSIZE0_NBLOCKS_DEFVAL +#undef DDRC_SARSIZE0_NBLOCKS_SHIFT +#undef DDRC_SARSIZE0_NBLOCKS_MASK +#define DDRC_SARSIZE0_NBLOCKS_DEFVAL +#define DDRC_SARSIZE0_NBLOCKS_SHIFT 0 +#define DDRC_SARSIZE0_NBLOCKS_MASK 0x000000FFU + +/* +* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). +*/ +#undef DDRC_SARBASE1_BASE_ADDR_DEFVAL +#undef DDRC_SARBASE1_BASE_ADDR_SHIFT +#undef DDRC_SARBASE1_BASE_ADDR_MASK +#define DDRC_SARBASE1_BASE_ADDR_DEFVAL +#define DDRC_SARBASE1_BASE_ADDR_SHIFT 0 +#define DDRC_SARBASE1_BASE_ADDR_MASK 0x000001FFU + +/* +* Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. +*/ +#undef DDRC_SARSIZE1_NBLOCKS_DEFVAL +#undef DDRC_SARSIZE1_NBLOCKS_SHIFT +#undef DDRC_SARSIZE1_NBLOCKS_MASK +#define DDRC_SARSIZE1_NBLOCKS_DEFVAL +#define DDRC_SARSIZE1_NBLOCKS_SHIFT 0 +#define DDRC_SARSIZE1_NBLOCKS_MASK 0x000000FFU + +/* +* Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. +*/ +#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL +#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT +#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 24 +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 0x1F000000U + +/* +* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. +*/ +#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL +#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT +#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 23 +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 0x00800000U + +/* +* Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks +*/ +#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL +#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT +#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 16 +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 0x003F0000U + +/* +* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. +*/ +#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL +#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT +#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 15 +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 0x00008000U + +/* +* Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks +*/ +#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL +#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT +#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 8 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 0x00003F00U + +/* +* Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. +*/ +#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL +#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT +#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 0 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 0x0000003FU + +/* +* DDR block level reset inside of the DDR Sub System +*/ +#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL +#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT +#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK +#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 +#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U + +/* +* APM block level reset inside of the DDR Sub System +*/ +#undef CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL +#undef CRF_APB_RST_DDR_SS_APM_RESET_SHIFT +#undef CRF_APB_RST_DDR_SS_APM_RESET_MASK +#define CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_APM_RESET_SHIFT 2 +#define CRF_APB_RST_DDR_SS_APM_RESET_MASK 0x00000004U + +/* +* Address Copy +*/ +#undef DDR_PHY_PGCR0_ADCP_DEFVAL +#undef DDR_PHY_PGCR0_ADCP_SHIFT +#undef DDR_PHY_PGCR0_ADCP_MASK +#define DDR_PHY_PGCR0_ADCP_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_ADCP_SHIFT 31 +#define DDR_PHY_PGCR0_ADCP_MASK 0x80000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL +#undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT +#undef DDR_PHY_PGCR0_RESERVED_30_27_MASK +#define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 27 +#define DDR_PHY_PGCR0_RESERVED_30_27_MASK 0x78000000U + +/* +* PHY FIFO Reset +*/ +#undef DDR_PHY_PGCR0_PHYFRST_DEFVAL +#undef DDR_PHY_PGCR0_PHYFRST_SHIFT +#undef DDR_PHY_PGCR0_PHYFRST_MASK +#define DDR_PHY_PGCR0_PHYFRST_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_PHYFRST_SHIFT 26 +#define DDR_PHY_PGCR0_PHYFRST_MASK 0x04000000U + +/* +* Oscillator Mode Address/Command Delay Line Select +*/ +#undef DDR_PHY_PGCR0_OSCACDL_DEFVAL +#undef DDR_PHY_PGCR0_OSCACDL_SHIFT +#undef DDR_PHY_PGCR0_OSCACDL_MASK +#define DDR_PHY_PGCR0_OSCACDL_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCACDL_SHIFT 24 +#define DDR_PHY_PGCR0_OSCACDL_MASK 0x03000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL +#undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT +#undef DDR_PHY_PGCR0_RESERVED_23_19_MASK +#define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 19 +#define DDR_PHY_PGCR0_RESERVED_23_19_MASK 0x00F80000U + +/* +* Digital Test Output Select +*/ +#undef DDR_PHY_PGCR0_DTOSEL_DEFVAL +#undef DDR_PHY_PGCR0_DTOSEL_SHIFT +#undef DDR_PHY_PGCR0_DTOSEL_MASK +#define DDR_PHY_PGCR0_DTOSEL_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_DTOSEL_SHIFT 14 +#define DDR_PHY_PGCR0_DTOSEL_MASK 0x0007C000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL +#undef DDR_PHY_PGCR0_RESERVED_13_SHIFT +#undef DDR_PHY_PGCR0_RESERVED_13_MASK +#define DDR_PHY_PGCR0_RESERVED_13_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_13_SHIFT 13 +#define DDR_PHY_PGCR0_RESERVED_13_MASK 0x00002000U + +/* +* Oscillator Mode Division +*/ +#undef DDR_PHY_PGCR0_OSCDIV_DEFVAL +#undef DDR_PHY_PGCR0_OSCDIV_SHIFT +#undef DDR_PHY_PGCR0_OSCDIV_MASK +#define DDR_PHY_PGCR0_OSCDIV_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCDIV_SHIFT 9 +#define DDR_PHY_PGCR0_OSCDIV_MASK 0x00001E00U + +/* +* Oscillator Enable +*/ +#undef DDR_PHY_PGCR0_OSCEN_DEFVAL +#undef DDR_PHY_PGCR0_OSCEN_SHIFT +#undef DDR_PHY_PGCR0_OSCEN_MASK +#define DDR_PHY_PGCR0_OSCEN_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCEN_SHIFT 8 +#define DDR_PHY_PGCR0_OSCEN_MASK 0x00000100U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL +#undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT +#undef DDR_PHY_PGCR0_RESERVED_7_0_MASK +#define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 0 +#define DDR_PHY_PGCR0_RESERVED_7_0_MASK 0x000000FFU + +/* +* Clear Training Status Registers +*/ +#undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL +#undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT +#undef DDR_PHY_PGCR2_CLRTSTAT_MASK +#define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRTSTAT_SHIFT 31 +#define DDR_PHY_PGCR2_CLRTSTAT_MASK 0x80000000U + +/* +* Clear Impedance Calibration +*/ +#undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL +#undef DDR_PHY_PGCR2_CLRZCAL_SHIFT +#undef DDR_PHY_PGCR2_CLRZCAL_MASK +#define DDR_PHY_PGCR2_CLRZCAL_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRZCAL_SHIFT 30 +#define DDR_PHY_PGCR2_CLRZCAL_MASK 0x40000000U + +/* +* Clear Parity Error +*/ +#undef DDR_PHY_PGCR2_CLRPERR_DEFVAL +#undef DDR_PHY_PGCR2_CLRPERR_SHIFT +#undef DDR_PHY_PGCR2_CLRPERR_MASK +#define DDR_PHY_PGCR2_CLRPERR_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRPERR_SHIFT 29 +#define DDR_PHY_PGCR2_CLRPERR_MASK 0x20000000U + +/* +* Initialization Complete Pin Configuration +*/ +#undef DDR_PHY_PGCR2_ICPC_DEFVAL +#undef DDR_PHY_PGCR2_ICPC_SHIFT +#undef DDR_PHY_PGCR2_ICPC_MASK +#define DDR_PHY_PGCR2_ICPC_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_ICPC_SHIFT 28 +#define DDR_PHY_PGCR2_ICPC_MASK 0x10000000U + +/* +* Data Training PUB Mode Exit Timer +*/ +#undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL +#undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT +#undef DDR_PHY_PGCR2_DTPMXTMR_MASK +#define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_DTPMXTMR_SHIFT 20 +#define DDR_PHY_PGCR2_DTPMXTMR_MASK 0x0FF00000U + +/* +* Initialization Bypass +*/ +#undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL +#undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT +#undef DDR_PHY_PGCR2_INITFSMBYP_MASK +#define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_INITFSMBYP_SHIFT 19 +#define DDR_PHY_PGCR2_INITFSMBYP_MASK 0x00080000U + +/* +* PLL FSM Bypass +*/ +#undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL +#undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT +#undef DDR_PHY_PGCR2_PLLFSMBYP_MASK +#define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 18 +#define DDR_PHY_PGCR2_PLLFSMBYP_MASK 0x00040000U + +/* +* Refresh Period +*/ +#undef DDR_PHY_PGCR2_TREFPRD_DEFVAL +#undef DDR_PHY_PGCR2_TREFPRD_SHIFT +#undef DDR_PHY_PGCR2_TREFPRD_MASK +#define DDR_PHY_PGCR2_TREFPRD_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_TREFPRD_SHIFT 0 +#define DDR_PHY_PGCR2_TREFPRD_MASK 0x0003FFFFU + +/* +* CKN Enable +*/ +#undef DDR_PHY_PGCR3_CKNEN_DEFVAL +#undef DDR_PHY_PGCR3_CKNEN_SHIFT +#undef DDR_PHY_PGCR3_CKNEN_MASK +#define DDR_PHY_PGCR3_CKNEN_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CKNEN_SHIFT 24 +#define DDR_PHY_PGCR3_CKNEN_MASK 0xFF000000U + +/* +* CK Enable +*/ +#undef DDR_PHY_PGCR3_CKEN_DEFVAL +#undef DDR_PHY_PGCR3_CKEN_SHIFT +#undef DDR_PHY_PGCR3_CKEN_MASK +#define DDR_PHY_PGCR3_CKEN_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CKEN_SHIFT 16 +#define DDR_PHY_PGCR3_CKEN_MASK 0x00FF0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL +#undef DDR_PHY_PGCR3_RESERVED_15_SHIFT +#undef DDR_PHY_PGCR3_RESERVED_15_MASK +#define DDR_PHY_PGCR3_RESERVED_15_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RESERVED_15_SHIFT 15 +#define DDR_PHY_PGCR3_RESERVED_15_MASK 0x00008000U + +/* +* Enable Clock Gating for AC [0] ctl_rd_clk +*/ +#undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL +#undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT +#undef DDR_PHY_PGCR3_GATEACRDCLK_MASK +#define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 13 +#define DDR_PHY_PGCR3_GATEACRDCLK_MASK 0x00006000U + +/* +* Enable Clock Gating for AC [0] ddr_clk +*/ +#undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL +#undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT +#undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK +#define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 11 +#define DDR_PHY_PGCR3_GATEACDDRCLK_MASK 0x00001800U + +/* +* Enable Clock Gating for AC [0] ctl_clk +*/ +#undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL +#undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT +#undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK +#define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 9 +#define DDR_PHY_PGCR3_GATEACCTLCLK_MASK 0x00000600U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL +#undef DDR_PHY_PGCR3_RESERVED_8_SHIFT +#undef DDR_PHY_PGCR3_RESERVED_8_MASK +#define DDR_PHY_PGCR3_RESERVED_8_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RESERVED_8_SHIFT 8 +#define DDR_PHY_PGCR3_RESERVED_8_MASK 0x00000100U + +/* +* Controls DDL Bypass Modes +*/ +#undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL +#undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT +#undef DDR_PHY_PGCR3_DDLBYPMODE_MASK +#define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6 +#define DDR_PHY_PGCR3_DDLBYPMODE_MASK 0x000000C0U + +/* +* IO Loop-Back Select +*/ +#undef DDR_PHY_PGCR3_IOLB_DEFVAL +#undef DDR_PHY_PGCR3_IOLB_SHIFT +#undef DDR_PHY_PGCR3_IOLB_MASK +#define DDR_PHY_PGCR3_IOLB_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_IOLB_SHIFT 5 +#define DDR_PHY_PGCR3_IOLB_MASK 0x00000020U + +/* +* AC Receive FIFO Read Mode +*/ +#undef DDR_PHY_PGCR3_RDMODE_DEFVAL +#undef DDR_PHY_PGCR3_RDMODE_SHIFT +#undef DDR_PHY_PGCR3_RDMODE_MASK +#define DDR_PHY_PGCR3_RDMODE_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RDMODE_SHIFT 3 +#define DDR_PHY_PGCR3_RDMODE_MASK 0x00000018U + +/* +* Read FIFO Reset Disable +*/ +#undef DDR_PHY_PGCR3_DISRST_DEFVAL +#undef DDR_PHY_PGCR3_DISRST_SHIFT +#undef DDR_PHY_PGCR3_DISRST_MASK +#define DDR_PHY_PGCR3_DISRST_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_DISRST_SHIFT 2 +#define DDR_PHY_PGCR3_DISRST_MASK 0x00000004U + +/* +* Clock Level when Clock Gating +*/ +#undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL +#undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT +#undef DDR_PHY_PGCR3_CLKLEVEL_MASK +#define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CLKLEVEL_SHIFT 0 +#define DDR_PHY_PGCR3_CLKLEVEL_MASK 0x00000003U + +/* +* Frequency B Ratio Term +*/ +#undef DDR_PHY_PGCR5_FRQBT_DEFVAL +#undef DDR_PHY_PGCR5_FRQBT_SHIFT +#undef DDR_PHY_PGCR5_FRQBT_MASK +#define DDR_PHY_PGCR5_FRQBT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_FRQBT_SHIFT 24 +#define DDR_PHY_PGCR5_FRQBT_MASK 0xFF000000U + +/* +* Frequency A Ratio Term +*/ +#undef DDR_PHY_PGCR5_FRQAT_DEFVAL +#undef DDR_PHY_PGCR5_FRQAT_SHIFT +#undef DDR_PHY_PGCR5_FRQAT_MASK +#define DDR_PHY_PGCR5_FRQAT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_FRQAT_SHIFT 16 +#define DDR_PHY_PGCR5_FRQAT_MASK 0x00FF0000U + +/* +* DFI Disconnect Time Period +*/ +#undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL +#undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT +#undef DDR_PHY_PGCR5_DISCNPERIOD_MASK +#define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 8 +#define DDR_PHY_PGCR5_DISCNPERIOD_MASK 0x0000FF00U + +/* +* Receiver bias core side control +*/ +#undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL +#undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT +#undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK +#define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 4 +#define DDR_PHY_PGCR5_VREF_RBCTRL_MASK 0x000000F0U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL +#undef DDR_PHY_PGCR5_RESERVED_3_SHIFT +#undef DDR_PHY_PGCR5_RESERVED_3_MASK +#define DDR_PHY_PGCR5_RESERVED_3_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_RESERVED_3_SHIFT 3 +#define DDR_PHY_PGCR5_RESERVED_3_MASK 0x00000008U + +/* +* Internal VREF generator REFSEL ragne select +*/ +#undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL +#undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT +#undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK +#define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 2 +#define DDR_PHY_PGCR5_DXREFISELRANGE_MASK 0x00000004U + +/* +* DDL Page Read Write select +*/ +#undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL +#undef DDR_PHY_PGCR5_DDLPGACT_SHIFT +#undef DDR_PHY_PGCR5_DDLPGACT_MASK +#define DDR_PHY_PGCR5_DDLPGACT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DDLPGACT_SHIFT 1 +#define DDR_PHY_PGCR5_DDLPGACT_MASK 0x00000002U + +/* +* DDL Page Read Write select +*/ +#undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL +#undef DDR_PHY_PGCR5_DDLPGRW_SHIFT +#undef DDR_PHY_PGCR5_DDLPGRW_MASK +#define DDR_PHY_PGCR5_DDLPGRW_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DDLPGRW_SHIFT 0 +#define DDR_PHY_PGCR5_DDLPGRW_MASK 0x00000001U + +/* +* PLL Power-Down Time +*/ +#undef DDR_PHY_PTR0_TPLLPD_DEFVAL +#undef DDR_PHY_PTR0_TPLLPD_SHIFT +#undef DDR_PHY_PTR0_TPLLPD_MASK +#define DDR_PHY_PTR0_TPLLPD_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPLLPD_SHIFT 21 +#define DDR_PHY_PTR0_TPLLPD_MASK 0xFFE00000U + +/* +* PLL Gear Shift Time +*/ +#undef DDR_PHY_PTR0_TPLLGS_DEFVAL +#undef DDR_PHY_PTR0_TPLLGS_SHIFT +#undef DDR_PHY_PTR0_TPLLGS_MASK +#define DDR_PHY_PTR0_TPLLGS_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPLLGS_SHIFT 6 +#define DDR_PHY_PTR0_TPLLGS_MASK 0x001FFFC0U + +/* +* PHY Reset Time +*/ +#undef DDR_PHY_PTR0_TPHYRST_DEFVAL +#undef DDR_PHY_PTR0_TPHYRST_SHIFT +#undef DDR_PHY_PTR0_TPHYRST_MASK +#define DDR_PHY_PTR0_TPHYRST_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPHYRST_SHIFT 0 +#define DDR_PHY_PTR0_TPHYRST_MASK 0x0000003FU + +/* +* PLL Lock Time +*/ +#undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL +#undef DDR_PHY_PTR1_TPLLLOCK_SHIFT +#undef DDR_PHY_PTR1_TPLLLOCK_MASK +#define DDR_PHY_PTR1_TPLLLOCK_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_TPLLLOCK_SHIFT 16 +#define DDR_PHY_PTR1_TPLLLOCK_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL +#undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT +#undef DDR_PHY_PTR1_RESERVED_15_13_MASK +#define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_RESERVED_15_13_SHIFT 13 +#define DDR_PHY_PTR1_RESERVED_15_13_MASK 0x0000E000U + +/* +* PLL Reset Time +*/ +#undef DDR_PHY_PTR1_TPLLRST_DEFVAL +#undef DDR_PHY_PTR1_TPLLRST_SHIFT +#undef DDR_PHY_PTR1_TPLLRST_MASK +#define DDR_PHY_PTR1_TPLLRST_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_TPLLRST_SHIFT 0 +#define DDR_PHY_PTR1_TPLLRST_MASK 0x00001FFFU + +/* +* PLL Bypass +*/ +#undef DDR_PHY_PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_PLLCR0_PLLBYP_MASK +#define DDR_PHY_PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_PLLCR0_PLLRST_MASK +#define DDR_PHY_PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_PLLCR0_PLLPD_MASK +#define DDR_PHY_PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_PLLCR0_RSTOPM_MASK +#define DDR_PHY_PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_PLLCR0_FRQSEL_MASK +#define DDR_PHY_PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_PLLCR0_RLOCKM_MASK +#define DDR_PHY_PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_PLLCR0_CPPC_SHIFT +#undef DDR_PHY_PLLCR0_CPPC_MASK +#define DDR_PHY_PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_PLLCR0_CPIC_SHIFT +#undef DDR_PHY_PLLCR0_CPIC_MASK +#define DDR_PHY_PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_PLLCR0_GSHIFT_MASK +#define DDR_PHY_PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable +*/ +#undef DDR_PHY_PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_PLLCR0_ATOEN_MASK +#define DDR_PHY_PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_PLLCR0_ATC_DEFVAL +#undef DDR_PHY_PLLCR0_ATC_SHIFT +#undef DDR_PHY_PLLCR0_ATC_MASK +#define DDR_PHY_PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_PLLCR0_DTC_DEFVAL +#undef DDR_PHY_PLLCR0_DTC_SHIFT +#undef DDR_PHY_PLLCR0_DTC_MASK +#define DDR_PHY_PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL +#undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT +#undef DDR_PHY_DSGCR_RESERVED_31_28_MASK +#define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 28 +#define DDR_PHY_DSGCR_RESERVED_31_28_MASK 0xF0000000U + +/* +* When RDBI enabled, this bit is used to select RDBI CL calculation, if it + * is 1b1, calculation will use RDBICL, otherwise use default calculation. +*/ +#undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL +#undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT +#undef DDR_PHY_DSGCR_RDBICLSEL_MASK +#define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RDBICLSEL_SHIFT 27 +#define DDR_PHY_DSGCR_RDBICLSEL_MASK 0x08000000U + +/* +* When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v + * alue. +*/ +#undef DDR_PHY_DSGCR_RDBICL_DEFVAL +#undef DDR_PHY_DSGCR_RDBICL_SHIFT +#undef DDR_PHY_DSGCR_RDBICL_MASK +#define DDR_PHY_DSGCR_RDBICL_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RDBICL_SHIFT 24 +#define DDR_PHY_DSGCR_RDBICL_MASK 0x07000000U + +/* +* PHY Impedance Update Enable +*/ +#undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL +#undef DDR_PHY_DSGCR_PHYZUEN_SHIFT +#undef DDR_PHY_DSGCR_PHYZUEN_MASK +#define DDR_PHY_DSGCR_PHYZUEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PHYZUEN_SHIFT 23 +#define DDR_PHY_DSGCR_PHYZUEN_MASK 0x00800000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL +#undef DDR_PHY_DSGCR_RESERVED_22_SHIFT +#undef DDR_PHY_DSGCR_RESERVED_22_MASK +#define DDR_PHY_DSGCR_RESERVED_22_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_22_SHIFT 22 +#define DDR_PHY_DSGCR_RESERVED_22_MASK 0x00400000U + +/* +* SDRAM Reset Output Enable +*/ +#undef DDR_PHY_DSGCR_RSTOE_DEFVAL +#undef DDR_PHY_DSGCR_RSTOE_SHIFT +#undef DDR_PHY_DSGCR_RSTOE_MASK +#define DDR_PHY_DSGCR_RSTOE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RSTOE_SHIFT 21 +#define DDR_PHY_DSGCR_RSTOE_MASK 0x00200000U + +/* +* Single Data Rate Mode +*/ +#undef DDR_PHY_DSGCR_SDRMODE_DEFVAL +#undef DDR_PHY_DSGCR_SDRMODE_SHIFT +#undef DDR_PHY_DSGCR_SDRMODE_MASK +#define DDR_PHY_DSGCR_SDRMODE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_SDRMODE_SHIFT 19 +#define DDR_PHY_DSGCR_SDRMODE_MASK 0x00180000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL +#undef DDR_PHY_DSGCR_RESERVED_18_SHIFT +#undef DDR_PHY_DSGCR_RESERVED_18_MASK +#define DDR_PHY_DSGCR_RESERVED_18_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_18_SHIFT 18 +#define DDR_PHY_DSGCR_RESERVED_18_MASK 0x00040000U + +/* +* ATO Analog Test Enable +*/ +#undef DDR_PHY_DSGCR_ATOAE_DEFVAL +#undef DDR_PHY_DSGCR_ATOAE_SHIFT +#undef DDR_PHY_DSGCR_ATOAE_MASK +#define DDR_PHY_DSGCR_ATOAE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_ATOAE_SHIFT 17 +#define DDR_PHY_DSGCR_ATOAE_MASK 0x00020000U + +/* +* DTO Output Enable +*/ +#undef DDR_PHY_DSGCR_DTOOE_DEFVAL +#undef DDR_PHY_DSGCR_DTOOE_SHIFT +#undef DDR_PHY_DSGCR_DTOOE_MASK +#define DDR_PHY_DSGCR_DTOOE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOOE_SHIFT 16 +#define DDR_PHY_DSGCR_DTOOE_MASK 0x00010000U + +/* +* DTO I/O Mode +*/ +#undef DDR_PHY_DSGCR_DTOIOM_DEFVAL +#undef DDR_PHY_DSGCR_DTOIOM_SHIFT +#undef DDR_PHY_DSGCR_DTOIOM_MASK +#define DDR_PHY_DSGCR_DTOIOM_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOIOM_SHIFT 15 +#define DDR_PHY_DSGCR_DTOIOM_MASK 0x00008000U + +/* +* DTO Power Down Receiver +*/ +#undef DDR_PHY_DSGCR_DTOPDR_DEFVAL +#undef DDR_PHY_DSGCR_DTOPDR_SHIFT +#undef DDR_PHY_DSGCR_DTOPDR_MASK +#define DDR_PHY_DSGCR_DTOPDR_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOPDR_SHIFT 14 +#define DDR_PHY_DSGCR_DTOPDR_MASK 0x00004000U + +/* +* Reserved. Return zeroes on reads +*/ +#undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL +#undef DDR_PHY_DSGCR_RESERVED_13_SHIFT +#undef DDR_PHY_DSGCR_RESERVED_13_MASK +#define DDR_PHY_DSGCR_RESERVED_13_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_13_SHIFT 13 +#define DDR_PHY_DSGCR_RESERVED_13_MASK 0x00002000U + +/* +* DTO On-Die Termination +*/ +#undef DDR_PHY_DSGCR_DTOODT_DEFVAL +#undef DDR_PHY_DSGCR_DTOODT_SHIFT +#undef DDR_PHY_DSGCR_DTOODT_MASK +#define DDR_PHY_DSGCR_DTOODT_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOODT_SHIFT 12 +#define DDR_PHY_DSGCR_DTOODT_MASK 0x00001000U + +/* +* PHY Update Acknowledge Delay +*/ +#undef DDR_PHY_DSGCR_PUAD_DEFVAL +#undef DDR_PHY_DSGCR_PUAD_SHIFT +#undef DDR_PHY_DSGCR_PUAD_MASK +#define DDR_PHY_DSGCR_PUAD_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PUAD_SHIFT 6 +#define DDR_PHY_DSGCR_PUAD_MASK 0x00000FC0U + +/* +* Controller Update Acknowledge Enable +*/ +#undef DDR_PHY_DSGCR_CUAEN_DEFVAL +#undef DDR_PHY_DSGCR_CUAEN_SHIFT +#undef DDR_PHY_DSGCR_CUAEN_MASK +#define DDR_PHY_DSGCR_CUAEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_CUAEN_SHIFT 5 +#define DDR_PHY_DSGCR_CUAEN_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads +*/ +#undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL +#undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT +#undef DDR_PHY_DSGCR_RESERVED_4_3_MASK +#define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 3 +#define DDR_PHY_DSGCR_RESERVED_4_3_MASK 0x00000018U + +/* +* Controller Impedance Update Enable +*/ +#undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL +#undef DDR_PHY_DSGCR_CTLZUEN_SHIFT +#undef DDR_PHY_DSGCR_CTLZUEN_MASK +#define DDR_PHY_DSGCR_CTLZUEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_CTLZUEN_SHIFT 2 +#define DDR_PHY_DSGCR_CTLZUEN_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads +*/ +#undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL +#undef DDR_PHY_DSGCR_RESERVED_1_SHIFT +#undef DDR_PHY_DSGCR_RESERVED_1_MASK +#define DDR_PHY_DSGCR_RESERVED_1_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_1_SHIFT 1 +#define DDR_PHY_DSGCR_RESERVED_1_MASK 0x00000002U + +/* +* PHY Update Request Enable +*/ +#undef DDR_PHY_DSGCR_PUREN_DEFVAL +#undef DDR_PHY_DSGCR_PUREN_SHIFT +#undef DDR_PHY_DSGCR_PUREN_MASK +#define DDR_PHY_DSGCR_PUREN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PUREN_SHIFT 0 +#define DDR_PHY_DSGCR_PUREN_MASK 0x00000001U + +/* +* General Purpose Register 0 +*/ +#undef DDR_PHY_GPR0_GPR0_DEFVAL +#undef DDR_PHY_GPR0_GPR0_SHIFT +#undef DDR_PHY_GPR0_GPR0_MASK +#define DDR_PHY_GPR0_GPR0_DEFVAL +#define DDR_PHY_GPR0_GPR0_SHIFT 0 +#define DDR_PHY_GPR0_GPR0_MASK 0xFFFFFFFFU + +/* +* General Purpose Register 1 +*/ +#undef DDR_PHY_GPR1_GPR1_DEFVAL +#undef DDR_PHY_GPR1_GPR1_SHIFT +#undef DDR_PHY_GPR1_GPR1_MASK +#define DDR_PHY_GPR1_GPR1_DEFVAL +#define DDR_PHY_GPR1_GPR1_SHIFT 0 +#define DDR_PHY_GPR1_GPR1_MASK 0xFFFFFFFFU + +/* +* DDR4 Gear Down Timing. +*/ +#undef DDR_PHY_DCR_GEARDN_DEFVAL +#undef DDR_PHY_DCR_GEARDN_SHIFT +#undef DDR_PHY_DCR_GEARDN_MASK +#define DDR_PHY_DCR_GEARDN_DEFVAL 0x0000040D +#define DDR_PHY_DCR_GEARDN_SHIFT 31 +#define DDR_PHY_DCR_GEARDN_MASK 0x80000000U + +/* +* Un-used Bank Group +*/ +#undef DDR_PHY_DCR_UBG_DEFVAL +#undef DDR_PHY_DCR_UBG_SHIFT +#undef DDR_PHY_DCR_UBG_MASK +#define DDR_PHY_DCR_UBG_DEFVAL 0x0000040D +#define DDR_PHY_DCR_UBG_SHIFT 30 +#define DDR_PHY_DCR_UBG_MASK 0x40000000U + +/* +* Un-buffered DIMM Address Mirroring +*/ +#undef DDR_PHY_DCR_UDIMM_DEFVAL +#undef DDR_PHY_DCR_UDIMM_SHIFT +#undef DDR_PHY_DCR_UDIMM_MASK +#define DDR_PHY_DCR_UDIMM_DEFVAL 0x0000040D +#define DDR_PHY_DCR_UDIMM_SHIFT 29 +#define DDR_PHY_DCR_UDIMM_MASK 0x20000000U + +/* +* DDR 2T Timing +*/ +#undef DDR_PHY_DCR_DDR2T_DEFVAL +#undef DDR_PHY_DCR_DDR2T_SHIFT +#undef DDR_PHY_DCR_DDR2T_MASK +#define DDR_PHY_DCR_DDR2T_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDR2T_SHIFT 28 +#define DDR_PHY_DCR_DDR2T_MASK 0x10000000U + +/* +* No Simultaneous Rank Access +*/ +#undef DDR_PHY_DCR_NOSRA_DEFVAL +#undef DDR_PHY_DCR_NOSRA_SHIFT +#undef DDR_PHY_DCR_NOSRA_MASK +#define DDR_PHY_DCR_NOSRA_DEFVAL 0x0000040D +#define DDR_PHY_DCR_NOSRA_SHIFT 27 +#define DDR_PHY_DCR_NOSRA_MASK 0x08000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL +#undef DDR_PHY_DCR_RESERVED_26_18_SHIFT +#undef DDR_PHY_DCR_RESERVED_26_18_MASK +#define DDR_PHY_DCR_RESERVED_26_18_DEFVAL 0x0000040D +#define DDR_PHY_DCR_RESERVED_26_18_SHIFT 18 +#define DDR_PHY_DCR_RESERVED_26_18_MASK 0x07FC0000U + +/* +* Byte Mask +*/ +#undef DDR_PHY_DCR_BYTEMASK_DEFVAL +#undef DDR_PHY_DCR_BYTEMASK_SHIFT +#undef DDR_PHY_DCR_BYTEMASK_MASK +#define DDR_PHY_DCR_BYTEMASK_DEFVAL 0x0000040D +#define DDR_PHY_DCR_BYTEMASK_SHIFT 10 +#define DDR_PHY_DCR_BYTEMASK_MASK 0x0003FC00U + +/* +* DDR Type +*/ +#undef DDR_PHY_DCR_DDRTYPE_DEFVAL +#undef DDR_PHY_DCR_DDRTYPE_SHIFT +#undef DDR_PHY_DCR_DDRTYPE_MASK +#define DDR_PHY_DCR_DDRTYPE_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDRTYPE_SHIFT 8 +#define DDR_PHY_DCR_DDRTYPE_MASK 0x00000300U + +/* +* Multi-Purpose Register (MPR) DQ (DDR3 Only) +*/ +#undef DDR_PHY_DCR_MPRDQ_DEFVAL +#undef DDR_PHY_DCR_MPRDQ_SHIFT +#undef DDR_PHY_DCR_MPRDQ_MASK +#define DDR_PHY_DCR_MPRDQ_DEFVAL 0x0000040D +#define DDR_PHY_DCR_MPRDQ_SHIFT 7 +#define DDR_PHY_DCR_MPRDQ_MASK 0x00000080U + +/* +* Primary DQ (DDR3 Only) +*/ +#undef DDR_PHY_DCR_PDQ_DEFVAL +#undef DDR_PHY_DCR_PDQ_SHIFT +#undef DDR_PHY_DCR_PDQ_MASK +#define DDR_PHY_DCR_PDQ_DEFVAL 0x0000040D +#define DDR_PHY_DCR_PDQ_SHIFT 4 +#define DDR_PHY_DCR_PDQ_MASK 0x00000070U + +/* +* DDR 8-Bank +*/ +#undef DDR_PHY_DCR_DDR8BNK_DEFVAL +#undef DDR_PHY_DCR_DDR8BNK_SHIFT +#undef DDR_PHY_DCR_DDR8BNK_MASK +#define DDR_PHY_DCR_DDR8BNK_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDR8BNK_SHIFT 3 +#define DDR_PHY_DCR_DDR8BNK_MASK 0x00000008U + +/* +* DDR Mode +*/ +#undef DDR_PHY_DCR_DDRMD_DEFVAL +#undef DDR_PHY_DCR_DDRMD_SHIFT +#undef DDR_PHY_DCR_DDRMD_MASK +#define DDR_PHY_DCR_DDRMD_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDRMD_SHIFT 0 +#define DDR_PHY_DCR_DDRMD_MASK 0x00000007U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT +#undef DDR_PHY_DTPR0_RESERVED_31_29_MASK +#define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DTPR0_RESERVED_31_29_MASK 0xE0000000U + +/* +* Activate to activate command delay (different banks) +*/ +#undef DDR_PHY_DTPR0_TRRD_DEFVAL +#undef DDR_PHY_DTPR0_TRRD_SHIFT +#undef DDR_PHY_DTPR0_TRRD_MASK +#define DDR_PHY_DTPR0_TRRD_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRRD_SHIFT 24 +#define DDR_PHY_DTPR0_TRRD_MASK 0x1F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL +#undef DDR_PHY_DTPR0_RESERVED_23_SHIFT +#undef DDR_PHY_DTPR0_RESERVED_23_MASK +#define DDR_PHY_DTPR0_RESERVED_23_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_23_SHIFT 23 +#define DDR_PHY_DTPR0_RESERVED_23_MASK 0x00800000U + +/* +* Activate to precharge command delay +*/ +#undef DDR_PHY_DTPR0_TRAS_DEFVAL +#undef DDR_PHY_DTPR0_TRAS_SHIFT +#undef DDR_PHY_DTPR0_TRAS_MASK +#define DDR_PHY_DTPR0_TRAS_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRAS_SHIFT 16 +#define DDR_PHY_DTPR0_TRAS_MASK 0x007F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL +#undef DDR_PHY_DTPR0_RESERVED_15_SHIFT +#undef DDR_PHY_DTPR0_RESERVED_15_MASK +#define DDR_PHY_DTPR0_RESERVED_15_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_15_SHIFT 15 +#define DDR_PHY_DTPR0_RESERVED_15_MASK 0x00008000U + +/* +* Precharge command period +*/ +#undef DDR_PHY_DTPR0_TRP_DEFVAL +#undef DDR_PHY_DTPR0_TRP_SHIFT +#undef DDR_PHY_DTPR0_TRP_MASK +#define DDR_PHY_DTPR0_TRP_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRP_SHIFT 8 +#define DDR_PHY_DTPR0_TRP_MASK 0x00007F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL +#undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT +#undef DDR_PHY_DTPR0_RESERVED_7_5_MASK +#define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR0_RESERVED_7_5_MASK 0x000000E0U + +/* +* Internal read to precharge command delay +*/ +#undef DDR_PHY_DTPR0_TRTP_DEFVAL +#undef DDR_PHY_DTPR0_TRTP_SHIFT +#undef DDR_PHY_DTPR0_TRTP_MASK +#define DDR_PHY_DTPR0_TRTP_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRTP_SHIFT 0 +#define DDR_PHY_DTPR0_TRTP_MASK 0x0000001FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL +#undef DDR_PHY_DTPR1_RESERVED_31_SHIFT +#undef DDR_PHY_DTPR1_RESERVED_31_MASK +#define DDR_PHY_DTPR1_RESERVED_31_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_31_SHIFT 31 +#define DDR_PHY_DTPR1_RESERVED_31_MASK 0x80000000U + +/* +* Minimum delay from when write leveling mode is programmed to the first D + * QS/DQS# rising edge. +*/ +#undef DDR_PHY_DTPR1_TWLMRD_DEFVAL +#undef DDR_PHY_DTPR1_TWLMRD_SHIFT +#undef DDR_PHY_DTPR1_TWLMRD_MASK +#define DDR_PHY_DTPR1_TWLMRD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TWLMRD_SHIFT 24 +#define DDR_PHY_DTPR1_TWLMRD_MASK 0x7F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL +#undef DDR_PHY_DTPR1_RESERVED_23_SHIFT +#undef DDR_PHY_DTPR1_RESERVED_23_MASK +#define DDR_PHY_DTPR1_RESERVED_23_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_23_SHIFT 23 +#define DDR_PHY_DTPR1_RESERVED_23_MASK 0x00800000U + +/* +* 4-bank activate period +*/ +#undef DDR_PHY_DTPR1_TFAW_DEFVAL +#undef DDR_PHY_DTPR1_TFAW_SHIFT +#undef DDR_PHY_DTPR1_TFAW_MASK +#define DDR_PHY_DTPR1_TFAW_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TFAW_SHIFT 16 +#define DDR_PHY_DTPR1_TFAW_MASK 0x007F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL +#undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT +#undef DDR_PHY_DTPR1_RESERVED_15_11_MASK +#define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 11 +#define DDR_PHY_DTPR1_RESERVED_15_11_MASK 0x0000F800U + +/* +* Load mode update delay (DDR4 and DDR3 only) +*/ +#undef DDR_PHY_DTPR1_TMOD_DEFVAL +#undef DDR_PHY_DTPR1_TMOD_SHIFT +#undef DDR_PHY_DTPR1_TMOD_MASK +#define DDR_PHY_DTPR1_TMOD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TMOD_SHIFT 8 +#define DDR_PHY_DTPR1_TMOD_MASK 0x00000700U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL +#undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT +#undef DDR_PHY_DTPR1_RESERVED_7_5_MASK +#define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR1_RESERVED_7_5_MASK 0x000000E0U + +/* +* Load mode cycle time +*/ +#undef DDR_PHY_DTPR1_TMRD_DEFVAL +#undef DDR_PHY_DTPR1_TMRD_SHIFT +#undef DDR_PHY_DTPR1_TMRD_MASK +#define DDR_PHY_DTPR1_TMRD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TMRD_SHIFT 0 +#define DDR_PHY_DTPR1_TMRD_MASK 0x0000001FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT +#undef DDR_PHY_DTPR2_RESERVED_31_29_MASK +#define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DTPR2_RESERVED_31_29_MASK 0xE0000000U + +/* +* Read to Write command delay. Valid values are +*/ +#undef DDR_PHY_DTPR2_TRTW_DEFVAL +#undef DDR_PHY_DTPR2_TRTW_SHIFT +#undef DDR_PHY_DTPR2_TRTW_MASK +#define DDR_PHY_DTPR2_TRTW_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TRTW_SHIFT 28 +#define DDR_PHY_DTPR2_TRTW_MASK 0x10000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL +#undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT +#undef DDR_PHY_DTPR2_RESERVED_27_25_MASK +#define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 25 +#define DDR_PHY_DTPR2_RESERVED_27_25_MASK 0x0E000000U + +/* +* Read to ODT delay (DDR3 only) +*/ +#undef DDR_PHY_DTPR2_TRTODT_DEFVAL +#undef DDR_PHY_DTPR2_TRTODT_SHIFT +#undef DDR_PHY_DTPR2_TRTODT_MASK +#define DDR_PHY_DTPR2_TRTODT_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TRTODT_SHIFT 24 +#define DDR_PHY_DTPR2_TRTODT_MASK 0x01000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL +#undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT +#undef DDR_PHY_DTPR2_RESERVED_23_20_MASK +#define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 20 +#define DDR_PHY_DTPR2_RESERVED_23_20_MASK 0x00F00000U + +/* +* CKE minimum pulse width +*/ +#undef DDR_PHY_DTPR2_TCKE_DEFVAL +#undef DDR_PHY_DTPR2_TCKE_SHIFT +#undef DDR_PHY_DTPR2_TCKE_MASK +#define DDR_PHY_DTPR2_TCKE_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TCKE_SHIFT 16 +#define DDR_PHY_DTPR2_TCKE_MASK 0x000F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL +#undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT +#undef DDR_PHY_DTPR2_RESERVED_15_10_MASK +#define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_DTPR2_RESERVED_15_10_MASK 0x0000FC00U + +/* +* Self refresh exit delay +*/ +#undef DDR_PHY_DTPR2_TXS_DEFVAL +#undef DDR_PHY_DTPR2_TXS_SHIFT +#undef DDR_PHY_DTPR2_TXS_MASK +#define DDR_PHY_DTPR2_TXS_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TXS_SHIFT 0 +#define DDR_PHY_DTPR2_TXS_MASK 0x000003FFU + +/* +* ODT turn-off delay extension +*/ +#undef DDR_PHY_DTPR3_TOFDX_DEFVAL +#undef DDR_PHY_DTPR3_TOFDX_SHIFT +#undef DDR_PHY_DTPR3_TOFDX_MASK +#define DDR_PHY_DTPR3_TOFDX_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TOFDX_SHIFT 29 +#define DDR_PHY_DTPR3_TOFDX_MASK 0xE0000000U + +/* +* Read to read and write to write command delay +*/ +#undef DDR_PHY_DTPR3_TCCD_DEFVAL +#undef DDR_PHY_DTPR3_TCCD_SHIFT +#undef DDR_PHY_DTPR3_TCCD_MASK +#define DDR_PHY_DTPR3_TCCD_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TCCD_SHIFT 26 +#define DDR_PHY_DTPR3_TCCD_MASK 0x1C000000U + +/* +* DLL locking time +*/ +#undef DDR_PHY_DTPR3_TDLLK_DEFVAL +#undef DDR_PHY_DTPR3_TDLLK_SHIFT +#undef DDR_PHY_DTPR3_TDLLK_MASK +#define DDR_PHY_DTPR3_TDLLK_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDLLK_SHIFT 16 +#define DDR_PHY_DTPR3_TDLLK_MASK 0x03FF0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL +#undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT +#undef DDR_PHY_DTPR3_RESERVED_15_12_MASK +#define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 12 +#define DDR_PHY_DTPR3_RESERVED_15_12_MASK 0x0000F000U + +/* +* Maximum DQS output access time from CK/CK# (LPDDR2/3 only) +*/ +#undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL +#undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT +#undef DDR_PHY_DTPR3_TDQSCKMAX_MASK +#define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 8 +#define DDR_PHY_DTPR3_TDQSCKMAX_MASK 0x00000F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL +#undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT +#undef DDR_PHY_DTPR3_RESERVED_7_3_MASK +#define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 3 +#define DDR_PHY_DTPR3_RESERVED_7_3_MASK 0x000000F8U + +/* +* DQS output access time from CK/CK# (LPDDR2/3 only) +*/ +#undef DDR_PHY_DTPR3_TDQSCK_DEFVAL +#undef DDR_PHY_DTPR3_TDQSCK_SHIFT +#undef DDR_PHY_DTPR3_TDQSCK_MASK +#define DDR_PHY_DTPR3_TDQSCK_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDQSCK_SHIFT 0 +#define DDR_PHY_DTPR3_TDQSCK_MASK 0x00000007U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT +#undef DDR_PHY_DTPR4_RESERVED_31_30_MASK +#define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DTPR4_RESERVED_31_30_MASK 0xC0000000U + +/* +* ODT turn-on/turn-off delays (DDR2 only) +*/ +#undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL +#undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT +#undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK +#define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 28 +#define DDR_PHY_DTPR4_TAOND_TAOFD_MASK 0x30000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL +#undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT +#undef DDR_PHY_DTPR4_RESERVED_27_26_MASK +#define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 26 +#define DDR_PHY_DTPR4_RESERVED_27_26_MASK 0x0C000000U + +/* +* Refresh-to-Refresh +*/ +#undef DDR_PHY_DTPR4_TRFC_DEFVAL +#undef DDR_PHY_DTPR4_TRFC_SHIFT +#undef DDR_PHY_DTPR4_TRFC_MASK +#define DDR_PHY_DTPR4_TRFC_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TRFC_SHIFT 16 +#define DDR_PHY_DTPR4_TRFC_MASK 0x03FF0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT +#undef DDR_PHY_DTPR4_RESERVED_15_14_MASK +#define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DTPR4_RESERVED_15_14_MASK 0x0000C000U + +/* +* Write leveling output delay +*/ +#undef DDR_PHY_DTPR4_TWLO_DEFVAL +#undef DDR_PHY_DTPR4_TWLO_SHIFT +#undef DDR_PHY_DTPR4_TWLO_MASK +#define DDR_PHY_DTPR4_TWLO_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TWLO_SHIFT 8 +#define DDR_PHY_DTPR4_TWLO_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL +#undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT +#undef DDR_PHY_DTPR4_RESERVED_7_5_MASK +#define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR4_RESERVED_7_5_MASK 0x000000E0U + +/* +* Power down exit delay +*/ +#undef DDR_PHY_DTPR4_TXP_DEFVAL +#undef DDR_PHY_DTPR4_TXP_SHIFT +#undef DDR_PHY_DTPR4_TXP_MASK +#define DDR_PHY_DTPR4_TXP_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TXP_SHIFT 0 +#define DDR_PHY_DTPR4_TXP_MASK 0x0000001FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL +#undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT +#undef DDR_PHY_DTPR5_RESERVED_31_24_MASK +#define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DTPR5_RESERVED_31_24_MASK 0xFF000000U + +/* +* Activate to activate command delay (same bank) +*/ +#undef DDR_PHY_DTPR5_TRC_DEFVAL +#undef DDR_PHY_DTPR5_TRC_SHIFT +#undef DDR_PHY_DTPR5_TRC_MASK +#define DDR_PHY_DTPR5_TRC_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TRC_SHIFT 16 +#define DDR_PHY_DTPR5_TRC_MASK 0x00FF0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DTPR5_RESERVED_15_SHIFT +#undef DDR_PHY_DTPR5_RESERVED_15_MASK +#define DDR_PHY_DTPR5_RESERVED_15_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DTPR5_RESERVED_15_MASK 0x00008000U + +/* +* Activate to read or write delay +*/ +#undef DDR_PHY_DTPR5_TRCD_DEFVAL +#undef DDR_PHY_DTPR5_TRCD_SHIFT +#undef DDR_PHY_DTPR5_TRCD_MASK +#define DDR_PHY_DTPR5_TRCD_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TRCD_SHIFT 8 +#define DDR_PHY_DTPR5_TRCD_MASK 0x00007F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL +#undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT +#undef DDR_PHY_DTPR5_RESERVED_7_5_MASK +#define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR5_RESERVED_7_5_MASK 0x000000E0U + +/* +* Internal write to read command delay +*/ +#undef DDR_PHY_DTPR5_TWTR_DEFVAL +#undef DDR_PHY_DTPR5_TWTR_SHIFT +#undef DDR_PHY_DTPR5_TWTR_MASK +#define DDR_PHY_DTPR5_TWTR_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TWTR_SHIFT 0 +#define DDR_PHY_DTPR5_TWTR_MASK 0x0000001FU + +/* +* PUB Write Latency Enable +*/ +#undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL +#undef DDR_PHY_DTPR6_PUBWLEN_SHIFT +#undef DDR_PHY_DTPR6_PUBWLEN_MASK +#define DDR_PHY_DTPR6_PUBWLEN_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBWLEN_SHIFT 31 +#define DDR_PHY_DTPR6_PUBWLEN_MASK 0x80000000U + +/* +* PUB Read Latency Enable +*/ +#undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL +#undef DDR_PHY_DTPR6_PUBRLEN_SHIFT +#undef DDR_PHY_DTPR6_PUBRLEN_MASK +#define DDR_PHY_DTPR6_PUBRLEN_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBRLEN_SHIFT 30 +#define DDR_PHY_DTPR6_PUBRLEN_MASK 0x40000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL +#undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT +#undef DDR_PHY_DTPR6_RESERVED_29_14_MASK +#define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 14 +#define DDR_PHY_DTPR6_RESERVED_29_14_MASK 0x3FFFC000U + +/* +* Write Latency +*/ +#undef DDR_PHY_DTPR6_PUBWL_DEFVAL +#undef DDR_PHY_DTPR6_PUBWL_SHIFT +#undef DDR_PHY_DTPR6_PUBWL_MASK +#define DDR_PHY_DTPR6_PUBWL_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBWL_SHIFT 8 +#define DDR_PHY_DTPR6_PUBWL_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DTPR6_RESERVED_7_6_MASK +#define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DTPR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* Read Latency +*/ +#undef DDR_PHY_DTPR6_PUBRL_DEFVAL +#undef DDR_PHY_DTPR6_PUBRL_SHIFT +#undef DDR_PHY_DTPR6_PUBRL_MASK +#define DDR_PHY_DTPR6_PUBRL_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBRL_SHIFT 0 +#define DDR_PHY_DTPR6_PUBRL_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT +#undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK +#define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 31 +#define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 0x80000000U + +/* +* RDMIMM Quad CS Enable +*/ +#undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL +#undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT +#undef DDR_PHY_RDIMMGCR0_QCSEN_MASK +#define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 30 +#define DDR_PHY_RDIMMGCR0_QCSEN_MASK 0x40000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT +#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 28 +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 0x30000000U + +/* +* RDIMM Outputs I/O Mode +*/ +#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT +#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 27 +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 0x08000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT +#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 24 +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 0x07000000U + +/* +* ERROUT# Output Enable +*/ +#undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL +#undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT +#undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK +#define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 23 +#define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 0x00800000U + +/* +* ERROUT# I/O Mode +*/ +#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL +#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT +#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 22 +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 0x00400000U + +/* +* ERROUT# Power Down Receiver +*/ +#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL +#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT +#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 21 +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 0x00200000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT +#undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK +#define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 20 +#define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 0x00100000U + +/* +* ERROUT# On-Die Termination +*/ +#undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL +#undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT +#undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK +#define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 19 +#define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 0x00080000U + +/* +* Load Reduced DIMM +*/ +#undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL +#undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT +#undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK +#define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 18 +#define DDR_PHY_RDIMMGCR0_LRDIMM_MASK 0x00040000U + +/* +* PAR_IN I/O Mode +*/ +#undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL +#undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT +#undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK +#define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 17 +#define DDR_PHY_RDIMMGCR0_PARINIOM_MASK 0x00020000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT +#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 8 +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 0x0001FF00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT +#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 6 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 0x000000C0U + +/* +* Rank Mirror Enable. +*/ +#undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT +#undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK +#define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 4 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 0x00000030U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT +#undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK +#define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 3 +#define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 0x00000008U + +/* +* Stop on Parity Error +*/ +#undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL +#undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT +#undef DDR_PHY_RDIMMGCR0_SOPERR_MASK +#define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 2 +#define DDR_PHY_RDIMMGCR0_SOPERR_MASK 0x00000004U + +/* +* Parity Error No Registering +*/ +#undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL +#undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT +#undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK +#define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 1 +#define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 0x00000002U + +/* +* Registered DIMM +*/ +#undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL +#undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT +#undef DDR_PHY_RDIMMGCR0_RDIMM_MASK +#define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 0 +#define DDR_PHY_RDIMMGCR0_RDIMM_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL +#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT +#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 0xE0000000U + +/* +* Address [17] B-side Inversion Disable +*/ +#undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL +#undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT +#undef DDR_PHY_RDIMMGCR1_A17BID_MASK +#define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_A17BID_SHIFT 28 +#define DDR_PHY_RDIMMGCR1_A17BID_MASK 0x10000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL +#undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT +#undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK +#define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 27 +#define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 0x08000000U + +/* +* Command word to command word programming delay +*/ +#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL +#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT +#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 24 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 0x07000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL +#undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT +#undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK +#define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 23 +#define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 0x00800000U + +/* +* Command word to command word programming delay +*/ +#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL +#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT +#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 20 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 0x00700000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL +#undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT +#undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK +#define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 19 +#define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 0x00080000U + +/* +* Command word to command word programming delay +*/ +#undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL +#undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT +#undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK +#define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 16 +#define DDR_PHY_RDIMMGCR1_TBCMRD_MASK 0x00070000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL +#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT +#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 0x0000C000U + +/* +* Stabilization time +*/ +#undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL +#undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT +#undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK +#define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 0 +#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 0x00003FFFU + +/* +* DDR4/DDR3 Control Word 7 +*/ +#undef DDR_PHY_RDIMMCR0_RC7_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC7_SHIFT +#undef DDR_PHY_RDIMMCR0_RC7_MASK +#define DDR_PHY_RDIMMCR0_RC7_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC7_SHIFT 28 +#define DDR_PHY_RDIMMCR0_RC7_MASK 0xF0000000U + +/* +* DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved +*/ +#undef DDR_PHY_RDIMMCR0_RC6_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC6_SHIFT +#undef DDR_PHY_RDIMMCR0_RC6_MASK +#define DDR_PHY_RDIMMCR0_RC6_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC6_SHIFT 24 +#define DDR_PHY_RDIMMCR0_RC6_MASK 0x0F000000U + +/* +* DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) +*/ +#undef DDR_PHY_RDIMMCR0_RC5_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC5_SHIFT +#undef DDR_PHY_RDIMMCR0_RC5_MASK +#define DDR_PHY_RDIMMCR0_RC5_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC5_SHIFT 20 +#define DDR_PHY_RDIMMCR0_RC5_MASK 0x00F00000U + +/* +* DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control + * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont + * rol Word) +*/ +#undef DDR_PHY_RDIMMCR0_RC4_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC4_SHIFT +#undef DDR_PHY_RDIMMCR0_RC4_MASK +#define DDR_PHY_RDIMMCR0_RC4_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC4_SHIFT 16 +#define DDR_PHY_RDIMMCR0_RC4_MASK 0x000F0000U + +/* +* DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo + * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri + * cs Control Word) +*/ +#undef DDR_PHY_RDIMMCR0_RC3_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC3_SHIFT +#undef DDR_PHY_RDIMMCR0_RC3_MASK +#define DDR_PHY_RDIMMCR0_RC3_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC3_SHIFT 12 +#define DDR_PHY_RDIMMCR0_RC3_MASK 0x0000F000U + +/* +* DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 + * (Timing Control Word) +*/ +#undef DDR_PHY_RDIMMCR0_RC2_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC2_SHIFT +#undef DDR_PHY_RDIMMCR0_RC2_MASK +#define DDR_PHY_RDIMMCR0_RC2_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC2_SHIFT 8 +#define DDR_PHY_RDIMMCR0_RC2_MASK 0x00000F00U + +/* +* DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) +*/ +#undef DDR_PHY_RDIMMCR0_RC1_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC1_SHIFT +#undef DDR_PHY_RDIMMCR0_RC1_MASK +#define DDR_PHY_RDIMMCR0_RC1_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC1_SHIFT 4 +#define DDR_PHY_RDIMMCR0_RC1_MASK 0x000000F0U + +/* +* DDR4/DDR3 Control Word 0 (Global Features Control Word) +*/ +#undef DDR_PHY_RDIMMCR0_RC0_DEFVAL +#undef DDR_PHY_RDIMMCR0_RC0_SHIFT +#undef DDR_PHY_RDIMMCR0_RC0_MASK +#define DDR_PHY_RDIMMCR0_RC0_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC0_SHIFT 0 +#define DDR_PHY_RDIMMCR0_RC0_MASK 0x0000000FU + +/* +* Control Word 15 +*/ +#undef DDR_PHY_RDIMMCR1_RC15_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC15_SHIFT +#undef DDR_PHY_RDIMMCR1_RC15_MASK +#define DDR_PHY_RDIMMCR1_RC15_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC15_SHIFT 28 +#define DDR_PHY_RDIMMCR1_RC15_MASK 0xF0000000U + +/* +* DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved +*/ +#undef DDR_PHY_RDIMMCR1_RC14_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC14_SHIFT +#undef DDR_PHY_RDIMMCR1_RC14_MASK +#define DDR_PHY_RDIMMCR1_RC14_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC14_SHIFT 24 +#define DDR_PHY_RDIMMCR1_RC14_MASK 0x0F000000U + +/* +* DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved +*/ +#undef DDR_PHY_RDIMMCR1_RC13_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC13_SHIFT +#undef DDR_PHY_RDIMMCR1_RC13_MASK +#define DDR_PHY_RDIMMCR1_RC13_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC13_SHIFT 20 +#define DDR_PHY_RDIMMCR1_RC13_MASK 0x00F00000U + +/* +* DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved +*/ +#undef DDR_PHY_RDIMMCR1_RC12_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC12_SHIFT +#undef DDR_PHY_RDIMMCR1_RC12_MASK +#define DDR_PHY_RDIMMCR1_RC12_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC12_SHIFT 16 +#define DDR_PHY_RDIMMCR1_RC12_MASK 0x000F0000U + +/* +* DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo + * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word) +*/ +#undef DDR_PHY_RDIMMCR1_RC11_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC11_SHIFT +#undef DDR_PHY_RDIMMCR1_RC11_MASK +#define DDR_PHY_RDIMMCR1_RC11_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC11_SHIFT 12 +#define DDR_PHY_RDIMMCR1_RC11_MASK 0x0000F000U + +/* +* DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) +*/ +#undef DDR_PHY_RDIMMCR1_RC10_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC10_SHIFT +#undef DDR_PHY_RDIMMCR1_RC10_MASK +#define DDR_PHY_RDIMMCR1_RC10_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC10_SHIFT 8 +#define DDR_PHY_RDIMMCR1_RC10_MASK 0x00000F00U + +/* +* DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) +*/ +#undef DDR_PHY_RDIMMCR1_RC9_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC9_SHIFT +#undef DDR_PHY_RDIMMCR1_RC9_MASK +#define DDR_PHY_RDIMMCR1_RC9_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC9_SHIFT 4 +#define DDR_PHY_RDIMMCR1_RC9_MASK 0x000000F0U + +/* +* DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con + * trol Word 8 (Additional Input Bus Termination Setting Control Word) +*/ +#undef DDR_PHY_RDIMMCR1_RC8_DEFVAL +#undef DDR_PHY_RDIMMCR1_RC8_SHIFT +#undef DDR_PHY_RDIMMCR1_RC8_MASK +#define DDR_PHY_RDIMMCR1_RC8_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC8_SHIFT 0 +#define DDR_PHY_RDIMMCR1_RC8_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR0_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR0_RESERVED_31_8_MASK +#define DDR_PHY_MR0_RESERVED_31_8_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR0_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* CA Terminating Rank +*/ +#undef DDR_PHY_MR0_CATR_DEFVAL +#undef DDR_PHY_MR0_CATR_SHIFT +#undef DDR_PHY_MR0_CATR_MASK +#define DDR_PHY_MR0_CATR_DEFVAL 0x00000052 +#define DDR_PHY_MR0_CATR_SHIFT 7 +#define DDR_PHY_MR0_CATR_MASK 0x00000080U + +/* +* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. +*/ +#undef DDR_PHY_MR0_RSVD_6_5_DEFVAL +#undef DDR_PHY_MR0_RSVD_6_5_SHIFT +#undef DDR_PHY_MR0_RSVD_6_5_MASK +#define DDR_PHY_MR0_RSVD_6_5_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RSVD_6_5_SHIFT 5 +#define DDR_PHY_MR0_RSVD_6_5_MASK 0x00000060U + +/* +* Built-in Self-Test for RZQ +*/ +#undef DDR_PHY_MR0_RZQI_DEFVAL +#undef DDR_PHY_MR0_RZQI_SHIFT +#undef DDR_PHY_MR0_RZQI_MASK +#define DDR_PHY_MR0_RZQI_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RZQI_SHIFT 3 +#define DDR_PHY_MR0_RZQI_MASK 0x00000018U + +/* +* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. +*/ +#undef DDR_PHY_MR0_RSVD_2_0_DEFVAL +#undef DDR_PHY_MR0_RSVD_2_0_SHIFT +#undef DDR_PHY_MR0_RSVD_2_0_MASK +#define DDR_PHY_MR0_RSVD_2_0_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RSVD_2_0_SHIFT 0 +#define DDR_PHY_MR0_RSVD_2_0_MASK 0x00000007U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR1_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR1_RESERVED_31_8_MASK +#define DDR_PHY_MR1_RESERVED_31_8_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR1_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* Read Postamble Length +*/ +#undef DDR_PHY_MR1_RDPST_DEFVAL +#undef DDR_PHY_MR1_RDPST_SHIFT +#undef DDR_PHY_MR1_RDPST_MASK +#define DDR_PHY_MR1_RDPST_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RDPST_SHIFT 7 +#define DDR_PHY_MR1_RDPST_MASK 0x00000080U + +/* +* Write-recovery for auto-precharge command +*/ +#undef DDR_PHY_MR1_NWR_DEFVAL +#undef DDR_PHY_MR1_NWR_SHIFT +#undef DDR_PHY_MR1_NWR_MASK +#define DDR_PHY_MR1_NWR_DEFVAL 0x00000004 +#define DDR_PHY_MR1_NWR_SHIFT 4 +#define DDR_PHY_MR1_NWR_MASK 0x00000070U + +/* +* Read Preamble Length +*/ +#undef DDR_PHY_MR1_RDPRE_DEFVAL +#undef DDR_PHY_MR1_RDPRE_SHIFT +#undef DDR_PHY_MR1_RDPRE_MASK +#define DDR_PHY_MR1_RDPRE_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RDPRE_SHIFT 3 +#define DDR_PHY_MR1_RDPRE_MASK 0x00000008U + +/* +* Write Preamble Length +*/ +#undef DDR_PHY_MR1_WRPRE_DEFVAL +#undef DDR_PHY_MR1_WRPRE_SHIFT +#undef DDR_PHY_MR1_WRPRE_MASK +#define DDR_PHY_MR1_WRPRE_DEFVAL 0x00000004 +#define DDR_PHY_MR1_WRPRE_SHIFT 2 +#define DDR_PHY_MR1_WRPRE_MASK 0x00000004U + +/* +* Burst Length +*/ +#undef DDR_PHY_MR1_BL_DEFVAL +#undef DDR_PHY_MR1_BL_SHIFT +#undef DDR_PHY_MR1_BL_MASK +#define DDR_PHY_MR1_BL_DEFVAL 0x00000004 +#define DDR_PHY_MR1_BL_SHIFT 0 +#define DDR_PHY_MR1_BL_MASK 0x00000003U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR2_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR2_RESERVED_31_8_MASK +#define DDR_PHY_MR2_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR2_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR2_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* Write Leveling +*/ +#undef DDR_PHY_MR2_WRL_DEFVAL +#undef DDR_PHY_MR2_WRL_SHIFT +#undef DDR_PHY_MR2_WRL_MASK +#define DDR_PHY_MR2_WRL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WRL_SHIFT 7 +#define DDR_PHY_MR2_WRL_MASK 0x00000080U + +/* +* Write Latency Set +*/ +#undef DDR_PHY_MR2_WLS_DEFVAL +#undef DDR_PHY_MR2_WLS_SHIFT +#undef DDR_PHY_MR2_WLS_MASK +#define DDR_PHY_MR2_WLS_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WLS_SHIFT 6 +#define DDR_PHY_MR2_WLS_MASK 0x00000040U + +/* +* Write Latency +*/ +#undef DDR_PHY_MR2_WL_DEFVAL +#undef DDR_PHY_MR2_WL_SHIFT +#undef DDR_PHY_MR2_WL_MASK +#define DDR_PHY_MR2_WL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WL_SHIFT 3 +#define DDR_PHY_MR2_WL_MASK 0x00000038U + +/* +* Read Latency +*/ +#undef DDR_PHY_MR2_RL_DEFVAL +#undef DDR_PHY_MR2_RL_SHIFT +#undef DDR_PHY_MR2_RL_MASK +#define DDR_PHY_MR2_RL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_RL_SHIFT 0 +#define DDR_PHY_MR2_RL_MASK 0x00000007U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR3_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR3_RESERVED_31_8_MASK +#define DDR_PHY_MR3_RESERVED_31_8_DEFVAL 0x00000031 +#define DDR_PHY_MR3_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR3_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* DBI-Write Enable +*/ +#undef DDR_PHY_MR3_DBIWR_DEFVAL +#undef DDR_PHY_MR3_DBIWR_SHIFT +#undef DDR_PHY_MR3_DBIWR_MASK +#define DDR_PHY_MR3_DBIWR_DEFVAL 0x00000031 +#define DDR_PHY_MR3_DBIWR_SHIFT 7 +#define DDR_PHY_MR3_DBIWR_MASK 0x00000080U + +/* +* DBI-Read Enable +*/ +#undef DDR_PHY_MR3_DBIRD_DEFVAL +#undef DDR_PHY_MR3_DBIRD_SHIFT +#undef DDR_PHY_MR3_DBIRD_MASK +#define DDR_PHY_MR3_DBIRD_DEFVAL 0x00000031 +#define DDR_PHY_MR3_DBIRD_SHIFT 6 +#define DDR_PHY_MR3_DBIRD_MASK 0x00000040U + +/* +* Pull-down Drive Strength +*/ +#undef DDR_PHY_MR3_PDDS_DEFVAL +#undef DDR_PHY_MR3_PDDS_SHIFT +#undef DDR_PHY_MR3_PDDS_MASK +#define DDR_PHY_MR3_PDDS_DEFVAL 0x00000031 +#define DDR_PHY_MR3_PDDS_SHIFT 3 +#define DDR_PHY_MR3_PDDS_MASK 0x00000038U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR3_RSVD_DEFVAL +#undef DDR_PHY_MR3_RSVD_SHIFT +#undef DDR_PHY_MR3_RSVD_MASK +#define DDR_PHY_MR3_RSVD_DEFVAL 0x00000031 +#define DDR_PHY_MR3_RSVD_SHIFT 2 +#define DDR_PHY_MR3_RSVD_MASK 0x00000004U + +/* +* Write Postamble Length +*/ +#undef DDR_PHY_MR3_WRPST_DEFVAL +#undef DDR_PHY_MR3_WRPST_SHIFT +#undef DDR_PHY_MR3_WRPST_MASK +#define DDR_PHY_MR3_WRPST_DEFVAL 0x00000031 +#define DDR_PHY_MR3_WRPST_SHIFT 1 +#define DDR_PHY_MR3_WRPST_MASK 0x00000002U + +/* +* Pull-up Calibration Point +*/ +#undef DDR_PHY_MR3_PUCAL_DEFVAL +#undef DDR_PHY_MR3_PUCAL_SHIFT +#undef DDR_PHY_MR3_PUCAL_MASK +#define DDR_PHY_MR3_PUCAL_DEFVAL 0x00000031 +#define DDR_PHY_MR3_PUCAL_SHIFT 0 +#define DDR_PHY_MR3_PUCAL_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL +#undef DDR_PHY_MR4_RESERVED_31_16_SHIFT +#undef DDR_PHY_MR4_RESERVED_31_16_MASK +#define DDR_PHY_MR4_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR4_RESERVED_31_16_MASK 0xFFFF0000U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR4_RSVD_15_13_DEFVAL +#undef DDR_PHY_MR4_RSVD_15_13_SHIFT +#undef DDR_PHY_MR4_RSVD_15_13_MASK +#define DDR_PHY_MR4_RSVD_15_13_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD_15_13_SHIFT 13 +#define DDR_PHY_MR4_RSVD_15_13_MASK 0x0000E000U + +/* +* Write Preamble +*/ +#undef DDR_PHY_MR4_WRP_DEFVAL +#undef DDR_PHY_MR4_WRP_SHIFT +#undef DDR_PHY_MR4_WRP_MASK +#define DDR_PHY_MR4_WRP_DEFVAL 0x00000000 +#define DDR_PHY_MR4_WRP_SHIFT 12 +#define DDR_PHY_MR4_WRP_MASK 0x00001000U + +/* +* Read Preamble +*/ +#undef DDR_PHY_MR4_RDP_DEFVAL +#undef DDR_PHY_MR4_RDP_SHIFT +#undef DDR_PHY_MR4_RDP_MASK +#define DDR_PHY_MR4_RDP_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RDP_SHIFT 11 +#define DDR_PHY_MR4_RDP_MASK 0x00000800U + +/* +* Read Preamble Training Mode +*/ +#undef DDR_PHY_MR4_RPTM_DEFVAL +#undef DDR_PHY_MR4_RPTM_SHIFT +#undef DDR_PHY_MR4_RPTM_MASK +#define DDR_PHY_MR4_RPTM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RPTM_SHIFT 10 +#define DDR_PHY_MR4_RPTM_MASK 0x00000400U + +/* +* Self Refresh Abort +*/ +#undef DDR_PHY_MR4_SRA_DEFVAL +#undef DDR_PHY_MR4_SRA_SHIFT +#undef DDR_PHY_MR4_SRA_MASK +#define DDR_PHY_MR4_SRA_DEFVAL 0x00000000 +#define DDR_PHY_MR4_SRA_SHIFT 9 +#define DDR_PHY_MR4_SRA_MASK 0x00000200U + +/* +* CS to Command Latency Mode +*/ +#undef DDR_PHY_MR4_CS2CMDL_DEFVAL +#undef DDR_PHY_MR4_CS2CMDL_SHIFT +#undef DDR_PHY_MR4_CS2CMDL_MASK +#define DDR_PHY_MR4_CS2CMDL_DEFVAL 0x00000000 +#define DDR_PHY_MR4_CS2CMDL_SHIFT 6 +#define DDR_PHY_MR4_CS2CMDL_MASK 0x000001C0U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR4_RSVD1_DEFVAL +#undef DDR_PHY_MR4_RSVD1_SHIFT +#undef DDR_PHY_MR4_RSVD1_MASK +#define DDR_PHY_MR4_RSVD1_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD1_SHIFT 5 +#define DDR_PHY_MR4_RSVD1_MASK 0x00000020U + +/* +* Internal VREF Monitor +*/ +#undef DDR_PHY_MR4_IVM_DEFVAL +#undef DDR_PHY_MR4_IVM_SHIFT +#undef DDR_PHY_MR4_IVM_MASK +#define DDR_PHY_MR4_IVM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_IVM_SHIFT 4 +#define DDR_PHY_MR4_IVM_MASK 0x00000010U + +/* +* Temperature Controlled Refresh Mode +*/ +#undef DDR_PHY_MR4_TCRM_DEFVAL +#undef DDR_PHY_MR4_TCRM_SHIFT +#undef DDR_PHY_MR4_TCRM_MASK +#define DDR_PHY_MR4_TCRM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_TCRM_SHIFT 3 +#define DDR_PHY_MR4_TCRM_MASK 0x00000008U + +/* +* Temperature Controlled Refresh Range +*/ +#undef DDR_PHY_MR4_TCRR_DEFVAL +#undef DDR_PHY_MR4_TCRR_SHIFT +#undef DDR_PHY_MR4_TCRR_MASK +#define DDR_PHY_MR4_TCRR_DEFVAL 0x00000000 +#define DDR_PHY_MR4_TCRR_SHIFT 2 +#define DDR_PHY_MR4_TCRR_MASK 0x00000004U + +/* +* Maximum Power Down Mode +*/ +#undef DDR_PHY_MR4_MPDM_DEFVAL +#undef DDR_PHY_MR4_MPDM_SHIFT +#undef DDR_PHY_MR4_MPDM_MASK +#define DDR_PHY_MR4_MPDM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_MPDM_SHIFT 1 +#define DDR_PHY_MR4_MPDM_MASK 0x00000002U + +/* +* This is a JEDEC reserved bit and is recommended by JEDEC to be programme + * d to 0x0. +*/ +#undef DDR_PHY_MR4_RSVD_0_DEFVAL +#undef DDR_PHY_MR4_RSVD_0_SHIFT +#undef DDR_PHY_MR4_RSVD_0_MASK +#define DDR_PHY_MR4_RSVD_0_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD_0_SHIFT 0 +#define DDR_PHY_MR4_RSVD_0_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL +#undef DDR_PHY_MR5_RESERVED_31_16_SHIFT +#undef DDR_PHY_MR5_RESERVED_31_16_MASK +#define DDR_PHY_MR5_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR5_RESERVED_31_16_MASK 0xFFFF0000U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR5_RSVD_DEFVAL +#undef DDR_PHY_MR5_RSVD_SHIFT +#undef DDR_PHY_MR5_RSVD_MASK +#define DDR_PHY_MR5_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RSVD_SHIFT 13 +#define DDR_PHY_MR5_RSVD_MASK 0x0000E000U + +/* +* Read DBI +*/ +#undef DDR_PHY_MR5_RDBI_DEFVAL +#undef DDR_PHY_MR5_RDBI_SHIFT +#undef DDR_PHY_MR5_RDBI_MASK +#define DDR_PHY_MR5_RDBI_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RDBI_SHIFT 12 +#define DDR_PHY_MR5_RDBI_MASK 0x00001000U + +/* +* Write DBI +*/ +#undef DDR_PHY_MR5_WDBI_DEFVAL +#undef DDR_PHY_MR5_WDBI_SHIFT +#undef DDR_PHY_MR5_WDBI_MASK +#define DDR_PHY_MR5_WDBI_DEFVAL 0x00000000 +#define DDR_PHY_MR5_WDBI_SHIFT 11 +#define DDR_PHY_MR5_WDBI_MASK 0x00000800U + +/* +* Data Mask +*/ +#undef DDR_PHY_MR5_DM_DEFVAL +#undef DDR_PHY_MR5_DM_SHIFT +#undef DDR_PHY_MR5_DM_MASK +#define DDR_PHY_MR5_DM_DEFVAL 0x00000000 +#define DDR_PHY_MR5_DM_SHIFT 10 +#define DDR_PHY_MR5_DM_MASK 0x00000400U + +/* +* CA Parity Persistent Error +*/ +#undef DDR_PHY_MR5_CAPPE_DEFVAL +#undef DDR_PHY_MR5_CAPPE_SHIFT +#undef DDR_PHY_MR5_CAPPE_MASK +#define DDR_PHY_MR5_CAPPE_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPPE_SHIFT 9 +#define DDR_PHY_MR5_CAPPE_MASK 0x00000200U + +/* +* RTT_PARK +*/ +#undef DDR_PHY_MR5_RTTPARK_DEFVAL +#undef DDR_PHY_MR5_RTTPARK_SHIFT +#undef DDR_PHY_MR5_RTTPARK_MASK +#define DDR_PHY_MR5_RTTPARK_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RTTPARK_SHIFT 6 +#define DDR_PHY_MR5_RTTPARK_MASK 0x000001C0U + +/* +* ODT Input Buffer during Power Down mode +*/ +#undef DDR_PHY_MR5_ODTIBPD_DEFVAL +#undef DDR_PHY_MR5_ODTIBPD_SHIFT +#undef DDR_PHY_MR5_ODTIBPD_MASK +#define DDR_PHY_MR5_ODTIBPD_DEFVAL 0x00000000 +#define DDR_PHY_MR5_ODTIBPD_SHIFT 5 +#define DDR_PHY_MR5_ODTIBPD_MASK 0x00000020U + +/* +* C/A Parity Error Status +*/ +#undef DDR_PHY_MR5_CAPES_DEFVAL +#undef DDR_PHY_MR5_CAPES_SHIFT +#undef DDR_PHY_MR5_CAPES_MASK +#define DDR_PHY_MR5_CAPES_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPES_SHIFT 4 +#define DDR_PHY_MR5_CAPES_MASK 0x00000010U + +/* +* CRC Error Clear +*/ +#undef DDR_PHY_MR5_CRCEC_DEFVAL +#undef DDR_PHY_MR5_CRCEC_SHIFT +#undef DDR_PHY_MR5_CRCEC_MASK +#define DDR_PHY_MR5_CRCEC_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CRCEC_SHIFT 3 +#define DDR_PHY_MR5_CRCEC_MASK 0x00000008U + +/* +* C/A Parity Latency Mode +*/ +#undef DDR_PHY_MR5_CAPM_DEFVAL +#undef DDR_PHY_MR5_CAPM_SHIFT +#undef DDR_PHY_MR5_CAPM_MASK +#define DDR_PHY_MR5_CAPM_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPM_SHIFT 0 +#define DDR_PHY_MR5_CAPM_MASK 0x00000007U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL +#undef DDR_PHY_MR6_RESERVED_31_16_SHIFT +#undef DDR_PHY_MR6_RESERVED_31_16_MASK +#define DDR_PHY_MR6_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR6_RESERVED_31_16_MASK 0xFFFF0000U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR6_RSVD_15_13_DEFVAL +#undef DDR_PHY_MR6_RSVD_15_13_SHIFT +#undef DDR_PHY_MR6_RSVD_15_13_MASK +#define DDR_PHY_MR6_RSVD_15_13_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RSVD_15_13_SHIFT 13 +#define DDR_PHY_MR6_RSVD_15_13_MASK 0x0000E000U + +/* +* CAS_n to CAS_n command delay for same bank group (tCCD_L) +*/ +#undef DDR_PHY_MR6_TCCDL_DEFVAL +#undef DDR_PHY_MR6_TCCDL_SHIFT +#undef DDR_PHY_MR6_TCCDL_MASK +#define DDR_PHY_MR6_TCCDL_DEFVAL 0x00000000 +#define DDR_PHY_MR6_TCCDL_SHIFT 10 +#define DDR_PHY_MR6_TCCDL_MASK 0x00001C00U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR6_RSVD_9_8_DEFVAL +#undef DDR_PHY_MR6_RSVD_9_8_SHIFT +#undef DDR_PHY_MR6_RSVD_9_8_MASK +#define DDR_PHY_MR6_RSVD_9_8_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RSVD_9_8_SHIFT 8 +#define DDR_PHY_MR6_RSVD_9_8_MASK 0x00000300U + +/* +* VrefDQ Training Enable +*/ +#undef DDR_PHY_MR6_VDDQTEN_DEFVAL +#undef DDR_PHY_MR6_VDDQTEN_SHIFT +#undef DDR_PHY_MR6_VDDQTEN_MASK +#define DDR_PHY_MR6_VDDQTEN_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDDQTEN_SHIFT 7 +#define DDR_PHY_MR6_VDDQTEN_MASK 0x00000080U + +/* +* VrefDQ Training Range +*/ +#undef DDR_PHY_MR6_VDQTRG_DEFVAL +#undef DDR_PHY_MR6_VDQTRG_SHIFT +#undef DDR_PHY_MR6_VDQTRG_MASK +#define DDR_PHY_MR6_VDQTRG_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDQTRG_SHIFT 6 +#define DDR_PHY_MR6_VDQTRG_MASK 0x00000040U + +/* +* VrefDQ Training Values +*/ +#undef DDR_PHY_MR6_VDQTVAL_DEFVAL +#undef DDR_PHY_MR6_VDQTVAL_SHIFT +#undef DDR_PHY_MR6_VDQTVAL_MASK +#define DDR_PHY_MR6_VDQTVAL_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDQTVAL_SHIFT 0 +#define DDR_PHY_MR6_VDQTVAL_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR11_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR11_RESERVED_31_8_MASK +#define DDR_PHY_MR11_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR11_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR11_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR11_RSVD_DEFVAL +#undef DDR_PHY_MR11_RSVD_SHIFT +#undef DDR_PHY_MR11_RSVD_MASK +#define DDR_PHY_MR11_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR11_RSVD_SHIFT 3 +#define DDR_PHY_MR11_RSVD_MASK 0x000000F8U + +/* +* Power Down Control +*/ +#undef DDR_PHY_MR11_PDCTL_DEFVAL +#undef DDR_PHY_MR11_PDCTL_SHIFT +#undef DDR_PHY_MR11_PDCTL_MASK +#define DDR_PHY_MR11_PDCTL_DEFVAL 0x00000000 +#define DDR_PHY_MR11_PDCTL_SHIFT 2 +#define DDR_PHY_MR11_PDCTL_MASK 0x00000004U + +/* +* DQ Bus Receiver On-Die-Termination +*/ +#undef DDR_PHY_MR11_DQODT_DEFVAL +#undef DDR_PHY_MR11_DQODT_SHIFT +#undef DDR_PHY_MR11_DQODT_MASK +#define DDR_PHY_MR11_DQODT_DEFVAL 0x00000000 +#define DDR_PHY_MR11_DQODT_SHIFT 0 +#define DDR_PHY_MR11_DQODT_MASK 0x00000003U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR12_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR12_RESERVED_31_8_MASK +#define DDR_PHY_MR12_RESERVED_31_8_DEFVAL 0x0000004D +#define DDR_PHY_MR12_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR12_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR12_RSVD_DEFVAL +#undef DDR_PHY_MR12_RSVD_SHIFT +#undef DDR_PHY_MR12_RSVD_MASK +#define DDR_PHY_MR12_RSVD_DEFVAL 0x0000004D +#define DDR_PHY_MR12_RSVD_SHIFT 7 +#define DDR_PHY_MR12_RSVD_MASK 0x00000080U + +/* +* VREF_CA Range Select. +*/ +#undef DDR_PHY_MR12_VR_CA_DEFVAL +#undef DDR_PHY_MR12_VR_CA_SHIFT +#undef DDR_PHY_MR12_VR_CA_MASK +#define DDR_PHY_MR12_VR_CA_DEFVAL 0x0000004D +#define DDR_PHY_MR12_VR_CA_SHIFT 6 +#define DDR_PHY_MR12_VR_CA_MASK 0x00000040U + +/* +* Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. +*/ +#undef DDR_PHY_MR12_VREF_CA_DEFVAL +#undef DDR_PHY_MR12_VREF_CA_SHIFT +#undef DDR_PHY_MR12_VREF_CA_MASK +#define DDR_PHY_MR12_VREF_CA_DEFVAL 0x0000004D +#define DDR_PHY_MR12_VREF_CA_SHIFT 0 +#define DDR_PHY_MR12_VREF_CA_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR13_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR13_RESERVED_31_8_MASK +#define DDR_PHY_MR13_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR13_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* Frequency Set Point Operation Mode +*/ +#undef DDR_PHY_MR13_FSPOP_DEFVAL +#undef DDR_PHY_MR13_FSPOP_SHIFT +#undef DDR_PHY_MR13_FSPOP_MASK +#define DDR_PHY_MR13_FSPOP_DEFVAL 0x00000000 +#define DDR_PHY_MR13_FSPOP_SHIFT 7 +#define DDR_PHY_MR13_FSPOP_MASK 0x00000080U + +/* +* Frequency Set Point Write Enable +*/ +#undef DDR_PHY_MR13_FSPWR_DEFVAL +#undef DDR_PHY_MR13_FSPWR_SHIFT +#undef DDR_PHY_MR13_FSPWR_MASK +#define DDR_PHY_MR13_FSPWR_DEFVAL 0x00000000 +#define DDR_PHY_MR13_FSPWR_SHIFT 6 +#define DDR_PHY_MR13_FSPWR_MASK 0x00000040U + +/* +* Data Mask Enable +*/ +#undef DDR_PHY_MR13_DMD_DEFVAL +#undef DDR_PHY_MR13_DMD_SHIFT +#undef DDR_PHY_MR13_DMD_MASK +#define DDR_PHY_MR13_DMD_DEFVAL 0x00000000 +#define DDR_PHY_MR13_DMD_SHIFT 5 +#define DDR_PHY_MR13_DMD_MASK 0x00000020U + +/* +* Refresh Rate Option +*/ +#undef DDR_PHY_MR13_RRO_DEFVAL +#undef DDR_PHY_MR13_RRO_SHIFT +#undef DDR_PHY_MR13_RRO_MASK +#define DDR_PHY_MR13_RRO_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RRO_SHIFT 4 +#define DDR_PHY_MR13_RRO_MASK 0x00000010U + +/* +* VREF Current Generator +*/ +#undef DDR_PHY_MR13_VRCG_DEFVAL +#undef DDR_PHY_MR13_VRCG_SHIFT +#undef DDR_PHY_MR13_VRCG_MASK +#define DDR_PHY_MR13_VRCG_DEFVAL 0x00000000 +#define DDR_PHY_MR13_VRCG_SHIFT 3 +#define DDR_PHY_MR13_VRCG_MASK 0x00000008U + +/* +* VREF Output +*/ +#undef DDR_PHY_MR13_VRO_DEFVAL +#undef DDR_PHY_MR13_VRO_SHIFT +#undef DDR_PHY_MR13_VRO_MASK +#define DDR_PHY_MR13_VRO_DEFVAL 0x00000000 +#define DDR_PHY_MR13_VRO_SHIFT 2 +#define DDR_PHY_MR13_VRO_MASK 0x00000004U + +/* +* Read Preamble Training Mode +*/ +#undef DDR_PHY_MR13_RPT_DEFVAL +#undef DDR_PHY_MR13_RPT_SHIFT +#undef DDR_PHY_MR13_RPT_MASK +#define DDR_PHY_MR13_RPT_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RPT_SHIFT 1 +#define DDR_PHY_MR13_RPT_MASK 0x00000002U + +/* +* Command Bus Training +*/ +#undef DDR_PHY_MR13_CBT_DEFVAL +#undef DDR_PHY_MR13_CBT_SHIFT +#undef DDR_PHY_MR13_CBT_MASK +#define DDR_PHY_MR13_CBT_DEFVAL 0x00000000 +#define DDR_PHY_MR13_CBT_SHIFT 0 +#define DDR_PHY_MR13_CBT_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR14_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR14_RESERVED_31_8_MASK +#define DDR_PHY_MR14_RESERVED_31_8_DEFVAL 0x0000004D +#define DDR_PHY_MR14_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR14_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR14_RSVD_DEFVAL +#undef DDR_PHY_MR14_RSVD_SHIFT +#undef DDR_PHY_MR14_RSVD_MASK +#define DDR_PHY_MR14_RSVD_DEFVAL 0x0000004D +#define DDR_PHY_MR14_RSVD_SHIFT 7 +#define DDR_PHY_MR14_RSVD_MASK 0x00000080U + +/* +* VREFDQ Range Selects. +*/ +#undef DDR_PHY_MR14_VR_DQ_DEFVAL +#undef DDR_PHY_MR14_VR_DQ_SHIFT +#undef DDR_PHY_MR14_VR_DQ_MASK +#define DDR_PHY_MR14_VR_DQ_DEFVAL 0x0000004D +#define DDR_PHY_MR14_VR_DQ_SHIFT 6 +#define DDR_PHY_MR14_VR_DQ_MASK 0x00000040U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR14_VREF_DQ_DEFVAL +#undef DDR_PHY_MR14_VREF_DQ_SHIFT +#undef DDR_PHY_MR14_VREF_DQ_MASK +#define DDR_PHY_MR14_VREF_DQ_DEFVAL 0x0000004D +#define DDR_PHY_MR14_VREF_DQ_SHIFT 0 +#define DDR_PHY_MR14_VREF_DQ_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL +#undef DDR_PHY_MR22_RESERVED_31_8_SHIFT +#undef DDR_PHY_MR22_RESERVED_31_8_MASK +#define DDR_PHY_MR22_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR22_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR22_RESERVED_31_8_MASK 0xFFFFFF00U + +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ +#undef DDR_PHY_MR22_RSVD_DEFVAL +#undef DDR_PHY_MR22_RSVD_SHIFT +#undef DDR_PHY_MR22_RSVD_MASK +#define DDR_PHY_MR22_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR22_RSVD_SHIFT 6 +#define DDR_PHY_MR22_RSVD_MASK 0x000000C0U + +/* +* CA ODT termination disable. +*/ +#undef DDR_PHY_MR22_ODTD_CA_DEFVAL +#undef DDR_PHY_MR22_ODTD_CA_SHIFT +#undef DDR_PHY_MR22_ODTD_CA_MASK +#define DDR_PHY_MR22_ODTD_CA_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTD_CA_SHIFT 5 +#define DDR_PHY_MR22_ODTD_CA_MASK 0x00000020U + +/* +* ODT CS override. +*/ +#undef DDR_PHY_MR22_ODTE_CS_DEFVAL +#undef DDR_PHY_MR22_ODTE_CS_SHIFT +#undef DDR_PHY_MR22_ODTE_CS_MASK +#define DDR_PHY_MR22_ODTE_CS_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTE_CS_SHIFT 4 +#define DDR_PHY_MR22_ODTE_CS_MASK 0x00000010U + +/* +* ODT CK override. +*/ +#undef DDR_PHY_MR22_ODTE_CK_DEFVAL +#undef DDR_PHY_MR22_ODTE_CK_SHIFT +#undef DDR_PHY_MR22_ODTE_CK_MASK +#define DDR_PHY_MR22_ODTE_CK_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTE_CK_SHIFT 3 +#define DDR_PHY_MR22_ODTE_CK_MASK 0x00000008U + +/* +* Controller ODT value for VOH calibration. +*/ +#undef DDR_PHY_MR22_CODT_DEFVAL +#undef DDR_PHY_MR22_CODT_SHIFT +#undef DDR_PHY_MR22_CODT_MASK +#define DDR_PHY_MR22_CODT_DEFVAL 0x00000000 +#define DDR_PHY_MR22_CODT_SHIFT 0 +#define DDR_PHY_MR22_CODT_MASK 0x00000007U + +/* +* Refresh During Training +*/ +#undef DDR_PHY_DTCR0_RFSHDT_DEFVAL +#undef DDR_PHY_DTCR0_RFSHDT_SHIFT +#undef DDR_PHY_DTCR0_RFSHDT_MASK +#define DDR_PHY_DTCR0_RFSHDT_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RFSHDT_SHIFT 28 +#define DDR_PHY_DTCR0_RFSHDT_MASK 0xF0000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL +#undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT +#undef DDR_PHY_DTCR0_RESERVED_27_26_MASK +#define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 26 +#define DDR_PHY_DTCR0_RESERVED_27_26_MASK 0x0C000000U + +/* +* Data Training Debug Rank Select +*/ +#undef DDR_PHY_DTCR0_DTDRS_DEFVAL +#undef DDR_PHY_DTCR0_DTDRS_SHIFT +#undef DDR_PHY_DTCR0_DTDRS_MASK +#define DDR_PHY_DTCR0_DTDRS_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDRS_SHIFT 24 +#define DDR_PHY_DTCR0_DTDRS_MASK 0x03000000U + +/* +* Data Training with Early/Extended Gate +*/ +#undef DDR_PHY_DTCR0_DTEXG_DEFVAL +#undef DDR_PHY_DTCR0_DTEXG_SHIFT +#undef DDR_PHY_DTCR0_DTEXG_MASK +#define DDR_PHY_DTCR0_DTEXG_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTEXG_SHIFT 23 +#define DDR_PHY_DTCR0_DTEXG_MASK 0x00800000U + +/* +* Data Training Extended Write DQS +*/ +#undef DDR_PHY_DTCR0_DTEXD_DEFVAL +#undef DDR_PHY_DTCR0_DTEXD_SHIFT +#undef DDR_PHY_DTCR0_DTEXD_MASK +#define DDR_PHY_DTCR0_DTEXD_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTEXD_SHIFT 22 +#define DDR_PHY_DTCR0_DTEXD_MASK 0x00400000U + +/* +* Data Training Debug Step +*/ +#undef DDR_PHY_DTCR0_DTDSTP_DEFVAL +#undef DDR_PHY_DTCR0_DTDSTP_SHIFT +#undef DDR_PHY_DTCR0_DTDSTP_MASK +#define DDR_PHY_DTCR0_DTDSTP_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDSTP_SHIFT 21 +#define DDR_PHY_DTCR0_DTDSTP_MASK 0x00200000U + +/* +* Data Training Debug Enable +*/ +#undef DDR_PHY_DTCR0_DTDEN_DEFVAL +#undef DDR_PHY_DTCR0_DTDEN_SHIFT +#undef DDR_PHY_DTCR0_DTDEN_MASK +#define DDR_PHY_DTCR0_DTDEN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDEN_SHIFT 20 +#define DDR_PHY_DTCR0_DTDEN_MASK 0x00100000U + +/* +* Data Training Debug Byte Select +*/ +#undef DDR_PHY_DTCR0_DTDBS_DEFVAL +#undef DDR_PHY_DTCR0_DTDBS_SHIFT +#undef DDR_PHY_DTCR0_DTDBS_MASK +#define DDR_PHY_DTCR0_DTDBS_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDBS_SHIFT 16 +#define DDR_PHY_DTCR0_DTDBS_MASK 0x000F0000U + +/* +* Data Training read DBI deskewing configuration +*/ +#undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL +#undef DDR_PHY_DTCR0_DTRDBITR_SHIFT +#undef DDR_PHY_DTCR0_DTRDBITR_MASK +#define DDR_PHY_DTCR0_DTRDBITR_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTRDBITR_SHIFT 14 +#define DDR_PHY_DTCR0_DTRDBITR_MASK 0x0000C000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL +#undef DDR_PHY_DTCR0_RESERVED_13_SHIFT +#undef DDR_PHY_DTCR0_RESERVED_13_MASK +#define DDR_PHY_DTCR0_RESERVED_13_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_13_SHIFT 13 +#define DDR_PHY_DTCR0_RESERVED_13_MASK 0x00002000U + +/* +* Data Training Write Bit Deskew Data Mask +*/ +#undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL +#undef DDR_PHY_DTCR0_DTWBDDM_SHIFT +#undef DDR_PHY_DTCR0_DTWBDDM_MASK +#define DDR_PHY_DTCR0_DTWBDDM_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTWBDDM_SHIFT 12 +#define DDR_PHY_DTCR0_DTWBDDM_MASK 0x00001000U + +/* +* Refreshes Issued During Entry to Training +*/ +#undef DDR_PHY_DTCR0_RFSHEN_DEFVAL +#undef DDR_PHY_DTCR0_RFSHEN_SHIFT +#undef DDR_PHY_DTCR0_RFSHEN_MASK +#define DDR_PHY_DTCR0_RFSHEN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RFSHEN_SHIFT 8 +#define DDR_PHY_DTCR0_RFSHEN_MASK 0x00000F00U + +/* +* Data Training Compare Data +*/ +#undef DDR_PHY_DTCR0_DTCMPD_DEFVAL +#undef DDR_PHY_DTCR0_DTCMPD_SHIFT +#undef DDR_PHY_DTCR0_DTCMPD_MASK +#define DDR_PHY_DTCR0_DTCMPD_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTCMPD_SHIFT 7 +#define DDR_PHY_DTCR0_DTCMPD_MASK 0x00000080U + +/* +* Data Training Using MPR +*/ +#undef DDR_PHY_DTCR0_DTMPR_DEFVAL +#undef DDR_PHY_DTCR0_DTMPR_SHIFT +#undef DDR_PHY_DTCR0_DTMPR_MASK +#define DDR_PHY_DTCR0_DTMPR_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTMPR_SHIFT 6 +#define DDR_PHY_DTCR0_DTMPR_MASK 0x00000040U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL +#undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT +#undef DDR_PHY_DTCR0_RESERVED_5_4_MASK +#define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 4 +#define DDR_PHY_DTCR0_RESERVED_5_4_MASK 0x00000030U + +/* +* Data Training Repeat Number +*/ +#undef DDR_PHY_DTCR0_DTRPTN_DEFVAL +#undef DDR_PHY_DTCR0_DTRPTN_SHIFT +#undef DDR_PHY_DTCR0_DTRPTN_MASK +#define DDR_PHY_DTCR0_DTRPTN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTRPTN_SHIFT 0 +#define DDR_PHY_DTCR0_DTRPTN_MASK 0x0000000FU + +/* +* Rank Enable. +*/ +#undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL +#undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT +#undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK +#define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 18 +#define DDR_PHY_DTCR1_RANKEN_RSVD_MASK 0xFFFC0000U + +/* +* Rank Enable. +*/ +#undef DDR_PHY_DTCR1_RANKEN_DEFVAL +#undef DDR_PHY_DTCR1_RANKEN_SHIFT +#undef DDR_PHY_DTCR1_RANKEN_MASK +#define DDR_PHY_DTCR1_RANKEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RANKEN_SHIFT 16 +#define DDR_PHY_DTCR1_RANKEN_MASK 0x00030000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT +#undef DDR_PHY_DTCR1_RESERVED_15_14_MASK +#define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DTCR1_RESERVED_15_14_MASK 0x0000C000U + +/* +* Data Training Rank +*/ +#undef DDR_PHY_DTCR1_DTRANK_DEFVAL +#undef DDR_PHY_DTCR1_DTRANK_SHIFT +#undef DDR_PHY_DTCR1_DTRANK_MASK +#define DDR_PHY_DTCR1_DTRANK_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_DTRANK_SHIFT 12 +#define DDR_PHY_DTCR1_DTRANK_MASK 0x00003000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL +#undef DDR_PHY_DTCR1_RESERVED_11_SHIFT +#undef DDR_PHY_DTCR1_RESERVED_11_MASK +#define DDR_PHY_DTCR1_RESERVED_11_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_11_SHIFT 11 +#define DDR_PHY_DTCR1_RESERVED_11_MASK 0x00000800U + +/* +* Read Leveling Gate Sampling Difference +*/ +#undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL +#undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT +#undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK +#define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 8 +#define DDR_PHY_DTCR1_RDLVLGDIFF_MASK 0x00000700U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL +#undef DDR_PHY_DTCR1_RESERVED_7_SHIFT +#undef DDR_PHY_DTCR1_RESERVED_7_MASK +#define DDR_PHY_DTCR1_RESERVED_7_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_7_SHIFT 7 +#define DDR_PHY_DTCR1_RESERVED_7_MASK 0x00000080U + +/* +* Read Leveling Gate Shift +*/ +#undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL +#undef DDR_PHY_DTCR1_RDLVLGS_SHIFT +#undef DDR_PHY_DTCR1_RDLVLGS_MASK +#define DDR_PHY_DTCR1_RDLVLGS_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLGS_SHIFT 4 +#define DDR_PHY_DTCR1_RDLVLGS_MASK 0x00000070U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL +#undef DDR_PHY_DTCR1_RESERVED_3_SHIFT +#undef DDR_PHY_DTCR1_RESERVED_3_MASK +#define DDR_PHY_DTCR1_RESERVED_3_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_3_SHIFT 3 +#define DDR_PHY_DTCR1_RESERVED_3_MASK 0x00000008U + +/* +* Read Preamble Training enable +*/ +#undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL +#undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT +#undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK +#define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 2 +#define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 0x00000004U + +/* +* Read Leveling Enable +*/ +#undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL +#undef DDR_PHY_DTCR1_RDLVLEN_SHIFT +#undef DDR_PHY_DTCR1_RDLVLEN_MASK +#define DDR_PHY_DTCR1_RDLVLEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLEN_SHIFT 1 +#define DDR_PHY_DTCR1_RDLVLEN_MASK 0x00000002U + +/* +* Basic Gate Training Enable +*/ +#undef DDR_PHY_DTCR1_BSTEN_DEFVAL +#undef DDR_PHY_DTCR1_BSTEN_SHIFT +#undef DDR_PHY_DTCR1_BSTEN_MASK +#define DDR_PHY_DTCR1_BSTEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_BSTEN_SHIFT 0 +#define DDR_PHY_DTCR1_BSTEN_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL +#undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT +#undef DDR_PHY_CATR0_RESERVED_31_21_MASK +#define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_RESERVED_31_21_SHIFT 21 +#define DDR_PHY_CATR0_RESERVED_31_21_MASK 0xFFE00000U + +/* +* Minimum time (in terms of number of dram clocks) between two consectuve + * CA calibration command +*/ +#undef DDR_PHY_CATR0_CACD_DEFVAL +#undef DDR_PHY_CATR0_CACD_SHIFT +#undef DDR_PHY_CATR0_CACD_MASK +#define DDR_PHY_CATR0_CACD_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CACD_SHIFT 16 +#define DDR_PHY_CATR0_CACD_MASK 0x001F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL +#undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT +#undef DDR_PHY_CATR0_RESERVED_15_13_MASK +#define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_RESERVED_15_13_SHIFT 13 +#define DDR_PHY_CATR0_RESERVED_15_13_MASK 0x0000E000U + +/* +* Minimum time (in terms of number of dram clocks) PUB should wait before + * sampling the CA response after Calibration command has been sent to the + * memory +*/ +#undef DDR_PHY_CATR0_CAADR_DEFVAL +#undef DDR_PHY_CATR0_CAADR_SHIFT +#undef DDR_PHY_CATR0_CAADR_MASK +#define DDR_PHY_CATR0_CAADR_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CAADR_SHIFT 8 +#define DDR_PHY_CATR0_CAADR_MASK 0x00001F00U + +/* +* CA_1 Response Byte Lane 1 +*/ +#undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL +#undef DDR_PHY_CATR0_CA1BYTE1_SHIFT +#undef DDR_PHY_CATR0_CA1BYTE1_MASK +#define DDR_PHY_CATR0_CA1BYTE1_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CA1BYTE1_SHIFT 4 +#define DDR_PHY_CATR0_CA1BYTE1_MASK 0x000000F0U + +/* +* CA_1 Response Byte Lane 0 +*/ +#undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL +#undef DDR_PHY_CATR0_CA1BYTE0_SHIFT +#undef DDR_PHY_CATR0_CA1BYTE0_MASK +#define DDR_PHY_CATR0_CA1BYTE0_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CA1BYTE0_SHIFT 0 +#define DDR_PHY_CATR0_CA1BYTE0_MASK 0x0000000FU + +/* +* Number of delay taps by which the DQS gate LCDL will be updated when DQS + * drift is detected +*/ +#undef DDR_PHY_DQSDR0_DFTDLY_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDLY_SHIFT +#undef DDR_PHY_DQSDR0_DFTDLY_MASK +#define DDR_PHY_DQSDR0_DFTDLY_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDLY_SHIFT 28 +#define DDR_PHY_DQSDR0_DFTDLY_MASK 0xF0000000U + +/* +* Drift Impedance Update +*/ +#undef DDR_PHY_DQSDR0_DFTZQUP_DEFVAL +#undef DDR_PHY_DQSDR0_DFTZQUP_SHIFT +#undef DDR_PHY_DQSDR0_DFTZQUP_MASK +#define DDR_PHY_DQSDR0_DFTZQUP_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTZQUP_SHIFT 27 +#define DDR_PHY_DQSDR0_DFTZQUP_MASK 0x08000000U + +/* +* Drift DDL Update +*/ +#undef DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDDLUP_SHIFT +#undef DDR_PHY_DQSDR0_DFTDDLUP_MASK +#define DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDDLUP_SHIFT 26 +#define DDR_PHY_DQSDR0_DFTDDLUP_MASK 0x04000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL +#undef DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT +#undef DDR_PHY_DQSDR0_RESERVED_25_22_MASK +#define DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT 22 +#define DDR_PHY_DQSDR0_RESERVED_25_22_MASK 0x03C00000U + +/* +* Drift Read Spacing +*/ +#undef DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL +#undef DDR_PHY_DQSDR0_DFTRDSPC_SHIFT +#undef DDR_PHY_DQSDR0_DFTRDSPC_MASK +#define DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTRDSPC_SHIFT 20 +#define DDR_PHY_DQSDR0_DFTRDSPC_MASK 0x00300000U + +/* +* Drift Back-to-Back Reads +*/ +#undef DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL +#undef DDR_PHY_DQSDR0_DFTB2BRD_SHIFT +#undef DDR_PHY_DQSDR0_DFTB2BRD_MASK +#define DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTB2BRD_SHIFT 16 +#define DDR_PHY_DQSDR0_DFTB2BRD_MASK 0x000F0000U + +/* +* Drift Idle Reads +*/ +#undef DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL +#undef DDR_PHY_DQSDR0_DFTIDLRD_SHIFT +#undef DDR_PHY_DQSDR0_DFTIDLRD_MASK +#define DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTIDLRD_SHIFT 12 +#define DDR_PHY_DQSDR0_DFTIDLRD_MASK 0x0000F000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL +#undef DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT +#undef DDR_PHY_DQSDR0_RESERVED_11_8_MASK +#define DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT 8 +#define DDR_PHY_DQSDR0_RESERVED_11_8_MASK 0x00000F00U + +/* +* Gate Pulse Enable +*/ +#undef DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTGPULSE_SHIFT +#undef DDR_PHY_DQSDR0_DFTGPULSE_MASK +#define DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTGPULSE_SHIFT 4 +#define DDR_PHY_DQSDR0_DFTGPULSE_MASK 0x000000F0U + +/* +* DQS Drift Update Mode +*/ +#undef DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTUPMODE_SHIFT +#undef DDR_PHY_DQSDR0_DFTUPMODE_MASK +#define DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTUPMODE_SHIFT 2 +#define DDR_PHY_DQSDR0_DFTUPMODE_MASK 0x0000000CU + +/* +* DQS Drift Detection Mode +*/ +#undef DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDTMODE_SHIFT +#undef DDR_PHY_DQSDR0_DFTDTMODE_MASK +#define DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDTMODE_SHIFT 1 +#define DDR_PHY_DQSDR0_DFTDTMODE_MASK 0x00000002U + +/* +* DQS Drift Detection Enable +*/ +#undef DDR_PHY_DQSDR0_DFTDTEN_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDTEN_SHIFT +#undef DDR_PHY_DQSDR0_DFTDTEN_MASK +#define DDR_PHY_DQSDR0_DFTDTEN_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDTEN_SHIFT 0 +#define DDR_PHY_DQSDR0_DFTDTEN_MASK 0x00000001U + +/* +* LFSR seed for pseudo-random BIST patterns +*/ +#undef DDR_PHY_BISTLSR_SEED_DEFVAL +#undef DDR_PHY_BISTLSR_SEED_SHIFT +#undef DDR_PHY_BISTLSR_SEED_MASK +#define DDR_PHY_BISTLSR_SEED_DEFVAL +#define DDR_PHY_BISTLSR_SEED_SHIFT 0 +#define DDR_PHY_BISTLSR_SEED_MASK 0xFFFFFFFFU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL +#undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT +#undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK +#define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_RIOCR5_RESERVED_31_16_MASK 0xFFFF0000U + +/* +* Reserved. Return zeros on reads. +*/ +#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL +#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT +#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 4 +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 0x0000FFF0U + +/* +* SDRAM On-die Termination Output Enable (OE) Mode Selection. +*/ +#undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL +#undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT +#undef DDR_PHY_RIOCR5_ODTOEMODE_MASK +#define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 0 +#define DDR_PHY_RIOCR5_ODTOEMODE_MASK 0x0000000FU + +/* +* Address/Command Slew Rate (D3F I/O Only) +*/ +#undef DDR_PHY_ACIOCR0_ACSR_DEFVAL +#undef DDR_PHY_ACIOCR0_ACSR_SHIFT +#undef DDR_PHY_ACIOCR0_ACSR_MASK +#define DDR_PHY_ACIOCR0_ACSR_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACSR_SHIFT 30 +#define DDR_PHY_ACIOCR0_ACSR_MASK 0xC0000000U + +/* +* SDRAM Reset I/O Mode +*/ +#undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL +#undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT +#undef DDR_PHY_ACIOCR0_RSTIOM_MASK +#define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTIOM_SHIFT 29 +#define DDR_PHY_ACIOCR0_RSTIOM_MASK 0x20000000U + +/* +* SDRAM Reset Power Down Receiver +*/ +#undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL +#undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT +#undef DDR_PHY_ACIOCR0_RSTPDR_MASK +#define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTPDR_SHIFT 28 +#define DDR_PHY_ACIOCR0_RSTPDR_MASK 0x10000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL +#undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT +#undef DDR_PHY_ACIOCR0_RESERVED_27_MASK +#define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 27 +#define DDR_PHY_ACIOCR0_RESERVED_27_MASK 0x08000000U + +/* +* SDRAM Reset On-Die Termination +*/ +#undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL +#undef DDR_PHY_ACIOCR0_RSTODT_SHIFT +#undef DDR_PHY_ACIOCR0_RSTODT_MASK +#define DDR_PHY_ACIOCR0_RSTODT_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTODT_SHIFT 26 +#define DDR_PHY_ACIOCR0_RSTODT_MASK 0x04000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL +#undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT +#undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK +#define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 10 +#define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 0x03FFFC00U + +/* +* CK Duty Cycle Correction +*/ +#undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL +#undef DDR_PHY_ACIOCR0_CKDCC_SHIFT +#undef DDR_PHY_ACIOCR0_CKDCC_MASK +#define DDR_PHY_ACIOCR0_CKDCC_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_CKDCC_SHIFT 6 +#define DDR_PHY_ACIOCR0_CKDCC_MASK 0x000003C0U + +/* +* AC Power Down Receiver Mode +*/ +#undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL +#undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT +#undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK +#define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 4 +#define DDR_PHY_ACIOCR0_ACPDRMODE_MASK 0x00000030U + +/* +* AC On-die Termination Mode +*/ +#undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL +#undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT +#undef DDR_PHY_ACIOCR0_ACODTMODE_MASK +#define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 2 +#define DDR_PHY_ACIOCR0_ACODTMODE_MASK 0x0000000CU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL +#undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT +#undef DDR_PHY_ACIOCR0_RESERVED_1_MASK +#define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 1 +#define DDR_PHY_ACIOCR0_RESERVED_1_MASK 0x00000002U + +/* +* Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. +*/ +#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL +#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT +#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 0 +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 0x00000001U + +/* +* Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL + * slice +*/ +#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL +#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT +#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 31 +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 0x80000000U + +/* +* Clock gating for Output Enable D slices [0] +*/ +#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL +#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT +#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 30 +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 0x40000000U + +/* +* Clock gating for Power Down Receiver D slices [0] +*/ +#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL +#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT +#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 29 +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 0x20000000U + +/* +* Clock gating for Termination Enable D slices [0] +*/ +#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL +#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT +#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 28 +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 0x10000000U + +/* +* Clock gating for CK# D slices [1:0] +*/ +#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL +#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT +#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 26 +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 0x0C000000U + +/* +* Clock gating for CK D slices [1:0] +*/ +#undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL +#undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT +#undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK +#define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 24 +#define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 0x03000000U + +/* +* Clock gating for AC D slices [23:0] +*/ +#undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL +#undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT +#undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK +#define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 0 +#define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 0x00FFFFFFU + +/* +* SDRAM Parity Output Enable (OE) Mode Selection +*/ +#undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL +#undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT +#undef DDR_PHY_ACIOCR3_PAROEMODE_MASK +#define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 30 +#define DDR_PHY_ACIOCR3_PAROEMODE_MASK 0xC0000000U + +/* +* SDRAM Bank Group Output Enable (OE) Mode Selection +*/ +#undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL +#undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT +#undef DDR_PHY_ACIOCR3_BGOEMODE_MASK +#define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 26 +#define DDR_PHY_ACIOCR3_BGOEMODE_MASK 0x3C000000U + +/* +* SDRAM Bank Address Output Enable (OE) Mode Selection +*/ +#undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL +#undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT +#undef DDR_PHY_ACIOCR3_BAOEMODE_MASK +#define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 22 +#define DDR_PHY_ACIOCR3_BAOEMODE_MASK 0x03C00000U + +/* +* SDRAM A[17] Output Enable (OE) Mode Selection +*/ +#undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL +#undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT +#undef DDR_PHY_ACIOCR3_A17OEMODE_MASK +#define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 20 +#define DDR_PHY_ACIOCR3_A17OEMODE_MASK 0x00300000U + +/* +* SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection +*/ +#undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL +#undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT +#undef DDR_PHY_ACIOCR3_A16OEMODE_MASK +#define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 18 +#define DDR_PHY_ACIOCR3_A16OEMODE_MASK 0x000C0000U + +/* +* SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) +*/ +#undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL +#undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT +#undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK +#define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 16 +#define DDR_PHY_ACIOCR3_ACTOEMODE_MASK 0x00030000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL +#undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT +#undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK +#define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 8 +#define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 0x0000FF00U + +/* +* Reserved. Return zeros on reads. +*/ +#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL +#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT +#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 4 +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 0x000000F0U + +/* +* SDRAM CK Output Enable (OE) Mode Selection. +*/ +#undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL +#undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT +#undef DDR_PHY_ACIOCR3_CKOEMODE_MASK +#define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 0 +#define DDR_PHY_ACIOCR3_CKOEMODE_MASK 0x0000000FU + +/* +* Clock gating for AC LB slices and loopback read valid slices +*/ +#undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL +#undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT +#undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK +#define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 31 +#define DDR_PHY_ACIOCR4_LBCLKGATE_MASK 0x80000000U + +/* +* Clock gating for Output Enable D slices [1] +*/ +#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL +#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT +#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 30 +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 0x40000000U + +/* +* Clock gating for Power Down Receiver D slices [1] +*/ +#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL +#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT +#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 29 +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 0x20000000U + +/* +* Clock gating for Termination Enable D slices [1] +*/ +#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL +#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT +#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 28 +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 0x10000000U + +/* +* Clock gating for CK# D slices [3:2] +*/ +#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL +#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT +#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 26 +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 0x0C000000U + +/* +* Clock gating for CK D slices [3:2] +*/ +#undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL +#undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT +#undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK +#define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 24 +#define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 0x03000000U + +/* +* Clock gating for AC D slices [47:24] +*/ +#undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL +#undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT +#undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK +#define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 0 +#define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 0x00FFFFFFU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL +#undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT +#undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK +#define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_IOVCR0_RESERVED_31_29_MASK 0xE0000000U + +/* +* Address/command lane VREF Pad Enable +*/ +#undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT +#undef DDR_PHY_IOVCR0_ACREFPEN_MASK +#define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFPEN_SHIFT 28 +#define DDR_PHY_IOVCR0_ACREFPEN_MASK 0x10000000U + +/* +* Address/command lane Internal VREF Enable +*/ +#undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT +#undef DDR_PHY_IOVCR0_ACREFEEN_MASK +#define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFEEN_SHIFT 26 +#define DDR_PHY_IOVCR0_ACREFEEN_MASK 0x0C000000U + +/* +* Address/command lane Single-End VREF Enable +*/ +#undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT +#undef DDR_PHY_IOVCR0_ACREFSEN_MASK +#define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSEN_SHIFT 25 +#define DDR_PHY_IOVCR0_ACREFSEN_MASK 0x02000000U + +/* +* Address/command lane Internal VREF Enable +*/ +#undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT +#undef DDR_PHY_IOVCR0_ACREFIEN_MASK +#define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFIEN_SHIFT 24 +#define DDR_PHY_IOVCR0_ACREFIEN_MASK 0x01000000U + +/* +* External VREF generato REFSEL range select +*/ +#undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT +#undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK +#define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 23 +#define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 0x00800000U + +/* +* Address/command lane External VREF Select +*/ +#undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT +#undef DDR_PHY_IOVCR0_ACREFESEL_MASK +#define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFESEL_SHIFT 16 +#define DDR_PHY_IOVCR0_ACREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT +#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 15 +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 0x00008000U + +/* +* Address/command lane Single-End VREF Select +*/ +#undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL +#undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT +#undef DDR_PHY_IOVCR0_ACREFSSEL_MASK +#define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 8 +#define DDR_PHY_IOVCR0_ACREFSSEL_MASK 0x00007F00U + +/* +* Internal VREF generator REFSEL ragne select +*/ +#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL +#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT +#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 7 +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 0x00000080U + +/* +* REFSEL Control for internal AC IOs +*/ +#undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL +#undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT +#undef DDR_PHY_IOVCR0_ACVREFISEL_MASK +#define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 0 +#define DDR_PHY_IOVCR0_ACVREFISEL_MASK 0x0000007FU + +/* +* Number of ctl_clk required to meet (> 150ns) timing requirements during + * DRAM DQ VREF training +*/ +#undef DDR_PHY_VTCR0_TVREF_DEFVAL +#undef DDR_PHY_VTCR0_TVREF_SHIFT +#undef DDR_PHY_VTCR0_TVREF_MASK +#define DDR_PHY_VTCR0_TVREF_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_TVREF_SHIFT 29 +#define DDR_PHY_VTCR0_TVREF_MASK 0xE0000000U + +/* +* DRM DQ VREF training Enable +*/ +#undef DDR_PHY_VTCR0_DVEN_DEFVAL +#undef DDR_PHY_VTCR0_DVEN_SHIFT +#undef DDR_PHY_VTCR0_DVEN_MASK +#define DDR_PHY_VTCR0_DVEN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVEN_SHIFT 28 +#define DDR_PHY_VTCR0_DVEN_MASK 0x10000000U + +/* +* Per Device Addressability Enable +*/ +#undef DDR_PHY_VTCR0_PDAEN_DEFVAL +#undef DDR_PHY_VTCR0_PDAEN_SHIFT +#undef DDR_PHY_VTCR0_PDAEN_MASK +#define DDR_PHY_VTCR0_PDAEN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_PDAEN_SHIFT 27 +#define DDR_PHY_VTCR0_PDAEN_MASK 0x08000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL +#undef DDR_PHY_VTCR0_RESERVED_26_SHIFT +#undef DDR_PHY_VTCR0_RESERVED_26_MASK +#define DDR_PHY_VTCR0_RESERVED_26_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_RESERVED_26_SHIFT 26 +#define DDR_PHY_VTCR0_RESERVED_26_MASK 0x04000000U + +/* +* VREF Word Count +*/ +#undef DDR_PHY_VTCR0_VWCR_DEFVAL +#undef DDR_PHY_VTCR0_VWCR_SHIFT +#undef DDR_PHY_VTCR0_VWCR_MASK +#define DDR_PHY_VTCR0_VWCR_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_VWCR_SHIFT 22 +#define DDR_PHY_VTCR0_VWCR_MASK 0x03C00000U + +/* +* DRAM DQ VREF step size used during DRAM VREF training +*/ +#undef DDR_PHY_VTCR0_DVSS_DEFVAL +#undef DDR_PHY_VTCR0_DVSS_SHIFT +#undef DDR_PHY_VTCR0_DVSS_MASK +#define DDR_PHY_VTCR0_DVSS_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVSS_SHIFT 18 +#define DDR_PHY_VTCR0_DVSS_MASK 0x003C0000U + +/* +* Maximum VREF limit value used during DRAM VREF training +*/ +#undef DDR_PHY_VTCR0_DVMAX_DEFVAL +#undef DDR_PHY_VTCR0_DVMAX_SHIFT +#undef DDR_PHY_VTCR0_DVMAX_MASK +#define DDR_PHY_VTCR0_DVMAX_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVMAX_SHIFT 12 +#define DDR_PHY_VTCR0_DVMAX_MASK 0x0003F000U + +/* +* Minimum VREF limit value used during DRAM VREF training +*/ +#undef DDR_PHY_VTCR0_DVMIN_DEFVAL +#undef DDR_PHY_VTCR0_DVMIN_SHIFT +#undef DDR_PHY_VTCR0_DVMIN_MASK +#define DDR_PHY_VTCR0_DVMIN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVMIN_SHIFT 6 +#define DDR_PHY_VTCR0_DVMIN_MASK 0x00000FC0U + +/* +* Initial DRAM DQ VREF value used during DRAM VREF training +*/ +#undef DDR_PHY_VTCR0_DVINIT_DEFVAL +#undef DDR_PHY_VTCR0_DVINIT_SHIFT +#undef DDR_PHY_VTCR0_DVINIT_MASK +#define DDR_PHY_VTCR0_DVINIT_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVINIT_SHIFT 0 +#define DDR_PHY_VTCR0_DVINIT_MASK 0x0000003FU + +/* +* Host VREF step size used during VREF training. The register value of N i + * ndicates step size of (N+1) +*/ +#undef DDR_PHY_VTCR1_HVSS_DEFVAL +#undef DDR_PHY_VTCR1_HVSS_SHIFT +#undef DDR_PHY_VTCR1_HVSS_MASK +#define DDR_PHY_VTCR1_HVSS_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVSS_SHIFT 28 +#define DDR_PHY_VTCR1_HVSS_MASK 0xF0000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL +#undef DDR_PHY_VTCR1_RESERVED_27_SHIFT +#undef DDR_PHY_VTCR1_RESERVED_27_MASK +#define DDR_PHY_VTCR1_RESERVED_27_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_27_SHIFT 27 +#define DDR_PHY_VTCR1_RESERVED_27_MASK 0x08000000U + +/* +* Maximum VREF limit value used during DRAM VREF training. +*/ +#undef DDR_PHY_VTCR1_HVMAX_DEFVAL +#undef DDR_PHY_VTCR1_HVMAX_SHIFT +#undef DDR_PHY_VTCR1_HVMAX_MASK +#define DDR_PHY_VTCR1_HVMAX_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVMAX_SHIFT 20 +#define DDR_PHY_VTCR1_HVMAX_MASK 0x07F00000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL +#undef DDR_PHY_VTCR1_RESERVED_19_SHIFT +#undef DDR_PHY_VTCR1_RESERVED_19_MASK +#define DDR_PHY_VTCR1_RESERVED_19_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_19_SHIFT 19 +#define DDR_PHY_VTCR1_RESERVED_19_MASK 0x00080000U + +/* +* Minimum VREF limit value used during DRAM VREF training. +*/ +#undef DDR_PHY_VTCR1_HVMIN_DEFVAL +#undef DDR_PHY_VTCR1_HVMIN_SHIFT +#undef DDR_PHY_VTCR1_HVMIN_MASK +#define DDR_PHY_VTCR1_HVMIN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVMIN_SHIFT 12 +#define DDR_PHY_VTCR1_HVMIN_MASK 0x0007F000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL +#undef DDR_PHY_VTCR1_RESERVED_11_SHIFT +#undef DDR_PHY_VTCR1_RESERVED_11_MASK +#define DDR_PHY_VTCR1_RESERVED_11_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_11_SHIFT 11 +#define DDR_PHY_VTCR1_RESERVED_11_MASK 0x00000800U + +/* +* Static Host Vref Rank Value +*/ +#undef DDR_PHY_VTCR1_SHRNK_DEFVAL +#undef DDR_PHY_VTCR1_SHRNK_SHIFT +#undef DDR_PHY_VTCR1_SHRNK_MASK +#define DDR_PHY_VTCR1_SHRNK_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_SHRNK_SHIFT 9 +#define DDR_PHY_VTCR1_SHRNK_MASK 0x00000600U + +/* +* Static Host Vref Rank Enable +*/ +#undef DDR_PHY_VTCR1_SHREN_DEFVAL +#undef DDR_PHY_VTCR1_SHREN_SHIFT +#undef DDR_PHY_VTCR1_SHREN_MASK +#define DDR_PHY_VTCR1_SHREN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_SHREN_SHIFT 8 +#define DDR_PHY_VTCR1_SHREN_MASK 0x00000100U + +/* +* Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir + * ements during Host IO VREF training +*/ +#undef DDR_PHY_VTCR1_TVREFIO_DEFVAL +#undef DDR_PHY_VTCR1_TVREFIO_SHIFT +#undef DDR_PHY_VTCR1_TVREFIO_MASK +#define DDR_PHY_VTCR1_TVREFIO_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_TVREFIO_SHIFT 5 +#define DDR_PHY_VTCR1_TVREFIO_MASK 0x000000E0U + +/* +* Eye LCDL Offset value for VREF training +*/ +#undef DDR_PHY_VTCR1_EOFF_DEFVAL +#undef DDR_PHY_VTCR1_EOFF_SHIFT +#undef DDR_PHY_VTCR1_EOFF_MASK +#define DDR_PHY_VTCR1_EOFF_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_EOFF_SHIFT 3 +#define DDR_PHY_VTCR1_EOFF_MASK 0x00000018U + +/* +* Number of LCDL Eye points for which VREF training is repeated +*/ +#undef DDR_PHY_VTCR1_ENUM_DEFVAL +#undef DDR_PHY_VTCR1_ENUM_SHIFT +#undef DDR_PHY_VTCR1_ENUM_MASK +#define DDR_PHY_VTCR1_ENUM_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_ENUM_SHIFT 2 +#define DDR_PHY_VTCR1_ENUM_MASK 0x00000004U + +/* +* HOST (IO) internal VREF training Enable +*/ +#undef DDR_PHY_VTCR1_HVEN_DEFVAL +#undef DDR_PHY_VTCR1_HVEN_SHIFT +#undef DDR_PHY_VTCR1_HVEN_MASK +#define DDR_PHY_VTCR1_HVEN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVEN_SHIFT 1 +#define DDR_PHY_VTCR1_HVEN_MASK 0x00000002U + +/* +* Host IO Type Control +*/ +#undef DDR_PHY_VTCR1_HVIO_DEFVAL +#undef DDR_PHY_VTCR1_HVIO_SHIFT +#undef DDR_PHY_VTCR1_HVIO_MASK +#define DDR_PHY_VTCR1_HVIO_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVIO_SHIFT 0 +#define DDR_PHY_VTCR1_HVIO_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL +#undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT +#undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK +#define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 0xC0000000U + +/* +* Delay select for the BDL on Parity. +*/ +#undef DDR_PHY_ACBDLR1_PARBD_DEFVAL +#undef DDR_PHY_ACBDLR1_PARBD_SHIFT +#undef DDR_PHY_ACBDLR1_PARBD_MASK +#define DDR_PHY_ACBDLR1_PARBD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_PARBD_SHIFT 24 +#define DDR_PHY_ACBDLR1_PARBD_MASK 0x3F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL +#undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT +#undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK +#define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 0x00C00000U + +/* +* Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn + * ected to WE. +*/ +#undef DDR_PHY_ACBDLR1_A16BD_DEFVAL +#undef DDR_PHY_ACBDLR1_A16BD_SHIFT +#undef DDR_PHY_ACBDLR1_A16BD_MASK +#define DDR_PHY_ACBDLR1_A16BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_A16BD_SHIFT 16 +#define DDR_PHY_ACBDLR1_A16BD_MASK 0x003F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL +#undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT +#undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK +#define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 0x0000C000U + +/* +* Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi + * s pin is connected to CAS. +*/ +#undef DDR_PHY_ACBDLR1_A17BD_DEFVAL +#undef DDR_PHY_ACBDLR1_A17BD_SHIFT +#undef DDR_PHY_ACBDLR1_A17BD_MASK +#define DDR_PHY_ACBDLR1_A17BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_A17BD_SHIFT 8 +#define DDR_PHY_ACBDLR1_A17BD_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL +#undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT +#undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK +#define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 0x000000C0U + +/* +* Delay select for the BDL on ACTN. +*/ +#undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL +#undef DDR_PHY_ACBDLR1_ACTBD_SHIFT +#undef DDR_PHY_ACBDLR1_ACTBD_MASK +#define DDR_PHY_ACBDLR1_ACTBD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_ACTBD_SHIFT 0 +#define DDR_PHY_ACBDLR1_ACTBD_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL +#undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT +#undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK +#define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 0xC0000000U + +/* +* Delay select for the BDL on BG[1]. +*/ +#undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL +#undef DDR_PHY_ACBDLR2_BG1BD_SHIFT +#undef DDR_PHY_ACBDLR2_BG1BD_MASK +#define DDR_PHY_ACBDLR2_BG1BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BG1BD_SHIFT 24 +#define DDR_PHY_ACBDLR2_BG1BD_MASK 0x3F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL +#undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT +#undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK +#define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 0x00C00000U + +/* +* Delay select for the BDL on BG[0]. +*/ +#undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL +#undef DDR_PHY_ACBDLR2_BG0BD_SHIFT +#undef DDR_PHY_ACBDLR2_BG0BD_MASK +#define DDR_PHY_ACBDLR2_BG0BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BG0BD_SHIFT 16 +#define DDR_PHY_ACBDLR2_BG0BD_MASK 0x003F0000U + +/* +* Reser.ved Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL +#undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT +#undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK +#define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 0x0000C000U + +/* +* Delay select for the BDL on BA[1]. +*/ +#undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL +#undef DDR_PHY_ACBDLR2_BA1BD_SHIFT +#undef DDR_PHY_ACBDLR2_BA1BD_MASK +#define DDR_PHY_ACBDLR2_BA1BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BA1BD_SHIFT 8 +#define DDR_PHY_ACBDLR2_BA1BD_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL +#undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT +#undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK +#define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 0x000000C0U + +/* +* Delay select for the BDL on BA[0]. +*/ +#undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL +#undef DDR_PHY_ACBDLR2_BA0BD_SHIFT +#undef DDR_PHY_ACBDLR2_BA0BD_MASK +#define DDR_PHY_ACBDLR2_BA0BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BA0BD_SHIFT 0 +#define DDR_PHY_ACBDLR2_BA0BD_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK +#define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* Delay select for the BDL on Address A[3]. +*/ +#undef DDR_PHY_ACBDLR6_A03BD_DEFVAL +#undef DDR_PHY_ACBDLR6_A03BD_SHIFT +#undef DDR_PHY_ACBDLR6_A03BD_MASK +#define DDR_PHY_ACBDLR6_A03BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A03BD_SHIFT 24 +#define DDR_PHY_ACBDLR6_A03BD_MASK 0x3F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK +#define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* Delay select for the BDL on Address A[2]. +*/ +#undef DDR_PHY_ACBDLR6_A02BD_DEFVAL +#undef DDR_PHY_ACBDLR6_A02BD_SHIFT +#undef DDR_PHY_ACBDLR6_A02BD_MASK +#define DDR_PHY_ACBDLR6_A02BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A02BD_SHIFT 16 +#define DDR_PHY_ACBDLR6_A02BD_MASK 0x003F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK +#define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* Delay select for the BDL on Address A[1]. +*/ +#undef DDR_PHY_ACBDLR6_A01BD_DEFVAL +#undef DDR_PHY_ACBDLR6_A01BD_SHIFT +#undef DDR_PHY_ACBDLR6_A01BD_MASK +#define DDR_PHY_ACBDLR6_A01BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A01BD_SHIFT 8 +#define DDR_PHY_ACBDLR6_A01BD_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK +#define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* Delay select for the BDL on Address A[0]. +*/ +#undef DDR_PHY_ACBDLR6_A00BD_DEFVAL +#undef DDR_PHY_ACBDLR6_A00BD_SHIFT +#undef DDR_PHY_ACBDLR6_A00BD_MASK +#define DDR_PHY_ACBDLR6_A00BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A00BD_SHIFT 0 +#define DDR_PHY_ACBDLR6_A00BD_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL +#undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT +#undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK +#define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 0xC0000000U + +/* +* Delay select for the BDL on Address A[7]. +*/ +#undef DDR_PHY_ACBDLR7_A07BD_DEFVAL +#undef DDR_PHY_ACBDLR7_A07BD_SHIFT +#undef DDR_PHY_ACBDLR7_A07BD_MASK +#define DDR_PHY_ACBDLR7_A07BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A07BD_SHIFT 24 +#define DDR_PHY_ACBDLR7_A07BD_MASK 0x3F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL +#undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT +#undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK +#define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 0x00C00000U + +/* +* Delay select for the BDL on Address A[6]. +*/ +#undef DDR_PHY_ACBDLR7_A06BD_DEFVAL +#undef DDR_PHY_ACBDLR7_A06BD_SHIFT +#undef DDR_PHY_ACBDLR7_A06BD_MASK +#define DDR_PHY_ACBDLR7_A06BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A06BD_SHIFT 16 +#define DDR_PHY_ACBDLR7_A06BD_MASK 0x003F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL +#undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT +#undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK +#define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 0x0000C000U + +/* +* Delay select for the BDL on Address A[5]. +*/ +#undef DDR_PHY_ACBDLR7_A05BD_DEFVAL +#undef DDR_PHY_ACBDLR7_A05BD_SHIFT +#undef DDR_PHY_ACBDLR7_A05BD_MASK +#define DDR_PHY_ACBDLR7_A05BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A05BD_SHIFT 8 +#define DDR_PHY_ACBDLR7_A05BD_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL +#undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT +#undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK +#define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 0x000000C0U + +/* +* Delay select for the BDL on Address A[4]. +*/ +#undef DDR_PHY_ACBDLR7_A04BD_DEFVAL +#undef DDR_PHY_ACBDLR7_A04BD_SHIFT +#undef DDR_PHY_ACBDLR7_A04BD_MASK +#define DDR_PHY_ACBDLR7_A04BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A04BD_SHIFT 0 +#define DDR_PHY_ACBDLR7_A04BD_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL +#undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT +#undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK +#define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 0xC0000000U + +/* +* Delay select for the BDL on Address A[11]. +*/ +#undef DDR_PHY_ACBDLR8_A11BD_DEFVAL +#undef DDR_PHY_ACBDLR8_A11BD_SHIFT +#undef DDR_PHY_ACBDLR8_A11BD_MASK +#define DDR_PHY_ACBDLR8_A11BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A11BD_SHIFT 24 +#define DDR_PHY_ACBDLR8_A11BD_MASK 0x3F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL +#undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT +#undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK +#define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 0x00C00000U + +/* +* Delay select for the BDL on Address A[10]. +*/ +#undef DDR_PHY_ACBDLR8_A10BD_DEFVAL +#undef DDR_PHY_ACBDLR8_A10BD_SHIFT +#undef DDR_PHY_ACBDLR8_A10BD_MASK +#define DDR_PHY_ACBDLR8_A10BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A10BD_SHIFT 16 +#define DDR_PHY_ACBDLR8_A10BD_MASK 0x003F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL +#undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT +#undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK +#define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 0x0000C000U + +/* +* Delay select for the BDL on Address A[9]. +*/ +#undef DDR_PHY_ACBDLR8_A09BD_DEFVAL +#undef DDR_PHY_ACBDLR8_A09BD_SHIFT +#undef DDR_PHY_ACBDLR8_A09BD_MASK +#define DDR_PHY_ACBDLR8_A09BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A09BD_SHIFT 8 +#define DDR_PHY_ACBDLR8_A09BD_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL +#undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT +#undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK +#define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 0x000000C0U + +/* +* Delay select for the BDL on Address A[8]. +*/ +#undef DDR_PHY_ACBDLR8_A08BD_DEFVAL +#undef DDR_PHY_ACBDLR8_A08BD_SHIFT +#undef DDR_PHY_ACBDLR8_A08BD_MASK +#define DDR_PHY_ACBDLR8_A08BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A08BD_SHIFT 0 +#define DDR_PHY_ACBDLR8_A08BD_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL +#undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT +#undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK +#define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 0xC0000000U + +/* +* Delay select for the BDL on Address A[15]. +*/ +#undef DDR_PHY_ACBDLR9_A15BD_DEFVAL +#undef DDR_PHY_ACBDLR9_A15BD_SHIFT +#undef DDR_PHY_ACBDLR9_A15BD_MASK +#define DDR_PHY_ACBDLR9_A15BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A15BD_SHIFT 24 +#define DDR_PHY_ACBDLR9_A15BD_MASK 0x3F000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL +#undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT +#undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK +#define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 0x00C00000U + +/* +* Delay select for the BDL on Address A[14]. +*/ +#undef DDR_PHY_ACBDLR9_A14BD_DEFVAL +#undef DDR_PHY_ACBDLR9_A14BD_SHIFT +#undef DDR_PHY_ACBDLR9_A14BD_MASK +#define DDR_PHY_ACBDLR9_A14BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A14BD_SHIFT 16 +#define DDR_PHY_ACBDLR9_A14BD_MASK 0x003F0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL +#undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT +#undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK +#define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 0x0000C000U + +/* +* Delay select for the BDL on Address A[13]. +*/ +#undef DDR_PHY_ACBDLR9_A13BD_DEFVAL +#undef DDR_PHY_ACBDLR9_A13BD_SHIFT +#undef DDR_PHY_ACBDLR9_A13BD_MASK +#define DDR_PHY_ACBDLR9_A13BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A13BD_SHIFT 8 +#define DDR_PHY_ACBDLR9_A13BD_MASK 0x00003F00U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL +#undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT +#undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK +#define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 0x000000C0U + +/* +* Delay select for the BDL on Address A[12]. +*/ +#undef DDR_PHY_ACBDLR9_A12BD_DEFVAL +#undef DDR_PHY_ACBDLR9_A12BD_SHIFT +#undef DDR_PHY_ACBDLR9_A12BD_MASK +#define DDR_PHY_ACBDLR9_A12BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A12BD_SHIFT 0 +#define DDR_PHY_ACBDLR9_A12BD_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL +#undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT +#undef DDR_PHY_ZQCR_RESERVED_31_26_MASK +#define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQCR_RESERVED_31_26_MASK 0xFC000000U + +/* +* ZQ VREF Range +*/ +#undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL +#undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT +#undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK +#define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 25 +#define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 0x02000000U + +/* +* Programmable Wait for Frequency B +*/ +#undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL +#undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT +#undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK +#define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 19 +#define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 0x01F80000U + +/* +* Programmable Wait for Frequency A +*/ +#undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL +#undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT +#undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK +#define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 13 +#define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 0x0007E000U + +/* +* ZQ VREF Pad Enable +*/ +#undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL +#undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT +#undef DDR_PHY_ZQCR_ZQREFPEN_MASK +#define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFPEN_SHIFT 12 +#define DDR_PHY_ZQCR_ZQREFPEN_MASK 0x00001000U + +/* +* ZQ Internal VREF Enable +*/ +#undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL +#undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT +#undef DDR_PHY_ZQCR_ZQREFIEN_MASK +#define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFIEN_SHIFT 11 +#define DDR_PHY_ZQCR_ZQREFIEN_MASK 0x00000800U + +/* +* Choice of termination mode +*/ +#undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL +#undef DDR_PHY_ZQCR_ODT_MODE_SHIFT +#undef DDR_PHY_ZQCR_ODT_MODE_MASK +#define DDR_PHY_ZQCR_ODT_MODE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ODT_MODE_SHIFT 9 +#define DDR_PHY_ZQCR_ODT_MODE_MASK 0x00000600U + +/* +* Force ZCAL VT update +*/ +#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL +#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT +#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 8 +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 0x00000100U + +/* +* IO VT Drift Limit +*/ +#undef DDR_PHY_ZQCR_IODLMT_DEFVAL +#undef DDR_PHY_ZQCR_IODLMT_SHIFT +#undef DDR_PHY_ZQCR_IODLMT_MASK +#define DDR_PHY_ZQCR_IODLMT_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_IODLMT_SHIFT 5 +#define DDR_PHY_ZQCR_IODLMT_MASK 0x000000E0U + +/* +* Averaging algorithm enable, if set, enables averaging algorithm +*/ +#undef DDR_PHY_ZQCR_AVGEN_DEFVAL +#undef DDR_PHY_ZQCR_AVGEN_SHIFT +#undef DDR_PHY_ZQCR_AVGEN_MASK +#define DDR_PHY_ZQCR_AVGEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_AVGEN_SHIFT 4 +#define DDR_PHY_ZQCR_AVGEN_MASK 0x00000010U + +/* +* Maximum number of averaging rounds to be used by averaging algorithm +*/ +#undef DDR_PHY_ZQCR_AVGMAX_DEFVAL +#undef DDR_PHY_ZQCR_AVGMAX_SHIFT +#undef DDR_PHY_ZQCR_AVGMAX_MASK +#define DDR_PHY_ZQCR_AVGMAX_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_AVGMAX_SHIFT 2 +#define DDR_PHY_ZQCR_AVGMAX_MASK 0x0000000CU + +/* +* ZQ Calibration Type +*/ +#undef DDR_PHY_ZQCR_ZCALT_DEFVAL +#undef DDR_PHY_ZQCR_ZCALT_SHIFT +#undef DDR_PHY_ZQCR_ZCALT_MASK +#define DDR_PHY_ZQCR_ZCALT_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZCALT_SHIFT 1 +#define DDR_PHY_ZQCR_ZCALT_MASK 0x00000002U + +/* +* ZQ Power Down +*/ +#undef DDR_PHY_ZQCR_ZQPD_DEFVAL +#undef DDR_PHY_ZQCR_ZQPD_SHIFT +#undef DDR_PHY_ZQCR_ZQPD_MASK +#define DDR_PHY_ZQCR_ZQPD_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQPD_SHIFT 0 +#define DDR_PHY_ZQCR_ZQPD_MASK 0x00000001U + +/* +* Pull-down drive strength ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL +#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT +#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 31 +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 0x80000000U + +/* +* Pull-up drive strength ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL +#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT +#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 30 +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 0x40000000U + +/* +* Pull-down termination ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL +#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT +#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 29 +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 0x20000000U + +/* +* Pull-up termination ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL +#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT +#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 28 +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 0x10000000U + +/* +* Calibration segment bypass +*/ +#undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL +#undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT +#undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK +#define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 27 +#define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 0x08000000U + +/* +* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB +*/ +#undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL +#undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT +#undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK +#define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 25 +#define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 0x06000000U + +/* +* Termination adjustment +*/ +#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL +#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT +#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 22 +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 0x01C00000U + +/* +* Pulldown drive strength adjustment +*/ +#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL +#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT +#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 19 +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 0x00380000U + +/* +* Pullup drive strength adjustment +*/ +#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL +#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT +#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 16 +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 0x00070000U + +/* +* DRAM Impedance Divide Ratio +*/ +#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL +#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT +#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 12 +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U + +/* +* HOST Impedance Divide Ratio +*/ +#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL +#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT +#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 8 +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 0x00000F00U + +/* +* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) +*/ +#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL +#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT +#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U + +/* +* Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) +*/ +#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL +#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT +#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU + +/* +* Reserved. Return zeros on reads. +*/ +#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL +#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT +#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 0xFC000000U + +/* +* Override value for the pull-up output impedance +*/ +#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL +#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT +#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 16 +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 0x03FF0000U + +/* +* Reserved. Return zeros on reads. +*/ +#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL +#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT +#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 0x0000FC00U + +/* +* Override value for the pull-down output impedance +*/ +#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL +#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT +#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 0 +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 0x000003FFU + +/* +* Reserved. Return zeros on reads. +*/ +#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL +#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT +#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 0xFC000000U + +/* +* Override value for the pull-up termination +*/ +#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL +#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT +#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 16 +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 0x03FF0000U + +/* +* Reserved. Return zeros on reads. +*/ +#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL +#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT +#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 0x0000FC00U + +/* +* Override value for the pull-down termination +*/ +#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL +#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT +#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 0 +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 0x000003FFU + +/* +* Pull-down drive strength ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL +#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT +#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 31 +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 0x80000000U + +/* +* Pull-up drive strength ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL +#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT +#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 30 +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 0x40000000U + +/* +* Pull-down termination ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL +#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT +#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 29 +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 0x20000000U + +/* +* Pull-up termination ZCTRL over-ride enable +*/ +#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL +#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT +#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 28 +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 0x10000000U + +/* +* Calibration segment bypass +*/ +#undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL +#undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT +#undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK +#define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 27 +#define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 0x08000000U + +/* +* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB +*/ +#undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL +#undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT +#undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK +#define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 25 +#define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 0x06000000U + +/* +* Termination adjustment +*/ +#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL +#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT +#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 22 +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 0x01C00000U + +/* +* Pulldown drive strength adjustment +*/ +#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL +#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT +#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 19 +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 0x00380000U + +/* +* Pullup drive strength adjustment +*/ +#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL +#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT +#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 16 +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 0x00070000U + +/* +* DRAM Impedance Divide Ratio +*/ +#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL +#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT +#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 12 +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U + +/* +* HOST Impedance Divide Ratio +*/ +#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL +#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT +#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 8 +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 0x00000F00U + +/* +* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) +*/ +#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL +#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT +#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U + +/* +* Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) +*/ +#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL +#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT +#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX0GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX0GCR0_CALBYP_MASK +#define DDR_PHY_DX0GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX0GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX0GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX0GCR0_MDLEN_MASK +#define DDR_PHY_DX0GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX0GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX0GCR0_CODTSHFT_MASK +#define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX0GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX0GCR0_DQSDCC_MASK +#define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX0GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX0GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX0GCR0_RDDLY_MASK +#define DDR_PHY_DX0GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX0GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX0GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX0GCR0_RTTOAL_MASK +#define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX0GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX0GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX0GCR0_RTTOH_MASK +#define DDR_PHY_DX0GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX0GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX0GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX0GCR0_DQSRPD_MASK +#define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX0GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX0GCR0_DQSGPDR_MASK +#define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX0GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX0GCR0_RESERVED_4_MASK +#define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX0GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX0GCR0_DQSGODT_MASK +#define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX0GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX0GCR0_DQSGOE_MASK +#define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX0GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX0GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX0GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX0GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX0GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX0GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX0GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX0GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX0GCR1_RESERVED_15_MASK +#define DDR_PHY_DX0GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX0GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX0GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX0GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX0GCR1_QSNSEL_MASK +#define DDR_PHY_DX0GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX0GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX0GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX0GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX0GCR1_QSSEL_MASK +#define DDR_PHY_DX0GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX0GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX0GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX0GCR1_OEEN_SHIFT +#undef DDR_PHY_DX0GCR1_OEEN_MASK +#define DDR_PHY_DX0GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX0GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX0GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX0GCR1_PDREN_SHIFT +#undef DDR_PHY_DX0GCR1_PDREN_MASK +#define DDR_PHY_DX0GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX0GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX0GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX0GCR1_TEEN_SHIFT +#undef DDR_PHY_DX0GCR1_TEEN_MASK +#define DDR_PHY_DX0GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX0GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX0GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX0GCR1_DSEN_SHIFT +#undef DDR_PHY_DX0GCR1_DSEN_MASK +#define DDR_PHY_DX0GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX0GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX0GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX0GCR1_DMEN_SHIFT +#undef DDR_PHY_DX0GCR1_DMEN_MASK +#define DDR_PHY_DX0GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX0GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX0GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX0GCR1_DQEN_SHIFT +#undef DDR_PHY_DX0GCR1_DQEN_MASK +#define DDR_PHY_DX0GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX0GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX0GCR1_DQEN_MASK 0x000000FFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX0GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX0GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX0GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX0GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX0GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX0GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX0GCR3_RDBVT_MASK +#define DDR_PHY_DX0GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX0GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX0GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX0GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX0GCR3_WDBVT_MASK +#define DDR_PHY_DX0GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX0GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX0GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX0GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX0GCR3_RGLVT_MASK +#define DDR_PHY_DX0GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX0GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX0GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX0GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX0GCR3_RDLVT_MASK +#define DDR_PHY_DX0GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX0GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX0GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX0GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX0GCR3_WDLVT_MASK +#define DDR_PHY_DX0GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX0GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX0GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX0GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX0GCR3_WLLVT_MASK +#define DDR_PHY_DX0GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX0GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX0GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX0GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX0GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX0GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX0GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX0GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX0GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX0GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX0GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX0GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX0GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX0GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX0GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX0GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX0GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DMOEMODE_MASK +#define DDR_PHY_DX0GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX0GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX0GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DMTEMODE_MASK +#define DDR_PHY_DX0GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX0GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX0GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX0GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX0GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX0GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX0GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX0GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX0GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX0GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX0GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DSOEMODE_MASK +#define DDR_PHY_DX0GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX0GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX0GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DSTEMODE_MASK +#define DDR_PHY_DX0GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX0GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX0GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX0GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX0GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX0GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX0GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX0GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX0GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX0GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX0GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX0GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX0GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFPEN_MASK +#define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX0GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFEEN_MASK +#define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX0GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFSEN_MASK +#define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX0GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX0GCR4_RESERVED_24_MASK +#define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX0GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFESEL_MASK +#define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX0GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX0GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFIEN_MASK +#define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX0GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX0GCR4_DXREFIMON_MASK +#define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX0GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX0GCR5_RESERVED_31_MASK +#define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX0GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX0GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX0GCR5_RESERVED_23_MASK +#define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX0GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX0GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX0GCR5_RESERVED_15_MASK +#define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX0GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX0GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX0GCR5_RESERVED_7_MASK +#define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX0GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX0GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX1GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX1GCR0_CALBYP_MASK +#define DDR_PHY_DX1GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX1GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX1GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX1GCR0_MDLEN_MASK +#define DDR_PHY_DX1GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX1GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX1GCR0_CODTSHFT_MASK +#define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX1GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX1GCR0_DQSDCC_MASK +#define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX1GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX1GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX1GCR0_RDDLY_MASK +#define DDR_PHY_DX1GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX1GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX1GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX1GCR0_RTTOAL_MASK +#define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX1GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX1GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX1GCR0_RTTOH_MASK +#define DDR_PHY_DX1GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX1GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX1GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX1GCR0_DQSRPD_MASK +#define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX1GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX1GCR0_DQSGPDR_MASK +#define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX1GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX1GCR0_RESERVED_4_MASK +#define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX1GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX1GCR0_DQSGODT_MASK +#define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX1GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX1GCR0_DQSGOE_MASK +#define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX1GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX1GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX1GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX1GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX1GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX1GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX1GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX1GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX1GCR1_RESERVED_15_MASK +#define DDR_PHY_DX1GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX1GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX1GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX1GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX1GCR1_QSNSEL_MASK +#define DDR_PHY_DX1GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX1GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX1GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX1GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX1GCR1_QSSEL_MASK +#define DDR_PHY_DX1GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX1GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX1GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX1GCR1_OEEN_SHIFT +#undef DDR_PHY_DX1GCR1_OEEN_MASK +#define DDR_PHY_DX1GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX1GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX1GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX1GCR1_PDREN_SHIFT +#undef DDR_PHY_DX1GCR1_PDREN_MASK +#define DDR_PHY_DX1GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX1GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX1GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX1GCR1_TEEN_SHIFT +#undef DDR_PHY_DX1GCR1_TEEN_MASK +#define DDR_PHY_DX1GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX1GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX1GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX1GCR1_DSEN_SHIFT +#undef DDR_PHY_DX1GCR1_DSEN_MASK +#define DDR_PHY_DX1GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX1GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX1GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX1GCR1_DMEN_SHIFT +#undef DDR_PHY_DX1GCR1_DMEN_MASK +#define DDR_PHY_DX1GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX1GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX1GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX1GCR1_DQEN_SHIFT +#undef DDR_PHY_DX1GCR1_DQEN_MASK +#define DDR_PHY_DX1GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX1GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX1GCR1_DQEN_MASK 0x000000FFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX1GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX1GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX1GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX1GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX1GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX1GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX1GCR3_RDBVT_MASK +#define DDR_PHY_DX1GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX1GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX1GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX1GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX1GCR3_WDBVT_MASK +#define DDR_PHY_DX1GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX1GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX1GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX1GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX1GCR3_RGLVT_MASK +#define DDR_PHY_DX1GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX1GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX1GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX1GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX1GCR3_RDLVT_MASK +#define DDR_PHY_DX1GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX1GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX1GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX1GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX1GCR3_WDLVT_MASK +#define DDR_PHY_DX1GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX1GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX1GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX1GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX1GCR3_WLLVT_MASK +#define DDR_PHY_DX1GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX1GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX1GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX1GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX1GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX1GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX1GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX1GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX1GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX1GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX1GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX1GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX1GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX1GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX1GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX1GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX1GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DMOEMODE_MASK +#define DDR_PHY_DX1GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX1GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX1GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DMTEMODE_MASK +#define DDR_PHY_DX1GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX1GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX1GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX1GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX1GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX1GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX1GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX1GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX1GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX1GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX1GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DSOEMODE_MASK +#define DDR_PHY_DX1GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX1GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX1GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DSTEMODE_MASK +#define DDR_PHY_DX1GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX1GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX1GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX1GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX1GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX1GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX1GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX1GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX1GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX1GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX1GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX1GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX1GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFPEN_MASK +#define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX1GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFEEN_MASK +#define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX1GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFSEN_MASK +#define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX1GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX1GCR4_RESERVED_24_MASK +#define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX1GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFESEL_MASK +#define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX1GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX1GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFIEN_MASK +#define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX1GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX1GCR4_DXREFIMON_MASK +#define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX1GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX1GCR5_RESERVED_31_MASK +#define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX1GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX1GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX1GCR5_RESERVED_23_MASK +#define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX1GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX1GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX1GCR5_RESERVED_15_MASK +#define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX1GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX1GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX1GCR5_RESERVED_7_MASK +#define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX1GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX1GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX2GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX2GCR0_CALBYP_MASK +#define DDR_PHY_DX2GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX2GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX2GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX2GCR0_MDLEN_MASK +#define DDR_PHY_DX2GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX2GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX2GCR0_CODTSHFT_MASK +#define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX2GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX2GCR0_DQSDCC_MASK +#define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX2GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX2GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX2GCR0_RDDLY_MASK +#define DDR_PHY_DX2GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX2GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX2GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX2GCR0_RTTOAL_MASK +#define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX2GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX2GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX2GCR0_RTTOH_MASK +#define DDR_PHY_DX2GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX2GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX2GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX2GCR0_DQSRPD_MASK +#define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX2GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX2GCR0_DQSGPDR_MASK +#define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX2GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX2GCR0_RESERVED_4_MASK +#define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX2GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX2GCR0_DQSGODT_MASK +#define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX2GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX2GCR0_DQSGOE_MASK +#define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX2GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX2GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX2GCR1_RESERVED_15_MASK +#define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX2GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX2GCR1_QSNSEL_MASK +#define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX2GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX2GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX2GCR1_QSSEL_MASK +#define DDR_PHY_DX2GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX2GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX2GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX2GCR1_OEEN_SHIFT +#undef DDR_PHY_DX2GCR1_OEEN_MASK +#define DDR_PHY_DX2GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX2GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX2GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX2GCR1_PDREN_SHIFT +#undef DDR_PHY_DX2GCR1_PDREN_MASK +#define DDR_PHY_DX2GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX2GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX2GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX2GCR1_TEEN_SHIFT +#undef DDR_PHY_DX2GCR1_TEEN_MASK +#define DDR_PHY_DX2GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX2GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX2GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX2GCR1_DSEN_SHIFT +#undef DDR_PHY_DX2GCR1_DSEN_MASK +#define DDR_PHY_DX2GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX2GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX2GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX2GCR1_DMEN_SHIFT +#undef DDR_PHY_DX2GCR1_DMEN_MASK +#define DDR_PHY_DX2GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX2GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX2GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX2GCR1_DQEN_SHIFT +#undef DDR_PHY_DX2GCR1_DQEN_MASK +#define DDR_PHY_DX2GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX2GCR1_DQEN_MASK 0x000000FFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX2GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX2GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX2GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX2GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX2GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX2GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX2GCR3_RDBVT_MASK +#define DDR_PHY_DX2GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX2GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX2GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX2GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX2GCR3_WDBVT_MASK +#define DDR_PHY_DX2GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX2GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX2GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX2GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX2GCR3_RGLVT_MASK +#define DDR_PHY_DX2GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX2GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX2GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX2GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX2GCR3_RDLVT_MASK +#define DDR_PHY_DX2GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX2GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX2GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX2GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX2GCR3_WDLVT_MASK +#define DDR_PHY_DX2GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX2GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX2GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX2GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX2GCR3_WLLVT_MASK +#define DDR_PHY_DX2GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX2GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX2GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX2GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX2GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX2GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX2GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX2GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX2GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX2GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX2GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX2GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX2GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX2GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX2GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX2GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX2GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DMOEMODE_MASK +#define DDR_PHY_DX2GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX2GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX2GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DMTEMODE_MASK +#define DDR_PHY_DX2GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX2GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX2GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX2GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX2GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX2GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX2GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX2GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX2GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX2GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX2GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DSOEMODE_MASK +#define DDR_PHY_DX2GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX2GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX2GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DSTEMODE_MASK +#define DDR_PHY_DX2GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX2GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX2GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX2GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX2GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX2GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX2GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX2GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX2GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX2GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX2GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX2GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX2GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFPEN_MASK +#define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX2GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFEEN_MASK +#define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX2GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFSEN_MASK +#define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX2GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX2GCR4_RESERVED_24_MASK +#define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX2GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFESEL_MASK +#define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX2GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX2GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFIEN_MASK +#define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX2GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX2GCR4_DXREFIMON_MASK +#define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX2GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX2GCR5_RESERVED_31_MASK +#define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX2GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX2GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX2GCR5_RESERVED_23_MASK +#define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX2GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX2GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX2GCR5_RESERVED_15_MASK +#define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX2GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX2GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX2GCR5_RESERVED_7_MASK +#define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX2GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX2GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX3GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX3GCR0_CALBYP_MASK +#define DDR_PHY_DX3GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX3GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX3GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX3GCR0_MDLEN_MASK +#define DDR_PHY_DX3GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX3GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX3GCR0_CODTSHFT_MASK +#define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX3GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX3GCR0_DQSDCC_MASK +#define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX3GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX3GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX3GCR0_RDDLY_MASK +#define DDR_PHY_DX3GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX3GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX3GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX3GCR0_RTTOAL_MASK +#define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX3GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX3GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX3GCR0_RTTOH_MASK +#define DDR_PHY_DX3GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX3GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX3GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX3GCR0_DQSRPD_MASK +#define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX3GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX3GCR0_DQSGPDR_MASK +#define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX3GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX3GCR0_RESERVED_4_MASK +#define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX3GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX3GCR0_DQSGODT_MASK +#define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX3GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX3GCR0_DQSGOE_MASK +#define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX3GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX3GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX3GCR1_RESERVED_15_MASK +#define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX3GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX3GCR1_QSNSEL_MASK +#define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX3GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX3GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX3GCR1_QSSEL_MASK +#define DDR_PHY_DX3GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX3GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX3GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX3GCR1_OEEN_SHIFT +#undef DDR_PHY_DX3GCR1_OEEN_MASK +#define DDR_PHY_DX3GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX3GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX3GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX3GCR1_PDREN_SHIFT +#undef DDR_PHY_DX3GCR1_PDREN_MASK +#define DDR_PHY_DX3GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX3GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX3GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX3GCR1_TEEN_SHIFT +#undef DDR_PHY_DX3GCR1_TEEN_MASK +#define DDR_PHY_DX3GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX3GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX3GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX3GCR1_DSEN_SHIFT +#undef DDR_PHY_DX3GCR1_DSEN_MASK +#define DDR_PHY_DX3GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX3GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX3GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX3GCR1_DMEN_SHIFT +#undef DDR_PHY_DX3GCR1_DMEN_MASK +#define DDR_PHY_DX3GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX3GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX3GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX3GCR1_DQEN_SHIFT +#undef DDR_PHY_DX3GCR1_DQEN_MASK +#define DDR_PHY_DX3GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX3GCR1_DQEN_MASK 0x000000FFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX3GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX3GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX3GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX3GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX3GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX3GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX3GCR3_RDBVT_MASK +#define DDR_PHY_DX3GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX3GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX3GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX3GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX3GCR3_WDBVT_MASK +#define DDR_PHY_DX3GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX3GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX3GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX3GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX3GCR3_RGLVT_MASK +#define DDR_PHY_DX3GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX3GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX3GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX3GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX3GCR3_RDLVT_MASK +#define DDR_PHY_DX3GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX3GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX3GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX3GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX3GCR3_WDLVT_MASK +#define DDR_PHY_DX3GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX3GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX3GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX3GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX3GCR3_WLLVT_MASK +#define DDR_PHY_DX3GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX3GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX3GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX3GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX3GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX3GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX3GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX3GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX3GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX3GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX3GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX3GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX3GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX3GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX3GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX3GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX3GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DMOEMODE_MASK +#define DDR_PHY_DX3GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX3GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX3GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DMTEMODE_MASK +#define DDR_PHY_DX3GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX3GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX3GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX3GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX3GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX3GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX3GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX3GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX3GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX3GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX3GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DSOEMODE_MASK +#define DDR_PHY_DX3GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX3GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX3GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DSTEMODE_MASK +#define DDR_PHY_DX3GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX3GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX3GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX3GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX3GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX3GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX3GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX3GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX3GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX3GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX3GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX3GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX3GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFPEN_MASK +#define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX3GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFEEN_MASK +#define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX3GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFSEN_MASK +#define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX3GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX3GCR4_RESERVED_24_MASK +#define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX3GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFESEL_MASK +#define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX3GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX3GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFIEN_MASK +#define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX3GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX3GCR4_DXREFIMON_MASK +#define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX3GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX3GCR5_RESERVED_31_MASK +#define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX3GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX3GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX3GCR5_RESERVED_23_MASK +#define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX3GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX3GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX3GCR5_RESERVED_15_MASK +#define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX3GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX3GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX3GCR5_RESERVED_7_MASK +#define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX3GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX3GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX4GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX4GCR0_CALBYP_MASK +#define DDR_PHY_DX4GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX4GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX4GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX4GCR0_MDLEN_MASK +#define DDR_PHY_DX4GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX4GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX4GCR0_CODTSHFT_MASK +#define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX4GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX4GCR0_DQSDCC_MASK +#define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX4GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX4GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX4GCR0_RDDLY_MASK +#define DDR_PHY_DX4GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX4GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX4GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX4GCR0_RTTOAL_MASK +#define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX4GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX4GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX4GCR0_RTTOH_MASK +#define DDR_PHY_DX4GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX4GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX4GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX4GCR0_DQSRPD_MASK +#define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX4GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX4GCR0_DQSGPDR_MASK +#define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX4GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX4GCR0_RESERVED_4_MASK +#define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX4GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX4GCR0_DQSGODT_MASK +#define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX4GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX4GCR0_DQSGOE_MASK +#define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX4GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX4GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX4GCR1_RESERVED_15_MASK +#define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX4GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX4GCR1_QSNSEL_MASK +#define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX4GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX4GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX4GCR1_QSSEL_MASK +#define DDR_PHY_DX4GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX4GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX4GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX4GCR1_OEEN_SHIFT +#undef DDR_PHY_DX4GCR1_OEEN_MASK +#define DDR_PHY_DX4GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX4GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX4GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX4GCR1_PDREN_SHIFT +#undef DDR_PHY_DX4GCR1_PDREN_MASK +#define DDR_PHY_DX4GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX4GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX4GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX4GCR1_TEEN_SHIFT +#undef DDR_PHY_DX4GCR1_TEEN_MASK +#define DDR_PHY_DX4GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX4GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX4GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX4GCR1_DSEN_SHIFT +#undef DDR_PHY_DX4GCR1_DSEN_MASK +#define DDR_PHY_DX4GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX4GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX4GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX4GCR1_DMEN_SHIFT +#undef DDR_PHY_DX4GCR1_DMEN_MASK +#define DDR_PHY_DX4GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX4GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX4GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX4GCR1_DQEN_SHIFT +#undef DDR_PHY_DX4GCR1_DQEN_MASK +#define DDR_PHY_DX4GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX4GCR1_DQEN_MASK 0x000000FFU + +/* +* Enables the OE mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX4GCR2_DXOEMODE_DEFVAL +#undef DDR_PHY_DX4GCR2_DXOEMODE_SHIFT +#undef DDR_PHY_DX4GCR2_DXOEMODE_MASK +#define DDR_PHY_DX4GCR2_DXOEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX4GCR2_DXOEMODE_SHIFT 16 +#define DDR_PHY_DX4GCR2_DXOEMODE_MASK 0xFFFF0000U + +/* +* Enables the TE (ODT) mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX4GCR2_DXTEMODE_DEFVAL +#undef DDR_PHY_DX4GCR2_DXTEMODE_SHIFT +#undef DDR_PHY_DX4GCR2_DXTEMODE_MASK +#define DDR_PHY_DX4GCR2_DXTEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX4GCR2_DXTEMODE_SHIFT 0 +#define DDR_PHY_DX4GCR2_DXTEMODE_MASK 0x0000FFFFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX4GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX4GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX4GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX4GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX4GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX4GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX4GCR3_RDBVT_MASK +#define DDR_PHY_DX4GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX4GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX4GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX4GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX4GCR3_WDBVT_MASK +#define DDR_PHY_DX4GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX4GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX4GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX4GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX4GCR3_RGLVT_MASK +#define DDR_PHY_DX4GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX4GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX4GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX4GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX4GCR3_RDLVT_MASK +#define DDR_PHY_DX4GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX4GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX4GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX4GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX4GCR3_WDLVT_MASK +#define DDR_PHY_DX4GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX4GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX4GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX4GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX4GCR3_WLLVT_MASK +#define DDR_PHY_DX4GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX4GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX4GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX4GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX4GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX4GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX4GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX4GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX4GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX4GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX4GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX4GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX4GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX4GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX4GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX4GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX4GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DMOEMODE_MASK +#define DDR_PHY_DX4GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX4GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX4GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DMTEMODE_MASK +#define DDR_PHY_DX4GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX4GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX4GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX4GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX4GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX4GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX4GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX4GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX4GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX4GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX4GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DSOEMODE_MASK +#define DDR_PHY_DX4GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX4GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX4GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DSTEMODE_MASK +#define DDR_PHY_DX4GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX4GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX4GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX4GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX4GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX4GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX4GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX4GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX4GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX4GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX4GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX4GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX4GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFPEN_MASK +#define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX4GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFEEN_MASK +#define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX4GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFSEN_MASK +#define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX4GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX4GCR4_RESERVED_24_MASK +#define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX4GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFESEL_MASK +#define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX4GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX4GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFIEN_MASK +#define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX4GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX4GCR4_DXREFIMON_MASK +#define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX4GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX4GCR5_RESERVED_31_MASK +#define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX4GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX4GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX4GCR5_RESERVED_23_MASK +#define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX4GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX4GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX4GCR5_RESERVED_15_MASK +#define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX4GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX4GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX4GCR5_RESERVED_7_MASK +#define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX4GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX4GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX5GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX5GCR0_CALBYP_MASK +#define DDR_PHY_DX5GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX5GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX5GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX5GCR0_MDLEN_MASK +#define DDR_PHY_DX5GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX5GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX5GCR0_CODTSHFT_MASK +#define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX5GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX5GCR0_DQSDCC_MASK +#define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX5GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX5GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX5GCR0_RDDLY_MASK +#define DDR_PHY_DX5GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX5GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX5GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX5GCR0_RTTOAL_MASK +#define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX5GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX5GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX5GCR0_RTTOH_MASK +#define DDR_PHY_DX5GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX5GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX5GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX5GCR0_DQSRPD_MASK +#define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX5GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX5GCR0_DQSGPDR_MASK +#define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX5GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX5GCR0_RESERVED_4_MASK +#define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX5GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX5GCR0_DQSGODT_MASK +#define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX5GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX5GCR0_DQSGOE_MASK +#define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX5GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX5GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX5GCR1_RESERVED_15_MASK +#define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX5GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX5GCR1_QSNSEL_MASK +#define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX5GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX5GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX5GCR1_QSSEL_MASK +#define DDR_PHY_DX5GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX5GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX5GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX5GCR1_OEEN_SHIFT +#undef DDR_PHY_DX5GCR1_OEEN_MASK +#define DDR_PHY_DX5GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX5GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX5GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX5GCR1_PDREN_SHIFT +#undef DDR_PHY_DX5GCR1_PDREN_MASK +#define DDR_PHY_DX5GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX5GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX5GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX5GCR1_TEEN_SHIFT +#undef DDR_PHY_DX5GCR1_TEEN_MASK +#define DDR_PHY_DX5GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX5GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX5GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX5GCR1_DSEN_SHIFT +#undef DDR_PHY_DX5GCR1_DSEN_MASK +#define DDR_PHY_DX5GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX5GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX5GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX5GCR1_DMEN_SHIFT +#undef DDR_PHY_DX5GCR1_DMEN_MASK +#define DDR_PHY_DX5GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX5GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX5GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX5GCR1_DQEN_SHIFT +#undef DDR_PHY_DX5GCR1_DQEN_MASK +#define DDR_PHY_DX5GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX5GCR1_DQEN_MASK 0x000000FFU + +/* +* Enables the OE mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX5GCR2_DXOEMODE_DEFVAL +#undef DDR_PHY_DX5GCR2_DXOEMODE_SHIFT +#undef DDR_PHY_DX5GCR2_DXOEMODE_MASK +#define DDR_PHY_DX5GCR2_DXOEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX5GCR2_DXOEMODE_SHIFT 16 +#define DDR_PHY_DX5GCR2_DXOEMODE_MASK 0xFFFF0000U + +/* +* Enables the TE (ODT) mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX5GCR2_DXTEMODE_DEFVAL +#undef DDR_PHY_DX5GCR2_DXTEMODE_SHIFT +#undef DDR_PHY_DX5GCR2_DXTEMODE_MASK +#define DDR_PHY_DX5GCR2_DXTEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX5GCR2_DXTEMODE_SHIFT 0 +#define DDR_PHY_DX5GCR2_DXTEMODE_MASK 0x0000FFFFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX5GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX5GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX5GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX5GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX5GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX5GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX5GCR3_RDBVT_MASK +#define DDR_PHY_DX5GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX5GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX5GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX5GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX5GCR3_WDBVT_MASK +#define DDR_PHY_DX5GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX5GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX5GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX5GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX5GCR3_RGLVT_MASK +#define DDR_PHY_DX5GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX5GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX5GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX5GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX5GCR3_RDLVT_MASK +#define DDR_PHY_DX5GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX5GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX5GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX5GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX5GCR3_WDLVT_MASK +#define DDR_PHY_DX5GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX5GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX5GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX5GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX5GCR3_WLLVT_MASK +#define DDR_PHY_DX5GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX5GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX5GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX5GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX5GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX5GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX5GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX5GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX5GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX5GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX5GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX5GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX5GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX5GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX5GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX5GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX5GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DMOEMODE_MASK +#define DDR_PHY_DX5GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX5GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX5GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DMTEMODE_MASK +#define DDR_PHY_DX5GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX5GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX5GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX5GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX5GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX5GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX5GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX5GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX5GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX5GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX5GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DSOEMODE_MASK +#define DDR_PHY_DX5GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX5GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX5GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DSTEMODE_MASK +#define DDR_PHY_DX5GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX5GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX5GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX5GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX5GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX5GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX5GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX5GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX5GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX5GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX5GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX5GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX5GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFPEN_MASK +#define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX5GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFEEN_MASK +#define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX5GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFSEN_MASK +#define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX5GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX5GCR4_RESERVED_24_MASK +#define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX5GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFESEL_MASK +#define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX5GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX5GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFIEN_MASK +#define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX5GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX5GCR4_DXREFIMON_MASK +#define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX5GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX5GCR5_RESERVED_31_MASK +#define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX5GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX5GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX5GCR5_RESERVED_23_MASK +#define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX5GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX5GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX5GCR5_RESERVED_15_MASK +#define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX5GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX5GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX5GCR5_RESERVED_7_MASK +#define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX5GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX5GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX6GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX6GCR0_CALBYP_MASK +#define DDR_PHY_DX6GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX6GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX6GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX6GCR0_MDLEN_MASK +#define DDR_PHY_DX6GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX6GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX6GCR0_CODTSHFT_MASK +#define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX6GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX6GCR0_DQSDCC_MASK +#define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX6GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX6GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX6GCR0_RDDLY_MASK +#define DDR_PHY_DX6GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX6GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX6GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX6GCR0_RTTOAL_MASK +#define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX6GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX6GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX6GCR0_RTTOH_MASK +#define DDR_PHY_DX6GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX6GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX6GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX6GCR0_DQSRPD_MASK +#define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX6GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX6GCR0_DQSGPDR_MASK +#define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX6GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX6GCR0_RESERVED_4_MASK +#define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX6GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX6GCR0_DQSGODT_MASK +#define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX6GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX6GCR0_DQSGOE_MASK +#define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX6GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX6GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX6GCR1_RESERVED_15_MASK +#define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX6GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX6GCR1_QSNSEL_MASK +#define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX6GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX6GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX6GCR1_QSSEL_MASK +#define DDR_PHY_DX6GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX6GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX6GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX6GCR1_OEEN_SHIFT +#undef DDR_PHY_DX6GCR1_OEEN_MASK +#define DDR_PHY_DX6GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX6GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX6GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX6GCR1_PDREN_SHIFT +#undef DDR_PHY_DX6GCR1_PDREN_MASK +#define DDR_PHY_DX6GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX6GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX6GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX6GCR1_TEEN_SHIFT +#undef DDR_PHY_DX6GCR1_TEEN_MASK +#define DDR_PHY_DX6GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX6GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX6GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX6GCR1_DSEN_SHIFT +#undef DDR_PHY_DX6GCR1_DSEN_MASK +#define DDR_PHY_DX6GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX6GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX6GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX6GCR1_DMEN_SHIFT +#undef DDR_PHY_DX6GCR1_DMEN_MASK +#define DDR_PHY_DX6GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX6GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX6GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX6GCR1_DQEN_SHIFT +#undef DDR_PHY_DX6GCR1_DQEN_MASK +#define DDR_PHY_DX6GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX6GCR1_DQEN_MASK 0x000000FFU + +/* +* Enables the OE mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX6GCR2_DXOEMODE_DEFVAL +#undef DDR_PHY_DX6GCR2_DXOEMODE_SHIFT +#undef DDR_PHY_DX6GCR2_DXOEMODE_MASK +#define DDR_PHY_DX6GCR2_DXOEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX6GCR2_DXOEMODE_SHIFT 16 +#define DDR_PHY_DX6GCR2_DXOEMODE_MASK 0xFFFF0000U + +/* +* Enables the TE (ODT) mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX6GCR2_DXTEMODE_DEFVAL +#undef DDR_PHY_DX6GCR2_DXTEMODE_SHIFT +#undef DDR_PHY_DX6GCR2_DXTEMODE_MASK +#define DDR_PHY_DX6GCR2_DXTEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX6GCR2_DXTEMODE_SHIFT 0 +#define DDR_PHY_DX6GCR2_DXTEMODE_MASK 0x0000FFFFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX6GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX6GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX6GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX6GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX6GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX6GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX6GCR3_RDBVT_MASK +#define DDR_PHY_DX6GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX6GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX6GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX6GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX6GCR3_WDBVT_MASK +#define DDR_PHY_DX6GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX6GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX6GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX6GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX6GCR3_RGLVT_MASK +#define DDR_PHY_DX6GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX6GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX6GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX6GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX6GCR3_RDLVT_MASK +#define DDR_PHY_DX6GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX6GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX6GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX6GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX6GCR3_WDLVT_MASK +#define DDR_PHY_DX6GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX6GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX6GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX6GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX6GCR3_WLLVT_MASK +#define DDR_PHY_DX6GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX6GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX6GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX6GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX6GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX6GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX6GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX6GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX6GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX6GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX6GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX6GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX6GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX6GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX6GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX6GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX6GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DMOEMODE_MASK +#define DDR_PHY_DX6GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX6GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX6GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DMTEMODE_MASK +#define DDR_PHY_DX6GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX6GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX6GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX6GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX6GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX6GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX6GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX6GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX6GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX6GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX6GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DSOEMODE_MASK +#define DDR_PHY_DX6GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX6GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX6GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DSTEMODE_MASK +#define DDR_PHY_DX6GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX6GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX6GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX6GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX6GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX6GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX6GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX6GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX6GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX6GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX6GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX6GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX6GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFPEN_MASK +#define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX6GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFEEN_MASK +#define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX6GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFSEN_MASK +#define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX6GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX6GCR4_RESERVED_24_MASK +#define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX6GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFESEL_MASK +#define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX6GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX6GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFIEN_MASK +#define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX6GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX6GCR4_DXREFIMON_MASK +#define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX6GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX6GCR5_RESERVED_31_MASK +#define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX6GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX6GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX6GCR5_RESERVED_23_MASK +#define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX6GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX6GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX6GCR5_RESERVED_15_MASK +#define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX6GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX6GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX6GCR5_RESERVED_7_MASK +#define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX6GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX6GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX7GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX7GCR0_CALBYP_MASK +#define DDR_PHY_DX7GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX7GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX7GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX7GCR0_MDLEN_MASK +#define DDR_PHY_DX7GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX7GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX7GCR0_CODTSHFT_MASK +#define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX7GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX7GCR0_DQSDCC_MASK +#define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX7GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX7GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX7GCR0_RDDLY_MASK +#define DDR_PHY_DX7GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX7GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX7GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX7GCR0_RTTOAL_MASK +#define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX7GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX7GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX7GCR0_RTTOH_MASK +#define DDR_PHY_DX7GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX7GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX7GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX7GCR0_DQSRPD_MASK +#define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX7GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX7GCR0_DQSGPDR_MASK +#define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX7GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX7GCR0_RESERVED_4_MASK +#define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX7GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX7GCR0_DQSGODT_MASK +#define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX7GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX7GCR0_DQSGOE_MASK +#define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX7GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX7GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX7GCR1_RESERVED_15_MASK +#define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX7GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX7GCR1_QSNSEL_MASK +#define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX7GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX7GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX7GCR1_QSSEL_MASK +#define DDR_PHY_DX7GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX7GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX7GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX7GCR1_OEEN_SHIFT +#undef DDR_PHY_DX7GCR1_OEEN_MASK +#define DDR_PHY_DX7GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX7GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX7GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX7GCR1_PDREN_SHIFT +#undef DDR_PHY_DX7GCR1_PDREN_MASK +#define DDR_PHY_DX7GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX7GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX7GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX7GCR1_TEEN_SHIFT +#undef DDR_PHY_DX7GCR1_TEEN_MASK +#define DDR_PHY_DX7GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX7GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX7GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX7GCR1_DSEN_SHIFT +#undef DDR_PHY_DX7GCR1_DSEN_MASK +#define DDR_PHY_DX7GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX7GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX7GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX7GCR1_DMEN_SHIFT +#undef DDR_PHY_DX7GCR1_DMEN_MASK +#define DDR_PHY_DX7GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX7GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX7GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX7GCR1_DQEN_SHIFT +#undef DDR_PHY_DX7GCR1_DQEN_MASK +#define DDR_PHY_DX7GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX7GCR1_DQEN_MASK 0x000000FFU + +/* +* Enables the OE mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX7GCR2_DXOEMODE_DEFVAL +#undef DDR_PHY_DX7GCR2_DXOEMODE_SHIFT +#undef DDR_PHY_DX7GCR2_DXOEMODE_MASK +#define DDR_PHY_DX7GCR2_DXOEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX7GCR2_DXOEMODE_SHIFT 16 +#define DDR_PHY_DX7GCR2_DXOEMODE_MASK 0xFFFF0000U + +/* +* Enables the TE (ODT) mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX7GCR2_DXTEMODE_DEFVAL +#undef DDR_PHY_DX7GCR2_DXTEMODE_SHIFT +#undef DDR_PHY_DX7GCR2_DXTEMODE_MASK +#define DDR_PHY_DX7GCR2_DXTEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX7GCR2_DXTEMODE_SHIFT 0 +#define DDR_PHY_DX7GCR2_DXTEMODE_MASK 0x0000FFFFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX7GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX7GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX7GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX7GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX7GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX7GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX7GCR3_RDBVT_MASK +#define DDR_PHY_DX7GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX7GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX7GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX7GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX7GCR3_WDBVT_MASK +#define DDR_PHY_DX7GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX7GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX7GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX7GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX7GCR3_RGLVT_MASK +#define DDR_PHY_DX7GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX7GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX7GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX7GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX7GCR3_RDLVT_MASK +#define DDR_PHY_DX7GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX7GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX7GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX7GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX7GCR3_WDLVT_MASK +#define DDR_PHY_DX7GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX7GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX7GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX7GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX7GCR3_WLLVT_MASK +#define DDR_PHY_DX7GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX7GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX7GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX7GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX7GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX7GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX7GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX7GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX7GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX7GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX7GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX7GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX7GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX7GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX7GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX7GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX7GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DMOEMODE_MASK +#define DDR_PHY_DX7GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX7GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX7GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DMTEMODE_MASK +#define DDR_PHY_DX7GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX7GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX7GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX7GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX7GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX7GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX7GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX7GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX7GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX7GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX7GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DSOEMODE_MASK +#define DDR_PHY_DX7GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX7GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX7GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DSTEMODE_MASK +#define DDR_PHY_DX7GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX7GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX7GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX7GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX7GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX7GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX7GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX7GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX7GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX7GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX7GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX7GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX7GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFPEN_MASK +#define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX7GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFEEN_MASK +#define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX7GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFSEN_MASK +#define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX7GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX7GCR4_RESERVED_24_MASK +#define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX7GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFESEL_MASK +#define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX7GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX7GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFIEN_MASK +#define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX7GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX7GCR4_DXREFIMON_MASK +#define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX7GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX7GCR5_RESERVED_31_MASK +#define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX7GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX7GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX7GCR5_RESERVED_23_MASK +#define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX7GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX7GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX7GCR5_RESERVED_15_MASK +#define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX7GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX7GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX7GCR5_RESERVED_7_MASK +#define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX7GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX7GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Calibration Bypass +*/ +#undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL +#undef DDR_PHY_DX8GCR0_CALBYP_SHIFT +#undef DDR_PHY_DX8GCR0_CALBYP_MASK +#define DDR_PHY_DX8GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX8GCR0_CALBYP_MASK 0x80000000U + +/* +* Master Delay Line Enable +*/ +#undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL +#undef DDR_PHY_DX8GCR0_MDLEN_SHIFT +#undef DDR_PHY_DX8GCR0_MDLEN_MASK +#define DDR_PHY_DX8GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX8GCR0_MDLEN_MASK 0x40000000U + +/* +* Configurable ODT(TE) Phase Shift +*/ +#undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL +#undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT +#undef DDR_PHY_DX8GCR0_CODTSHFT_MASK +#define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX8GCR0_CODTSHFT_MASK 0x30000000U + +/* +* DQS Duty Cycle Correction +*/ +#undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL +#undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT +#undef DDR_PHY_DX8GCR0_DQSDCC_MASK +#define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX8GCR0_DQSDCC_MASK 0x0F000000U + +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ +#undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL +#undef DDR_PHY_DX8GCR0_RDDLY_SHIFT +#undef DDR_PHY_DX8GCR0_RDDLY_MASK +#define DDR_PHY_DX8GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX8GCR0_RDDLY_MASK 0x00F00000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL +#undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT +#undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK +#define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 0x000FC000U + +/* +* DQSNSE Power Down Receiver +*/ +#undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL +#undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT +#undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK +#define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 0x00002000U + +/* +* DQSSE Power Down Receiver +*/ +#undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL +#undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT +#undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK +#define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX8GCR0_DQSSEPDR_MASK 0x00001000U + +/* +* RTT On Additive Latency +*/ +#undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL +#undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT +#undef DDR_PHY_DX8GCR0_RTTOAL_MASK +#define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX8GCR0_RTTOAL_MASK 0x00000800U + +/* +* RTT Output Hold +*/ +#undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL +#undef DDR_PHY_DX8GCR0_RTTOH_SHIFT +#undef DDR_PHY_DX8GCR0_RTTOH_MASK +#define DDR_PHY_DX8GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX8GCR0_RTTOH_MASK 0x00000600U + +/* +* Configurable PDR Phase Shift +*/ +#undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL +#undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT +#undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK +#define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX8GCR0_CPDRSHFT_MASK 0x00000180U + +/* +* DQSR Power Down +*/ +#undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL +#undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT +#undef DDR_PHY_DX8GCR0_DQSRPD_MASK +#define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX8GCR0_DQSRPD_MASK 0x00000040U + +/* +* DQSG Power Down Receiver +*/ +#undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL +#undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT +#undef DDR_PHY_DX8GCR0_DQSGPDR_MASK +#define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX8GCR0_DQSGPDR_MASK 0x00000020U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL +#undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT +#undef DDR_PHY_DX8GCR0_RESERVED_4_MASK +#define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX8GCR0_RESERVED_4_MASK 0x00000010U + +/* +* DQSG On-Die Termination +*/ +#undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL +#undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT +#undef DDR_PHY_DX8GCR0_DQSGODT_MASK +#define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX8GCR0_DQSGODT_MASK 0x00000008U + +/* +* DQSG Output Enable +*/ +#undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL +#undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT +#undef DDR_PHY_DX8GCR0_DQSGOE_MASK +#define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX8GCR0_DQSGOE_MASK 0x00000004U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK +#define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 0x00000003U + +/* +* Enables the PDR mode for DQ[7:0] +*/ +#undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL +#undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT +#undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK +#define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX8GCR1_DXPDRMODE_MASK 0xFFFF0000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL +#undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT +#undef DDR_PHY_DX8GCR1_RESERVED_15_MASK +#define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX8GCR1_RESERVED_15_MASK 0x00008000U + +/* +* Select the delayed or non-delayed read data strobe # +*/ +#undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL +#undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT +#undef DDR_PHY_DX8GCR1_QSNSEL_MASK +#define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX8GCR1_QSNSEL_MASK 0x00004000U + +/* +* Select the delayed or non-delayed read data strobe +*/ +#undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL +#undef DDR_PHY_DX8GCR1_QSSEL_SHIFT +#undef DDR_PHY_DX8GCR1_QSSEL_MASK +#define DDR_PHY_DX8GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX8GCR1_QSSEL_MASK 0x00002000U + +/* +* Enables Read Data Strobe in a byte lane +*/ +#undef DDR_PHY_DX8GCR1_OEEN_DEFVAL +#undef DDR_PHY_DX8GCR1_OEEN_SHIFT +#undef DDR_PHY_DX8GCR1_OEEN_MASK +#define DDR_PHY_DX8GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX8GCR1_OEEN_MASK 0x00001000U + +/* +* Enables PDR in a byte lane +*/ +#undef DDR_PHY_DX8GCR1_PDREN_DEFVAL +#undef DDR_PHY_DX8GCR1_PDREN_SHIFT +#undef DDR_PHY_DX8GCR1_PDREN_MASK +#define DDR_PHY_DX8GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX8GCR1_PDREN_MASK 0x00000800U + +/* +* Enables ODT/TE in a byte lane +*/ +#undef DDR_PHY_DX8GCR1_TEEN_DEFVAL +#undef DDR_PHY_DX8GCR1_TEEN_SHIFT +#undef DDR_PHY_DX8GCR1_TEEN_MASK +#define DDR_PHY_DX8GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX8GCR1_TEEN_MASK 0x00000400U + +/* +* Enables Write Data strobe in a byte lane +*/ +#undef DDR_PHY_DX8GCR1_DSEN_DEFVAL +#undef DDR_PHY_DX8GCR1_DSEN_SHIFT +#undef DDR_PHY_DX8GCR1_DSEN_MASK +#define DDR_PHY_DX8GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX8GCR1_DSEN_MASK 0x00000200U + +/* +* Enables DM pin in a byte lane +*/ +#undef DDR_PHY_DX8GCR1_DMEN_DEFVAL +#undef DDR_PHY_DX8GCR1_DMEN_SHIFT +#undef DDR_PHY_DX8GCR1_DMEN_MASK +#define DDR_PHY_DX8GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX8GCR1_DMEN_MASK 0x00000100U + +/* +* Enables DQ corresponding to each bit in a byte +*/ +#undef DDR_PHY_DX8GCR1_DQEN_DEFVAL +#undef DDR_PHY_DX8GCR1_DQEN_SHIFT +#undef DDR_PHY_DX8GCR1_DQEN_MASK +#define DDR_PHY_DX8GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX8GCR1_DQEN_MASK 0x000000FFU + +/* +* Enables the OE mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX8GCR2_DXOEMODE_DEFVAL +#undef DDR_PHY_DX8GCR2_DXOEMODE_SHIFT +#undef DDR_PHY_DX8GCR2_DXOEMODE_MASK +#define DDR_PHY_DX8GCR2_DXOEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8GCR2_DXOEMODE_SHIFT 16 +#define DDR_PHY_DX8GCR2_DXOEMODE_MASK 0xFFFF0000U + +/* +* Enables the TE (ODT) mode values for DQ[7:0] +*/ +#undef DDR_PHY_DX8GCR2_DXTEMODE_DEFVAL +#undef DDR_PHY_DX8GCR2_DXTEMODE_SHIFT +#undef DDR_PHY_DX8GCR2_DXTEMODE_MASK +#define DDR_PHY_DX8GCR2_DXTEMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8GCR2_DXTEMODE_SHIFT 0 +#define DDR_PHY_DX8GCR2_DXTEMODE_MASK 0x0000FFFFU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR3_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX8GCR3_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX8GCR3_RESERVED_31_30_MASK +#define DDR_PHY_DX8GCR3_RESERVED_31_30_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8GCR3_RESERVED_31_30_MASK 0xC0000000U + +/* +* Read Data BDL VT Compensation +*/ +#undef DDR_PHY_DX8GCR3_RDBVT_DEFVAL +#undef DDR_PHY_DX8GCR3_RDBVT_SHIFT +#undef DDR_PHY_DX8GCR3_RDBVT_MASK +#define DDR_PHY_DX8GCR3_RDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_RDBVT_SHIFT 29 +#define DDR_PHY_DX8GCR3_RDBVT_MASK 0x20000000U + +/* +* Write Data BDL VT Compensation +*/ +#undef DDR_PHY_DX8GCR3_WDBVT_DEFVAL +#undef DDR_PHY_DX8GCR3_WDBVT_SHIFT +#undef DDR_PHY_DX8GCR3_WDBVT_MASK +#define DDR_PHY_DX8GCR3_WDBVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_WDBVT_SHIFT 28 +#define DDR_PHY_DX8GCR3_WDBVT_MASK 0x10000000U + +/* +* Read DQS Gating LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX8GCR3_RGLVT_DEFVAL +#undef DDR_PHY_DX8GCR3_RGLVT_SHIFT +#undef DDR_PHY_DX8GCR3_RGLVT_MASK +#define DDR_PHY_DX8GCR3_RGLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_RGLVT_SHIFT 27 +#define DDR_PHY_DX8GCR3_RGLVT_MASK 0x08000000U + +/* +* Read DQS LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX8GCR3_RDLVT_DEFVAL +#undef DDR_PHY_DX8GCR3_RDLVT_SHIFT +#undef DDR_PHY_DX8GCR3_RDLVT_MASK +#define DDR_PHY_DX8GCR3_RDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_RDLVT_SHIFT 26 +#define DDR_PHY_DX8GCR3_RDLVT_MASK 0x04000000U + +/* +* Write DQ LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX8GCR3_WDLVT_DEFVAL +#undef DDR_PHY_DX8GCR3_WDLVT_SHIFT +#undef DDR_PHY_DX8GCR3_WDLVT_MASK +#define DDR_PHY_DX8GCR3_WDLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_WDLVT_SHIFT 25 +#define DDR_PHY_DX8GCR3_WDLVT_MASK 0x02000000U + +/* +* Write Leveling LCDL Delay VT Compensation +*/ +#undef DDR_PHY_DX8GCR3_WLLVT_DEFVAL +#undef DDR_PHY_DX8GCR3_WLLVT_SHIFT +#undef DDR_PHY_DX8GCR3_WLLVT_MASK +#define DDR_PHY_DX8GCR3_WLLVT_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_WLLVT_SHIFT 24 +#define DDR_PHY_DX8GCR3_WLLVT_MASK 0x01000000U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX8GCR3_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8GCR3_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8GCR3_RESERVED_23_22_MASK +#define DDR_PHY_DX8GCR3_RESERVED_23_22_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8GCR3_RESERVED_23_22_MASK 0x00C00000U + +/* +* Enables the OE mode for DQs +*/ +#undef DDR_PHY_DX8GCR3_DSNOEMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DSNOEMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DSNOEMODE_MASK +#define DDR_PHY_DX8GCR3_DSNOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DSNOEMODE_SHIFT 20 +#define DDR_PHY_DX8GCR3_DSNOEMODE_MASK 0x00300000U + +/* +* Enables the TE mode for DQS +*/ +#undef DDR_PHY_DX8GCR3_DSNTEMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DSNTEMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DSNTEMODE_MASK +#define DDR_PHY_DX8GCR3_DSNTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DSNTEMODE_SHIFT 18 +#define DDR_PHY_DX8GCR3_DSNTEMODE_MASK 0x000C0000U + +/* +* Enables the PDR mode for DQS +*/ +#undef DDR_PHY_DX8GCR3_DSNPDRMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DSNPDRMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DSNPDRMODE_MASK +#define DDR_PHY_DX8GCR3_DSNPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DSNPDRMODE_SHIFT 16 +#define DDR_PHY_DX8GCR3_DSNPDRMODE_MASK 0x00030000U + +/* +* Enables the OE mode values for DM. +*/ +#undef DDR_PHY_DX8GCR3_DMOEMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DMOEMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DMOEMODE_MASK +#define DDR_PHY_DX8GCR3_DMOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DMOEMODE_SHIFT 14 +#define DDR_PHY_DX8GCR3_DMOEMODE_MASK 0x0000C000U + +/* +* Enables the TE mode values for DM. +*/ +#undef DDR_PHY_DX8GCR3_DMTEMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DMTEMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DMTEMODE_MASK +#define DDR_PHY_DX8GCR3_DMTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DMTEMODE_SHIFT 12 +#define DDR_PHY_DX8GCR3_DMTEMODE_MASK 0x00003000U + +/* +* Enables the PDR mode values for DM. +*/ +#undef DDR_PHY_DX8GCR3_DMPDRMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DMPDRMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DMPDRMODE_MASK +#define DDR_PHY_DX8GCR3_DMPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DMPDRMODE_SHIFT 10 +#define DDR_PHY_DX8GCR3_DMPDRMODE_MASK 0x00000C00U + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX8GCR3_RESERVED_9_8_DEFVAL +#undef DDR_PHY_DX8GCR3_RESERVED_9_8_SHIFT +#undef DDR_PHY_DX8GCR3_RESERVED_9_8_MASK +#define DDR_PHY_DX8GCR3_RESERVED_9_8_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_RESERVED_9_8_SHIFT 8 +#define DDR_PHY_DX8GCR3_RESERVED_9_8_MASK 0x00000300U + +/* +* Enables the OE mode values for DQS. +*/ +#undef DDR_PHY_DX8GCR3_DSOEMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DSOEMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DSOEMODE_MASK +#define DDR_PHY_DX8GCR3_DSOEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DSOEMODE_SHIFT 6 +#define DDR_PHY_DX8GCR3_DSOEMODE_MASK 0x000000C0U + +/* +* Enables the TE mode values for DQS. +*/ +#undef DDR_PHY_DX8GCR3_DSTEMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DSTEMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DSTEMODE_MASK +#define DDR_PHY_DX8GCR3_DSTEMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DSTEMODE_SHIFT 4 +#define DDR_PHY_DX8GCR3_DSTEMODE_MASK 0x00000030U + +/* +* Enables the PDR mode values for DQS. +*/ +#undef DDR_PHY_DX8GCR3_DSPDRMODE_DEFVAL +#undef DDR_PHY_DX8GCR3_DSPDRMODE_SHIFT +#undef DDR_PHY_DX8GCR3_DSPDRMODE_MASK +#define DDR_PHY_DX8GCR3_DSPDRMODE_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_DSPDRMODE_SHIFT 2 +#define DDR_PHY_DX8GCR3_DSPDRMODE_MASK 0x0000000CU + +/* +* Reserved. Returns zeroes on reads. +*/ +#undef DDR_PHY_DX8GCR3_RESERVED_1_0_DEFVAL +#undef DDR_PHY_DX8GCR3_RESERVED_1_0_SHIFT +#undef DDR_PHY_DX8GCR3_RESERVED_1_0_MASK +#define DDR_PHY_DX8GCR3_RESERVED_1_0_DEFVAL 0x3F000008 +#define DDR_PHY_DX8GCR3_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX8GCR3_RESERVED_1_0_MASK 0x00000003U + +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ +#undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL +#undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT +#undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK +#define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 0xE0000000U + +/* +* Byte Lane VREF Pad Enable +*/ +#undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFPEN_MASK +#define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX8GCR4_DXREFPEN_MASK 0x10000000U + +/* +* Byte Lane Internal VREF Enable +*/ +#undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFEEN_MASK +#define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX8GCR4_DXREFEEN_MASK 0x0C000000U + +/* +* Byte Lane Single-End VREF Enable +*/ +#undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFSEN_MASK +#define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX8GCR4_DXREFSEN_MASK 0x02000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL +#undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT +#undef DDR_PHY_DX8GCR4_RESERVED_24_MASK +#define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX8GCR4_RESERVED_24_MASK 0x01000000U + +/* +* External VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 0x00800000U + +/* +* Byte Lane External VREF Select +*/ +#undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFESEL_MASK +#define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX8GCR4_DXREFESEL_MASK 0x007F0000U + +/* +* Single ended VREF generator REFSEL range select +*/ +#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 0x00008000U + +/* +* Byte Lane Single-End VREF Select +*/ +#undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK +#define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX8GCR4_DXREFSSEL_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK +#define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 0x000000C0U + +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFIEN_MASK +#define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX8GCR4_DXREFIEN_MASK 0x0000003CU + +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ +#undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL +#undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT +#undef DDR_PHY_DX8GCR4_DXREFIMON_MASK +#define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX8GCR4_DXREFIMON_MASK 0x00000003U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL +#undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT +#undef DDR_PHY_DX8GCR5_RESERVED_31_MASK +#define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8GCR5_RESERVED_31_MASK 0x80000000U + +/* +* Byte Lane internal VREF Select for Rank 3 +*/ +#undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL +#undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT +#undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK +#define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX8GCR5_DXREFISELR3_MASK 0x7F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL +#undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT +#undef DDR_PHY_DX8GCR5_RESERVED_23_MASK +#define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX8GCR5_RESERVED_23_MASK 0x00800000U + +/* +* Byte Lane internal VREF Select for Rank 2 +*/ +#undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL +#undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT +#undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK +#define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX8GCR5_DXREFISELR2_MASK 0x007F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL +#undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT +#undef DDR_PHY_DX8GCR5_RESERVED_15_MASK +#define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX8GCR5_RESERVED_15_MASK 0x00008000U + +/* +* Byte Lane internal VREF Select for Rank 1 +*/ +#undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL +#undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT +#undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK +#define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX8GCR5_DXREFISELR1_MASK 0x00007F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL +#undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT +#undef DDR_PHY_DX8GCR5_RESERVED_7_MASK +#define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX8GCR5_RESERVED_7_MASK 0x00000080U + +/* +* Byte Lane internal VREF Select for Rank 0 +*/ +#undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL +#undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT +#undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK +#define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX8GCR5_DXREFISELR0_MASK 0x0000007FU + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK +#define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 0xC0000000U + +/* +* DRAM DQ VREF Select for Rank3 +*/ +#undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL +#undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT +#undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK +#define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 0x3F000000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK +#define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 0x00C00000U + +/* +* DRAM DQ VREF Select for Rank2 +*/ +#undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL +#undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT +#undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK +#define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 0x003F0000U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL +#undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT +#undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK +#define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 0x0000C000U + +/* +* DRAM DQ VREF Select for Rank1 +*/ +#undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL +#undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT +#undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK +#define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 0x00003F00U + +/* +* Reserved. Returns zeros on reads. +*/ +#undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL +#undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT +#undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK +#define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 0x000000C0U + +/* +* DRAM DQ VREF Select for Rank0 +*/ +#undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL +#undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT +#undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK +#define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 0x0000003FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 0xC0000000U + +/* +* Enable Clock Gating for DX ddr_clk +*/ +#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL +#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT +#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 0x30000000U + +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ +#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL +#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT +#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 0x0C000000U + +/* +* Enable Clock Gating for DX ctl_clk +*/ +#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL +#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT +#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 0x03000000U + +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ +#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL +#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT +#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 0x00C00000U + +/* +* Loopback Mode +*/ +#undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL +#undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT +#undef DDR_PHY_DX8SL0OSC_LBMODE_MASK +#define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL0OSC_LBMODE_MASK 0x00200000U + +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ +#undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL +#undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT +#undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK +#define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 0x00100000U + +/* +* Loopback DQS Gating +*/ +#undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL +#undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT +#undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK +#define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL0OSC_LBGDQS_MASK 0x000C0000U + +/* +* Loopback DQS Shift +*/ +#undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL +#undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT +#undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK +#define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL0OSC_LBDQSS_MASK 0x00020000U + +/* +* PHY High-Speed Reset +*/ +#undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL +#undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT +#undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK +#define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL0OSC_PHYHRST_MASK 0x00010000U + +/* +* PHY FIFO Reset +*/ +#undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL +#undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT +#undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK +#define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL0OSC_PHYFRST_MASK 0x00008000U + +/* +* Delay Line Test Start +*/ +#undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL +#undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT +#undef DDR_PHY_DX8SL0OSC_DLTST_MASK +#define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL0OSC_DLTST_MASK 0x00004000U + +/* +* Delay Line Test Mode +*/ +#undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL +#undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT +#undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK +#define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL0OSC_DLTMODE_MASK 0x00002000U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL +#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT +#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 0x00001800U + +/* +* Oscillator Mode Write-Data Delay Line Select +*/ +#undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL +#undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT +#undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK +#define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 0x00000600U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL +#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT +#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 0x00000180U + +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ +#undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL +#undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT +#undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK +#define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL0OSC_OSCWDL_MASK 0x00000060U + +/* +* Oscillator Mode Division +*/ +#undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL +#undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT +#undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK +#define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL0OSC_OSCDIV_MASK 0x0000001EU + +/* +* Oscillator Enable +*/ +#undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL +#undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT +#undef DDR_PHY_DX8SL0OSC_OSCEN_MASK +#define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL0OSC_OSCEN_MASK 0x00000001U + +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL0PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL0PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL0PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL0PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 0xFE000000U + +/* +* Read Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 0x01000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 0x00C00000U + +/* +* Write Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 0x00200000U + +/* +* DQS Gate Extension +*/ +#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 0x00180000U + +/* +* Low Power PLL Power Down +*/ +#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 0x00040000U + +/* +* Low Power I/O Power Down +*/ +#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 0x00020000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 0x00018000U + +/* +* QS Counter Enable +*/ +#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 0x00004000U + +/* +* Unused DQ I/O Mode +*/ +#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 0x00002000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 0x00001C00U + +/* +* Data Slew Rate +*/ +#undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK +#define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 0x00000300U + +/* +* DQS_N Resistor +*/ +#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 0x000000F0U + +/* +* DQS Resistor +*/ +#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL +#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT +#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 0xFF000000U + +/* +* Configurable Read Data Enable +*/ +#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 0x00800000U + +/* +* OX Extension during Post-amble +*/ +#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 0x00700000U + +/* +* OE Extension during Pre-amble +*/ +#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 0x000C0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 0x00020000U + +/* +* I/O Assisted Gate Select +*/ +#undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK +#define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 0x00010000U + +/* +* I/O Loopback Select +*/ +#undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK +#define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 0x00008000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 0x00006000U + +/* +* Low Power Wakeup Threshold +*/ +#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U + +/* +* Read Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK +#define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 0x00000100U + +/* +* Write Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK +#define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 0x00000080U + +/* +* PUB Read FIFO Bypass +*/ +#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 0x00000040U + +/* +* DATX8 Receive FIFO Read Mode +*/ +#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 0x00000030U + +/* +* Disables the Read FIFO Reset +*/ +#undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK +#define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 0x00000008U + +/* +* Read DQS Gate I/O Loopback +*/ +#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 0x00000006U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT +#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL +#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT +#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 0x80000000U + +/* +* PVREF_DAC REFSEL range select +*/ +#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL +#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT +#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 0x70000000U + +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ +#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL +#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT +#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 0x0E000000U + +/* +* DX IO Mode +*/ +#undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL +#undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT +#undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK +#define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL0IOCR_DXIOM_MASK 0x01C00000U + +/* +* DX IO Transmitter Mode +*/ +#undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL +#undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT +#undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK +#define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL0IOCR_DXTXM_MASK 0x003FF800U + +/* +* DX IO Receiver Mode +*/ +#undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL +#undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT +#undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK +#define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK 0x000007FFU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 0xC0000000U + +/* +* Enable Clock Gating for DX ddr_clk +*/ +#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL +#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT +#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 0x30000000U + +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ +#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL +#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT +#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 0x0C000000U + +/* +* Enable Clock Gating for DX ctl_clk +*/ +#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL +#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT +#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 0x03000000U + +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ +#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL +#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT +#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 0x00C00000U + +/* +* Loopback Mode +*/ +#undef DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL +#undef DDR_PHY_DX8SL1OSC_LBMODE_SHIFT +#undef DDR_PHY_DX8SL1OSC_LBMODE_MASK +#define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL1OSC_LBMODE_MASK 0x00200000U + +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ +#undef DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL +#undef DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT +#undef DDR_PHY_DX8SL1OSC_LBGSDQS_MASK +#define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 0x00100000U + +/* +* Loopback DQS Gating +*/ +#undef DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL +#undef DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT +#undef DDR_PHY_DX8SL1OSC_LBGDQS_MASK +#define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL1OSC_LBGDQS_MASK 0x000C0000U + +/* +* Loopback DQS Shift +*/ +#undef DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL +#undef DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT +#undef DDR_PHY_DX8SL1OSC_LBDQSS_MASK +#define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL1OSC_LBDQSS_MASK 0x00020000U + +/* +* PHY High-Speed Reset +*/ +#undef DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL +#undef DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT +#undef DDR_PHY_DX8SL1OSC_PHYHRST_MASK +#define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL1OSC_PHYHRST_MASK 0x00010000U + +/* +* PHY FIFO Reset +*/ +#undef DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL +#undef DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT +#undef DDR_PHY_DX8SL1OSC_PHYFRST_MASK +#define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL1OSC_PHYFRST_MASK 0x00008000U + +/* +* Delay Line Test Start +*/ +#undef DDR_PHY_DX8SL1OSC_DLTST_DEFVAL +#undef DDR_PHY_DX8SL1OSC_DLTST_SHIFT +#undef DDR_PHY_DX8SL1OSC_DLTST_MASK +#define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL1OSC_DLTST_MASK 0x00004000U + +/* +* Delay Line Test Mode +*/ +#undef DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL +#undef DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT +#undef DDR_PHY_DX8SL1OSC_DLTMODE_MASK +#define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL1OSC_DLTMODE_MASK 0x00002000U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL +#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT +#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 0x00001800U + +/* +* Oscillator Mode Write-Data Delay Line Select +*/ +#undef DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL +#undef DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT +#undef DDR_PHY_DX8SL1OSC_OSCWDDL_MASK +#define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 0x00000600U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL +#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT +#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 0x00000180U + +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ +#undef DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL +#undef DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT +#undef DDR_PHY_DX8SL1OSC_OSCWDL_MASK +#define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL1OSC_OSCWDL_MASK 0x00000060U + +/* +* Oscillator Mode Division +*/ +#undef DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL +#undef DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT +#undef DDR_PHY_DX8SL1OSC_OSCDIV_MASK +#define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL1OSC_OSCDIV_MASK 0x0000001EU + +/* +* Oscillator Enable +*/ +#undef DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL +#undef DDR_PHY_DX8SL1OSC_OSCEN_SHIFT +#undef DDR_PHY_DX8SL1OSC_OSCEN_MASK +#define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL1OSC_OSCEN_MASK 0x00000001U + +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL1PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL1PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL1PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL1PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 0xFE000000U + +/* +* Read Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 0x01000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 0x00C00000U + +/* +* Write Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 0x00200000U + +/* +* DQS Gate Extension +*/ +#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 0x00180000U + +/* +* Low Power PLL Power Down +*/ +#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 0x00040000U + +/* +* Low Power I/O Power Down +*/ +#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 0x00020000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 0x00018000U + +/* +* QS Counter Enable +*/ +#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 0x00004000U + +/* +* Unused DQ I/O Mode +*/ +#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 0x00002000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 0x00001C00U + +/* +* Data Slew Rate +*/ +#undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK +#define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 0x00000300U + +/* +* DQS_N Resistor +*/ +#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 0x000000F0U + +/* +* DQS Resistor +*/ +#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL +#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT +#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 0xFF000000U + +/* +* Configurable Read Data Enable +*/ +#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 0x00800000U + +/* +* OX Extension during Post-amble +*/ +#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 0x00700000U + +/* +* OE Extension during Pre-amble +*/ +#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 0x000C0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 0x00020000U + +/* +* I/O Assisted Gate Select +*/ +#undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK +#define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 0x00010000U + +/* +* I/O Loopback Select +*/ +#undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK +#define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 0x00008000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 0x00006000U + +/* +* Low Power Wakeup Threshold +*/ +#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U + +/* +* Read Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK +#define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 0x00000100U + +/* +* Write Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK +#define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 0x00000080U + +/* +* PUB Read FIFO Bypass +*/ +#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 0x00000040U + +/* +* DATX8 Receive FIFO Read Mode +*/ +#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 0x00000030U + +/* +* Disables the Read FIFO Reset +*/ +#undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK +#define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 0x00000008U + +/* +* Read DQS Gate I/O Loopback +*/ +#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 0x00000006U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT +#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL +#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT +#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 0x80000000U + +/* +* PVREF_DAC REFSEL range select +*/ +#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL +#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT +#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 0x70000000U + +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ +#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL +#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT +#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 0x0E000000U + +/* +* DX IO Mode +*/ +#undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL +#undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT +#undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK +#define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL1IOCR_DXIOM_MASK 0x01C00000U + +/* +* DX IO Transmitter Mode +*/ +#undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL +#undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT +#undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK +#define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL1IOCR_DXTXM_MASK 0x003FF800U + +/* +* DX IO Receiver Mode +*/ +#undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL +#undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT +#undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK +#define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK 0x000007FFU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 0xC0000000U + +/* +* Enable Clock Gating for DX ddr_clk +*/ +#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL +#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT +#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 0x30000000U + +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ +#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL +#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT +#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 0x0C000000U + +/* +* Enable Clock Gating for DX ctl_clk +*/ +#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL +#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT +#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 0x03000000U + +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ +#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL +#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT +#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 0x00C00000U + +/* +* Loopback Mode +*/ +#undef DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL +#undef DDR_PHY_DX8SL2OSC_LBMODE_SHIFT +#undef DDR_PHY_DX8SL2OSC_LBMODE_MASK +#define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL2OSC_LBMODE_MASK 0x00200000U + +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ +#undef DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL +#undef DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT +#undef DDR_PHY_DX8SL2OSC_LBGSDQS_MASK +#define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 0x00100000U + +/* +* Loopback DQS Gating +*/ +#undef DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL +#undef DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT +#undef DDR_PHY_DX8SL2OSC_LBGDQS_MASK +#define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL2OSC_LBGDQS_MASK 0x000C0000U + +/* +* Loopback DQS Shift +*/ +#undef DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL +#undef DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT +#undef DDR_PHY_DX8SL2OSC_LBDQSS_MASK +#define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL2OSC_LBDQSS_MASK 0x00020000U + +/* +* PHY High-Speed Reset +*/ +#undef DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL +#undef DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT +#undef DDR_PHY_DX8SL2OSC_PHYHRST_MASK +#define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL2OSC_PHYHRST_MASK 0x00010000U + +/* +* PHY FIFO Reset +*/ +#undef DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL +#undef DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT +#undef DDR_PHY_DX8SL2OSC_PHYFRST_MASK +#define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL2OSC_PHYFRST_MASK 0x00008000U + +/* +* Delay Line Test Start +*/ +#undef DDR_PHY_DX8SL2OSC_DLTST_DEFVAL +#undef DDR_PHY_DX8SL2OSC_DLTST_SHIFT +#undef DDR_PHY_DX8SL2OSC_DLTST_MASK +#define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL2OSC_DLTST_MASK 0x00004000U + +/* +* Delay Line Test Mode +*/ +#undef DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL +#undef DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT +#undef DDR_PHY_DX8SL2OSC_DLTMODE_MASK +#define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL2OSC_DLTMODE_MASK 0x00002000U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL +#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT +#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 0x00001800U + +/* +* Oscillator Mode Write-Data Delay Line Select +*/ +#undef DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL +#undef DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT +#undef DDR_PHY_DX8SL2OSC_OSCWDDL_MASK +#define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 0x00000600U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL +#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT +#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 0x00000180U + +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ +#undef DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL +#undef DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT +#undef DDR_PHY_DX8SL2OSC_OSCWDL_MASK +#define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL2OSC_OSCWDL_MASK 0x00000060U + +/* +* Oscillator Mode Division +*/ +#undef DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL +#undef DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT +#undef DDR_PHY_DX8SL2OSC_OSCDIV_MASK +#define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL2OSC_OSCDIV_MASK 0x0000001EU + +/* +* Oscillator Enable +*/ +#undef DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL +#undef DDR_PHY_DX8SL2OSC_OSCEN_SHIFT +#undef DDR_PHY_DX8SL2OSC_OSCEN_MASK +#define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL2OSC_OSCEN_MASK 0x00000001U + +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL2PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL2PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL2PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL2PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 0xFE000000U + +/* +* Read Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 0x01000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 0x00C00000U + +/* +* Write Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 0x00200000U + +/* +* DQS Gate Extension +*/ +#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 0x00180000U + +/* +* Low Power PLL Power Down +*/ +#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 0x00040000U + +/* +* Low Power I/O Power Down +*/ +#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 0x00020000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 0x00018000U + +/* +* QS Counter Enable +*/ +#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 0x00004000U + +/* +* Unused DQ I/O Mode +*/ +#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 0x00002000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 0x00001C00U + +/* +* Data Slew Rate +*/ +#undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK +#define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 0x00000300U + +/* +* DQS_N Resistor +*/ +#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 0x000000F0U + +/* +* DQS Resistor +*/ +#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL +#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT +#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 0xFF000000U + +/* +* Configurable Read Data Enable +*/ +#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 0x00800000U + +/* +* OX Extension during Post-amble +*/ +#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 0x00700000U + +/* +* OE Extension during Pre-amble +*/ +#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 0x000C0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 0x00020000U + +/* +* I/O Assisted Gate Select +*/ +#undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK +#define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 0x00010000U + +/* +* I/O Loopback Select +*/ +#undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK +#define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 0x00008000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 0x00006000U + +/* +* Low Power Wakeup Threshold +*/ +#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U + +/* +* Read Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK +#define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 0x00000100U + +/* +* Write Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK +#define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 0x00000080U + +/* +* PUB Read FIFO Bypass +*/ +#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 0x00000040U + +/* +* DATX8 Receive FIFO Read Mode +*/ +#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 0x00000030U + +/* +* Disables the Read FIFO Reset +*/ +#undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK +#define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 0x00000008U + +/* +* Read DQS Gate I/O Loopback +*/ +#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 0x00000006U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT +#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL +#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT +#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 0x80000000U + +/* +* PVREF_DAC REFSEL range select +*/ +#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL +#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT +#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 0x70000000U + +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ +#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL +#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT +#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 0x0E000000U + +/* +* DX IO Mode +*/ +#undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL +#undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT +#undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK +#define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL2IOCR_DXIOM_MASK 0x01C00000U + +/* +* DX IO Transmitter Mode +*/ +#undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL +#undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT +#undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK +#define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL2IOCR_DXTXM_MASK 0x003FF800U + +/* +* DX IO Receiver Mode +*/ +#undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL +#undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT +#undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK +#define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK 0x000007FFU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 0xC0000000U + +/* +* Enable Clock Gating for DX ddr_clk +*/ +#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL +#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT +#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 0x30000000U + +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ +#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL +#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT +#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 0x0C000000U + +/* +* Enable Clock Gating for DX ctl_clk +*/ +#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL +#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT +#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 0x03000000U + +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ +#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL +#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT +#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 0x00C00000U + +/* +* Loopback Mode +*/ +#undef DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL +#undef DDR_PHY_DX8SL3OSC_LBMODE_SHIFT +#undef DDR_PHY_DX8SL3OSC_LBMODE_MASK +#define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL3OSC_LBMODE_MASK 0x00200000U + +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ +#undef DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL +#undef DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT +#undef DDR_PHY_DX8SL3OSC_LBGSDQS_MASK +#define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 0x00100000U + +/* +* Loopback DQS Gating +*/ +#undef DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL +#undef DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT +#undef DDR_PHY_DX8SL3OSC_LBGDQS_MASK +#define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL3OSC_LBGDQS_MASK 0x000C0000U + +/* +* Loopback DQS Shift +*/ +#undef DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL +#undef DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT +#undef DDR_PHY_DX8SL3OSC_LBDQSS_MASK +#define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL3OSC_LBDQSS_MASK 0x00020000U + +/* +* PHY High-Speed Reset +*/ +#undef DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL +#undef DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT +#undef DDR_PHY_DX8SL3OSC_PHYHRST_MASK +#define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL3OSC_PHYHRST_MASK 0x00010000U + +/* +* PHY FIFO Reset +*/ +#undef DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL +#undef DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT +#undef DDR_PHY_DX8SL3OSC_PHYFRST_MASK +#define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL3OSC_PHYFRST_MASK 0x00008000U + +/* +* Delay Line Test Start +*/ +#undef DDR_PHY_DX8SL3OSC_DLTST_DEFVAL +#undef DDR_PHY_DX8SL3OSC_DLTST_SHIFT +#undef DDR_PHY_DX8SL3OSC_DLTST_MASK +#define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL3OSC_DLTST_MASK 0x00004000U + +/* +* Delay Line Test Mode +*/ +#undef DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL +#undef DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT +#undef DDR_PHY_DX8SL3OSC_DLTMODE_MASK +#define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL3OSC_DLTMODE_MASK 0x00002000U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL +#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT +#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 0x00001800U + +/* +* Oscillator Mode Write-Data Delay Line Select +*/ +#undef DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL +#undef DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT +#undef DDR_PHY_DX8SL3OSC_OSCWDDL_MASK +#define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 0x00000600U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL +#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT +#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 0x00000180U + +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ +#undef DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL +#undef DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT +#undef DDR_PHY_DX8SL3OSC_OSCWDL_MASK +#define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL3OSC_OSCWDL_MASK 0x00000060U + +/* +* Oscillator Mode Division +*/ +#undef DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL +#undef DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT +#undef DDR_PHY_DX8SL3OSC_OSCDIV_MASK +#define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL3OSC_OSCDIV_MASK 0x0000001EU + +/* +* Oscillator Enable +*/ +#undef DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL +#undef DDR_PHY_DX8SL3OSC_OSCEN_SHIFT +#undef DDR_PHY_DX8SL3OSC_OSCEN_MASK +#define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL3OSC_OSCEN_MASK 0x00000001U + +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL3PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL3PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL3PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL3PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 0xFE000000U + +/* +* Read Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 0x01000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 0x00C00000U + +/* +* Write Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 0x00200000U + +/* +* DQS Gate Extension +*/ +#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 0x00180000U + +/* +* Low Power PLL Power Down +*/ +#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 0x00040000U + +/* +* Low Power I/O Power Down +*/ +#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 0x00020000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 0x00018000U + +/* +* QS Counter Enable +*/ +#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 0x00004000U + +/* +* Unused DQ I/O Mode +*/ +#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 0x00002000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 0x00001C00U + +/* +* Data Slew Rate +*/ +#undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK +#define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 0x00000300U + +/* +* DQS_N Resistor +*/ +#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 0x000000F0U + +/* +* DQS Resistor +*/ +#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL +#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT +#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 0xFF000000U + +/* +* Configurable Read Data Enable +*/ +#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 0x00800000U + +/* +* OX Extension during Post-amble +*/ +#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 0x00700000U + +/* +* OE Extension during Pre-amble +*/ +#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 0x000C0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 0x00020000U + +/* +* I/O Assisted Gate Select +*/ +#undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK +#define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 0x00010000U + +/* +* I/O Loopback Select +*/ +#undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK +#define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 0x00008000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 0x00006000U + +/* +* Low Power Wakeup Threshold +*/ +#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U + +/* +* Read Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK +#define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 0x00000100U + +/* +* Write Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK +#define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 0x00000080U + +/* +* PUB Read FIFO Bypass +*/ +#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 0x00000040U + +/* +* DATX8 Receive FIFO Read Mode +*/ +#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 0x00000030U + +/* +* Disables the Read FIFO Reset +*/ +#undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK +#define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 0x00000008U + +/* +* Read DQS Gate I/O Loopback +*/ +#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 0x00000006U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT +#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL +#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT +#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 0x80000000U + +/* +* PVREF_DAC REFSEL range select +*/ +#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL +#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT +#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 0x70000000U + +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ +#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL +#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT +#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 0x0E000000U + +/* +* DX IO Mode +*/ +#undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL +#undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT +#undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK +#define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL3IOCR_DXIOM_MASK 0x01C00000U + +/* +* DX IO Transmitter Mode +*/ +#undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL +#undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT +#undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK +#define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL3IOCR_DXTXM_MASK 0x003FF800U + +/* +* DX IO Receiver Mode +*/ +#undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL +#undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT +#undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK +#define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK 0x000007FFU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL +#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT +#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 0xC0000000U + +/* +* Enable Clock Gating for DX ddr_clk +*/ +#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL +#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT +#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 0x30000000U + +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ +#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL +#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT +#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 0x0C000000U + +/* +* Enable Clock Gating for DX ctl_clk +*/ +#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL +#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT +#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 0x03000000U + +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ +#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL +#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT +#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 0x00C00000U + +/* +* Loopback Mode +*/ +#undef DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL +#undef DDR_PHY_DX8SL4OSC_LBMODE_SHIFT +#undef DDR_PHY_DX8SL4OSC_LBMODE_MASK +#define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL4OSC_LBMODE_MASK 0x00200000U + +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ +#undef DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL +#undef DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT +#undef DDR_PHY_DX8SL4OSC_LBGSDQS_MASK +#define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 0x00100000U + +/* +* Loopback DQS Gating +*/ +#undef DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL +#undef DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT +#undef DDR_PHY_DX8SL4OSC_LBGDQS_MASK +#define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL4OSC_LBGDQS_MASK 0x000C0000U + +/* +* Loopback DQS Shift +*/ +#undef DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL +#undef DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT +#undef DDR_PHY_DX8SL4OSC_LBDQSS_MASK +#define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL4OSC_LBDQSS_MASK 0x00020000U + +/* +* PHY High-Speed Reset +*/ +#undef DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL +#undef DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT +#undef DDR_PHY_DX8SL4OSC_PHYHRST_MASK +#define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL4OSC_PHYHRST_MASK 0x00010000U + +/* +* PHY FIFO Reset +*/ +#undef DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL +#undef DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT +#undef DDR_PHY_DX8SL4OSC_PHYFRST_MASK +#define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL4OSC_PHYFRST_MASK 0x00008000U + +/* +* Delay Line Test Start +*/ +#undef DDR_PHY_DX8SL4OSC_DLTST_DEFVAL +#undef DDR_PHY_DX8SL4OSC_DLTST_SHIFT +#undef DDR_PHY_DX8SL4OSC_DLTST_MASK +#define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL4OSC_DLTST_MASK 0x00004000U + +/* +* Delay Line Test Mode +*/ +#undef DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL +#undef DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT +#undef DDR_PHY_DX8SL4OSC_DLTMODE_MASK +#define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL4OSC_DLTMODE_MASK 0x00002000U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL +#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT +#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 0x00001800U + +/* +* Oscillator Mode Write-Data Delay Line Select +*/ +#undef DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL +#undef DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT +#undef DDR_PHY_DX8SL4OSC_OSCWDDL_MASK +#define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 0x00000600U + +/* +* Reserved. Caution, do not write to this register field. +*/ +#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL +#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT +#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 0x00000180U + +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ +#undef DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL +#undef DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT +#undef DDR_PHY_DX8SL4OSC_OSCWDL_MASK +#define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL4OSC_OSCWDL_MASK 0x00000060U + +/* +* Oscillator Mode Division +*/ +#undef DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL +#undef DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT +#undef DDR_PHY_DX8SL4OSC_OSCDIV_MASK +#define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL4OSC_OSCDIV_MASK 0x0000001EU + +/* +* Oscillator Enable +*/ +#undef DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL +#undef DDR_PHY_DX8SL4OSC_OSCEN_SHIFT +#undef DDR_PHY_DX8SL4OSC_OSCEN_MASK +#define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL4OSC_OSCEN_MASK 0x00000001U + +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL4PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL4PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL4PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL4PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 0xFE000000U + +/* +* Read Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 0x01000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 0x00C00000U + +/* +* Write Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 0x00200000U + +/* +* DQS Gate Extension +*/ +#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 0x00180000U + +/* +* Low Power PLL Power Down +*/ +#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 0x00040000U + +/* +* Low Power I/O Power Down +*/ +#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 0x00020000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 0x00018000U + +/* +* QS Counter Enable +*/ +#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 0x00004000U + +/* +* Unused DQ I/O Mode +*/ +#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 0x00002000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 0x00001C00U + +/* +* Data Slew Rate +*/ +#undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK +#define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 0x00000300U + +/* +* DQS_N Resistor +*/ +#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 0x000000F0U + +/* +* DQS Resistor +*/ +#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL +#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT +#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 0xFF000000U + +/* +* Configurable Read Data Enable +*/ +#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 0x00800000U + +/* +* OX Extension during Post-amble +*/ +#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 0x00700000U + +/* +* OE Extension during Pre-amble +*/ +#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 0x000C0000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 0x00020000U + +/* +* I/O Assisted Gate Select +*/ +#undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK +#define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 0x00010000U + +/* +* I/O Loopback Select +*/ +#undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK +#define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 0x00008000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 0x00006000U + +/* +* Low Power Wakeup Threshold +*/ +#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U + +/* +* Read Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK +#define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 0x00000100U + +/* +* Write Data Bus Inversion Enable +*/ +#undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK +#define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 0x00000080U + +/* +* PUB Read FIFO Bypass +*/ +#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 0x00000040U + +/* +* DATX8 Receive FIFO Read Mode +*/ +#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 0x00000030U + +/* +* Disables the Read FIFO Reset +*/ +#undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK +#define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 0x00000008U + +/* +* Read DQS Gate I/O Loopback +*/ +#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 0x00000006U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT +#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 0x00000001U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL +#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT +#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 0x80000000U + +/* +* PVREF_DAC REFSEL range select +*/ +#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL +#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT +#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 0x70000000U + +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ +#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL +#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT +#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 0x0E000000U + +/* +* DX IO Mode +*/ +#undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL +#undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT +#undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK +#define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL4IOCR_DXIOM_MASK 0x01C00000U + +/* +* DX IO Transmitter Mode +*/ +#undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL +#undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT +#undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK +#define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL4IOCR_DXTXM_MASK 0x003FF800U + +/* +* DX IO Receiver Mode +*/ +#undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL +#undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT +#undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK +#define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL4IOCR_DXRXM_MASK 0x000007FFU + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 0xFE000000U + +/* +* Read Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 0x01000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 0x00C00000U + +/* +* Write Path Rise-to-Rise Mode +*/ +#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 0x00200000U + +/* +* DQS Gate Extension +*/ +#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 0x00180000U + +/* +* Low Power PLL Power Down +*/ +#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 0x00040000U + +/* +* Low Power I/O Power Down +*/ +#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 0x00020000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 0x00018000U + +/* +* QS Counter Enable +*/ +#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 0x00004000U + +/* +* Unused DQ I/O Mode +*/ +#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 0x00002000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 0x00001C00U + +/* +* Data Slew Rate +*/ +#undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK +#define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 0x00000300U + +/* +* DQS# Resistor +*/ +#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 0x000000F0U + +/* +* DQS Resistor +*/ +#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL +#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT +#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 0x0000000FU +#undef AFIFM0_AFIFM_RDQOS_OFFSET +#define AFIFM0_AFIFM_RDQOS_OFFSET 0XFD360008 +#undef AFIFM0_AFIFM_WRQOS_OFFSET +#define AFIFM0_AFIFM_WRQOS_OFFSET 0XFD36001C +#undef AFIFM1_AFIFM_RDQOS_OFFSET +#define AFIFM1_AFIFM_RDQOS_OFFSET 0XFD370008 +#undef AFIFM1_AFIFM_WRQOS_OFFSET +#define AFIFM1_AFIFM_WRQOS_OFFSET 0XFD37001C +#undef AFIFM2_AFIFM_RDQOS_OFFSET +#define AFIFM2_AFIFM_RDQOS_OFFSET 0XFD380008 +#undef AFIFM2_AFIFM_WRQOS_OFFSET +#define AFIFM2_AFIFM_WRQOS_OFFSET 0XFD38001C +#undef AFIFM3_AFIFM_RDQOS_OFFSET +#define AFIFM3_AFIFM_RDQOS_OFFSET 0XFD390008 +#undef AFIFM3_AFIFM_WRQOS_OFFSET +#define AFIFM3_AFIFM_WRQOS_OFFSET 0XFD39001C +#undef AFIFM4_AFIFM_RDQOS_OFFSET +#define AFIFM4_AFIFM_RDQOS_OFFSET 0XFD3A0008 +#undef AFIFM4_AFIFM_WRQOS_OFFSET +#define AFIFM4_AFIFM_WRQOS_OFFSET 0XFD3A001C +#undef AFIFM5_AFIFM_RDQOS_OFFSET +#define AFIFM5_AFIFM_RDQOS_OFFSET 0XFD3B0008 +#undef AFIFM5_AFIFM_WRQOS_OFFSET +#define AFIFM5_AFIFM_WRQOS_OFFSET 0XFD3B001C +#undef AFIFM6_AFIFM_RDQOS_OFFSET +#define AFIFM6_AFIFM_RDQOS_OFFSET 0XFF9B0008 +#undef AFIFM6_AFIFM_WRQOS_OFFSET +#define AFIFM6_AFIFM_WRQOS_OFFSET 0XFF9B001C + +/* +* Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM0_AFIFM_RDQOS_VALUE_DEFVAL +#undef AFIFM0_AFIFM_RDQOS_VALUE_SHIFT +#undef AFIFM0_AFIFM_RDQOS_VALUE_MASK +#define AFIFM0_AFIFM_RDQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM0_AFIFM_RDQOS_VALUE_SHIFT 0 +#define AFIFM0_AFIFM_RDQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM0_AFIFM_WRQOS_VALUE_DEFVAL +#undef AFIFM0_AFIFM_WRQOS_VALUE_SHIFT +#undef AFIFM0_AFIFM_WRQOS_VALUE_MASK +#define AFIFM0_AFIFM_WRQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM0_AFIFM_WRQOS_VALUE_SHIFT 0 +#define AFIFM0_AFIFM_WRQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM1_AFIFM_RDQOS_VALUE_DEFVAL +#undef AFIFM1_AFIFM_RDQOS_VALUE_SHIFT +#undef AFIFM1_AFIFM_RDQOS_VALUE_MASK +#define AFIFM1_AFIFM_RDQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM1_AFIFM_RDQOS_VALUE_SHIFT 0 +#define AFIFM1_AFIFM_RDQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM1_AFIFM_WRQOS_VALUE_DEFVAL +#undef AFIFM1_AFIFM_WRQOS_VALUE_SHIFT +#undef AFIFM1_AFIFM_WRQOS_VALUE_MASK +#define AFIFM1_AFIFM_WRQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM1_AFIFM_WRQOS_VALUE_SHIFT 0 +#define AFIFM1_AFIFM_WRQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM2_AFIFM_RDQOS_VALUE_DEFVAL +#undef AFIFM2_AFIFM_RDQOS_VALUE_SHIFT +#undef AFIFM2_AFIFM_RDQOS_VALUE_MASK +#define AFIFM2_AFIFM_RDQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM2_AFIFM_RDQOS_VALUE_SHIFT 0 +#define AFIFM2_AFIFM_RDQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM2_AFIFM_WRQOS_VALUE_DEFVAL +#undef AFIFM2_AFIFM_WRQOS_VALUE_SHIFT +#undef AFIFM2_AFIFM_WRQOS_VALUE_MASK +#define AFIFM2_AFIFM_WRQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM2_AFIFM_WRQOS_VALUE_SHIFT 0 +#define AFIFM2_AFIFM_WRQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM3_AFIFM_RDQOS_VALUE_DEFVAL +#undef AFIFM3_AFIFM_RDQOS_VALUE_SHIFT +#undef AFIFM3_AFIFM_RDQOS_VALUE_MASK +#define AFIFM3_AFIFM_RDQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM3_AFIFM_RDQOS_VALUE_SHIFT 0 +#define AFIFM3_AFIFM_RDQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM3_AFIFM_WRQOS_VALUE_DEFVAL +#undef AFIFM3_AFIFM_WRQOS_VALUE_SHIFT +#undef AFIFM3_AFIFM_WRQOS_VALUE_MASK +#define AFIFM3_AFIFM_WRQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM3_AFIFM_WRQOS_VALUE_SHIFT 0 +#define AFIFM3_AFIFM_WRQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM4_AFIFM_RDQOS_VALUE_DEFVAL +#undef AFIFM4_AFIFM_RDQOS_VALUE_SHIFT +#undef AFIFM4_AFIFM_RDQOS_VALUE_MASK +#define AFIFM4_AFIFM_RDQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM4_AFIFM_RDQOS_VALUE_SHIFT 0 +#define AFIFM4_AFIFM_RDQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM4_AFIFM_WRQOS_VALUE_DEFVAL +#undef AFIFM4_AFIFM_WRQOS_VALUE_SHIFT +#undef AFIFM4_AFIFM_WRQOS_VALUE_MASK +#define AFIFM4_AFIFM_WRQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM4_AFIFM_WRQOS_VALUE_SHIFT 0 +#define AFIFM4_AFIFM_WRQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM5_AFIFM_RDQOS_VALUE_DEFVAL +#undef AFIFM5_AFIFM_RDQOS_VALUE_SHIFT +#undef AFIFM5_AFIFM_RDQOS_VALUE_MASK +#define AFIFM5_AFIFM_RDQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM5_AFIFM_RDQOS_VALUE_SHIFT 0 +#define AFIFM5_AFIFM_RDQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM5_AFIFM_WRQOS_VALUE_DEFVAL +#undef AFIFM5_AFIFM_WRQOS_VALUE_SHIFT +#undef AFIFM5_AFIFM_WRQOS_VALUE_MASK +#define AFIFM5_AFIFM_WRQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM5_AFIFM_WRQOS_VALUE_SHIFT 0 +#define AFIFM5_AFIFM_WRQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the read channel 4'b0000: + * Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM6_AFIFM_RDQOS_VALUE_DEFVAL +#undef AFIFM6_AFIFM_RDQOS_VALUE_SHIFT +#undef AFIFM6_AFIFM_RDQOS_VALUE_MASK +#define AFIFM6_AFIFM_RDQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM6_AFIFM_RDQOS_VALUE_SHIFT 0 +#define AFIFM6_AFIFM_RDQOS_VALUE_MASK 0x0000000FU + +/* +* Sets the level of the QoS field to be used for the write channel 4'b0000 + * : Lowest Priority' ' '4'b1111: Highest Priority +*/ +#undef AFIFM6_AFIFM_WRQOS_VALUE_DEFVAL +#undef AFIFM6_AFIFM_WRQOS_VALUE_SHIFT +#undef AFIFM6_AFIFM_WRQOS_VALUE_MASK +#define AFIFM6_AFIFM_WRQOS_VALUE_DEFVAL 0x00000007 +#define AFIFM6_AFIFM_WRQOS_VALUE_SHIFT 0 +#define AFIFM6_AFIFM_WRQOS_VALUE_MASK 0x0000000FU +#undef IOU_SLCR_MIO_PIN_0_OFFSET +#define IOU_SLCR_MIO_PIN_0_OFFSET 0XFF180000 +#undef IOU_SLCR_MIO_PIN_1_OFFSET +#define IOU_SLCR_MIO_PIN_1_OFFSET 0XFF180004 +#undef IOU_SLCR_MIO_PIN_2_OFFSET +#define IOU_SLCR_MIO_PIN_2_OFFSET 0XFF180008 +#undef IOU_SLCR_MIO_PIN_3_OFFSET +#define IOU_SLCR_MIO_PIN_3_OFFSET 0XFF18000C +#undef IOU_SLCR_MIO_PIN_4_OFFSET +#define IOU_SLCR_MIO_PIN_4_OFFSET 0XFF180010 +#undef IOU_SLCR_MIO_PIN_5_OFFSET +#define IOU_SLCR_MIO_PIN_5_OFFSET 0XFF180014 +#undef IOU_SLCR_MIO_PIN_6_OFFSET +#define IOU_SLCR_MIO_PIN_6_OFFSET 0XFF180018 +#undef IOU_SLCR_MIO_PIN_7_OFFSET +#define IOU_SLCR_MIO_PIN_7_OFFSET 0XFF18001C +#undef IOU_SLCR_MIO_PIN_8_OFFSET +#define IOU_SLCR_MIO_PIN_8_OFFSET 0XFF180020 +#undef IOU_SLCR_MIO_PIN_9_OFFSET +#define IOU_SLCR_MIO_PIN_9_OFFSET 0XFF180024 +#undef IOU_SLCR_MIO_PIN_10_OFFSET +#define IOU_SLCR_MIO_PIN_10_OFFSET 0XFF180028 +#undef IOU_SLCR_MIO_PIN_11_OFFSET +#define IOU_SLCR_MIO_PIN_11_OFFSET 0XFF18002C +#undef IOU_SLCR_MIO_PIN_12_OFFSET +#define IOU_SLCR_MIO_PIN_12_OFFSET 0XFF180030 +#undef IOU_SLCR_MIO_PIN_13_OFFSET +#define IOU_SLCR_MIO_PIN_13_OFFSET 0XFF180034 +#undef IOU_SLCR_MIO_PIN_14_OFFSET +#define IOU_SLCR_MIO_PIN_14_OFFSET 0XFF180038 +#undef IOU_SLCR_MIO_PIN_15_OFFSET +#define IOU_SLCR_MIO_PIN_15_OFFSET 0XFF18003C +#undef IOU_SLCR_MIO_PIN_16_OFFSET +#define IOU_SLCR_MIO_PIN_16_OFFSET 0XFF180040 +#undef IOU_SLCR_MIO_PIN_17_OFFSET +#define IOU_SLCR_MIO_PIN_17_OFFSET 0XFF180044 +#undef IOU_SLCR_MIO_PIN_18_OFFSET +#define IOU_SLCR_MIO_PIN_18_OFFSET 0XFF180048 +#undef IOU_SLCR_MIO_PIN_19_OFFSET +#define IOU_SLCR_MIO_PIN_19_OFFSET 0XFF18004C +#undef IOU_SLCR_MIO_PIN_20_OFFSET +#define IOU_SLCR_MIO_PIN_20_OFFSET 0XFF180050 +#undef IOU_SLCR_MIO_PIN_21_OFFSET +#define IOU_SLCR_MIO_PIN_21_OFFSET 0XFF180054 +#undef IOU_SLCR_MIO_PIN_22_OFFSET +#define IOU_SLCR_MIO_PIN_22_OFFSET 0XFF180058 +#undef IOU_SLCR_MIO_PIN_23_OFFSET +#define IOU_SLCR_MIO_PIN_23_OFFSET 0XFF18005C +#undef IOU_SLCR_MIO_PIN_24_OFFSET +#define IOU_SLCR_MIO_PIN_24_OFFSET 0XFF180060 +#undef IOU_SLCR_MIO_PIN_25_OFFSET +#define IOU_SLCR_MIO_PIN_25_OFFSET 0XFF180064 +#undef IOU_SLCR_MIO_PIN_26_OFFSET +#define IOU_SLCR_MIO_PIN_26_OFFSET 0XFF180068 +#undef IOU_SLCR_MIO_PIN_27_OFFSET +#define IOU_SLCR_MIO_PIN_27_OFFSET 0XFF18006C +#undef IOU_SLCR_MIO_PIN_28_OFFSET +#define IOU_SLCR_MIO_PIN_28_OFFSET 0XFF180070 +#undef IOU_SLCR_MIO_PIN_29_OFFSET +#define IOU_SLCR_MIO_PIN_29_OFFSET 0XFF180074 +#undef IOU_SLCR_MIO_PIN_30_OFFSET +#define IOU_SLCR_MIO_PIN_30_OFFSET 0XFF180078 +#undef IOU_SLCR_MIO_PIN_31_OFFSET +#define IOU_SLCR_MIO_PIN_31_OFFSET 0XFF18007C +#undef IOU_SLCR_MIO_PIN_32_OFFSET +#define IOU_SLCR_MIO_PIN_32_OFFSET 0XFF180080 +#undef IOU_SLCR_MIO_PIN_33_OFFSET +#define IOU_SLCR_MIO_PIN_33_OFFSET 0XFF180084 +#undef IOU_SLCR_MIO_PIN_38_OFFSET +#define IOU_SLCR_MIO_PIN_38_OFFSET 0XFF180098 +#undef IOU_SLCR_MIO_PIN_39_OFFSET +#define IOU_SLCR_MIO_PIN_39_OFFSET 0XFF18009C +#undef IOU_SLCR_MIO_PIN_40_OFFSET +#define IOU_SLCR_MIO_PIN_40_OFFSET 0XFF1800A0 +#undef IOU_SLCR_MIO_PIN_41_OFFSET +#define IOU_SLCR_MIO_PIN_41_OFFSET 0XFF1800A4 +#undef IOU_SLCR_MIO_PIN_42_OFFSET +#define IOU_SLCR_MIO_PIN_42_OFFSET 0XFF1800A8 +#undef IOU_SLCR_MIO_PIN_43_OFFSET +#define IOU_SLCR_MIO_PIN_43_OFFSET 0XFF1800AC +#undef IOU_SLCR_MIO_PIN_44_OFFSET +#define IOU_SLCR_MIO_PIN_44_OFFSET 0XFF1800B0 +#undef IOU_SLCR_MIO_PIN_45_OFFSET +#define IOU_SLCR_MIO_PIN_45_OFFSET 0XFF1800B4 +#undef IOU_SLCR_MIO_PIN_46_OFFSET +#define IOU_SLCR_MIO_PIN_46_OFFSET 0XFF1800B8 +#undef IOU_SLCR_MIO_PIN_47_OFFSET +#define IOU_SLCR_MIO_PIN_47_OFFSET 0XFF1800BC +#undef IOU_SLCR_MIO_PIN_48_OFFSET +#define IOU_SLCR_MIO_PIN_48_OFFSET 0XFF1800C0 +#undef IOU_SLCR_MIO_PIN_49_OFFSET +#define IOU_SLCR_MIO_PIN_49_OFFSET 0XFF1800C4 +#undef IOU_SLCR_MIO_PIN_50_OFFSET +#define IOU_SLCR_MIO_PIN_50_OFFSET 0XFF1800C8 +#undef IOU_SLCR_MIO_PIN_51_OFFSET +#define IOU_SLCR_MIO_PIN_51_OFFSET 0XFF1800CC +#undef IOU_SLCR_MIO_PIN_52_OFFSET +#define IOU_SLCR_MIO_PIN_52_OFFSET 0XFF1800D0 +#undef IOU_SLCR_MIO_PIN_53_OFFSET +#define IOU_SLCR_MIO_PIN_53_OFFSET 0XFF1800D4 +#undef IOU_SLCR_MIO_PIN_54_OFFSET +#define IOU_SLCR_MIO_PIN_54_OFFSET 0XFF1800D8 +#undef IOU_SLCR_MIO_PIN_55_OFFSET +#define IOU_SLCR_MIO_PIN_55_OFFSET 0XFF1800DC +#undef IOU_SLCR_MIO_PIN_56_OFFSET +#define IOU_SLCR_MIO_PIN_56_OFFSET 0XFF1800E0 +#undef IOU_SLCR_MIO_PIN_57_OFFSET +#define IOU_SLCR_MIO_PIN_57_OFFSET 0XFF1800E4 +#undef IOU_SLCR_MIO_PIN_58_OFFSET +#define IOU_SLCR_MIO_PIN_58_OFFSET 0XFF1800E8 +#undef IOU_SLCR_MIO_PIN_59_OFFSET +#define IOU_SLCR_MIO_PIN_59_OFFSET 0XFF1800EC +#undef IOU_SLCR_MIO_PIN_60_OFFSET +#define IOU_SLCR_MIO_PIN_60_OFFSET 0XFF1800F0 +#undef IOU_SLCR_MIO_PIN_61_OFFSET +#define IOU_SLCR_MIO_PIN_61_OFFSET 0XFF1800F4 +#undef IOU_SLCR_MIO_PIN_62_OFFSET +#define IOU_SLCR_MIO_PIN_62_OFFSET 0XFF1800F8 +#undef IOU_SLCR_MIO_PIN_63_OFFSET +#define IOU_SLCR_MIO_PIN_63_OFFSET 0XFF1800FC +#undef IOU_SLCR_MIO_PIN_64_OFFSET +#define IOU_SLCR_MIO_PIN_64_OFFSET 0XFF180100 +#undef IOU_SLCR_MIO_PIN_65_OFFSET +#define IOU_SLCR_MIO_PIN_65_OFFSET 0XFF180104 +#undef IOU_SLCR_MIO_PIN_66_OFFSET +#define IOU_SLCR_MIO_PIN_66_OFFSET 0XFF180108 +#undef IOU_SLCR_MIO_PIN_67_OFFSET +#define IOU_SLCR_MIO_PIN_67_OFFSET 0XFF18010C +#undef IOU_SLCR_MIO_PIN_68_OFFSET +#define IOU_SLCR_MIO_PIN_68_OFFSET 0XFF180110 +#undef IOU_SLCR_MIO_PIN_69_OFFSET +#define IOU_SLCR_MIO_PIN_69_OFFSET 0XFF180114 +#undef IOU_SLCR_MIO_PIN_70_OFFSET +#define IOU_SLCR_MIO_PIN_70_OFFSET 0XFF180118 +#undef IOU_SLCR_MIO_PIN_71_OFFSET +#define IOU_SLCR_MIO_PIN_71_OFFSET 0XFF18011C +#undef IOU_SLCR_MIO_PIN_72_OFFSET +#define IOU_SLCR_MIO_PIN_72_OFFSET 0XFF180120 +#undef IOU_SLCR_MIO_PIN_73_OFFSET +#define IOU_SLCR_MIO_PIN_73_OFFSET 0XFF180124 +#undef IOU_SLCR_MIO_PIN_74_OFFSET +#define IOU_SLCR_MIO_PIN_74_OFFSET 0XFF180128 +#undef IOU_SLCR_MIO_PIN_75_OFFSET +#define IOU_SLCR_MIO_PIN_75_OFFSET 0XFF18012C +#undef IOU_SLCR_MIO_PIN_76_OFFSET +#define IOU_SLCR_MIO_PIN_76_OFFSET 0XFF180130 +#undef IOU_SLCR_MIO_PIN_77_OFFSET +#define IOU_SLCR_MIO_PIN_77_OFFSET 0XFF180134 +#undef IOU_SLCR_MIO_MST_TRI0_OFFSET +#define IOU_SLCR_MIO_MST_TRI0_OFFSET 0XFF180204 +#undef IOU_SLCR_MIO_MST_TRI1_OFFSET +#define IOU_SLCR_MIO_MST_TRI1_OFFSET 0XFF180208 +#undef IOU_SLCR_MIO_MST_TRI2_OFFSET +#define IOU_SLCR_MIO_MST_TRI2_OFFSET 0XFF18020C +#undef IOU_SLCR_BANK0_CTRL0_OFFSET +#define IOU_SLCR_BANK0_CTRL0_OFFSET 0XFF180138 +#undef IOU_SLCR_BANK0_CTRL1_OFFSET +#define IOU_SLCR_BANK0_CTRL1_OFFSET 0XFF18013C +#undef IOU_SLCR_BANK0_CTRL3_OFFSET +#define IOU_SLCR_BANK0_CTRL3_OFFSET 0XFF180140 +#undef IOU_SLCR_BANK0_CTRL4_OFFSET +#define IOU_SLCR_BANK0_CTRL4_OFFSET 0XFF180144 +#undef IOU_SLCR_BANK0_CTRL5_OFFSET +#define IOU_SLCR_BANK0_CTRL5_OFFSET 0XFF180148 +#undef IOU_SLCR_BANK0_CTRL6_OFFSET +#define IOU_SLCR_BANK0_CTRL6_OFFSET 0XFF18014C +#undef IOU_SLCR_BANK1_CTRL0_OFFSET +#define IOU_SLCR_BANK1_CTRL0_OFFSET 0XFF180154 +#undef IOU_SLCR_BANK1_CTRL1_OFFSET +#define IOU_SLCR_BANK1_CTRL1_OFFSET 0XFF180158 +#undef IOU_SLCR_BANK1_CTRL3_OFFSET +#define IOU_SLCR_BANK1_CTRL3_OFFSET 0XFF18015C +#undef IOU_SLCR_BANK1_CTRL4_OFFSET +#define IOU_SLCR_BANK1_CTRL4_OFFSET 0XFF180160 +#undef IOU_SLCR_BANK1_CTRL5_OFFSET +#define IOU_SLCR_BANK1_CTRL5_OFFSET 0XFF180164 +#undef IOU_SLCR_BANK1_CTRL6_OFFSET +#define IOU_SLCR_BANK1_CTRL6_OFFSET 0XFF180168 +#undef IOU_SLCR_BANK2_CTRL0_OFFSET +#define IOU_SLCR_BANK2_CTRL0_OFFSET 0XFF180170 +#undef IOU_SLCR_BANK2_CTRL1_OFFSET +#define IOU_SLCR_BANK2_CTRL1_OFFSET 0XFF180174 +#undef IOU_SLCR_BANK2_CTRL3_OFFSET +#define IOU_SLCR_BANK2_CTRL3_OFFSET 0XFF180178 +#undef IOU_SLCR_BANK2_CTRL4_OFFSET +#define IOU_SLCR_BANK2_CTRL4_OFFSET 0XFF18017C +#undef IOU_SLCR_BANK2_CTRL5_OFFSET +#define IOU_SLCR_BANK2_CTRL5_OFFSET 0XFF180180 +#undef IOU_SLCR_BANK2_CTRL6_OFFSET +#define IOU_SLCR_BANK2_CTRL6_OFFSET 0XFF180184 +#undef IOU_SLCR_MIO_LOOPBACK_OFFSET +#define IOU_SLCR_MIO_LOOPBACK_OFFSET 0XFF180200 + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- + * (QSPI Clock) +*/ +#undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) +*/ +#undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q + * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +*/ +#undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou + * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) +*/ +#undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI + * Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +*/ +#undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I + * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI + * Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +*/ +#undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- ( + * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +*/ +#undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- + * (QSPI Slave Select) +*/ +#undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l + * pbk- (QSPI Clock to be fed-back) +*/ +#undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s + * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT + * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, + * Output, tracedq[4]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_ + * upper- (QSPI Slave Select upper) +*/ +#undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma + * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua + * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t + * racedq[5]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D + * atabus) +*/ +#undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste + * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_ + * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra + * ce Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D + * atabus) +*/ +#undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) +*/ +#undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9 + * ]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S + * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, + * Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA + * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D + * atabus) +*/ +#undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) +*/ +#undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 10]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D + * atabus) +*/ +#undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) +*/ +#undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 11]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_ + * upper- (QSPI Upper Clock) +*/ +#undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) +*/ +#undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 12]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT + * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_ + * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O + * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace + * dq[10]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA + * ND chip enable) +*/ +#undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, + * test_scan_out[13]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA + * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, + * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR + * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND + * Command Latch Enable) +*/ +#undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, + * test_scan_out[14]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT + * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, + * Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver + * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND + * Address Latch Enable) +*/ +#undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, + * test_scan_out[15]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT + * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp + * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou + * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria + * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, + * test_scan_out[16]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, + * test_scan_out[17]- (Test Scan Port) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, + * test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, + * test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, + * test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua + * 1_txd- (UART transmitter serial output) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes + * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t + * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E + * xt Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc + * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- ( + * UART receiver serial input) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN + * D Write Enable) +*/ +#undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = + * test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c + * su_ext_tamper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed +*/ +#undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po + * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp + * ut, csu_ext_tamper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus) +*/ +#undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test + * Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= + * csu, Input, csu_ext_tamper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N + * ot Used +*/ +#undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN + * D Read Enable) +*/ +#undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]- + * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port + * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou + * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in + * put) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * clk- (TX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) +*/ +#undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [0]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) +*/ +#undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ +#undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) +*/ +#undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [1]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) +*/ +#undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) +*/ +#undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [2]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ +#undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ +#undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, + * spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [3]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ +#undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) +*/ +#undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0 + * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock + * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, + * tracedq[8]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * ctl- (TX RGMII control) +*/ +#undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ +#undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT + * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp + * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * lk- (RX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) +*/ +#undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t + * race, Output, tracedq[10]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ +#undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) +*/ +#undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas + * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1 + * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq + * [11]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * clk- (TX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA + * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s + * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In + * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- + * (Trace Port Clock) +*/ +#undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [0]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b + * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT + * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, + * Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U + * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port + * Control Signal) +*/ +#undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [1]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1 + * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[ + * 5]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ + * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3 + * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi + * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [2]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[6]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA + * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu + * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out + * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp + * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [3]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[7]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp + * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[2]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * ctl- (TX RGMII control) +*/ +#undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) + * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * lk- (RX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4 + * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * Not Used +*/ +#undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste + * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt + * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us + * ed +*/ +#undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * tl- (RX RGMII control ) +*/ +#undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd + * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) +*/ +#undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind + * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= + * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece + * iver serial input) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) +*/ +#undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi + * o1_clk_out- (SDSDIO clock) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat + * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa + * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter + * serial output) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * clk- (TX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i + * n- (ULPI Clock) +*/ +#undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) +*/ +#undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [0]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- + * (Data bus direction control) +*/ +#undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou + * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) +*/ +#undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [1]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I + * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [2]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- + * (Data flow control signal from the PHY) +*/ +#undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [3]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * ctl- (TX RGMII control) +*/ +#undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * lk- (RX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- + * (Asserted to end or interrupt transfers) +*/ +#undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) +*/ +#undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, + * spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * tl- (RX RGMII control ) +*/ +#undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ +#undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * clk- (TX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i + * n- (ULPI Clock) +*/ +#undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4 + * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * trace, Output, tracedq[10]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [0]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- + * (Data bus direction control) +*/ +#undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= Not Used 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace + * dq[11]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [1]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not + * Used 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace + * Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [2]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- + * (Data flow control signal from the PHY) +*/ +#undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N + * ot Used 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste + * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt + * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace + * Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [3]- (TX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N + * ot Used 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * ctl- (TX RGMII control) +*/ +#undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ +#undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * lk- (RX RGMII clock) +*/ +#undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- + * (Asserted to end or interrupt transfers) +*/ +#undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed +*/ +#undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri + * al output) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not + * Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ +#undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[3]- (8-bit Data bus) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- ( + * UART receiver serial input) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * tl- (RX RGMII control ) +*/ +#undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data + * bus) +*/ +#undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1 + * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t + * xd- (UART transmitter serial output) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO + * clock) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI + * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2 + * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000E0U + +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK +#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002U + +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK +#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004U + +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio + * 1_cd_n- (SD card detect from connector) 3= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK +#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018U + +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M + * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, + * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5 + * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou + * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp + * ut, gem3_mdio_out- (MDIO Data) 7= Not Used +*/ +#undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL +#undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT +#undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK +#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000E0U + +/* +* Master Tri-state Enable for pin 0, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001U + +/* +* Master Tri-state Enable for pin 1, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002U + +/* +* Master Tri-state Enable for pin 2, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004U + +/* +* Master Tri-state Enable for pin 3, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008U + +/* +* Master Tri-state Enable for pin 4, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010U + +/* +* Master Tri-state Enable for pin 5, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020U + +/* +* Master Tri-state Enable for pin 6, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040U + +/* +* Master Tri-state Enable for pin 7, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080U + +/* +* Master Tri-state Enable for pin 8, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100U + +/* +* Master Tri-state Enable for pin 9, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200U + +/* +* Master Tri-state Enable for pin 10, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400U + +/* +* Master Tri-state Enable for pin 11, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800U + +/* +* Master Tri-state Enable for pin 12, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000U + +/* +* Master Tri-state Enable for pin 13, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000U + +/* +* Master Tri-state Enable for pin 14, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14 +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000U + +/* +* Master Tri-state Enable for pin 15, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15 +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000U + +/* +* Master Tri-state Enable for pin 16, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16 +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000U + +/* +* Master Tri-state Enable for pin 17, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17 +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000U + +/* +* Master Tri-state Enable for pin 18, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18 +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000U + +/* +* Master Tri-state Enable for pin 19, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19 +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000U + +/* +* Master Tri-state Enable for pin 20, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20 +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000U + +/* +* Master Tri-state Enable for pin 21, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21 +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000U + +/* +* Master Tri-state Enable for pin 22, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22 +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000U + +/* +* Master Tri-state Enable for pin 23, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23 +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000U + +/* +* Master Tri-state Enable for pin 24, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24 +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000U + +/* +* Master Tri-state Enable for pin 25, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25 +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000U + +/* +* Master Tri-state Enable for pin 26, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26 +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000U + +/* +* Master Tri-state Enable for pin 27, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27 +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000U + +/* +* Master Tri-state Enable for pin 28, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28 +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000U + +/* +* Master Tri-state Enable for pin 29, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29 +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000U + +/* +* Master Tri-state Enable for pin 30, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30 +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000U + +/* +* Master Tri-state Enable for pin 31, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31 +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000U + +/* +* Master Tri-state Enable for pin 32, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001U + +/* +* Master Tri-state Enable for pin 33, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002U + +/* +* Master Tri-state Enable for pin 34, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004U + +/* +* Master Tri-state Enable for pin 35, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008U + +/* +* Master Tri-state Enable for pin 36, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010U + +/* +* Master Tri-state Enable for pin 37, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020U + +/* +* Master Tri-state Enable for pin 38, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040U + +/* +* Master Tri-state Enable for pin 39, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080U + +/* +* Master Tri-state Enable for pin 40, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100U + +/* +* Master Tri-state Enable for pin 41, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200U + +/* +* Master Tri-state Enable for pin 42, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400U + +/* +* Master Tri-state Enable for pin 43, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800U + +/* +* Master Tri-state Enable for pin 44, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000U + +/* +* Master Tri-state Enable for pin 45, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000U + +/* +* Master Tri-state Enable for pin 46, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14 +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000U + +/* +* Master Tri-state Enable for pin 47, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15 +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000U + +/* +* Master Tri-state Enable for pin 48, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16 +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000U + +/* +* Master Tri-state Enable for pin 49, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17 +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000U + +/* +* Master Tri-state Enable for pin 50, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18 +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000U + +/* +* Master Tri-state Enable for pin 51, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19 +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000U + +/* +* Master Tri-state Enable for pin 52, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20 +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000U + +/* +* Master Tri-state Enable for pin 53, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21 +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000U + +/* +* Master Tri-state Enable for pin 54, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22 +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000U + +/* +* Master Tri-state Enable for pin 55, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23 +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000U + +/* +* Master Tri-state Enable for pin 56, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24 +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000U + +/* +* Master Tri-state Enable for pin 57, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25 +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000U + +/* +* Master Tri-state Enable for pin 58, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26 +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000U + +/* +* Master Tri-state Enable for pin 59, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27 +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000U + +/* +* Master Tri-state Enable for pin 60, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28 +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000U + +/* +* Master Tri-state Enable for pin 61, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29 +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000U + +/* +* Master Tri-state Enable for pin 62, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30 +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000U + +/* +* Master Tri-state Enable for pin 63, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31 +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000U + +/* +* Master Tri-state Enable for pin 64, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001U + +/* +* Master Tri-state Enable for pin 65, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002U + +/* +* Master Tri-state Enable for pin 66, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004U + +/* +* Master Tri-state Enable for pin 67, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008U + +/* +* Master Tri-state Enable for pin 68, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010U + +/* +* Master Tri-state Enable for pin 69, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020U + +/* +* Master Tri-state Enable for pin 70, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040U + +/* +* Master Tri-state Enable for pin 71, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080U + +/* +* Master Tri-state Enable for pin 72, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100U + +/* +* Master Tri-state Enable for pin 73, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200U + +/* +* Master Tri-state Enable for pin 74, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400U + +/* +* Master Tri-state Enable for pin 75, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800U + +/* +* Master Tri-state Enable for pin 76, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000U + +/* +* Master Tri-state Enable for pin 77, active high +*/ +#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL +#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT +#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT +#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT +#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT +#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT +#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT +#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT +#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT +#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT +#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT +#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U + +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT +#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U + +/* +* I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 + * = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs + * . +*/ +#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL +#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT +#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 3 +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 0x00000008U + +/* +* CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 + * = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. +*/ +#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL +#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT +#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 2 +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 0x00000004U + +/* +* UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. + * 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 + * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD + * and RI not used. +*/ +#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL +#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT +#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 1 +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 0x00000002U + +/* +* SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 + * = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs + * . The other SPI core will appear on the LS Slave Select. +*/ +#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL +#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT +#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0 +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U +#undef CRL_APB_AMS_REF_CTRL_OFFSET +#define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 + +/* +* 6 bit divider +*/ +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* 6 bit divider +*/ +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK +#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK +#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0 +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef CRL_APB_RST_LPD_IOU0_OFFSET +#define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET +#define IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET 0XFF180390 +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef IOU_SLCR_CTRL_REG_SD_OFFSET +#define IOU_SLCR_CTRL_REG_SD_OFFSET 0XFF180310 +#undef IOU_SLCR_SD_CONFIG_REG2_OFFSET +#define IOU_SLCR_SD_CONFIG_REG2_OFFSET 0XFF180320 +#undef IOU_SLCR_SD_CONFIG_REG1_OFFSET +#define IOU_SLCR_SD_CONFIG_REG1_OFFSET 0XFF18031C +#undef IOU_SLCR_SD_DLL_CTRL_OFFSET +#define IOU_SLCR_SD_DLL_CTRL_OFFSET 0XFF180358 +#undef IOU_SLCR_SD_CONFIG_REG3_OFFSET +#define IOU_SLCR_SD_CONFIG_REG3_OFFSET 0XFF180324 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET +#define UART0_BAUD_RATE_DIVIDER_REG0_OFFSET 0XFF000034 +#undef UART0_BAUD_RATE_GEN_REG0_OFFSET +#define UART0_BAUD_RATE_GEN_REG0_OFFSET 0XFF000018 +#undef UART0_CONTROL_REG0_OFFSET +#define UART0_CONTROL_REG0_OFFSET 0XFF000000 +#undef UART0_MODE_REG0_OFFSET +#define UART0_MODE_REG0_OFFSET 0XFF000004 +#undef UART1_BAUD_RATE_DIVIDER_REG0_OFFSET +#define UART1_BAUD_RATE_DIVIDER_REG0_OFFSET 0XFF010034 +#undef UART1_BAUD_RATE_GEN_REG0_OFFSET +#define UART1_BAUD_RATE_GEN_REG0_OFFSET 0XFF010018 +#undef UART1_CONTROL_REG0_OFFSET +#define UART1_CONTROL_REG0_OFFSET 0XFF010000 +#undef UART1_MODE_REG0_OFFSET +#define UART1_MODE_REG0_OFFSET 0XFF010004 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET +#define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024 +#undef CSU_TAMPER_STATUS_OFFSET +#define CSU_TAMPER_STATUS_OFFSET 0XFFCA5000 +#undef APU_ACE_CTRL_OFFSET +#define APU_ACE_CTRL_OFFSET 0XFD5C0060 +#undef RTC_CONTROL_OFFSET +#define RTC_CONTROL_OFFSET 0XFFA60040 +#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET 0XFF260020 +#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET 0XFF260000 +#undef CRL_APB_BOOT_PIN_CTRL_OFFSET +#define CRL_APB_BOOT_PIN_CTRL_OFFSET 0XFF5E0250 +#undef CRL_APB_BOOT_PIN_CTRL_OFFSET +#define CRL_APB_BOOT_PIN_CTRL_OFFSET 0XFF5E0250 +#undef CRL_APB_BOOT_PIN_CTRL_OFFSET +#define CRL_APB_BOOT_PIN_CTRL_OFFSET 0XFF5E0250 +#undef GPIO_DIRM_1_OFFSET +#define GPIO_DIRM_1_OFFSET 0XFF0A0244 +#undef GPIO_OEN_1_OFFSET +#define GPIO_OEN_1_OFFSET 0XFF0A0248 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 +#undef GPIO_DIRM_1_OFFSET +#define GPIO_DIRM_1_OFFSET 0XFF0A0244 +#undef GPIO_OEN_1_OFFSET +#define GPIO_OEN_1_OFFSET 0XFF0A0248 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 + +/* +* PCIE config reset +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U + +/* +* PCIE control block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U + +/* +* PCIE bridge block level reset (AXI interface) +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U + +/* +* Display Port block level reset (includes DPDMA) +*/ +#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U + +/* +* FPD WDT reset +*/ +#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 15 +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 0x00008000U + +/* +* GDMA block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 6 +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 0x00000040U + +/* +* Pixel Processor (submodule of GPU) block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 4 +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 0x00000010U + +/* +* Pixel Processor (submodule of GPU) block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 5 +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 0x00000020U + +/* +* GPU block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK +#define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 3 +#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 0x00000008U + +/* +* GT block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK +#define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 2 +#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK 0x00000004U + +/* +* Sata block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20 +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 0x00100000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT 19 +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK 0x00080000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT 17 +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK 0x00020000U + +/* +* Reset entire full power domain. +*/ +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_MASK +#define CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT 23 +#define CRL_APB_RST_LPD_TOP_FPD_RESET_MASK 0x00800000U + +/* +* LPD SWDT +*/ +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT 20 +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK 0x00100000U + +/* +* Sysmonitor reset +*/ +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT 17 +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK 0x00020000U + +/* +* Real Time Clock reset +*/ +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_MASK +#define CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT 16 +#define CRL_APB_RST_LPD_TOP_RTC_RESET_MASK 0x00010000U + +/* +* APM reset +*/ +#undef CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_APM_RESET_MASK +#define CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT 15 +#define CRL_APB_RST_LPD_TOP_APM_RESET_MASK 0x00008000U + +/* +* IPI reset +*/ +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_MASK +#define CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT 14 +#define CRL_APB_RST_LPD_TOP_IPI_RESET_MASK 0x00004000U + +/* +* reset entire RPU power island +*/ +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT 4 +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK 0x00000010U + +/* +* reset ocm +*/ +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_MASK +#define CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_TOP_OCM_RESET_MASK 0x00000008U + +/* +* GEM 3 reset +*/ +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0 +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U + +/* +* 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa + * ss the Tap delay on the Rx clock signal of LQSPI +*/ +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x00000007 +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2 +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U + +/* +* USB 0 reset for control registers +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 6 +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 0x00000040U + +/* +* SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled +*/ +#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL +#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT +#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 15 +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 0x00008000U + +/* +* Should be set based on the final product usage 00 - Removable SCard Slot + * 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved +*/ +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 28 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 0x30000000U + +/* +* 8-bit Support for Embedded Device 1: The Core supports 8-bit Interface 0 + * : Supports only 4-bit SD Interface +*/ +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_8BIT_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_8BIT_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_8BIT_MASK +#define IOU_SLCR_SD_CONFIG_REG2_SD1_8BIT_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_8BIT_SHIFT 18 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_8BIT_MASK 0x00040000U + +/* +* 1.8V Support 1: 1.8V supported 0: 1.8V not supported support +*/ +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 25 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 0x02000000U + +/* +* 3.0V Support 1: 3.0V supported 0: 3.0V not supported support +*/ +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 24 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 0x01000000U + +/* +* 3.3V Support 1: 3.3V supported 0: 3.3V not supported support +*/ +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 23 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 0x00800000U + +/* +* Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. +*/ +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 0x32403240 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 23 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 0x7F800000U + +/* +* Configures the Number of Taps (Phases) of the rxclk_in that is supported + * . +*/ +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL 0x32403240 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT 17 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK 0x007E0000U + +/* +* Reserved. +*/ +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL 0x00080008 +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT 3 +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK 0x00000008U + +/* +* This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S + * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other + * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n + * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved +*/ +#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 0x06070607 +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 22 +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 0x03C00000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8 +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 0x00000100U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9 +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 0x00000200U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 0x00000400U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 15 +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 0x00008000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11 +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 0x00000800U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12 +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 0x00001000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13 +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 0x00002000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14 +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1 +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 0x00000002U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2 +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 0x00000004U + +/* +* Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +*/ +#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL +#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT +#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU + +/* +* Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +*/ +#undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL +#undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT +#undef UART0_BAUD_RATE_GEN_REG0_CD_MASK +#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B +#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0 +#define UART0_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU + +/* +* Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. +*/ +#undef UART0_CONTROL_REG0_STPBRK_DEFVAL +#undef UART0_CONTROL_REG0_STPBRK_SHIFT +#undef UART0_CONTROL_REG0_STPBRK_MASK +#define UART0_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_STPBRK_SHIFT 8 +#define UART0_CONTROL_REG0_STPBRK_MASK 0x00000100U + +/* +* Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. +*/ +#undef UART0_CONTROL_REG0_STTBRK_DEFVAL +#undef UART0_CONTROL_REG0_STTBRK_SHIFT +#undef UART0_CONTROL_REG0_STTBRK_MASK +#define UART0_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_STTBRK_SHIFT 7 +#define UART0_CONTROL_REG0_STTBRK_MASK 0x00000080U + +/* +* Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. +*/ +#undef UART0_CONTROL_REG0_RSTTO_DEFVAL +#undef UART0_CONTROL_REG0_RSTTO_SHIFT +#undef UART0_CONTROL_REG0_RSTTO_MASK +#define UART0_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RSTTO_SHIFT 6 +#define UART0_CONTROL_REG0_RSTTO_MASK 0x00000040U + +/* +* Transmit disable: 0: enable transmitter 1: disable transmitter +*/ +#undef UART0_CONTROL_REG0_TXDIS_DEFVAL +#undef UART0_CONTROL_REG0_TXDIS_SHIFT +#undef UART0_CONTROL_REG0_TXDIS_MASK +#define UART0_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXDIS_SHIFT 5 +#define UART0_CONTROL_REG0_TXDIS_MASK 0x00000020U + +/* +* Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. +*/ +#undef UART0_CONTROL_REG0_TXEN_DEFVAL +#undef UART0_CONTROL_REG0_TXEN_SHIFT +#undef UART0_CONTROL_REG0_TXEN_MASK +#define UART0_CONTROL_REG0_TXEN_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXEN_SHIFT 4 +#define UART0_CONTROL_REG0_TXEN_MASK 0x00000010U + +/* +* Receive disable: 0: enable 1: disable, regardless of the value of RXEN +*/ +#undef UART0_CONTROL_REG0_RXDIS_DEFVAL +#undef UART0_CONTROL_REG0_RXDIS_SHIFT +#undef UART0_CONTROL_REG0_RXDIS_MASK +#define UART0_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXDIS_SHIFT 3 +#define UART0_CONTROL_REG0_RXDIS_MASK 0x00000008U + +/* +* Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. +*/ +#undef UART0_CONTROL_REG0_RXEN_DEFVAL +#undef UART0_CONTROL_REG0_RXEN_SHIFT +#undef UART0_CONTROL_REG0_RXEN_MASK +#define UART0_CONTROL_REG0_RXEN_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXEN_SHIFT 2 +#define UART0_CONTROL_REG0_RXEN_MASK 0x00000004U + +/* +* Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. +*/ +#undef UART0_CONTROL_REG0_TXRES_DEFVAL +#undef UART0_CONTROL_REG0_TXRES_SHIFT +#undef UART0_CONTROL_REG0_TXRES_MASK +#define UART0_CONTROL_REG0_TXRES_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXRES_SHIFT 1 +#define UART0_CONTROL_REG0_TXRES_MASK 0x00000002U + +/* +* Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. +*/ +#undef UART0_CONTROL_REG0_RXRES_DEFVAL +#undef UART0_CONTROL_REG0_RXRES_SHIFT +#undef UART0_CONTROL_REG0_RXRES_MASK +#define UART0_CONTROL_REG0_RXRES_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXRES_SHIFT 0 +#define UART0_CONTROL_REG0_RXRES_MASK 0x00000001U + +/* +* Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback +*/ +#undef UART0_MODE_REG0_CHMODE_DEFVAL +#undef UART0_MODE_REG0_CHMODE_SHIFT +#undef UART0_MODE_REG0_CHMODE_MASK +#define UART0_MODE_REG0_CHMODE_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CHMODE_SHIFT 8 +#define UART0_MODE_REG0_CHMODE_MASK 0x00000300U + +/* +* Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved +*/ +#undef UART0_MODE_REG0_NBSTOP_DEFVAL +#undef UART0_MODE_REG0_NBSTOP_SHIFT +#undef UART0_MODE_REG0_NBSTOP_MASK +#define UART0_MODE_REG0_NBSTOP_DEFVAL 0x00000000 +#define UART0_MODE_REG0_NBSTOP_SHIFT 6 +#define UART0_MODE_REG0_NBSTOP_MASK 0x000000C0U + +/* +* Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty +*/ +#undef UART0_MODE_REG0_PAR_DEFVAL +#undef UART0_MODE_REG0_PAR_SHIFT +#undef UART0_MODE_REG0_PAR_MASK +#define UART0_MODE_REG0_PAR_DEFVAL 0x00000000 +#define UART0_MODE_REG0_PAR_SHIFT 3 +#define UART0_MODE_REG0_PAR_MASK 0x00000038U + +/* +* Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits +*/ +#undef UART0_MODE_REG0_CHRL_DEFVAL +#undef UART0_MODE_REG0_CHRL_SHIFT +#undef UART0_MODE_REG0_CHRL_MASK +#define UART0_MODE_REG0_CHRL_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CHRL_SHIFT 1 +#define UART0_MODE_REG0_CHRL_MASK 0x00000006U + +/* +* Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 +*/ +#undef UART0_MODE_REG0_CLKS_DEFVAL +#undef UART0_MODE_REG0_CLKS_SHIFT +#undef UART0_MODE_REG0_CLKS_MASK +#define UART0_MODE_REG0_CLKS_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CLKS_SHIFT 0 +#define UART0_MODE_REG0_CLKS_MASK 0x00000001U + +/* +* Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +*/ +#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL +#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT +#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU + +/* +* Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +*/ +#undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL +#undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT +#undef UART1_BAUD_RATE_GEN_REG0_CD_MASK +#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B +#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0 +#define UART1_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU + +/* +* Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. +*/ +#undef UART1_CONTROL_REG0_STPBRK_DEFVAL +#undef UART1_CONTROL_REG0_STPBRK_SHIFT +#undef UART1_CONTROL_REG0_STPBRK_MASK +#define UART1_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_STPBRK_SHIFT 8 +#define UART1_CONTROL_REG0_STPBRK_MASK 0x00000100U + +/* +* Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. +*/ +#undef UART1_CONTROL_REG0_STTBRK_DEFVAL +#undef UART1_CONTROL_REG0_STTBRK_SHIFT +#undef UART1_CONTROL_REG0_STTBRK_MASK +#define UART1_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_STTBRK_SHIFT 7 +#define UART1_CONTROL_REG0_STTBRK_MASK 0x00000080U + +/* +* Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. +*/ +#undef UART1_CONTROL_REG0_RSTTO_DEFVAL +#undef UART1_CONTROL_REG0_RSTTO_SHIFT +#undef UART1_CONTROL_REG0_RSTTO_MASK +#define UART1_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RSTTO_SHIFT 6 +#define UART1_CONTROL_REG0_RSTTO_MASK 0x00000040U + +/* +* Transmit disable: 0: enable transmitter 1: disable transmitter +*/ +#undef UART1_CONTROL_REG0_TXDIS_DEFVAL +#undef UART1_CONTROL_REG0_TXDIS_SHIFT +#undef UART1_CONTROL_REG0_TXDIS_MASK +#define UART1_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXDIS_SHIFT 5 +#define UART1_CONTROL_REG0_TXDIS_MASK 0x00000020U + +/* +* Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. +*/ +#undef UART1_CONTROL_REG0_TXEN_DEFVAL +#undef UART1_CONTROL_REG0_TXEN_SHIFT +#undef UART1_CONTROL_REG0_TXEN_MASK +#define UART1_CONTROL_REG0_TXEN_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXEN_SHIFT 4 +#define UART1_CONTROL_REG0_TXEN_MASK 0x00000010U + +/* +* Receive disable: 0: enable 1: disable, regardless of the value of RXEN +*/ +#undef UART1_CONTROL_REG0_RXDIS_DEFVAL +#undef UART1_CONTROL_REG0_RXDIS_SHIFT +#undef UART1_CONTROL_REG0_RXDIS_MASK +#define UART1_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXDIS_SHIFT 3 +#define UART1_CONTROL_REG0_RXDIS_MASK 0x00000008U + +/* +* Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. +*/ +#undef UART1_CONTROL_REG0_RXEN_DEFVAL +#undef UART1_CONTROL_REG0_RXEN_SHIFT +#undef UART1_CONTROL_REG0_RXEN_MASK +#define UART1_CONTROL_REG0_RXEN_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXEN_SHIFT 2 +#define UART1_CONTROL_REG0_RXEN_MASK 0x00000004U + +/* +* Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. +*/ +#undef UART1_CONTROL_REG0_TXRES_DEFVAL +#undef UART1_CONTROL_REG0_TXRES_SHIFT +#undef UART1_CONTROL_REG0_TXRES_MASK +#define UART1_CONTROL_REG0_TXRES_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXRES_SHIFT 1 +#define UART1_CONTROL_REG0_TXRES_MASK 0x00000002U + +/* +* Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. +*/ +#undef UART1_CONTROL_REG0_RXRES_DEFVAL +#undef UART1_CONTROL_REG0_RXRES_SHIFT +#undef UART1_CONTROL_REG0_RXRES_MASK +#define UART1_CONTROL_REG0_RXRES_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXRES_SHIFT 0 +#define UART1_CONTROL_REG0_RXRES_MASK 0x00000001U + +/* +* Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback +*/ +#undef UART1_MODE_REG0_CHMODE_DEFVAL +#undef UART1_MODE_REG0_CHMODE_SHIFT +#undef UART1_MODE_REG0_CHMODE_MASK +#define UART1_MODE_REG0_CHMODE_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CHMODE_SHIFT 8 +#define UART1_MODE_REG0_CHMODE_MASK 0x00000300U + +/* +* Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved +*/ +#undef UART1_MODE_REG0_NBSTOP_DEFVAL +#undef UART1_MODE_REG0_NBSTOP_SHIFT +#undef UART1_MODE_REG0_NBSTOP_MASK +#define UART1_MODE_REG0_NBSTOP_DEFVAL 0x00000000 +#define UART1_MODE_REG0_NBSTOP_SHIFT 6 +#define UART1_MODE_REG0_NBSTOP_MASK 0x000000C0U + +/* +* Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty +*/ +#undef UART1_MODE_REG0_PAR_DEFVAL +#undef UART1_MODE_REG0_PAR_SHIFT +#undef UART1_MODE_REG0_PAR_MASK +#define UART1_MODE_REG0_PAR_DEFVAL 0x00000000 +#define UART1_MODE_REG0_PAR_SHIFT 3 +#define UART1_MODE_REG0_PAR_MASK 0x00000038U + +/* +* Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits +*/ +#undef UART1_MODE_REG0_CHRL_DEFVAL +#undef UART1_MODE_REG0_CHRL_SHIFT +#undef UART1_MODE_REG0_CHRL_MASK +#define UART1_MODE_REG0_CHRL_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CHRL_SHIFT 1 +#define UART1_MODE_REG0_CHRL_MASK 0x00000006U + +/* +* Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 +*/ +#undef UART1_MODE_REG0_CLKS_DEFVAL +#undef UART1_MODE_REG0_CLKS_SHIFT +#undef UART1_MODE_REG0_CLKS_MASK +#define UART1_MODE_REG0_CLKS_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CLKS_SHIFT 0 +#define UART1_MODE_REG0_CLKS_MASK 0x00000001U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT 18 +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK 0x00040000U + +/* +* TrustZone Classification for ADMA +*/ +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU + +/* +* CSU regsiter +*/ +#undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_0_MASK +#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT 0 +#define CSU_TAMPER_STATUS_TAMPER_0_MASK 0x00000001U + +/* +* External MIO +*/ +#undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_1_MASK +#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT 1 +#define CSU_TAMPER_STATUS_TAMPER_1_MASK 0x00000002U + +/* +* JTAG toggle detect +*/ +#undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_2_MASK +#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT 2 +#define CSU_TAMPER_STATUS_TAMPER_2_MASK 0x00000004U + +/* +* PL SEU error +*/ +#undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_3_MASK +#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT 3 +#define CSU_TAMPER_STATUS_TAMPER_3_MASK 0x00000008U + +/* +* AMS over temperature alarm for LPD +*/ +#undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_4_MASK +#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT 4 +#define CSU_TAMPER_STATUS_TAMPER_4_MASK 0x00000010U + +/* +* AMS over temperature alarm for APU +*/ +#undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_5_MASK +#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT 5 +#define CSU_TAMPER_STATUS_TAMPER_5_MASK 0x00000020U + +/* +* AMS voltage alarm for VCCPINT_FPD +*/ +#undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_6_MASK +#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT 6 +#define CSU_TAMPER_STATUS_TAMPER_6_MASK 0x00000040U + +/* +* AMS voltage alarm for VCCPINT_LPD +*/ +#undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_7_MASK +#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT 7 +#define CSU_TAMPER_STATUS_TAMPER_7_MASK 0x00000080U + +/* +* AMS voltage alarm for VCCPAUX +*/ +#undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_8_MASK +#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT 8 +#define CSU_TAMPER_STATUS_TAMPER_8_MASK 0x00000100U + +/* +* AMS voltage alarm for DDRPHY +*/ +#undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_9_MASK +#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT 9 +#define CSU_TAMPER_STATUS_TAMPER_9_MASK 0x00000200U + +/* +* AMS voltage alarm for PSIO bank 0/1/2 +*/ +#undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_10_MASK +#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT 10 +#define CSU_TAMPER_STATUS_TAMPER_10_MASK 0x00000400U + +/* +* AMS voltage alarm for PSIO bank 3 (dedicated pins) +*/ +#undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_11_MASK +#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT 11 +#define CSU_TAMPER_STATUS_TAMPER_11_MASK 0x00000800U + +/* +* AMS voltaage alarm for GT +*/ +#undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL +#undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT +#undef CSU_TAMPER_STATUS_TAMPER_12_MASK +#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT 12 +#define CSU_TAMPER_STATUS_TAMPER_12_MASK 0x00001000U + +/* +* Set ACE outgoing AWQOS value +*/ +#undef APU_ACE_CTRL_AWQOS_DEFVAL +#undef APU_ACE_CTRL_AWQOS_SHIFT +#undef APU_ACE_CTRL_AWQOS_MASK +#define APU_ACE_CTRL_AWQOS_DEFVAL 0x000F000F +#define APU_ACE_CTRL_AWQOS_SHIFT 16 +#define APU_ACE_CTRL_AWQOS_MASK 0x000F0000U + +/* +* Set ACE outgoing ARQOS value +*/ +#undef APU_ACE_CTRL_ARQOS_DEFVAL +#undef APU_ACE_CTRL_ARQOS_SHIFT +#undef APU_ACE_CTRL_ARQOS_MASK +#define APU_ACE_CTRL_ARQOS_DEFVAL 0x000F000F +#define APU_ACE_CTRL_ARQOS_SHIFT 0 +#define APU_ACE_CTRL_ARQOS_MASK 0x0000000FU + +/* +* Enables the RTC. By writing a 0 to this bit, RTC will be powered off and + * the only module that potentially draws current from the battery will be + * BBRAM. The value read through this bit does not necessarily reflect whe + * ther RTC is enabled or not. It is expected that RTC is enabled every tim + * e it is being configured. If RTC is not used in the design, FSBL will di + * sable it by writing a 0 to this bit. +*/ +#undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL +#undef RTC_CONTROL_BATTERY_DISABLE_SHIFT +#undef RTC_CONTROL_BATTERY_DISABLE_MASK +#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL 0x01000000 +#define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31 +#define RTC_CONTROL_BATTERY_DISABLE_MASK 0x80000000U + +/* +* Frequency in number of ticks per second. Valid range from 10 MHz to 100 + * MHz. +*/ +#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL +#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT +#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 0 +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 0xFFFFFFFFU + +/* +* Enable 0: The counter is disabled and not incrementing. 1: The counter i + * s enabled and is incrementing. +*/ +#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL +#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT +#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 0x00000000 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 0 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 0x00000001U + +/* +* Value driven onto the mode pins, when out_en = 1 +*/ +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_DEFVAL +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_MASK +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_DEFVAL 0x00000000 +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_MASK 0x00000F00U + +/* +* When 0, the pins will be inputs from the board to the PS. When 1, the PS + * will drive these pins +*/ +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_DEFVAL +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_MASK +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_DEFVAL 0x00000000 +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_MASK 0x0000000FU + +/* +* Value driven onto the mode pins, when out_en = 1 +*/ +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_DEFVAL +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_MASK +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_DEFVAL 0x00000000 +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_MASK 0x00000F00U + +/* +* When 0, the pins will be inputs from the board to the PS. When 1, the PS + * will drive these pins +*/ +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_DEFVAL +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_MASK +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_DEFVAL 0x00000000 +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_MASK 0x0000000FU + +/* +* Value driven onto the mode pins, when out_en = 1 +*/ +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_DEFVAL +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT +#undef CRL_APB_BOOT_PIN_CTRL_OUT_VAL_MASK +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_DEFVAL 0x00000000 +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 +#define CRL_APB_BOOT_PIN_CTRL_OUT_VAL_MASK 0x00000F00U + +/* +* When 0, the pins will be inputs from the board to the PS. When 1, the PS + * will drive these pins +*/ +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_DEFVAL +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT +#undef CRL_APB_BOOT_PIN_CTRL_OUT_EN_MASK +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_DEFVAL 0x00000000 +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 +#define CRL_APB_BOOT_PIN_CTRL_OUT_EN_MASK 0x0000000FU + +/* +* Operation is the same as DIRM_0[DIRECTION_0] +*/ +#undef GPIO_DIRM_1_DIRECTION_1_DEFVAL +#undef GPIO_DIRM_1_DIRECTION_1_SHIFT +#undef GPIO_DIRM_1_DIRECTION_1_MASK +#define GPIO_DIRM_1_DIRECTION_1_DEFVAL 0x00000000 +#define GPIO_DIRM_1_DIRECTION_1_SHIFT 0 +#define GPIO_DIRM_1_DIRECTION_1_MASK 0x03FFFFFFU + +/* +* Operation is the same as OEN_0[OP_ENABLE_0] +*/ +#undef GPIO_OEN_1_OP_ENABLE_1_DEFVAL +#undef GPIO_OEN_1_OP_ENABLE_1_SHIFT +#undef GPIO_OEN_1_OP_ENABLE_1_MASK +#define GPIO_OEN_1_OP_ENABLE_1_DEFVAL 0x00000000 +#define GPIO_OEN_1_OP_ENABLE_1_SHIFT 0 +#define GPIO_OEN_1_OP_ENABLE_1_MASK 0x03FFFFFFU + +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U + +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU + +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U + +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU + +/* +* Operation is the same as DIRM_0[DIRECTION_0] +*/ +#undef GPIO_DIRM_1_DIRECTION_1_DEFVAL +#undef GPIO_DIRM_1_DIRECTION_1_SHIFT +#undef GPIO_DIRM_1_DIRECTION_1_MASK +#define GPIO_DIRM_1_DIRECTION_1_DEFVAL 0x00000000 +#define GPIO_DIRM_1_DIRECTION_1_SHIFT 0 +#define GPIO_DIRM_1_DIRECTION_1_MASK 0x03FFFFFFU + +/* +* Operation is the same as OEN_0[OP_ENABLE_0] +*/ +#undef GPIO_OEN_1_OP_ENABLE_1_DEFVAL +#undef GPIO_OEN_1_OP_ENABLE_1_SHIFT +#undef GPIO_OEN_1_OP_ENABLE_1_MASK +#define GPIO_OEN_1_OP_ENABLE_1_DEFVAL 0x00000000 +#define GPIO_OEN_1_OP_ENABLE_1_SHIFT 0 +#define GPIO_OEN_1_OP_ENABLE_1_MASK 0x03FFFFFFU + +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U + +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU +#undef FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET +#define FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET 0XFD690040 +#undef FPD_SLCR_SECURE_SLCR_PCIE_OFFSET +#define FPD_SLCR_SECURE_SLCR_PCIE_OFFSET 0XFD690030 +#undef LPD_SLCR_SECURE_SLCR_USB_OFFSET +#define LPD_SLCR_SECURE_SLCR_USB_OFFSET 0XFF4B0034 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET +#define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024 +#undef FPD_SLCR_SECURE_SLCR_GDMA_OFFSET +#define FPD_SLCR_SECURE_SLCR_GDMA_OFFSET 0XFD690050 + +/* +* TrustZone classification for DisplayPort DMA +*/ +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL 0x00000001 +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK 0x00000001U + +/* +* TrustZone classification for DMA Channel 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT 21 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK 0x00200000U + +/* +* TrustZone classification for DMA Channel 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT 22 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK 0x00400000U + +/* +* TrustZone classification for DMA Channel 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT 23 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK 0x00800000U + +/* +* TrustZone classification for DMA Channel 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT 24 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK 0x01000000U + +/* +* TrustZone classification for Ingress Address Translation 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT 13 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK 0x00002000U + +/* +* TrustZone classification for Ingress Address Translation 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT 14 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK 0x00004000U + +/* +* TrustZone classification for Ingress Address Translation 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT 15 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK 0x00008000U + +/* +* TrustZone classification for Ingress Address Translation 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT 16 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK 0x00010000U + +/* +* TrustZone classification for Ingress Address Translation 4 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT 17 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK 0x00020000U + +/* +* TrustZone classification for Ingress Address Translation 5 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT 18 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK 0x00040000U + +/* +* TrustZone classification for Ingress Address Translation 6 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT 19 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK 0x00080000U + +/* +* TrustZone classification for Ingress Address Translation 7 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT 20 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK 0x00100000U + +/* +* TrustZone classification for Egress Address Translation 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT 5 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK 0x00000020U + +/* +* TrustZone classification for Egress Address Translation 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT 6 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK 0x00000040U + +/* +* TrustZone classification for Egress Address Translation 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT 7 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK 0x00000080U + +/* +* TrustZone classification for Egress Address Translation 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT 8 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK 0x00000100U + +/* +* TrustZone classification for Egress Address Translation 4 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT 9 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK 0x00000200U + +/* +* TrustZone classification for Egress Address Translation 5 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT 10 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK 0x00000400U + +/* +* TrustZone classification for Egress Address Translation 6 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT 11 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK 0x00000800U + +/* +* TrustZone classification for Egress Address Translation 7 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT 12 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK 0x00001000U + +/* +* TrustZone classification for DMA Registers +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT 4 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK 0x00000010U + +/* +* TrustZone classification for MSIx Table +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT 2 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK 0x00000004U + +/* +* TrustZone classification for MSIx PBA +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT 3 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK 0x00000008U + +/* +* TrustZone classification for ECAM +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT 1 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK 0x00000002U + +/* +* TrustZone classification for Bridge Common Registers +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001U + +/* +* TrustZone Classification for USB3_0 +*/ +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL 0x00000003 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK 0x00000001U + +/* +* TrustZone Classification for USB3_1 +*/ +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL 0x00000003 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT 1 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK 0x00000002U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT 16 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK 0x00070000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT 19 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK 0x00380000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT 16 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK 0x00070000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT 19 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK 0x00380000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT 0 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK 0x00000007U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT 3 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK 0x00000038U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT 6 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK 0x000001C0U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT 9 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK 0x00000E00U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT 0 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK 0x00000007U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT 3 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK 0x00000038U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT 6 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK 0x000001C0U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT 9 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK 0x00000E00U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT 25 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK 0x0E000000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT 22 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK 0x01C00000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT 22 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK 0x01C00000U + +/* +* TrustZone Classification for ADMA +*/ +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU + +/* +* TrustZone Classification for GDMA +*/ +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK 0x000000FFU +#undef SERDES_PLL_REF_SEL0_OFFSET +#define SERDES_PLL_REF_SEL0_OFFSET 0XFD410000 +#undef SERDES_PLL_REF_SEL1_OFFSET +#define SERDES_PLL_REF_SEL1_OFFSET 0XFD410004 +#undef SERDES_PLL_REF_SEL2_OFFSET +#define SERDES_PLL_REF_SEL2_OFFSET 0XFD410008 +#undef SERDES_PLL_REF_SEL3_OFFSET +#define SERDES_PLL_REF_SEL3_OFFSET 0XFD41000C +#undef SERDES_L0_L0_REF_CLK_SEL_OFFSET +#define SERDES_L0_L0_REF_CLK_SEL_OFFSET 0XFD402860 +#undef SERDES_L0_L1_REF_CLK_SEL_OFFSET +#define SERDES_L0_L1_REF_CLK_SEL_OFFSET 0XFD402864 +#undef SERDES_L0_L2_REF_CLK_SEL_OFFSET +#define SERDES_L0_L2_REF_CLK_SEL_OFFSET 0XFD402868 +#undef SERDES_L0_L3_REF_CLK_SEL_OFFSET +#define SERDES_L0_L3_REF_CLK_SEL_OFFSET 0XFD40286C +#undef SERDES_L2_TM_PLL_DIG_37_OFFSET +#define SERDES_L2_TM_PLL_DIG_37_OFFSET 0XFD40A094 +#undef SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET +#define SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET 0XFD40A368 +#undef SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET +#define SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40A36C +#undef SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET +#define SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET 0XFD40E368 +#undef SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET +#define SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40E36C +#undef SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET +#define SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET 0XFD406368 +#undef SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET +#define SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40636C +#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET 0XFD406370 +#undef SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET +#define SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET 0XFD406374 +#undef SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET +#define SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET 0XFD406378 +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET 0XFD40637C +#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET 0XFD40A370 +#undef SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET +#define SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET 0XFD40A374 +#undef SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET +#define SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET 0XFD40A378 +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET 0XFD40A37C +#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET 0XFD40E370 +#undef SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET +#define SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET 0XFD40E374 +#undef SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET +#define SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET 0XFD40E378 +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET 0XFD40E37C +#undef SERDES_L2_TM_DIG_6_OFFSET +#define SERDES_L2_TM_DIG_6_OFFSET 0XFD40906C +#undef SERDES_L2_TX_DIG_TM_61_OFFSET +#define SERDES_L2_TX_DIG_TM_61_OFFSET 0XFD4080F4 +#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET 0XFD40E360 +#undef SERDES_L3_TM_DIG_6_OFFSET +#define SERDES_L3_TM_DIG_6_OFFSET 0XFD40D06C +#undef SERDES_L3_TX_DIG_TM_61_OFFSET +#define SERDES_L3_TX_DIG_TM_61_OFFSET 0XFD40C0F4 +#undef SERDES_L0_TM_AUX_0_OFFSET +#define SERDES_L0_TM_AUX_0_OFFSET 0XFD4010CC +#undef SERDES_L2_TM_AUX_0_OFFSET +#define SERDES_L2_TM_AUX_0_OFFSET 0XFD4090CC +#undef SERDES_L0_TM_DIG_8_OFFSET +#define SERDES_L0_TM_DIG_8_OFFSET 0XFD401074 +#undef SERDES_L1_TM_DIG_8_OFFSET +#define SERDES_L1_TM_DIG_8_OFFSET 0XFD405074 +#undef SERDES_L2_TM_DIG_8_OFFSET +#define SERDES_L2_TM_DIG_8_OFFSET 0XFD409074 +#undef SERDES_L3_TM_DIG_8_OFFSET +#define SERDES_L3_TM_DIG_8_OFFSET 0XFD40D074 +#undef SERDES_L0_TM_MISC2_OFFSET +#define SERDES_L0_TM_MISC2_OFFSET 0XFD40189C +#undef SERDES_L0_TM_IQ_ILL1_OFFSET +#define SERDES_L0_TM_IQ_ILL1_OFFSET 0XFD4018F8 +#undef SERDES_L0_TM_IQ_ILL2_OFFSET +#define SERDES_L0_TM_IQ_ILL2_OFFSET 0XFD4018FC +#undef SERDES_L0_TM_ILL12_OFFSET +#define SERDES_L0_TM_ILL12_OFFSET 0XFD401990 +#undef SERDES_L0_TM_E_ILL1_OFFSET +#define SERDES_L0_TM_E_ILL1_OFFSET 0XFD401924 +#undef SERDES_L0_TM_E_ILL2_OFFSET +#define SERDES_L0_TM_E_ILL2_OFFSET 0XFD401928 +#undef SERDES_L0_TM_IQ_ILL3_OFFSET +#define SERDES_L0_TM_IQ_ILL3_OFFSET 0XFD401900 +#undef SERDES_L0_TM_E_ILL3_OFFSET +#define SERDES_L0_TM_E_ILL3_OFFSET 0XFD40192C +#undef SERDES_L0_TM_ILL8_OFFSET +#define SERDES_L0_TM_ILL8_OFFSET 0XFD401980 +#undef SERDES_L0_TM_IQ_ILL8_OFFSET +#define SERDES_L0_TM_IQ_ILL8_OFFSET 0XFD401914 +#undef SERDES_L0_TM_IQ_ILL9_OFFSET +#define SERDES_L0_TM_IQ_ILL9_OFFSET 0XFD401918 +#undef SERDES_L0_TM_E_ILL8_OFFSET +#define SERDES_L0_TM_E_ILL8_OFFSET 0XFD401940 +#undef SERDES_L0_TM_E_ILL9_OFFSET +#define SERDES_L0_TM_E_ILL9_OFFSET 0XFD401944 +#undef SERDES_L0_TM_ILL13_OFFSET +#define SERDES_L0_TM_ILL13_OFFSET 0XFD401994 +#undef SERDES_L1_TM_ILL13_OFFSET +#define SERDES_L1_TM_ILL13_OFFSET 0XFD405994 +#undef SERDES_L2_TM_MISC2_OFFSET +#define SERDES_L2_TM_MISC2_OFFSET 0XFD40989C +#undef SERDES_L2_TM_IQ_ILL1_OFFSET +#define SERDES_L2_TM_IQ_ILL1_OFFSET 0XFD4098F8 +#undef SERDES_L2_TM_IQ_ILL2_OFFSET +#define SERDES_L2_TM_IQ_ILL2_OFFSET 0XFD4098FC +#undef SERDES_L2_TM_ILL12_OFFSET +#define SERDES_L2_TM_ILL12_OFFSET 0XFD409990 +#undef SERDES_L2_TM_E_ILL1_OFFSET +#define SERDES_L2_TM_E_ILL1_OFFSET 0XFD409924 +#undef SERDES_L2_TM_E_ILL2_OFFSET +#define SERDES_L2_TM_E_ILL2_OFFSET 0XFD409928 +#undef SERDES_L2_TM_IQ_ILL3_OFFSET +#define SERDES_L2_TM_IQ_ILL3_OFFSET 0XFD409900 +#undef SERDES_L2_TM_E_ILL3_OFFSET +#define SERDES_L2_TM_E_ILL3_OFFSET 0XFD40992C +#undef SERDES_L2_TM_ILL8_OFFSET +#define SERDES_L2_TM_ILL8_OFFSET 0XFD409980 +#undef SERDES_L2_TM_IQ_ILL8_OFFSET +#define SERDES_L2_TM_IQ_ILL8_OFFSET 0XFD409914 +#undef SERDES_L2_TM_IQ_ILL9_OFFSET +#define SERDES_L2_TM_IQ_ILL9_OFFSET 0XFD409918 +#undef SERDES_L2_TM_E_ILL8_OFFSET +#define SERDES_L2_TM_E_ILL8_OFFSET 0XFD409940 +#undef SERDES_L2_TM_E_ILL9_OFFSET +#define SERDES_L2_TM_E_ILL9_OFFSET 0XFD409944 +#undef SERDES_L2_TM_ILL13_OFFSET +#define SERDES_L2_TM_ILL13_OFFSET 0XFD409994 +#undef SERDES_L3_TM_MISC2_OFFSET +#define SERDES_L3_TM_MISC2_OFFSET 0XFD40D89C +#undef SERDES_L3_TM_IQ_ILL1_OFFSET +#define SERDES_L3_TM_IQ_ILL1_OFFSET 0XFD40D8F8 +#undef SERDES_L3_TM_IQ_ILL2_OFFSET +#define SERDES_L3_TM_IQ_ILL2_OFFSET 0XFD40D8FC +#undef SERDES_L3_TM_ILL12_OFFSET +#define SERDES_L3_TM_ILL12_OFFSET 0XFD40D990 +#undef SERDES_L3_TM_E_ILL1_OFFSET +#define SERDES_L3_TM_E_ILL1_OFFSET 0XFD40D924 +#undef SERDES_L3_TM_E_ILL2_OFFSET +#define SERDES_L3_TM_E_ILL2_OFFSET 0XFD40D928 +#undef SERDES_L3_TM_ILL11_OFFSET +#define SERDES_L3_TM_ILL11_OFFSET 0XFD40D98C +#undef SERDES_L3_TM_IQ_ILL3_OFFSET +#define SERDES_L3_TM_IQ_ILL3_OFFSET 0XFD40D900 +#undef SERDES_L3_TM_E_ILL3_OFFSET +#define SERDES_L3_TM_E_ILL3_OFFSET 0XFD40D92C +#undef SERDES_L3_TM_ILL8_OFFSET +#define SERDES_L3_TM_ILL8_OFFSET 0XFD40D980 +#undef SERDES_L3_TM_IQ_ILL8_OFFSET +#define SERDES_L3_TM_IQ_ILL8_OFFSET 0XFD40D914 +#undef SERDES_L3_TM_IQ_ILL9_OFFSET +#define SERDES_L3_TM_IQ_ILL9_OFFSET 0XFD40D918 +#undef SERDES_L3_TM_E_ILL8_OFFSET +#define SERDES_L3_TM_E_ILL8_OFFSET 0XFD40D940 +#undef SERDES_L3_TM_E_ILL9_OFFSET +#define SERDES_L3_TM_E_ILL9_OFFSET 0XFD40D944 +#undef SERDES_L3_TM_ILL13_OFFSET +#define SERDES_L3_TM_ILL13_OFFSET 0XFD40D994 +#undef SERDES_L0_TM_DIG_10_OFFSET +#define SERDES_L0_TM_DIG_10_OFFSET 0XFD40107C +#undef SERDES_L1_TM_DIG_10_OFFSET +#define SERDES_L1_TM_DIG_10_OFFSET 0XFD40507C +#undef SERDES_L2_TM_DIG_10_OFFSET +#define SERDES_L2_TM_DIG_10_OFFSET 0XFD40907C +#undef SERDES_L3_TM_DIG_10_OFFSET +#define SERDES_L3_TM_DIG_10_OFFSET 0XFD40D07C +#undef SERDES_L0_TM_RST_DLY_OFFSET +#define SERDES_L0_TM_RST_DLY_OFFSET 0XFD4019A4 +#undef SERDES_L0_TM_ANA_BYP_15_OFFSET +#define SERDES_L0_TM_ANA_BYP_15_OFFSET 0XFD401038 +#undef SERDES_L0_TM_ANA_BYP_12_OFFSET +#define SERDES_L0_TM_ANA_BYP_12_OFFSET 0XFD40102C +#undef SERDES_L1_TM_RST_DLY_OFFSET +#define SERDES_L1_TM_RST_DLY_OFFSET 0XFD4059A4 +#undef SERDES_L1_TM_ANA_BYP_15_OFFSET +#define SERDES_L1_TM_ANA_BYP_15_OFFSET 0XFD405038 +#undef SERDES_L1_TM_ANA_BYP_12_OFFSET +#define SERDES_L1_TM_ANA_BYP_12_OFFSET 0XFD40502C +#undef SERDES_L2_TM_RST_DLY_OFFSET +#define SERDES_L2_TM_RST_DLY_OFFSET 0XFD4099A4 +#undef SERDES_L2_TM_ANA_BYP_15_OFFSET +#define SERDES_L2_TM_ANA_BYP_15_OFFSET 0XFD409038 +#undef SERDES_L2_TM_ANA_BYP_12_OFFSET +#define SERDES_L2_TM_ANA_BYP_12_OFFSET 0XFD40902C +#undef SERDES_L3_TM_RST_DLY_OFFSET +#define SERDES_L3_TM_RST_DLY_OFFSET 0XFD40D9A4 +#undef SERDES_L3_TM_ANA_BYP_15_OFFSET +#define SERDES_L3_TM_ANA_BYP_15_OFFSET 0XFD40D038 +#undef SERDES_L3_TM_ANA_BYP_12_OFFSET +#define SERDES_L3_TM_ANA_BYP_12_OFFSET 0XFD40D02C +#undef SERDES_L0_TM_MISC3_OFFSET +#define SERDES_L0_TM_MISC3_OFFSET 0XFD4019AC +#undef SERDES_L1_TM_MISC3_OFFSET +#define SERDES_L1_TM_MISC3_OFFSET 0XFD4059AC +#undef SERDES_L2_TM_MISC3_OFFSET +#define SERDES_L2_TM_MISC3_OFFSET 0XFD4099AC +#undef SERDES_L3_TM_MISC3_OFFSET +#define SERDES_L3_TM_MISC3_OFFSET 0XFD40D9AC +#undef SERDES_L0_TM_EQ11_OFFSET +#define SERDES_L0_TM_EQ11_OFFSET 0XFD401978 +#undef SERDES_L1_TM_EQ11_OFFSET +#define SERDES_L1_TM_EQ11_OFFSET 0XFD405978 +#undef SERDES_L2_TM_EQ11_OFFSET +#define SERDES_L2_TM_EQ11_OFFSET 0XFD409978 +#undef SERDES_L3_TM_EQ11_OFFSET +#define SERDES_L3_TM_EQ11_OFFSET 0XFD40D978 +#undef SIOU_ECO_0_OFFSET +#define SIOU_ECO_0_OFFSET 0XFD3D001C +#undef SERDES_ICM_CFG0_OFFSET +#define SERDES_ICM_CFG0_OFFSET 0XFD410010 +#undef SERDES_ICM_CFG1_OFFSET +#define SERDES_ICM_CFG1_OFFSET 0XFD410014 +#undef SERDES_L1_TXPMD_TM_45_OFFSET +#define SERDES_L1_TXPMD_TM_45_OFFSET 0XFD404CB4 +#undef SERDES_L1_TX_ANA_TM_118_OFFSET +#define SERDES_L1_TX_ANA_TM_118_OFFSET 0XFD4041D8 +#undef SERDES_L3_TX_ANA_TM_118_OFFSET +#define SERDES_L3_TX_ANA_TM_118_OFFSET 0XFD40C1D8 +#undef SERDES_L3_TM_CDR5_OFFSET +#define SERDES_L3_TM_CDR5_OFFSET 0XFD40DC14 +#undef SERDES_L3_TM_CDR16_OFFSET +#define SERDES_L3_TM_CDR16_OFFSET 0XFD40DC40 +#undef SERDES_L3_TM_EQ0_OFFSET +#define SERDES_L3_TM_EQ0_OFFSET 0XFD40D94C +#undef SERDES_L3_TM_EQ1_OFFSET +#define SERDES_L3_TM_EQ1_OFFSET 0XFD40D950 +#undef SERDES_L1_TXPMD_TM_48_OFFSET +#define SERDES_L1_TXPMD_TM_48_OFFSET 0XFD404CC0 +#undef SERDES_L1_TX_ANA_TM_18_OFFSET +#define SERDES_L1_TX_ANA_TM_18_OFFSET 0XFD404048 +#undef SERDES_L3_TX_ANA_TM_18_OFFSET +#define SERDES_L3_TX_ANA_TM_18_OFFSET 0XFD40C048 + +/* +* PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ +#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL +#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT +#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 0x0000000D +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 0 +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 0x0000001FU + +/* +* PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ +#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL +#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT +#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 0x00000008 +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 0 +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 0x0000001FU + +/* +* PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ +#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL +#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT +#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 0x0000000F +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 0 +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 0x0000001FU + +/* +* PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ +#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL +#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT +#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 0x0000000E +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 0 +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 0x0000001FU + +/* +* Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp + * ut. Set to 0 to select lane0 ref clock mux output. +*/ +#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL +#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT +#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 0x00000080U + +/* +* Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane1 ref clock mux output. +*/ +#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL +#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT +#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 0x00000080U + +/* +* Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli + * cer output from ref clock network +*/ +#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL +#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT +#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 0x00000080 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 3 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 0x00000008U + +/* +* Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane2 ref clock mux output. +*/ +#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL +#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT +#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 0x00000080U + +/* +* Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp + * ut. Set to 0 to select lane3 ref clock mux output. +*/ +#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL +#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT +#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 0x00000080U + +/* +* Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli + * cer output from ref clock network +*/ +#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL +#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT +#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 0x00000080 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 1 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 0x00000002U + +/* +* Enable/Disable coarse code satureation limiting logic +*/ +#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL +#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT +#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 0x00000000 +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 4 +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 0x00000010U + +/* +* Spread Spectrum No of Steps [7:0] +*/ +#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL +#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT +#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU + +/* +* Spread Spectrum No of Steps [10:8] +*/ +#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL +#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT +#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U + +/* +* Spread Spectrum No of Steps [7:0] +*/ +#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL +#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT +#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU + +/* +* Spread Spectrum No of Steps [10:8] +*/ +#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL +#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT +#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U + +/* +* Spread Spectrum No of Steps [7:0] +*/ +#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL +#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT +#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU + +/* +* Spread Spectrum No of Steps [10:8] +*/ +#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL +#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT +#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U + +/* +* Step Size for Spread Spectrum [7:0] +*/ +#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL +#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT +#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [15:8] +*/ +#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL +#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT +#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [23:16] +*/ +#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL +#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT +#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [25:24] +*/ +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U + +/* +* Enable/Disable test mode force on SS step size +*/ +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U + +/* +* Enable/Disable test mode force on SS no of steps +*/ +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT +#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U + +/* +* Step Size for Spread Spectrum [7:0] +*/ +#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL +#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT +#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [15:8] +*/ +#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL +#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT +#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [23:16] +*/ +#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL +#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT +#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [25:24] +*/ +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U + +/* +* Enable/Disable test mode force on SS step size +*/ +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U + +/* +* Enable/Disable test mode force on SS no of steps +*/ +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT +#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U + +/* +* Step Size for Spread Spectrum [7:0] +*/ +#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL +#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT +#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [15:8] +*/ +#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL +#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT +#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [23:16] +*/ +#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL +#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT +#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU + +/* +* Step Size for Spread Spectrum [25:24] +*/ +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U + +/* +* Enable/Disable test mode force on SS step size +*/ +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U + +/* +* Enable/Disable test mode force on SS no of steps +*/ +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U + +/* +* Enable test mode forcing on enable Spread Spectrum +*/ +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT +#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 7 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 0x00000080U + +/* +* Bypass Descrambler +*/ +#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL +#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT +#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U + +/* +* Enable Bypass for <1> TM_DIG_CTRL_6 +*/ +#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL +#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT +#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U + +/* +* Bypass scrambler signal +*/ +#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL +#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT +#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U + +/* +* Enable/disable scrambler bypass signal +*/ +#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL +#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT +#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U + +/* +* Enable test mode force on fractional mode enable +*/ +#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL +#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT +#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 0x00000000 +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 6 +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 0x00000040U + +/* +* Bypass 8b10b decoder +*/ +#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL +#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT +#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 3 +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 0x00000008U + +/* +* Enable Bypass for <3> TM_DIG_CTRL_6 +*/ +#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL +#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT +#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 2 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 0x00000004U + +/* +* Bypass Descrambler +*/ +#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL +#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT +#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U + +/* +* Enable Bypass for <1> TM_DIG_CTRL_6 +*/ +#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL +#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT +#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U + +/* +* Enable/disable encoder bypass signal +*/ +#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL +#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT +#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 3 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 0x00000008U + +/* +* Bypass scrambler signal +*/ +#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL +#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT +#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U + +/* +* Enable/disable scrambler bypass signal +*/ +#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL +#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT +#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U + +/* +* Spare- not used +*/ +#undef SERDES_L0_TM_AUX_0_BIT_2_DEFVAL +#undef SERDES_L0_TM_AUX_0_BIT_2_SHIFT +#undef SERDES_L0_TM_AUX_0_BIT_2_MASK +#define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 0x00000000 +#define SERDES_L0_TM_AUX_0_BIT_2_SHIFT 5 +#define SERDES_L0_TM_AUX_0_BIT_2_MASK 0x00000020U + +/* +* Spare- not used +*/ +#undef SERDES_L2_TM_AUX_0_BIT_2_DEFVAL +#undef SERDES_L2_TM_AUX_0_BIT_2_SHIFT +#undef SERDES_L2_TM_AUX_0_BIT_2_MASK +#define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 0x00000000 +#define SERDES_L2_TM_AUX_0_BIT_2_SHIFT 5 +#define SERDES_L2_TM_AUX_0_BIT_2_MASK 0x00000020U + +/* +* Enable Eye Surf +*/ +#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL +#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT +#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U + +/* +* Enable Eye Surf +*/ +#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL +#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT +#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U + +/* +* Enable Eye Surf +*/ +#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL +#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT +#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U + +/* +* Enable Eye Surf +*/ +#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL +#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT +#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U + +/* +* ILL calib counts BYPASSED with calcode bits +*/ +#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL +#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT +#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U + +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ +#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL +#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT +#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU + +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ +#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL +#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT +#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU + +/* +* G1A pll ctr bypass value +*/ +#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL +#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT +#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU + +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ +#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL +#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT +#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU + +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ +#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL +#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT +#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU + +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ +#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL +#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT +#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU + +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ +#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL +#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT +#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU + +/* +* ILL calibration code change wait time +*/ +#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL +#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT +#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU + +/* +* IQ ILL polytrim bypass value +*/ +#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL +#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT +#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU + +/* +* bypass IQ polytrim +*/ +#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL +#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT +#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U + +/* +* E ILL polytrim bypass value +*/ +#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL +#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT +#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU + +/* +* bypass E polytrim +*/ +#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL +#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT +#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U + +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL calib counts BYPASSED with calcode bits +*/ +#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL +#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT +#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U + +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ +#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL +#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT +#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU + +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ +#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL +#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT +#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU + +/* +* G1A pll ctr bypass value +*/ +#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL +#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT +#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU + +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ +#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL +#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT +#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU + +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ +#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL +#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT +#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU + +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ +#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL +#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT +#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU + +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ +#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL +#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT +#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU + +/* +* ILL calibration code change wait time +*/ +#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL +#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT +#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU + +/* +* IQ ILL polytrim bypass value +*/ +#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL +#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT +#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU + +/* +* bypass IQ polytrim +*/ +#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL +#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT +#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U + +/* +* E ILL polytrim bypass value +*/ +#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL +#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT +#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU + +/* +* bypass E polytrim +*/ +#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL +#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT +#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U + +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL calib counts BYPASSED with calcode bits +*/ +#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL +#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT +#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U + +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ +#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL +#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT +#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU + +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ +#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL +#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT +#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU + +/* +* G1A pll ctr bypass value +*/ +#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL +#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT +#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU + +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ +#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL +#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT +#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU + +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ +#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL +#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT +#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU + +/* +* G2A_PCIe1 PLL ctr bypass value +*/ +#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL +#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT +#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 4 +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 0x000000F0U + +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ +#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL +#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT +#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU + +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ +#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL +#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT +#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU + +/* +* ILL calibration code change wait time +*/ +#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL +#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT +#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU + +/* +* IQ ILL polytrim bypass value +*/ +#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL +#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT +#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU + +/* +* bypass IQ polytrim +*/ +#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL +#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT +#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U + +/* +* E ILL polytrim bypass value +*/ +#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL +#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT +#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU + +/* +* bypass E polytrim +*/ +#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL +#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT +#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U + +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* Delay apb reset by specified amount +*/ +#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL +#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT +#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ +#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL +#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT +#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ +#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL +#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT +#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U + +/* +* Delay apb reset by specified amount +*/ +#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL +#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT +#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ +#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL +#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT +#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ +#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL +#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT +#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U + +/* +* Delay apb reset by specified amount +*/ +#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL +#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT +#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ +#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL +#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT +#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ +#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL +#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT +#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U + +/* +* Delay apb reset by specified amount +*/ +#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL +#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT +#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ +#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL +#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT +#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U + +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ +#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL +#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT +#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* For future use +*/ +#undef SIOU_ECO_0_FIELD_DEFVAL +#undef SIOU_ECO_0_FIELD_SHIFT +#undef SIOU_ECO_0_FIELD_MASK +#define SIOU_ECO_0_FIELD_DEFVAL +#define SIOU_ECO_0_FIELD_SHIFT 0 +#define SIOU_ECO_0_FIELD_MASK 0xFFFFFFFFU + +/* +* Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused +*/ +#undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL +#undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT +#undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK +#define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 0 +#define SERDES_ICM_CFG0_L0_ICM_CFG_MASK 0x00000007U + +/* +* Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused +*/ +#undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL +#undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT +#undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK +#define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 4 +#define SERDES_ICM_CFG0_L1_ICM_CFG_MASK 0x00000070U + +/* +* Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused +*/ +#undef SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL +#undef SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT +#undef SERDES_ICM_CFG1_L2_ICM_CFG_MASK +#define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 0 +#define SERDES_ICM_CFG1_L2_ICM_CFG_MASK 0x00000007U + +/* +* Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, + * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused +*/ +#undef SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL +#undef SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT +#undef SERDES_ICM_CFG1_L3_ICM_CFG_MASK +#define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 4 +#define SERDES_ICM_CFG1_L3_ICM_CFG_MASK 0x00000070U + +/* +* Enable/disable DP post2 path +*/ +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 5 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 0x00000020U + +/* +* Override enable/disable of DP post2 path +*/ +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 4 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 0x00000010U + +/* +* Override enable/disable of DP post1 path +*/ +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 2 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 0x00000004U + +/* +* Enable/disable DP main path +*/ +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 1 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 0x00000002U + +/* +* Override enable/disable of DP main path +*/ +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT +#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 0 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 0x00000001U + +/* +* Test register force for enabling/disablign TX deemphasis bits <17:0> +*/ +#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL +#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT +#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U + +/* +* Test register force for enabling/disablign TX deemphasis bits <17:0> +*/ +#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL +#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT +#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U + +/* +* FPHL FSM accumulate cycles +*/ +#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL +#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT +#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 5 +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 0x000000E0U + +/* +* FFL Phase0 int gain aka 2ol SD update rate +*/ +#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL +#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT +#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 0 +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 0x0000001FU + +/* +* FFL Phase0 prop gain aka 1ol SD update rate +*/ +#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL +#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT +#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 0 +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 0x0000001FU + +/* +* EQ stg 2 controls BYPASSED +*/ +#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL +#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT +#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 5 +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 0x00000020U + +/* +* EQ STG2 RL PROG +*/ +#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL +#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT +#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 0 +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 0x00000003U + +/* +* EQ stg 2 preamp mode val +*/ +#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL +#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT +#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 2 +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 0x00000004U + +/* +* Margining factor value +*/ +#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL +#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT +#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 0 +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 0x0000001FU + +/* +* pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved +*/ +#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL +#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT +#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU + +/* +* pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved +*/ +#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL +#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT +#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef USB3_0_FPD_POWER_PRSNT_OFFSET +#define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080 +#undef USB3_0_FPD_PIPE_CLK_OFFSET +#define USB3_0_FPD_PIPE_CLK_OFFSET 0XFF9D007C +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef CRL_APB_RST_LPD_IOU0_OFFSET +#define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230 +#undef SIOU_SATA_MISC_CTRL_OFFSET +#define SIOU_SATA_MISC_CTRL_OFFSET 0XFD3D0100 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef DP_DP_PHY_RESET_OFFSET +#define DP_DP_PHY_RESET_OFFSET 0XFD4A0200 +#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET +#define DP_DP_TX_PHY_POWER_DOWN_OFFSET 0XFD4A0238 +#undef USB3_0_XHCI_GUSB2PHYCFG_OFFSET +#define USB3_0_XHCI_GUSB2PHYCFG_OFFSET 0XFE20C200 +#undef USB3_0_XHCI_GFLADJ_OFFSET +#define USB3_0_XHCI_GFLADJ_OFFSET 0XFE20C630 +#undef USB3_0_XHCI_GUCTL1_OFFSET +#define USB3_0_XHCI_GUCTL1_OFFSET 0XFE20C11C +#undef USB3_0_XHCI_GUCTL_OFFSET +#define USB3_0_XHCI_GUCTL_OFFSET 0XFE20C12C +#undef PCIE_ATTRIB_ATTR_25_OFFSET +#define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064 +#undef PCIE_ATTRIB_ATTR_7_OFFSET +#define PCIE_ATTRIB_ATTR_7_OFFSET 0XFD48001C +#undef PCIE_ATTRIB_ATTR_8_OFFSET +#define PCIE_ATTRIB_ATTR_8_OFFSET 0XFD480020 +#undef PCIE_ATTRIB_ATTR_9_OFFSET +#define PCIE_ATTRIB_ATTR_9_OFFSET 0XFD480024 +#undef PCIE_ATTRIB_ATTR_10_OFFSET +#define PCIE_ATTRIB_ATTR_10_OFFSET 0XFD480028 +#undef PCIE_ATTRIB_ATTR_11_OFFSET +#define PCIE_ATTRIB_ATTR_11_OFFSET 0XFD48002C +#undef PCIE_ATTRIB_ATTR_12_OFFSET +#define PCIE_ATTRIB_ATTR_12_OFFSET 0XFD480030 +#undef PCIE_ATTRIB_ATTR_13_OFFSET +#define PCIE_ATTRIB_ATTR_13_OFFSET 0XFD480034 +#undef PCIE_ATTRIB_ATTR_14_OFFSET +#define PCIE_ATTRIB_ATTR_14_OFFSET 0XFD480038 +#undef PCIE_ATTRIB_ATTR_15_OFFSET +#define PCIE_ATTRIB_ATTR_15_OFFSET 0XFD48003C +#undef PCIE_ATTRIB_ATTR_16_OFFSET +#define PCIE_ATTRIB_ATTR_16_OFFSET 0XFD480040 +#undef PCIE_ATTRIB_ATTR_17_OFFSET +#define PCIE_ATTRIB_ATTR_17_OFFSET 0XFD480044 +#undef PCIE_ATTRIB_ATTR_18_OFFSET +#define PCIE_ATTRIB_ATTR_18_OFFSET 0XFD480048 +#undef PCIE_ATTRIB_ATTR_27_OFFSET +#define PCIE_ATTRIB_ATTR_27_OFFSET 0XFD48006C +#undef PCIE_ATTRIB_ATTR_50_OFFSET +#define PCIE_ATTRIB_ATTR_50_OFFSET 0XFD4800C8 +#undef PCIE_ATTRIB_ATTR_105_OFFSET +#define PCIE_ATTRIB_ATTR_105_OFFSET 0XFD4801A4 +#undef PCIE_ATTRIB_ATTR_106_OFFSET +#define PCIE_ATTRIB_ATTR_106_OFFSET 0XFD4801A8 +#undef PCIE_ATTRIB_ATTR_107_OFFSET +#define PCIE_ATTRIB_ATTR_107_OFFSET 0XFD4801AC +#undef PCIE_ATTRIB_ATTR_108_OFFSET +#define PCIE_ATTRIB_ATTR_108_OFFSET 0XFD4801B0 +#undef PCIE_ATTRIB_ATTR_109_OFFSET +#define PCIE_ATTRIB_ATTR_109_OFFSET 0XFD4801B4 +#undef PCIE_ATTRIB_ATTR_34_OFFSET +#define PCIE_ATTRIB_ATTR_34_OFFSET 0XFD480088 +#undef PCIE_ATTRIB_ATTR_53_OFFSET +#define PCIE_ATTRIB_ATTR_53_OFFSET 0XFD4800D4 +#undef PCIE_ATTRIB_ATTR_41_OFFSET +#define PCIE_ATTRIB_ATTR_41_OFFSET 0XFD4800A4 +#undef PCIE_ATTRIB_ATTR_97_OFFSET +#define PCIE_ATTRIB_ATTR_97_OFFSET 0XFD480184 +#undef PCIE_ATTRIB_ATTR_100_OFFSET +#define PCIE_ATTRIB_ATTR_100_OFFSET 0XFD480190 +#undef PCIE_ATTRIB_ATTR_101_OFFSET +#define PCIE_ATTRIB_ATTR_101_OFFSET 0XFD480194 +#undef PCIE_ATTRIB_ATTR_37_OFFSET +#define PCIE_ATTRIB_ATTR_37_OFFSET 0XFD480094 +#undef PCIE_ATTRIB_ATTR_93_OFFSET +#define PCIE_ATTRIB_ATTR_93_OFFSET 0XFD480174 +#undef PCIE_ATTRIB_ID_OFFSET +#define PCIE_ATTRIB_ID_OFFSET 0XFD480200 +#undef PCIE_ATTRIB_SUBSYS_ID_OFFSET +#define PCIE_ATTRIB_SUBSYS_ID_OFFSET 0XFD480204 +#undef PCIE_ATTRIB_REV_ID_OFFSET +#define PCIE_ATTRIB_REV_ID_OFFSET 0XFD480208 +#undef PCIE_ATTRIB_ATTR_24_OFFSET +#define PCIE_ATTRIB_ATTR_24_OFFSET 0XFD480060 +#undef PCIE_ATTRIB_ATTR_25_OFFSET +#define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064 +#undef PCIE_ATTRIB_ATTR_4_OFFSET +#define PCIE_ATTRIB_ATTR_4_OFFSET 0XFD480010 +#undef PCIE_ATTRIB_ATTR_89_OFFSET +#define PCIE_ATTRIB_ATTR_89_OFFSET 0XFD480164 +#undef PCIE_ATTRIB_ATTR_79_OFFSET +#define PCIE_ATTRIB_ATTR_79_OFFSET 0XFD48013C +#undef PCIE_ATTRIB_ATTR_43_OFFSET +#define PCIE_ATTRIB_ATTR_43_OFFSET 0XFD4800AC +#undef PCIE_ATTRIB_ATTR_48_OFFSET +#define PCIE_ATTRIB_ATTR_48_OFFSET 0XFD4800C0 +#undef PCIE_ATTRIB_ATTR_46_OFFSET +#define PCIE_ATTRIB_ATTR_46_OFFSET 0XFD4800B8 +#undef PCIE_ATTRIB_ATTR_47_OFFSET +#define PCIE_ATTRIB_ATTR_47_OFFSET 0XFD4800BC +#undef PCIE_ATTRIB_ATTR_44_OFFSET +#define PCIE_ATTRIB_ATTR_44_OFFSET 0XFD4800B0 +#undef PCIE_ATTRIB_ATTR_45_OFFSET +#define PCIE_ATTRIB_ATTR_45_OFFSET 0XFD4800B4 +#undef PCIE_ATTRIB_CB_OFFSET +#define PCIE_ATTRIB_CB_OFFSET 0XFD48031C +#undef PCIE_ATTRIB_ATTR_35_OFFSET +#define PCIE_ATTRIB_ATTR_35_OFFSET 0XFD48008C +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 +#undef SATA_AHCI_VENDOR_PP2C_OFFSET +#define SATA_AHCI_VENDOR_PP2C_OFFSET 0XFD0C00AC +#undef SATA_AHCI_VENDOR_PP3C_OFFSET +#define SATA_AHCI_VENDOR_PP3C_OFFSET 0XFD0C00B0 +#undef SATA_AHCI_VENDOR_PP4C_OFFSET +#define SATA_AHCI_VENDOR_PP4C_OFFSET 0XFD0C00B4 +#undef SATA_AHCI_VENDOR_PP5C_OFFSET +#define SATA_AHCI_VENDOR_PP5C_OFFSET 0XFD0C00B8 + +/* +* USB 0 reset for control registers +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U + +/* +* This bit is used to choose between PIPE power present and 1'b1 +*/ +#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL +#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT +#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK +#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL +#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0 +#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U + +/* +* This bit is used to choose between PIPE clock coming from SerDes and the + * suspend clk +*/ +#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL +#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT +#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK +#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL +#define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 0 +#define USB3_0_FPD_PIPE_CLK_OPTION_MASK 0x00000001U + +/* +* USB 0 sleep circuit reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U + +/* +* USB 0 reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U + +/* +* GEM 3 reset +*/ +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U + +/* +* Sata PM clock control select +*/ +#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL +#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT +#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 0 +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 0x00000003U + +/* +* Sata block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U + +/* +* PCIE config reset +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U + +/* +* PCIE bridge block level reset (AXI interface) +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U + +/* +* Display Port block level reset (includes DPDMA) +*/ +#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U + +/* +* Set to '1' to hold the GT in reset. Clear to release. +*/ +#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL +#undef DP_DP_PHY_RESET_GT_RESET_SHIFT +#undef DP_DP_PHY_RESET_GT_RESET_MASK +#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 +#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 +#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U + +/* +* Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 +*/ +#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL +#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT +#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU + +/* +* USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc + * ks. Specifies the response time for a MAC request to the Packet FIFO Con + * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th + * e required values for the minimum SoC bus frequency of 60 MHz. USB turna + * round time is a critical certification criteria when using long cables a + * nd five hub levels. The required values for this field: - 4'h5: When the + * MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit + * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim + * e is not critical, this field can be set to a larger value. Note: This f + * ield is valid only in device mode. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 10 +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 0x00003C00U + +/* +* Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP + * I Transceiver Select signal (for HS) and the assertion of the TxValid si + * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima + * tely 2.5 us) is introduced from the time when the Transceiver Select is + * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the + * chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you + * enable the hibernation feature when the device core comes out of power- + * off, you must re-initialize this bit with the appropriate value because + * the core does not save and restore this bit value during hibernation. - + * This bit is valid only in device mode. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 9 +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 0x00000200U + +/* +* Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use + * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th + * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert + * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s + * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t + * he external PHY. Note: This bit must be set high for Port0 if PHY is use + * d. Note: In Device mode - Before issuing any device endpoint command whe + * n operating in 2.0 speeds, disable this bit and enable it after the comm + * and completes. Without disabling this bit, if a command is issued when t + * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of + * f, the command will not get completed. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 8 +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 0x00000100U + +/* +* USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T + * he application uses this bit to select a high-speed PHY or a full-speed + * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a + * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans + * ceiver. This bit is always 1, with Write Only access. If both interface + * types are selected in coreConsultant (that is, parameters' values are no + * t zero), the application uses this bit to select the active interface is + * active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv + * er is not supported. This bit always reads as 1'b0. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U + +/* +* Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend + * mode if Suspend conditions are valid. For DRD/OTG configurations, it is + * recommended that this bit is set to 0 during coreConsultant configurati + * on. If it is set to 1, then the application must clear this bit after po + * wer-on reset. Application needs to set it to 1 after the core initializa + * tion completes. For all other configurations, this bit can be set to 1 d + * uring core configuration. Note: - In host mode, on reset, this bit is se + * t to 1. Software can override this bit after reset. - In device mode, be + * fore issuing any device endpoint command when operating in 2.0 speeds, d + * isable this bit and enable it after the command completes. If you issue + * a command without disabling this bit when the device is in L2 state and + * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c + * ompleted. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 6 +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 0x00000040U + +/* +* Full-Speed Serial Interface Select (FSIntf) The application uses this bi + * t to select a unidirectional or bidirectional USB 1.1 full-speed serial + * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in + * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir + * ectional full-speed serial interface. This bit is set to 0 with Read Onl + * y access. Note: USB 1.1 full-speed serial interface is not supported. Th + * is bit always reads as 1'b0. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 5 +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 0x00000020U + +/* +* ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se + * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int + * erface This bit is writable only if UTMI+ and ULPI is specified for High + * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_ + * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o + * n the interface selected through DWC_USB3_HSPHY_INTERFACE. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 4 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 0x00000010U + +/* +* PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi + * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte + * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en + * abled 2.0 ports must have the same clock frequency as Port0 clock freque + * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge + * ther for different ports at the same time (that is, all the ports must b + * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If + * any of the USB 2.0 ports is selected as ULPI port for operation, then a + * ll the USB 2.0 ports must be operating at 60 MHz. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 3 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 0x00000008U + +/* +* HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat + * ed by the application in this field, is multiplied by a bit-time factor; + * this factor is added to the high-speed/full-speed interpacket timeout d + * uration in the core to account for additional delays introduced by the P + * HY. This may be required, since the delay introduced by the PHY in gener + * ating the linestate condition may vary among PHYs. The USB standard time + * out value for high-speed operation is 736 to 816 (inclusive) bit times. + * The USB standard timeout value for full-speed operation is 16 to 18 (inc + * lusive) bit times. The application must program this field based on the + * speed of connection. The number of bit times added per PHY clock are: Hi + * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P + * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0. + * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc + * k = 0.25 bit times +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 0 +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 0x00000007U + +/* +* ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive + * 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char + * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl + * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3) +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT 17 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK 0x00020000U + +/* +* This field indicates the frame length adjustment to be applied when SOF/ + * ITP counter is running on the ref_clk. This register value is used to ad + * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i + * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must + * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t + * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows: + * FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe + * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege + * r value of the ref_clk period got by truncating the decimal (fractional) + * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c + * lk_period is the ref_clk period including the fractional value. Examples + * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA + * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin + * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE + * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2 + * 0.8333 = 5208 (ignoring the fractional value) +*/ +#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL +#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT +#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 0x00000000 +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8 +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U + +/* +* When this bit is set to '0', termsel, xcvrsel will become 0 during end o + * f resume while the opmode will become 0 once controller completes end of + * resume and enters U0 state (2 separate commandswill be issued). When th + * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during + * end of resume itself (only 1 command will be issued) +*/ +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT 10 +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK 0x00000400U + +/* +* Reserved +*/ +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_MASK +#define USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT 9 +#define USB3_0_XHCI_GUCTL1_RESERVED_9_MASK 0x00000200U + +/* +* Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th + * e Auto Retry feature. For IN transfers (non-isochronous) that encounter + * data packets with CRC errors or internal overrun scenarios, the auto ret + * ry feature causes the Host core to reply to the device with a non-termin + * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N + * umP != 0). If the Auto Retry feature is disabled (default), the core wil + * l respond with a terminating retry ACK (that is, an ACK transaction pack + * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut + * o Retry Enabled Note: This bit is also applicable to the device mode. +*/ +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT 14 +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK 0x00004000U + +/* +* If TRUE Completion Timeout Disable is supported. This is required to be + * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi + * ce Capability 2 [4]; EP=0x0001; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL +#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT +#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 9 +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 0x00000200U + +/* +* Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0x0004; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL +#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT +#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 0 +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 0x0000FFFFU + +/* +* Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0xFFF0; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL +#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT +#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 0 +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 0x0000FFFFU + +/* +* Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL +#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT +#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 0 +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 0x0000FFFFU + +/* +* Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL +#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT +#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 0 +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFFF +*/ +#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL +#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT +#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 0 +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0x00FF +*/ +#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL +#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT +#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 0 +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL +#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT +#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 0 +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0xFFFF +*/ +#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL +#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT +#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 0 +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFF0 +*/ +#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL +#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT +#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 0 +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0xFFF0 +*/ +#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL +#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT +#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 0 +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 +*/ +#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL +#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT +#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 0 +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 0x0000FFFFU + +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 +*/ +#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL +#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT +#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 0 +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 0x0000FFFFU + +/* +* Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1 + * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa + * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo + * rted; EP=0x0001; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL +#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT +#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 0x00002138 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 8 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 0x00000700U + +/* +* Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca + * n withstand on transitions from L1 state to L0 (if L1 state supported). + * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to + * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For + * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL +#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT +#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 0x00002138 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 3 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 0x00000038U + +/* +* Identifies the type of device/port as follows: 0000b PCI Express Endpoin + * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P + * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110 + * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X + * Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre + * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM + * _FACING settings.; EP=0x0000; RP=0x0004 +*/ +#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL +#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT +#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 0x00009C02 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 4 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 0x000000F0U + +/* +* PCIe Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x009C; + * RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL +#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT +#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 0x00009C02 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 8 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 0x0000FF00U + +/* +* Number of credits that should be advertised for Completion data received + * on Virtual Channel 0. The bytes advertised must be less than or equal t + * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD +*/ +#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL +#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT +#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 0x000007FFU + +/* +* Number of credits that should be advertised for Completion headers recei + * ved on Virtual Channel 0. The sum of the posted, non posted, and complet + * ion header credits must be <= 80; EP=0x0048; RP=0x0024 +*/ +#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL +#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT +#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 0x00000248 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 0x0000007FU + +/* +* Number of credits that should be advertised for Non-Posted headers recei + * ved on Virtual Channel 0. The number of non posted data credits advertis + * ed by the block is equal to the number of non posted header credits. The + * sum of the posted, non posted, and completion header credits must be <= + * 80; EP=0x0004; RP=0x000C +*/ +#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL +#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT +#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 0x00000248 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 7 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 0x00003F80U + +/* +* Number of credits that should be advertised for Non-Posted data received + * on Virtual Channel 0. The number of non posted data credits advertised + * by the block is equal to two times the number of non posted header credi + * ts if atomic operations are supported or is equal to the number of non p + * osted header credits if atomic operations are not supported. The bytes a + * dvertised must be less than or equal to the bram bytes available. See VC + * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 +*/ +#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL +#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT +#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 0x000007FFU + +/* +* Number of credits that should be advertised for Posted data received on + * Virtual Channel 0. The bytes advertised must be less than or equal to th + * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 +*/ +#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL +#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT +#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 0x000007FFU + +/* +* Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_ + * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL +#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT +#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 15 +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 0x00008000U + +/* +* Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim + * TRUE == trim.; EP=0x0001; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL +#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT +#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 14 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 0x00004000U + +/* +* Enables ECRC check on received TLP's 0 == don't check 1 == always check + * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP= + * 0x0003; RP=0x0003 +*/ +#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL +#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT +#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 12 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 0x00003000U + +/* +* Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). + * Calculated from max payload size supported and the number of brams conf + * igured for transmit; EP=0x001C; RP=0x001C +*/ +#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL +#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT +#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 7 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 0x00000F80U + +/* +* Number of credits that should be advertised for Posted headers received + * on Virtual Channel 0. The sum of the posted, non posted, and completion + * header credits must be <= 80; EP=0x0004; RP=0x0020 +*/ +#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL +#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT +#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 0x0000007FU + +/* +* Specifies values to be transferred to Header Type register. Bit 7 should + * be set to '0' indicating single-function device. Bit 0 identifies heade + * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; + * RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL +#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT +#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 0x00000100 +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 0x000000FFU + +/* +* PM Capability's Next Capability Offset pointer to the next item in the c + * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP + * =0x0060 +*/ +#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL +#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT +#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 0x00003D48 +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 0 +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 0x000000FFU + +/* +* MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont + * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure; + * EP=0x0000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 9 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 0x00000200U + +/* +* Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U + +/* +* MSI Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x0060; R + * P=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 0 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 0x000000FFU + +/* +* Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT +#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U + +/* +* Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b + * x4, 001000b x8.; EP=0x0004; RP=0x0004 +*/ +#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL +#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT +#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 0x00000104 +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 0x0000003FU + +/* +* Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1 + * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004 +*/ +#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL +#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT +#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 0x00000104 +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 6 +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 0x00000FC0U + +/* +* TRUE specifies upstream-facing port. FALSE specifies downstream-facing p + * ort.; EP=0x0001; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL +#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT +#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 0x000000F0 +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 6 +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 0x00000040U + +/* +* Enable the routing of message TLPs to the user through the TRN RX interf + * ace. A bit value of 1 enables routing of the message TLP to the user. Me + * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 + * - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I + * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit + * 10 PME_Turn_Off; EP=0x0000; RP=0x07FF +*/ +#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL +#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT +#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 5 +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 0x0000FFE0U + +/* +* Disable BAR filtering. Does not change the behavior of the bar hit outpu + * ts; EP=0x0000; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL +#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT +#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 1 +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 0x00000002U + +/* +* Link Bandwidth notification capability. Indicates support for the link b + * andwidth notification status and interrupt mechanism. Required for Root. + * ; EP=0x0000; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 0x000009FF +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 9 +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 0x00000200U + +/* +* Maximum Link Speed. Valid settings are: 0001b [2.5 GT/s], 0010b [5.0 GT/ + * s and 2.5 GT/s].; EP=0x0002; RP=0x0002 +*/ +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_MAX_LINK_SPEED_DEFVAL +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_MAX_LINK_SPEED_SHIFT +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_MAX_LINK_SPEED_MASK +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_MAX_LINK_SPEED_DEFVAL 0x000009FF +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_MAX_LINK_SPEED_SHIFT 10 +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_MAX_LINK_SPEED_MASK 0x00003C00U + +/* +* Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op + * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001 + * ; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT +#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14 +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U + +/* +* Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value + * (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU + * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL +#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT +#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 15 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 0x00008000U + +/* +* Sets a user-defined timeout for the Replay Timer to force cause the retr + * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_ + * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att + * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.; + * EP=0x0000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL +#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT +#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 0 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 0x00007FFFU + +/* +* Device ID for the the PCIe Cap Structure Device ID field +*/ +#undef PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL +#undef PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT +#undef PCIE_ATTRIB_ID_CFG_DEV_ID_MASK +#define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 0x10EE7024 +#define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 0 +#define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 0x0000FFFFU + +/* +* Vendor ID for the PCIe Cap Structure Vendor ID field +*/ +#undef PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL +#undef PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT +#undef PCIE_ATTRIB_ID_CFG_VEND_ID_MASK +#define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 0x10EE7024 +#define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 16 +#define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 0xFFFF0000U + +/* +* Subsystem ID for the the PCIe Cap Structure Subsystem ID field +*/ +#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL +#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT +#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 0x10EE0007 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 0 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 0x0000FFFFU + +/* +* Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field +*/ +#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL +#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT +#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 0x10EE0007 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 16 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 0xFFFF0000U + +/* +* Revision ID for the the PCIe Cap Structure +*/ +#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL +#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT +#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 0 +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 0x000000FFU + +/* +* Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000 +*/ +#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL +#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT +#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 0x0000FFFFU + +/* +* Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006 +*/ +#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL +#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT +#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 0x000000FFU + +/* +* INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] + * to be hardwired to 0.; EP=0x0001; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL +#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT +#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 8 +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 0x00000100U + +/* +* Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL +#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT +#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U + +/* +* Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL +#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT +#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U + +/* +* VSEC's Next Capability Offset pointer to the next item in the capabiliti + * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140 +*/ +#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL +#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT +#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 0x00002281 +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 1 +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 0x00001FFEU + +/* +* CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the + * Root Capabilities register.; EP=0x0000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL +#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT +#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 5 +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 0x00000020U + +/* +* Indicates that the MSIX structures exists. If this is FALSE, then the MS + * IX structure cannot be accessed via either the link or the management po + * rt.; EP=0x0001; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL +#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT +#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100 +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U + +/* +* MSI-X Table Size. This value is transferred to the MSI-X Message Control + * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does + * not implement the table; that must be implemented in user logic.; EP=0x0 + * 003; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL +#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT +#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 0x000007FFU + +/* +* MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT +#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x0000FFFFU + +/* +* MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT +#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x00001FFFU + +/* +* MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL +#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT +#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFFFU + +/* +* MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL +#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT +#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 0x00008000 +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 3 +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFF8U + +/* +* DT837748 Enable +*/ +#undef PCIE_ATTRIB_CB_CB1_DEFVAL +#undef PCIE_ATTRIB_CB_CB1_SHIFT +#undef PCIE_ATTRIB_CB_CB1_MASK +#define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001 +#define PCIE_ATTRIB_CB_CB1_SHIFT 1 +#define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U + +/* +* Active State PM Support. Indicates the level of active state power manag + * ement supported by the selected PCI Express Link, encoded as follows: 0 + * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte + * d.; EP=0x0001; RP=0x0001 +*/ +#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL +#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT +#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12 +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U + +/* +* Data Link Layer Link Active status notification is supported. This is op + * tional for Upstream ports.; EP=0x0000; RP=0x0000 +*/ +#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_DEFVAL +#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_SHIFT +#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_MASK +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_DEFVAL 0x00001FFD +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_SHIFT 15 +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_MASK 0x00008000U + +/* +* PCIE control block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U + +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U + +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU + +/* +* Status Read value of PLL Lock +*/ +#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL +#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT +#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L0_PLL_STATUS_READ_1_OFFSET 0XFD4023E4 + +/* +* Status Read value of PLL Lock +*/ +#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL +#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT +#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L1_PLL_STATUS_READ_1_OFFSET 0XFD4063E4 + +/* +* Status Read value of PLL Lock +*/ +#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL +#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT +#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L2_PLL_STATUS_READ_1_OFFSET 0XFD40A3E4 + +/* +* Status Read value of PLL Lock +*/ +#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL +#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT +#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L3_PLL_STATUS_READ_1_OFFSET 0XFD40E3E4 + +/* +* CIBGMN: COMINIT Burst Gap Minimum. +*/ +#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL +#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT +#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 0 +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 0x000000FFU + +/* +* CIBGMX: COMINIT Burst Gap Maximum. +*/ +#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL +#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT +#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 8 +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 0x0000FF00U + +/* +* CIBGN: COMINIT Burst Gap Nominal. +*/ +#undef SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL +#undef SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT +#undef SATA_AHCI_VENDOR_PP2C_CIBGN_MASK +#define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 16 +#define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 0x00FF0000U + +/* +* CINMP: COMINIT Negate Minimum Period. +*/ +#undef SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL +#undef SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT +#undef SATA_AHCI_VENDOR_PP2C_CINMP_MASK +#define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 24 +#define SATA_AHCI_VENDOR_PP2C_CINMP_MASK 0xFF000000U + +/* +* CWBGMN: COMWAKE Burst Gap Minimum. +*/ +#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL +#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT +#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 0 +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 0x000000FFU + +/* +* CWBGMX: COMWAKE Burst Gap Maximum. +*/ +#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL +#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT +#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 8 +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 0x0000FF00U + +/* +* CWBGN: COMWAKE Burst Gap Nominal. +*/ +#undef SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL +#undef SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT +#undef SATA_AHCI_VENDOR_PP3C_CWBGN_MASK +#define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 16 +#define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 0x00FF0000U + +/* +* CWNMP: COMWAKE Negate Minimum Period. +*/ +#undef SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL +#undef SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT +#undef SATA_AHCI_VENDOR_PP3C_CWNMP_MASK +#define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 24 +#define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 0xFF000000U + +/* +* BMX: COM Burst Maximum. +*/ +#undef SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL +#undef SATA_AHCI_VENDOR_PP4C_BMX_SHIFT +#undef SATA_AHCI_VENDOR_PP4C_BMX_MASK +#define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 0 +#define SATA_AHCI_VENDOR_PP4C_BMX_MASK 0x000000FFU + +/* +* BNM: COM Burst Nominal. +*/ +#undef SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL +#undef SATA_AHCI_VENDOR_PP4C_BNM_SHIFT +#undef SATA_AHCI_VENDOR_PP4C_BNM_MASK +#define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 8 +#define SATA_AHCI_VENDOR_PP4C_BNM_MASK 0x0000FF00U + +/* +* SFD: Signal Failure Detection, if the signal detection de-asserts for a + * time greater than this then the OOB detector will determine this is a li + * ne idle and cause the PhyInit state machine to exit the Phy Ready State. + * A value of zero disables the Signal Failure Detector. The value is base + * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving + * a nominal time of 500ns based on a 150MHz PMCLK. +*/ +#undef SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL +#undef SATA_AHCI_VENDOR_PP4C_SFD_SHIFT +#undef SATA_AHCI_VENDOR_PP4C_SFD_MASK +#define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 16 +#define SATA_AHCI_VENDOR_PP4C_SFD_MASK 0x00FF0000U + +/* +* PTST: Partial to Slumber timer value, specific delay the controller shou + * ld apply while in partial before entering slumber. The value is bases on + * the system clock divided by 128, total delay = (Sys Clock Period) * PTS + * T * 128 +*/ +#undef SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL +#undef SATA_AHCI_VENDOR_PP4C_PTST_SHIFT +#undef SATA_AHCI_VENDOR_PP4C_PTST_MASK +#define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 24 +#define SATA_AHCI_VENDOR_PP4C_PTST_MASK 0xFF000000U + +/* +* RIT: Retry Interval Timer. The calculated value divided by two, the lowe + * r digit of precision is not needed. +*/ +#undef SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL +#undef SATA_AHCI_VENDOR_PP5C_RIT_SHIFT +#undef SATA_AHCI_VENDOR_PP5C_RIT_MASK +#define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 0x3FFC96A4 +#define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 0 +#define SATA_AHCI_VENDOR_PP5C_RIT_MASK 0x000FFFFFU + +/* +* RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev + * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a + * fast SERDES it is suggested that this value be 54.2us / 4 +*/ +#undef SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL +#undef SATA_AHCI_VENDOR_PP5C_RCT_SHIFT +#undef SATA_AHCI_VENDOR_PP5C_RCT_MASK +#define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 0x3FFC96A4 +#define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 20 +#define SATA_AHCI_VENDOR_PP5C_RCT_MASK 0xFFF00000U +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef CRL_APB_RST_LPD_IOU0_OFFSET +#define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET +#define DP_DP_TX_PHY_POWER_DOWN_OFFSET 0XFD4A0238 +#undef DP_DP_PHY_RESET_OFFSET +#define DP_DP_PHY_RESET_OFFSET 0XFD4A0200 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 + +/* +* USB 0 reset for control registers +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U + +/* +* USB 0 sleep circuit reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U + +/* +* USB 0 reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U + +/* +* GEM 3 reset +*/ +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U + +/* +* Sata block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U + +/* +* PCIE config reset +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U + +/* +* PCIE control block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U + +/* +* PCIE bridge block level reset (AXI interface) +*/ +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U + +/* +* Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 +*/ +#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL +#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT +#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU + +/* +* Set to '1' to hold the GT in reset. Clear to release. +*/ +#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL +#undef DP_DP_PHY_RESET_GT_RESET_SHIFT +#undef DP_DP_PHY_RESET_GT_RESET_MASK +#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 +#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 +#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U + +/* +* Display Port block level reset (includes DPDMA) +*/ +#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U +#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET 0XFFD80118 +#undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET +#define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET 0XFFD80120 + +/* +* Power-up Request Interrupt Enable for PL +*/ +#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL +#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT +#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 0x00800000U + +/* +* Power-up Request Trigger for PL +*/ +#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL +#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT +#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 0x00800000U + +/* +* Power-up Request Status for PL +*/ +#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL +#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT +#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 0x00800000U +#define PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET 0XFFD80110 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef LPD_SLCR_AFI_FS_OFFSET +#define LPD_SLCR_AFI_FS_OFFSET 0XFF419000 +#undef AFIFM2_AFIFM_RDCTRL_OFFSET +#define AFIFM2_AFIFM_RDCTRL_OFFSET 0XFD380000 +#undef AFIFM2_AFIFM_WRCTRL_OFFSET +#define AFIFM2_AFIFM_WRCTRL_OFFSET 0XFD380014 + +/* +* AF_FM0 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT 7 +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK 0x00000080U + +/* +* AF_FM1 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT 8 +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK 0x00000100U + +/* +* AF_FM2 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT 9 +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK 0x00000200U + +/* +* AF_FM3 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT 10 +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK 0x00000400U + +/* +* AF_FM4 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT 11 +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK 0x00000800U + +/* +* AF_FM5 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT 12 +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK 0x00001000U + +/* +* AFI FM 6 +*/ +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT 19 +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK 0x00080000U + +/* +* Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved +*/ +#undef LPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL +#undef LPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT +#undef LPD_SLCR_AFI_FS_DW_SS2_SEL_MASK +#define LPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL 0x00000200 +#define LPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT 8 +#define LPD_SLCR_AFI_FS_DW_SS2_SEL_MASK 0x00000300U + +/* +* Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b + * 10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128-bit enabled +*/ +#undef AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL +#undef AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT +#undef AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_MASK +#define AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0 +#define AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT 0 +#define AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_MASK 0x00000003U + +/* +* Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2' + * b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128-bit enabled +*/ +#undef AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL +#undef AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT +#undef AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_MASK +#define AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0 +#define AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT 0 +#define AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_MASK 0x00000003U +#undef GPIO_MASK_DATA_5_MSW_OFFSET +#define GPIO_MASK_DATA_5_MSW_OFFSET 0XFF0A002C +#undef GPIO_DIRM_5_OFFSET +#define GPIO_DIRM_5_OFFSET 0XFF0A0344 +#undef GPIO_OEN_5_OFFSET +#define GPIO_OEN_5_OFFSET 0XFF0A0348 +#undef GPIO_DATA_5_OFFSET +#define GPIO_DATA_5_OFFSET 0XFF0A0054 +#undef GPIO_DATA_5_OFFSET +#define GPIO_DATA_5_OFFSET 0XFF0A0054 +#undef GPIO_DATA_5_OFFSET +#define GPIO_DATA_5_OFFSET 0XFF0A0054 + +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL +#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT +#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 16 +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 0xFFFF0000U + +/* +* Operation is the same as DIRM_0[DIRECTION_0] +*/ +#undef GPIO_DIRM_5_DIRECTION_5_DEFVAL +#undef GPIO_DIRM_5_DIRECTION_5_SHIFT +#undef GPIO_DIRM_5_DIRECTION_5_MASK +#define GPIO_DIRM_5_DIRECTION_5_DEFVAL +#define GPIO_DIRM_5_DIRECTION_5_SHIFT 0 +#define GPIO_DIRM_5_DIRECTION_5_MASK 0xFFFFFFFFU + +/* +* Operation is the same as OEN_0[OP_ENABLE_0] +*/ +#undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL +#undef GPIO_OEN_5_OP_ENABLE_5_SHIFT +#undef GPIO_OEN_5_OP_ENABLE_5_MASK +#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL +#define GPIO_OEN_5_OP_ENABLE_5_SHIFT 0 +#define GPIO_OEN_5_OP_ENABLE_5_MASK 0xFFFFFFFFU + +/* +* Output Data +*/ +#undef GPIO_DATA_5_DATA_5_DEFVAL +#undef GPIO_DATA_5_DATA_5_SHIFT +#undef GPIO_DATA_5_DATA_5_MASK +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU + +/* +* Output Data +*/ +#undef GPIO_DATA_5_DATA_5_DEFVAL +#undef GPIO_DATA_5_DATA_5_SHIFT +#undef GPIO_DATA_5_DATA_5_MASK +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU + +/* +* Output Data +*/ +#undef GPIO_DATA_5_DATA_5_DEFVAL +#undef GPIO_DATA_5_DATA_5_SHIFT +#undef GPIO_DATA_5_DATA_5_MASK +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU +#ifdef __cplusplus +extern "C" { +#endif + int psu_init (); + unsigned long psu_ps_pl_isolation_removal_data(); + unsigned long psu_ps_pl_reset_config_data(); + int psu_protection(); + int psu_fpd_protection(); + int psu_ocm_protection(); + int psu_ddr_protection(); + int psu_lpd_protection(); + int psu_protection_lock(); + unsigned long psu_ddr_qos_init_data(void); + unsigned long psu_apply_master_tz(); +#ifdef __cplusplus +} +#endif diff --git a/Petalinux/project-spec/hw-description/system.xsa b/Petalinux/project-spec/hw-description/system.xsa new file mode 100644 index 0000000..c792f43 Binary files /dev/null and b/Petalinux/project-spec/hw-description/system.xsa differ diff --git a/Petalinux/project-spec/meta-user/COPYING.MIT b/Petalinux/project-spec/meta-user/COPYING.MIT new file mode 100644 index 0000000..89de354 --- /dev/null +++ b/Petalinux/project-spec/meta-user/COPYING.MIT @@ -0,0 +1,17 @@ +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. diff --git a/Petalinux/project-spec/meta-user/README b/Petalinux/project-spec/meta-user/README new file mode 100644 index 0000000..5a5b9b9 --- /dev/null +++ b/Petalinux/project-spec/meta-user/README @@ -0,0 +1,64 @@ +This README file contains information on the contents of the +meta-user layer. + +Please see the corresponding sections below for details. + + +Dependencies +============ + +This layer depends on: + + URI: git://git.openembedded.org/bitbake + branch: master + + URI: git://git.openembedded.org/openembedded-core + layers: meta + branch: master + + URI: git://git.yoctoproject.org/xxxx + layers: xxxx + branch: master + + +Patches +======= + +Please submit any patches against the meta-user layer to the +xxxx mailing list (xxxx@zzzz.org) and cc: the maintainer: + +Maintainer: XXX YYYYYY + + +Table of Contents +================= + + I. Adding the meta-user layer to your build + II. Misc + + +I. Adding the meta-user layer to your build +================================================= + +--- replace with specific instructions for the meta-user layer --- + +In order to use this layer, you need to make the build system aware of +it. + +Assuming the meta-user layer exists at the top-level of your +yocto build tree, you can add it to the build system by adding the +location of the meta-user layer to bblayers.conf, along with any +other layers needed. e.g.: + + BBLAYERS ?= " \ + /path/to/yocto/meta \ + /path/to/yocto/meta-poky \ + /path/to/yocto/meta-yocto-bsp \ + /path/to/yocto/meta-meta-user \ + " + + +II. Misc +======== + +--- replace with specific information about the meta-user layer --- diff --git a/Petalinux/project-spec/meta-user/conf/layer.conf b/Petalinux/project-spec/meta-user/conf/layer.conf new file mode 100644 index 0000000..dfac84b --- /dev/null +++ b/Petalinux/project-spec/meta-user/conf/layer.conf @@ -0,0 +1,11 @@ +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have recipes-* directories, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ + ${LAYERDIR}/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "meta-user" +BBFILE_PATTERN_meta-user = "^${LAYERDIR}/" +BBFILE_PRIORITY_meta-user = "6" +LAYERSERIES_COMPAT_meta-user = "zeus" diff --git a/Petalinux/project-spec/meta-user/conf/petalinuxbsp.conf b/Petalinux/project-spec/meta-user/conf/petalinuxbsp.conf new file mode 100644 index 0000000..dd433fa --- /dev/null +++ b/Petalinux/project-spec/meta-user/conf/petalinuxbsp.conf @@ -0,0 +1,5 @@ +#User Configuration + +#OE_TERMINAL = "tmux" + +IMAGE_BOOT_FILES_zynqmp = "BOOT.BIN boot.scr Image rootfs.cpio.gz.u-boot" diff --git a/Petalinux/project-spec/meta-user/conf/user-rootfsconfig b/Petalinux/project-spec/meta-user/conf/user-rootfsconfig new file mode 100644 index 0000000..467fd41 --- /dev/null +++ b/Petalinux/project-spec/meta-user/conf/user-rootfsconfig @@ -0,0 +1,11 @@ +#Note: Mention Each package in individual line +#These packages will get added into rootfs menu entry + +CONFIG_gpio-demo +CONFIG_peekpoke +CONFIG_myapp-init + +CONFIG_iperf3 +CONFIG_ethtool +CONFIG_phytool + diff --git a/Petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/Makefile b/Petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/Makefile new file mode 100644 index 0000000..9106be1 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/Makefile @@ -0,0 +1,14 @@ +APP = gpio-demo + +# Add any other object files to this list below +APP_OBJS = gpio-demo.o + +all: $(APP) + +$(APP): $(APP_OBJS) + $(CC) $(LDFLAGS) -o $@ $(APP_OBJS) $(LDLIBS) + +clean: + -rm -f $(APP) *.elf *.gdb *.o + + diff --git a/Petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c b/Petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c new file mode 100644 index 0000000..4e17779 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c @@ -0,0 +1,355 @@ +/* +* +* gpio-demo app +* +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person +* obtaining a copy of this software and associated documentation +* files (the "Software"), to deal in the Software without restriction, +* including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, +* and to permit persons to whom the Software is furnished to do so, +* subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in this +* Software without prior written authorization from Xilinx. +* +*/ + +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_ROOT "/sys/class/gpio" +#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0])) + +static enum {NONE, IN, OUT, CYLON, KIT} gpio_opt = NONE; + +static const unsigned long cylon[] = { + 0x00000080, 0x00000040, 0x00000020, 0x00000010, + 0x00000008, 0x00000004, 0x00000002, 0x00000001, + 0x00000002, 0x00000004, 0x00000008, + 0x00000010, 0x00000020, 0x00000040, 0x00000080, +}; + +static const unsigned long kit[] = { + 0x000000e0, 0x00000070, 0x00000038, 0x0000001c, + 0x0000000e, 0x00000007, 0x00000003, 0x00000001, + 0x00000003, 0x00000007, 0x0000000e, + 0x0000001c, 0x00000038, 0x00000070, 0x000000e0, +}; + +static int gl_gpio_base = 0; + +static void usage (char *argv0) +{ + char *basename = strrchr(argv0, '/'); + if (!basename) + basename = argv0; + + fprintf(stderr, + "Usage: %s [-g GPIO_BASE] COMMAND\n" + "\twhere COMMAND is one of:\n" + "\t\t-i\t\tInput value from GPIO and print it\n" + "\t\t-o\tVALUE\tOutput value to GPIO\n" + "\t\t-c\t\tCylon test pattern\n" + "\t\t-k\t\t KIT test pattern\n" + "\tGPIO_BASE indicates which GPIO chip to talk to (The number can be \n" + "\tfound at /sys/class/gpio/gpiochipN).\n" + "\tThe highest gpiochipN is the first gpio listed in the dts file, \n" + "\tand the lowest gpiochipN is the last gpio listed in the dts file.\n" + "\tE.g.If the gpiochip240 is the LED_8bit gpio, and I want to output '1' \n" + "\tto the LED_8bit gpio, the command should be:\n" + "\t\tgpio-demo -g 240 -o 1\n" + "\n" + "\tgpio-demo written by Xilinx Inc.\n" + "\n" + , basename); + exit(-2); +} + +static int open_gpio_channel(int gpio_base) +{ + char gpio_nchan_file[128]; + int gpio_nchan_fd; + int gpio_max; + int nchannel; + char nchannel_str[5]; + char *cptr; + int c; + char channel_str[5]; + + char *gpio_export_file = "/sys/class/gpio/export"; + int export_fd=0; + + /* Check how many channels the GPIO chip has */ + sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base); + gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY); + if (gpio_nchan_fd < 0) { + fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno)); + return -1; + } + read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str)); + close(gpio_nchan_fd); + nchannel=(int)strtoul(nchannel_str, &cptr, 0); + if (cptr == nchannel_str) { + fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str); + exit(1); + } + + /* Open files for each GPIO channel */ + export_fd=open(gpio_export_file, O_WRONLY); + if (export_fd < 0) { + fprintf(stderr, "Cannot open GPIO to export %d\n", gpio_base); + return -1; + } + + gpio_max = gpio_base + nchannel; + for(c = gpio_base; c < gpio_max; c++) { + sprintf(channel_str, "%d", c); + write(export_fd, channel_str, (strlen(channel_str)+1)); + } + close(export_fd); + return nchannel; +} + +static int close_gpio_channel(int gpio_base) +{ + char gpio_nchan_file[128]; + int gpio_nchan_fd; + int gpio_max; + int nchannel; + char nchannel_str[5]; + char *cptr; + int c; + char channel_str[5]; + + char *gpio_unexport_file = "/sys/class/gpio/unexport"; + int unexport_fd=0; + + /* Check how many channels the GPIO chip has */ + sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base); + gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY); + if (gpio_nchan_fd < 0) { + fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno)); + return -1; + } + read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str)); + close(gpio_nchan_fd); + nchannel=(int)strtoul(nchannel_str, &cptr, 0); + if (cptr == nchannel_str) { + fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str); + exit(1); + } + + /* Close opened files for each GPIO channel */ + unexport_fd=open(gpio_unexport_file, O_WRONLY); + if (unexport_fd < 0) { + fprintf(stderr, "Cannot close GPIO by writing unexport %d\n", gpio_base); + return -1; + } + + gpio_max = gpio_base + nchannel; + for(c = gpio_base; c < gpio_max; c++) { + sprintf(channel_str, "%d", c); + write(unexport_fd, channel_str, (strlen(channel_str)+1)); + } + close(unexport_fd); + return 0; +} + +static int set_gpio_direction(int gpio_base, int nchannel, char *direction) +{ + char gpio_dir_file[128]; + int direction_fd=0; + int gpio_max; + int c; + + gpio_max = gpio_base + nchannel; + for(c = gpio_base; c < gpio_max; c++) { + sprintf(gpio_dir_file, "/sys/class/gpio/gpio%d/direction",c); + direction_fd=open(gpio_dir_file, O_RDWR); + if (direction_fd < 0) { + fprintf(stderr, "Cannot open the direction file for GPIO %d\n", c); + return 1; + } + write(direction_fd, direction, (strlen(direction)+1)); + close(direction_fd); + } + return 0; +} + +static int set_gpio_value(int gpio_base, int nchannel, int value) +{ + char gpio_val_file[128]; + int val_fd=0; + int gpio_max; + char val_str[2]; + int c; + + gpio_max = gpio_base + nchannel; + + for(c = gpio_base; c < gpio_max; c++) { + sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c); + val_fd=open(gpio_val_file, O_RDWR); + if (val_fd < 0) { + fprintf(stderr, "Cannot open the value file of GPIO %d\n", c); + return -1; + } + sprintf(val_str,"%d", (value & 1)); + write(val_fd, val_str, sizeof(val_str)); + close(val_fd); + value >>= 1; + } + return 0; +} + +static int get_gpio_value(int gpio_base, int nchannel) +{ + char gpio_val_file[128]; + int val_fd=0; + int gpio_max; + char val_str[2]; + char *cptr; + int value = 0; + int c; + + gpio_max = gpio_base + nchannel; + + for(c = gpio_max-1; c >= gpio_base; c--) { + sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c); + val_fd=open(gpio_val_file, O_RDWR); + if (val_fd < 0) { + fprintf(stderr, "Cannot open GPIO to export %d\n", c); + return -1; + } + read(val_fd, val_str, sizeof(val_str)); + value <<= 1; + value += (int)strtoul(val_str, &cptr, 0); + if (cptr == optarg) { + fprintf(stderr, "Failed to change %s into integer", val_str); + } + close(val_fd); + } + return value; +} + +void signal_handler(int sig) +{ + switch (sig) { + case SIGTERM: + case SIGHUP: + case SIGQUIT: + case SIGINT: + close_gpio_channel(gl_gpio_base); + exit(0) ; + default: + break; + } +} + +int main(int argc, char *argv[]) +{ + extern char *optarg; + char *cptr; + int gpio_value = 0; + int nchannel = 0; + + int c; + int i; + + opterr = 0; + + while ((c = getopt(argc, argv, "g:io:ck")) != -1) { + switch (c) { + case 'g': + gl_gpio_base = (int)strtoul(optarg, &cptr, 0); + if (cptr == optarg) + usage(argv[0]); + break; + case 'i': + gpio_opt = IN; + break; + case 'o': + gpio_opt = OUT; + gpio_value = (int)strtoul(optarg, &cptr, 0); + if (cptr == optarg) + usage(argv[0]); + break; + case 'c': + gpio_opt = CYLON; + break; + case 'k': + gpio_opt = KIT; + break; + case '?': + usage(argv[0]); + default: + usage(argv[0]); + + } + } + + if (gl_gpio_base == 0) { + usage(argv[0]); + } + + nchannel = open_gpio_channel(gl_gpio_base); + signal(SIGTERM, signal_handler); /* catch kill signal */ + signal(SIGHUP, signal_handler); /* catch hang up signal */ + signal(SIGQUIT, signal_handler); /* catch quit signal */ + signal(SIGINT, signal_handler); /* catch a CTRL-c signal */ + switch (gpio_opt) { + case IN: + set_gpio_direction(gl_gpio_base, nchannel, "in"); + gpio_value=get_gpio_value(gl_gpio_base, nchannel); + fprintf(stdout,"0x%08X\n", gpio_value); + break; + case OUT: + set_gpio_direction(gl_gpio_base, nchannel, "out"); + set_gpio_value(gl_gpio_base, nchannel, gpio_value); + break; + case CYLON: +#define CYLON_DELAY_USECS (10000) + set_gpio_direction(gl_gpio_base, nchannel, "out"); + for (;;) { + for(i=0; i < ARRAY_SIZE(cylon); i++) { + gpio_value=(int)cylon[i]; + set_gpio_value(gl_gpio_base, nchannel, gpio_value); + } + usleep(CYLON_DELAY_USECS); + } + case KIT: +#define KIT_DELAY_USECS (10000) + set_gpio_direction(gl_gpio_base, nchannel, "out"); + for (;;) { + for (i=0; i" submenu. + +To install your prebuilt application or script to the target file system +copy on the host, simply run the command. + "petalinux-build -c rootfs/myapp-init" + +You will also need to rebuild PetaLinux bootable images so that the images +is updated with the updated target filesystem copy, run this command: + "petalinux-build -c rootfs" + +You can also run one PetaLinux command to install the application to the +target filesystem host copy and update the bootable images as follows: + "petalinux-build" + diff --git a/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/files/myapp-init b/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/files/myapp-init new file mode 100644 index 0000000..3c200d5 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/files/myapp-init @@ -0,0 +1,5 @@ +#!/bin/sh + +echo "booting from sd card, in myapp" +cd /mnt/sd-mmcblk0p1 +./startup_script.cmd diff --git a/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/files/myapp-init.bak b/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/files/myapp-init.bak new file mode 100644 index 0000000..47f9237 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/files/myapp-init.bak @@ -0,0 +1,63 @@ +#!/bin/sh + +echo "Hello PetaLinux World This is an example startup script, ver 4" + +reset_counters() { + # Read the file into an associative array + declare -A counters + while read line; do + # Split the line into key and value + key=$(echo "$line" | cut -d= -f1) + value=$(echo "$line" | cut -d= -f2) + # Store the key-value pair in the array + counters["$key"]=$value + done < counter_env + + # Reset the values in the array + counters["nu_nw_upgrade_counter"]=0 + counters["nu_nw_global_counter"]=0 + counters["nu_lc_boot_counter"]=0 + counters["nu_lc_backup_counter"]=0 + + # Write the array back to the file + for key in "${!counters[@]}"; do + echo "$key=${counters[$key]}" >> counter_env.tmp + done + + # Replace the original file with the updated file + mv counter_env.tmp counter_env +} + +# get the user boot mode pins +boot_mode_reg=`peek 0x00FF5E0204` +boot_from_sd_card_reg_val="0x00000555" +boot_from_emmc_reg_val="0x00000666" + +if [ "$boot_mode_reg" = "$boot_from_sd_card_reg_val" ]; then +# +# SD BOOT +# +echo "booting from sd card based on user boot mode" +cd /mnt/sd-mmcblk1p1 + echo "Starting Crashkernel Service" + kexec -p /mnt/sd-mmcblk1p1/crashkernel/vmlinux --initrd=/mnt/sd-mmcblk1p1/crashkernel/rootfs.cpio + echo "Resetting U-Boot Counters" + reset_counters +./startup_script.cmd +elif [ "$boot_mode_reg" = "$boot_from_emmc_reg_val" ]; then +# +# EMMC BOOT +# +echo "booting from emmc based on boot mode" +cd /mnt/sd-mmcblk0p1 + echo "Starting Crashkernel Service" + kexec -p /mnt/sd-mmcblk0p1/crashkernel/vmlinux --initrd=/mnt/sd-mmcblk0p1/crashkernel/rootfs.cpio + echo "Resetting U-Boot Counters" + reset_counters +./startup_script.cmd +else +# +# Should never be here +# +echo "[ERROR] user boot mode unsupported, waiting for system reset..." +fi \ No newline at end of file diff --git a/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/myapp-init.bb b/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/myapp-init.bb new file mode 100644 index 0000000..9108f52 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/myapp-init.bb @@ -0,0 +1,26 @@ +# +# This file is the myapp-init recipe. +# + +SUMMARY = "Simple myapp-init application" +SECTION = "PETALINUX/apps" +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" + +SRC_URI = "file://myapp-init \ + " + +S = "${WORKDIR}" + +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" + +inherit update-rc.d + +INITSCRIPT_NAME = "myapp-init" +INITSCRIPT_PARAMS = "start 99 S ." + +do_install() { + install -d ${D}${sysconfdir}/init.d + install -m 0755 ${S}/myapp-init ${D}${sysconfdir}/init.d/myapp-init +} +FILES_${PN} += "${sysconfdir}/*" diff --git a/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/myapp-init.bb.bak b/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/myapp-init.bb.bak new file mode 100644 index 0000000..d807341 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-apps/myapp-init/myapp-init.bb.bak @@ -0,0 +1,18 @@ +# +# This file is the myapp-init recipe. +# + +SUMMARY = "Simple myapp-init application" +SECTION = "PETALINUX/apps" +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" + +SRC_URI = "file://myapp-init \ + " + +S = "${WORKDIR}" + +do_install() { + install -d ${D}/${bindir} + install -m 0755 ${S}/myapp-init ${D}/${bindir} +} diff --git a/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/Makefile b/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/Makefile new file mode 100644 index 0000000..29fb5cd --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/Makefile @@ -0,0 +1,19 @@ +PEEK = peek +POKE = poke + +# Add any other object files to this list below +PEEK_OBJS = peek.o +POKE_OBJS = poke.o + +all: $(PEEK) $(POKE) + +$(POKE): $(POKE_OBJS) + $(CC) $(LDFLAGS) -o $@ $(POKE_OBJS) $(LDLIBS) + +$(PEEK): $(PEEK_OBJS) + $(CC) $(LDFLAGS) -o $@ $(PEEK_OBJS) $(LDLIBS) + +clean: + -rm -f $(POKE) $(PEEK) *.elf *.gdb *.o + + diff --git a/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/peek.c b/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/peek.c new file mode 100644 index 0000000..0891b79 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/peek.c @@ -0,0 +1,77 @@ +/* +* peek utility - for those who remember the good old days! +* +* +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person +* obtaining a copy of this software and associated documentation +* files (the "Software"), to deal in the Software without restriction, +* including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, +* and to permit persons to whom the Software is furnished to do so, +* subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in this +* Software without prior written authorization from Xilinx. +* +*/ + +#include +#include +#include +#include +#include + +void usage(char *prog) +{ + printf("usage: %s ADDR\n",prog); + printf("\n"); + printf("ADDR may be specified as hex values\n"); +} + + +int main(int argc, char *argv[]) +{ + int fd; + void *ptr; + unsigned addr, page_addr, page_offset; + unsigned page_size=sysconf(_SC_PAGESIZE); + + if(argc!=2) { + usage(argv[0]); + exit(-1); + } + + fd=open("/dev/mem",O_RDONLY); + if(fd<1) { + perror(argv[0]); + exit(-1); + } + + addr=strtoul(argv[1],NULL,0); + page_addr=(addr & ~(page_size-1)); + page_offset=addr-page_addr; + + ptr=mmap(NULL,page_size,PROT_READ,MAP_SHARED,fd,(addr & ~(page_size-1))); + if((int)ptr==-1) { + perror(argv[0]); + exit(-1); + } + + printf("0x%08x\n",*((unsigned *)(ptr+page_offset))); + return 0; +} + + diff --git a/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c b/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c new file mode 100644 index 0000000..bc670c3 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c @@ -0,0 +1,77 @@ +/* +* poke utility - for those who remember the good old days! +* + +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person +* obtaining a copy of this software and associated documentation +* files (the "Software"), to deal in the Software without restriction, +* including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, +* and to permit persons to whom the Software is furnished to do so, +* subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in this +* Software without prior written authorization from Xilinx. +* +*/ + +#include +#include +#include +#include +#include + +void usage(char *prog) +{ + printf("usage: %s ADDR VAL\n",prog); + printf("\n"); + printf("ADDR and VAL may be specified as hex values\n"); +} + +int main(int argc, char *argv[]) +{ + int fd; + void *ptr; + unsigned val; + unsigned addr, page_addr, page_offset; + unsigned page_size=sysconf(_SC_PAGESIZE); + + fd=open("/dev/mem",O_RDWR); + if(fd<1) { + perror(argv[0]); + exit(-1); + } + + if(argc!=3) { + usage(argv[0]); + exit(-1); + } + + addr=strtoul(argv[1],NULL,0); + val=strtoul(argv[2],NULL,0); + + page_addr=(addr & ~(page_size-1)); + page_offset=addr-page_addr; + + ptr=mmap(NULL,page_size,PROT_READ|PROT_WRITE,MAP_SHARED,fd,(addr & ~(page_size-1))); + if((int)ptr==-1) { + perror(argv[0]); + exit(-1); + } + + *((unsigned *)(ptr+page_offset))=val; + return 0; +} diff --git a/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/peekpoke.bb b/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/peekpoke.bb new file mode 100644 index 0000000..bace395 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-apps/peekpoke/peekpoke.bb @@ -0,0 +1,25 @@ +# +# This is the peekpoke apllication recipe +# +# + +SUMMARY = "peekpoke application" +SECTION = "PETALINUX/apps" +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" +SRC_URI = "file://peek.c \ + file://poke.c \ + file://Makefile \ + " +S = "${WORKDIR}" +CFLAGS_prepend = "-I ${S}/include" +do_compile() { + oe_runmake +} +do_install() { + install -d ${D}${bindir} + install -m 0755 ${S}/peek ${D}${bindir} + install -m 0755 ${S}/poke ${D}${bindir} + +} + diff --git a/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend new file mode 100644 index 0000000..fabb6de --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend @@ -0,0 +1,17 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" + +SRC_URI += "file://system-user.dtsi" + +python () { + if d.getVar("CONFIG_DISABLE"): + d.setVarFlag("do_configure", "noexec", "1") +} + +export PETALINUX +do_configure_append () { + script="${PETALINUX}/etc/hsm/scripts/petalinux_hsm_bridge.tcl" + data=${PETALINUX}/etc/hsm/data/ + eval xsct -sdx -nodisp ${script} -c ${WORKDIR}/config \ + -hdf ${DT_FILES_PATH}/hardware_description.${HDF_EXT} -repo ${S} \ + -data ${data} -sw ${DT_FILES_PATH} -o ${DT_FILES_PATH} -a "soc_mapping" +} diff --git a/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/openamp.dtsi b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/openamp.dtsi new file mode 100644 index 0000000..0589f12 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/openamp.dtsi @@ -0,0 +1,74 @@ +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + rpu0vdev0vring0: rpu0vdev0vring0@3ed40000 { + no-map; + reg = <0x0 0x3ed40000 0x0 0x4000>; + }; + rpu0vdev0vring1: rpu0vdev0vring1@3ed44000 { + no-map; + reg = <0x0 0x3ed44000 0x0 0x4000>; + }; + rpu0vdev0buffer: rpu0vdev0buffer@3ed48000 { + no-map; + reg = <0x0 0x3ed48000 0x0 0x100000>; + }; + rproc_0_reserved: rproc@3ed00000 { + no-map; + reg = <0x0 0x3ed00000 0x0 0x40000>; + }; + }; + + zynqmp-rpu { + compatible = "xlnx,zynqmp-r5-remoteproc-1.0"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + core_conf = "split"; + reg = <0x0 0xFF9A0000 0x0 0x10000>; + r5_0: r5@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges; + memory-region = <&rproc_0_reserved>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; + pnode-id = <0x7>; + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; + mbox-names = "tx", "rx"; + tcm_0_a: tcm_0@0 { + reg = <0x0 0xFFE00000 0x0 0x10000>; + pnode-id = <0xf>; + }; + tcm_0_b: tcm_0@1 { + reg = <0x0 0xFFE20000 0x0 0x10000>; + pnode-id = <0x10>; + }; + }; + }; + + + zynqmp_ipi1 { + compatible = "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent = <&gic>; + interrupts = <0 29 4>; + xlnx,ipi-id = <7>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* APU<->RPU0 IPI mailbox controller */ + ipi_mailbox_rpu0: mailbox@ff990600 { + reg = <0xff990600 0x20>, + <0xff990620 0x20>, + <0xff9900c0 0x20>, + <0xff9900e0 0x20>; + reg-names = "local_request_region", + "local_response_region", + "remote_request_region", + "remote_response_region"; + #mbox-cells = <1>; + xlnx,ipi-id = <1>; + }; + }; +}; diff --git a/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi new file mode 100644 index 0000000..336d7a2 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi @@ -0,0 +1,2 @@ +/ { +}; diff --git a/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi new file mode 100644 index 0000000..9ff762d --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi @@ -0,0 +1,54 @@ +/include/ "system-conf.dtsi" +/ { + chosen { + bootargs = " earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/ram0 rw cpuidle.off=1"; + stdout-path = "serial0:115200n8"; + }; +}; + + +&uart1 { + status = "okay"; + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; +}; + +&spi0{ + is-decoded-cs = <0>; + num-cs = <1>; + status = "okay"; + bus-num = <0>; + spidev@0x00 { + compatible = "spidev"; + spi-max-frequency = <1000000>; + spi-cpol; + spi-cpha; + reg = <0>; + bus-num = <0>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + i2c-mux@74 { /* u34 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@3 { /* i2c mw 74 0 8 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator@5d { + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <156250000>; + clock-frequency = <156250000>; + }; + }; + }; +}; + diff --git a/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi.bak b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi.bak new file mode 100644 index 0000000..d24bf02 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi.bak @@ -0,0 +1,10 @@ +/include/ "system-conf.dtsi" +/ { +}; + +&uart1 { + status = "okay"; + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; +}; + diff --git a/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/xen-qemu.dtsi b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/xen-qemu.dtsi new file mode 100644 index 0000000..249a786 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/xen-qemu.dtsi @@ -0,0 +1,16 @@ +/ { + cpus { + cpu@1 { + //compatible = "disabled"; + device_type = "none"; + }; + cpu@2 { + //compatible = "disabled"; + device_type = "none"; + }; + cpu@3 { + //compatible = "disabled"; + device_type = "none"; + }; + }; +}; diff --git a/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/xen.dtsi b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/xen.dtsi new file mode 100644 index 0000000..7793a30 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/xen.dtsi @@ -0,0 +1,29 @@ +&smmu { + status = "okay"; + mmu-masters = < &gem0 0x874 + &gem1 0x875 + &gem2 0x876 + &gem3 0x877 + &dwc3_0 0x860 + &dwc3_1 0x861 + &qspi 0x873 + &lpd_dma_chan1 0x868 + &lpd_dma_chan2 0x869 + &lpd_dma_chan3 0x86a + &lpd_dma_chan4 0x86b + &lpd_dma_chan5 0x86c + &lpd_dma_chan6 0x86d + &lpd_dma_chan7 0x86e + &lpd_dma_chan8 0x86f + &fpd_dma_chan1 0x14e8 + &fpd_dma_chan2 0x14e9 + &fpd_dma_chan3 0x14ea + &fpd_dma_chan4 0x14eb + &fpd_dma_chan5 0x14ec + &fpd_dma_chan6 0x14ed + &fpd_dma_chan7 0x14ee + &fpd_dma_chan8 0x14ef + &sdhci0 0x870 + &sdhci1 0x871 + &nand0 0x872>; +}; diff --git a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/0001-ubifs-distroboot-support.patch b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/0001-ubifs-distroboot-support.patch new file mode 100644 index 0000000..01cdb6d --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/0001-ubifs-distroboot-support.patch @@ -0,0 +1,28 @@ +From 357b3eebaa54be1ec8d14b306625eb73732ee5dc Mon Sep 17 00:00:00 2001 +From: Ashok Reddy Soma +Date: Wed, 19 Aug 2020 05:29:40 -0600 +Subject: [UBOOT PATCH] ubifs: distroboot support + +Signed-off-by: Ashok Reddy Soma +--- + include/configs/xilinx_zynqmp.h | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h +index d3f465a..dc231b8 100644 +--- a/include/configs/xilinx_zynqmp.h ++++ b/include/configs/xilinx_zynqmp.h +@@ -154,7 +154,10 @@ + + #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=sf probe " #instance " 0 0 && " \ +- "sf read $scriptaddr $script_offset_f $script_size_f && " \ ++ "setenv mtdids 'nor0=nor0' && " \ ++ "setenv mtdparts 'mtdparts=nor0:16m(raw),-(boot)' && " \ ++ "mtdparts && " \ ++ "ubi part boot; ubifsmount ubi0:boot; ubifsload $scriptaddr boot.scr; && " \ + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0" + +-- +2.7.4 diff --git a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/bsp.cfg b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/bsp.cfg new file mode 100644 index 0000000..8363080 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/bsp.cfg @@ -0,0 +1,5 @@ +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 +CONFIG_SYS_TEXT_BASE=0x10080000 +CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 diff --git a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h new file mode 100644 index 0000000..6542b60 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h @@ -0,0 +1,2 @@ +#include +#include diff --git a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend new file mode 100644 index 0000000..a8dd414 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend @@ -0,0 +1,18 @@ +SRC_URI_append = " file://platform-top.h" +SRC_URI += "file://bsp.cfg" + +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" + +do_configure_append () { + if [ "${U_BOOT_AUTO_CONFIG}" = "1" ]; then + install ${WORKDIR}/platform-auto.h ${S}/include/configs/ + install ${WORKDIR}/platform-top.h ${S}/include/configs/ + fi +} + +do_configure_append_microblaze () { + if [ "${U_BOOT_AUTO_CONFIG}" = "1" ]; then + install -d ${B}/source/board/xilinx/microblaze-generic/ + install ${WORKDIR}/config.mk ${B}/source/board/xilinx/microblaze-generic/ + fi +} diff --git a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr.bbappend b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr.bbappend new file mode 100644 index 0000000..d98395a --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr.bbappend @@ -0,0 +1,145 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" + +SRC_URI += "file://boot.cmd.default.initrd \ + file://boot.cmd.default \ + file://boot.cmd.default.ubifs" + +BOOTMODE = "default" +BOOTFILE_EXT = ".initrd" +#Make this value to "1" to skip appending base address to ddr offsets. +SKIP_APPEND_BASEADDR = "0" + +RAMDISK_IMAGE_zynq = "rootfs.cpio.gz.u-boot" +RAMDISK_IMAGE_zynqmp = "rootfs.cpio.gz.u-boot" +RAMDISK_IMAGE_versal = "rootfs.cpio.gz.u-boot" + +KERNEL_IMAGE_zynq = "uImage" +KERNEL_IMAGE_zynqmp = "Image" +KERNEL_IMAGE_versal = "Image" + +KERNEL_BOOTCMD_zynq = "bootm" +KERNEL_BOOTCMD_zynqmp = "booti" +KERNEL_BOOTCMD_versal = "booti" + +DEVICETREE_ADDRESS_zynq = "${@append_baseaddr(d,"0x100000")}" +DEVICETREE_ADDRESS_zynqmp = "${@append_baseaddr(d,"0x100000")}" +DEVICETREE_ADDRESS_versal = "${@append_baseaddr(d,"0x1000")}" + +KERNEL_LOAD_ADDRESS_zynq = "${@append_baseaddr(d,"0x200000")}" +KERNEL_LOAD_ADDRESS_zynqmp = "${@append_baseaddr(d,"0x200000")}" +KERNEL_LOAD_ADDRESS_versal = "${@append_baseaddr(d,"0x80000")}" + +RAMDISK_IMAGE_ADDRESS_zynq = "${@append_baseaddr(d,"0x4000000")}" +RAMDISK_IMAGE_ADDRESS_zynqmp = "${@append_baseaddr(d,"0x4000000")}" +RAMDISK_IMAGE_ADDRESS_versal = "${@append_baseaddr(d,"0x4000000")}" + +## Below offsets and sizes are based on 32MB QSPI Memory for zynq +## For zynq +## Load boot.scr at 0xFC0000 -> 15MB of QSPI/NAND Memory +QSPI_KERNEL_OFFSET_zynq = "0x1000000" +QSPI_RAMDISK_OFFSET_zynq = "0x1580000" + +NAND_KERNEL_OFFSET_zynq = "0x1000000" +NAND_RAMDISK_OFFSET_zynq = "0x4600000" + +QSPI_KERNEL_SIZE_zynq = "0x500000" +QSPI_RAMDISK_SIZE_zynq = "0xA00000" + +NAND_KERNEL_SIZE = "0x3200000" +NAND_RAMDISK_SIZE = "0x3200000" + +## Below offsets and sizes are based on 128MB QSPI Memory for zynqmp/versal +## For zynqMP +## Load boot.scr at 0x3E80000 -> 62MB of QSPI/NAND Memory +QSPI_KERNEL_OFFSET = "0xF00000" +QSPI_KERNEL_OFFSET_zynqmpdr = "0x3F00000" +QSPI_RAMDISK_OFFSET = "0x4000000" +QSPI_RAMDISK_OFFSET_zynqmpdr = "0x5D00000" + +NAND_KERNEL_OFFSET_zynqmp = "0x4100000" +NAND_RAMDISK_OFFSET_zynqmp = "0x7800000" + +QSPI_KERNEL_SIZE_zynqmp = "0x1D00000" +QSPI_RAMDISK_SIZE = "0x4000000" +QSPI_RAMDISK_SIZE_zynqmpdr = "0x1D00000" + +## For versal +## Load boot.scr at 0x7F80000 -> 127MB of QSPI/NAND Memory +QSPI_KERNEL_OFFSET_versal = "0xF00000" +QSPI_RAMDISK_OFFSET_versal = "0x2E00000" + +NAND_KERNEL_OFFSET_versal = "0x4100000" +NAND_RAMDISK_OFFSET_versal = "0x8200000" + +QSPI_KERNEL_SIZE_versal = "0x1D00000" +QSPI_RAMDISK_SIZE_versal = "0x4000000" + +QSPI_KERNEL_IMAGE_zynq = "image.ub" +QSPI_KERNEL_IMAGE_zynqmp = "image.ub" +QSPI_KERNEL_IMAGE_versal = "image.ub" + +NAND_KERNEL_IMAGE = "image.ub" + +FIT_IMAGE_LOAD_ADDRESS = "${@append_baseaddr(d,"0x10000000")}" + +QSPI_FIT_IMAGE_LOAD_ADDRESS = "${@append_baseaddr(d,"0x10000000")}" +QSPI_FIT_IMAGE_SIZE = "0x6400000" +QSPI_FIT_IMAGE_SIZE_zynqmpdr = "0x3F00000" +QSPI_FIT_IMAGE_SIZE_zynq = "0xF00000" + +NAND_FIT_IMAGE_LOAD_ADDRESS = "${@append_baseaddr(d,"0x10000000")}" +NAND_FIT_IMAGE_SIZE = "0x6400000" + +FIT_IMAGE = "image.ub" + +python () { + baseaddr = d.getVar('DDR_BASEADDR') or "0x0" + if baseaddr == "0x0": + d.setVar('PRE_BOOTENV','') + else: + soc_family = d.getVar('SOC_FAMILY') or "" + if soc_family == "zynqmp": + fdt_high = "0x10000000" + elif soc_family == "zynq": + fdt_high = "0x20000000" + elif soc_family == "versal": + fdt_high = "0x70000000" + + if fdt_high: + basefdt_high = append_baseaddr(d,fdt_high) + bootenv = "setenv fdt_high " + basefdt_high + d.setVar('PRE_BOOTENV',bootenv) +} + +def append_baseaddr(d,offset): + skip_append = d.getVar('SKIP_APPEND_BASEADDR') or "" + if skip_append == "1": + return offset + import subprocess + baseaddr = d.getVar('DDR_BASEADDR') or "0x0" + subcmd = "$((%s+%s));" % (baseaddr,offset) + cmd = "printf '0x%08x' " + str(subcmd) + output = subprocess.check_output(cmd, shell=True).decode("utf-8") + return output + +do_compile_prepend() { + sed -e 's/@@QSPI_KERNEL_OFFSET@@/${QSPI_KERNEL_OFFSET}/' \ + -e 's/@@NAND_KERNEL_OFFSET@@/${NAND_KERNEL_OFFSET}/' \ + -e 's/@@QSPI_KERNEL_SIZE@@/${QSPI_KERNEL_SIZE}/' \ + -e 's/@@NAND_KERNEL_SIZE@@/${NAND_KERNEL_SIZE}/' \ + -e 's/@@QSPI_RAMDISK_OFFSET@@/${QSPI_RAMDISK_OFFSET}/' \ + -e 's/@@NAND_RAMDISK_OFFSET@@/${NAND_RAMDISK_OFFSET}/' \ + -e 's/@@QSPI_RAMDISK_SIZE@@/${QSPI_RAMDISK_SIZE}/' \ + -e 's/@@NAND_RAMDISK_SIZE@@/${NAND_RAMDISK_SIZE}/' \ + -e 's/@@KERNEL_IMAGE@@/${KERNEL_IMAGE}/' \ + -e 's/@@QSPI_KERNEL_IMAGE@@/${QSPI_KERNEL_IMAGE}/' \ + -e 's/@@NAND_KERNEL_IMAGE@@/${NAND_KERNEL_IMAGE}/' \ + -e 's/@@QSPI_FIT_IMAGE_LOAD_ADDRESS@@/${QSPI_FIT_IMAGE_LOAD_ADDRESS}/' \ + -e 's/@@FIT_IMAGE_LOAD_ADDRESS@@/${FIT_IMAGE_LOAD_ADDRESS}/' \ + -e 's/@@QSPI_FIT_IMAGE_SIZE@@/${QSPI_FIT_IMAGE_SIZE}/' \ + -e 's/@@NAND_FIT_IMAGE_LOAD_ADDRESS@@/${NAND_FIT_IMAGE_LOAD_ADDRESS}/' \ + -e 's/@@NAND_FIT_IMAGE_SIZE@@/${NAND_FIT_IMAGE_SIZE}/' \ + -e 's/@@FIT_IMAGE@@/${FIT_IMAGE}/' \ + -e 's/@@PRE_BOOTENV@@/${PRE_BOOTENV}/' \ + "${WORKDIR}/boot.cmd.${BOOTMODE}${BOOTFILE_EXT}" > "${WORKDIR}/boot.cmd.${BOOTMODE}.${SOC_FAMILY}" +} diff --git a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.default b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.default new file mode 100644 index 0000000..f37246c --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.default @@ -0,0 +1,52 @@ +# This is a boot script for U-Boot +# Generate boot.scr: +# mkimage -c none -A arm -T script -d boot.cmd.default boot.scr +# +################ +## Please change the kernel_offset and kernel_size if the kernel image size more than +## the 100MB and BOOT.BIN size more than the 30MB +## kernel_offset --> is the address of qspi which you want load the kernel image +## kernel_size --> size of the kernel image in hex +############### +fdt_addr=0x1000 +imageub_addr=0x10000000 +kernel_addr=0x80000 +kernel_offset=0x1E00200 +kernel_size=0x7800000 +kernel_type=image.ub + +for boot_target in ${boot_targets}; +do + if test "${boot_target}" = "jtag" ; then + booti ${kernel_addr} - ${fdt_addr}; + exit; + fi + if test "${boot_target}" = "mmc0" || test "${boot_target}" = "mmc1" ; then + if test -e ${devtype} ${devnum}:${distro_bootpart} /image.ub; then + fatload ${devtype} ${devnum}:${distro_bootpart} ${imageub_addr} image.ub; + bootm ${imageub_addr}; + exit; + fi + if test -e ${devtype} ${devnum}:${distro_bootpart} /Image; then + fatload ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr} Image; + booti ${kernel_addr} - ${fdt_addr}; + exit; + fi + booti ${kernel_addr} - ${fdt_addr}; + exit; + fi + if test "${boot_target}" = "xspi0"; then + sf probe 0 0 0; + if test "${kernel_type}" = "image.ub"; then + sf read ${imageub_addr} ${kernel_offset} ${kernel_size}; + bootm ${imageub_addr}; + exit; + fi + if test "${kernel_type}" = "Image"; then + sf read ${kernel_addr} ${kernel_offset} ${kernel_size}; + booti ${kernel_addr} - ${fdt_addr}; + exit; + fi + exit; + fi +done diff --git a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.default.initrd b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.default.initrd new file mode 100644 index 0000000..cd9a932 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.default.initrd @@ -0,0 +1,63 @@ +# This is a boot script for U-Boot +# Generate boot.scr: +# mkimage -c none -A arm -T script -d boot.cmd.default boot.scr +# +################ +@@PRE_BOOTENV@@ + +for boot_target in ${boot_targets}; +do + if test "${boot_target}" = "jtag" ; then + @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ + exit; + fi + if test "${boot_target}" = "mmc0" || test "${boot_target}" = "mmc1" ; then + if test -e ${devtype} ${devnum}:${distro_bootpart} /@@FIT_IMAGE@@; then + fatload ${devtype} ${devnum}:${distro_bootpart} @@FIT_IMAGE_LOAD_ADDRESS@@ @@FIT_IMAGE@@; + bootm @@FIT_IMAGE_LOAD_ADDRESS@@; + exit; + fi + if test -e ${devtype} ${devnum}:${distro_bootpart} /@@KERNEL_IMAGE@@; then + fatload ${devtype} ${devnum}:${distro_bootpart} @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGE@@;; + fi + if test -e ${devtype} ${devnum}:${distro_bootpart} /system.dtb; then + fatload ${devtype} ${devnum}:${distro_bootpart} @@DEVICETREE_ADDRESS@@ system.dtb; + fi + if test -e ${devtype} ${devnum}:${distro_bootpart} /@@RAMDISK_IMAGE@@; then + fatload ${devtype} ${devnum}:${distro_bootpart} @@RAMDISK_IMAGE_ADDRESS@@ @@RAMDISK_IMAGE@@; + @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ + exit; + fi + @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@ + exit; + fi + if test "${boot_target}" = "xspi0" || test "${boot_target}" = "qspi" || test "${boot_target}" = "qspi0"; then + sf probe 0 0 0; + if test "@@QSPI_KERNEL_IMAGE@@" = "@@FIT_IMAGE@@"; then + sf read @@QSPI_FIT_IMAGE_LOAD_ADDRESS@@ @@QSPI_KERNEL_OFFSET@@ @@QSPI_FIT_IMAGE_SIZE@@; + bootm @@QSPI_FIT_IMAGE_LOAD_ADDRESS@@; + exit; + fi + if test "@@QSPI_KERNEL_IMAGE@@" = "@@KERNEL_IMAGE@@"; then + sf read @@KERNEL_LOAD_ADDRESS@@ @@QSPI_KERNEL_OFFSET@@ @@QSPI_KERNEL_SIZE@@; + sf read @@RAMDISK_IMAGE_ADDRESS@@ @@QSPI_RAMDISK_OFFSET@@ @@QSPI_RAMDISK_SIZE@@ + @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ + exit; + fi + exit; + fi + if test "${boot_target}" = "nand" || test "${boot_target}" = "nand0"; then + nand info + if test "@@NAND_KERNEL_IMAGE@@" = "@@FIT_IMAGE@@"; then + nand read @@NAND_FIT_IMAGE_LOAD_ADDRESS@@ @@NAND_KERNEL_OFFSET@@ @@NAND_FIT_IMAGE_SIZE@@; + bootm @@NAND_FIT_IMAGE_LOAD_ADDRESS@@; + exit; + fi + if test "@@NAND_KERNEL_IMAGE@@" = "@@KERNEL_IMAGE@@"; then + nand read @@KERNEL_LOAD_ADDRESS@@ @@NAND_KERNEL_OFFSET@@ @@NAND_KERNEL_SIZE@@; + nand read @@RAMDISK_IMAGE_ADDRESS@@ @@NAND_RAMDISK_OFFSET@@ @@NAND_RAMDISK_SIZE@@; + @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ + exit; + fi + fi +done diff --git a/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.default.ubifs b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.default.ubifs new file mode 100644 index 0000000..2b21c3c --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.default.ubifs @@ -0,0 +1,55 @@ +# This is a boot script for U-Boot +# Generate boot.scr: +# mkimage -c none -A arm -T script -d boot.cmd.default boot.scr +# +################ +@@PRE_BOOTENV@@ + +for boot_target in ${boot_targets}; +do + if test "${boot_target}" = "xspi0" || test "${boot_target}" = "qspi" || test "${boot_target}" = "qspi0"; then + ubifsls @@FIT_IMAGE@@ + if test $? = 0; then + ubifsload @@QSPI_FIT_IMAGE_LOAD_ADDRESS@@ @@FIT_IMAGE@@; + bootm @@QSPI_FIT_IMAGE_LOAD_ADDRESS@@; + exit; + fi + ubifsls @@KERNEL_IMAGE@@ + if test $? = 0; then + ubifsload @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGE@@; + fi + ubifsls system.dtb + if test $? = 0; then + ubifsload @@DEVICETREE_ADDRESS@@ system.dtb + fi + ubifsls @@RAMDISK_IMAGE@@ + if test $? = 0; then + ubifsload @@RAMDISK_IMAGE_ADDRESS@@ @@RAMDISK_IMAGE@@ + @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ + exit; + fi + @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@ + exit; + fi + if test "${boot_target}" = "mmc0" || test "${boot_target}" = "mmc1" ; then + run bootcmd_${boot_target}; + if test -e ${devtype} ${devnum}:${distro_bootpart} /@@FIT_IMAGE@@; then + ext4load ${devtype} ${devnum}:${distro_bootpart} @@FIT_IMAGE_LOAD_ADDRESS@@ @@FIT_IMAGE@@; + bootm @@FIT_IMAGE_LOAD_ADDRESS@@; + exit; + fi + if test -e ${devtype} ${devnum}:${distro_bootpart} /@@KERNEL_IMAGE@@; then + ext4load ${devtype} ${devnum}:${distro_bootpart} @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGE@@; + fi + if test -e ${devtype} ${devnum}:${distro_bootpart} /system.dtb; then + ext4load ${devtype} ${devnum}:${distro_bootpart} @@DEVICETREE_ADDRESS@@ system.dtb; + fi + if test -e ${devtype} ${devnum}:${distro_bootpart} /@@RAMDISK_IMAGE@@; then + ext4load ${devtype} ${devnum}:${distro_bootpart} @@RAMDISK_IMAGE_ADDRESS@@ @@RAMDISK_IMAGE@@; + @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ + exit; + fi + @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@ + exit; + fi +done diff --git a/Petalinux/project-spec/meta-user/recipes-core/images/petalinux-image-full.bbappend b/Petalinux/project-spec/meta-user/recipes-core/images/petalinux-image-full.bbappend new file mode 100644 index 0000000..47d8f0e --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-core/images/petalinux-image-full.bbappend @@ -0,0 +1,7 @@ +#Note: Mention Each package in individual line +# cascaded representation with line breaks are not valid in this file. +IMAGE_INSTALL_append = " peekpoke" +IMAGE_INSTALL_append = " gpio-demo" + +IMAGE_INSTALL_append = " ethtool" +IMAGE_INSTALL_append = " iperf3" diff --git a/Petalinux/project-spec/meta-user/recipes-core/init-ifupdown/files/myinterfaces b/Petalinux/project-spec/meta-user/recipes-core/init-ifupdown/files/myinterfaces new file mode 100644 index 0000000..cd2724c --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-core/init-ifupdown/files/myinterfaces @@ -0,0 +1,15 @@ +# myinterfaces content + +# /etc/network/interfaces -- configuration file for ifup(8), ifdown(8) + +# The loopback interface +auto lo +iface lo inet loopback + +# Wired or wireless interfaces +auto eth0 +iface eth0 inet dhcp + +# Add auto config for eth1 +auto eth1 +iface eth1 inet dhcp \ No newline at end of file diff --git a/Petalinux/project-spec/meta-user/recipes-core/init-ifupdown/init-ifupdown_%.bbappend b/Petalinux/project-spec/meta-user/recipes-core/init-ifupdown/init-ifupdown_%.bbappend new file mode 100644 index 0000000..3dd51bc --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-core/init-ifupdown/init-ifupdown_%.bbappend @@ -0,0 +1,12 @@ +# init-ifupdown_%.bbappend content + +SRC_URI += " \ + file://myinterfaces \ + " + +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" + +# Overwrite interface file with myinterface file in rootfs +do_install_append() { + install -m 0644 ${WORKDIR}/myinterfaces ${D}${sysconfdir}/network/interfaces +} \ No newline at end of file diff --git a/Petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg b/Petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg new file mode 100644 index 0000000..28c6bfe --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg @@ -0,0 +1,3 @@ +CONFIG_XILINX_PHY=y +# CONFIG_XILINX_DMA is not set + diff --git a/Petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend b/Petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend new file mode 100644 index 0000000..b89c177 --- /dev/null +++ b/Petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend @@ -0,0 +1,3 @@ +SRC_URI += "file://bsp.cfg" +KERNEL_FEATURES_append = " bsp.cfg" +FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" diff --git a/images/BOOT.BIN b/images/BOOT.BIN new file mode 100644 index 0000000..2624716 Binary files /dev/null and b/images/BOOT.BIN differ diff --git a/images/boot.scr b/images/boot.scr new file mode 100644 index 0000000..05a11cd Binary files /dev/null and b/images/boot.scr differ diff --git a/images/image.ub b/images/image.ub new file mode 100644 index 0000000..5f79de5 Binary files /dev/null and b/images/image.ub differ diff --git a/images/system.dtb b/images/system.dtb new file mode 100644 index 0000000..0226012 Binary files /dev/null and b/images/system.dtb differ diff --git a/results/Results_MTU_9000.png b/results/Results_MTU_9000.png new file mode 100644 index 0000000..cadb477 Binary files /dev/null and b/results/Results_MTU_9000.png differ diff --git a/src/constraints/README b/src/constraints/README new file mode 100644 index 0000000..85400df --- /dev/null +++ b/src/constraints/README @@ -0,0 +1 @@ +Use this directory to track your constraint files diff --git a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/gui_handlers.wdf b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/gui_handlers.wdf index a1647b9..5044b24 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/gui_handlers.wdf +++ b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/gui_handlers.wdf @@ -1,46 +1,49 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3136:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:3135:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:35:00:00 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a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/java_command_handlers.wdf +++ b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/java_command_handlers.wdf @@ -1,22 +1,22 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:37:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65727362626c6f636b:36:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65786974617070:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:38:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65727362626c6f636b:3134:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65786974617070:35:00:00 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a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/synthesis.wdf +++ b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/synthesis.wdf @@ -1,7 +1,7 @@ version:1 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:72746c5f31:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78637a753765762d66667663313135362d322d65:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:706c5f6574685f3130675f77726170706572:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 @@ -10,7 +10,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:5b7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 @@ -36,4 +36,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -eof:3126106825 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30373a333073:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:343432312e3735304d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:333237372e3631374d42:00:00 +eof:3543237790 diff --git a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/webtalk_pa.xml b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/webtalk_pa.xml index 5a72f6c..8edcf78 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/webtalk_pa.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
    @@ -17,77 +17,80 @@ This means code written to parse this file will need to be revisited each subseq - - - + + + - - - + + + - - + + - - - + + + - + - + - - - - - + + + + + - + - - - - - - - - - + + + + + + + + + + - - + + + - - - + + + - - + + - + + - + - + - +
    diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hdl/pl_eth_10g_wrapper.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hdl/pl_eth_10g_wrapper.v index 2cc84ab..5c27ccc 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hdl/pl_eth_10g_wrapper.v +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hdl/pl_eth_10g_wrapper.v @@ -1,7 +1,7 @@ //Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -//Date : Fri Oct 20 12:44:41 2023 +//Date : Fri Oct 20 19:29:21 2023 //Host : DESKTOP-5FH9OH3 running 64-bit major release (build 9200) //Command : generate_target pl_eth_10g_wrapper.bd //Design : pl_eth_10g_wrapper diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g.hwh b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g.hwh index 1304fff..ab87bbc 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g.hwh +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g.hwh @@ -1,5 +1,5 @@  - + @@ -9,16 +9,6 @@ - - - - - - - - - - @@ -29,6 +19,16 @@ + + + + + + + + + + @@ -911,7 +911,7 @@ - + @@ -940,7 +940,7 @@ - + @@ -1603,7 +1603,7 @@ - + @@ -10102,155 +10102,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -10400,6 +10251,155 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -12915,7 +12915,7 @@ - + @@ -13082,7 +13082,7 @@ - + @@ -13109,7 +13109,7 @@ - + @@ -13117,7 +13117,7 @@ - + @@ -13143,7 +13143,7 @@ - + @@ -13155,16 +13155,16 @@ - + - + - + - + diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g_bd.tcl b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g_bd.tcl index e5350bd..2a335f2 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g_bd.tcl +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hw_handoff/pl_eth_10g_bd.tcl @@ -790,7 +790,7 @@ proc create_hier_cell_zups { parentCell nameHier } { CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \ CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1333.333} \ CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ @@ -883,7 +883,7 @@ proc create_hier_cell_zups { parentCell nameHier } { CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {499.994995} \ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {600} \ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ @@ -915,7 +915,7 @@ proc create_hier_cell_zups { parentCell nameHier } { CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {533.333} \ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ @@ -939,7 +939,7 @@ proc create_hier_cell_zups { parentCell nameHier } { CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {533.333} \ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \ @@ -1000,7 +1000,7 @@ proc create_hier_cell_zups { parentCell nameHier } { CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {267} \ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ @@ -1008,7 +1008,7 @@ proc create_hier_cell_zups { parentCell nameHier } { CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {533.333} \ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ @@ -1043,10 +1043,10 @@ proc create_hier_cell_zups { parentCell nameHier } { CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {299.997009} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {300} \ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {90} \ @@ -1889,7 +1889,7 @@ proc create_root_design { parentCell } { CONFIG.c_m_axi_mm2s_data_width {64} \ CONFIG.c_m_axis_mm2s_tdata_width {64} \ CONFIG.c_mm2s_burst_size {64} \ - CONFIG.c_s2mm_burst_size {8} \ + CONFIG.c_s2mm_burst_size {16} \ CONFIG.c_sg_include_stscntrl_strm {0} \ CONFIG.c_sg_length_width {16} \ ] $axi_dma_0 diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0.xml index 3d23f3b..4e98e53 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0.xml @@ -1627,7 +1627,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1658,7 +1658,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1684,7 +1684,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1704,7 +1704,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1732,7 +1732,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1752,7 +1752,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1775,7 +1775,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1.xml index 2cfd896..fa4c522 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1.xml @@ -583,7 +583,7 @@ MAX_BURST_LENGTH - 4 + 8 simulation.tlm @@ -1233,7 +1233,7 @@ MAX_BURST_LENGTH - 4 + 8 simulation.tlm @@ -1627,7 +1627,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1658,7 +1658,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1684,7 +1684,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1704,11 +1704,11 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC - 9:c5200498 + 9:ad94d400 sim_type @@ -1732,7 +1732,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1752,11 +1752,11 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC - 9:c5200498 + 9:ad94d400 sim_type @@ -1775,7 +1775,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.cpp index 248a50d..da0afc8 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.cpp +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.cpp @@ -114,7 +114,7 @@ void pl_eth_10g_auto_cc_1::before_end_of_elaboration() S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4"); + S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -195,7 +195,7 @@ void pl_eth_10g_auto_cc_1::before_end_of_elaboration() M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -307,7 +307,7 @@ void pl_eth_10g_auto_cc_1::before_end_of_elaboration() S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4"); + S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -388,7 +388,7 @@ void pl_eth_10g_auto_cc_1::before_end_of_elaboration() M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -500,7 +500,7 @@ void pl_eth_10g_auto_cc_1::before_end_of_elaboration() S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4"); + S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -581,7 +581,7 @@ void pl_eth_10g_auto_cc_1::before_end_of_elaboration() M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -681,7 +681,7 @@ pl_eth_10g_auto_cc_1::pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm) : S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4"); + S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -742,7 +742,7 @@ pl_eth_10g_auto_cc_1::pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm) : M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -868,7 +868,7 @@ pl_eth_10g_auto_cc_1::pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm) : S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4"); + S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -929,7 +929,7 @@ pl_eth_10g_auto_cc_1::pl_eth_10g_auto_cc_1(const sc_core::sc_module_name& nm) : M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.v index a330076..4eaaa0f 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.v +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/sim/pl_eth_10g_auto_cc_1.v @@ -140,7 +140,7 @@ output wire s_axi_wready; output wire [1 : 0] s_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output wire s_axi_bvalid; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\ +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\ M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input wire s_axi_bready; @@ -186,7 +186,7 @@ input wire m_axi_wready; input wire [1 : 0] m_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input wire m_axi_bvalid; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \ +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \ NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output wire m_axi_bready; diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/synth/pl_eth_10g_auto_cc_1.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/synth/pl_eth_10g_auto_cc_1.v index 37cf1dc..b0bfd05 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/synth/pl_eth_10g_auto_cc_1.v +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/synth/pl_eth_10g_auto_cc_1.v @@ -142,7 +142,7 @@ output wire s_axi_wready; output wire [1 : 0] s_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output wire s_axi_bvalid; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\ +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\ M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input wire s_axi_bready; @@ -188,7 +188,7 @@ input wire m_axi_wready; input wire [1 : 0] m_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input wire m_axi_bvalid; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \ +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 124998749, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0.000, CLK_DOMAIN pl_eth_10g_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, \ NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output wire m_axi_bready; diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0.xml index baea326..e8b0fd5 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0.xml @@ -1519,7 +1519,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1550,7 +1550,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1594,7 +1594,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1614,7 +1614,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1642,7 +1642,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1662,7 +1662,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1685,7 +1685,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1.xml index 6092a06..05b96aa 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1.xml @@ -1519,7 +1519,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1550,7 +1550,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1594,7 +1594,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1614,7 +1614,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1642,7 +1642,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1662,7 +1662,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1685,7 +1685,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/pl_eth_10g_auto_pc_0.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/pl_eth_10g_auto_pc_0.xml index f6f3174..e576671 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/pl_eth_10g_auto_pc_0.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_0/pl_eth_10g_auto_pc_0.xml @@ -1511,7 +1511,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1542,7 +1542,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1577,7 +1577,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1597,7 +1597,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1625,7 +1625,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1645,7 +1645,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/pl_eth_10g_auto_pc_1.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/pl_eth_10g_auto_pc_1.xml index f678364..1c9b07f 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/pl_eth_10g_auto_pc_1.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_pc_1/pl_eth_10g_auto_pc_1.xml @@ -1511,7 +1511,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1542,7 +1542,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1577,7 +1577,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1597,7 +1597,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1625,7 +1625,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1645,7 +1645,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0.xml index 0977807..dd1aff1 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0.xml @@ -1519,7 +1519,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1550,7 +1550,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1594,7 +1594,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1614,7 +1614,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1642,7 +1642,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1662,7 +1662,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1685,7 +1685,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1.xml index 15b9c24..8670f53 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1.xml @@ -1519,7 +1519,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1550,7 +1550,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1594,7 +1594,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1614,7 +1614,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1642,7 +1642,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1662,7 +1662,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1685,7 +1685,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2.xml index ac2fb02..4ec84d8 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2.xml @@ -535,7 +535,7 @@ MAX_BURST_LENGTH - 8 + 16 simulation.tlm @@ -1105,7 +1105,7 @@ MAX_BURST_LENGTH - 4 + 8 simulation.tlm @@ -1519,7 +1519,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1550,7 +1550,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1594,7 +1594,7 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1614,11 +1614,11 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC - 9:8b059e5b + 9:67119cc3 sim_type @@ -1642,7 +1642,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC @@ -1662,11 +1662,11 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC - 9:8b059e5b + 9:67119cc3 sim_type @@ -1685,7 +1685,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.cpp b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.cpp index 34144e0..293c9b1 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.cpp +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.cpp @@ -112,7 +112,7 @@ void pl_eth_10g_auto_us_2::before_end_of_elaboration() S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); + S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16"); S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -193,7 +193,7 @@ void pl_eth_10g_auto_us_2::before_end_of_elaboration() M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -303,7 +303,7 @@ void pl_eth_10g_auto_us_2::before_end_of_elaboration() S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); + S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16"); S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -384,7 +384,7 @@ void pl_eth_10g_auto_us_2::before_end_of_elaboration() M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -494,7 +494,7 @@ void pl_eth_10g_auto_us_2::before_end_of_elaboration() S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); + S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16"); S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -575,7 +575,7 @@ void pl_eth_10g_auto_us_2::before_end_of_elaboration() M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -673,7 +673,7 @@ pl_eth_10g_auto_us_2::pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm) : S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); + S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16"); S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -734,7 +734,7 @@ pl_eth_10g_auto_us_2::pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm) : M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -858,7 +858,7 @@ pl_eth_10g_auto_us_2::pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm) : S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); + S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16"); S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); @@ -919,7 +919,7 @@ pl_eth_10g_auto_us_2::pl_eth_10g_auto_us_2(const sc_core::sc_module_name& nm) : M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0"); M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2"); M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16"); - M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "4"); + M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "8"); M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1"); M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1"); M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0"); diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.v index 1c1df42..1198e97 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.v +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/sim/pl_eth_10g_auto_us_2.v @@ -138,8 +138,8 @@ output wire s_axi_wready; output wire [1 : 0] s_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output wire s_axi_bvalid; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NUM\ -_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\ +M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input wire s_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) @@ -178,7 +178,7 @@ input wire m_axi_wready; input wire [1 : 0] m_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input wire m_axi_bvalid; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\ +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\ M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output wire m_axi_bready; diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/synth/pl_eth_10g_auto_us_2.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/synth/pl_eth_10g_auto_us_2.v index f2375ca..4f01f4a 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/synth/pl_eth_10g_auto_us_2.v +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/synth/pl_eth_10g_auto_us_2.v @@ -140,8 +140,8 @@ output wire s_axi_wready; output wire [1 : 0] s_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output wire s_axi_bvalid; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NUM\ -_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\ +M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input wire s_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) @@ -180,7 +180,7 @@ input wire m_axi_wready; input wire [1 : 0] m_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input wire m_axi_bvalid; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 4, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\ +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\ M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output wire m_axi_bready; diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0.xml index f6bc6cd..574434a 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0.xml @@ -2233,7 +2233,7 @@ MAX_BURST_LENGTH - 8 + 16 none @@ -5068,7 +5068,7 @@ Note: This value must be greater than or equal to the largest expected packet to outputProductCRC - 9:de9c90d9 + 9:888ce341 @@ -5079,7 +5079,7 @@ Note: This value must be greater than or equal to the largest expected packet to outputProductCRC - 9:de9c90d9 + 9:888ce341 @@ -5095,11 +5095,11 @@ Note: This value must be greater than or equal to the largest expected packet to GENtimestamp - Fri Oct 20 03:08:17 UTC 2023 + Sat Oct 21 02:29:22 UTC 2023 outputProductCRC - 9:de9c90d9 + 9:888ce341 @@ -5140,7 +5140,7 @@ Note: This value must be greater than or equal to the largest expected packet to outputProductCRC - 9:94903a0b + 9:2a5bc1d6 @@ -5156,11 +5156,11 @@ Note: This value must be greater than or equal to the largest expected packet to GENtimestamp - Fri Oct 20 03:08:17 UTC 2023 + Sat Oct 21 02:29:22 UTC 2023 outputProductCRC - 9:94903a0b + 9:2a5bc1d6 @@ -7892,7 +7892,7 @@ Note: This value must be greater than or equal to the largest expected packet to C_S2MM_BURST_SIZE - 8 + 16 @@ -8603,7 +8603,7 @@ Note: This value must be greater than or equal to the largest expected packet to c_s2mm_burst_size Max Burst Size - 8 + 16 diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/sim/pl_eth_10g_axi_dma_0_0.vhd b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/sim/pl_eth_10g_axi_dma_0_0.vhd index 16df0a5..050202b 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/sim/pl_eth_10g_axi_dma_0_0.vhd +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/sim/pl_eth_10g_axi_dma_0_0.vhd @@ -341,8 +341,8 @@ ARCHITECTURE pl_eth_10g_axi_dma_0_0_arch OF pl_eth_10g_axi_dma_0_0 IS ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN"; - ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1" & -", NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS " & +"1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY"; @@ -454,7 +454,7 @@ BEGIN C_INCLUDE_MM2S_DRE => 1, C_INCLUDE_S2MM => 1, C_INCLUDE_S2MM_SF => 1, - C_S2MM_BURST_SIZE => 8, + C_S2MM_BURST_SIZE => 16, C_M_AXI_S2MM_ADDR_WIDTH => 32, C_M_AXI_S2MM_DATA_WIDTH => 64, C_S_AXIS_S2MM_TDATA_WIDTH => 64, diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/synth/pl_eth_10g_axi_dma_0_0.vhd b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/synth/pl_eth_10g_axi_dma_0_0.vhd index cc30b2d..a55cbfd 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/synth/pl_eth_10g_axi_dma_0_0.vhd +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/synth/pl_eth_10g_axi_dma_0_0.vhd @@ -318,7 +318,7 @@ ARCHITECTURE pl_eth_10g_axi_dma_0_0_arch OF pl_eth_10g_axi_dma_0_0 IS ATTRIBUTE CHECK_LICENSE_TYPE OF pl_eth_10g_axi_dma_0_0_arch : ARCHITECTURE IS "pl_eth_10g_axi_dma_0_0,axi_dma,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF pl_eth_10g_axi_dma_0_0_arch: ARCHITECTURE IS "pl_eth_10g_axi_dma_0_0,axi_dma,{x_ipProduct=Vivado 2020.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=23,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=1,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=16,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=3" & -"2,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=64,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=64,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=8,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=64,C_INCLUDE_S2MM_DRE=1,C_INCREASE_THROUGHPUT=0,C_FAMILY=zynquplus}"; +"2,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=64,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=64,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=64,C_INCLUDE_S2MM_DRE=1,C_INCREASE_THROUGHPUT=0,C_FAMILY=zynquplus}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_PARAMETER : STRING; ATTRIBUTE X_INTERFACE_PARAMETER OF s2mm_introut: SIGNAL IS "XIL_INTERFACENAME S2MM_INTROUT, SENSITIVITY LEVEL_HIGH, PortWidth 1"; @@ -348,8 +348,8 @@ ARCHITECTURE pl_eth_10g_axi_dma_0_0_arch OF pl_eth_10g_axi_dma_0_0 IS ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN"; - ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1" & -", NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_s2mm_awaddr: SIGNAL IS "XIL_INTERFACENAME M_AXI_S2MM, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, NUM_READ_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS " & +"1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY"; @@ -461,7 +461,7 @@ BEGIN C_INCLUDE_MM2S_DRE => 1, C_INCLUDE_S2MM => 1, C_INCLUDE_S2MM_SF => 1, - C_S2MM_BURST_SIZE => 8, + C_S2MM_BURST_SIZE => 16, C_M_AXI_S2MM_ADDR_WIDTH => 32, C_M_AXI_S2MM_DATA_WIDTH => 64, C_S_AXIS_S2MM_TDATA_WIDTH => 64, diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s00_mmu_0/pl_eth_10g_s00_mmu_0.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s00_mmu_0/pl_eth_10g_s00_mmu_0.xml index fccd6ff..116a234 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s00_mmu_0/pl_eth_10g_s00_mmu_0.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s00_mmu_0/pl_eth_10g_s00_mmu_0.xml @@ -1419,7 +1419,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1450,7 +1450,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1476,7 +1476,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1496,7 +1496,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s01_mmu_0/pl_eth_10g_s01_mmu_0.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s01_mmu_0/pl_eth_10g_s01_mmu_0.xml index 4aca5b6..a55fa21 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s01_mmu_0/pl_eth_10g_s01_mmu_0.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s01_mmu_0/pl_eth_10g_s01_mmu_0.xml @@ -1419,7 +1419,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1450,7 +1450,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1476,7 +1476,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1496,7 +1496,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/pl_eth_10g_s02_mmu_0.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/pl_eth_10g_s02_mmu_0.xml index f860b32..b479158 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/pl_eth_10g_s02_mmu_0.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/pl_eth_10g_s02_mmu_0.xml @@ -567,7 +567,7 @@ MAX_BURST_LENGTH - 8 + 16 none @@ -1201,7 +1201,7 @@ MAX_BURST_LENGTH - 8 + 16 none @@ -1419,7 +1419,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1450,7 +1450,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1476,7 +1476,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC @@ -1496,7 +1496,7 @@ GENtimestamp - Fri Oct 20 19:45:20 UTC 2023 + Sat Oct 21 02:30:01 UTC 2023 outputProductCRC diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/sim/pl_eth_10g_s02_mmu_0.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/sim/pl_eth_10g_s02_mmu_0.v index b942822..f4a3bff 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/sim/pl_eth_10g_s02_mmu_0.v +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/sim/pl_eth_10g_s02_mmu_0.v @@ -134,8 +134,8 @@ output wire s_axi_wready; output wire [1 : 0] s_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output wire s_axi_bvalid; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NUM\ -_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\ +M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input wire s_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) @@ -172,8 +172,8 @@ input wire m_axi_wready; input wire [1 : 0] m_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input wire m_axi_bvalid; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NUM\ -_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\ +M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output wire m_axi_bready; diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/synth/pl_eth_10g_s02_mmu_0.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/synth/pl_eth_10g_s02_mmu_0.v index 8b3ce0e..d5a0b6c 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/synth/pl_eth_10g_s02_mmu_0.v +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_s02_mmu_0/synth/pl_eth_10g_s02_mmu_0.v @@ -136,8 +136,8 @@ output wire s_axi_wready; output wire [1 : 0] s_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output wire s_axi_bvalid; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NUM\ -_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\ +M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input wire s_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) @@ -174,8 +174,8 @@ input wire m_axi_wready; input wire [1 : 0] m_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input wire m_axi_bvalid; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 8, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NUM\ -_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 156250000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE WRITE_ONLY, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 0, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 16, PHASE 0, CLK_DOMAIN pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0, NUM_READ_THREADS 1, NU\ +M_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output wire m_axi_bready; diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/hdl/pl_eth_10g_zynq_ultra_ps_e_0_0.hwdef b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/hdl/pl_eth_10g_zynq_ultra_ps_e_0_0.hwdef index 4cb6f5c..d548426 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/hdl/pl_eth_10g_zynq_ultra_ps_e_0_0.hwdef and b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/hdl/pl_eth_10g_zynq_ultra_ps_e_0_0.hwdef differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_3.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_3.v index c21e22c..3241f06 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_3.v +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/hdl/zynq_ultra_ps_e_v3_3_3.v @@ -76,7 +76,7 @@ \ \ \ - \ + \ \ \ \ @@ -329,12 +329,12 @@ SATA1_MGTRTXP3, , , OUT, PS_MGTRTXP3_505, , , , , ,, \n\ , PSU__PMU__GPI0__ENABLE=0, PSU__PMU__GPI1__ENABLE=0, PSU__PMU__GPI2__ENABLE=0, PSU__PMU__GPI3__ENABLE=0, PSU__PMU__GPI4__ENABLE=0, PSU__PMU__GPI5__ENABLE=0, PSU__PMU__GPO0__ENABLE=1, PSU__PMU__GPO1__ENABLE=1, PSU__PMU__GPO2__ENABLE=1, PSU__PMU__GPO3__ENABLE=1, PSU__PMU__GPO4__ENABLE=1, PSU__PMU__GPO5__ENABLE=1, PSU__PMU__GPO0__IO=MIO 32, PSU__PMU__GPO1__IO=MIO 33, PSU__PMU__GPO2__IO=MIO 34, PSU__PMU__GPO3__IO=MIO 35, PSU__PMU__GPO4__IO=MIO 36, PSU__PMU__GPO5__IO=MIO 37, PSU__CSU__PERIPHERAL__ENABLE=0, PSU__QSPI__PERIPHERAL__ENABLE=1, PSU__QSPI__PERIPHERAL__IO=MIO 0 .. 12, PSU__QSPI__PERIPHERAL__MODE=Dual Parallel, PSU__QSPI__PERIPHERAL__DATA_MODE=x4, PSU__QSPI__GRP_FBCLK__ENABLE=1, PSU__QSPI__GRP_FBCLK__IO=MIO 6, PSU__SD0__PERIPHERAL__ENABLE=0, PSU__SD0__GRP_CD__ENABLE=0, PSU__SD0__GRP_POW__ENABLE=0, PSU__SD0__GRP_WP__ENABLE=0, PSU__SD1__PERIPHERAL__ENABLE=1, PSU__SD1__PERIPHERAL__IO=MIO 39 .. 51, PSU__SD1__GRP_CD__ENABLE=1, PSU__SD1__GRP_CD__IO=MIO 45, PSU__SD1__GRP_POW__ENABLE=1, PSU__SD1__GRP_POW__IO=MIO 43, PSU__SD1__GRP_WP__ENABLE=1, PSU__SD1__GRP_WP__IO=MIO 44, PSU__SD1__SLOT_TYPE=SD 3.0, PSU__SPI0__PERIPHERAL__ENABLE=0, PSU__SPI0__GRP_SS0__ENABLE=0, PSU__SPI0__GRP_SS1__ENABLE=0, PSU__SPI0__GRP_SS2__ENABLE=0, PSU__SPI1__PERIPHERAL__ENABLE=0, PSU__SPI1__GRP_SS0__ENABLE=0, PSU__SPI1__GRP_SS1__ENABLE=0, PSU__SPI1__GRP_SS2__ENABLE=0, PSU__SPI0_LOOP_SPI1__ENABLE=0, PSU__SWDT0__PERIPHERAL__ENABLE=1, PSU__SWDT0__PERIPHERAL__IO=EMIO, PSU__SWDT1__PERIPHERAL__ENABLE=1\ , PSU__SWDT1__PERIPHERAL__IO=EMIO, PSU__UART0__BAUD_RATE=115200, PSU__TRACE__PERIPHERAL__ENABLE=0, PSU__TTC0__PERIPHERAL__ENABLE=1, PSU__TTC0__PERIPHERAL__IO=EMIO, PSU__TTC1__PERIPHERAL__ENABLE=1, PSU__TTC1__PERIPHERAL__IO=EMIO, PSU__UART1__BAUD_RATE=115200, PSU__TTC2__PERIPHERAL__ENABLE=1, PSU__TTC2__PERIPHERAL__IO=EMIO, PSU__TTC3__PERIPHERAL__ENABLE=1, PSU__TTC3__PERIPHERAL__IO=EMIO, PSU__DDRC__AL=0, PSU__DDRC__BANK_ADDR_COUNT=2, PSU__DDRC__BUS_WIDTH=64 Bit, PSU__DDRC__CL=15, PSU__DDRC__CLOCK_STOP_EN=0, PSU__DDRC__COL_ADDR_COUNT=10, PSU__DDRC__CWL=14, PSU__DDRC__DEVICE_CAPACITY=8192 MBits, PSU__DDRC__DRAM_WIDTH=16 Bits, PSU__DDRC__ECC=Disabled, PSU__DDRC__ENABLE=1, PSU__DDRC__FREQ_MHZ=1066.50, PSU__DDRC__MEMORY_TYPE=DDR 4, PSU__DDRC__ROW_ADDR_COUNT=16, PSU__DDRC__SPEED_BIN=DDR4_2133P, PSU__DDRC__T_FAW=30.0, PSU__DDRC__T_RAS_MIN=33, PSU__DDRC__T_RC=47.06, PSU__DDRC__T_RCD=15, PSU__DDRC__T_RP=15, PSU__DDRC__TRAIN_DATA_EYE=1, PSU__DDRC__TRAIN_READ_GATE=1, PSU__DDRC__TRAIN_WRITE_LEVEL=1, PSU__FP__POWER__ON=1, PSU__PL__POWER__ON=1, PSU__OCM_BANK0__POWER__ON=1, PSU__OCM_BANK1__POWER__ON=1, PSU__OCM_BANK2__POWER__ON=1, PSU__OCM_BANK3__POWER__ON=1, PSU__TCM0A__POWER__ON=1, PSU__TCM0B__POWER__ON=1, PSU__TCM1A__POWER__ON=1, PSU__TCM1B__POWER__ON=1, PSU__RPU__POWER__ON=1, PSU__L2_BANK0__POWER__ON=1, PSU__GPU_PP0__POWER__ON=1, PSU__GPU_PP1__POWER__ON=1, PSU__ACPU0__POWER__ON=1\ , PSU__ACPU1__POWER__ON=1, PSU__ACPU2__POWER__ON=1, PSU__ACPU3__POWER__ON=1, PSU__UART0__PERIPHERAL__ENABLE=1, PSU__UART0__PERIPHERAL__IO=MIO 18 .. 19, PSU__UART1__PERIPHERAL__ENABLE=1, PSU__UART1__PERIPHERAL__IO=MIO 20 .. 21, PSU__UART0_LOOP_UART1__ENABLE=0, PSU__UART0__MODEM__ENABLE=0, PSU__UART1__MODEM__ENABLE=0, PSU__USB0__PERIPHERAL__ENABLE=1, PSU__USB0__PERIPHERAL__IO=MIO 52 .. 63, PSU__USB1__PERIPHERAL__ENABLE=0, PSU__CRF_APB__DPLL_CTRL__DIV2=1, PSU__CRF_APB__APLL_CTRL__DIV2=1, PSU__CRL_APB__IOPLL_CTRL__DIV2=1, PSU__CRL_APB__RPLL_CTRL__DIV2=1, PSU__CRF_APB__VPLL_CTRL__DIV2=1, PSU__CRF_APB__APLL_CTRL__FBDIV=72, PSU__CRF_APB__DPLL_CTRL__FBDIV=64, PSU__CRF_APB__VPLL_CTRL__FBDIV=90, PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0=3, PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0=2, PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0=3, PSU__CRF_APB__ACPU_CTRL__DIVISOR0=1, PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0=5, PSU__DISPLAYPORT__PERIPHERAL__ENABLE=1, PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0=2, PSU__CRF_APB__APM_CTRL__DIVISOR0=1, PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0=5, PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1=1, PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0=20, PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1=1, PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0=19, PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1=1, PSU__CRF_APB__DDR_CTRL__DIVISOR0=2, PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0=1, PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI0_REF__ENABLE=0, PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI1_REF__ENABLE=0, PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI2_REF__ENABLE=0, PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI3_REF__ENABLE=0, PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI4_REF__ENABLE=0, PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__AFI5_REF__ENABLE=0, PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0=2\ -, PSU__SATA__PERIPHERAL__ENABLE=1, PSU__SATA__LANE0__ENABLE=0, PSU__SATA__LANE1__ENABLE=1, PSU__SATA__LANE1__IO=GT Lane3, PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0=2, PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0=4, PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0=4, PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0=30, PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0=3, PSU__CRL_APB__AFI6__ENABLE=0, PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0=25, PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1=3, PSU__CRL_APB__USB3__ENABLE=1, PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0=2, PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0=5, PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0=2, PSU__CRL_APB__IOPLL_CTRL__FBDIV=90, PSU__CRL_APB__RPLL_CTRL__FBDIV=90, PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0=3, PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0=3, PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0=6, PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0=6, PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0=6, PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0=7, PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0=8, PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1=1\ +, PSU__SATA__PERIPHERAL__ENABLE=1, PSU__SATA__LANE0__ENABLE=0, PSU__SATA__LANE1__ENABLE=1, PSU__SATA__LANE1__IO=GT Lane3, PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0=2, PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0=4, PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0=4, PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0=30, PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0=3, PSU__CRL_APB__AFI6__ENABLE=0, PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0=25, PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1=3, PSU__CRL_APB__USB3__ENABLE=1, PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0=2, PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0=2, PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0=5, PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0=2, PSU__CRL_APB__IOPLL_CTRL__FBDIV=90, PSU__CRL_APB__RPLL_CTRL__FBDIV=90, PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0=3, PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0=3, PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0=12, PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0=6, PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0=6, PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0=6, PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0=5, PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0=7, PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0=8, PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1=1\ , PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0=7, PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0=7, PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0=6, PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0=3, PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0=3, PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0=6, PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0=4, PSU__CRL_APB__PCAP_CTRL__DIVISOR0=8, PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0=15, PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0=3, PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0=6, PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0=15, PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1=1, PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0=3, PSU__CRF_APB__APLL_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRF_APB__DPLL_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRF_APB__VPLL_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRF_APB__ACPU_CTRL__SRCSEL=APLL, PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL=IOPLL, PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL=IOPLL, PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL=VPLL, PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL=RPLL, PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL=RPLL, PSU__CRF_APB__DDR_CTRL__SRCSEL=DPLL, PSU__CRF_APB__GPU_REF_CTRL__SRCSEL=IOPLL, PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL=DPLL, PSU__CRF_APB__SATA_REF_CTRL__SRCSEL=IOPLL, PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__PL0_REF_CTRL__SRCSEL=RPLL, PSU__CRL_APB__PL1_REF_CTRL__SRCSEL=RPLL, PSU__CRL_APB__PL2_REF_CTRL__SRCSEL=RPLL\ , PSU__CRL_APB__PL3_REF_CTRL__SRCSEL=RPLL, PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL=APLL, PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL=APLL, PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL=DPLL, PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL=IOPLL, PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__IOPLL_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRL_APB__RPLL_CTRL__SRCSEL=PSS_REF_CLK, PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__UART0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__UART1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL=RPLL, PSU__CRL_APB__CPU_R5_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__PCAP_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__NAND_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__DLL_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__AMS_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL=IOPLL, PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL=IOPLL, PSU__IOU_SLCR__WDT_CLK_SEL__SELECT=APB, PSU__FPD_SLCR__WDT_CLK_SEL__SELECT=APB, PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL=APB, PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL=APB, PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL=APB, PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL=APB, PSU__CRF_APB__APLL_FRAC_CFG__ENABLED=0, PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED=0\ -, PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED=0, PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED=0, PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED=0, PSU__OVERRIDE__BASIC_CLOCK=0, PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ=1199.988037, PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ=250, PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ=249.997498, PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ=1, PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ=299.997009, PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ=24.999750, PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ=26.315527, PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ=533.328003, PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ=499.994995, PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ=124.998749, PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ=100, PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ=599.994019, PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ=599.994019, PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ=533.328003, PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ=99.999001, PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ=124.998749, PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ=250, PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ=124.998749, PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ=200, PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ=187.498123, PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ=214, PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ=214, PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ=1000, PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ=499.994995\ -, PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ=500, PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ=500, PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ=187.498123, PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ=499.994995, PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ=499.994995, PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ=1499.984985, PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ=49.999500, PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ=500, PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ=19.999800, PSU__CRF_APB__ACPU_CTRL__FREQMHZ=1200, PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ=250, PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ=250, PSU__CRF_APB__APM_CTRL__FREQMHZ=1, PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ=300, PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ=25, PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ=27, PSU__CRF_APB__DDR_CTRL__FREQMHZ=1067, PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ=500, PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ=250, PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ=100, PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ=600, PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ=600, PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ=533.333, PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ=100, PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ=250, PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ=200\ -, PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ=1000, PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ=500, PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ=500, PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ=250, PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ=400, PSU__CRL_APB__PCAP_CTRL__FREQMHZ=200, PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ=100, PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ=500, PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ=250, PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ=500, PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ=1500, PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ=50, PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ=500, PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ=20, PSU__CSU__CSU_TAMPER_0__ENABLE=0, PSU__CSU__CSU_TAMPER_1__ENABLE=0, PSU__CSU__CSU_TAMPER_2__ENABLE=0, PSU__CSU__CSU_TAMPER_3__ENABLE=0, PSU__CSU__CSU_TAMPER_4__ENABLE=0, PSU__CSU__CSU_TAMPER_5__ENABLE=0, PSU__CSU__CSU_TAMPER_6__ENABLE=0, PSU__CSU__CSU_TAMPER_7__ENABLE=0, PSU__CSU__CSU_TAMPER_8__ENABLE=0, PSU__CSU__CSU_TAMPER_9__ENABLE=0, PSU__CSU__CSU_TAMPER_10__ENABLE=0, PSU__CSU__CSU_TAMPER_11__ENABLE=0, PSU__CSU__CSU_TAMPER_12__ENABLE=0, PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM=0\ +, PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED=0, PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED=0, PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED=0, PSU__OVERRIDE__BASIC_CLOCK=0, PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ=1199.988037, PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ=250, PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ=249.997498, PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ=1, PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ=299.997009, PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ=24.999750, PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ=26.315527, PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ=533.328003, PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ=499.994995, PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ=667, PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ=124.998749, PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ=100, PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ=599.994019, PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ=599.994019, PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ=533.328003, PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ=99.999001, PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ=125, PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ=124.998749, PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ=250, PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ=299.997009, PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ=200, PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ=187.498123, PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ=214, PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ=214, PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ=1000, PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ=499.994995\ +, PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ=500, PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ=500, PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ=187.498123, PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ=499.994995, PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ=249.997498, PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ=100, PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ=499.994995, PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ=1499.984985, PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ=49.999500, PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ=99.999001, PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ=500, PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ=19.999800, PSU__CRF_APB__ACPU_CTRL__FREQMHZ=1333.333, PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ=250, PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ=250, PSU__CRF_APB__APM_CTRL__FREQMHZ=1, PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ=300, PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ=25, PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ=27, PSU__CRF_APB__DDR_CTRL__FREQMHZ=1067, PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ=600, PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ=667, PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ=250, PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ=100, PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ=600, PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ=600, PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ=533.333, PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ=100, PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ=250, PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ=125, PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ=250, PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ=300, PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ=200\ +, PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ=200, PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ=1000, PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ=533.333, PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ=500, PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ=267, PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ=400, PSU__CRL_APB__PCAP_CTRL__FREQMHZ=200, PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ=100, PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ=533.333, PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ=250, PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ=533.333, PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ=1500, PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ=50, PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ=100, PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ=500, PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ=20, PSU__CSU__CSU_TAMPER_0__ENABLE=0, PSU__CSU__CSU_TAMPER_1__ENABLE=0, PSU__CSU__CSU_TAMPER_2__ENABLE=0, PSU__CSU__CSU_TAMPER_3__ENABLE=0, PSU__CSU__CSU_TAMPER_4__ENABLE=0, PSU__CSU__CSU_TAMPER_5__ENABLE=0, PSU__CSU__CSU_TAMPER_6__ENABLE=0, PSU__CSU__CSU_TAMPER_7__ENABLE=0, PSU__CSU__CSU_TAMPER_8__ENABLE=0, PSU__CSU__CSU_TAMPER_9__ENABLE=0, PSU__CSU__CSU_TAMPER_10__ENABLE=0, PSU__CSU__CSU_TAMPER_11__ENABLE=0, PSU__CSU__CSU_TAMPER_12__ENABLE=0, PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM=0, PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM=0\ , PSU__GEN_IPI_0__MASTER=APU, PSU__GEN_IPI_1__MASTER=RPU0, PSU__GEN_IPI_2__MASTER=RPU1, PSU__GEN_IPI_3__MASTER=PMU, PSU__GEN_IPI_4__MASTER=PMU, PSU__GEN_IPI_5__MASTER=PMU, PSU__GEN_IPI_6__MASTER=PMU, PSU__GEN_IPI_7__MASTER=NONE, PSU__GEN_IPI_8__MASTER=NONE, PSU__GEN_IPI_9__MASTER=NONE, PSU__GEN_IPI_10__MASTER=NONE, PSU__PROTECTION__SUBSYSTEMS=PMU Firmware:PMU, PSU__PROTECTION__DDR_SEGMENTS=NONE, PSU__PROTECTION__OCM_SEGMENTS=NONE, PSU__PROTECTION__LPD_SEGMENTS=SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware, PSU__PROTECTION__FPD_SEGMENTS=SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD000000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD020000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD040000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD610000 ;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware, PSU__PROTECTION__DEBUG=0, PSU__PROTECTION__PRESUBSYSTEMS=NONE, PSU__DDR_QOS_ENABLE=0, PSU__DDR_QOS_RD_LPR_THRSHLD=, PSU__DDR_QOS_RD_HPR_THRSHLD=, PSU__DDR_QOS_WR_THRSHLD=, PSU__DDR_QOS_HP0_RDQOS=, PSU__DDR_QOS_HP0_WRQOS=, PSU__DDR_QOS_HP1_RDQOS=, PSU__DDR_QOS_HP1_WRQOS=, PSU__DDR_QOS_HP2_RDQOS=, PSU__DDR_QOS_HP2_WRQOS=, PSU__DDR_QOS_HP3_RDQOS=, PSU__DDR_QOS_HP3_WRQOS= }" *) (* HW_HANDOFF = "pl_eth_10g_zynq_ultra_ps_e_0_0.hwdef" *) diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/pl_eth_10g_zynq_ultra_ps_e_0_0.xml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/pl_eth_10g_zynq_ultra_ps_e_0_0.xml index 508c0ce..8a30552 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/pl_eth_10g_zynq_ultra_ps_e_0_0.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/pl_eth_10g_zynq_ultra_ps_e_0_0.xml @@ -31175,11 +31175,11 @@ GENtimestamp - Fri Oct 20 19:45:15 UTC 2023 + Sat Oct 21 02:29:57 UTC 2023 outputProductCRC - 9:a138200d + 9:d6bf550d @@ -31190,7 +31190,7 @@ outputProductCRC - 9:a138200d + 9:d6bf550d @@ -31206,11 +31206,11 @@ GENtimestamp - Fri Oct 20 19:45:17 UTC 2023 + Sat Oct 21 02:29:59 UTC 2023 outputProductCRC - 9:a138200d + 9:d6bf550d @@ -31235,7 +31235,7 @@ outputProductCRC - 9:30caf542 + 9:ec384d49 @@ -31251,11 +31251,11 @@ GENtimestamp - Fri Oct 20 19:45:18 UTC 2023 + Sat Oct 21 02:29:59 UTC 2023 outputProductCRC - 9:8aa2bfbc + 9:1037eaf7 sim_type @@ -31274,11 +31274,11 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC - 9:30caf542 + 9:ec384d49 @@ -31294,11 +31294,11 @@ GENtimestamp - Fri Oct 20 19:45:19 UTC 2023 + Sat Oct 21 02:30:00 UTC 2023 outputProductCRC - 9:8aa2bfbc + 9:1037eaf7 sim_type @@ -31313,7 +31313,7 @@ outputProductCRC - 9:a138200d + 9:d6bf550d @@ -77788,7 +77788,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 QSPI DIV0 - 12 + 5 @@ -78918,7 +78918,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ ACT QSPI - 124.998749 + 299.997009 PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ @@ -79053,7 +79053,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD PSU__CRF_APB__ACPU_CTRL__FREQMHZ ACPU - 1200 + 1333.333 PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ @@ -79093,7 +79093,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ GPU REF - 500 + 600 PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ @@ -79237,7 +79237,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ QSPI - 125 + 300 PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ @@ -79297,7 +79297,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ CPU_R5 - 500 + 533.333 PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ @@ -79307,7 +79307,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ IOU_SWITCH - 250 + 267 PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ @@ -79327,7 +79327,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ LPD_SWITCH - 500 + 533.333 PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ @@ -79342,7 +79342,7 @@ FFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DD PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ ADMA_REF - 500 + 533.333 PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.c b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.c index 0290275..4076d69 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.c +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.c @@ -960,7 +960,7 @@ unsigned long psu_clock_init_data(void) * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1 * 6 bit divider - * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc + * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0x5 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not @@ -968,10 +968,10 @@ unsigned long psu_clock_init_data(void) * PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 * This register controls this reference clock - * (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U) + * (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010500U) */ PSU_Mask_Write(CRL_APB_QSPI_REF_CTRL_OFFSET, - 0x013F3F07U, 0x01010C00U); + 0x013F3F07U, 0x01010500U); /*##################################################################### */ /* @@ -16082,13 +16082,13 @@ unsigned long psu_peripherals_init_data(void) * 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa * ss the Tap delay on the Rx clock signal of LQSPI - * PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1 + * PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 0 * IOU tap delay bypass for the LQSPI and NAND controllers - * (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) + * (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000000U) */ PSU_Mask_Write(IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET, - 0x00000004U, 0x00000004U); + 0x00000004U, 0x00000000U); /*##################################################################### */ /* diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.html b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.html index c98b9eb..8f9bd3c 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.html +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.html @@ -2267,13 +2267,13 @@ IOPLL QSPI freq (MHz) -125 +300 IOPLL -124.998749 +299.997009 @@ -2365,7 +2365,7 @@ IOPLL CPU_R5 freq (MHz) -500 +533.333 IOPLL @@ -2379,7 +2379,7 @@ IOPLL IOU_SWITCH freq (MHz) -250 +267 IOPLL @@ -2393,7 +2393,7 @@ IOPLL LPD_SWITCH freq (MHz) -500 +533.333 IOPLL @@ -2491,7 +2491,7 @@ IOPLL ADMA freq (MHz) -500 +533.333 IOPLL @@ -2547,7 +2547,7 @@ IOPLL ACPU freq (MHz) -1200 +1333.333 APLL @@ -2659,7 +2659,7 @@ DPLL GPU freq (MHz) -500 +600 IOPLL diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.tcl b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.tcl index 54df77b..b94425d 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.tcl +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init.tcl @@ -614,7 +614,7 @@ set psu_clock_init_data { # PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1 # 6 bit divider - # PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc + # PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0x5 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not @@ -622,8 +622,8 @@ set psu_clock_init_data { # PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U) */ - mask_write 0XFF5E0068 0x013F3F07 0x01010C00 + #(OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010500U) */ + mask_write 0XFF5E0068 0x013F3F07 0x01010500 # Register : SDIO1_REF_CTRL @ 0XFF5E0070

    # Clock active signal. Switch to 0 to disable the clock @@ -13956,11 +13956,11 @@ set psu_peripherals_init_data { # 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa # ss the Tap delay on the Rx clock signal of LQSPI - # PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1 + # PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 0 # IOU tap delay bypass for the LQSPI and NAND controllers - #(OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) */ - mask_write 0XFF180390 0x00000004 0x00000004 + #(OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000000U) */ + mask_write 0XFF180390 0x00000004 0x00000000 # : NAND # : USB RESET # Register : RST_LPD_TOP @ 0XFF5E023C

    diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init_gpl.c b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init_gpl.c index c61524f..a379ee3 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init_gpl.c +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/psu_init_gpl.c @@ -969,7 +969,7 @@ unsigned long psu_clock_init_data(void) * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1 * 6 bit divider - * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc + * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0x5 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not @@ -977,10 +977,10 @@ unsigned long psu_clock_init_data(void) * PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 * This register controls this reference clock - * (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U) + * (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010500U) */ PSU_Mask_Write(CRL_APB_QSPI_REF_CTRL_OFFSET, - 0x013F3F07U, 0x01010C00U); + 0x013F3F07U, 0x01010500U); /*##################################################################### */ /* @@ -16091,13 +16091,13 @@ unsigned long psu_peripherals_init_data(void) * 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa * ss the Tap delay on the Rx clock signal of LQSPI - * PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1 + * PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 0 * IOU tap delay bypass for the LQSPI and NAND controllers - * (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) + * (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000000U) */ PSU_Mask_Write(IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET, - 0x00000004U, 0x00000004U); + 0x00000004U, 0x00000000U); /*##################################################################### */ /* diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/pl_eth_10g.bda b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/pl_eth_10g.bda index d142c62..a8efa14 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/pl_eth_10g.bda +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/pl_eth_10g.bda @@ -21,6 +21,101 @@ + 0xC0000000 + C_BASEADDR + 0xDFFFFFFF + C_HIGHADDR + Data_S2MM + /axi_dma_0 + M_AXI_S2MM + SEG_zynq_ultra_ps_e_0_HP0_QSPI + xilinx.com:ip:axi_dma:7.1 + both + /zups/zynq_ultra_ps_e_0 + S_AXI_HP0_FPD + HP0_QSPI + xilinx.com:ip:zynq_ultra_ps_e:3.3 + memory + AC + + + 0xE0000000 + C_BASEADDR + 0xEFFFFFFF + C_HIGHADDR + Data_SG + /axi_dma_0 + M_AXI_SG + SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW + xilinx.com:ip:axi_dma:7.1 + both + /zups/zynq_ultra_ps_e_0 + S_AXI_HP0_FPD + HP0_PCIE_LOW + xilinx.com:ip:zynq_ultra_ps_e:3.3 + memory + AC + + + 0xC0000000 + C_BASEADDR + 0xDFFFFFFF + C_HIGHADDR + Data_SG + /axi_dma_0 + M_AXI_SG + SEG_zynq_ultra_ps_e_0_HP0_QSPI + xilinx.com:ip:axi_dma:7.1 + both + /zups/zynq_ultra_ps_e_0 + S_AXI_HP0_FPD + HP0_QSPI + xilinx.com:ip:zynq_ultra_ps_e:3.3 + memory + AC + + + 0xC0000000 + C_BASEADDR + 0xDFFFFFFF + C_HIGHADDR + Data_MM2S + /axi_dma_0 + M_AXI_MM2S + SEG_zynq_ultra_ps_e_0_HP0_QSPI + xilinx.com:ip:axi_dma:7.1 + both + /zups/zynq_ultra_ps_e_0 + S_AXI_HP0_FPD + HP0_QSPI + xilinx.com:ip:zynq_ultra_ps_e:3.3 + memory + AC + + + 2 + pl_eth_10g + VR + + + 0xE0000000 + C_BASEADDR + 0xEFFFFFFF + C_HIGHADDR + Data_MM2S + /axi_dma_0 + M_AXI_MM2S + SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW + xilinx.com:ip:axi_dma:7.1 + both + /zups/zynq_ultra_ps_e_0 + S_AXI_HP0_FPD + HP0_PCIE_LOW + xilinx.com:ip:zynq_ultra_ps_e:3.3 + memory + AC + + 0x00000000 C_BASEADDR 0x7FFFFFFF @@ -38,52 +133,7 @@ memory AC - - active - 2 - PM - - - pl_eth_10g - BC - - - 0xE0000000 - C_BASEADDR - 0xEFFFFFFF - C_HIGHADDR - Data_S2MM - /axi_dma_0 - M_AXI_S2MM - SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW - xilinx.com:ip:axi_dma:7.1 - both - /zups/zynq_ultra_ps_e_0 - S_AXI_HP0_FPD - HP0_PCIE_LOW - xilinx.com:ip:zynq_ultra_ps_e:3.3 - memory - AC - - - 0xE0000000 - C_BASEADDR - 0xEFFFFFFF - C_HIGHADDR - Data_MM2S - /axi_dma_0 - M_AXI_MM2S - SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW - xilinx.com:ip:axi_dma:7.1 - both - /zups/zynq_ultra_ps_e_0 - S_AXI_HP0_FPD - HP0_PCIE_LOW - xilinx.com:ip:zynq_ultra_ps_e:3.3 - memory - AC - - + 0x0080010000 C_BASEADDR 0x008001FFFF @@ -101,61 +151,7 @@ register AC - - 0xE0000000 - C_BASEADDR - 0xEFFFFFFF - C_HIGHADDR - Data_SG - /axi_dma_0 - M_AXI_SG - SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW - xilinx.com:ip:axi_dma:7.1 - both - /zups/zynq_ultra_ps_e_0 - S_AXI_HP0_FPD - HP0_PCIE_LOW - xilinx.com:ip:zynq_ultra_ps_e:3.3 - memory - AC - - - 0xC0000000 - C_BASEADDR - 0xDFFFFFFF - C_HIGHADDR - Data_SG - /axi_dma_0 - M_AXI_SG - SEG_zynq_ultra_ps_e_0_HP0_QSPI - xilinx.com:ip:axi_dma:7.1 - both - /zups/zynq_ultra_ps_e_0 - S_AXI_HP0_FPD - HP0_QSPI - xilinx.com:ip:zynq_ultra_ps_e:3.3 - memory - AC - - 0xC0000000 - C_BASEADDR - 0xDFFFFFFF - C_HIGHADDR - Data_MM2S - /axi_dma_0 - M_AXI_MM2S - SEG_zynq_ultra_ps_e_0_HP0_QSPI - xilinx.com:ip:axi_dma:7.1 - both - /zups/zynq_ultra_ps_e_0 - S_AXI_HP0_FPD - HP0_QSPI - xilinx.com:ip:zynq_ultra_ps_e:3.3 - memory - AC - - 0x0080000000 C_BASEADDR 0x008000FFFF @@ -173,7 +169,7 @@ register AC - + 0x00000000 C_BASEADDR 0x7FFFFFFF @@ -191,7 +187,7 @@ memory AC - + 0x00000000 C_BASEADDR 0x7FFFFFFF @@ -209,30 +205,29 @@ memory AC + + pl_eth_10g + BC + - 0xC0000000 + 0xE0000000 C_BASEADDR - 0xDFFFFFFF + 0xEFFFFFFF C_HIGHADDR Data_S2MM /axi_dma_0 M_AXI_S2MM - SEG_zynq_ultra_ps_e_0_HP0_QSPI + SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW xilinx.com:ip:axi_dma:7.1 both /zups/zynq_ultra_ps_e_0 S_AXI_HP0_FPD - HP0_QSPI + HP0_PCIE_LOW xilinx.com:ip:zynq_ultra_ps_e:3.3 memory AC - 2 - pl_eth_10g - VR - - 0xFF000000 C_BASEADDR 0xFFFFFFFF @@ -250,44 +245,49 @@ register AC - + + active + 2 + PM + + - + - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/pl_eth_10g.bxml b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/pl_eth_10g.bxml index 5afc622..964e856 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/pl_eth_10g.bxml +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/pl_eth_10g.bxml @@ -2,10 +2,10 @@ Composite Fileset - - - - + + + + diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/sim/pl_eth_10g.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/sim/pl_eth_10g.v index 31acda9..a64a335 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/sim/pl_eth_10g.v +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/sim/pl_eth_10g.v @@ -1,7 +1,7 @@ //Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -//Date : Fri Oct 20 12:44:41 2023 +//Date : Fri Oct 20 19:29:21 2023 //Host : DESKTOP-5FH9OH3 running 64-bit major release (build 9200) //Command : generate_target pl_eth_10g.bd //Design : pl_eth_10g diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/synth/pl_eth_10g.hwdef b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/synth/pl_eth_10g.hwdef index c573164..f2a5f24 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/synth/pl_eth_10g.hwdef and b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/synth/pl_eth_10g.hwdef differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/synth/pl_eth_10g.v b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/synth/pl_eth_10g.v index 31acda9..a64a335 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/synth/pl_eth_10g.v +++ b/src/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/synth/pl_eth_10g.v @@ -1,7 +1,7 @@ //Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -//Date : Fri Oct 20 12:44:41 2023 +//Date : Fri Oct 20 19:29:21 2023 //Host : DESKTOP-5FH9OH3 running 64-bit major release (build 9200) //Command : generate_target pl_eth_10g.bd //Design : pl_eth_10g diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/.jobs/vrs_config_10.xml b/src/pl_eth_10g_hw/pl_eth_10g.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..18b0723 --- /dev/null +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/.jobs/vrs_config_8.xml b/src/pl_eth_10g_hw/pl_eth_10g.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..a181675 --- /dev/null +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/.jobs/vrs_config_9.xml b/src/pl_eth_10g_hw/pl_eth_10g.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..ad543f4 --- /dev/null +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.init_design.begin.rst b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.init_design.begin.rst index 51522e7..80574a9 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.init_design.begin.rst +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.init_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.opt_design.begin.rst b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.opt_design.begin.rst index 51522e7..80574a9 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.opt_design.begin.rst +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.opt_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.phys_opt_design.begin.rst b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.phys_opt_design.begin.rst index 51522e7..80574a9 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.phys_opt_design.begin.rst +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.phys_opt_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.place_design.begin.rst b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.place_design.begin.rst index 51522e7..80574a9 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.place_design.begin.rst +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.place_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.route_design.begin.rst b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.route_design.begin.rst index 51522e7..80574a9 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.route_design.begin.rst +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.route_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.vivado.begin.rst b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.vivado.begin.rst index 0002ec1..38a1c70 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.vivado.begin.rst +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.vivado.begin.rst @@ -1,10 +1,10 @@ - + - + diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.write_bitstream.begin.rst b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.write_bitstream.begin.rst index 73cb71a..8b5f168 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.write_bitstream.begin.rst +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/.write_bitstream.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/gen_run.xml b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/gen_run.xml index 159e8cd..a8d8d0f 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/gen_run.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/init_design.pb b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/init_design.pb index 57c6c5b..ea7c631 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/init_design.pb and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/init_design.pb differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/opt_design.pb b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/opt_design.pb index 2c8ca2a..b412004 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/opt_design.pb and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/opt_design.pb differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/phys_opt_design.pb b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/phys_opt_design.pb index 12d1a98..40d7189 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/phys_opt_design.pb and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/phys_opt_design.pb differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.bit b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.bit index 244b75b..a509357 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.bit and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.bit differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.hwdef b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.hwdef index 8348f3d..711d3a3 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.hwdef and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.hwdef differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.vdi b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.vdi index 0ff05f7..7104c73 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.vdi +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.vdi @@ -2,8 +2,8 @@ # Vivado v2020.2 (64-bit) # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 -# Start of session at: Fri Oct 20 12:54:24 2023 -# Process ID: 69332 +# Start of session at: Fri Oct 20 19:41:49 2023 +# Process ID: 171500 # Current directory: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1 # Command line: vivado.exe -log pl_eth_10g_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source pl_eth_10g_wrapper.tcl -notrace # Log file: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.vdi @@ -13,12 +13,12 @@ source pl_eth_10g_wrapper.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'. -add_files: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1144.477 ; gain = 0.000 +add_files: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1144.215 ; gain = 0.000 Command: link_design -top pl_eth_10g_wrapper -part xczu7ev-ffvc1156-2-e Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.816 . Memory (MB): peak = 1762.703 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.810 . Memory (MB): peak = 1759.492 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 876 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 @@ -53,7 +53,7 @@ Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardwar Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_clocks.xdc:16] INFO: [Timing 38-2] Deriving generated clocks [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_clocks.xdc:16] -all_fanout: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2297.480 ; gain = 330.117 +all_fanout: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2295.293 ; gain = 328.082 Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst' Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst' Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst' @@ -66,7 +66,7 @@ Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardwar INFO: [Project 1-1715] 7 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 18 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2299.633 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2297.664 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 62 instances were transformed. RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 13 instances @@ -75,7 +75,7 @@ INFO: [Project 1-111] Unisim Transformation Summary: 14 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:31 . Memory (MB): peak = 2299.633 ; gain = 1155.156 +link_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:31 . Memory (MB): peak = 2297.664 ; gain = 1153.449 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' @@ -86,58 +86,58 @@ INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2299.633 ; gain = 0.000 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2297.664 ; gain = 0.000 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: d5ae2a81 +Ending Cache Timing Information Task | Checksum: 138337785 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2299.633 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2297.664 ; gain = 0.000 Starting Logic Optimization Task Phase 1 Retarget -INFO: [Opt 31-138] Pushed 41 inverter(s) to 2272 load pin(s). +INFO: [Opt 31-138] Pushed 41 inverter(s) to 2274 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 261221661 +Phase 1 Retarget | Checksum: 12f7198c8 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2487.625 ; gain = 2.207 -INFO: [Opt 31-389] Phase Retarget created 9 cells and removed 434 cells +Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2482.816 ; gain = 2.074 +INFO: [Opt 31-389] Phase Retarget created 9 cells and removed 433 cells INFO: [Opt 31-1021] In phase Retarget, 143 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 1e002a5df +Phase 2 Constant propagation | Checksum: 13a3a3d4f -Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2487.625 ; gain = 2.207 -INFO: [Opt 31-389] Phase Constant propagation created 492 cells and removed 1260 cells +Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2482.816 ; gain = 2.074 +INFO: [Opt 31-389] Phase Constant propagation created 490 cells and removed 1256 cells INFO: [Opt 31-1021] In phase Constant propagation, 142 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Sweep -Phase 3 Sweep | Checksum: 20d6b0d7d +Phase 3 Sweep | Checksum: 17dc2c8da -Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2487.625 ; gain = 2.207 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2482.816 ; gain = 2.074 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1051 cells INFO: [Opt 31-1021] In phase Sweep, 407 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT. -Phase 4 BUFG optimization | Checksum: 20d6b0d7d +Phase 4 BUFG optimization | Checksum: 17dc2c8da -Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2487.625 ; gain = 2.207 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2482.816 ; gain = 2.074 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 5 Shift Register Optimization | Checksum: 20d6b0d7d +Phase 5 Shift Register Optimization | Checksum: 17dc2c8da -Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2487.625 ; gain = 2.207 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2482.816 ; gain = 2.074 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 20d6b0d7d +Phase 6 Post Processing Netlist | Checksum: 17dc2c8da -Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 2487.625 ; gain = 2.207 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2482.816 ; gain = 2.074 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 175 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary @@ -147,8 +147,8 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- -| Retarget | 9 | 434 | 143 | -| Constant propagation | 492 | 1260 | 142 | +| Retarget | 9 | 433 | 143 | +| Constant propagation | 490 | 1256 | 142 | | Sweep | 0 | 1051 | 407 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | @@ -159,10 +159,10 @@ Opt_design Change Summary Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 2487.625 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 1e5ca8a39 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.109 . Memory (MB): peak = 2482.816 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 2040f7235 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2487.625 ; gain = 2.207 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2482.816 ; gain = 2.074 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. @@ -179,43 +179,43 @@ INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 139 ha INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 133 WE to EN ports Number of BRAM Ports augmented: 5 newly gated: 133 Total Ports: 278 -Ending PowerOpt Patch Enables Task | Checksum: 1d101fdd6 +Ending PowerOpt Patch Enables Task | Checksum: 2397c5aae -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Ending Power Optimization Task | Checksum: 1d101fdd6 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Ending Power Optimization Task | Checksum: 2397c5aae -Time (s): cpu = 00:00:38 ; elapsed = 00:00:44 . Memory (MB): peak = 4688.359 ; gain = 2200.734 +Time (s): cpu = 00:00:50 ; elapsed = 00:00:47 . Memory (MB): peak = 4670.074 ; gain = 2187.258 Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 1d101fdd6 +Ending Final Cleanup Task | Checksum: 2397c5aae -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4670.074 ; gain = 0.000 Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.094 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 1d9522167 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 1e978e3e4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.094 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 42 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:58 . Memory (MB): peak = 4688.359 ; gain = 2388.727 +opt_design: Time (s): cpu = 00:01:04 ; elapsed = 00:01:01 . Memory (MB): peak = 4670.074 ; gain = 2372.410 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.064 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_opt.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [runtcl-4] Executing : report_drc -file pl_eth_10g_wrapper_drc_opted.rpt -pb pl_eth_10g_wrapper_drc_opted.pb -rpx pl_eth_10g_wrapper_drc_opted.rpx Command: report_drc -file pl_eth_10g_wrapper_drc_opted.rpt -pb pl_eth_10g_wrapper_drc_opted.pb -rpx pl_eth_10g_wrapper_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_opted.rpt. report_drc completed successfully -report_drc: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 4688.359 ; gain = 0.000 +report_drc: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' @@ -234,29 +234,29 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 135b4e4ba +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14ac46bc1 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14ad04f73 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a4892a73 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 1bf2762b0 +Phase 1.3 Build Placer Netlist Model | Checksum: a636ca79 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 1bf2762b0 +Phase 1.4 Constrain Clocks/Macros | Checksum: a636ca79 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 1bf2762b0 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: a636ca79 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2 Global Placement @@ -265,61 +265,61 @@ Phase 2.1 Floorplanning Phase 2.1.1 Partition Driven Placement Phase 2.1.1.1 PBP: Partition Driven Placement -Phase 2.1.1.1 PBP: Partition Driven Placement | Checksum: 24259bfbd +Phase 2.1.1.1 PBP: Partition Driven Placement | Checksum: be748173 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:28 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.1.1.2 PBP: Clock Region Placement -Phase 2.1.1.2 PBP: Clock Region Placement | Checksum: 182bf8902 +Phase 2.1.1.2 PBP: Clock Region Placement | Checksum: a4c8b2cf -Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.1.1.3 PBP: Discrete Incremental -Phase 2.1.1.3 PBP: Discrete Incremental | Checksum: 1683ce54b +Phase 2.1.1.3 PBP: Discrete Incremental | Checksum: 19273f8f0 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.1.1.4 PBP: Compute Congestion -Phase 2.1.1.4 PBP: Compute Congestion | Checksum: 1683ce54b +Phase 2.1.1.4 PBP: Compute Congestion | Checksum: 19273f8f0 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.1.1.5 PBP: Macro Placement -Phase 2.1.1.5 PBP: Macro Placement | Checksum: 1b60fd256 +Phase 2.1.1.5 PBP: Macro Placement | Checksum: a17d3753 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.1.1.6 PBP: UpdateTiming -Phase 2.1.1.6 PBP: UpdateTiming | Checksum: 1de9913ba +Phase 2.1.1.6 PBP: UpdateTiming | Checksum: af3a95f3 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.1.1.7 PBP: Add part constraints -Phase 2.1.1.7 PBP: Add part constraints | Checksum: 1de9913ba +Phase 2.1.1.7 PBP: Add part constraints | Checksum: af3a95f3 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 2.1.1 Partition Driven Placement | Checksum: 1de9913ba +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 2.1.1 Partition Driven Placement | Checksum: af3a95f3 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 2.1 Floorplanning | Checksum: 1de9913ba +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 2.1 Floorplanning | Checksum: af3a95f3 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.2 Update Timing before SLR Path Opt -Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1de9913ba +Phase 2.2 Update Timing before SLR Path Opt | Checksum: af3a95f3 -Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer -INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 938 LUT instances to create LUTNM shape +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 927 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-775] End 1 Pass. Optimized 367 nets or cells. Created 0 new cell, deleted 367 existing cells and moved 0 existing cell -INFO: [Physopt 32-1030] Pass 1. Identified 33 candidate driver sets for equivalent driver rewiring. -INFO: [Physopt 32-661] Optimized 22 nets. Re-placed 244 instances. -INFO: [Physopt 32-775] End 1 Pass. Optimized 22 nets or cells. Created 0 new cell, deleted 1 existing cell and moved 244 existing cells -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.198 . Memory (MB): peak = 4688.359 ; gain = 0.000 +INFO: [Physopt 32-1030] Pass 1. Identified 31 candidate driver sets for equivalent driver rewiring. +INFO: [Physopt 32-661] Optimized 24 nets. Re-placed 265 instances. +INFO: [Physopt 32-775] End 1 Pass. Optimized 24 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 265 existing cells +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.154 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell @@ -330,7 +330,7 @@ INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 4670.074 ; gain = 0.000 Summary of Physical Synthesis Optimizations ============================================ @@ -340,7 +340,7 @@ Summary of Physical Synthesis Optimizations | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 367 | 367 | 0 | 1 | 00:00:01 | -| Equivalent Driver Rewiring | 0 | 1 | 22 | 0 | 1 | 00:00:03 | +| Equivalent Driver Rewiring | 0 | 0 | 24 | 0 | 1 | 00:00:03 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | @@ -348,64 +348,64 @@ Summary of Physical Synthesis Optimizations | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 368 | 389 | 0 | 4 | 00:00:04 | +| Total | 0 | 367 | 391 | 0 | 4 | 00:00:04 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- -Phase 2.3.1 Physical Synthesis In Placer | Checksum: 22a901e76 +Phase 2.3.1 Physical Synthesis In Placer | Checksum: 139138c10 -Time (s): cpu = 00:00:52 ; elapsed = 00:01:21 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 2.3 Global Placement Core | Checksum: 184ba6d65 +Time (s): cpu = 00:01:03 ; elapsed = 00:01:14 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 2.3 Global Placement Core | Checksum: 167c195fa -Time (s): cpu = 00:00:55 ; elapsed = 00:01:26 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 184ba6d65 +Time (s): cpu = 00:01:07 ; elapsed = 00:01:18 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 167c195fa -Time (s): cpu = 00:00:55 ; elapsed = 00:01:26 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:07 ; elapsed = 00:01:18 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 1829a8e06 +Phase 3.1 Commit Multi Column Macros | Checksum: 1599f8778 -Time (s): cpu = 00:00:57 ; elapsed = 00:01:28 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:09 ; elapsed = 00:01:21 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c2077e23 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 132be9d92 -Time (s): cpu = 00:00:58 ; elapsed = 00:01:31 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:12 ; elapsed = 00:01:23 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 3.3 Small Shape DP Phase 3.3.1 Small Shape Clustering -Phase 3.3.1 Small Shape Clustering | Checksum: 10bc04dd4 +Phase 3.3.1 Small Shape Clustering | Checksum: a1b5ebd2 -Time (s): cpu = 00:01:02 ; elapsed = 00:01:35 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:17 ; elapsed = 00:01:28 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 3.3.2 Flow Legalize Slice Clusters -Phase 3.3.2 Flow Legalize Slice Clusters | Checksum: e00bb846 +Phase 3.3.2 Flow Legalize Slice Clusters | Checksum: 66bdfa70 -Time (s): cpu = 00:01:03 ; elapsed = 00:01:35 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:17 ; elapsed = 00:01:28 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 3.3.3 Slice Area Swap -Phase 3.3.3 Slice Area Swap | Checksum: 13cea96ba +Phase 3.3.3 Slice Area Swap | Checksum: b4a03078 -Time (s): cpu = 00:01:04 ; elapsed = 00:01:42 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 3.3 Small Shape DP | Checksum: 1e9d05258 +Time (s): cpu = 00:01:18 ; elapsed = 00:01:31 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 3.3 Small Shape DP | Checksum: f3e77f5a -Time (s): cpu = 00:01:12 ; elapsed = 00:01:48 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:27 ; elapsed = 00:01:37 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 3.4 Re-assign LUT pins -Phase 3.4 Re-assign LUT pins | Checksum: 1cc66f7a9 +Phase 3.4 Re-assign LUT pins | Checksum: 1ccb856d8 -Time (s): cpu = 00:01:13 ; elapsed = 00:01:52 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:29 ; elapsed = 00:01:41 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 3.5 Pipeline Register Optimization -Phase 3.5 Pipeline Register Optimization | Checksum: f627ec5f +Phase 3.5 Pipeline Register Optimization | Checksum: 1646d4a6a -Time (s): cpu = 00:01:14 ; elapsed = 00:01:52 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: f627ec5f +Time (s): cpu = 00:01:30 ; elapsed = 00:01:42 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 1646d4a6a -Time (s): cpu = 00:01:14 ; elapsed = 00:01:52 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:30 ; elapsed = 00:01:42 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up @@ -413,7 +413,7 @@ Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 10661162e +Post Placement Optimization Initialization | Checksum: 21ad82e5a Phase 4.1.1.1 BUFG Insertion @@ -421,33 +421,33 @@ Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.577 | TNS=0.000 | -Phase 1 Physical Synthesis Initialization | Checksum: 1c374d8b9 +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.637 | TNS=0.000 | +Phase 1 Physical Synthesis Initialization | Checksum: 1947f44a7 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Place 46-35] Processed net pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0], inserted BUFG to drive 1680 loads. INFO: [Place 46-35] Processed net pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out, inserted BUFG to drive 1159 loads. INFO: [Place 46-45] Replicated bufg driver pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out_reg_replica INFO: [Place 46-35] Processed net pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0], inserted BUFG to drive 1152 loads. INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 3, Replicated BUFG Driver: 1, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. -Ending Physical Synthesis Task | Checksum: b7d053a7 +Ending Physical Synthesis Task | Checksum: 161227327 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 4.1.1.1 BUFG Insertion | Checksum: a2080de3 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 4.1.1.1 BUFG Insertion | Checksum: 1b3d14eea -Time (s): cpu = 00:01:24 ; elapsed = 00:02:05 . Memory (MB): peak = 4688.359 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=1.577. For the most accurate timing information please run report_timing. +Time (s): cpu = 00:01:42 ; elapsed = 00:01:56 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Place 30-746] Post Placement Timing Summary WNS=1.637. For the most accurate timing information please run report_timing. -Time (s): cpu = 00:01:24 ; elapsed = 00:02:05 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: d011626d +Time (s): cpu = 00:01:42 ; elapsed = 00:01:56 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 4.1 Post Commit Optimization | Checksum: 18af3dba2 -Time (s): cpu = 00:01:24 ; elapsed = 00:02:06 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:42 ; elapsed = 00:01:57 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 1a4375091 +Phase 4.2 Post Placement Cleanup | Checksum: 1fb723624 -Time (s): cpu = 00:01:27 ; elapsed = 00:02:09 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:46 ; elapsed = 00:02:00 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 4.3 Placer Reporting @@ -466,40 +466,40 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion | West| 1x1| 1x1| 4x4| |___________|___________________|___________________|___________________| -Phase 4.3.1 Print Estimated Congestion | Checksum: 1a4375091 +Phase 4.3.1 Print Estimated Congestion | Checksum: 1fb723624 -Time (s): cpu = 00:01:27 ; elapsed = 00:02:09 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 4.3 Placer Reporting | Checksum: 1a4375091 +Time (s): cpu = 00:01:46 ; elapsed = 00:02:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 4.3 Placer Reporting | Checksum: 1fb723624 -Time (s): cpu = 00:01:28 ; elapsed = 00:02:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:46 ; elapsed = 00:02:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 4670.074 ; gain = 0.000 -Time (s): cpu = 00:01:28 ; elapsed = 00:02:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21b3ac3a0 +Time (s): cpu = 00:01:46 ; elapsed = 00:02:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 269a85b9d -Time (s): cpu = 00:01:28 ; elapsed = 00:02:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Ending Placer Task | Checksum: 1779cef7d +Time (s): cpu = 00:01:47 ; elapsed = 00:02:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Ending Placer Task | Checksum: 1e2aa1291 -Time (s): cpu = 00:01:28 ; elapsed = 00:02:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:47 ; elapsed = 00:02:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 84 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. place_design completed successfully -place_design: Time (s): cpu = 00:01:30 ; elapsed = 00:02:12 . Memory (MB): peak = 4688.359 ; gain = 0.000 +place_design: Time (s): cpu = 00:01:50 ; elapsed = 00:02:04 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_placed.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 4688.359 ; gain = 0.000 +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [runtcl-4] Executing : report_io -file pl_eth_10g_wrapper_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.071 . Memory (MB): peak = 4688.359 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.080 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file pl_eth_10g_wrapper_utilization_placed.rpt -pb pl_eth_10g_wrapper_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file pl_eth_10g_wrapper_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 4688.359 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.127 . Memory (MB): peak = 4670.074 ; gain = 0.000 Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' @@ -508,15 +508,15 @@ INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 93 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully -phys_opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 4688.359 ; gain = 0.000 +phys_opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_physopt.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 4688.359 ; gain = 0.000 +write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' @@ -528,150 +528,153 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: 1cdd801d ConstDB: 0 ShapeSum: 8699813c RouteDB: d425ee24 +Checksum: PlaceDB: ba17791b ConstDB: 0 ShapeSum: b8143ef4 RouteDB: 707e5a82 Phase 1 Build RT Design -Nodegraph reading from file. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 1 Build RT Design | Checksum: 121342218 +Nodegraph reading from file. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 1 Build RT Design | Checksum: 1ccd8f4d8 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Post Restoration Checksum: NetGraph: f18a6085 NumContArr: 2d83f4b7 Constraints: 7fa99f0d Timing: 0 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Post Restoration Checksum: NetGraph: eaea5d6 NumContArr: 4d575875 Constraints: c401714a Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: 19eb7f449 +Phase 2.1 Create Timer | Checksum: 120076f95 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: 19eb7f449 +Phase 2.2 Fix Topology Constraints | Checksum: 120076f95 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: 19eb7f449 +Phase 2.3 Pre Route Cleanup | Checksum: 120076f95 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.4 Global Clock Net Routing Number of Nodes with overlaps = 0 -Phase 2.4 Global Clock Net Routing | Checksum: 12230a291 +Phase 2.4 Global Clock Net Routing | Checksum: 12fb7e7e6 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.5 Update Timing -Phase 2.5 Update Timing | Checksum: 213dbeb6f +Phase 2.5 Update Timing | Checksum: 265dc8b5b -Time (s): cpu = 00:00:12 ; elapsed = 00:00:24 . Memory (MB): peak = 4688.359 ; gain = 0.000 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.730 | TNS=0.000 | WHS=-0.156 | THS=-20.586| +Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.822 | TNS=0.000 | WHS=-0.190 | THS=-26.919| Phase 2.6 Update Timing for Bus Skew Phase 2.6.1 Update Timing -Phase 2.6.1 Update Timing | Checksum: 24e59fe80 +Phase 2.6.1 Update Timing | Checksum: 27464ca79 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:38 . Memory (MB): peak = 4688.359 ; gain = 0.000 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.730 | TNS=0.000 | WHS=N/A | THS=N/A | +Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.822 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 2.6 Update Timing for Bus Skew | Checksum: 24f74bfa0 +Phase 2.6 Update Timing for Bus Skew | Checksum: 24be47c62 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:38 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 2 Router Initialization | Checksum: 21144913e +Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 2 Router Initialization | Checksum: 227779a70 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:38 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 Router Utilization Summary - Global Vertical Routing Utilization = 0.000163859 % - Global Horizontal Routing Utilization = 0.000207685 % + Global Vertical Routing Utilization = 5.04182e-05 % + Global Horizontal Routing Utilization = 0.000129803 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. - Number of Failed Nets = 46937 + Number of Failed Nets = 46965 (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 40192 - Number of Partially Routed Nets = 6745 + Number of Unrouted Nets = 40223 + Number of Partially Routed Nets = 6742 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing -Phase 3.1 Global Routing | Checksum: 21144913e +Phase 3.1 Global Routing | Checksum: 227779a70 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:39 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 3 Initial Routing | Checksum: 4368cb15 +Time (s): cpu = 00:00:25 ; elapsed = 00:00:33 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 3 Initial Routing | Checksum: 1d65e8aff -Time (s): cpu = 00:00:28 ; elapsed = 00:00:46 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 6167 - Number of Nodes with overlaps = 386 - Number of Nodes with overlaps = 11 - Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 5873 + Number of Nodes with overlaps = 350 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.870 | TNS=0.000 | WHS=-0.040 | THS=-0.082 | + +Phase 4.1 Global Iteration 0 | Checksum: 13fe249c9 + +Time (s): cpu = 00:00:45 ; elapsed = 00:01:11 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.423 | TNS=0.000 | WHS=-0.005 | THS=-0.006 | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.870 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 4.1 Global Iteration 0 | Checksum: 1f712922e +Phase 4.2 Global Iteration 1 | Checksum: 1ca0d0fbb -Time (s): cpu = 00:00:42 ; elapsed = 00:01:21 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:48 ; elapsed = 00:01:15 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 4 Rip-up And Reroute | Checksum: 1ca0d0fbb -Phase 4.2 Additional Iteration for Hold -Phase 4.2 Additional Iteration for Hold | Checksum: 1fbb3bf88 - -Time (s): cpu = 00:00:43 ; elapsed = 00:01:21 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 4 Rip-up And Reroute | Checksum: 1fbb3bf88 - -Time (s): cpu = 00:00:43 ; elapsed = 00:01:21 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:48 ; elapsed = 00:01:15 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing -Phase 5.1.1 Update Timing | Checksum: 25dbf9062 +Phase 5.1.1 Update Timing | Checksum: 1b62e6b82 -Time (s): cpu = 00:00:46 ; elapsed = 00:01:26 . Memory (MB): peak = 4688.359 ; gain = 0.000 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.423 | TNS=0.000 | WHS=0.011 | THS=0.000 | +Time (s): cpu = 00:00:52 ; elapsed = 00:01:20 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.870 | TNS=0.000 | WHS=0.010 | THS=0.000 | -Phase 5.1 Delay CleanUp | Checksum: 1e7c15182 +Phase 5.1 Delay CleanUp | Checksum: 22b577808 -Time (s): cpu = 00:00:46 ; elapsed = 00:01:27 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:52 ; elapsed = 00:01:20 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 1e7c15182 +Phase 5.2 Clock Skew Optimization | Checksum: 22b577808 -Time (s): cpu = 00:00:46 ; elapsed = 00:01:27 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 5 Delay and Skew Optimization | Checksum: 1e7c15182 +Time (s): cpu = 00:00:52 ; elapsed = 00:01:21 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 5 Delay and Skew Optimization | Checksum: 22b577808 -Time (s): cpu = 00:00:46 ; elapsed = 00:01:27 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:52 ; elapsed = 00:01:21 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 21862d4aa +Phase 6.1.1 Update Timing | Checksum: 1805b0dba -Time (s): cpu = 00:00:48 ; elapsed = 00:01:31 . Memory (MB): peak = 4688.359 ; gain = 0.000 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.423 | TNS=0.000 | WHS=0.011 | THS=0.000 | +Time (s): cpu = 00:00:55 ; elapsed = 00:01:24 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.870 | TNS=0.000 | WHS=0.010 | THS=0.000 | -Phase 6.1 Hold Fix Iter | Checksum: 28e5b0a03 +Phase 6.1 Hold Fix Iter | Checksum: 16069ca04 -Time (s): cpu = 00:00:48 ; elapsed = 00:01:32 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 6 Post Hold Fix | Checksum: 28e5b0a03 +Time (s): cpu = 00:00:56 ; elapsed = 00:01:25 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 6 Post Hold Fix | Checksum: 16069ca04 -Time (s): cpu = 00:00:48 ; elapsed = 00:01:32 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:56 ; elapsed = 00:01:25 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 3.24213 % - Global Horizontal Routing Utilization = 2.86314 % + Global Vertical Routing Utilization = 3.18683 % + Global Horizontal Routing Utilization = 2.82098 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -681,61 +684,61 @@ Router Utilization Summary Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 7 Route finalize | Checksum: 28559f170 +Phase 7 Route finalize | Checksum: 1cf9de95a -Time (s): cpu = 00:00:49 ; elapsed = 00:01:32 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:57 ; elapsed = 00:01:25 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 28559f170 +Phase 8 Verifying routed nets | Checksum: 1cf9de95a -Time (s): cpu = 00:00:49 ; elapsed = 00:01:33 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:57 ; elapsed = 00:01:26 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 9 Depositing Routes INFO: [Route 35-467] Router swapped GT pin pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_common_wrapper/pl_eth_10g_xxv_ethernet_0_0_gt_gthe4_common_wrapper_i/common_inst/gthe4_common_gen.GTHE4_COMMON_PRIM_INST/GTREFCLK00 to physical pin GTHE4_COMMON_X0Y2/COM0_REFCLKOUT5 -Phase 9 Depositing Routes | Checksum: 28559f170 +Phase 9 Depositing Routes | Checksum: 1cf9de95a -Time (s): cpu = 00:00:50 ; elapsed = 00:01:38 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:59 ; elapsed = 00:01:30 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=1.423 | TNS=0.000 | WHS=0.011 | THS=0.000 | +INFO: [Route 35-57] Estimated Timing Summary | WNS=0.870 | TNS=0.000 | WHS=0.010 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 28559f170 +Phase 10 Post Router Timing | Checksum: 1cf9de95a -Time (s): cpu = 00:00:51 ; elapsed = 00:01:38 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:59 ; elapsed = 00:01:30 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Route 35-16] Router Completed Successfully -Time (s): cpu = 00:00:51 ; elapsed = 00:01:38 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:59 ; elapsed = 00:01:30 . Memory (MB): peak = 4670.074 ; gain = 0.000 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation -110 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. +111 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:55 ; elapsed = 00:01:43 . Memory (MB): peak = 4688.359 ; gain = 0.000 +route_design: Time (s): cpu = 00:01:05 ; elapsed = 00:01:35 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_routed.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 4688.359 ; gain = 0.000 +write_checkpoint: Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [runtcl-4] Executing : report_drc -file pl_eth_10g_wrapper_drc_routed.rpt -pb pl_eth_10g_wrapper_drc_routed.pb -rpx pl_eth_10g_wrapper_drc_routed.rpx Command: report_drc -file pl_eth_10g_wrapper_drc_routed.rpt -pb pl_eth_10g_wrapper_drc_routed.pb -rpx pl_eth_10g_wrapper_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_routed.rpt. report_drc completed successfully -report_drc: Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 4688.359 ; gain = 0.000 +report_drc: Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [runtcl-4] Executing : report_methodology -file pl_eth_10g_wrapper_methodology_drc_routed.rpt -pb pl_eth_10g_wrapper_methodology_drc_routed.pb -rpx pl_eth_10g_wrapper_methodology_drc_routed.rpx Command: report_methodology -file pl_eth_10g_wrapper_methodology_drc_routed.rpt -pb pl_eth_10g_wrapper_methodology_drc_routed.pb -rpx pl_eth_10g_wrapper_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads INFO: [Coretcl 2-1520] The results of Report Methodology are in file E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_methodology_drc_routed.rpt. report_methodology completed successfully -report_methodology: Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 4688.359 ; gain = 0.000 +report_methodology: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [runtcl-4] Executing : report_power -file pl_eth_10g_wrapper_power_routed.rpt -pb pl_eth_10g_wrapper_power_summary_routed.pb -rpx pl_eth_10g_wrapper_power_routed.rpx Command: report_power -file pl_eth_10g_wrapper_power_routed.rpt -pb pl_eth_10g_wrapper_power_summary_routed.pb -rpx pl_eth_10g_wrapper_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. @@ -744,9 +747,9 @@ Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. -122 Infos, 3 Warnings, 1 Critical Warnings and 0 Errors encountered. +123 Infos, 3 Warnings, 1 Critical Warnings and 0 Errors encountered. report_power completed successfully -report_power: Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 4688.359 ; gain = 0.000 +report_power: Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [runtcl-4] Executing : report_route_status -file pl_eth_10g_wrapper_route_status.rpt -pb pl_eth_10g_wrapper_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file pl_eth_10g_wrapper_timing_summary_routed.rpt -pb pl_eth_10g_wrapper_timing_summary_routed.pb -rpx pl_eth_10g_wrapper_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. @@ -755,17 +758,16 @@ WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Pl INFO: [runtcl-4] Executing : report_incremental_reuse -file pl_eth_10g_wrapper_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file pl_eth_10g_wrapper_clock_utilization_routed.rpt -report_clock_utilization: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 4688.359 ; gain = 0.000 INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file pl_eth_10g_wrapper_bus_skew_routed.rpt -pb pl_eth_10g_wrapper_bus_skew_routed.pb -rpx pl_eth_10g_wrapper_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Fri Oct 20 13:01:38 2023... +INFO: [Common 17-206] Exiting Vivado at Fri Oct 20 19:48:36 2023... #----------------------------------------------------------- # Vivado v2020.2 (64-bit) # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 -# Start of session at: Fri Oct 20 13:01:57 2023 -# Process ID: 167024 +# Start of session at: Fri Oct 20 19:49:09 2023 +# Process ID: 77788 # Current directory: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1 # Command line: vivado.exe -log pl_eth_10g_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source pl_eth_10g_wrapper.tcl -notrace # Log file: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.vdi @@ -776,9 +778,9 @@ Command: open_checkpoint pl_eth_10g_wrapper_routed.dcp Starting open_checkpoint Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1126.957 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1143.684 ; gain = 0.000 INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e -Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.816 . Memory (MB): peak = 1691.883 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.753 . Memory (MB): peak = 1691.023 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 872 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 @@ -790,10 +792,10 @@ INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. -Read XDEF File: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2282.707 ; gain = 79.668 +Read XDEF File: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2278.703 ; gain = 78.188 Restored from archive | CPU: 4.000000 secs | Memory: 0.000000 MB | -Finished XDEF File Restore: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2282.707 ; gain = 79.668 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 2748.277 ; gain = 0.000 +Finished XDEF File Restore: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2278.703 ; gain = 78.188 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 2746.234 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 68 instances were transformed. RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 13 instances @@ -802,7 +804,7 @@ INFO: [Project 1-111] Unisim Transformation Summary: SRLC32E => SRL16E: 6 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2020.2 (64-bit) build 3064766 -open_checkpoint: Time (s): cpu = 00:00:26 ; elapsed = 00:00:42 . Memory (MB): peak = 2748.277 ; gain = 1621.320 +open_checkpoint: Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2746.234 ; gain = 1602.551 INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. @@ -830,7 +832,7 @@ INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'. INFO: [DRC 23-27] Running DRC with 2 threads -WARNING: [DRC RTSTAT-10] No routable loads: 111 net(s) have no routable loads. The problem bus(es) and/or net(s) are pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb... and (the first 15 of 67 listed). +WARNING: [DRC RTSTAT-10] No routable loads: 111 net(s) have no routable loads. The problem bus(es) and/or net(s) are pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb... and (the first 15 of 67 listed). INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. @@ -849,5 +851,5 @@ INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Common 17-83] Releasing license: Implementation 34 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3419.621 ; gain = 671.344 -INFO: [Common 17-206] Exiting Vivado at Fri Oct 20 13:03:35 2023... +write_bitstream: Time (s): cpu = 00:00:50 ; elapsed = 00:00:46 . Memory (MB): peak = 3409.320 ; gain = 663.086 +INFO: [Common 17-206] Exiting Vivado at Fri Oct 20 19:50:35 2023... diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_171500.backup.vdi b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_171500.backup.vdi new file mode 100644 index 0000000..b1fffc1 --- /dev/null +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_171500.backup.vdi @@ -0,0 +1,764 @@ +#----------------------------------------------------------- +# Vivado v2020.2 (64-bit) +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 +# Start of session at: Fri Oct 20 19:41:49 2023 +# Process ID: 171500 +# Current directory: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1 +# Command line: vivado.exe -log pl_eth_10g_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source pl_eth_10g_wrapper.tcl -notrace +# Log file: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.vdi +# Journal file: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source pl_eth_10g_wrapper.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'. +add_files: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1144.215 ; gain = 0.000 +Command: link_design -top pl_eth_10g_wrapper -part xczu7ev-ffvc1156-2-e +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.810 . Memory (MB): peak = 1759.492 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 876 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2020.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0.xdc] for cell 'pl_eth_10g_i/axi_dma_0/U0' +WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0.xdc:61] +Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0.xdc] for cell 'pl_eth_10g_i/axi_dma_0/U0' +Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_xxv_ethernet_0_0/ip_0/synth/pl_eth_10g_xxv_ethernet_0_0_gt.xdc] for cell 'pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst' +Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_xxv_ethernet_0_0/ip_0/synth/pl_eth_10g_xxv_ethernet_0_0_gt.xdc] for cell 'pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst' +Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_xxv_ethernet_0_0/synth/pl_eth_10g_xxv_ethernet_0_0_board.xdc] for cell 'pl_eth_10g_i/xxv_ethernet_0/inst' +Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_xxv_ethernet_0_0/synth/pl_eth_10g_xxv_ethernet_0_0_board.xdc] for cell 'pl_eth_10g_i/xxv_ethernet_0/inst' +Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_xxv_ethernet_0_0/synth/pl_eth_10g_xxv_ethernet_0_0.xdc] for cell 'pl_eth_10g_i/xxv_ethernet_0/inst' +Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_xxv_ethernet_0_0/synth/pl_eth_10g_xxv_ethernet_0_0.xdc] for cell 'pl_eth_10g_i/xxv_ethernet_0/inst' +Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_rst_ps8_0_99M_0/pl_eth_10g_rst_ps8_0_99M_0_board.xdc] for cell 'pl_eth_10g_i/zups/rst_ps8_0_99M/U0' +Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_rst_ps8_0_99M_0/pl_eth_10g_rst_ps8_0_99M_0_board.xdc] for cell 'pl_eth_10g_i/zups/rst_ps8_0_99M/U0' +Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_rst_ps8_0_99M_0/pl_eth_10g_rst_ps8_0_99M_0.xdc] for cell 'pl_eth_10g_i/zups/rst_ps8_0_99M/U0' +Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_rst_ps8_0_99M_0/pl_eth_10g_rst_ps8_0_99M_0.xdc] for cell 'pl_eth_10g_i/zups/rst_ps8_0_99M/U0' +Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/pl_eth_10g_zynq_ultra_ps_e_0_0.xdc] for cell 'pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst' +Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/pl_eth_10g_zynq_ultra_ps_e_0_0.xdc] for cell 'pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst' +Parsing XDC File [E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/constraints/constraints.xdc] +CRITICAL WARNING: [Constraints 18-1056] Clock 'gt_ref_clk' completely overrides clock 'gt_ref_clk_clk_p'. +New: create_clock -period 6.400 -name gt_ref_clk [get_ports gt_ref_clk_clk_p], [E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/constraints/constraints.xdc:27] +Previous: create_clock -period 6.400 [get_ports gt_ref_clk_clk_p], [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_xxv_ethernet_0_0/synth/pl_eth_10g_xxv_ethernet_0_0.xdc:65] +Resolution: Review the constraint files and remove the redundant clock definition(s). If the clock constraints are not saved in a file, you can first save the constraints to an XDC file and reload the design once the constraints have been corrected. +Finished Parsing XDC File [E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/constraints/constraints.xdc] +Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0_clocks.xdc] for cell 'pl_eth_10g_i/axi_dma_0/U0' +Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_axi_dma_0_0/pl_eth_10g_axi_dma_0_0_clocks.xdc] for cell 'pl_eth_10g_i/axi_dma_0/U0' +Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst' +Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_0/pl_eth_10g_auto_us_0_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst' +Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst' +Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_1/pl_eth_10g_auto_us_1_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst' +Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_clocks.xdc:16] +INFO: [Timing 38-2] Deriving generated clocks [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_clocks.xdc:16] +all_fanout: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2295.293 ; gain = 328.082 +Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst' +Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst' +Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst' +Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst' +Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst' +Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0_clocks.xdc] for cell 'pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst' +Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_0/pl_eth_10g_auto_ds_0_clocks.xdc] for cell 'pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst' +Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1_clocks.xdc] for cell 'pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst' +Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_ds_1/pl_eth_10g_auto_ds_1_clocks.xdc] for cell 'pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst' +INFO: [Project 1-1715] 7 XPM XDC files have been applied to the design. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-1687] 18 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2297.664 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 62 instances were transformed. + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 13 instances + RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 47 instances + RAM64X1S => RAM64X1S (RAMS64E): 2 instances + +14 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:31 . Memory (MB): peak = 2297.664 ; gain = 1153.449 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2297.664 ; gain = 0.000 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 138337785 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2297.664 ; gain = 0.000 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 41 inverter(s) to 2274 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 12f7198c8 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2482.816 ; gain = 2.074 +INFO: [Opt 31-389] Phase Retarget created 9 cells and removed 433 cells +INFO: [Opt 31-1021] In phase Retarget, 143 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 13a3a3d4f + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2482.816 ; gain = 2.074 +INFO: [Opt 31-389] Phase Constant propagation created 490 cells and removed 1256 cells +INFO: [Opt 31-1021] In phase Constant propagation, 142 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 17dc2c8da + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2482.816 ; gain = 2.074 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1051 cells +INFO: [Opt 31-1021] In phase Sweep, 407 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 4 BUFG optimization +INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT. +Phase 4 BUFG optimization | Checksum: 17dc2c8da + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2482.816 ; gain = 2.074 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 17dc2c8da + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2482.816 ; gain = 2.074 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 17dc2c8da + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2482.816 ; gain = 2.074 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +INFO: [Opt 31-1021] In phase Post Processing Netlist, 175 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 9 | 433 | 143 | +| Constant propagation | 490 | 1256 | 142 | +| Sweep | 0 | 1051 | 407 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 175 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.109 . Memory (MB): peak = 2482.816 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 2040f7235 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2482.816 ; gain = 2.074 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +INFO: [Pwropt 34-9] Applying IDT optimizations ... +INFO: [Pwropt 34-10] Applying ODC optimizations ... +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation + + +Starting PowerOpt Patch Enables Task +INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 139 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Pwropt 34-201] Structural ODC has moved 133 WE to EN ports +Number of BRAM Ports augmented: 5 newly gated: 133 Total Ports: 278 +Ending PowerOpt Patch Enables Task | Checksum: 2397c5aae + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Ending Power Optimization Task | Checksum: 2397c5aae + +Time (s): cpu = 00:00:50 ; elapsed = 00:00:47 . Memory (MB): peak = 4670.074 ; gain = 2187.258 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 2397c5aae + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 1e978e3e4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +42 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:01:04 ; elapsed = 00:01:01 . Memory (MB): peak = 4670.074 ; gain = 2372.410 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.064 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_opt.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_drc -file pl_eth_10g_wrapper_drc_opted.rpt -pb pl_eth_10g_wrapper_drc_opted.pb -rpx pl_eth_10g_wrapper_drc_opted.rpx +Command: report_drc -file pl_eth_10g_wrapper_drc_opted.rpt -pb pl_eth_10g_wrapper_drc_opted.pb -rpx pl_eth_10g_wrapper_drc_opted.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_opted.rpt. +report_drc completed successfully +report_drc: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' +WARNING: [Vivado_Tcl 4-1400] -ultrathreads option currently only supported on multi-SLR devices. Continuing placement in regular mode. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14ac46bc1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a4892a73 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: a636ca79 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: a636ca79 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: a636ca79 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning + +Phase 2.1.1 Partition Driven Placement + +Phase 2.1.1.1 PBP: Partition Driven Placement +Phase 2.1.1.1 PBP: Partition Driven Placement | Checksum: be748173 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 2.1.1.2 PBP: Clock Region Placement +Phase 2.1.1.2 PBP: Clock Region Placement | Checksum: a4c8b2cf + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 2.1.1.3 PBP: Discrete Incremental +Phase 2.1.1.3 PBP: Discrete Incremental | Checksum: 19273f8f0 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 2.1.1.4 PBP: Compute Congestion +Phase 2.1.1.4 PBP: Compute Congestion | Checksum: 19273f8f0 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 2.1.1.5 PBP: Macro Placement +Phase 2.1.1.5 PBP: Macro Placement | Checksum: a17d3753 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 2.1.1.6 PBP: UpdateTiming +Phase 2.1.1.6 PBP: UpdateTiming | Checksum: af3a95f3 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 2.1.1.7 PBP: Add part constraints +Phase 2.1.1.7 PBP: Add part constraints | Checksum: af3a95f3 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 2.1.1 Partition Driven Placement | Checksum: af3a95f3 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 2.1 Floorplanning | Checksum: af3a95f3 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: af3a95f3 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 2.3 Global Placement Core + +Phase 2.3.1 Physical Synthesis In Placer +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 927 LUT instances to create LUTNM shape +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 +INFO: [Physopt 32-775] End 1 Pass. Optimized 367 nets or cells. Created 0 new cell, deleted 367 existing cells and moved 0 existing cell +INFO: [Physopt 32-1030] Pass 1. Identified 31 candidate driver sets for equivalent driver rewiring. +INFO: [Physopt 32-661] Optimized 24 nets. Re-placed 265 instances. +INFO: [Physopt 32-775] End 1 Pass. Optimized 24 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 265 existing cells +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.154 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. +INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| LUT Combining | 0 | 367 | 367 | 0 | 1 | 00:00:01 | +| Equivalent Driver Rewiring | 0 | 0 | 24 | 0 | 1 | 00:00:03 | +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 367 | 391 | 0 | 4 | 00:00:04 | +----------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.3.1 Physical Synthesis In Placer | Checksum: 139138c10 + +Time (s): cpu = 00:01:03 ; elapsed = 00:01:14 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 2.3 Global Placement Core | Checksum: 167c195fa + +Time (s): cpu = 00:01:07 ; elapsed = 00:01:18 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 167c195fa + +Time (s): cpu = 00:01:07 ; elapsed = 00:01:18 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1599f8778 + +Time (s): cpu = 00:01:09 ; elapsed = 00:01:21 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 132be9d92 + +Time (s): cpu = 00:01:12 ; elapsed = 00:01:23 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 3.3 Small Shape DP + +Phase 3.3.1 Small Shape Clustering +Phase 3.3.1 Small Shape Clustering | Checksum: a1b5ebd2 + +Time (s): cpu = 00:01:17 ; elapsed = 00:01:28 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 3.3.2 Flow Legalize Slice Clusters +Phase 3.3.2 Flow Legalize Slice Clusters | Checksum: 66bdfa70 + +Time (s): cpu = 00:01:17 ; elapsed = 00:01:28 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 3.3.3 Slice Area Swap +Phase 3.3.3 Slice Area Swap | Checksum: b4a03078 + +Time (s): cpu = 00:01:18 ; elapsed = 00:01:31 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 3.3 Small Shape DP | Checksum: f3e77f5a + +Time (s): cpu = 00:01:27 ; elapsed = 00:01:37 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 3.4 Re-assign LUT pins +Phase 3.4 Re-assign LUT pins | Checksum: 1ccb856d8 + +Time (s): cpu = 00:01:29 ; elapsed = 00:01:41 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 3.5 Pipeline Register Optimization +Phase 3.5 Pipeline Register Optimization | Checksum: 1646d4a6a + +Time (s): cpu = 00:01:30 ; elapsed = 00:01:42 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 1646d4a6a + +Time (s): cpu = 00:01:30 ; elapsed = 00:01:42 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 21ad82e5a + +Phase 4.1.1.1 BUFG Insertion + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.637 | TNS=0.000 | +Phase 1 Physical Synthesis Initialization | Checksum: 1947f44a7 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Place 46-35] Processed net pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0], inserted BUFG to drive 1680 loads. +INFO: [Place 46-35] Processed net pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out, inserted BUFG to drive 1159 loads. +INFO: [Place 46-45] Replicated bufg driver pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out_reg_replica +INFO: [Place 46-35] Processed net pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0], inserted BUFG to drive 1152 loads. +INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 3, Replicated BUFG Driver: 1, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. +Ending Physical Synthesis Task | Checksum: 161227327 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 4.1.1.1 BUFG Insertion | Checksum: 1b3d14eea + +Time (s): cpu = 00:01:42 ; elapsed = 00:01:56 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Place 30-746] Post Placement Timing Summary WNS=1.637. For the most accurate timing information please run report_timing. + +Time (s): cpu = 00:01:42 ; elapsed = 00:01:56 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 4.1 Post Commit Optimization | Checksum: 18af3dba2 + +Time (s): cpu = 00:01:42 ; elapsed = 00:01:57 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1fb723624 + +Time (s): cpu = 00:01:46 ; elapsed = 00:02:00 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ________________________________________________________________________ +| | Global Congestion | Long Congestion | Short Congestion | +| Direction | Region Size | Region Size | Region Size | +|___________|___________________|___________________|___________________| +| North| 1x1| 1x1| 2x2| +|___________|___________________|___________________|___________________| +| South| 1x1| 16x16| 2x2| +|___________|___________________|___________________|___________________| +| East| 1x1| 1x1| 8x8| +|___________|___________________|___________________|___________________| +| West| 1x1| 1x1| 4x4| +|___________|___________________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 1fb723624 + +Time (s): cpu = 00:01:46 ; elapsed = 00:02:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 4.3 Placer Reporting | Checksum: 1fb723624 + +Time (s): cpu = 00:01:46 ; elapsed = 00:02:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Time (s): cpu = 00:01:46 ; elapsed = 00:02:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 269a85b9d + +Time (s): cpu = 00:01:47 ; elapsed = 00:02:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Ending Placer Task | Checksum: 1e2aa1291 + +Time (s): cpu = 00:01:47 ; elapsed = 00:02:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +84 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:01:50 ; elapsed = 00:02:04 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_placed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_io -file pl_eth_10g_wrapper_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.080 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file pl_eth_10g_wrapper_utilization_placed.rpt -pb pl_eth_10g_wrapper_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file pl_eth_10g_wrapper_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.127 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' +INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. +INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +93 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +phys_opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_physopt.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: ba17791b ConstDB: 0 ShapeSum: b8143ef4 RouteDB: 707e5a82 + +Phase 1 Build RT Design +Nodegraph reading from file. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 1 Build RT Design | Checksum: 1ccd8f4d8 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Post Restoration Checksum: NetGraph: eaea5d6 NumContArr: 4d575875 Constraints: c401714a Timing: 0 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +Phase 2.1 Create Timer | Checksum: 120076f95 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 2.2 Fix Topology Constraints +Phase 2.2 Fix Topology Constraints | Checksum: 120076f95 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 2.3 Pre Route Cleanup +Phase 2.3 Pre Route Cleanup | Checksum: 120076f95 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 2.4 Global Clock Net Routing + Number of Nodes with overlaps = 0 +Phase 2.4 Global Clock Net Routing | Checksum: 12fb7e7e6 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 2.5 Update Timing +Phase 2.5 Update Timing | Checksum: 265dc8b5b + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.822 | TNS=0.000 | WHS=-0.190 | THS=-26.919| + + +Phase 2.6 Update Timing for Bus Skew + +Phase 2.6.1 Update Timing +Phase 2.6.1 Update Timing | Checksum: 27464ca79 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.822 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 2.6 Update Timing for Bus Skew | Checksum: 24be47c62 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 2 Router Initialization | Checksum: 227779a70 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Router Utilization Summary + Global Vertical Routing Utilization = 5.04182e-05 % + Global Horizontal Routing Utilization = 0.000129803 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 46965 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 40223 + Number of Partially Routed Nets = 6742 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing + +Phase 3.1 Global Routing +Phase 3.1 Global Routing | Checksum: 227779a70 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:33 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 3 Initial Routing | Checksum: 1d65e8aff + +Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 5873 + Number of Nodes with overlaps = 350 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.870 | TNS=0.000 | WHS=-0.040 | THS=-0.082 | + +Phase 4.1 Global Iteration 0 | Checksum: 13fe249c9 + +Time (s): cpu = 00:00:45 ; elapsed = 00:01:11 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 4.2 Global Iteration 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.870 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.2 Global Iteration 1 | Checksum: 1ca0d0fbb + +Time (s): cpu = 00:00:48 ; elapsed = 00:01:15 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 4 Rip-up And Reroute | Checksum: 1ca0d0fbb + +Time (s): cpu = 00:00:48 ; elapsed = 00:01:15 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 5 Delay and Skew Optimization + +Phase 5.1 Delay CleanUp + +Phase 5.1.1 Update Timing +Phase 5.1.1 Update Timing | Checksum: 1b62e6b82 + +Time (s): cpu = 00:00:52 ; elapsed = 00:01:20 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.870 | TNS=0.000 | WHS=0.010 | THS=0.000 | + +Phase 5.1 Delay CleanUp | Checksum: 22b577808 + +Time (s): cpu = 00:00:52 ; elapsed = 00:01:20 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 5.2 Clock Skew Optimization +Phase 5.2 Clock Skew Optimization | Checksum: 22b577808 + +Time (s): cpu = 00:00:52 ; elapsed = 00:01:21 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 5 Delay and Skew Optimization | Checksum: 22b577808 + +Time (s): cpu = 00:00:52 ; elapsed = 00:01:21 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 1805b0dba + +Time (s): cpu = 00:00:55 ; elapsed = 00:01:24 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.870 | TNS=0.000 | WHS=0.010 | THS=0.000 | + +Phase 6.1 Hold Fix Iter | Checksum: 16069ca04 + +Time (s): cpu = 00:00:56 ; elapsed = 00:01:25 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 6 Post Hold Fix | Checksum: 16069ca04 + +Time (s): cpu = 00:00:56 ; elapsed = 00:01:25 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 3.18683 % + Global Horizontal Routing Utilization = 2.82098 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 7 Route finalize | Checksum: 1cf9de95a + +Time (s): cpu = 00:00:57 ; elapsed = 00:01:25 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 1cf9de95a + +Time (s): cpu = 00:00:57 ; elapsed = 00:01:26 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 9 Depositing Routes +INFO: [Route 35-467] Router swapped GT pin pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_common_wrapper/pl_eth_10g_xxv_ethernet_0_0_gt_gthe4_common_wrapper_i/common_inst/gthe4_common_gen.GTHE4_COMMON_PRIM_INST/GTREFCLK00 to physical pin GTHE4_COMMON_X0Y2/COM0_REFCLKOUT5 +Phase 9 Depositing Routes | Checksum: 1cf9de95a + +Time (s): cpu = 00:00:59 ; elapsed = 00:01:30 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 10 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=0.870 | TNS=0.000 | WHS=0.010 | THS=0.000 | + +INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. +Phase 10 Post Router Timing | Checksum: 1cf9de95a + +Time (s): cpu = 00:00:59 ; elapsed = 00:01:30 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:59 ; elapsed = 00:01:30 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +111 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:01:05 ; elapsed = 00:01:35 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_routed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_drc -file pl_eth_10g_wrapper_drc_routed.rpt -pb pl_eth_10g_wrapper_drc_routed.pb -rpx pl_eth_10g_wrapper_drc_routed.rpx +Command: report_drc -file pl_eth_10g_wrapper_drc_routed.rpt -pb pl_eth_10g_wrapper_drc_routed.pb -rpx pl_eth_10g_wrapper_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_routed.rpt. +report_drc completed successfully +report_drc: Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_methodology -file pl_eth_10g_wrapper_methodology_drc_routed.rpt -pb pl_eth_10g_wrapper_methodology_drc_routed.pb -rpx pl_eth_10g_wrapper_methodology_drc_routed.rpx +Command: report_methodology -file pl_eth_10g_wrapper_methodology_drc_routed.rpt -pb pl_eth_10g_wrapper_methodology_drc_routed.pb -rpx pl_eth_10g_wrapper_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_methodology_drc_routed.rpt. +report_methodology completed successfully +report_methodology: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_power -file pl_eth_10g_wrapper_power_routed.rpt -pb pl_eth_10g_wrapper_power_summary_routed.pb -rpx pl_eth_10g_wrapper_power_routed.rpx +Command: report_power -file pl_eth_10g_wrapper_power_routed.rpt -pb pl_eth_10g_wrapper_power_summary_routed.pb -rpx pl_eth_10g_wrapper_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. +Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. +123 Infos, 3 Warnings, 1 Critical Warnings and 0 Errors encountered. +report_power completed successfully +report_power: Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_route_status -file pl_eth_10g_wrapper_route_status.rpt -pb pl_eth_10g_wrapper_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file pl_eth_10g_wrapper_timing_summary_routed.rpt -pb pl_eth_10g_wrapper_timing_summary_routed.pb -rpx pl_eth_10g_wrapper_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +INFO: [runtcl-4] Executing : report_incremental_reuse -file pl_eth_10g_wrapper_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file pl_eth_10g_wrapper_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file pl_eth_10g_wrapper_bus_skew_routed.rpt -pb pl_eth_10g_wrapper_bus_skew_routed.pb -rpx pl_eth_10g_wrapper_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Fri Oct 20 19:48:36 2023... diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_bus_skew_routed.pb b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_bus_skew_routed.pb index 2fb8ad5..c65bf03 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_bus_skew_routed.pb +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_bus_skew_routed.pb @@ -1,2 +1,2 @@ -2018.1’Bus skew results˜¥sŒ¤@ \ No newline at end of file +2018.1’Bus skew results˜¥yð§@ \ No newline at end of file diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_bus_skew_routed.rpt b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_bus_skew_routed.rpt index 6387fb1..d670e86 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_bus_skew_routed.rpt +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_bus_skew_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -| Date : Fri Oct 20 13:01:38 2023 +| Date : Fri Oct 20 19:48:36 2023 | Host : DESKTOP-5FH9OH3 running 64-bit major release (build 9200) | Command : report_bus_skew -warn_on_violation -file pl_eth_10g_wrapper_bus_skew_routed.rpt -pb pl_eth_10g_wrapper_bus_skew_routed.pb -rpx pl_eth_10g_wrapper_bus_skew_routed.rpx | Design : pl_eth_10g_wrapper @@ -24,58 +24,58 @@ Id Position From To Co -- -------- ------------------------------ ------------------------------ ------ --------------- ---------- --------- 1 55 [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 0.466 5.934 + Slow 6.400 0.593 5.807 2 57 [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 0.628 5.772 + Slow 6.400 0.527 5.873 3 59 [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 0.439 5.961 + Slow 6.400 0.571 5.829 4 61 [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 0.581 5.819 + Slow 6.400 0.680 5.720 5 63 [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 0.519 5.881 + Slow 6.400 0.683 5.717 6 65 [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 0.565 5.835 + Slow 6.400 0.466 5.934 7 67 [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 0.509 5.891 + Slow 6.400 0.593 5.807 8 69 [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 0.625 5.775 + Slow 6.400 0.667 5.733 9 87 [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 0.936 5.464 + Slow 6.400 0.574 5.826 10 89 [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 0.847 5.553 + Slow 6.400 0.462 5.938 11 91 [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 0.455 5.945 + Slow 6.400 1.152 5.248 12 93 [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 0.553 5.847 + Slow 6.400 0.411 5.989 13 95 [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 0.528 5.872 + Slow 6.400 0.802 5.598 14 97 [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 1.078 5.322 + Slow 6.400 0.454 5.946 15 99 [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 1.258 5.142 + Slow 6.400 1.126 5.274 16 101 [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 0.710 5.690 + Slow 6.400 0.555 5.845 17 103 [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 0.535 5.865 + Slow 6.400 0.674 5.726 18 105 [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] [get_cells [list {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] - Slow 6.400 1.125 5.275 + Slow 6.400 0.544 5.856 2. Bus Skew Report Per Constraint @@ -89,27 +89,27 @@ Endpoints: 4 From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- xxv_ethernet_0_tx_clk_out_0 - clk_pl_0 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D - Slow 0.466 5.934 + clk_pl_0 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.593 5.807 -Slack (MET) : 5.934ns (requirement - actual skew) - Endpoint Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C +Slack (MET) : 5.807ns (requirement - actual skew) + Endpoint Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0) - Endpoint Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Endpoint Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) - Reference Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + Reference Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0) - Reference Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Reference Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 0.678ns - Reference Relative Delay: -0.104ns - Relative CRPR: 0.439ns + Endpoint Relative Delay: 0.729ns + Reference Relative Delay: -0.081ns + Relative CRPR: 0.339ns Uncertainty: 0.122ns - Actual Bus Skew: 0.466ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.593ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -120,13 +120,13 @@ Endpoint path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.876 2.119 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk - SLICE_X54Y57 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.863 2.106 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk + SLICE_X54Y57 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X54Y57 FDRE (Prop_CFF_SLICEM_C_Q) - 0.078 2.197 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.307 2.504 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2] - SLICE_X55Y57 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + SLICE_X54Y57 FDRE (Prop_EFF_SLICEM_C_Q) + 0.076 2.182 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.381 2.563 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3] + SLICE_X54Y57 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -135,16 +135,16 @@ Endpoint path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.633 1.801 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk - SLICE_X55Y57 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C - clock pessimism 0.000 1.801 - SLICE_X55Y57 FDRE (Setup_DFF2_SLICEL_C_D) - 0.025 1.826 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.641 1.809 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk + SLICE_X54Y57 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism 0.000 1.809 + SLICE_X54Y57 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 1.834 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- - data arrival 2.504 - clock arrival 1.826 + data arrival 2.563 + clock arrival 1.834 ------------------------------------------------------------------- - relative delay 0.678 + relative delay 0.729 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -155,13 +155,13 @@ Reference path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.649 1.862 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk - SLICE_X54Y56 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.652 1.865 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk + SLICE_X53Y57 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X54Y56 FDRE (Prop_EFF_SLICEM_C_Q) - 0.058 1.920 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.114 2.034 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3] - SLICE_X54Y56 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X53Y57 FDRE (Prop_DFF_SLICEM_C_Q) + 0.058 1.923 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.110 2.033 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2] + SLICE_X53Y55 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -170,16 +170,16 @@ Reference path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.869 2.077 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk - SLICE_X54Y56 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C - clock pessimism 0.000 2.077 - SLICE_X54Y56 FDRE (Hold_DFF2_SLICEM_C_D) - 0.061 2.138 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.844 2.052 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk + SLICE_X53Y55 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.000 2.052 + SLICE_X53Y55 FDRE (Hold_HFF2_SLICEM_C_D) + 0.062 2.114 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - data arrival 2.034 - clock arrival 2.138 + data arrival 2.033 + clock arrival 2.114 ------------------------------------------------------------------- - relative delay -0.104 + relative delay -0.081 @@ -190,27 +190,27 @@ Endpoints: 4 From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- -clk_pl_0 Net pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D - Slow 0.628 5.772 +clk_pl_0 Net pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.527 5.873 -Slack (MET) : 5.772ns (requirement - actual skew) - Endpoint Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C +Slack (MET) : 5.873ns (requirement - actual skew) + Endpoint Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) - Endpoint Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Endpoint Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D (rising edge-triggered cell FDRE clocked by Net) - Reference Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + Reference Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) - Reference Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Reference Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by Net) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 0.677ns - Reference Relative Delay: -0.147ns - Relative CRPR: 0.318ns + Endpoint Relative Delay: 0.618ns + Reference Relative Delay: -0.180ns + Relative CRPR: 0.394ns Uncertainty: 0.122ns - Actual Bus Skew: 0.628ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.527ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -221,13 +221,13 @@ Endpoint path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.859 2.067 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk - SLICE_X57Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.844 2.052 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk + SLICE_X54Y67 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X57Y68 FDRE (Prop_HFF2_SLICEM_C_Q) - 0.078 2.145 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.358 2.503 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1] - SLICE_X58Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + SLICE_X54Y67 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 2.131 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.323 2.454 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0] + SLICE_X56Y67 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -235,16 +235,16 @@ Endpoint path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.588 1.801 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk - SLICE_X58Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C - clock pessimism 0.000 1.801 - SLICE_X58Y68 FDRE (Setup_HFF2_SLICEL_C_D) - 0.025 1.826 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.598 1.811 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk + SLICE_X56Y67 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.000 1.811 + SLICE_X56Y67 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 1.836 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- - data arrival 2.503 - clock arrival 1.826 + data arrival 2.454 + clock arrival 1.836 ------------------------------------------------------------------- - relative delay 0.677 + relative delay 0.618 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -255,13 +255,13 @@ Reference path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.629 1.797 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk - SLICE_X59Y69 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.627 1.795 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk + SLICE_X54Y67 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X59Y69 FDRE (Prop_EFF_SLICEL_C_Q) - 0.059 1.856 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.094 1.950 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3] - SLICE_X59Y69 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X54Y67 FDRE (Prop_GFF_SLICEM_C_Q) + 0.058 1.853 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.071 1.924 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2] + SLICE_X55Y67 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -269,16 +269,16 @@ Reference path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.792 2.035 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk - SLICE_X59Y69 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C - clock pessimism 0.000 2.035 - SLICE_X59Y69 FDRE (Hold_DFF2_SLICEL_C_D) - 0.062 2.097 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.799 2.042 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk + SLICE_X55Y67 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.000 2.042 + SLICE_X55Y67 FDRE (Hold_DFF2_SLICEL_C_D) + 0.062 2.104 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - data arrival 1.950 - clock arrival 2.097 + data arrival 1.924 + clock arrival 2.104 ------------------------------------------------------------------- - relative delay -0.147 + relative delay -0.180 @@ -291,10 +291,10 @@ From Clock To Clock Endpoint Pin Refe -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- Net clk_pl_0 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - Slow 0.439 5.961 + Slow 0.571 5.829 -Slack (MET) : 5.961ns (requirement - actual skew) +Slack (MET) : 5.829ns (requirement - actual skew) Endpoint Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by Net) Endpoint Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D @@ -305,11 +305,11 @@ Slack (MET) : 5.961ns (requirement - actual skew) (rising edge-triggered cell FDRE clocked by clk_pl_0) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 0.611ns - Reference Relative Delay: -0.159ns - Relative CRPR: 0.453ns + Endpoint Relative Delay: 0.725ns + Reference Relative Delay: -0.118ns + Relative CRPR: 0.394ns Uncertainty: 0.122ns - Actual Bus Skew: 0.439ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.571ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -319,13 +319,13 @@ Endpoint path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.803 2.046 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk - SLICE_X59Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.793 2.036 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk + SLICE_X56Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X59Y68 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 2.125 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.303 2.428 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0] - SLICE_X60Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + SLICE_X56Y68 FDRE (Prop_DFF_SLICEM_C_Q) + 0.078 2.114 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.439 2.553 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0] + SLICE_X57Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -334,16 +334,16 @@ Endpoint path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.624 1.792 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk - SLICE_X60Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C - clock pessimism 0.000 1.792 - SLICE_X60Y68 FDRE (Setup_HFF2_SLICEL_C_D) - 0.025 1.817 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.635 1.803 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk + SLICE_X57Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.000 1.803 + SLICE_X57Y68 FDRE (Setup_HFF2_SLICEM_C_D) + 0.025 1.828 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- - data arrival 2.428 - clock arrival 1.817 + data arrival 2.553 + clock arrival 1.828 ------------------------------------------------------------------- - relative delay 0.611 + relative delay 0.725 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -353,13 +353,13 @@ Reference path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.593 1.806 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk - SLICE_X59Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.592 1.805 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk + SLICE_X56Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X59Y68 FDRE (Prop_DFF2_SLICEL_C_Q) - 0.061 1.867 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.100 1.967 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1] - SLICE_X60Y70 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + SLICE_X56Y68 FDRE (Prop_DFF2_SLICEM_C_Q) + 0.061 1.866 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.118 1.984 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1] + SLICE_X56Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -368,16 +368,16 @@ Reference path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.856 2.064 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk - SLICE_X60Y70 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C - clock pessimism 0.000 2.064 - SLICE_X60Y70 FDRE (Hold_HFF2_SLICEL_C_D) - 0.062 2.126 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.832 2.040 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk + SLICE_X56Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.000 2.040 + SLICE_X56Y68 FDRE (Hold_HFF2_SLICEM_C_D) + 0.062 2.102 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] ------------------------------------------------------------------- - data arrival 1.967 - clock arrival 2.126 + data arrival 1.984 + clock arrival 2.102 ------------------------------------------------------------------- - relative delay -0.159 + relative delay -0.118 @@ -389,27 +389,27 @@ Endpoints: 4 From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- xxv_ethernet_0_tx_clk_out_0 - clk_pl_0 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D - Slow 0.581 5.819 + clk_pl_0 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Slow 0.680 5.720 -Slack (MET) : 5.819ns (requirement - actual skew) - Endpoint Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C +Slack (MET) : 5.720ns (requirement - actual skew) + Endpoint Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0) - Endpoint Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Endpoint Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) - Reference Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + Reference Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0) - Reference Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Reference Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 0.750ns - Reference Relative Delay: -0.048ns + Endpoint Relative Delay: 0.773ns + Reference Relative Delay: -0.124ns Relative CRPR: 0.339ns Uncertainty: 0.122ns - Actual Bus Skew: 0.581ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.680ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -420,13 +420,13 @@ Endpoint path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.871 2.114 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk - SLICE_X49Y51 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.862 2.105 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk + SLICE_X53Y47 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X49Y51 FDRE (Prop_DFF2_SLICEM_C_Q) - 0.080 2.194 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.382 2.576 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1] - SLICE_X52Y52 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + SLICE_X53Y47 FDRE (Prop_HFF2_SLICEM_C_Q) + 0.078 2.183 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.411 2.594 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3] + SLICE_X53Y47 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -435,16 +435,16 @@ Endpoint path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.633 1.801 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk - SLICE_X52Y52 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C - clock pessimism 0.000 1.801 - SLICE_X52Y52 FDRE (Setup_DFF2_SLICEL_C_D) - 0.025 1.826 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.628 1.796 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk + SLICE_X53Y47 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism 0.000 1.796 + SLICE_X53Y47 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 1.821 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- - data arrival 2.576 - clock arrival 1.826 + data arrival 2.594 + clock arrival 1.821 ------------------------------------------------------------------- - relative delay 0.750 + relative delay 0.773 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -455,13 +455,13 @@ Reference path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.649 1.862 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk - SLICE_X53Y49 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.654 1.867 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk + SLICE_X52Y49 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X53Y49 FDRE (Prop_EFF_SLICEM_C_Q) - 0.058 1.920 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.146 2.066 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3] - SLICE_X53Y49 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X52Y49 FDRE (Prop_HFF2_SLICEL_C_Q) + 0.059 1.926 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.070 1.996 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1] + SLICE_X52Y50 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -470,16 +470,16 @@ Reference path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.844 2.052 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk - SLICE_X53Y49 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C - clock pessimism 0.000 2.052 - SLICE_X53Y49 FDRE (Hold_CFF2_SLICEM_C_D) - 0.062 2.114 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.850 2.058 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk + SLICE_X52Y50 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.000 2.058 + SLICE_X52Y50 FDRE (Hold_DFF2_SLICEL_C_D) + 0.062 2.120 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] ------------------------------------------------------------------- - data arrival 2.066 - clock arrival 2.114 + data arrival 1.996 + clock arrival 2.120 ------------------------------------------------------------------- - relative delay -0.048 + relative delay -0.124 @@ -491,27 +491,27 @@ Endpoints: 4 From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- clk_pl_0 xxv_ethernet_0_tx_clk_out_0 - pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D - Slow 0.519 5.881 + pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.683 5.717 -Slack (MET) : 5.881ns (requirement - actual skew) - Endpoint Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C +Slack (MET) : 5.717ns (requirement - actual skew) + Endpoint Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) - Endpoint Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Endpoint Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0) - Reference Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + Reference Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) - Reference Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Reference Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 0.535ns - Reference Relative Delay: -0.201ns - Relative CRPR: 0.339ns + Endpoint Relative Delay: 0.756ns + Reference Relative Delay: -0.191ns + Relative CRPR: 0.387ns Uncertainty: 0.122ns - Actual Bus Skew: 0.519ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.683ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -522,13 +522,13 @@ Endpoint path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.838 2.046 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk - SLICE_X52Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.844 2.052 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk + SLICE_X53Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X52Y48 FDRE (Prop_DFF2_SLICEL_C_Q) - 0.081 2.127 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.303 2.430 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1] - SLICE_X52Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + SLICE_X53Y48 FDRE (Prop_DFF_SLICEM_C_Q) + 0.078 2.130 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.515 2.645 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0] + SLICE_X54Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -537,16 +537,16 @@ Endpoint path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.657 1.870 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk - SLICE_X52Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C - clock pessimism 0.000 1.870 - SLICE_X52Y48 FDRE (Setup_HFF2_SLICEL_C_D) - 0.025 1.895 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.651 1.864 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk + SLICE_X54Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.000 1.864 + SLICE_X54Y48 FDRE (Setup_HFF2_SLICEM_C_D) + 0.025 1.889 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- - data arrival 2.430 - clock arrival 1.895 + data arrival 2.645 + clock arrival 1.889 ------------------------------------------------------------------- - relative delay 0.535 + relative delay 0.756 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -557,13 +557,13 @@ Reference path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.628 1.796 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk - SLICE_X53Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.630 1.798 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk + SLICE_X53Y49 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X53Y48 FDRE (Prop_EFF_SLICEM_C_Q) - 0.058 1.854 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.114 1.968 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3] - SLICE_X53Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X53Y49 FDRE (Prop_DFF2_SLICEM_C_Q) + 0.061 1.859 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.118 1.977 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2] + SLICE_X53Y49 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -572,16 +572,16 @@ Reference path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.865 2.108 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk - SLICE_X53Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C - clock pessimism 0.000 2.108 - SLICE_X53Y48 FDRE (Hold_DFF2_SLICEM_C_D) - 0.061 2.169 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.863 2.106 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk + SLICE_X53Y49 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.000 2.106 + SLICE_X53Y49 FDRE (Hold_HFF2_SLICEM_C_D) + 0.062 2.168 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - data arrival 1.968 - clock arrival 2.169 + data arrival 1.977 + clock arrival 2.168 ------------------------------------------------------------------- - relative delay -0.201 + relative delay -0.191 @@ -593,27 +593,27 @@ Endpoints: 4 From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- clk_pl_0 xxv_ethernet_0_tx_clk_out_0 - pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D - pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - Slow 0.565 5.835 + pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 0.466 5.934 -Slack (MET) : 5.835ns (requirement - actual skew) - Endpoint Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C +Slack (MET) : 5.934ns (requirement - actual skew) + Endpoint Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) - Endpoint Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Endpoint Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0) - Reference Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + Reference Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) - Reference Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Reference Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 0.629ns - Reference Relative Delay: -0.153ns - Relative CRPR: 0.339ns + Endpoint Relative Delay: 0.540ns + Reference Relative Delay: -0.244ns + Relative CRPR: 0.440ns Uncertainty: 0.122ns - Actual Bus Skew: 0.565ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.466ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -624,13 +624,13 @@ Endpoint path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.844 2.052 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk - SLICE_X53Y53 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.845 2.053 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk + SLICE_X53Y57 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X53Y53 FDRE (Prop_EFF_SLICEM_C_Q) - 0.076 2.128 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.390 2.518 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3] - SLICE_X53Y53 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X53Y57 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 2.132 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.298 2.430 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2] + SLICE_X53Y57 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -639,16 +639,16 @@ Endpoint path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.651 1.864 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk - SLICE_X53Y53 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C - clock pessimism 0.000 1.864 - SLICE_X53Y53 FDRE (Setup_DFF2_SLICEM_C_D) - 0.025 1.889 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.652 1.865 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk + SLICE_X53Y57 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.000 1.865 + SLICE_X53Y57 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 1.890 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - data arrival 2.518 - clock arrival 1.889 + data arrival 2.430 + clock arrival 1.890 ------------------------------------------------------------------- - relative delay 0.629 + relative delay 0.540 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -659,13 +659,13 @@ Reference path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.634 1.802 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk - SLICE_X52Y56 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.631 1.799 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk + SLICE_X53Y55 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X52Y56 FDRE (Prop_CFF_SLICEL_C_Q) - 0.058 1.860 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.155 2.015 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2] - SLICE_X54Y56 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + SLICE_X53Y55 FDRE (Prop_EFF_SLICEM_C_Q) + 0.058 1.857 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.080 1.937 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3] + SLICE_X53Y54 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -674,16 +674,16 @@ Reference path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.863 2.106 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk - SLICE_X54Y56 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C - clock pessimism 0.000 2.106 - SLICE_X54Y56 FDRE (Hold_HFF2_SLICEM_C_D) - 0.062 2.168 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.876 2.119 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk + SLICE_X53Y54 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism 0.000 2.119 + SLICE_X53Y54 FDRE (Hold_HFF2_SLICEM_C_D) + 0.062 2.181 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- - data arrival 2.015 - clock arrival 2.168 + data arrival 1.937 + clock arrival 2.181 ------------------------------------------------------------------- - relative delay -0.153 + relative delay -0.244 @@ -694,27 +694,27 @@ Endpoints: 4 From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- -Net clk_pl_0 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D - Slow 0.509 5.891 +Net clk_pl_0 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.593 5.807 -Slack (MET) : 5.891ns (requirement - actual skew) - Endpoint Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C +Slack (MET) : 5.807ns (requirement - actual skew) + Endpoint Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C (rising edge-triggered cell FDRE clocked by Net) - Endpoint Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Endpoint Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) - Reference Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + Reference Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by Net) - Reference Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Reference Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 0.691ns - Reference Relative Delay: -0.094ns - Relative CRPR: 0.398ns + Endpoint Relative Delay: 0.618ns + Reference Relative Delay: -0.171ns + Relative CRPR: 0.318ns Uncertainty: 0.122ns - Actual Bus Skew: 0.509ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.593ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -724,13 +724,13 @@ Endpoint path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.802 2.045 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk - SLICE_X52Y75 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.793 2.036 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk + SLICE_X53Y74 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 FDRE (Prop_GFF2_SLICEL_C_Q) - 0.081 2.126 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.390 2.516 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2] - SLICE_X57Y76 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + SLICE_X53Y74 FDRE (Prop_DFF2_SLICEM_C_Q) + 0.080 2.116 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.313 2.429 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1] + SLICE_X53Y74 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -739,16 +739,16 @@ Endpoint path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.632 1.800 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk - SLICE_X57Y76 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C - clock pessimism 0.000 1.800 - SLICE_X57Y76 FDRE (Setup_DFF2_SLICEM_C_D) - 0.025 1.825 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.618 1.786 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk + SLICE_X53Y74 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.000 1.786 + SLICE_X53Y74 FDRE (Setup_HFF2_SLICEM_C_D) + 0.025 1.811 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] ------------------------------------------------------------------- - data arrival 2.516 - clock arrival 1.825 + data arrival 2.429 + clock arrival 1.811 ------------------------------------------------------------------- - relative delay 0.691 + relative delay 0.618 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -758,13 +758,13 @@ Reference path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.597 1.810 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk - SLICE_X52Y75 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.593 1.806 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk + SLICE_X52Y73 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 FDRE (Prop_HFF_SLICEL_C_Q) - 0.058 1.868 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.159 2.027 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0] - SLICE_X55Y76 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + SLICE_X52Y73 FDRE (Prop_HFF2_SLICEL_C_Q) + 0.059 1.865 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.066 1.931 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2] + SLICE_X52Y72 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -773,16 +773,16 @@ Reference path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.851 2.059 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk - SLICE_X55Y76 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C - clock pessimism 0.000 2.059 - SLICE_X55Y76 FDRE (Hold_DFF2_SLICEL_C_D) - 0.062 2.121 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.832 2.040 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk + SLICE_X52Y72 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.000 2.040 + SLICE_X52Y72 FDRE (Hold_DFF2_SLICEL_C_D) + 0.062 2.102 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - data arrival 2.027 - clock arrival 2.121 + data arrival 1.931 + clock arrival 2.102 ------------------------------------------------------------------- - relative delay -0.094 + relative delay -0.171 @@ -793,15 +793,15 @@ Endpoints: 4 From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- -clk_pl_0 Net pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D +clk_pl_0 Net pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D - Slow 0.625 5.775 + Slow 0.667 5.733 -Slack (MET) : 5.775ns (requirement - actual skew) - Endpoint Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C +Slack (MET) : 5.733ns (requirement - actual skew) + Endpoint Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) - Endpoint Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Endpoint Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by Net) Reference Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) @@ -809,11 +809,11 @@ Slack (MET) : 5.775ns (requirement - actual skew) (rising edge-triggered cell FDRE clocked by Net) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 0.654ns - Reference Relative Delay: -0.167ns + Endpoint Relative Delay: 0.685ns + Reference Relative Delay: -0.178ns Relative CRPR: 0.318ns Uncertainty: 0.122ns - Actual Bus Skew: 0.625ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.667ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -824,13 +824,13 @@ Endpoint path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.838 2.046 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk - SLICE_X56Y77 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.821 2.029 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk + SLICE_X52Y73 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X56Y77 FDRE (Prop_DFF_SLICEM_C_Q) - 0.078 2.124 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.365 2.489 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0] - SLICE_X59Y75 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + SLICE_X52Y73 FDRE (Prop_CFF_SLICEL_C_Q) + 0.079 2.108 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.408 2.516 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2] + SLICE_X52Y73 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -838,16 +838,16 @@ Endpoint path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.597 1.810 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk - SLICE_X59Y75 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C - clock pessimism 0.000 1.810 - SLICE_X59Y75 FDRE (Setup_HFF2_SLICEL_C_D) - 0.025 1.835 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.593 1.806 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk + SLICE_X52Y73 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.000 1.806 + SLICE_X52Y73 FDRE (Setup_GFF2_SLICEL_C_D) + 0.025 1.831 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - data arrival 2.489 - clock arrival 1.835 + data arrival 2.516 + clock arrival 1.831 ------------------------------------------------------------------- - relative delay 0.654 + relative delay 0.685 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -858,13 +858,13 @@ Reference path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.618 1.786 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk - SLICE_X58Y75 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.620 1.788 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk + SLICE_X56Y73 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X58Y75 FDRE (Prop_EFF_SLICEL_C_Q) - 0.059 1.845 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.094 1.939 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3] - SLICE_X58Y75 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X56Y73 FDRE (Prop_EFF_SLICEM_C_Q) + 0.058 1.846 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.081 1.927 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3] + SLICE_X56Y72 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -872,16 +872,16 @@ Reference path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.801 2.044 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk - SLICE_X58Y75 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C - clock pessimism 0.000 2.044 - SLICE_X58Y75 FDRE (Hold_DFF2_SLICEL_C_D) - 0.062 2.106 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.800 2.043 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk + SLICE_X56Y72 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism 0.000 2.043 + SLICE_X56Y72 FDRE (Hold_HFF2_SLICEM_C_D) + 0.062 2.105 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- - data arrival 1.939 - clock arrival 2.106 + data arrival 1.927 + clock arrival 2.105 ------------------------------------------------------------------- - relative delay -0.167 + relative delay -0.178 @@ -893,27 +893,27 @@ Endpoints: 4 From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- clk_pl_0 xxv_ethernet_0_tx_clk_out_0 - pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D - pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - Slow 0.936 5.464 + pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.574 5.826 -Slack (MET) : 5.464ns (requirement - actual skew) - Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C +Slack (MET) : 5.826ns (requirement - actual skew) + Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) - Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0) - Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) - Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 0.994ns - Reference Relative Delay: -0.149ns - Relative CRPR: 0.330ns + Endpoint Relative Delay: 0.723ns + Reference Relative Delay: -0.127ns + Relative CRPR: 0.399ns Uncertainty: 0.122ns - Actual Bus Skew: 0.936ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.574ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -924,13 +924,13 @@ Endpoint path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.866 2.074 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk - SLICE_X64Y62 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.850 2.058 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X62Y63 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y62 FDRE (Prop_AFF_SLICEM_C_Q) - 0.077 2.151 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.684 2.835 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] - SLICE_X64Y62 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X62Y63 FDRE (Prop_DFF_SLICEL_C_Q) + 0.079 2.137 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.435 2.572 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X62Y63 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -939,16 +939,16 @@ Endpoint path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.603 1.816 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk - SLICE_X64Y62 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C - clock pessimism 0.000 1.816 - SLICE_X64Y62 FDRE (Setup_HFF2_SLICEM_C_D) - 0.025 1.841 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.611 1.824 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X62Y63 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.000 1.824 + SLICE_X62Y63 FDRE (Setup_HFF2_SLICEL_C_D) + 0.025 1.849 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- - data arrival 2.835 - clock arrival 1.841 + data arrival 2.572 + clock arrival 1.849 ------------------------------------------------------------------- - relative delay 0.994 + relative delay 0.723 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -959,13 +959,13 @@ Reference path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.646 1.814 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk - SLICE_X65Y61 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.641 1.809 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X62Y63 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y61 FDRE (Prop_DFF2_SLICEL_C_Q) - 0.061 1.875 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.127 2.002 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] - SLICE_X65Y59 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + SLICE_X62Y63 FDRE (Prop_CFF_SLICEL_C_Q) + 0.058 1.867 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.155 2.022 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X64Y63 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -974,16 +974,16 @@ Reference path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.846 2.089 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk - SLICE_X65Y59 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C - clock pessimism 0.000 2.089 - SLICE_X65Y59 FDRE (Hold_DFF2_SLICEL_C_D) - 0.062 2.151 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.844 2.087 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X64Y63 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.000 2.087 + SLICE_X64Y63 FDRE (Hold_HFF2_SLICEM_C_D) + 0.062 2.149 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - data arrival 2.002 - clock arrival 2.151 + data arrival 2.022 + clock arrival 2.149 ------------------------------------------------------------------- - relative delay -0.149 + relative delay -0.127 @@ -994,27 +994,27 @@ Endpoints: 4 From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- -clk_pl_0 Net pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - Slow 0.847 5.553 +clk_pl_0 Net pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.462 5.938 -Slack (MET) : 5.553ns (requirement - actual skew) - Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C +Slack (MET) : 5.938ns (requirement - actual skew) + Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) - Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D (rising edge-triggered cell FDRE clocked by Net) - Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) - Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by Net) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 1.026ns - Reference Relative Delay: -0.085ns - Relative CRPR: 0.386ns + Endpoint Relative Delay: 0.878ns + Reference Relative Delay: 0.116ns + Relative CRPR: 0.423ns Uncertainty: 0.122ns - Actual Bus Skew: 0.847ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.462ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1025,13 +1025,13 @@ Endpoint path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.839 2.047 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk - SLICE_X64Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.944 2.152 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X68Y85 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y95 FDRE (Prop_FFF_SLICEM_C_Q) - 0.076 2.123 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.695 2.818 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] - SLICE_X64Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + SLICE_X68Y85 FDRE (Prop_EFF_SLICEL_C_Q) + 0.079 2.231 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.324 2.555 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X68Y85 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -1039,16 +1039,16 @@ Endpoint path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.554 1.767 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk - SLICE_X64Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C - clock pessimism 0.000 1.767 - SLICE_X64Y95 FDRE (Setup_CFF2_SLICEM_C_D) - 0.025 1.792 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.439 1.652 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X68Y85 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism 0.000 1.652 + SLICE_X68Y85 FDRE (Setup_DFF2_SLICEL_C_D) + 0.025 1.677 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- - data arrival 2.818 - clock arrival 1.792 + data arrival 2.555 + clock arrival 1.677 ------------------------------------------------------------------- - relative delay 1.026 + relative delay 0.878 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1059,13 +1059,13 @@ Reference path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.630 1.798 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk - SLICE_X64Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.716 1.884 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X68Y86 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y95 FDRE (Prop_GFF2_SLICEM_C_Q) - 0.060 1.858 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.117 1.975 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] - SLICE_X63Y94 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + SLICE_X68Y86 FDRE (Prop_DFF_SLICEL_C_Q) + 0.059 1.943 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.099 2.042 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X68Y86 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -1073,16 +1073,16 @@ Reference path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.755 1.998 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk - SLICE_X63Y94 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C - clock pessimism 0.000 1.998 - SLICE_X63Y94 FDRE (Hold_HFF2_SLICEM_C_D) - 0.062 2.060 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.621 1.864 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X68Y86 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.000 1.864 + SLICE_X68Y86 FDRE (Hold_GFF2_SLICEL_C_D) + 0.062 1.926 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - data arrival 1.975 - clock arrival 2.060 + data arrival 2.042 + clock arrival 1.926 ------------------------------------------------------------------- - relative delay -0.085 + relative delay 0.116 @@ -1094,26 +1094,26 @@ Endpoints: 4 From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- Net clk_pl_0 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D - pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - Slow 0.455 5.945 + pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 1.152 5.248 -Slack (MET) : 5.945ns (requirement - actual skew) +Slack (MET) : 5.248ns (requirement - actual skew) Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by Net) Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) - Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by Net) - Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 0.565ns - Reference Relative Delay: -0.230ns - Relative CRPR: 0.462ns + Endpoint Relative Delay: 1.048ns + Reference Relative Delay: -0.404ns + Relative CRPR: 0.423ns Uncertainty: 0.122ns - Actual Bus Skew: 0.455ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 1.152ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1123,13 +1123,13 @@ Endpoint path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.763 2.006 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk - SLICE_X64Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.621 1.864 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X68Y86 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y95 FDRE (Prop_DFF_SLICEM_C_Q) - 0.078 2.084 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.315 2.399 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] - SLICE_X64Y96 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + SLICE_X68Y86 FDRE (Prop_HFF_SLICEL_C_Q) + 0.079 1.943 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 1.017 2.960 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X68Y87 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1138,16 +1138,16 @@ Endpoint path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.641 1.809 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk - SLICE_X64Y96 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C - clock pessimism 0.000 1.809 - SLICE_X64Y96 FDRE (Setup_DFF2_SLICEM_C_D) - 0.025 1.834 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.719 1.887 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X68Y87 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.000 1.887 + SLICE_X68Y87 FDRE (Setup_DFF2_SLICEL_C_D) + 0.025 1.912 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- - data arrival 2.399 - clock arrival 1.834 + data arrival 2.960 + clock arrival 1.912 ------------------------------------------------------------------- - relative delay 0.565 + relative delay 1.048 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1157,13 +1157,13 @@ Reference path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.554 1.767 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk - SLICE_X64Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.439 1.652 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X68Y85 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y95 FDRE (Prop_DFF2_SLICEM_C_Q) - 0.061 1.828 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.075 1.903 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] - SLICE_X64Y96 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + SLICE_X68Y85 FDRE (Prop_DFF_SLICEL_C_Q) + 0.059 1.711 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.099 1.810 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X68Y85 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1172,16 +1172,16 @@ Reference path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.863 2.071 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk - SLICE_X64Y96 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C - clock pessimism 0.000 2.071 - SLICE_X64Y96 FDRE (Hold_HFF2_SLICEM_C_D) - 0.062 2.133 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.944 2.152 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X68Y85 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.000 2.152 + SLICE_X68Y85 FDRE (Hold_HFF2_SLICEL_C_D) + 0.062 2.214 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - data arrival 1.903 - clock arrival 2.133 + data arrival 1.810 + clock arrival 2.214 ------------------------------------------------------------------- - relative delay -0.230 + relative delay -0.404 @@ -1193,26 +1193,26 @@ Endpoints: 4 From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- Net clk_pl_0 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D - pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D - Slow 0.553 5.847 + pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.411 5.989 -Slack (MET) : 5.847ns (requirement - actual skew) +Slack (MET) : 5.989ns (requirement - actual skew) Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by Net) Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) - Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by Net) - Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 0.598ns - Reference Relative Delay: -0.151ns - Relative CRPR: 0.319ns + Endpoint Relative Delay: 0.586ns + Reference Relative Delay: -0.077ns + Relative CRPR: 0.374ns Uncertainty: 0.122ns - Actual Bus Skew: 0.553ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.411ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1222,13 +1222,13 @@ Endpoint path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.794 2.037 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk - SLICE_X55Y94 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.767 2.010 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X56Y91 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X55Y94 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 2.116 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.272 2.388 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] - SLICE_X55Y94 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X56Y91 FDRE (Prop_EFF_SLICEM_C_Q) + 0.076 2.086 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.294 2.380 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X56Y91 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1237,16 +1237,16 @@ Endpoint path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.597 1.765 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk - SLICE_X55Y94 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C - clock pessimism 0.000 1.765 - SLICE_X55Y94 FDRE (Setup_DFF2_SLICEL_C_D) - 0.025 1.790 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.601 1.769 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X56Y91 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism 0.000 1.769 + SLICE_X56Y91 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 1.794 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- - data arrival 2.388 - clock arrival 1.790 + data arrival 2.380 + clock arrival 1.794 ------------------------------------------------------------------- - relative delay 0.598 + relative delay 0.586 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1256,13 +1256,13 @@ Reference path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.576 1.789 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk - SLICE_X56Y96 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.575 1.788 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X56Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X56Y96 FDRE (Prop_DFF_SLICEM_C_Q) - 0.058 1.847 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.084 1.931 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] - SLICE_X56Y94 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + SLICE_X56Y95 FDRE (Prop_CFF_SLICEM_C_Q) + 0.058 1.846 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.159 2.005 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X57Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1271,16 +1271,16 @@ Reference path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.813 2.021 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk - SLICE_X56Y94 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C - clock pessimism 0.000 2.021 - SLICE_X56Y94 FDRE (Hold_DFF2_SLICEM_C_D) - 0.061 2.082 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.812 2.020 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X57Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.000 2.020 + SLICE_X57Y95 FDRE (Hold_HFF2_SLICEM_C_D) + 0.062 2.082 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - data arrival 1.931 + data arrival 2.005 clock arrival 2.082 ------------------------------------------------------------------- - relative delay -0.151 + relative delay -0.077 @@ -1291,27 +1291,27 @@ Endpoints: 4 From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- -clk_pl_0 Net pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D - pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - Slow 0.528 5.872 +clk_pl_0 Net pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.802 5.598 -Slack (MET) : 5.872ns (requirement - actual skew) - Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C +Slack (MET) : 5.598ns (requirement - actual skew) + Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) - Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D (rising edge-triggered cell FDRE clocked by Net) - Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) - Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by Net) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 0.599ns - Reference Relative Delay: -0.125ns + Endpoint Relative Delay: 0.899ns + Reference Relative Delay: -0.099ns Relative CRPR: 0.319ns Uncertainty: 0.122ns - Actual Bus Skew: 0.528ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.802ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1322,13 +1322,13 @@ Endpoint path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.814 2.022 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk - SLICE_X60Y94 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.813 2.021 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X56Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X60Y94 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 2.101 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.311 2.412 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] - SLICE_X60Y94 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X56Y95 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 2.100 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.618 2.718 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X56Y96 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -1336,16 +1336,16 @@ Endpoint path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.575 1.788 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk - SLICE_X60Y94 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C - clock pessimism 0.000 1.788 - SLICE_X60Y94 FDRE (Setup_DFF2_SLICEL_C_D) - 0.025 1.813 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.581 1.794 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X56Y96 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.000 1.794 + SLICE_X56Y96 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 1.819 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- - data arrival 2.412 - clock arrival 1.813 + data arrival 2.718 + clock arrival 1.819 ------------------------------------------------------------------- - relative delay 0.599 + relative delay 0.899 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1356,13 +1356,13 @@ Reference path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.609 1.777 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk - SLICE_X55Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.605 1.773 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X57Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X55Y95 FDRE (Prop_HFF2_SLICEL_C_Q) - 0.059 1.836 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.112 1.948 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] - SLICE_X55Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + SLICE_X57Y95 FDRE (Prop_HFF_SLICEM_C_Q) + 0.058 1.831 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.145 1.976 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X57Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -1370,16 +1370,16 @@ Reference path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.768 2.011 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk - SLICE_X55Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C - clock pessimism 0.000 2.011 - SLICE_X55Y95 FDRE (Hold_DFF2_SLICEL_C_D) - 0.062 2.073 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.771 2.014 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X57Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.000 2.014 + SLICE_X57Y95 FDRE (Hold_DFF2_SLICEM_C_D) + 0.061 2.075 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - data arrival 1.948 - clock arrival 2.073 + data arrival 1.976 + clock arrival 2.075 ------------------------------------------------------------------- - relative delay -0.125 + relative delay -0.099 @@ -1390,27 +1390,27 @@ Endpoints: 4 From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- -Net clk_pl_0 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - Slow 1.078 5.322 +Net clk_pl_0 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Slow 0.454 5.946 -Slack (MET) : 5.322ns (requirement - actual skew) - Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C +Slack (MET) : 5.946ns (requirement - actual skew) + Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by Net) - Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) - Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C (rising edge-triggered cell FDRE clocked by Net) - Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 1.191ns - Reference Relative Delay: -0.189ns + Endpoint Relative Delay: 0.531ns + Reference Relative Delay: -0.225ns Relative CRPR: 0.424ns Uncertainty: 0.122ns - Actual Bus Skew: 1.078ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.454ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1420,13 +1420,13 @@ Endpoint path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.746 1.989 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk - SLICE_X65Y83 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.760 2.003 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X65Y85 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y83 FDRE (Prop_HFF2_SLICEL_C_Q) - 0.080 2.069 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.956 3.025 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] - SLICE_X65Y84 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + SLICE_X65Y85 FDRE (Prop_DFF_SLICEL_C_Q) + 0.079 2.082 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.274 2.356 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X65Y85 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1435,16 +1435,16 @@ Endpoint path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.641 1.809 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk - SLICE_X65Y84 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C - clock pessimism 0.000 1.809 - SLICE_X65Y84 FDRE (Setup_CFF2_SLICEL_C_D) - 0.025 1.834 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.632 1.800 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X65Y85 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.000 1.800 + SLICE_X65Y85 FDRE (Setup_HFF2_SLICEL_C_D) + 0.025 1.825 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - data arrival 3.025 - clock arrival 1.834 + data arrival 2.356 + clock arrival 1.825 ------------------------------------------------------------------- - relative delay 1.191 + relative delay 0.531 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1454,13 +1454,13 @@ Reference path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.557 1.770 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk - SLICE_X65Y82 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.549 1.762 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X64Y87 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y82 FDRE (Prop_DFF_SLICEL_C_Q) - 0.059 1.829 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.099 1.928 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] - SLICE_X65Y82 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + SLICE_X64Y87 FDRE (Prop_HFF2_SLICEM_C_Q) + 0.059 1.821 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.070 1.891 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X65Y87 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1469,16 +1469,16 @@ Reference path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.847 2.055 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk - SLICE_X65Y82 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C - clock pessimism 0.000 2.055 - SLICE_X65Y82 FDRE (Hold_HFF2_SLICEL_C_D) - 0.062 2.117 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.846 2.054 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X65Y87 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.000 2.054 + SLICE_X65Y87 FDRE (Hold_DFF2_SLICEL_C_D) + 0.062 2.116 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] ------------------------------------------------------------------- - data arrival 1.928 - clock arrival 2.117 + data arrival 1.891 + clock arrival 2.116 ------------------------------------------------------------------- - relative delay -0.189 + relative delay -0.225 @@ -1489,27 +1489,27 @@ Endpoints: 4 From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- -clk_pl_0 Net pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D - pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - Slow 1.258 5.142 +clk_pl_0 Net pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Slow 1.126 5.274 -Slack (MET) : 5.142ns (requirement - actual skew) - Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C +Slack (MET) : 5.274ns (requirement - actual skew) + Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) - Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D (rising edge-triggered cell FDRE clocked by Net) - Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) - Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D (rising edge-triggered cell FDRE clocked by Net) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 1.446ns - Reference Relative Delay: -0.113ns - Relative CRPR: 0.424ns + Endpoint Relative Delay: 1.319ns + Reference Relative Delay: -0.131ns + Relative CRPR: 0.446ns Uncertainty: 0.122ns - Actual Bus Skew: 1.258ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 1.126ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1520,13 +1520,13 @@ Endpoint path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.864 2.072 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk - SLICE_X65Y83 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.836 2.044 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X65Y86 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y83 FDRE (Prop_AFF_SLICEL_C_Q) - 0.079 2.151 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 1.082 3.233 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] - SLICE_X65Y83 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X65Y86 FDRE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.125 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.986 3.111 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X65Y86 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -1534,16 +1534,16 @@ Endpoint path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.549 1.762 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk - SLICE_X65Y83 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C - clock pessimism 0.000 1.762 - SLICE_X65Y83 FDRE (Setup_GFF2_SLICEL_C_D) - 0.025 1.787 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.554 1.767 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X65Y86 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.000 1.767 + SLICE_X65Y86 FDRE (Setup_HFF2_SLICEL_C_D) + 0.025 1.792 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] ------------------------------------------------------------------- - data arrival 3.233 - clock arrival 1.787 + data arrival 3.111 + clock arrival 1.792 ------------------------------------------------------------------- - relative delay 1.446 + relative delay 1.319 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1554,13 +1554,13 @@ Reference path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.641 1.809 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk - SLICE_X65Y84 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.629 1.797 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X65Y86 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y84 FDRE (Prop_DFF2_SLICEL_C_Q) - 0.061 1.870 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.096 1.966 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] - SLICE_X65Y86 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + SLICE_X65Y86 FDRE (Prop_DFF_SLICEL_C_Q) + 0.059 1.856 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.082 1.938 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X64Y86 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -1568,16 +1568,16 @@ Reference path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.774 2.017 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk - SLICE_X65Y86 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C - clock pessimism 0.000 2.017 - SLICE_X65Y86 FDRE (Hold_HFF2_SLICEL_C_D) - 0.062 2.079 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.765 2.008 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X64Y86 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.000 2.008 + SLICE_X64Y86 FDRE (Hold_DFF2_SLICEM_C_D) + 0.061 2.069 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- - data arrival 1.966 - clock arrival 2.079 + data arrival 1.938 + clock arrival 2.069 ------------------------------------------------------------------- - relative delay -0.113 + relative delay -0.131 @@ -1591,10 +1591,10 @@ From Clock To Clock Endpoint Pin Refe clk_pl_0 xxv_ethernet_0_tx_clk_out_0 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - Slow 0.710 5.690 + Slow 0.555 5.845 -Slack (MET) : 5.690ns (requirement - actual skew) +Slack (MET) : 5.845ns (requirement - actual skew) Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_pl_0) Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D @@ -1605,11 +1605,11 @@ Slack (MET) : 5.690ns (requirement - actual skew) (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 0.864ns - Reference Relative Delay: -0.159ns - Relative CRPR: 0.436ns + Endpoint Relative Delay: 0.614ns + Reference Relative Delay: -0.149ns + Relative CRPR: 0.330ns Uncertainty: 0.122ns - Actual Bus Skew: 0.710ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.555ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1620,13 +1620,13 @@ Endpoint path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.854 2.062 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk - SLICE_X62Y66 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.832 2.040 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X58Y65 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X62Y66 FDRE (Prop_HFF_SLICEL_C_Q) - 0.079 2.141 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.569 2.710 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] - SLICE_X62Y66 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + SLICE_X58Y65 FDRE (Prop_HFF_SLICEL_C_Q) + 0.079 2.119 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.369 2.488 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X58Y65 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -1635,16 +1635,16 @@ Endpoint path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.608 1.821 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk - SLICE_X62Y66 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C - clock pessimism 0.000 1.821 - SLICE_X62Y66 FDRE (Setup_DFF2_SLICEL_C_D) - 0.025 1.846 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.636 1.849 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X58Y65 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.000 1.849 + SLICE_X58Y65 FDRE (Setup_DFF2_SLICEL_C_D) + 0.025 1.874 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- - data arrival 2.710 - clock arrival 1.846 + data arrival 2.488 + clock arrival 1.874 ------------------------------------------------------------------- - relative delay 0.864 + relative delay 0.614 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1655,13 +1655,13 @@ Reference path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.641 1.809 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk - SLICE_X62Y64 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.624 1.792 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X59Y64 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X62Y64 FDRE (Prop_DFF_SLICEL_C_Q) - 0.059 1.868 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.099 1.967 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] - SLICE_X62Y64 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + SLICE_X59Y64 FDRE (Prop_DFF_SLICEL_C_Q) + 0.059 1.851 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.144 1.995 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X59Y64 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -1670,16 +1670,16 @@ Reference path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.821 2.064 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk - SLICE_X62Y64 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C - clock pessimism 0.000 2.064 - SLICE_X62Y64 FDRE (Hold_HFF2_SLICEL_C_D) - 0.062 2.126 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.839 2.082 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X59Y64 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.000 2.082 + SLICE_X59Y64 FDRE (Hold_HFF2_SLICEL_C_D) + 0.062 2.144 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - data arrival 1.967 - clock arrival 2.126 + data arrival 1.995 + clock arrival 2.144 ------------------------------------------------------------------- - relative delay -0.159 + relative delay -0.149 @@ -1691,27 +1691,27 @@ Endpoints: 4 From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- xxv_ethernet_0_tx_clk_out_0 - clk_pl_0 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D - Slow 0.535 5.865 + clk_pl_0 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.674 5.726 -Slack (MET) : 5.865ns (requirement - actual skew) - Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C +Slack (MET) : 5.726ns (requirement - actual skew) + Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0) - Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) - Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0) - Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 0.573ns - Reference Relative Delay: -0.170ns + Endpoint Relative Delay: 0.755ns + Reference Relative Delay: -0.127ns Relative CRPR: 0.330ns Uncertainty: 0.122ns - Actual Bus Skew: 0.535ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.674ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1722,13 +1722,13 @@ Endpoint path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.818 2.061 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk - SLICE_X63Y67 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.838 2.081 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X60Y67 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X63Y67 FDRE (Prop_DFF_SLICEM_C_Q) - 0.078 2.139 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.275 2.414 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] - SLICE_X63Y67 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + SLICE_X60Y67 FDRE (Prop_HFF2_SLICEL_C_Q) + 0.080 2.161 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.439 2.600 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X63Y68 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1737,16 +1737,16 @@ Endpoint path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.648 1.816 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk - SLICE_X63Y67 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C - clock pessimism 0.000 1.816 - SLICE_X63Y67 FDRE (Setup_HFF2_SLICEM_C_D) - 0.025 1.841 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.652 1.820 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X63Y68 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.000 1.820 + SLICE_X63Y68 FDRE (Setup_HFF2_SLICEM_C_D) + 0.025 1.845 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] ------------------------------------------------------------------- - data arrival 2.414 - clock arrival 1.841 + data arrival 2.600 + clock arrival 1.845 ------------------------------------------------------------------- - relative delay 0.573 + relative delay 0.755 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1757,13 +1757,13 @@ Reference path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.604 1.817 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk - SLICE_X65Y67 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.627 1.840 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X58Y66 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y67 FDRE (Prop_AFF_SLICEL_C_Q) - 0.058 1.875 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.095 1.970 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] - SLICE_X65Y67 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X58Y66 FDRE (Prop_DFF_SLICEL_C_Q) + 0.059 1.899 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.099 1.998 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X58Y66 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1772,16 +1772,16 @@ Reference path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.870 2.078 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk - SLICE_X65Y67 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C - clock pessimism 0.000 2.078 - SLICE_X65Y67 FDRE (Hold_HFF2_SLICEL_C_D) - 0.062 2.140 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.855 2.063 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X58Y66 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.000 2.063 + SLICE_X58Y66 FDRE (Hold_HFF2_SLICEL_C_D) + 0.062 2.125 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - data arrival 1.970 - clock arrival 2.140 + data arrival 1.998 + clock arrival 2.125 ------------------------------------------------------------------- - relative delay -0.170 + relative delay -0.127 @@ -1794,26 +1794,26 @@ From Clock To Clock Endpoint Pin Refe -------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- xxv_ethernet_0_tx_clk_out_0 clk_pl_0 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D - Slow 1.125 5.275 + pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.544 5.856 -Slack (MET) : 5.275ns (requirement - actual skew) +Slack (MET) : 5.856ns (requirement - actual skew) Endpoint Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0) Endpoint Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) - Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + Reference Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0) - Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Reference Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by clk_pl_0) Path Type: Bus Skew (Max at Slow Process Corner) Requirement: 6.400ns - Endpoint Relative Delay: 1.275ns - Reference Relative Delay: -0.128ns - Relative CRPR: 0.400ns + Endpoint Relative Delay: 0.607ns + Reference Relative Delay: -0.145ns + Relative CRPR: 0.330ns Uncertainty: 0.122ns - Actual Bus Skew: 1.125ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) + Actual Bus Skew: 0.544ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR + Uncertainty) Endpoint path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1824,13 +1824,13 @@ Endpoint path: net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.806 2.049 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk - SLICE_X65Y63 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.816 2.059 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X63Y66 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y63 FDRE (Prop_DFF2_SLICEL_C_Q) - 0.081 2.130 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.986 3.116 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] - SLICE_X65Y63 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + SLICE_X63Y66 FDRE (Prop_HFF2_SLICEM_C_Q) + 0.078 2.137 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.324 2.461 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X64Y66 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1839,16 +1839,16 @@ Endpoint path: net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.648 1.816 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk - SLICE_X65Y63 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C - clock pessimism 0.000 1.816 - SLICE_X65Y63 FDRE (Setup_HFF2_SLICEL_C_D) - 0.025 1.841 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.661 1.829 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X64Y66 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.000 1.829 + SLICE_X64Y66 FDRE (Setup_GFF2_SLICEM_C_D) + 0.025 1.854 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] ------------------------------------------------------------------- - data arrival 3.116 - clock arrival 1.841 + data arrival 2.461 + clock arrival 1.854 ------------------------------------------------------------------- - relative delay 1.275 + relative delay 0.607 Reference path: Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1859,13 +1859,13 @@ Reference path: net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.600 1.813 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk - SLICE_X65Y63 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.608 1.821 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X62Y65 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y63 FDRE (Prop_DFF_SLICEL_C_Q) - 0.059 1.872 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.143 2.015 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] - SLICE_X63Y62 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + SLICE_X62Y65 FDRE (Prop_DFF_SLICEL_C_Q) + 0.059 1.880 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.099 1.979 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X62Y65 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1874,16 +1874,16 @@ Reference path: net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.873 2.081 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk - SLICE_X63Y62 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C - clock pessimism 0.000 2.081 - SLICE_X63Y62 FDRE (Hold_HFF2_SLICEM_C_D) - 0.062 2.143 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.854 2.062 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X62Y65 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.000 2.062 + SLICE_X62Y65 FDRE (Hold_HFF2_SLICEL_C_D) + 0.062 2.124 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - data arrival 2.015 - clock arrival 2.143 + data arrival 1.979 + clock arrival 2.124 ------------------------------------------------------------------- - relative delay -0.128 + relative delay -0.145 diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_bus_skew_routed.rpx b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_bus_skew_routed.rpx index 6ddbdee..ff6dc30 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_bus_skew_routed.rpx and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_bus_skew_routed.rpx differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_clock_utilization_routed.rpt b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_clock_utilization_routed.rpt index 9bfbd7e..9387beb 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_clock_utilization_routed.rpt +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_clock_utilization_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -| Date : Fri Oct 20 13:01:38 2023 +| Date : Fri Oct 20 19:48:36 2023 | Host : DESKTOP-5FH9OH3 running 64-bit major release (build 9200) | Command : report_clock_utilization -file pl_eth_10g_wrapper_clock_utilization_routed.rpt | Design : pl_eth_10g_wrapper @@ -33,24 +33,23 @@ Table of Contents 16. Device Cell Placement Summary for Global Clock g7 17. Clock Region Cell Placement per Global Clock: Region X1Y0 18. Clock Region Cell Placement per Global Clock: Region X2Y0 -19. Clock Region Cell Placement per Global Clock: Region X3Y0 -20. Clock Region Cell Placement per Global Clock: Region X1Y1 -21. Clock Region Cell Placement per Global Clock: Region X2Y1 -22. Clock Region Cell Placement per Global Clock: Region X3Y1 -23. Clock Region Cell Placement per Global Clock: Region X1Y2 -24. Clock Region Cell Placement per Global Clock: Region X2Y2 -25. Clock Region Cell Placement per Global Clock: Region X3Y2 -26. Clock Region Cell Placement per Global Clock: Region X1Y3 -27. Clock Region Cell Placement per Global Clock: Region X2Y3 -28. Clock Region Cell Placement per Global Clock: Region X3Y3 -29. Clock Region Cell Placement per Global Clock: Region X0Y4 -30. Clock Region Cell Placement per Global Clock: Region X1Y4 -31. Clock Region Cell Placement per Global Clock: Region X2Y4 -32. Clock Region Cell Placement per Global Clock: Region X3Y4 -33. Clock Region Cell Placement per Global Clock: Region X0Y5 -34. Clock Region Cell Placement per Global Clock: Region X1Y5 -35. Clock Region Cell Placement per Global Clock: Region X2Y5 -36. Clock Region Cell Placement per Global Clock: Region X3Y5 +19. Clock Region Cell Placement per Global Clock: Region X1Y1 +20. Clock Region Cell Placement per Global Clock: Region X2Y1 +21. Clock Region Cell Placement per Global Clock: Region X3Y1 +22. Clock Region Cell Placement per Global Clock: Region X1Y2 +23. Clock Region Cell Placement per Global Clock: Region X2Y2 +24. Clock Region Cell Placement per Global Clock: Region X3Y2 +25. Clock Region Cell Placement per Global Clock: Region X1Y3 +26. Clock Region Cell Placement per Global Clock: Region X2Y3 +27. Clock Region Cell Placement per Global Clock: Region X3Y3 +28. Clock Region Cell Placement per Global Clock: Region X0Y4 +29. Clock Region Cell Placement per Global Clock: Region X1Y4 +30. Clock Region Cell Placement per Global Clock: Region X2Y4 +31. Clock Region Cell Placement per Global Clock: Region X3Y4 +32. Clock Region Cell Placement per Global Clock: Region X0Y5 +33. Clock Region Cell Placement per Global Clock: Region X1Y5 +34. Clock Region Cell Placement per Global Clock: Region X2Y5 +35. Clock Region Cell Placement per Global Clock: Region X3Y5 1. Clock Primitive Utilization ------------------------------ @@ -73,14 +72,14 @@ Table of Contents +-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+-----------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Root | Clock Delay Group | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+-----------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| g0 | src0 | BUFG_GT/O | None | BUFG_GT_X0Y71 | X3Y2 | X2Y2 | | 15 | 10988 | 0 | 6.400 | Net | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | +| g0 | src0 | BUFG_GT/O | None | BUFG_GT_X0Y71 | X3Y2 | X2Y2 | | 16 | 11001 | 0 | 6.400 | Net | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | g1 | src0 | BUFG_GT/O | None | BUFG_GT_X0Y66 | X3Y2 | X2Y2 | | 1 | 1 | 0 | 3.200 | rxoutclk_out[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxusrclk_in[0] | -| g2 | src1 | BUFG_GT/O | None | BUFG_GT_X0Y48 | X3Y2 | X2Y2 | | 11 | 9063 | 0 | 6.400 | xxv_ethernet_0_tx_clk_out_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | +| g2 | src1 | BUFG_GT/O | None | BUFG_GT_X0Y48 | X3Y2 | X2Y2 | | 10 | 9063 | 0 | 6.400 | xxv_ethernet_0_tx_clk_out_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | g3 | src1 | BUFG_GT/O | None | BUFG_GT_X0Y55 | X3Y2 | X2Y2 | | 1 | 1 | 0 | 3.200 | txoutclk_out[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txusrclk_in[0] | -| g4 | src2 | BUFG_PS/O | None | BUFG_PS_X0Y84 | X1Y3 | X1Y2 | | 12 | 8664 | 0 | 8.000 | clk_pl_0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +| g4 | src2 | BUFG_PS/O | None | BUFG_PS_X0Y84 | X1Y3 | X1Y2 | | 12 | 8670 | 0 | 8.000 | clk_pl_0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | g5 | src3 | BUFGCE/O | None | BUFGCE_X1Y56 | X2Y2 | X2Y2 | n/a | 2 | 0 | 1159 | n/a | n/a | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out_reg_bufg_place/O | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | -| g6 | src4 | BUFGCE/O | None | BUFGCE_X1Y50 | X2Y2 | X2Y2 | n/a | 4 | 0 | 1680 | n/a | n/a | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/pass_statshold_value_reg_bufg_place/O | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0] | -| g7 | src5 | BUFGCE/O | None | BUFGCE_X1Y62 | X2Y2 | X2Y2 | n/a | 4 | 0 | 1152 | n/a | n/a | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/pass_statshold_value_reg_bufg_place/O | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0] | +| g6 | src4 | BUFGCE/O | None | BUFGCE_X1Y74 | X2Y3 | X2Y3 | n/a | 4 | 0 | 1680 | n/a | n/a | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/pass_statshold_value_reg_bufg_place/O | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0] | +| g7 | src5 | BUFGCE/O | None | BUFGCE_X1Y86 | X2Y3 | X2Y3 | n/a | 2 | 0 | 1152 | n/a | n/a | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/pass_statshold_value_reg_bufg_place/O | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0] | +-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+-----------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) @@ -97,9 +96,9 @@ Table of Contents | src1 | g2 | GTHE4_CHANNEL/TXOUTCLK | GTHE4_CHANNEL_X0Y10 | GTHE4_CHANNEL_X0Y10 | X3Y2 | 3 | 0 | 3.200 | txoutclk_out[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[0] | | src1 | g3 | GTHE4_CHANNEL/TXOUTCLK | GTHE4_CHANNEL_X0Y10 | GTHE4_CHANNEL_X0Y10 | X3Y2 | 3 | 0 | 3.200 | txoutclk_out[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[0] | | src2 | g4 | PS8/PLCLK[0] | None | PS8_X0Y0 | X0Y1 | 1 | 0 | 8.000 | clk_pl_0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] | -| src3 | g5 | FDRE/Q | None | SLICE_X77Y107 | X2Y1 | 1 | 0 | | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out_reg/Q | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out_bufg_place | -| src4 | g6 | FDSE/Q | None | SLICE_X70Y149 | X2Y2 | 1 | 0 | | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/pass_statshold_value_reg/Q | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0]_bufg_place | -| src5 | g7 | FDSE/Q | None | SLICE_X69Y148 | X2Y2 | 1 | 0 | | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/pass_statshold_value_reg/Q | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0]_bufg_place | +| src3 | g5 | FDRE/Q | None | SLICE_X94Y148 | X3Y2 | 1 | 0 | | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out_reg/Q | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out_bufg_place | +| src4 | g6 | FDSE/Q | None | SLICE_X95Y174 | X3Y2 | 1 | 0 | | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/pass_statshold_value_reg/Q | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0]_bufg_place | +| src5 | g7 | FDSE/Q | None | SLICE_X95Y170 | X3Y2 | 1 | 0 | | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/pass_statshold_value_reg/Q | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0]_bufg_place | +-----------+-----------+------------------------+---------------------+---------------------+--------------+-------------+-----------------+---------------------+-----------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) @@ -129,19 +128,19 @@ Table of Contents | X0Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X1Y0 | 2 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X2Y0 | 1 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | -| X3Y0 | 1 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 0 | +| X3Y0 | 0 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 0 | | X0Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X1Y1 | 3 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| X2Y1 | 5 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | -| X3Y1 | 4 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 0 | +| X2Y1 | 4 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | +| X3Y1 | 2 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 0 | | X0Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X1Y2 | 3 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| X2Y2 | 7 | 24 | 3 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | -| X3Y2 | 7 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 24 | 0 | 0 | 0 | 0 | +| X2Y2 | 8 | 24 | 1 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | +| X3Y2 | 8 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 24 | 0 | 0 | 0 | 0 | | X0Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X1Y3 | 2 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| X2Y3 | 4 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | -| X3Y3 | 3 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 0 | +| X2Y3 | 4 | 24 | 2 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | +| X3Y3 | 4 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 0 | | X0Y4 | 2 | 24 | 0 | 28 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X1Y4 | 2 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X2Y4 | 1 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | @@ -163,28 +162,28 @@ Table of Contents | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+ | X0Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| X1Y0 | 2 | 24 | 1585 | 17280 | 103 | 4320 | 6 | 24 | 0 | 16 | 0 | 96 | 0 | 0 | 0 | 0 | -| X2Y0 | 1 | 24 | 0 | 22080 | 0 | 5760 | 10 | 24 | 0 | 0 | 0 | 120 | 0 | 0 | 0 | 0 | -| X3Y0 | 1 | 24 | 0 | 22080 | 0 | 3360 | 16 | 48 | 0 | 0 | 0 | 48 | 0 | 4 | 0 | 1 | +| X1Y0 | 2 | 24 | 1674 | 17280 | 94 | 4320 | 6 | 24 | 0 | 16 | 0 | 96 | 0 | 0 | 0 | 0 | +| X2Y0 | 1 | 24 | 0 | 22080 | 0 | 5760 | 2 | 24 | 0 | 0 | 0 | 120 | 0 | 0 | 0 | 0 | +| X3Y0 | 0 | 24 | 0 | 22080 | 0 | 3360 | 0 | 48 | 0 | 0 | 0 | 48 | 0 | 4 | 0 | 1 | | X0Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| X1Y1 | 3 | 24 | 5091 | 17280 | 206 | 4320 | 6 | 24 | 0 | 16 | 0 | 96 | 0 | 0 | 0 | 0 | -| X2Y1 | 5 | 24 | 2483 | 22080 | 4 | 5760 | 24 | 24 | 0 | 0 | 0 | 120 | 0 | 0 | 0 | 0 | -| X3Y1 | 4 | 24 | 582 | 22080 | 1 | 3360 | 16 | 48 | 0 | 0 | 0 | 48 | 0 | 4 | 0 | 1 | +| X1Y1 | 3 | 24 | 4799 | 17280 | 218 | 4320 | 6 | 24 | 0 | 16 | 0 | 96 | 0 | 0 | 0 | 0 | +| X2Y1 | 4 | 24 | 232 | 22080 | 0 | 5760 | 24 | 24 | 0 | 0 | 0 | 120 | 0 | 0 | 0 | 0 | +| X3Y1 | 2 | 24 | 326 | 22080 | 0 | 3360 | 24 | 48 | 0 | 0 | 0 | 48 | 0 | 4 | 0 | 1 | | X0Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| X1Y2 | 3 | 24 | 1154 | 17280 | 24 | 4320 | 0 | 24 | 0 | 16 | 0 | 96 | 0 | 0 | 0 | 0 | -| X2Y2 | 7 | 24 | 7414 | 22080 | 0 | 5760 | 24 | 24 | 0 | 0 | 0 | 120 | 0 | 0 | 0 | 0 | -| X3Y2 | 7 | 24 | 4128 | 22080 | 1 | 3360 | 16 | 48 | 0 | 0 | 0 | 48 | 1 | 4 | 0 | 0 | +| X1Y2 | 3 | 24 | 1463 | 17280 | 23 | 4320 | 0 | 24 | 0 | 16 | 0 | 96 | 0 | 0 | 0 | 0 | +| X2Y2 | 8 | 24 | 3645 | 22080 | 0 | 5760 | 24 | 24 | 0 | 0 | 0 | 120 | 0 | 0 | 0 | 0 | +| X3Y2 | 8 | 24 | 5405 | 22080 | 5 | 3360 | 24 | 48 | 0 | 0 | 0 | 48 | 1 | 4 | 0 | 0 | | X0Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| X1Y3 | 2 | 24 | 1015 | 17280 | 41 | 4320 | 0 | 24 | 0 | 16 | 0 | 96 | 0 | 0 | 0 | 0 | -| X2Y3 | 4 | 24 | 825 | 22080 | 74 | 5760 | 20 | 24 | 0 | 0 | 0 | 120 | 0 | 0 | 0 | 0 | -| X3Y3 | 3 | 24 | 692 | 22080 | 33 | 3360 | 16 | 48 | 0 | 0 | 0 | 48 | 0 | 4 | 0 | 0 | -| X0Y4 | 2 | 24 | 2492 | 40320 | 19 | 9120 | 4 | 24 | 0 | 0 | 0 | 48 | 0 | 0 | 0 | 0 | -| X1Y4 | 2 | 24 | 306 | 23040 | 2 | 5760 | 14 | 24 | 0 | 16 | 0 | 120 | 0 | 0 | 0 | 0 | -| X2Y4 | 1 | 24 | 71 | 22080 | 0 | 5760 | 20 | 24 | 0 | 0 | 0 | 120 | 0 | 0 | 0 | 0 | -| X3Y4 | 1 | 24 | 0 | 22080 | 0 | 3360 | 16 | 48 | 0 | 0 | 0 | 48 | 0 | 4 | 0 | 0 | +| X1Y3 | 2 | 24 | 894 | 17280 | 42 | 4320 | 0 | 24 | 0 | 16 | 0 | 96 | 0 | 0 | 0 | 0 | +| X2Y3 | 4 | 24 | 2387 | 22080 | 0 | 5760 | 16 | 24 | 0 | 0 | 0 | 120 | 0 | 0 | 0 | 0 | +| X3Y3 | 4 | 24 | 4233 | 22080 | 108 | 3360 | 24 | 48 | 0 | 0 | 0 | 48 | 0 | 4 | 0 | 0 | +| X0Y4 | 2 | 24 | 2237 | 40320 | 19 | 9120 | 4 | 24 | 0 | 0 | 0 | 48 | 0 | 0 | 0 | 0 | +| X1Y4 | 2 | 24 | 467 | 23040 | 2 | 5760 | 16 | 24 | 0 | 16 | 0 | 120 | 0 | 0 | 0 | 0 | +| X2Y4 | 1 | 24 | 26 | 22080 | 0 | 5760 | 22 | 24 | 0 | 0 | 0 | 120 | 0 | 0 | 0 | 0 | +| X3Y4 | 1 | 24 | 66 | 22080 | 0 | 3360 | 24 | 48 | 0 | 0 | 0 | 48 | 0 | 4 | 0 | 0 | | X0Y5 | 1 | 24 | 0 | 40320 | 0 | 9120 | 16 | 24 | 0 | 0 | 0 | 48 | 0 | 0 | 0 | 0 | -| X1Y5 | 1 | 24 | 36 | 23040 | 0 | 5760 | 18 | 24 | 0 | 16 | 0 | 120 | 0 | 0 | 0 | 0 | -| X2Y5 | 1 | 24 | 0 | 22080 | 0 | 5760 | 16 | 24 | 0 | 0 | 0 | 120 | 0 | 0 | 0 | 0 | +| X1Y5 | 1 | 24 | 36 | 23040 | 0 | 5760 | 16 | 24 | 0 | 16 | 0 | 120 | 0 | 0 | 0 | 0 | +| X2Y5 | 1 | 24 | 0 | 22080 | 0 | 5760 | 10 | 24 | 0 | 0 | 0 | 120 | 0 | 0 | 0 | 0 | | X3Y5 | 1 | 24 | 0 | 22080 | 0 | 3360 | 16 | 48 | 0 | 0 | 0 | 48 | 0 | 4 | 0 | 0 | +-------------------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+ * Global Clock column represents track count; while other columns represents cell counts @@ -199,10 +198,10 @@ All Modules +----+----+----+----+----+ | Y5 | 1 | 1 | 1 | 1 | | Y4 | 2 | 2 | 1 | 1 | -| Y3 | 0 | 2 | 4 | 3 | -| Y2 | 0 | 3 | 8 | 7 | -| Y1 | 0 | 3 | 5 | 4 | -| Y0 | 0 | 2 | 1 | 1 | +| Y3 | 0 | 2 | 5 | 4 | +| Y2 | 0 | 3 | 8 | 8 | +| Y1 | 0 | 3 | 4 | 2 | +| Y0 | 0 | 2 | 1 | 0 | +----+----+----+----+----+ @@ -218,19 +217,19 @@ All Modules | X0Y0 | 0 | 0 | 0.00 | 0 | 0 | 0.00 | 0 | 0 | 0.00 | 0 | 0 | 0.00 | | X1Y0 | 0 | 24 | 0.00 | 2 | 24 | 8.33 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X2Y0 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | -| X3Y0 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | +| X3Y0 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X0Y1 | 0 | 0 | 0.00 | 0 | 0 | 0.00 | 0 | 0 | 0.00 | 0 | 0 | 0.00 | | X1Y1 | 0 | 24 | 0.00 | 3 | 24 | 12.50 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | -| X2Y1 | 0 | 24 | 0.00 | 5 | 24 | 20.83 | 0 | 24 | 0.00 | 4 | 24 | 16.67 | -| X3Y1 | 0 | 24 | 0.00 | 4 | 24 | 16.67 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | +| X2Y1 | 0 | 24 | 0.00 | 4 | 24 | 16.67 | 0 | 24 | 0.00 | 3 | 24 | 12.50 | +| X3Y1 | 0 | 24 | 0.00 | 2 | 24 | 8.33 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X0Y2 | 0 | 0 | 0.00 | 0 | 0 | 0.00 | 0 | 0 | 0.00 | 0 | 0 | 0.00 | | X1Y2 | 0 | 24 | 0.00 | 3 | 24 | 12.50 | 1 | 24 | 4.17 | 1 | 24 | 4.17 | -| X2Y2 | 6 | 24 | 25.00 | 7 | 24 | 29.17 | 0 | 24 | 0.00 | 7 | 24 | 29.17 | -| X3Y2 | 8 | 24 | 33.33 | 7 | 24 | 29.17 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | +| X2Y2 | 6 | 24 | 25.00 | 8 | 24 | 33.33 | 0 | 24 | 0.00 | 7 | 24 | 29.17 | +| X3Y2 | 8 | 24 | 33.33 | 8 | 24 | 33.33 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X0Y3 | 0 | 0 | 0.00 | 0 | 0 | 0.00 | 0 | 0 | 0.00 | 0 | 0 | 0.00 | | X1Y3 | 2 | 24 | 8.33 | 2 | 24 | 8.33 | 1 | 24 | 4.17 | 1 | 24 | 4.17 | -| X2Y3 | 0 | 24 | 0.00 | 4 | 24 | 16.67 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | -| X3Y3 | 0 | 24 | 0.00 | 3 | 24 | 12.50 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | +| X2Y3 | 0 | 24 | 0.00 | 4 | 24 | 16.67 | 0 | 24 | 0.00 | 3 | 24 | 12.50 | +| X3Y3 | 0 | 24 | 0.00 | 4 | 24 | 16.67 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X0Y4 | 0 | 24 | 0.00 | 2 | 24 | 8.33 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X1Y4 | 0 | 24 | 0.00 | 2 | 24 | 8.33 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X2Y4 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | @@ -248,7 +247,7 @@ All Modules +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------------------------------------------------------------+ -| g0 | BUFG_GT/O | X3Y2 | Net | 6.400 | {0.000 3.200} | X2Y2 | 10888 | 0 | 0 | 1 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | +| g0 | BUFG_GT/O | X3Y2 | Net | 6.400 | {0.000 3.200} | X2Y2 | 10901 | 0 | 0 | 1 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+---------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types @@ -256,16 +255,16 @@ All Modules **** GT Loads column represents load cell count of GT types -+----+----+-------+----------+-----------+-----------------------+ -| | X0 | X1 | X2 | X3 | HORIZONTAL PROG DELAY | -+----+----+-------+----------+-----------+-----------------------+ -| Y5 | 8 | 45 | 8 | 8 | 0 | -| Y4 | 2 | 136 | 81 | 8 | 1 | -| Y3 | 0 | 5 | 899 | 725 | 2 | -| Y2 | 0 | 157 | (R) 5077 | (D) 1690 | 2 | -| Y1 | 0 | 2040 | 0 | 0 | 1 | -| Y0 | 0 | 0 | 0 | 0 | 0 | -+----+----+-------+----------+-----------+-----------------------+ ++----+----+-------+---------+-----------+-----------------------+ +| | X0 | X1 | X2 | X3 | HORIZONTAL PROG DELAY | ++----+----+-------+---------+-----------+-----------------------+ +| Y5 | 8 | 44 | 5 | 8 | 0 | +| Y4 | 2 | 137 | 37 | 78 | 1 | +| Y3 | 0 | 5 | 2283 | 4278 | 2 | +| Y2 | 0 | 244 | (R) 334 | (D) 1473 | 2 | +| Y1 | 0 | 1914 | 52 | 0 | 1 | +| Y0 | 0 | 0 | 0 | 0 | 0 | ++----+----+-------+---------+-----------+-----------------------+ 10. Device Cell Placement Summary for Global Clock g1 @@ -313,10 +312,10 @@ All Modules +----+----+-------+----------+-----------+-----------------------+ | Y5 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | -| Y3 | 0 | 0 | 4 | 8 | 2 | -| Y2 | 0 | 5 | (R) 1929 | (D) 2237 | 2 | -| Y1 | 0 | 239 | 2427 | 581 | 1 | -| Y0 | 0 | 1547 | 5 | 8 | 0 | +| Y3 | 0 | 0 | 8 | 10 | 2 | +| Y2 | 0 | 1 | (R) 3305 | (D) 3395 | 2 | +| Y1 | 0 | 287 | 142 | 338 | 1 | +| Y0 | 0 | 1503 | 1 | 0 | 0 | +----+----+-------+----------+-----------+-----------------------+ @@ -352,7 +351,7 @@ All Modules +-----------+-----------------+-------------------+----------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------+ -| g4 | BUFG_PS/O | X1Y3 | clk_pl_0 | 8.000 | {0.000 4.000} | X1Y2 | 8634 | 0 | 0 | 1 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +| g4 | BUFG_PS/O | X1Y3 | clk_pl_0 | 8.000 | {0.000 4.000} | X1Y2 | 8640 | 0 | 0 | 1 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +-----------+-----------------+-------------------+----------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types @@ -360,16 +359,16 @@ All Modules **** GT Loads column represents load cell count of GT types -+----+-------+-----------+------+------+-----------------------+ -| | X0 | X1 | X2 | X3 | HORIZONTAL PROG DELAY | -+----+-------+-----------+------+------+-----------------------+ -| Y5 | 0 | 0 | 0 | 0 | 0 | -| Y4 | 2511 | 179 | 0 | 0 | 1 | -| Y3 | 0 | (D) 1051 | 6 | 0 | 2 | -| Y2 | 0 | (R) 1016 | 420 | 198 | 2 | -| Y1 | 1 | 3024 | 72 | 10 | 1 | -| Y0 | 0 | 147 | 0 | 0 | 0 | -+----+-------+-----------+------+------+-----------------------+ ++----+-------+----------+------+------+-----------------------+ +| | X0 | X1 | X2 | X3 | HORIZONTAL PROG DELAY | ++----+-------+----------+------+------+-----------------------+ +| Y5 | 0 | 0 | 0 | 0 | 0 | +| Y4 | 2256 | 340 | 0 | 0 | 1 | +| Y3 | 0 | (D) 931 | 104 | 65 | 2 | +| Y2 | 0 | (R) 1241 | 18 | 542 | 2 | +| Y1 | 1 | 2822 | 50 | 0 | 1 | +| Y0 | 0 | 271 | 0 | 0 | 0 | ++----+-------+----------+------+------+-----------------------+ 14. Device Cell Placement Summary for Global Clock g5 @@ -392,8 +391,8 @@ All Modules | Y5 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | -| Y2 | 0 | 0 | (R) (D) 0 | 0 | 0 | -| Y1 | 0 | 0 | 885 | 274 | 0 | +| Y2 | 0 | 0 | (R) (D) 0 | 833 | 0 | +| Y1 | 0 | 0 | 0 | 326 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+-----------+------+-----------------------+ @@ -404,7 +403,7 @@ All Modules +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| g6 | BUFGCE/O | X2Y2 | | | | X2Y2 | 1680 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0] | +| g6 | BUFGCE/O | X2Y3 | | | | X2Y3 | 1680 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0] | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types @@ -412,52 +411,52 @@ All Modules **** GT Loads column represents load cell count of GT types -+----+----+----+--------------+------+-----------------------+ -| | X0 | X1 | X2 | X3 | HORIZONTAL PROG DELAY | -+----+----+----+--------------+------+-----------------------+ -| Y5 | 0 | 0 | 0 | 0 | 0 | -| Y4 | 0 | 0 | 0 | 0 | 0 | -| Y3 | 0 | 0 | 65 | 28 | 0 | -| Y2 | 0 | 0 | (R) (D) 1290 | 297 | 0 | -| Y1 | 0 | 0 | 0 | 0 | 0 | -| Y0 | 0 | 0 | 0 | 0 | 0 | -+----+----+----+--------------+------+-----------------------+ - - -16. Device Cell Placement Summary for Global Clock g7 ------------------------------------------------------ - -+-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | -+-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| g7 | BUFGCE/O | X2Y2 | | | | X2Y2 | 1152 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0] | -+-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources -** IO Loads column represents load cell count of IO types -*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) -**** GT Loads column represents load cell count of GT types - - +----+----+----+-------------+------+-----------------------+ | | X0 | X1 | X2 | X3 | HORIZONTAL PROG DELAY | +----+----+----+-------------+------+-----------------------+ | Y5 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | -| Y3 | 0 | 0 | 0 | 0 | 0 | -| Y2 | 0 | 0 | (R) (D) 306 | 604 | 0 | -| Y1 | 0 | 0 | 179 | 63 | 0 | +| Y3 | 0 | 0 | (R) (D) 637 | 734 | 0 | +| Y2 | 0 | 0 | 119 | 190 | 0 | +| Y1 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+-------------+------+-----------------------+ +16. Device Cell Placement Summary for Global Clock g7 +----------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| g7 | BUFGCE/O | X2Y3 | | | | X2Y3 | 1152 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0] | ++-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+----+-----------+------+-----------------------+ +| | X0 | X1 | X2 | X3 | HORIZONTAL PROG DELAY | ++----+----+----+-----------+------+-----------------------+ +| Y5 | 0 | 0 | 0 | 0 | 0 | +| Y4 | 0 | 0 | 0 | 0 | 0 | +| Y3 | 0 | 0 | (R) (D) 0 | 0 | 0 | +| Y2 | 0 | 0 | 907 | 245 | 0 | +| Y1 | 0 | 0 | 0 | 0 | 0 | +| Y0 | 0 | 0 | 0 | 0 | 0 | ++----+----+----+-----------+------+-----------------------+ + + 17. Clock Region Cell Placement per Global Clock: Region X1Y0 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| g2 | 0 | BUFG_GT/O | None | 1547 | 0 | 1440 | 103 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | -| g4 | 12 | BUFG_PS/O | None | 147 | 0 | 145 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +| g2 | 0 | BUFG_GT/O | None | 1503 | 0 | 1405 | 94 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | +| g4 | 12 | BUFG_PS/O | None | 271 | 0 | 269 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) @@ -470,104 +469,88 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| g2 | 0 | BUFG_GT/O | None | 5 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | +| g2 | 0 | BUFG_GT/O | None | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts -19. Clock Region Cell Placement per Global Clock: Region X3Y0 -------------------------------------------------------------- - -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| g2 | 0 | BUFG_GT/O | None | 8 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) -*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts - - -20. Clock Region Cell Placement per Global Clock: Region X1Y1 +19. Clock Region Cell Placement per Global Clock: Region X1Y1 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| g0 | 23 | BUFG_GT/O | None | 2040 | 0 | 1894 | 142 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | -| g2 | 0 | BUFG_GT/O | None | 239 | 0 | 239 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | -| g4 | 12 | BUFG_PS/O | None | 3024 | 0 | 2958 | 64 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +| g0 | 23 | BUFG_GT/O | None | 1914 | 0 | 1765 | 145 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | +| g2 | 0 | BUFG_GT/O | None | 287 | 0 | 278 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | +| g4 | 12 | BUFG_PS/O | None | 2822 | 0 | 2756 | 64 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts -21. Clock Region Cell Placement per Global Clock: Region X2Y1 -------------------------------------------------------------- - -+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| g0+ | 23 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | -| g2 | 0 | BUFG_GT/O | None | 2427 | 0 | 2411 | 4 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | -| g4 | 12 | BUFG_PS/O | None | 72 | 0 | 72 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | -| g5 | 8 | BUFGCE/O | None | 0 | 885 | 885 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | -| g7 | 14 | BUFGCE/O | None | 0 | 179 | 179 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0] | -+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) -*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts -**** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. - - -22. Clock Region Cell Placement per Global Clock: Region X3Y1 +20. Clock Region Cell Placement per Global Clock: Region X2Y1 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| g2 | 0 | BUFG_GT/O | None | 581 | 0 | 573 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | -| g4 | 12 | BUFG_PS/O | None | 10 | 0 | 9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | -| g5 | 8 | BUFGCE/O | None | 0 | 274 | 274 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | -| g7 | 14 | BUFGCE/O | None | 0 | 63 | 63 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0] | +| g0 | 23 | BUFG_GT/O | None | 52 | 0 | 52 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | +| g2 | 0 | BUFG_GT/O | None | 142 | 0 | 130 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | +| g4 | 12 | BUFG_PS/O | None | 50 | 0 | 50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +| g5+ | 8 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts +**** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. + + +21. Clock Region Cell Placement per Global Clock: Region X3Y1 +------------------------------------------------------------- + ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| g2 | 0 | BUFG_GT/O | None | 338 | 0 | 326 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | +| g5 | 8 | BUFGCE/O | None | 0 | 326 | 326 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts -23. Clock Region Cell Placement per Global Clock: Region X1Y2 +22. Clock Region Cell Placement per Global Clock: Region X1Y2 ------------------------------------------------------------- -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| g0 | 23 | BUFG_GT/O | None | 157 | 0 | 157 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | -| g2 | 0 | BUFG_GT/O | None | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | -| g4 | 12 | BUFG_PS/O | None | 1016 | 0 | 992 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ ++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ +| g0 | 23 | BUFG_GT/O | None | 244 | 0 | 244 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | +| g2 | 0 | BUFG_GT/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | +| g4 | 12 | BUFG_PS/O | None | 1241 | 0 | 1218 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | ++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts -24. Clock Region Cell Placement per Global Clock: Region X2Y2 +23. Clock Region Cell Placement per Global Clock: Region X2Y2 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| g0 | 23 | BUFG_GT/O | None | 5077 | 0 | 5077 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | -| g2 | 0 | BUFG_GT/O | None | 1929 | 0 | 1917 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | -| g4 | 12 | BUFG_PS/O | None | 420 | 0 | 420 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +| g0 | 23 | BUFG_GT/O | None | 334 | 0 | 334 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | +| g2 | 0 | BUFG_GT/O | None | 3305 | 0 | 3293 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | +| g4 | 12 | BUFG_PS/O | None | 18 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | g1+ | 18 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxusrclk_in[0] | | g3+ | 7 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txusrclk_in[0] | | g5+ | 8 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | -| g6 | 2 | BUFGCE/O | None | 0 | 1290 | 1290 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0] | -| g7 | 14 | BUFGCE/O | None | 0 | 306 | 306 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0] | +| g6 | 2 | BUFGCE/O | None | 0 | 119 | 119 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0] | +| g7 | 14 | BUFGCE/O | None | 0 | 907 | 907 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0] | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) @@ -575,112 +558,129 @@ All Modules **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. -25. Clock Region Cell Placement per Global Clock: Region X3Y2 +24. Clock Region Cell Placement per Global Clock: Region X3Y2 +------------------------------------------------------------- + ++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| g0 | 23 | BUFG_GT/O | None | 1473 | 0 | 1472 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | +| g2 | 0 | BUFG_GT/O | None | 3395 | 0 | 3378 | 4 | 12 | 0 | 0 | 1 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | +| g4 | 12 | BUFG_PS/O | None | 542 | 0 | 540 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +| g1 | 18 | BUFG_GT/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxusrclk_in[0] | +| g3 | 7 | BUFG_GT/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txusrclk_in[0] | +| g5 | 8 | BUFGCE/O | None | 0 | 833 | 833 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | +| g6 | 2 | BUFGCE/O | None | 0 | 190 | 190 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0] | +| g7 | 14 | BUFGCE/O | None | 0 | 245 | 245 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0] | ++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +25. Clock Region Cell Placement per Global Clock: Region X1Y3 +------------------------------------------------------------- + ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ +| g0 | 23 | BUFG_GT/O | None | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | +| g4 | 12 | BUFG_PS/O | None | 931 | 0 | 889 | 42 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +26. Clock Region Cell Placement per Global Clock: Region X2Y3 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| g0 | 23 | BUFG_GT/O | None | 1690 | 0 | 1688 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | -| g2 | 0 | BUFG_GT/O | None | 2237 | 0 | 2228 | 0 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | -| g4 | 12 | BUFG_PS/O | None | 198 | 0 | 197 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | -| g1 | 18 | BUFG_GT/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxusrclk_in[0] | -| g3 | 7 | BUFG_GT/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txusrclk_in[0] | -| g6 | 2 | BUFGCE/O | None | 0 | 297 | 297 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0] | -| g7 | 14 | BUFGCE/O | None | 0 | 604 | 604 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0] | +| g0 | 23 | BUFG_GT/O | None | 2283 | 0 | 2283 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | +| g2 | 0 | BUFG_GT/O | None | 8 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | +| g4 | 12 | BUFG_PS/O | None | 104 | 0 | 104 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +| g6 | 2 | BUFGCE/O | None | 0 | 637 | 637 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0] | +| g7+ | 14 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0] | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts +**** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. -26. Clock Region Cell Placement per Global Clock: Region X1Y3 +27. Clock Region Cell Placement per Global Clock: Region X3Y3 ------------------------------------------------------------- -+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| g0 | 23 | BUFG_GT/O | None | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | -| g4 | 12 | BUFG_PS/O | None | 1051 | 0 | 1010 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | -+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ ++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| g0 | 23 | BUFG_GT/O | None | 4278 | 0 | 4166 | 108 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | +| g2 | 0 | BUFG_GT/O | None | 10 | 0 | 2 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | +| g4 | 12 | BUFG_PS/O | None | 65 | 0 | 65 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +| g6 | 2 | BUFGCE/O | None | 0 | 734 | 734 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0] | ++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts -27. Clock Region Cell Placement per Global Clock: Region X2Y3 -------------------------------------------------------------- - -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| g0 | 23 | BUFG_GT/O | None | 899 | 0 | 819 | 74 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | -| g2 | 0 | BUFG_GT/O | None | 4 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | -| g4 | 12 | BUFG_PS/O | None | 6 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | -| g6 | 2 | BUFGCE/O | None | 0 | 65 | 65 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0] | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) -*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts - - -28. Clock Region Cell Placement per Global Clock: Region X3Y3 -------------------------------------------------------------- - -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| g0 | 23 | BUFG_GT/O | None | 725 | 0 | 692 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | -| g2 | 0 | BUFG_GT/O | None | 8 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | -| g6 | 2 | BUFGCE/O | None | 0 | 28 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0] | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) -*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts - - -29. Clock Region Cell Placement per Global Clock: Region X0Y4 +28. Clock Region Cell Placement per Global Clock: Region X0Y4 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ | g0 | 23 | BUFG_GT/O | None | 2 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | -| g4 | 12 | BUFG_PS/O | None | 2511 | 0 | 2492 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +| g4 | 12 | BUFG_PS/O | None | 2256 | 0 | 2237 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts -30. Clock Region Cell Placement per Global Clock: Region X1Y4 +29. Clock Region Cell Placement per Global Clock: Region X1Y4 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| g0 | 23 | BUFG_GT/O | None | 136 | 0 | 129 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | -| g4 | 12 | BUFG_PS/O | None | 179 | 0 | 177 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +| g0 | 23 | BUFG_GT/O | None | 137 | 0 | 129 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | +| g4 | 12 | BUFG_PS/O | None | 340 | 0 | 338 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts -31. Clock Region Cell Placement per Global Clock: Region X2Y4 +30. Clock Region Cell Placement per Global Clock: Region X2Y4 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| g0 | 23 | BUFG_GT/O | None | 81 | 0 | 71 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | +| g0 | 23 | BUFG_GT/O | None | 37 | 0 | 26 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts -32. Clock Region Cell Placement per Global Clock: Region X3Y4 +31. Clock Region Cell Placement per Global Clock: Region X3Y4 +------------------------------------------------------------- + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ +| g0 | 23 | BUFG_GT/O | None | 78 | 0 | 66 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +32. Clock Region Cell Placement per Global Clock: Region X0Y5 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ @@ -693,46 +693,33 @@ All Modules *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts -33. Clock Region Cell Placement per Global Clock: Region X0Y5 -------------------------------------------------------------- - -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| g0 | 23 | BUFG_GT/O | None | 8 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) -*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts - - -34. Clock Region Cell Placement per Global Clock: Region X1Y5 -------------------------------------------------------------- - -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| g0 | 23 | BUFG_GT/O | None | 45 | 0 | 36 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) -*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts - - -35. Clock Region Cell Placement per Global Clock: Region X2Y5 -------------------------------------------------------------- - -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -| g0 | 23 | BUFG_GT/O | None | 8 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) -*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts - - -36. Clock Region Cell Placement per Global Clock: Region X3Y5 +33. Clock Region Cell Placement per Global Clock: Region X1Y5 +------------------------------------------------------------- + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ +| g0 | 23 | BUFG_GT/O | None | 44 | 0 | 36 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +34. Clock Region Cell Placement per Global Clock: Region X2Y5 +------------------------------------------------------------- + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | URAM | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ +| g0 | 23 | BUFG_GT/O | None | 5 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +35. Clock Region Cell Placement per Global Clock: Region X3Y5 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+------+-----+----+------+-----+---------+---------------------------------------------------------------------+ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_control_sets_placed.rpt b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_control_sets_placed.rpt index 3fe3771..02b5d43 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_control_sets_placed.rpt +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_control_sets_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -| Date : Fri Oct 20 12:58:41 2023 +| Date : Fri Oct 20 19:45:59 2023 | Host : DESKTOP-5FH9OH3 running 64-bit major release (build 9200) | Command : report_control_sets -verbose -file pl_eth_10g_wrapper_control_sets_placed.rpt | Design : pl_eth_10g_wrapper @@ -23,11 +23,11 @@ Table of Contents +----------------------------------------------------------+-------+ | Status | Count | +----------------------------------------------------------+-------+ -| Total control sets | 1083 | -| Minimum number of control sets | 1083 | +| Total control sets | 1082 | +| Minimum number of control sets | 1082 | | Addition due to synthesis replication | 0 | | Addition due to physical synthesis replication | 0 | -| Unused register locations in slices containing registers | 1326 | +| Unused register locations in slices containing registers | 1314 | +----------------------------------------------------------+-------+ * Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers ** Run report_qor_suggestions for automated merging and remapping suggestions @@ -39,15 +39,15 @@ Table of Contents +--------------------+-------+ | Fanout | Count | +--------------------+-------+ -| Total control sets | 1083 | -| >= 0 to < 4 | 182 | -| >= 4 to < 6 | 124 | -| >= 6 to < 8 | 44 | -| >= 8 to < 10 | 122 | -| >= 10 to < 12 | 68 | +| Total control sets | 1082 | +| >= 0 to < 4 | 180 | +| >= 4 to < 6 | 123 | +| >= 6 to < 8 | 41 | +| >= 8 to < 10 | 120 | +| >= 10 to < 12 | 69 | | >= 12 to < 14 | 29 | -| >= 14 to < 16 | 21 | -| >= 16 | 493 | +| >= 14 to < 16 | 20 | +| >= 16 | 500 | +--------------------+-------+ * Control sets can be remapped at either synth_design or opt_design @@ -58,12 +58,12 @@ Table of Contents +--------------+-----------------------+------------------------+-----------------+--------------+ | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | +--------------+-----------------------+------------------------+-----------------+--------------+ -| No | No | No | 2854 | 817 | -| No | No | Yes | 322 | 86 | -| No | Yes | No | 6623 | 1737 | -| Yes | No | No | 10437 | 1832 | -| Yes | No | Yes | 225 | 36 | -| Yes | Yes | No | 7413 | 1681 | +| No | No | No | 2854 | 839 | +| No | No | Yes | 322 | 88 | +| No | Yes | No | 6624 | 1721 | +| Yes | No | No | 10444 | 1828 | +| Yes | No | Yes | 225 | 34 | +| Yes | Yes | No | 7421 | 1701 | +--------------+-----------------------+------------------------+-----------------+--------------+ @@ -73,1089 +73,1088 @@ Table of Contents +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+ | Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+ +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RESET_FLOP_WORD_ALIGNER/reset_flop_out | 1 | 1 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup4 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 1 | 1 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclkpcs_out[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[0]_i_1_n_0 | | 1 | 1 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclkpcs_out[0] | | | 1 | 1 | 1.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/push | | 1 | 1 | 1.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/p_1_in | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/m_payload_i[127]_i_1_n_0 | 1 | 1 | 1.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/r_push_r | | 1 | 1 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/core_gtwiz_userclk_rx_reset_in_0 | 1 | 1 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/core_gtwiz_userclk_tx_reset_in_0 | 1 | 1 | 1.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/bresp_push | | 1 | 1 | 1.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/r_push_r | | 1 | 1 | 1.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 1 | 1 | 1.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/p_1_in | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/m_payload_i[127]_i_1_n_0 | 1 | 1 | 1.00 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclkpcs_out[0] | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gen_gtwizard_gthe4.gtpowergood_int | 1 | 1 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RESET_FLOP_WORD_ALIGNER/reset_flop_out | 1 | 1 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/f | | 1 | 1 | 1.00 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/f | | 1 | 1 | 1.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/push | | 1 | 1 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/core_gtwiz_userclk_rx_reset_in_0 | 1 | 1 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclkpcs_out[0] | | | 1 | 1 | 1.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/push | | 1 | 1 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/core_gtwiz_userclk_tx_reset_in_0 | 1 | 1 | 1.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/push | | 1 | 1 | 1.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/push | | 1 | 1 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/f | | 1 | 1 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclkpcs_out[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[0]_i_1_n_0 | | 1 | 1 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_reg_STAT_TX_STATUS_REG1_clear_syncer/STAT_TX_STATUS_REG1_clear_cond | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/tx_reset_pulse_len_reg_n_0_[0] | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/b.b_pipe/p_1_in | | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/rst_d2 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/push | | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_ETH_FRAME_PARSER/compare | | 2 | 2 | 1.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.splitter_aw_si/m_ready_d[1]_i_1_n_0 | 2 | 2 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_FTYPE_PARSER/ena | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_FTP/reset_flop_out | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/b.b_pipe/p_1_in | | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/r.r_pipe/p_1_in_0 | | 2 | 2 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DELETE_FCS/sop_d2 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/cnt_read[1]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 2 | 2 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_flush_db2_reg | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/soft_reset_clr | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_pmtick_rx_clk_syncer/i_syncpls_clkin_rstsync/reset_pipe_out | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/cnt_read[1]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_ETH_FRAME_PARSER/compare | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_ETH_FRAME_PARSER/o_multicast_i_1_n_0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dic_r | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dic_r[1]_i_1_n_0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_d2 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/M_AXI_WREADY_I | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/grant_hot | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_arbiter.grant_hot[2]_i_1_n_0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/grant_hot | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/gen_arbiter.grant_hot[1]_i_1_n_0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg[0] | | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DELETE_FCS/tstamp_d2_nxt | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DELETE_FCS/reset_flop_out | 2 | 2 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdpp1_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/REG_HRD_RST/mm2s_soft_reset_done0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/si_register_slice_inst/ar.ar_pipe/aresetn_d_reg[0]_1 | 2 | 2 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/sig_advance_pipe_data36_out | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/sig_tlast_out | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/aresetn_d_reg[1]_1 | 2 | 2 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_fwft.rdpp1_inst/gen_fwft.count_en | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/SR[0] | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_RESET_SYNC/reset_pipe_out | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_ENCODER/reset_flop_out | 2 | 2 | 1.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_rep[0].fifoaddr[1]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RX_WD_ALIGN/align_status[0]_i_1_n_0 | | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_pipes_r_b | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/mty_qual_r[1]_i_1_n_0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/sig_flush_db10 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_pmtick_tx_clk_syncer/i_syncpls_clkin_rstsync/reset_pipe_out | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SYNC_PRIM2SEC_RST/sig_cmd_stat_rst_user | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/ar.ar_pipe/aresetn_d_reg[0]_1 | 2 | 2 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/i_RX_64B66B_CHECKER/FSM_sequential_rx_decoder_state_d3_no_ena_reg[1][0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DECODER/reset_flop_out | 2 | 2 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdpp1_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/decerr_slave_inst/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 2 | 2 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/GEN_ENABLE_INDET_BTT.sig_coelsc_reg_full_reg | | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/m_ready_d_reg[0][0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_pmtick_tx_clk_syncer/i_syncpls_clkout_rstsync/reset_pipe_out | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/load_s1 | | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/decerr_slave_inst/gen_axi.gen_write.s_axi_bvalid_i_reg_0[0] | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg_n_0_[1] | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_wren2_new | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/queue_empty2_new0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_advance_pipe_data36_out | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_12 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_arbiter.s_ready_i[2]_i_1_n_0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_ld_cmd | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_cmd_full0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_single_thread.accept_cnt[1]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/push | | 1 | 1 | 1.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/arvalid_d1_i_1_n_0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_wren_new | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/queue_empty_new0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.splitter_aw_si/m_ready_d[1]_i_1__0_n_0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_STATS/my_total_good_bytes_nxt | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_STATS/reset_flop_out | 2 | 2 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | | 1 | 2 | 2.00 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/sig_tstrb_fifo_rdy | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/ld_btt_cntr_reg10 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/i_RX_64B66B_CHECKER/ena_d2_reg_1[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/rx_decoder_state_d4 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/decerr_slave_inst/FSM_onehot_gen_read.r_state_reg[2][0] | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/register_slice_inst/ar.ar_pipe/aresetn_d_reg[1]_0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d2 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/stat_rx_remote_fault_i_1_n_0 | 2 | 2 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/rst_d2 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_wr_fifo | | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/M_AXI_WREADY_I | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 2 | 2 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_fwft.rdpp1_inst/gen_fwft.count_en | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/SR[0] | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_single_thread.accept_cnt[1]_i_1__0_n_0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/rst_d2 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/rst_d2 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/rfi_seq[1]_i_2_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/rfi_seq[1]_i_1_n_0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/FSM_onehot_gen_write.w_state_reg[1][0] | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/lfi_fault | | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/soft_reset_clr | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/r.r_pipe/p_1_in_0 | | 2 | 2 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 2 | 2 | 1.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/M_AXI_WREADY_I | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dic_r | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dic_r[1]_i_1_n_0 | 1 | 2 | 2.00 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/lfi_seq[1]_i_2_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/lfi_seq[1]_i_1_n_0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/aresetn_d_reg[0] | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.splitter_aw_si/m_ready_d[1]_i_1_n_0 | 2 | 2 | 1.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/gen_arbiter.s_ready_i[1]_i_1_n_0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/REG_HRD_RST/mm2s_soft_reset_done0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/lfi_fault | | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/load_s1 | | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/cnt_read[1]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/rst_d2 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/si_register_slice_inst/ar.ar_pipe/aresetn_d_reg[0]_1 | 2 | 2 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/aresetn_d_reg[1]_1 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_reg_STAT_TX_STATUS_REG1_clear_syncer/STAT_TX_STATUS_REG1_clear_cond | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/tx_reset_pulse_len_reg_n_0_[0] | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_wren2_new | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/queue_empty2_new0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/rst_d2 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d2 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/stat_rx_remote_fault_i_1_n_0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_wr_fifo | | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_d2 | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_FTYPE_PARSER/ena | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_FTP/reset_flop_out | 2 | 2 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DELETE_FCS/tstamp_d2_nxt | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DELETE_FCS/reset_flop_out | 2 | 2 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_fwft.rdpp1_inst/gen_fwft.count_en | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/SR[0] | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_pmtick_rx_clk_syncer/i_syncpls_clkin_rstsync/reset_pipe_out | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_wren_new | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/queue_empty_new0 | 1 | 2 | 2.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_pmtick_rx_clk_syncer/i_syncpls_clkout_rstsync/reset_pipe_out | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/b.b_pipe/p_1_in | | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_fwft.rdpp1_inst/gen_fwft.count_en | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/SR[0] | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/rst_d2 | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.splitter_aw_si/m_ready_d[1]_i_1_n_0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/cnt_read[1]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/aresetn_d_reg[0] | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_pmtick_tx_clk_syncer/i_syncpls_clkout_rstsync/reset_pipe_out | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/b.b_pipe/p_1_in | | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/updt_sts_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts_queue_empty0 | 2 | 2 | 1.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/rst_d2 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/sig_flush_db10 | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/updt_data_reg_1[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/ptr_queue_empty0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/decerr_slave_inst/FSM_onehot_gen_read.r_state_reg[2][0] | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/register_slice_inst/ar.ar_pipe/aresetn_d_reg[1]_0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts2_rden | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/follower_full_s2mm0 | 2 | 2 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_STATS/my_total_good_bytes_nxt | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_STATS/reset_flop_out | 1 | 2 | 2.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/splitter_aw_mi/m_ready_d[1]_i_1__1_n_0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SYNC_PRIM2SEC_RST/sig_cmd_stat_rst_user | 2 | 2 | 1.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.splitter_aw_si/m_ready_d[1]_i_1__0_n_0 | 2 | 2 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/rfi_seq[1]_i_2_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/rfi_seq[1]_i_1_n_0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.splitter_aw_si/m_ready_d[1]_i_1_n_0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_arbiter.s_ready_i[2]_i_1_n_0 | 1 | 2 | 2.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sel | | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/GEN_DESC_UPDT_QUEUE.updt_sts_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts2_queue_empty0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/updt_data_reg_1[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/ptr2_queue_empty0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/updt_sts_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts_queue_empty0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/out | 2 | 2 | 1.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/updt_data_reg_1[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/ptr_queue_empty0 | 2 | 2 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_pmtick_tx_clk_syncer/i_syncpls_clkin_rstsync/reset_pipe_out | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_ld_cmd | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_cmd_full0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/gen_arbiter.s_ready_i[1]_i_1_n_0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/out | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/ar.ar_pipe/aresetn_d_reg[0]_1 | 2 | 2 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_pipes_r_b | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/mty_qual_r[1]_i_1_n_0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RX_WD_ALIGN/align_status[0]_i_1_n_0 | | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SYNC_PRIM2SEC_RST/sig_cmd_stat_rst_user | 2 | 2 | 1.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts_rden | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/follower_full_mm2s0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts2_rden | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/follower_full_s2mm0 | 1 | 2 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_gt_rx_reset_r_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 2 | 2 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 2 | 3 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_ETH_FRAME_PARSER/cycles[3]_i_2_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_FCS/SR[0] | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_0[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AS[0] | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 2 | 3 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rx_serdes_resetdone_0/rx_serdes_reset | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_calc2_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_strbgen_bytes_ireg2[2]_i_1_n_0 | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 3 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_TX_RESET_BUFFER/reset_flop_out | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/decerr_slave_inst/gen_axi.gen_write.s_axi_bvalid_i_reg_0[0] | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg_n_0_[1] | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/M_AXI_WREADY_I | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SYNC_PRIM2SEC_RST/sig_cmd_stat_rst_user | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DELETE_FCS/sop_d2 | 2 | 2 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdpp1_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/updt_data_reg_1[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/ptr2_queue_empty0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_ETH_FRAME_PARSER/compare | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_ETH_FRAME_PARSER/o_multicast_i_1_n_0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg[0] | | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_ETH_FRAME_PARSER/compare | | 2 | 2 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/i_RX_64B66B_CHECKER/ena_d2_reg_1[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/rx_decoder_state_d4 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/i_RX_64B66B_CHECKER/FSM_sequential_rx_decoder_state_d3_no_ena_reg[1][0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DECODER/reset_flop_out | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/GEN_DESC_UPDT_QUEUE.updt_sts_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts2_queue_empty0 | 2 | 2 | 1.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_gt_rx_reset_r_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_rep[0].fifoaddr[1]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/push | | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_RESET_SYNC/reset_pipe_out | 2 | 2 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_ENCODER/reset_flop_out | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_single_thread.accept_cnt[1]_i_1__0_n_0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_single_thread.accept_cnt[1]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/m_ready_d_reg[0][0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/sig_advance_pipe_data36_out | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/sig_tlast_out | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/grant_hot | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_arbiter.grant_hot[2]_i_1_n_0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdpp1_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/grant_hot | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/gen_arbiter.grant_hot[1]_i_1_n_0 | 1 | 2 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_advance_pipe_data36_out | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_14 | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/decerr_slave_inst/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 2 | 2 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_flush_db2_reg | 1 | 2 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/FSM_onehot_gen_write.w_state_reg[1][0] | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 1 | 2 | 2.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff[1] | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_3[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 3 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_4[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_1[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 3 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_2[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 3 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_6[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 3 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_5[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 3 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_8[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 3 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_7[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 3 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/decerr_slave_inst/FSM_onehot_gen_axi.gen_write.write_cs[2]_i_2_n_0 | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg_n_0_[1] | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/sig_addr_posted_cntr[2]_i_1__0_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/decerr_slave_inst/s_axi_rvalid | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RD_STATUS_CNTLR/sig_coelsc_tag_reg1 | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/sent_pause_class_nxt1 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/word_counter[2]_i_1_n_0 | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_rr_reg_9[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/shift_ptr_p4_r[2]_i_1_n_0 | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_wr_fifo | | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/aresetn_d_reg_n_0_[0] | 3 | 3 | 1.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_decerr_slave.decerr_slave_inst/FSM_onehot_gen_axi.write_cs[2]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/sig_addr_posted_cntr[2]_i_1__2_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_RX_RESET_BUFFER/reset_flop_out | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/aresetn_d_reg[1]_1 | 3 | 3 | 1.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_AXI_RESET_TX_SYNC/reset_pipe_out | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_RX_RESET_BUFFER/reset_flop_out | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_TX_RESET_BUFFER/reset_flop_out | 1 | 3 | 3.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff[1] | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/decerr_slave_inst/FSM_onehot_gen_axi.gen_write.write_cs[2]_i_2_n_0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/gtwiz_reset_tx_any_sync | 2 | 3 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_tx_resetdone_0/tx_reset | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/SR[0] | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 2 | 3 | 1.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_addr_posted_cntr[2]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_fifo_mssai0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/sig_eop_sent_reg_reg_0[0] | 2 | 3 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_ld_cmd | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/SR[0] | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_ld_cmd | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/sig_eop_sent_reg_reg[0] | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff[1] | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/register_slice_inst/ar.ar_pipe/aresetn_d_reg[1]_0 | 3 | 3 | 1.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff[1] | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_STATS/stat_tx_total_bytes[2]_i_1_n_0 | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/sig_cntl_accept | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/tx_reset_out_reg_0[0] | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/gen_no_arbiter.m_target_hot_i[3]_i_1_n_0 | | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_no_arbiter.m_target_hot_i[3]_i_1__0_n_0 | | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_decerr_slave.decerr_slave_inst/FSM_onehot_gen_axi.write_cs[2]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_rep[0].fifoaddr[2]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RD_STATUS_CNTLR/E[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DELETE_FCS/tstamp_d2_nxt | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_FCS/reset_flop_out_reg[0] | 2 | 3 | 1.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/E[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 2 | 3 | 1.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/GEN_FOR_ASYNC.REG_TO_SECONDARY/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/out | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/E[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_SG/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/aresetn_d_reg_n_0_[0] | 3 | 3 | 1.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/aresetn_d_reg[1]_1 | 3 | 3 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_LBUS_FIFO/i_FIFO_WADDR_GRAY_SYNC/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_RESET_SYNC/SR[0] | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_TX_RESET_BUFFER/reset_flop_out | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/decerr_slave_inst/FSM_onehot_gen_axi.gen_write.write_cs[2]_i_2_n_0 | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg_n_0_[1] | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_ETH_FRAME_PARSER/cycles[3]_i_2_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_FCS/SR[0] | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AS[0] | 1 | 3 | 3.00 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/rx_serdes_reset_out_reg[0]_0[0] | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_AXI_RESET_RX_SYNC/reset_pipe_out_0 | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_RESET_SERDES_SYNC/reset_pipe_out | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DELETE_FCS/tstamp_d2_nxt | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_FCS/reset_flop_out_reg[0] | 2 | 3 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/tx_reset_out_reg_0[0] | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_tx_resetdone_0/tx_reset | 1 | 3 | 3.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/desc_update_done_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_SG/GEN_ASYNC_RESET.scndry_resetn_reg[0] | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff[1] | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_rx_force_resync | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/gtwiz_reset_rx_any_sync | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtpowergood_inst/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/gtwiz_reset_all_sync | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_userclk_tx_active_inst/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/gtwiz_reset_tx_any_sync | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 2 | 3 | 1.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/E[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_SG/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/sig_addr_posted_cntr[2]_i_1__0_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/GEN_FOR_ASYNC.REG_TO_SECONDARY/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/out | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RD_STATUS_CNTLR/E[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_wr_fifo | | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_addr_posted_cntr[2]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/E[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 2 | 3 | 1.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_AXI_RESET_RX_SYNC/reset_pipe_out_0 | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_rx_timer_ctr0_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_rx_timer_clr_reg_n_0 | 1 | 3 | 3.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/p_0_in | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_tx_timer_clr_reg_n_0 | 1 | 3 | 3.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_all_timer_ctr0_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_all_timer_clr_reg_n_0 | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_rx_timer_ctr0_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_rx_timer_clr_reg_n_0 | 1 | 3 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_LBUS_FIFO/i_FIFO_WADDR_GRAY_SYNC/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_RESET_SYNC/SR[0] | 1 | 3 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_gt_reset_all_r_i_1_n_0 | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/last_rr_hot | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/r.r_pipe/aresetn_d_reg[1]_0 | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/aresetn_d_reg[0]_1 | 4 | 4 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_rr_reg_9[0] | | 3 | 4 | 1.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_ld_cmd | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/sig_eop_sent_reg_reg_0[0] | 3 | 4 | 1.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d2 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DECODER/reset_flop_out | 3 | 4 | 1.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 | 2 | 4 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RX_WD_ALIGN/delay_after_bitslip[3]_i_1_n_0 | | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/gen_arbiter.s_ready_i_reg[1]_0[1] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/SS[0] | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/m_ready_d_reg[0]_0[0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_ctl0_p5_r_reg[2]_2 | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/gtwiz_reset_all_sync | 1 | 4 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/syncer_reset_from_Bus2IP_clk_to_tx_clk/reset_pipe_out | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/SS[0] | 2 | 4 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/INCLUDE_DRE_CNTL.I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_cmd2dre_valid_reg | | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0]_1[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/gen_arbiter.s_ready_i_reg[1]_0[0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 3 | 4 | 1.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/aresetn_d_reg_n_0_[1] | 4 | 4 | 1.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/sig_token_cntr[3]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | 1 | 4 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup2 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/b.b_pipe/aresetn_d_reg[0]_0 | 3 | 4 | 1.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/syncer_reset_from_tx_clk_to_Bus2IP_clk/reset_pipe_out | 1 | 4 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 | 1 | 4 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/gen_master_slots[1].r_issuing_cnt_reg[10][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_ENCODER/enaout_reg_0[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_SCRAMBLER/reset_flop_out | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/gen_master_slots[0].r_issuing_cnt_reg[2][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_master_slots[0].w_issuing_cnt_reg[2][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.async_conv_reset_n | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_master_slots[1].w_issuing_cnt_reg[10][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/m_valid_i | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/SS[0] | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.accept_cnt_reg[1][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0]_6[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0]_0[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0]_4[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0]_2[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0]_3[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0]_5[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/last_rr_hot | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_calc2_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_strbgen_bytes_ireg2[2]_i_1_n_0 | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_userclk_tx_active_inst/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/gtwiz_reset_tx_any_sync | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtpowergood_inst/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/gtwiz_reset_all_sync | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/gtwiz_reset_rx_any_sync | 2 | 3 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_3[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_1[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 3 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_2[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 3 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_0[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 3 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_5[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 3 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_6[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 3 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_7[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 3 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_4[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 3 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/FSM_sequential_pause_pkt_state_8[2]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 3 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/sent_pause_class_nxt1 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/word_counter[2]_i_1_n_0 | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_rep[0].fifoaddr[2]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 3 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_rr_reg_9[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/shift_ptr_p4_r[2]_i_1_n_0 | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rx_serdes_resetdone_0/rx_serdes_reset | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_fifo_mssai0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/sig_eop_sent_reg_reg_0[0] | 2 | 3 | 1.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_decerr_slave.decerr_slave_inst/FSM_onehot_gen_axi.write_cs[2]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 2 | 3 | 1.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_no_arbiter.m_target_hot_i[3]_i_1__0_n_0 | | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/gen_no_arbiter.m_target_hot_i[3]_i_1_n_0 | | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/sig_addr_posted_cntr[2]_i_1__2_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_ld_cmd | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/SR[0] | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_ld_cmd | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/sig_eop_sent_reg_reg[0] | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_RESET_SERDES_SYNC/reset_pipe_out | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_STATS/stat_tx_total_bytes[2]_i_1_n_0 | 2 | 3 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/register_slice_inst/ar.ar_pipe/aresetn_d_reg[1]_0 | 3 | 3 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff[1] | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_decerr_slave.decerr_slave_inst/FSM_onehot_gen_axi.write_cs[2]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/gtwiz_reset_tx_any_sync | 2 | 3 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff[1] | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/sig_cntl_accept | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_TX_RESET_BUFFER/reset_flop_out | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_RX_RESET_BUFFER/reset_flop_out | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_rx_force_resync | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/decerr_slave_inst/s_axi_rvalid | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RD_STATUS_CNTLR/sig_coelsc_tag_reg1 | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_AXI_RESET_TX_SYNC/reset_pipe_out | 1 | 3 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_RX_RESET_BUFFER/reset_flop_out | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/decerr_slave_inst/FSM_onehot_gen_axi.gen_write.write_cs[2]_i_2_n_0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff[1] | 1 | 3 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/b.b_pipe/m_valid_i_reg_inv_0[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RX_WD_ALIGN/delay_after_bitslip[3]_i_1_n_0 | | 1 | 4 | 4.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.accept_cnt_reg[1][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[3][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[11][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[51][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[19][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[35][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[27][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[59][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[43][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg_n_0_[1] | 2 | 4 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RX_WD_ALIGN/sh_invalid_cnt | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RX_WD_ALIGN/sh_invalid_cnt[3]_i_1_n_0 | 1 | 4 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d1 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/i_RX_64B66B_CHECKER/start_block_i_1_n_0 | 4 | 4 | 1.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/m_valid_i | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1 | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/r.r_pipe/E[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/b.b_pipe/m_valid_i_reg_inv_0[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_STATS/stat_rx_unicast_i_1_n_0 | 1 | 4 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/aresetn_d_reg_n_0_[1] | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_push_to_wsc_i_2_n_0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_push_to_wsc0 | 1 | 4 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d2 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/rx_decoder_state_d4 | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/gtwiz_reset_rx_any_sync | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG3_WREADY/GEN_ASYNC_WRITE.rdy_back_reg | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/aresetn_d_reg[0]_1 | 3 | 4 | 1.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/m_valid_i | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/SS[0] | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_rep[0].fifoaddr[3]_i_1__0_n_0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.splitter_aw_si/m_ready_d_reg[0]_0[0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/b.b_pipe/m_valid_i_reg_inv_0 | | 2 | 4 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.async_conv_reset_n | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.splitter_aw_si/E[0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/rx_serdes_reset_r[0]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 3 | 4 | 1.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/preambleout[55]_i_1_n_0 | | 3 | 4 | 1.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/b.b_pipe/aresetn_d_reg[0]_0 | 4 | 4 | 1.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/last_rr_hot | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0]_5[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0]_6[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/r.r_pipe/aresetn_d_reg[1]_0 | 4 | 4 | 1.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0]_2[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0]_0[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0]_1[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0]_4[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_no_arbiter.s_ready_i_reg[0]_3[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/aresetn_d_reg[0]_1 | 2 | 4 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_ENCODER/enaout_reg_0[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_SCRAMBLER/reset_flop_out | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.accept_cnt_reg[1][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/sig_token_cntr[3]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | 1 | 4 | 4.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/E[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/sig_data2mstr_cmd_ready | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_clr_dqual_reg | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_master_slots[0].w_issuing_cnt_reg[2][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_master_slots[1].w_issuing_cnt_reg[10][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/rx_serdes_reset_r[0]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/gen_master_slots[0].r_issuing_cnt_reg[2][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/gen_master_slots[1].r_issuing_cnt_reg[10][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/INCLUDE_DRE_CNTL.I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_cmd2dre_valid_reg | | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/aresetn_d_reg_n_0_[1] | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/en_wr_slverr_indication_r_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 3 | 4 | 1.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/aresetn_d_reg_n_0_[1] | 3 | 4 | 1.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/aresetn_d_reg[0]_1 | 3 | 4 | 1.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_dre_tvalid_i_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_13[0] | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.async_conv_reset_n | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_gt_reset_all_r_i_1_n_0 | 3 | 4 | 1.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/syncer_reset_from_tx_clk_to_Bus2IP_clk/reset_pipe_out | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/gtwiz_reset_rx_any_sync | 2 | 4 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/gtwiz_reset_all_sync | 1 | 4 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.async_conv_reset_n | 1 | 4 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg_n_0_[1] | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[43][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_ctl0_p5_r_reg[2]_2 | 2 | 4 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_STATS/stat_rx_unicast_i_1_n_0 | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/b.b_pipe/m_valid_i_reg_inv_0 | | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_rep[0].fifoaddr[3]_i_1__0_n_0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/m_valid_i | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/SS[0] | 2 | 4 | 2.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.awvalid_d1_i_1_n_0 | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/sig_data2mstr_cmd_ready | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_clr_dqual_reg | 3 | 4 | 1.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/E[0] | | 3 | 4 | 1.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/en_wr_slverr_indication_r_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 1 | 4 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gtwiz_reset_rx_pll_and_datapath_int_reg_n_0 | 1 | 5 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_txprogdivreset_inst/rst_in0 | 1 | 5 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_LBUS_FIFO/reset_flop_out | 1 | 5 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_axi_ctl_gt_tx_reset_0/gtwiz_reset_tx_datapath_in[0] | 1 | 5 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_axi_gt_resetall_0/gtwiz_reset_all_in[0] | 1 | 5 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_i_1__0_n_0 | 1 | 5 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_ADDR.addr_q | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_tx_resetdone_0/user_tx_reset_0 | 4 | 5 | 1.25 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/E[0] | | 1 | 5 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 | 1 | 4 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d2 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DECODER/reset_flop_out | 3 | 4 | 1.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG3_WREADY/GEN_ASYNC_WRITE.rdy_back_reg | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_push_to_wsc_i_2_n_0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_push_to_wsc0 | 1 | 4 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | 2 | 4 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_ld_cmd | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/sig_eop_sent_reg_reg_0[0] | 3 | 4 | 1.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/m_valid_i | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/SS[0] | 1 | 4 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 | 1 | 4 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d2 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/rx_decoder_state_d4 | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/SS[0] | 1 | 4 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.wdata_router_w/wrouter_aw_fifo/SS[0] | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/m_valid_i | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1 | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.splitter_aw_si/m_ready_d_reg[0]_0[0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.splitter_aw_si/E[0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/r.r_pipe/E[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d1 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/i_RX_64B66B_CHECKER/start_block_i_1_n_0 | 3 | 4 | 1.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/preambleout[55]_i_1_n_0 | | 3 | 4 | 1.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/m_ready_d_reg[0]_0[0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[11][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[35][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[59][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/gen_arbiter.s_ready_i_reg[1]_0[0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 3 | 4 | 1.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[27][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/gen_arbiter.s_ready_i_reg[1]_0[1] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 3 | 4 | 1.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[19][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RX_WD_ALIGN/sh_invalid_cnt | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RX_WD_ALIGN/sh_invalid_cnt[3]_i_1_n_0 | 1 | 4 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/E[0] | | 2 | 4 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/syncer_reset_from_Bus2IP_clk_to_tx_clk/reset_pipe_out | 1 | 4 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[3][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_rr_reg_9[0] | | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/gen_multi_thread.active_cnt_reg[51][0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 4 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/last_rr_hot | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 4 | 4.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 1 | 5 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/gtwiz_reset_tx_any | 1 | 5 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup3 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 2 | 5 | 2.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/EXT_LPF/lpf_int | 1 | 5 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in0_0 | 1 | 5 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 3 | 5 | 1.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_ADDR.addr_q | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 1 | 5 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclkpcs_out[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gen_gtwizard_gthe4.gtpowergood_int | 1 | 5 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 2 | 5 | 2.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.splitter_aw_si/E[0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 5 | 2.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_ENCODER/dataout0[63]_i_1_n_0 | 3 | 5 | 1.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_read.si_transactor_ar/gen_single_thread.accept_cnt[4]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 5 | 2.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RD_DATA_CNTL/sig_push_rd_sts_reg | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_sts_tag_reg0 | 1 | 5 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_out_i_1_n_0 | 1 | 5 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 2 | 5 | 2.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/grant_hot | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 5 | 2.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/cnt_read[4]_i_1__0_n_0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 1 | 5 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/cnt_read[4]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 1 | 5 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/E[0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 5 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/stat_rx_bad_preamble_i_1_n_0 | 3 | 5 | 1.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/grant_hot | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 5 | 2.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/E[0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 5 | 2.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_ADDR.addr_q | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 2 | 5 | 2.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_ADDR.addr_q | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 1 | 5 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/REG_HRD_RST/scndry_out | 3 | 5 | 1.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/E[0] | | 1 | 5 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/cnt_read[4]_i_1__0_n_0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 2 | 5 | 2.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/cnt_read[4]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 2 | 5 | 2.50 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/E[0] | | 2 | 5 | 2.50 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 1 | 5 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/cnt_read[4]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 2 | 5 | 2.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/cnt_read[4]_i_1__0_n_0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 2 | 5 | 2.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_ENCODER/dataout0[63]_i_1_n_0 | 4 | 5 | 1.25 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/cnt_read[4]_i_1__0_n_0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 1 | 5 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/cnt_read[4]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 1 | 5 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RD_DATA_CNTL/sig_push_rd_sts_reg | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_sts_tag_reg0 | 1 | 5 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 3 | 5 | 1.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_out_i_1_n_0 | 1 | 5 | 5.00 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 5 | 2.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 | 1 | 5 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 3 | 5 | 1.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_i_1__0_n_0 | 1 | 5 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 2 | 5 | 2.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_ADDR.addr_q | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 2 | 5 | 2.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclkpcs_out[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gen_gtwizard_gthe4.gtpowergood_int | 1 | 5 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 3 | 5 | 1.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/EXT_LPF/lpf_int | 2 | 5 | 2.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 2 | 5 | 2.50 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/gtwiz_reset_rx_any | 1 | 5 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DELETE_FCS/reset_flop_out | 4 | 5 | 1.25 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/cmd_b_push_block_reg_0[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 1 | 6 | 6.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/sig_addr_valid_reg_reg[0] | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 2 | 6 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in0_0 | 1 | 5 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/gtwiz_reset_tx_any | 1 | 5 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_txprogdivreset_inst/rst_in0 | 1 | 5 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gtwiz_reset_rx_pll_and_datapath_int_reg_n_0 | 1 | 5 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 | 1 | 5 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_axi_ctl_gt_tx_reset_0/gtwiz_reset_tx_datapath_in[0] | 1 | 5 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_axi_gt_resetall_0/gtwiz_reset_all_in[0] | 1 | 5 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/REG_HRD_RST/scndry_out | 3 | 5 | 1.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/grant_hot | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 5 | 2.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/E[0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 5 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/stat_rx_bad_preamble_i_1_n_0 | 2 | 5 | 2.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/E[0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 5 | 2.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_ADDR.addr_q | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_tx_resetdone_0/user_tx_reset_0 | 2 | 5 | 2.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DELETE_FCS/reset_flop_out | 2 | 5 | 2.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/grant_hot | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 5 | 2.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_LBUS_FIFO/reset_flop_out | 1 | 5 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_read.si_transactor_ar/gen_single_thread.accept_cnt[4]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 5 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[2].gen_si_write.splitter_aw_si/E[0] | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 1 | 5 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_ADDR.addr_q | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 1 | 5 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_ADDR.addr_q | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 2 | 5 | 2.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_push_coelsc_reg | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_coelsc_tag_reg0 | 1 | 6 | 6.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 4 | 6 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/rx_reset | 2 | 6 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_push_input_reg11_out | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_input_cache_type_reg0 | 1 | 6 | 6.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/cmd_b_push_block_reg_0[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 2 | 6 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_ready_i_reg[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 5 | 6 | 1.20 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/gen_write.w_cnt[5]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg_n_0_[1] | 2 | 6 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/gen_write.w_cnt[5]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 3 | 6 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/sig_addr_valid_reg_reg[0] | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 2 | 6 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/register_slice_inst/aw.aw_pipe/s_ready_i_reg_0[0] | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg_n_0_[1] | 2 | 6 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 3 | 6 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/ar.ar_pipe/mm2s_rready_reg[0] | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 2 | 6 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/cmd_push_block_reg_0[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 2 | 6 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/E[0] | | 6 | 6 | 1.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_csm_pop_child_cmd | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 3 | 6 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/syncer_reset_from_rx_clk_to_Bus2IP_clk/reset_pipe_out | 1 | 6 | 6.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/sig_m_valid_dup_i_1_n_0 | 3 | 6 | 2.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/SEQ/seq_cnt_en | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/SEQ/seq_clr | 1 | 6 | 6.00 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RX_WD_ALIGN/sh_cnt0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RESET_FLOP_WORD_ALIGNER/SR[0] | 1 | 6 | 6.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/gen_write.w_cnt[5]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 2 | 6 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/cmd_push_block_reg_0[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 1 | 6 | 6.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/E[0] | | 4 | 6 | 1.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 4 | 6 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/counter_msb[23]_i_1__18_n_0 | 1 | 6 | 6.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/cmd_b_push_block_reg_0[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 1 | 6 | 6.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_ready_i_reg[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 4 | 6 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/register_slice_inst/aw.aw_pipe/s_ready_i_reg_0[0] | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg_n_0_[1] | 2 | 6 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/gen_write.w_cnt[5]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg_n_0_[1] | 2 | 6 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_csm_pop_child_cmd | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/areset_d_reg_n_0_[0] | 3 | 6 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/cmd_push_block_reg_0[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 1 | 6 | 6.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_push_input_reg11_out | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_input_cache_type_reg0 | 1 | 6 | 6.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/rx_reset | 2 | 6 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_push_coelsc_reg | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_coelsc_tag_reg0 | 2 | 6 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/sig_m_valid_dup_i_1_n_0 | 4 | 6 | 1.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/syncer_reset_from_rx_clk_to_Bus2IP_clk/reset_pipe_out | 1 | 6 | 6.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.async_conv_reset_n | 2 | 6 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/ar.ar_pipe/mm2s_rready_reg[0] | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 2 | 6 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d1 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DECODER/reset_flop_out | 5 | 6 | 1.20 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/syncer_reset_from_Bus2IP_clk_to_rx_clk/reset_pipe_out | 2 | 6 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/register_slice_inst/ar.ar_pipe/s_ready_i_reg_0[0] | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/register_slice_inst/ar.ar_pipe/aresetn_d_reg[1]_0 | 2 | 6 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d1 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DECODER/reset_flop_out | 4 | 6 | 1.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/cmd_b_push_block_reg_0[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 2 | 6 | 3.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.async_conv_reset_n | 2 | 6 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.REG_RESET_OUT/scndry_out | 2 | 7 | 3.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_ASYNC_RESET.REG_RESET_OUT/scndry_out | 2 | 7 | 3.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/syncer_reset_from_Bus2IP_clk_to_rx_clk/reset_pipe_out | 2 | 6 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/cmd_push_block_reg_0[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 2 | 6 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.async_conv_reset_n | 3 | 6 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/register_slice_inst/ar.ar_pipe/s_ready_i_reg_0[0] | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/register_slice_inst/ar.ar_pipe/aresetn_d_reg[1]_0 | 1 | 6 | 6.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d2 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/lfi | 4 | 7 | 1.75 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/cmd_translator_0/incr_cmd_0/axaddr_incr[6]_i_1__0_n_0 | | 4 | 7 | 1.75 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 5 | 7 | 1.40 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/FSM_sequential_state_reg[0]_1[0] | | 5 | 7 | 1.40 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_ENCODER/ctl_tx_test_pattern_enable_out_reg[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_SCRAMBLER/reset_flop_out | 2 | 7 | 3.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 3 | 7 | 2.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 7 | 2.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/counter_msb[23]_i_1__2_n_0 | 2 | 7 | 3.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.REG_RESET_OUT/scndry_out | 2 | 7 | 3.50 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/sig_push_coelsc_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/sig_coelsc_tag_reg0 | 2 | 7 | 3.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/cmd_translator_0/incr_cmd_0/axaddr_incr[6]_i_1__0_n_0 | | 2 | 7 | 3.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d2 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/lfi | 2 | 7 | 3.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/sig_set_push2wsc | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/sig_push_to_wsc_i_1__0_n_0 | 1 | 7 | 7.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_ENCODER/ctl_tx_test_pattern_enable_out_reg[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_SCRAMBLER/reset_flop_out | 2 | 7 | 3.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclkpcs_out[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4] | 1 | 7 | 7.00 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_HI_BER_MONITOR/framing_error_cnt[6]_i_2_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_HI_BER_MONITOR/framing_error_cnt[6]_i_1_n_0 | 2 | 7 | 3.50 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/test_ena | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DESCR/SR[0] | 2 | 7 | 3.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/sig_shift_case_reg0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | 3 | 7 | 2.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 5 | 7 | 1.40 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclkpcs_out[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4] | 1 | 7 | 7.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 2 | 7 | 3.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_clr_dbc_reg_reg[0] | 2 | 7 | 3.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/counter_msb[23]_i_1__10_n_0 | 1 | 7 | 7.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/sig_shift_case_reg0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | 1 | 7 | 7.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/sig_set_push2wsc | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/sig_push_to_wsc_i_1__0_n_0 | 1 | 7 | 7.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GEN_ASYNC_RESET.REG_RESET_OUT/scndry_out | 3 | 7 | 2.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | 3 | 8 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 8 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/sig_push_rd_sts_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/sig_rd_sts_tag_reg0 | 4 | 8 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[9][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 4 | 8 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[7].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 1 | 8 | 8.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/b.b_pipe/aresetn_d_reg[0]_0 | 3 | 8 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 2 | 8 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 2 | 8 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_rr | 3 | 8 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 3 | 8 | 2.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/b.b_pipe/aresetn_d_reg[1]_0 | 3 | 8 | 2.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[8][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 8 | 2.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[11][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 4 | 8 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[5].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[111]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 3 | 8 | 2.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[6][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 2 | 8 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[4][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 8 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/col_cnt[7]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DECODER/reset_flop_out | 5 | 8 | 1.60 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[5][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 4 | 8 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[6].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 2 | 8 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[7].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_2_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 1 | 8 | 8.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[79]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 3 | 8 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[4].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 2 | 8 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup3 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 2 | 8 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[5].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 2 | 8 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[7][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 4 | 8 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[6].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[119]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 2 | 8 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 2 | 8 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[4].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[103]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 3 | 8 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/parity_valid_pipe[0][7]_i_1_n_0 | 3 | 8 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/decerr_slave_inst/gen_axi.gen_read.read_cnt[7]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/register_slice_inst/ar.ar_pipe/aresetn_d_reg[1]_0 | 2 | 8 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[95]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 2 | 8 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GEN_INDET_BTT.lsig_end_of_cmd_reg_reg[1] | 1 | 8 | 8.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/decerr_slave_inst/s_axi_rvalid | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_2[0] | 3 | 8 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 1 | 8 | 8.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 1 | 8 | 8.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GEN_INDET_BTT.lsig_end_of_cmd_reg_reg[0] | 1 | 8 | 8.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_decerr_slave.decerr_slave_inst/gen_axi.read_cnt[7]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 3 | 8 | 2.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/irqthresh_wren_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 3 | 8 | 2.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/irqthresh_wren_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 2 | 8 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[2] | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK1/GEN_ASYNC_WRITE.axi2ip_wrce_reg[12][0] | 2 | 8 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[0] | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK1/GEN_ASYNC_WRITE.axi2ip_wrce_reg[0][0] | 1 | 8 | 8.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[87]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 3 | 8 | 2.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_dbeat_cntr[7]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 2 | 8 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/irqdelay_wren_reg_0[0] | 1 | 8 | 8.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/irqdelay_wren_reg_0[0] | 2 | 8 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 1 | 8 | 8.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[71]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 3 | 8 | 2.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 1 | 8 | 8.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 1 | 8 | 8.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RX_WD_ALIGN/bitslip_counter | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RX_WD_ALIGN/bitslip_counter[7]_i_1_n_0 | 2 | 8 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_decerr_slave.decerr_slave_inst/gen_axi.read_cnt[7]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 8 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 8 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/sig_dbeat_cntr[7]_i_1__1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 2 | 8 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 8 | 2.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/mhandshake_r | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/SR[0] | 2 | 8 | 4.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/b_push | | 1 | 8 | 8.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 3 | 8 | 2.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/s_ready_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/pushed_commands[7]_i_1__0_n_0 | 2 | 8 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_ready_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/pushed_commands[7]_i_1_n_0 | 2 | 8 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/mhandshake_r | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/SR[0] | 2 | 8 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/b_push | | 1 | 8 | 8.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/s_ready_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/pushed_commands[7]_i_1__0_n_0 | 3 | 8 | 2.67 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_ready_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/pushed_commands[7]_i_1_n_0 | 2 | 8 | 4.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 1 | 8 | 8.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 8 | 2.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/mhandshake_r | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/SR[0] | 2 | 8 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 5 | 8 | 1.60 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 8 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 2 | 8 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/decerr_slave_inst/gen_axi.gen_read.read_cnt[7]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 3 | 8 | 2.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 4 | 8 | 2.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 4 | 8 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 8 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1549_2047_bytes_accumulator/counter_msb[23]_i_1__57_n_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[15][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 2 | 8 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[15][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 8 | 2.67 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[13][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 8 | 2.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[14][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 1 | 8 | 8.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[10][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 4 | 8 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[11][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 4 | 8 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[14][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 2 | 8 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_dre_tvalid_i_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_clr_dbc_reg_reg[0] | 1 | 8 | 8.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[12][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 2 | 8 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_decerr_slave.decerr_slave_inst/gen_axi.read_cnt[7]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 8 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[8][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 8 | 2.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[9][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 8 | 2.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[7][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 8 | 2.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[6][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 8 | 2.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[4][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 2 | 8 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[5][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 8 | 2.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 1 | 8 | 8.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_decerr_slave.decerr_slave_inst/gen_axi.read_cnt[7]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 2 | 8 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/col_cnt[7]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DECODER/reset_flop_out | 4 | 8 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/decerr_slave_inst/s_axi_rvalid | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_2[0] | 2 | 8 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RX_WD_ALIGN/bitslip_counter | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_LANE/i_RX_WD_ALIGN/bitslip_counter[7]_i_1_n_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[5].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 1 | 8 | 8.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[7].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 1 | 8 | 8.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 3 | 8 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[6].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 3 | 8 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[4].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[95]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 3 | 8 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[79]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 3 | 8 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[87]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[4].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[103]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 3 | 8 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[71]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 3 | 8 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[7].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_2_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 1 | 8 | 8.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[5].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[111]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[6].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[119]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 1 | 8 | 8.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/decerr_slave_inst/gen_axi.gen_read.read_cnt[7]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/aresetn_d_reg[1]_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 8 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/SR[0] | 1 | 8 | 8.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/SR[1] | 1 | 8 | 8.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_dbeat_cntr[7]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/decerr_slave_inst/gen_axi.gen_read.read_cnt[7]_i_1_n_0 | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/register_slice_inst/ar.ar_pipe/aresetn_d_reg[1]_0 | 3 | 8 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/sig_dbeat_cntr[7]_i_1__1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 3 | 8 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/parity_valid_pipe[0][7]_i_1_n_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[0] | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK1/GEN_ASYNC_WRITE.axi2ip_wrce_reg[0][0] | 1 | 8 | 8.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[2] | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK1/GEN_ASYNC_WRITE.axi2ip_wrce_reg[12][0] | 2 | 8 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/irqthresh_wren_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 3 | 8 | 2.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/irqthresh_wren_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 4 | 8 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/b.b_pipe/aresetn_d_reg[1]_0 | 4 | 8 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/b.b_pipe/aresetn_d_reg[0]_0 | 4 | 8 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_rr | 2 | 8 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 8 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/irqdelay_wren_reg_0[0] | 2 | 8 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/irqdelay_wren_reg_0[0] | 2 | 8 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 1 | 8 | 8.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/sig_push_rd_sts_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/sig_rd_sts_tag_reg0 | 3 | 8 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 1 | 8 | 8.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | 4 | 8 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/b_push | | 1 | 8 | 8.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/mhandshake_r | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/SR[0] | 3 | 8 | 2.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/s_ready_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/pushed_commands[7]_i_1__0_n_0 | 2 | 8 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_ready_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/pushed_commands[7]_i_1_n_0 | 1 | 8 | 8.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 8 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/s_ready_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/pushed_commands[7]_i_1__0_n_0 | 4 | 8 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/ch2_dly_fast_cnt0 | 3 | 9 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 9 | 4.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 5 | 9 | 1.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[6].sig_output_data_reg_reg[6]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_6[0] | 5 | 9 | 1.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[4].sig_output_data_reg_reg[4]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_8[0] | 4 | 9 | 2.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[7].sig_output_data_reg_reg[7]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_5[0] | 6 | 9 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_pipes_r_b | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/stall_pipes_r_b_reg | 5 | 9 | 1.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff[1] | 1 | 9 | 9.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff[1] | 2 | 9 | 4.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_reg_STAT_RX_STATUS_REG1_clear_syncer/STAT_RX_STATUS_REG1_clear_cond | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/rx_reset_pulse_len_reg_n_0_[0] | 2 | 9 | 4.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[7].sig_output_data_reg_reg[7]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[7].sig_output_data_reg[7][8]_i_1_n_0 | 7 | 9 | 1.29 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[5].sig_output_data_reg_reg[5]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_7[0] | 5 | 9 | 1.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/w | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/cy_reg_n_0 | 2 | 9 | 4.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 5 | 9 | 1.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 5 | 9 | 1.80 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 9 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff[1] | 2 | 9 | 4.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[0].sig_output_data_reg_reg[0]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[0].sig_output_data_reg[0][8]_i_1_n_0 | 4 | 9 | 2.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 5 | 9 | 1.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_tx_resetdone_0/user_tx_reset_0 | 6 | 9 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_fwft.ram_regout_en | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 1 | 9 | 9.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/ch1_dly_fast_cnt0 | 3 | 9 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 9 | 4.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 9 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | | 1 | 9 | 9.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff[1] | 3 | 9 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[0].sig_output_data_reg_reg[0]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[0].sig_output_data_reg[0][8]_i_1__0_n_0 | 4 | 9 | 2.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[1].sig_output_data_reg_reg[1]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_11[0] | 5 | 9 | 1.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[2].sig_output_data_reg_reg[2]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_10[0] | 5 | 9 | 1.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_173_in | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 3 | 9 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[10][0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 8 | 2.67 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff[1] | 2 | 9 | 4.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/mm2s_rready_reg_0[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 2 | 9 | 4.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/pop_mi_data | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 2 | 9 | 4.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/w | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/cy_reg_0 | 2 | 9 | 4.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 9 | 4.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[4].sig_output_data_reg_reg[4]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[4].sig_output_data_reg[4][8]_i_1_n_0 | 5 | 9 | 1.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[1].sig_output_data_reg_reg[1]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[1].sig_output_data_reg[1][8]_i_1_n_0 | 6 | 9 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[5].sig_output_data_reg_reg[5]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[5].sig_output_data_reg[5][8]_i_1_n_0 | 5 | 9 | 1.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[6].sig_output_data_reg_reg[6]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[6].sig_output_data_reg[6][8]_i_1_n_0 | 5 | 9 | 1.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 6 | 9 | 1.50 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 9 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 9 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[2].sig_output_data_reg_reg[2]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[2].sig_output_data_reg[2][8]_i_1_n_0 | 6 | 9 | 1.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[3].sig_output_data_reg_reg[3]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[3].sig_output_data_reg[3][8]_i_1_n_0 | 4 | 9 | 2.25 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/sig_eop_sent_reg_reg_0[0] | 3 | 9 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[3].sig_output_data_reg_reg[3]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_9[0] | 4 | 9 | 2.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/pop_mi_data | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_tx_resetdone_0/user_tx_reset_0 | 6 | 9 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[2].sig_output_data_reg_reg[2]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[2].sig_output_data_reg[2][8]_i_1_n_0 | 6 | 9 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff[1] | 2 | 9 | 4.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff[1] | 1 | 9 | 9.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 3 | 9 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_pipes_r_b | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_PAUSE/stall_pipes_r_b_reg | 5 | 9 | 1.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 9 | 2.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_173_in | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 2 | 9 | 4.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 5 | 9 | 1.80 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 2 | 9 | 4.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/ch2_dly_fast_cnt0 | 3 | 9 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[3].sig_output_data_reg_reg[3]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[3].sig_output_data_reg[3][8]_i_1_n_0 | 4 | 9 | 2.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff[1] | 1 | 9 | 9.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[0].sig_output_data_reg_reg[0]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[0].sig_output_data_reg[0][8]_i_1__0_n_0 | 4 | 9 | 2.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 9 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_tx_resetdone_0/user_tx_reset_0 | 5 | 9 | 1.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[1].sig_output_data_reg_reg[1]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[1].sig_output_data_reg[1][8]_i_1_n_0 | 3 | 9 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/pop_mi_data | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 2 | 9 | 4.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[3].sig_output_data_reg_reg[3]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_10[0] | 4 | 9 | 2.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[5].sig_output_data_reg_reg[5]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_8[0] | 7 | 9 | 1.29 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[1].sig_output_data_reg_reg[1]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_12[0] | 5 | 9 | 1.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[4].sig_output_data_reg_reg[4]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_9[0] | 5 | 9 | 1.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[2].sig_output_data_reg_reg[2]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_11[0] | 4 | 9 | 2.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[6].sig_output_data_reg_reg[6]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_7[0] | 4 | 9 | 2.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_OUTPUT_REG[7].sig_output_data_reg_reg[7]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_6[0] | 6 | 9 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[5].sig_output_data_reg_reg[5]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[5].sig_output_data_reg[5][8]_i_1_n_0 | 5 | 9 | 1.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[4].sig_output_data_reg_reg[4]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[4].sig_output_data_reg[4][8]_i_1_n_0 | 6 | 9 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_reg_STAT_RX_STATUS_REG1_clear_syncer/STAT_RX_STATUS_REG1_clear_cond | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/rx_reset_pulse_len_reg_n_0_[0] | 3 | 9 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[6].sig_output_data_reg_reg[6]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[6].sig_output_data_reg[6][8]_i_1_n_0 | 7 | 9 | 1.29 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg_0 | 3 | 9 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 9 | 4.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[7].sig_output_data_reg_reg[7]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[7].sig_output_data_reg[7][8]_i_1_n_0 | 7 | 9 | 1.29 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.read_data_inst/p_15_in | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_tx_resetdone_0/user_tx_reset_0 | 5 | 9 | 1.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_7[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_8[0] | 2 | 10 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 3 | 10 | 3.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[2].sig_delay_data_reg_reg[2]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_3[0] | 7 | 10 | 1.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/chkr_error_block_d3_no_ena | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DECODER/reset_flop_out | 2 | 10 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 2 | 10 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_AXI_RESET_RX_SYNC/SS[0] | 1 | 10 | 10.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_strb_reg_out_reg[4][0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[4]_0[0] | 3 | 10 | 3.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_5[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_10[0] | 3 | 10 | 3.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_strb_reg_out_reg[6][0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[6]_0[0] | 3 | 10 | 3.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_strb_reg_out_reg[5][0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[5]_0[0] | 6 | 10 | 1.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_4[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_11[0] | 3 | 10 | 3.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 2 | 10 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/counter_msb[23]_i_1__46_n_0 | 3 | 10 | 3.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_2[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_12[0] | 2 | 10 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 3 | 10 | 3.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ram_empty_fb_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 10 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ram_empty_fb_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 10 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/sel_first_reg[0] | | 4 | 10 | 2.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ram_empty_fb_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 1 | 10 | 10.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/E[0] | | 4 | 10 | 2.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_READ.REG_ARVALID_TO_IPCLK/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/REG_HRD_RST/scndry_out | 4 | 10 | 2.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 5 | 10 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 2 | 10 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[4].sig_delay_data_reg[4][9]_i_2__0_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1[0] | 6 | 10 | 1.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ram_empty_fb_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 10 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 10 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_bytes_accumulator/counter_lsb[23]_i_1__6_n_0 | 2 | 10 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_6[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_9[0] | 2 | 10 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ram_empty_fb_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 10 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/ch1_dly_fast_cnt0 | 2 | 9 | 4.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/w | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/cy_reg_0 | 2 | 9 | 4.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[0].sig_output_data_reg_reg[0]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_OUTPUT_REG[0].sig_output_data_reg[0][8]_i_1_n_0 | 4 | 9 | 2.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/w | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/cy_reg_n_0 | 2 | 9 | 4.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/pop_mi_data | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_tx_resetdone_0/user_tx_reset_0 | 4 | 9 | 2.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 4 | 9 | 2.25 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/mm2s_rready_reg_0[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 9 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff[1] | 2 | 9 | 4.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[3].sig_delay_data_reg_reg[3]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_3[0] | 6 | 10 | 1.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[0].sig_delay_data_reg_reg[0]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[0].sig_delay_data_reg[0][9]_i_1_n_0 | 9 | 10 | 1.11 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_STATS/reset_flop_out | 5 | 10 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/chkr_error_block_d3_no_ena | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DECODER/reset_flop_out | 3 | 10 | 3.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 2 | 10 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[6].sig_delay_data_reg_reg[6]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[6].sig_delay_data_reg[6][9]_i_1_n_0 | 7 | 10 | 1.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[2].sig_delay_data_reg_reg[2]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[2].sig_delay_data_reg[2][9]_i_1_n_0 | 8 | 10 | 1.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[3].sig_delay_data_reg_reg[3]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[3].sig_delay_data_reg[3][9]_i_1_n_0 | 5 | 10 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[1].sig_delay_data_reg_reg[1]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[1].sig_delay_data_reg[1][9]_i_1_n_0 | 9 | 10 | 1.11 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[2].sig_delay_data_reg_reg[2]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_4[0] | 7 | 10 | 1.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[4].sig_delay_data_reg_reg[4]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[4].sig_delay_data_reg[4][9]_i_1_n_0 | 6 | 10 | 1.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[1].sig_delay_data_reg[1][9]_i_2__0_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_5[0] | 7 | 10 | 1.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[0].sig_delay_data_reg[0][9]_i_2__0_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_1[0] | 7 | 10 | 1.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[4].sig_delay_data_reg[4][9]_i_2__0_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_2[0] | 5 | 10 | 2.00 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[5].sig_delay_data_reg[5][9]_i_2__0_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[5].sig_delay_data_reg[5][9]_i_1__0_n_0 | 4 | 10 | 2.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 10 | 2.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[3].sig_delay_data_reg_reg[3]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_2[0] | 8 | 10 | 1.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1523_1548_bytes_accumulator/counter_msb[23]_i_1__14_n_0 | 2 | 10 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_AXI_RESET_TX_SYNC/SS[0] | 1 | 10 | 10.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 3 | 10 | 3.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_rx_pll_timer_clr_reg_n_0 | 3 | 10 | 3.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ram_empty_fb_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 1 | 10 | 10.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[0].sig_delay_data_reg_reg[0]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0[0] | 7 | 10 | 1.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_STATS/reset_flop_out | 6 | 10 | 1.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_tx_pll_timer_ctr[9]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_tx_pll_timer_clr_reg_n_0 | 3 | 10 | 3.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_3[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/SR[0] | 2 | 10 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[1].sig_delay_data_reg[1][9]_i_2__0_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_4[0] | 7 | 10 | 1.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[0].sig_delay_data_reg_reg[0]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[0].sig_delay_data_reg[0][9]_i_1_n_0 | 7 | 10 | 1.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[1].sig_delay_data_reg_reg[1]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[1].sig_delay_data_reg[1][9]_i_1_n_0 | 8 | 10 | 1.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[2].sig_delay_data_reg_reg[2]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[2].sig_delay_data_reg[2][9]_i_1_n_0 | 9 | 10 | 1.11 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[3].sig_delay_data_reg_reg[3]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[3].sig_delay_data_reg[3][9]_i_1_n_0 | 6 | 10 | 1.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[4].sig_delay_data_reg_reg[4]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[4].sig_delay_data_reg[4][9]_i_1_n_0 | 5 | 10 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[6].sig_delay_data_reg_reg[6]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[6].sig_delay_data_reg[6][9]_i_1_n_0 | 4 | 10 | 2.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_strb_reg_out_reg[2][0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[2]_0[0] | 3 | 10 | 3.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_strb_reg_out_reg[3][0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[3]_0[0] | 1 | 10 | 10.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_strb_reg_out_reg[0][0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[0]_0[0] | 3 | 10 | 3.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_strb_reg_out_reg[1][0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[1]_0[0] | 2 | 10 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[7]_0[0] | 2 | 10 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[5].sig_delay_data_reg_reg[5]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[5].sig_delay_data_reg[5][9]_i_1_n_0 | 5 | 10 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[6].sig_delay_data_reg_reg[6]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GEN_INPUT_REG[7].sig_input_data_reg_reg[7][8][0] | 6 | 10 | 1.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 1 | 10 | 10.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_0[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_14[0] | 3 | 10 | 3.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 1 | 10 | 10.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ram_empty_fb_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 10 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_strb_reg_out_reg[2][0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[2]_0[0] | 2 | 10 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_strb_reg_out_reg[1][0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[1]_0[0] | 2 | 10 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_strb_reg_out_reg[3][0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[3]_0[0] | 3 | 10 | 3.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_AXI_RESET_TX_SYNC/SS[0] | 2 | 10 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_bytes_accumulator/counter_lsb[23]_i_1__6_n_0 | 2 | 10 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_bytes_accumulator/counter_msb[23]_i_1__6_n_0 | 2 | 10 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_DRE.I_S2MM_DRE_BLOCK/GEN_DELAY_REG[6].sig_delay_data_reg_reg[6]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GEN_INPUT_REG[7].sig_input_data_reg_reg[7][8][0] | 5 | 10 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[7]_0[0] | 4 | 10 | 2.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_strb_reg_out_reg[4][0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[4]_0[0] | 4 | 10 | 2.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 3 | 10 | 3.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_strb_reg_out_reg[6][0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[6]_0[0] | 3 | 10 | 3.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_fwft.ram_regout_en | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 10 | 2.50 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_1[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_13[0] | 2 | 10 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_0[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_14[0] | 3 | 10 | 3.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_5[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_10[0] | 1 | 10 | 10.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_3[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/SR[0] | 4 | 10 | 2.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_4[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_11[0] | 2 | 10 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_2[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_12[0] | 3 | 10 | 3.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_7[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_8[0] | 3 | 10 | 3.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 7 | 10 | 1.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[5].sig_delay_data_reg_reg[5]0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_DRE.I_DRE_16_to_64/GEN_DELAY_REG[5].sig_delay_data_reg[5][9]_i_1_n_0 | 5 | 10 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ram_empty_fb_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 10 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 5 | 10 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 3 | 10 | 3.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_tx_pll_timer_ctr[9]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_tx_pll_timer_clr_reg_n_0 | 3 | 10 | 3.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_rx_pll_timer_clr_reg_n_0 | 3 | 10 | 3.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_strb_reg_out_reg[0][0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[0]_0[0] | 4 | 10 | 2.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_AXI_RESET_RX_SYNC/SS[0] | 1 | 10 | 10.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 4 | 10 | 2.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | | 1 | 10 | 10.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 10 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ram_empty_fb_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 10 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ram_empty_fb_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 3 | 10 | 3.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 10 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 2 | 10 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/sel_first_reg[0] | | 7 | 10 | 1.43 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/E[0] | | 5 | 10 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 3 | 10 | 3.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ram_empty_fb_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 10 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 4 | 10 | 2.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg_0 | 2 | 10 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 1 | 10 | 10.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ram_empty_fb_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 10 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_strb_reg_out_reg[5][0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_strb_reg_out_reg[5]_0[0] | 4 | 10 | 2.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_6[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_wr_a.gen_word_narrow.mem_reg_0_9[0] | 6 | 10 | 1.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_READ.REG_ARVALID_TO_IPCLK/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/REG_HRD_RST/scndry_out | 2 | 10 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_FTP/reset_flop_out | 5 | 11 | 2.20 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_rx_enable_r_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 8 | 11 | 1.38 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.USE_SPLIT.write_resp_inst/p_1_in | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 5 | 11 | 2.20 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_bytes_accumulator/counter_lsb[23]_i_1__25_n_0 | 3 | 11 | 3.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.USE_SPLIT.write_resp_inst/p_1_in | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 3 | 11 | 3.67 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_STATS/my_total_good_bytes_nxt | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_STATS/my_total_good_bytes[14]_i_1_n_0 | 3 | 11 | 3.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/counter_msb[23]_i_1__16_n_0 | 3 | 11 | 3.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/counter_msb[23]_i_1__2_n_0 | 2 | 11 | 5.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.USE_SPLIT.write_resp_inst/p_1_in | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 4 | 11 | 2.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_FTP/reset_flop_out | 4 | 11 | 2.75 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_rx_enable_r_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 7 | 11 | 1.57 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.USE_SPLIT.write_resp_inst/p_1_in | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 5 | 11 | 2.20 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_STATS/ena | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_STATS/my_total_good_bytes[14]_i_1__0_n_0 | 4 | 11 | 2.75 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/E[0] | | 6 | 12 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/valid_Write | | 2 | 12 | 6.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/AR[0] | 1 | 12 | 12.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_en | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 6 | 12 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/AR[0] | 1 | 12 | 12.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 3 | 12 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 3 | 12 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 4 | 12 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 3 | 12 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 4 | 12 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/AR[0] | 1 | 12 | 12.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_STATS/ena | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_STATS/my_total_good_bytes[14]_i_1__0_n_0 | 3 | 11 | 3.67 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 5 | 12 | 2.40 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 3 | 12 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/sel_first_reg[0] | | 5 | 12 | 2.40 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/valid_Write | | 2 | 12 | 6.00 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/AR[0] | 1 | 12 | 12.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/FSM_sequential_state_reg[0]_0[0] | | 5 | 12 | 2.40 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/AR[0] | 1 | 12 | 12.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 3 | 12 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 4 | 12 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/cmd_translator_0/incr_cmd_0/axaddr_incr[11]_i_1_n_0 | | 6 | 12 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/AR[0] | 1 | 12 | 12.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/AR[0] | 1 | 12 | 12.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/FSM_sequential_state_reg[0]_0[0] | | 7 | 12 | 1.71 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 3 | 12 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 3 | 12 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/cmd_translator_0/incr_cmd_0/axaddr_incr[11]_i_1_n_0 | | 5 | 12 | 2.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 3 | 12 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/sel_first_reg[0] | | 6 | 12 | 2.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 4 | 12 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/start_count_5K_reg_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/rx_clk_count[12]_i_1_n_0 | 3 | 13 | 4.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/empty_fwft_i_reg[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 5 | 13 | 2.60 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_mmap_reset_reg | 6 | 13 | 2.17 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/empty_fwft_i_reg[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 5 | 13 | 2.60 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DECODER/reset_flop_out | 10 | 13 | 1.30 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[2] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 6 | 13 | 2.17 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 5 | 13 | 2.60 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 3 | 12 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 3 | 12 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 4 | 12 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/AR[0] | 1 | 12 | 12.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_en | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 6 | 12 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 4 | 12 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/AR[0] | 1 | 12 | 12.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy | 2 | 12 | 6.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/E[0] | | 5 | 12 | 2.40 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/M_READY_I | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 3 | 13 | 4.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_128_255_bytes_accumulator/counter_msb[23]_i_1__23_n_0 | 3 | 14 | 4.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 2 | 14 | 7.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/p_4_in | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 6 | 14 | 2.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 14 | 4.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/E[0] | | 4 | 14 | 3.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DECODER/reset_flop_out | 11 | 13 | 1.18 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[2] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 7 | 13 | 1.86 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/empty_fwft_i_reg[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 5 | 13 | 2.60 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/start_count_5K_reg_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/rx_clk_count[12]_i_1_n_0 | 3 | 13 | 4.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_mmap_reset_reg | 7 | 13 | 1.86 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 9 | 13 | 1.44 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/empty_fwft_i_reg[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 5 | 13 | 2.60 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_STATS/stat_tx_total_good_bytes[13]_i_1_n_0 | 2 | 14 | 7.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 14 | 7.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/E[0] | | 5 | 14 | 2.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 14 | 3.50 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_STATS/stat_rx_total_good_bytes[13]_i_1_n_0 | 3 | 14 | 4.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 6 | 14 | 2.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 1 | 14 | 14.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/p_4_in | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 4 | 14 | 3.50 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_CORE_RESET_SYNC/SR[0] | 3 | 14 | 4.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_STATS/stat_tx_total_good_bytes[13]_i_1_n_0 | 3 | 14 | 4.67 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/rx_clk_noctrlcode_count[13]_i_1_n_0 | 3 | 14 | 4.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_3[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 4 | 15 | 3.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_STATS/ena | | 4 | 15 | 3.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_multicast_accumulator/counter_msb[23]_i_1__31_n_0 | 3 | 15 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_STATS/my_total_good_bytes_d1[14]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_STATS/reset_flop_out | 4 | 15 | 3.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_msb[23]_i_1__21_n_0 | 2 | 15 | 7.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_3[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 4 | 15 | 3.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_FCS/truncate_flag_reg[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_FCS/SS[0] | 4 | 15 | 3.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_STATS/my_total_good_bytes_d1[14]_i_1__0_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_STATS/reset_flop_out | 3 | 15 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 1 | 14 | 14.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_512_1023_bytes_accumulator/pm_tick_d1 | | 6 | 15 | 2.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_packets_accumulator/counter_msb[23]_i_1__9_n_0 | 2 | 15 | 7.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/counter_msb[23]_i_1__46_n_0 | 3 | 15 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_3[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 6 | 15 | 2.50 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_enable_r_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 7 | 15 | 2.14 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/counter_msb[23]_i_1__22_n_0 | 2 | 15 | 7.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/s_ready_i_reg[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 6 | 16 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_cntr[15]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 2 | 16 | 8.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_ready_i_reg[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 7 | 16 | 2.29 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_ETH_FRAME_PARSER/compare | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_ETH_FRAME_PARSER/o_length[15]_i_1_n_0 | 8 | 16 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | | 1 | 16 | 16.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_inrangeerr_accumulator/counter_msb[23]_i_1__53_n_0 | 3 | 16 | 5.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_decerr_slave.decerr_slave_inst/s_axi_rvalid_i | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 5 | 16 | 3.20 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_addr_cntr_im0_msh[15]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_mmap_reset_reg | 5 | 16 | 3.20 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/E[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 3 | 16 | 5.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/s2mm_all_idle | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/s_soft_reset_i_re | 2 | 16 | 8.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_STATS/stat_tx_total_good_packets_i_1_n_0 | 6 | 16 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_lsh[15]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 2 | 16 | 8.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_decerr_slave.decerr_slave_inst/gen_axi.s_axi_bid_i[15]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 6 | 16 | 2.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SM/FSM_sequential_mm2s_cs_reg[1]_0 | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/s_soft_reset_i_re | 2 | 16 | 8.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/REG_HRD_RST_OUT/scndry_out | 6 | 16 | 2.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | | 1 | 16 | 16.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_FCS/truncate_flag_reg[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_FCS/SS[0] | 4 | 15 | 3.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_STATS/my_total_good_bytes_d1[14]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_STATS/reset_flop_out | 3 | 15 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_STATS/my_total_good_bytes_d1[14]_i_1__0_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_STATS/reset_flop_out | 3 | 15 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 2 | 15 | 7.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_STATS/ena | | 3 | 15 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_3[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 8 | 15 | 1.88 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/E[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 4 | 16 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_ready_i_reg[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 8 | 16 | 2.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/E[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 4 | 16 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/E[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 7 | 16 | 2.29 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/b.b_pipe/E[0] | | 7 | 16 | 2.29 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_STATS/stat_tx_total_good_packets_i_1_n_0 | 7 | 16 | 2.29 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_decerr_slave.decerr_slave_inst/gen_axi.s_axi_bid_i[15]_i_1_n_0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 8 | 16 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_decerr_slave.decerr_slave_inst/s_axi_rvalid_i | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 5 | 16 | 3.20 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_multicast_accumulator/counter_msb[23]_i_1__31_n_0 | 3 | 16 | 5.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/b.b_pipe/E[0] | | 8 | 16 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | | 1 | 16 | 16.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/s2mm_all_idle | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/s_soft_reset_i_re | 2 | 16 | 8.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_addr_cntr_im0_msh[15]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_mmap_reset_reg | 6 | 16 | 2.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SM/FSM_sequential_mm2s_cs_reg[1]_0 | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/s_soft_reset_i_re | 2 | 16 | 8.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_calc2_reg_ns | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_mmap_reset_reg | 6 | 16 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/counter_msb[23]_i_1__49_n_0 | 4 | 16 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_ETH_FRAME_PARSER/compare | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_ETH_FRAME_PARSER/o_length[15]_i_1_n_0 | 5 | 16 | 3.20 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | | 1 | 16 | 16.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/E[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 6 | 16 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_calc2_reg_ns | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_mmap_reset_reg | 5 | 16 | 3.20 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_msh[15]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/areset_d_reg_n_0_[0] | 5 | 16 | 3.20 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_lsh[15]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 2 | 16 | 8.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_msh[15]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 5 | 16 | 3.20 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_cntr[15]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 2 | 16 | 8.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | | 1 | 16 | 16.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/REG_HRD_RST_OUT/scndry_out | 5 | 16 | 3.20 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/E[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 4 | 16 | 4.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/E[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 2 | 16 | 8.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/s_ready_i_reg[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 6 | 16 | 2.67 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | | 1 | 16 | 16.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/s_ready_i_reg_0 | | 5 | 17 | 3.40 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 11 | 17 | 1.55 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_toolong_accumulator/counter_msb[23]_i_1__24_n_0 | 2 | 17 | 8.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_broadcast_accumulator/counter_msb[23]_i_1__37_n_0 | 3 | 17 | 5.67 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/valid_Write | | 3 | 17 | 5.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/p_1_in | | 5 | 17 | 3.40 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/sig_push_dqual_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/sig_next_calc_error_reg_i_1_n_0 | 5 | 17 | 3.40 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.cmd_push_0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 7 | 18 | 2.57 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/b.b_pipe/E[0] | | 9 | 18 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_STATS/stat_rx_total_good_packets_i_1_n_0 | 6 | 18 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.cmd_push_2 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 6 | 18 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.cmd_push_1 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 6 | 18 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/s_ready_i_reg_0 | | 4 | 17 | 4.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/counter_msb[23]_i_1__41_n_0 | 3 | 17 | 5.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/p_1_in | | 4 | 17 | 4.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_last_dbeat_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | 3 | 17 | 5.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 12 | 17 | 1.42 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.cmd_push_2 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 5 | 18 | 3.60 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.cmd_push_6 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 6 | 18 | 3.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/M_READY_I | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 4 | 18 | 4.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_vlan_accumulator/counter_msb[23]_i_1__55_n_0 | 3 | 18 | 6.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.cmd_push_3 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 5 | 18 | 3.60 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.cmd_push_6 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 5 | 18 | 3.60 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.cmd_push_6 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 4 | 18 | 4.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.cmd_push_4 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 5 | 18 | 3.60 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/b.b_pipe/E[0] | | 10 | 18 | 1.80 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.cmd_push_1 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 6 | 18 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.cmd_push_0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 4 | 18 | 4.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_FCS/reset_flop_out | 6 | 18 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.cmd_push_7 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 5 | 18 | 3.60 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.cmd_push_2 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 5 | 18 | 3.60 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.cmd_push_1 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 7 | 18 | 2.57 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.cmd_push_7 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 4 | 18 | 4.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.cmd_push_2 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 6 | 18 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.cmd_push_5 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 5 | 18 | 3.60 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.cmd_push_3 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 6 | 18 | 3.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.cmd_push_0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 5 | 18 | 3.60 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.cmd_push_1 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 5 | 18 | 3.60 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.cmd_push_5 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 4 | 18 | 4.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.cmd_push_7 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 4 | 18 | 4.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.cmd_push_3 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 7 | 18 | 2.57 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.cmd_push_4 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 5 | 18 | 3.60 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.cmd_push_5 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 7 | 18 | 2.57 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.cmd_push_4 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 5 | 18 | 3.60 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/b.b_pipe/E[0] | | 8 | 18 | 2.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_FCS/reset_flop_out | 8 | 18 | 2.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/ram_wr_en_pf | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 5 | 19 | 3.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_64_bytes_accumulator/counter_msb[23]_i_1__19_n_0 | 3 | 19 | 6.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_STATS/stat_rx_total_good_packets_i_1_n_0 | 6 | 18 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.cmd_push_3 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 4 | 18 | 4.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.cmd_push_5 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 4 | 18 | 4.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.cmd_push_6 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 6 | 18 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/pm_tick_d1 | | 7 | 18 | 2.57 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/b.b_pipe/E[0] | | 7 | 18 | 2.57 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.cmd_push_0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 5 | 18 | 3.60 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/m_valid_i_reg[0] | | 4 | 19 | 4.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/ram_wr_en_pf | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 19 | 4.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 6 | 19 | 3.17 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/s_ready_i_reg_0 | | 4 | 19 | 4.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 5 | 19 | 3.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_code_accumulator/counter_msb[23]_i_1__44_n_0 | 3 | 19 | 6.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_STATS/reset_flop_out | 5 | 19 | 3.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_HI_BER_MONITOR/ber_125us_timer[19]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_HI_BER/reset_flop_out | 4 | 20 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_65_127_bytes_accumulator/counter_msb[23]_i_1__3_n_0 | 3 | 20 | 6.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1523_1548_bytes_accumulator/counter_msb[23]_i_1__14_n_0 | 5 | 19 | 3.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_STATS/reset_flop_out | 6 | 19 | 3.17 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_128_255_bytes_accumulator/counter_msb[23]_i_1__23_n_0 | 3 | 19 | 6.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_HI_BER_MONITOR/ber_125us_timer[19]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_HI_BER/reset_flop_out | 3 | 20 | 6.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/counter_lsb[23]_i_1__49_n_0 | 3 | 20 | 6.67 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/counter_lsb[23]_i_1__2_n_0 | 3 | 20 | 6.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_unicast_accumulator/counter_msb[23]_i_1__27_n_0 | 3 | 21 | 7.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_128_255_bytes_accumulator/counter_msb[23]_i_1__0_n_0 | 5 | 20 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_vlan_accumulator/counter_msb[23]_i_1__55_n_0 | 4 | 21 | 5.25 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_bytes_accumulator/counter_lsb[23]_i_1__42_n_0 | 4 | 21 | 5.25 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/GEN_FOR_ASYNC.REG_TO_SECONDARY/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/out | 8 | 21 | 2.62 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_small_accumulator/counter_msb[23]_i_1__51_n_0 | 4 | 21 | 5.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/counter_lsb[23] | 4 | 21 | 5.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_2048_4095_bytes_accumulator/counter_msb[23]_i_1__35_n_0 | 6 | 21 | 3.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_packets_accumulator/counter_lsb[23]_i_1__13_n_0 | 4 | 21 | 5.25 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/E[0] | | 6 | 21 | 3.50 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_ETH_FRAME_PARSER/efp_valid | | 5 | 21 | 4.20 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1519_1522_bytes_accumulator/counter_lsb[23] | 4 | 21 | 5.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_broadcast_accumulator/counter_lsb[23] | 4 | 21 | 5.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_large_accumulator/pm_tick_d1 | | 10 | 21 | 2.10 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/E[0] | | 9 | 21 | 2.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_4096_8191_bytes_accumulator/counter_lsb[23] | 4 | 21 | 5.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_fragment_accumulator/counter_msb[23]_i_1__40_n_0 | 4 | 22 | 5.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/GEN_DESC_UPDT_QUEUE.updt_sts_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 10 | 22 | 2.20 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts2_rden | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 11 | 22 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/GEN_FOR_ASYNC.REG_TO_SECONDARY/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/out | 8 | 21 | 2.62 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/counter_msb[23]_i_1__22_n_0 | 5 | 22 | 4.40 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/out | 8 | 22 | 2.75 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/s_ready_i_reg_0 | | 3 | 22 | 7.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/out | 10 | 22 | 2.20 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts2_rden | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 11 | 22 | 2.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/FSM_sequential_state_reg[1]_0[0] | | 3 | 22 | 7.33 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 2 | 22 | 11.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_multicast_accumulator/counter_lsb[23]_i_1__54_n_0 | 4 | 23 | 5.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1549_2047_bytes_accumulator/counter_lsb[23]_i_1__57_n_0 | 4 | 23 | 5.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/counter_lsb[23]_i_1__48_n_0 | 4 | 23 | 5.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_4096_8191_bytes_accumulator/counter_lsb[23]_i_1__47_n_0 | 4 | 23 | 5.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/counter_lsb[23]_i_1__52_n_0 | 5 | 23 | 4.60 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/counter_lsb[23]_i_1__49_n_0 | 4 | 23 | 5.75 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/GEN_DESC_UPDT_QUEUE.updt_sts_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 9 | 22 | 2.44 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_512_1023_bytes_accumulator/counter_msb[23]_i_1__11_n_0 | 4 | 22 | 5.50 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_small_accumulator/counter_lsb[23]_i_1__51_n_0 | 4 | 23 | 5.75 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/m_valid_i_reg_0[0] | | 7 | 23 | 3.29 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_test_pattern_mismatch_accumulator/counter_lsb[23]_i_1__50_n_0 | 4 | 23 | 5.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/counter_lsb__0[23] | 4 | 23 | 5.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_vlan_accumulator/counter_lsb[23]_i_1__55_n_0 | 5 | 23 | 4.60 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_256_511_bytes_accumulator/counter_lsb[23]_i_1__5_n_0 | 4 | 23 | 5.75 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_fcs_accumulator/counter_lsb[23]_i_1__26_n_0 | 5 | 23 | 4.60 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_packets_accumulator/counter_lsb[23]_i_1__13_n_0 | 5 | 23 | 4.60 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_push_to_wsc_reg | | 2 | 23 | 11.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_128_255_bytes_accumulator/counter_lsb[23]_i_1__0_n_0 | 4 | 23 | 5.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_256_511_bytes_accumulator/counter_lsb[23]_i_1__5_n_0 | 5 | 23 | 4.60 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_256_511_bytes_accumulator/counter_msb[23]_i_1__7_n_0 | 5 | 23 | 4.60 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_64_bytes_accumulator/counter_lsb[23]_i_1__4_n_0 | 4 | 23 | 5.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_65_127_bytes_accumulator/counter_lsb[23]_i_1__3_n_0 | 4 | 23 | 5.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/counter_lsb[23]_i_1__7_n_0 | 4 | 23 | 5.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_packets_accumulator/counter_lsb[23]_i_1__1_n_0 | 4 | 23 | 5.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_framing_err_accumulator/counter_lsb[23]_i_1__45_n_0 | 4 | 23 | 5.75 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/counter_lsb[23]_i_1__10_n_0 | 5 | 23 | 4.60 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 11 | 23 | 2.09 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 8 | 23 | 2.88 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_cycle_accumulator/counter_lsb[23]_i_1__43_n_0 | 4 | 23 | 5.75 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/m_valid_i_reg_0[0] | | 10 | 23 | 2.30 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_64_bytes_accumulator/counter_lsb[23]_i_1__4_n_0 | 4 | 23 | 5.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_vlan_accumulator/counter_lsb[23]_i_1__55_n_0 | 4 | 23 | 5.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/counter_lsb[23]_i_1__7_n_0 | 4 | 23 | 5.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_512_1023_bytes_accumulator/counter_msb[23]_i_1__15_n_0 | 3 | 23 | 7.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_65_127_bytes_accumulator/counter_lsb[23]_i_1__3_n_0 | 4 | 23 | 5.75 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/counter_lsb[23] | 4 | 23 | 5.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_code_accumulator/counter_lsb[23]_i_1__44_n_0 | 4 | 23 | 5.75 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_rx_min_packet_len_r[7]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 7 | 23 | 3.29 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_broadcast_accumulator/counter_lsb[23]_i_1__56_n_0 | 4 | 23 | 5.75 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_inrangeerr_accumulator/counter_lsb[23]_i_1__53_n_0 | 4 | 23 | 5.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_framing_err_accumulator/counter_lsb[23]_i_1__45_n_0 | 4 | 23 | 5.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/overflow | 10 | 24 | 2.40 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_512_1023_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/overflow | 6 | 24 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_128_255_bytes_accumulator/overflow | 11 | 24 | 2.18 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_large_accumulator/overflow | 8 | 24 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_512_1023_bytes_accumulator/overflow | 8 | 24 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_packets_accumulator/overflow_reg_n_0 | 6 | 24 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/overflow | 9 | 24 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_broadcast_accumulator/overflow | 6 | 24 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/overflow | 7 | 24 | 3.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_64_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_multicast_accumulator/overflow | 12 | 24 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/overflow | 6 | 24 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/overflow_reg_n_0 | 7 | 24 | 3.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_128_255_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_code_accumulator/counter_lsb[23]_i_1__44_n_0 | 4 | 23 | 5.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_128_255_bytes_accumulator/counter_lsb[23]_i_1__0_n_0 | 4 | 23 | 5.75 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 12 | 23 | 1.92 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_multicast_accumulator/counter_lsb[23]_i_1__54_n_0 | 4 | 23 | 5.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_cycle_accumulator/counter_lsb[23]_i_1__43_n_0 | 4 | 23 | 5.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_256_511_bytes_accumulator/counter_msb[23]_i_1__7_n_0 | 3 | 23 | 7.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/counter_lsb__0[23] | 4 | 23 | 5.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_packets_accumulator/counter_lsb[23]_i_1__1_n_0 | 4 | 23 | 5.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1549_2047_bytes_accumulator/counter_lsb[23]_i_1__57_n_0 | 4 | 23 | 5.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/counter_msb[23]_i_1__48_n_0 | 5 | 23 | 4.60 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/counter_lsb[23]_i_1__48_n_0 | 5 | 23 | 4.60 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_2048_4095_bytes_accumulator/pm_tick_d1 | | 11 | 23 | 2.09 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_rx_min_packet_len_r[7]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 13 | 23 | 1.77 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 8 | 23 | 2.88 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 2 | 23 | 11.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_4096_8191_bytes_accumulator/counter_lsb[23]_i_1__47_n_0 | 4 | 23 | 5.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_2048_4095_bytes_accumulator/overflow | 10 | 24 | 2.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_128_255_bytes_accumulator/overflow_reg_n_0 | 16 | 24 | 1.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1519_1522_bytes_accumulator/overflow | 8 | 24 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1519_1522_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1523_1548_bytes_accumulator/overflow | 10 | 24 | 2.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1523_1548_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_multicast_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_multicast_accumulator/overflow | 11 | 24 | 2.18 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/overflow | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_4096_8191_bytes_accumulator/overflow_reg_n_0 | 8 | 24 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_64_bytes_accumulator/overflow | 9 | 24 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_cycle_accumulator/overflow_reg_n_0 | 9 | 24 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_large_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_vlan_accumulator/overflow | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN.cnt_i_reg[2]_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SR[0] | 3 | 24 | 8.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_code_accumulator/overflow_reg_n_0 | 9 | 24 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_128_255_bytes_accumulator/overflow_reg_n_0 | 13 | 24 | 1.85 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1519_1522_bytes_accumulator/overflow | 9 | 24 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_realigner_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_tag_reg0 | 7 | 24 | 3.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1523_1548_bytes_accumulator/overflow | 6 | 24 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/overflow_reg_n_0 | 9 | 24 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1549_2047_bytes_accumulator/overflow_reg_n_0 | 9 | 24 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/overflow | 8 | 24 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_bytes_accumulator/overflow_reg_n_0 | 10 | 24 | 2.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_broadcast_accumulator/counter_msb[23]_i_1__37_n_0 | 4 | 24 | 6.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_broadcast_accumulator/overflow | 8 | 24 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_broadcast_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/overflow | 10 | 24 | 2.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/overflow | 6 | 24 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/overflow | 7 | 24 | 3.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/overflow_reg_n_0 | 10 | 24 | 2.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_bytes_accumulator/overflow_reg_n_0 | 6 | 24 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_vlan_accumulator/overflow | 9 | 24 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_vlan_accumulator/counter_msb[23]_i_1__12_n_0 | 4 | 24 | 6.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_vlan_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/overflow_reg_n_0 | 6 | 24 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_packets_accumulator/overflow_reg_n_0 | 10 | 24 | 2.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/overflow | 6 | 24 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_large_accumulator/overflow | 4 | 24 | 6.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_multicast_accumulator/overflow_reg_n_0 | 10 | 24 | 2.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_large_accumulator/counter_lsb[23] | 6 | 24 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/overflow | 11 | 24 | 2.18 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_256_511_bytes_accumulator/overflow_reg_n_0 | 10 | 24 | 2.40 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/overflow_reg_n_0 | 6 | 24 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_broadcast_accumulator/overflow_reg_n_0 | 7 | 24 | 3.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1549_2047_bytes_accumulator/overflow | 9 | 24 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1549_2047_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_4096_8191_bytes_accumulator/overflow | 8 | 24 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_2048_4095_bytes_accumulator/overflow | 8 | 24 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_2048_4095_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_fragment_accumulator/overflow | 12 | 24 | 2.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_fragment_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_framing_err_accumulator/overflow_reg_n_0 | 6 | 24 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_inrangeerr_accumulator/overflow_reg_n_0 | 10 | 24 | 2.40 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_jabber_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_65_127_bytes_accumulator/overflow | 10 | 24 | 2.40 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_512_1023_bytes_accumulator/overflow | 6 | 24 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_jabber_accumulator/overflow | 6 | 24 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_multicast_accumulator/counter_msb[23]_i_1__54_n_0 | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_multicast_accumulator/overflow_reg_n_0 | 8 | 24 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_bytes_accumulator/overflow | 7 | 24 | 3.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_oversize_accumulator/counter_msb[23]_i_1__33_n_0 | 3 | 24 | 8.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_64_bytes_accumulator/overflow_reg_n_0 | 11 | 24 | 2.18 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_oversize_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_bytes_accumulator/overflow | 6 | 24 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_packets_accumulator/overflow | 13 | 24 | 1.85 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_fcs_accumulator/overflow | 6 | 24 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_65_127_bytes_accumulator/overflow_reg_n_0 | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_vlan_accumulator/overflow_reg_n_0 | 9 | 24 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_unicast_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_unicast_accumulator/overflow | 7 | 24 | 3.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/overflow__0 | 9 | 24 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_packets_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/overflow | 9 | 24 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_packets_accumulator/overflow | 8 | 24 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_toolong_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_toolong_accumulator/overflow | 6 | 24 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_test_pattern_mismatch_accumulator/overflow_reg_n_0 | 4 | 24 | 6.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_oversize_accumulator/overflow | 6 | 24 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_small_accumulator/overflow_reg_n_0 | 7 | 24 | 3.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/overflow | 8 | 24 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/overflow_reg_n_0 | 9 | 24 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_65_127_bytes_accumulator/overflow_reg_n_0 | 7 | 24 | 3.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/overflow | 7 | 24 | 3.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_128_255_bytes_accumulator/overflow | 6 | 24 | 4.00 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/overflow | 10 | 24 | 2.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_128_255_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN.cnt_i_reg[2]_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SR[0] | 3 | 24 | 8.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_multicast_accumulator/counter_msb[23]_i_1__54_n_0 | 4 | 24 | 6.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_unicast_accumulator/overflow | 7 | 24 | 3.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_oversize_accumulator/overflow | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_oversize_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_framing_err_accumulator/overflow_reg_n_0 | 8 | 24 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_inrangeerr_accumulator/overflow_reg_n_0 | 9 | 24 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_jabber_accumulator/overflow | 6 | 24 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_jabber_accumulator/counter_lsb[23] | 6 | 24 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_broadcast_accumulator/overflow_reg_n_0 | 9 | 24 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_fragment_accumulator/overflow | 10 | 24 | 2.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/overflow__0 | 9 | 24 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_fragment_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_cycle_accumulator/overflow_reg_n_0 | 9 | 24 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_code_accumulator/overflow_reg_n_0 | 8 | 24 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_packets_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_65_127_bytes_accumulator/overflow | 10 | 24 | 2.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_64_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_64_bytes_accumulator/overflow | 10 | 24 | 2.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_realigner_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_tag_reg0 | 5 | 24 | 4.80 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_bad_fcs_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_bad_fcs_accumulator/overflow | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/overflow | 7 | 24 | 3.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_bad_fcs_accumulator/overflow | 9 | 24 | 2.67 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/overflow_reg_n_0 | 7 | 24 | 3.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_65_127_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_vlan_accumulator/counter_msb[23]_i_1__12_n_0 | 4 | 25 | 6.25 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/m_valid_i_reg_0[0] | | 9 | 25 | 2.78 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/counter_msb[23]_i_1__39_n_0 | 4 | 25 | 6.25 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/E[0] | | 9 | 25 | 2.78 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/counter_msb[23]_i_1_n_0 | 4 | 25 | 6.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_packets_accumulator/counter_msb[23]_i_1__1_n_0 | 4 | 25 | 6.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_cycle_accumulator/counter_msb[23]_i_1__43_n_0 | 3 | 25 | 8.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_128_255_bytes_accumulator/counter_msb[23]_i_1__0_n_0 | 4 | 25 | 6.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/counter_msb[23]_i_1__49_n_0 | 4 | 25 | 6.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/counter_msb[23]_i_1__41_n_0 | 5 | 25 | 5.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1549_2047_bytes_accumulator/counter_msb[23]_i_1__30_n_0 | 4 | 25 | 6.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_4096_8191_bytes_accumulator/counter_msb[23]_i_1__47_n_0 | 3 | 25 | 8.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_2048_4095_bytes_accumulator/counter_msb[23]_i_1__35_n_0 | 4 | 25 | 6.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_vlan_accumulator/overflow_reg_n_0 | 9 | 24 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_packets_accumulator/overflow | 8 | 24 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_bytes_accumulator/overflow | 10 | 24 | 2.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_fcs_accumulator/overflow | 7 | 24 | 3.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_small_accumulator/overflow_reg_n_0 | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_bytes_accumulator/overflow | 7 | 24 | 3.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/overflow_reg_n_0 | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_toolong_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_toolong_accumulator/overflow | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_test_pattern_mismatch_accumulator/overflow_reg_n_0 | 4 | 24 | 6.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/overflow | 8 | 24 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_packets_accumulator/overflow | 10 | 24 | 2.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_unicast_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/overflow | 7 | 24 | 3.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_512_1023_bytes_accumulator/overflow | 9 | 24 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/overflow | 9 | 24 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_512_1023_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/overflow | 9 | 24 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/overflow_reg_n_0 | 6 | 24 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_64_bytes_accumulator/overflow_reg_n_0 | 9 | 24 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_256_511_bytes_accumulator/overflow_reg_n_0 | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_4096_8191_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_4096_8191_bytes_accumulator/overflow | 6 | 24 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1549_2047_bytes_accumulator/overflow_reg_n_0 | 6 | 24 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1549_2047_bytes_accumulator/overflow | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_512_1023_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_512_1023_bytes_accumulator/overflow | 7 | 24 | 3.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1549_2047_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_4096_8191_bytes_accumulator/overflow_reg_n_0 | 11 | 24 | 2.18 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_2048_4095_bytes_accumulator/counter_lsb[23] | 5 | 24 | 4.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_oversize_accumulator/counter_msb[23]_i_1__33_n_0 | 5 | 25 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_code_accumulator/counter_msb[23]_i_1__44_n_0 | 4 | 25 | 6.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_unicast_accumulator/counter_msb[23]_i_1__27_n_0 | 4 | 25 | 6.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_4096_8191_bytes_accumulator/counter_msb[23]_i_1__29_n_0 | 6 | 25 | 4.17 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_framing_err_accumulator/counter_msb[23]_i_1__45_n_0 | 3 | 25 | 8.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_bad_fcs_accumulator/counter_msb[23]_i_1__20_n_0 | 4 | 25 | 6.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_toolong_accumulator/counter_msb[23]_i_1__24_n_0 | 4 | 25 | 6.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1549_2047_bytes_accumulator/counter_msb[23]_i_1__57_n_0 | 3 | 25 | 8.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/counter_msb[23]_i_1__5_n_0 | 5 | 25 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_64_bytes_accumulator/counter_msb[23]_i_1__4_n_0 | 4 | 25 | 6.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_calc2_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_mmap_reset_reg | 10 | 25 | 2.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_fcs_accumulator/counter_msb[23]_i_1__26_n_0 | 5 | 25 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_65_127_bytes_accumulator/counter_msb[23]_i_1__3_n_0 | 4 | 25 | 6.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_cycle_accumulator/counter_msb[23]_i_1__43_n_0 | 4 | 25 | 6.25 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_packets_accumulator/counter_msb[23]_i_1__13_n_0 | 4 | 25 | 6.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_64_bytes_accumulator/counter_msb[23]_i_1__4_n_0 | 3 | 25 | 8.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_calc2_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_mmap_reset_reg | 6 | 25 | 4.17 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_512_1023_bytes_accumulator/counter_msb[23]_i_1__15_n_0 | 3 | 25 | 8.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_large_accumulator/counter_msb[23]_i_1__32_n_0 | 4 | 25 | 6.25 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/lsbnxtdesc_tready | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 5 | 26 | 5.20 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH1.ch1_fetch_address_i[31]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 12 | 26 | 2.17 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH2.ch2_fetch_address_i[31]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 13 | 26 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_SG/ftch_cmnd_wr | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 7 | 26 | 3.71 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_SG/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 10 | 26 | 2.60 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_65_127_bytes_accumulator/counter_msb[23]_i_1__28_n_0 | 4 | 26 | 6.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_512_1023_bytes_accumulator/counter_msb[23]_i_1__11_n_0 | 4 | 26 | 6.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_broadcast_accumulator/counter_msb[23]_i_1__56_n_0 | 3 | 26 | 8.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_framing_err_accumulator/pm_tick_d1 | | 12 | 26 | 2.17 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[57]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 16 | 26 | 1.62 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_fragment_accumulator/counter_msb[23]_i_1__40_n_0 | 4 | 25 | 6.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_bytes_accumulator/counter_msb[23]_i_1__25_n_0 | 3 | 25 | 8.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/E[0] | | 10 | 25 | 2.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_msb[23]_i_1__21_n_0 | 5 | 25 | 5.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_test_pattern_mismatch_accumulator/counter_msb[23]_i_1__50_n_0 | 5 | 25 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/m_valid_i_reg_0[0] | | 8 | 25 | 3.12 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_64_bytes_accumulator/counter_msb[23]_i_1__19_n_0 | 3 | 25 | 8.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/counter_lsb[23]_i_1__52_n_0 | 5 | 26 | 5.20 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[57]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 14 | 26 | 1.86 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/GEN_CH1_UPDATE.ch1_dma_decerr_set_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 6 | 26 | 4.33 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_ENCODER/dataout0[61]_i_1_n_0 | 8 | 26 | 3.25 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_MM2S.queue_dout_valid_reg_0 | | 2 | 26 | 13.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/updt_curdesc0 | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 8 | 26 | 3.25 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/updt_cmnd_wr | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 7 | 26 | 3.71 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_MM2S.queue_dout_valid_reg_0 | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/out | 8 | 26 | 3.25 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.queue_dout2_valid_reg_0 | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/out | 7 | 26 | 3.71 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/updt_data_reg_1[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 8 | 26 | 3.25 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[4] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 12 | 26 | 2.17 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 10 | 26 | 2.60 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/lsbnxtdesc_tready | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 4 | 26 | 6.50 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/updt_data_reg_1[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 9 | 26 | 2.89 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/updt_cmnd_wr | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 12 | 26 | 2.17 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/GEN_CH1_UPDATE.ch1_dma_decerr_set_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 7 | 26 | 3.71 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/updt_curdesc0 | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 6 | 26 | 4.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.queue_dout2_valid_reg_0 | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/out | 6 | 26 | 4.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_SG/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 9 | 26 | 2.89 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/updt_data_reg_1[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 9 | 26 | 2.89 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_SG/ftch_cmnd_wr | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 6 | 26 | 4.33 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_rx_cdr_to_clr | 4 | 26 | 6.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 16 | 26 | 1.62 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_512_1023_bytes_accumulator/counter_lsb[23] | 6 | 27 | 4.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 11 | 26 | 2.36 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH2.ch2_fetch_address_i[31]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 10 | 26 | 2.60 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH1.ch1_fetch_address_i[31]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 11 | 26 | 2.36 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_MM2S.queue_dout_valid_reg_0 | | 2 | 26 | 13.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 13 | 26 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_test_pattern_mismatch_accumulator/pm_tick_d1 | | 10 | 26 | 2.60 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/axi2ip_wrce[4] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 12 | 26 | 2.17 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_65_127_bytes_accumulator/counter_lsb[23] | 6 | 26 | 4.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_large_accumulator/counter_msb[23]_i_1__32_n_0 | 5 | 27 | 5.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/counter_msb[23]_i_1__10_n_0 | 4 | 27 | 6.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/counter_msb[23]_i_1__39_n_0 | 4 | 27 | 6.75 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN.cnt_i_reg[3]_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/SR[0] | 4 | 27 | 6.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/valid_Write | | 4 | 27 | 6.75 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_packets_accumulator/counter_msb[23]_i_1__9_n_0 | 4 | 27 | 6.75 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/curdesc_lsb_i | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 10 | 27 | 2.70 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/curdesc_lsb_i | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 12 | 27 | 2.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1523_1548_bytes_accumulator/counter_lsb[23] | 6 | 27 | 4.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_CMDSTS_IF/s_axis_ftch_cmd_tvalid_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 5 | 27 | 5.40 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_vlan_accumulator/counter_lsb[23] | 6 | 27 | 4.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/counter_msb[23]_i_1__48_n_0 | 4 | 27 | 6.75 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/E[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 8 | 27 | 3.38 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/M_READY_I | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 5 | 28 | 5.60 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/counter_reg_n_0_[6] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 10 | 28 | 2.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_cmd2data_valid_reg | | 3 | 28 | 9.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/pm_tick_d1 | | 10 | 28 | 2.80 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/s_ready_i_reg_0 | | 4 | 28 | 7.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/m_valid_i_reg[0] | | 4 | 28 | 7.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 3 | 28 | 9.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/E[0] | | 6 | 28 | 4.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_CMDSTS_IF/s_axis_updt_cmd_tvalid_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 9 | 28 | 3.11 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 3 | 28 | 9.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/curdesc_lsb_i | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 13 | 27 | 2.08 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/curdesc_lsb_i | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 9 | 27 | 3.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/counter_lsb[23] | 6 | 27 | 4.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_4096_8191_bytes_accumulator/counter_msb[23]_i_1__47_n_0 | 5 | 27 | 5.40 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_CMDSTS_IF/s_axis_ftch_cmd_tvalid_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 8 | 27 | 3.38 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/valid_Write | | 4 | 28 | 7.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_broadcast_accumulator/counter_msb[23]_i_1__56_n_0 | 6 | 28 | 4.67 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/E[0] | | 5 | 28 | 5.60 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_65_127_bytes_accumulator/pm_tick_d1 | | 12 | 28 | 2.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_rx_resetdone_dclk_0/master_watchdog_00 | 4 | 29 | 7.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/valid_Write | | 5 | 29 | 5.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_bad_fcs_accumulator/counter_msb[23]_i_1__20_n_0 | 4 | 29 | 7.25 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/E[0] | | 4 | 29 | 7.25 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/E[0] | | 7 | 29 | 4.14 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 3 | 29 | 9.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 3 | 28 | 9.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/s_ready_i_reg_0 | | 4 | 28 | 7.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/E[0] | | 6 | 28 | 4.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_cmd2data_valid_reg | | 3 | 28 | 9.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_CMDSTS_IF/s_axis_updt_cmd_tvalid_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_stat_rst_user_reg_n_cdc_from_reg_0 | 9 | 28 | 3.11 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 3 | 28 | 9.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/counter_reg_n_0_[6] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 13 | 28 | 2.15 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_inrangeerr_accumulator/counter_msb[23]_i_1__53_n_0 | 4 | 28 | 7.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup2 | | 5 | 28 | 5.60 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/m_valid_i_reg[0] | | 4 | 28 | 7.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/E[0] | | 6 | 29 | 4.83 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 3 | 29 | 9.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | 13 | 30 | 2.31 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_FOR_ASYNC.REG_TO_SECONDARY/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/out | 4 | 30 | 7.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/counter_msb[23]_i_1__18_n_0 | 5 | 29 | 5.80 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_rx_resetdone_dclk_0/master_watchdog_00 | 4 | 29 | 7.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/M_READY_I | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_rxreset_0/user_rx_reset_0 | 5 | 29 | 5.80 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 3 | 29 | 9.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/valid_Write | | 5 | 29 | 5.80 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/E[0] | | 9 | 29 | 3.22 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_bytes_accumulator/counter_msb[23]_i_1__42_n_0 | 4 | 29 | 7.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_65_127_bytes_accumulator/counter_msb[23]_i_1__28_n_0 | 5 | 29 | 5.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/counter_msb[23]_i_1__34_n_0 | 6 | 29 | 4.83 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[35]_i_2_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_core_cdc_sync_gt_tx_resetdone_0/user_tx_reset_0 | 6 | 30 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_load_input_cmd | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_ADDR_CNTL/sig_addr_reg_empty_reg_0 | 6 | 30 | 5.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/si_register_slice_inst/ar.ar_pipe/E[0] | | 7 | 31 | 4.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_512_1023_bytes_accumulator/pm_tick_d1 | | 13 | 31 | 2.38 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdpp1_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 8 | 31 | 3.88 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_load_input_cmd | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/SR[0] | 7 | 31 | 4.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_framing_err_accumulator/counter_msb[23]_i_1__45_n_0 | 6 | 31 | 5.17 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_ADDR_CNTL/sig_push_addr_reg1_out | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg0 | 3 | 31 | 10.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/si_register_slice_inst/aw.aw_pipe/E[0] | | 4 | 31 | 7.75 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/s_ready_i_reg[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 9 | 31 | 3.44 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts_rden | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 10 | 31 | 3.10 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdpp1_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 7 | 31 | 4.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_bytes_accumulator/counter_msb[23]_i_1__25_n_0 | 6 | 31 | 5.17 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/updt_sts_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 8 | 31 | 3.88 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_TX_FCS/o_crc0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 14 | 32 | 2.29 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_1[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 20 | 32 | 1.60 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_2[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 22 | 32 | 1.45 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_push_input_reg11_out | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_mmap_reset_reg | 10 | 32 | 3.20 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 24 | 32 | 1.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_FTYPE_PARSER/ena | | 6 | 32 | 5.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | 14 | 30 | 2.14 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/pm_tick_d1 | | 10 | 30 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_FOR_ASYNC.REG_TO_SECONDARY/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/out | 4 | 30 | 7.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_load_input_cmd | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_ADDR_CNTL/sig_addr_reg_empty_reg_0 | 7 | 30 | 4.29 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts_rden | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 9 | 31 | 3.44 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_load_input_cmd | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/SR[0] | 6 | 31 | 5.17 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdpp1_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 8 | 31 | 3.88 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1519_1522_bytes_accumulator/counter_msb[23]_i_1__17_n_0 | 5 | 31 | 6.20 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdpp1_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 6 | 31 | 5.17 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/updt_sts_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 7 | 31 | 4.43 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/s_ready_i_reg[0] | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 8 | 31 | 3.88 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_ADDR_CNTL/sig_push_addr_reg1_out | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg0 | 5 | 31 | 6.20 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/si_register_slice_inst/aw.aw_pipe/E[0] | | 7 | 31 | 4.43 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/si_register_slice_inst/ar.ar_pipe/E[0] | | 10 | 31 | 3.10 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 23 | 32 | 1.39 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_0[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 21 | 32 | 1.52 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_1[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 25 | 32 | 1.28 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_2[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 24 | 32 | 1.33 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_pkt_fifo_cc.axis_pkt_cnt[0]_i_1_n_0 | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst/syncstages_ff[3] | 4 | 32 | 8.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_FCS/ena_d2 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_FCS/reset_flop_out | 17 | 32 | 1.88 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/ar.ar_pipe/m_valid_i_reg_inv_0 | | 4 | 32 | 8.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/arready_d12 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 | 7 | 32 | 4.57 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/rvalid | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/REG_HRD_RST/scndry_out | 15 | 32 | 2.13 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_addr_cntr_lsh_im0[15]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_mmap_reset_reg | 6 | 32 | 5.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/m_valid_i_reg_inv_0 | | 5 | 32 | 6.40 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 18 | 32 | 1.78 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/p_1_in | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 10 | 32 | 3.20 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_0[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 20 | 32 | 1.60 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_2[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 21 | 32 | 1.52 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/sig_btt_eq_0_reg[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/SR[0] | 7 | 32 | 4.57 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_pkt_fifo_cc.axis_pkt_cnt[0]_i_1_n_0 | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst/syncstages_ff[3] | 4 | 32 | 8.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_ENCODER/dataout0[54]_i_1_n_0 | 14 | 32 | 2.29 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/user_reg0_r[31]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 17 | 32 | 1.88 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/user_reg1_r[31]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 6 | 32 | 5.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/fcs_crc_hold0 | | 14 | 32 | 2.29 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_0[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 24 | 32 | 1.33 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_wdata0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 14 | 32 | 2.29 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_rvalid0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/AXI_Reset0 | 4 | 32 | 8.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_arready0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/AXI_Reset0 | 8 | 32 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/wr_en0 | | 8 | 32 | 4.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[31]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 19 | 32 | 1.68 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[31]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 18 | 32 | 1.78 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_1[0] | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 26 | 32 | 1.23 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_push_addr_reg1_out | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg0 | 5 | 33 | 6.60 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_multicast_accumulator/pm_tick_d1 | | 16 | 33 | 2.06 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/counter_msb[23]_i_1__52_n_0 | 5 | 33 | 6.60 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_jabber_accumulator/counter_msb[23]_i_1__8_n_0 | 5 | 33 | 6.60 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/s_ready_i_reg_0 | | 6 | 33 | 5.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/pm_tick_d1 | | 12 | 33 | 2.75 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 17 | 33 | 1.94 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/p_1_in | | 6 | 33 | 5.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_xfer_reg_ns | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_mmap_reset_reg | 9 | 33 | 3.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_bytes_accumulator/counter_msb[23]_i_1__42_n_0 | 6 | 33 | 5.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[31]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 18 | 32 | 1.78 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/user_reg1_r[31]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 16 | 32 | 2.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/user_reg0_r[31]_i_1_n_0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 11 | 32 | 2.91 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_ENCODER/dataout0[54]_i_1_n_0 | 13 | 32 | 2.46 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_addr_cntr_lsh_im0[15]_i_1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_mmap_reset_reg | 7 | 32 | 4.57 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_push_input_reg11_out | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_mmap_reset_reg | 11 | 32 | 2.91 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_FTYPE_PARSER/ena | | 9 | 32 | 3.56 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_TX_FCS/o_crc0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 15 | 32 | 2.13 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/fcs_crc_hold0 | | 11 | 32 | 2.91 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/arready_d12 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 | 3 | 32 | 10.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/rvalid | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/REG_HRD_RST/scndry_out | 15 | 32 | 2.13 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_arready0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/AXI_Reset0 | 9 | 32 | 3.56 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_wdata0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 15 | 32 | 2.13 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_rvalid0 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/AXI_Reset0 | 10 | 32 | 3.20 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/aw.aw_pipe/m_valid_i_reg_inv_0 | | 6 | 32 | 5.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_FCS/ena_d2 | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_FCS/reset_flop_out | 16 | 32 | 2.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_bytes_accumulator/pm_tick_d1 | | 12 | 32 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_pkt_fifo_cc.axis_pkt_cnt[0]_i_1_n_0 | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/gaxis_rst_sync.xpm_cdc_sync_rst_inst/syncstages_ff[3] | 4 | 32 | 8.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/p_1_in | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 12 | 32 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_packets_accumulator/pm_tick_d1 | | 11 | 32 | 2.91 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/sig_btt_eq_0_reg[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/SR[0] | 7 | 32 | 4.57 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/counter_msb[23]_i_1__52_n_0 | 7 | 32 | 4.57 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 23 | 32 | 1.39 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_1[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 26 | 32 | 1.23 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_2[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 23 | 32 | 1.39 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/m_valid_i_reg_0[0] | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N[0] | 19 | 32 | 1.68 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_mmu/inst/register_slice_inst/ar.ar_pipe/m_valid_i_reg_inv_0 | | 6 | 32 | 5.33 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/wr_en0 | | 10 | 32 | 3.20 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_framing_err_accumulator/pm_tick_d1 | | 12 | 33 | 2.75 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_jabber_accumulator/counter_msb[23]_i_1__8_n_0 | 4 | 33 | 8.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/counter_msb[23]_i_1__38_n_0 | 5 | 33 | 6.60 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/wr_en0 | | 10 | 33 | 3.30 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_push_addr_reg1_out | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg0 | 7 | 33 | 4.71 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/peripheral_aresetn[0] | 20 | 33 | 1.65 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/counter_msb[23]_i_1_n_0 | 4 | 33 | 8.25 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/p_1_in | | 10 | 33 | 3.30 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/counter_msb[23]_i_1__16_n_0 | 6 | 33 | 5.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_xfer_reg_ns | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_mmap_reset_reg | 9 | 33 | 3.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/s_ready_i_reg_0 | | 10 | 33 | 3.30 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_broadcast_accumulator/pm_tick_d1 | | 11 | 33 | 3.00 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_ctl_reg_rx_clk_write_hold_syncer/dataout_reg | | 22 | 34 | 1.55 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/p_1_in | | 6 | 34 | 5.67 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/si_rs_rready | | 6 | 34 | 5.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/areset_d_reg_n_0_[0] | 10 | 34 | 3.40 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_test_pattern_mismatch_accumulator/counter_msb[23]_i_1__50_n_0 | 7 | 34 | 4.86 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_toolong_accumulator/pm_tick_d1 | | 11 | 34 | 3.09 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 9 | 34 | 3.78 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/p_1_in | | 9 | 34 | 3.78 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/out | 12 | 34 | 2.83 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_packets_accumulator/pm_tick_d1 | | 15 | 35 | 2.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/counter_msb[23]_i_1__34_n_0 | 6 | 35 | 5.83 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_2048_4095_bytes_accumulator/pm_tick_d1 | | 11 | 36 | 3.27 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AREADY_I_reg_0 | | 16 | 36 | 2.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_small_accumulator/counter_msb[23]_i_1__51_n_0 | 5 | 36 | 7.20 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1 | | 15 | 37 | 2.47 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/pm_tick_d1 | | 12 | 37 | 3.08 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_packets_accumulator/pm_tick_d1 | | 15 | 37 | 2.47 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/pm_tick_d1 | | 19 | 38 | 2.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 14 | 38 | 2.71 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_push_input_reg13_out | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_1[0] | 9 | 39 | 4.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_4096_8191_bytes_accumulator/counter_msb[23]_i_1__29_n_0 | 7 | 39 | 5.57 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/si_register_slice_inst/aw.aw_pipe/E[0] | | 5 | 39 | 7.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_bytes_accumulator/counter_msb[23]_i_1__6_n_0 | 6 | 39 | 6.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/pm_tick_d1 | | 17 | 40 | 2.35 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_chcmd_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_2[0] | 10 | 40 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/FIFO_Full_reg | | 3 | 40 | 13.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/register_slice_inst/aw.aw_pipe/m_valid_i_reg_inv_0 | | 6 | 40 | 6.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_64_bytes_accumulator/pm_tick_d1 | | 16 | 41 | 2.56 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/si_register_slice_inst/ar.ar_pipe/E[0] | | 7 | 41 | 5.86 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/counter_msb[23]_i_1__38_n_0 | 7 | 41 | 5.86 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/pm_tick_d1 | | 16 | 41 | 2.56 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/counter_msb[23]_i_1__36_n_0 | 6 | 42 | 7.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1523_1548_bytes_accumulator/pm_tick_d1 | | 14 | 42 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_cycle_accumulator/pm_tick_d1 | | 13 | 42 | 3.23 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_bytes_accumulator/pm_tick_d1 | | 18 | 42 | 2.33 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/register_slice_inst/ar.ar_pipe/m_valid_i_reg_inv_0 | | 8 | 42 | 5.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_64_bytes_accumulator/pm_tick_d1 | | 14 | 42 | 3.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/si_rs_rready | | 9 | 34 | 3.78 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/pm_tick_d1 | | 15 | 35 | 2.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/pm_tick_d1 | | 16 | 35 | 2.19 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup | | 6 | 36 | 6.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AREADY_I_reg_0 | | 20 | 36 | 1.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_packets_accumulator/pm_tick_d1 | | 14 | 37 | 2.64 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_multicast_accumulator/pm_tick_d1 | | 12 | 37 | 3.08 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/counter_msb[23]_i_1__36_n_0 | 7 | 37 | 5.29 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/pm_tick_d1 | | 14 | 38 | 2.71 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/pm_tick_d1 | | 18 | 38 | 2.11 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_packets_accumulator/counter_msb[23]_i_1__1_n_0 | 7 | 38 | 5.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_toolong_accumulator/pm_tick_d1 | | 14 | 38 | 2.71 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/AXI_Reset | 12 | 38 | 3.17 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_jabber_accumulator/pm_tick_d1 | | 19 | 39 | 2.05 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_push_input_reg13_out | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_1[0] | 6 | 39 | 6.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_chcmd_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_2[0] | 11 | 40 | 3.64 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/si_register_slice_inst/aw.aw_pipe/E[0] | | 7 | 40 | 5.71 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_256_511_bytes_accumulator/pm_tick_d1 | | 15 | 40 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/si_register_slice_inst/ar.ar_pipe/E[0] | | 9 | 41 | 4.56 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sel | | 3 | 41 | 13.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_64_bytes_accumulator/pm_tick_d1 | | 15 | 41 | 2.73 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_mmu/inst/register_slice_inst/aw.aw_pipe/m_valid_i_reg_inv_0 | | 8 | 41 | 5.12 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1519_1522_bytes_accumulator/pm_tick_d1 | | 18 | 42 | 2.33 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_mmu/inst/register_slice_inst/ar.ar_pipe/m_valid_i_reg_inv_0 | | 10 | 42 | 4.20 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1549_2047_bytes_accumulator/pm_tick_d1 | | 16 | 42 | 2.62 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_cmd2addr_valid_reg | | 3 | 42 | 14.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/pm_tick_d1 | | 14 | 42 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_128_255_bytes_accumulator/pm_tick_d1 | | 19 | 43 | 2.26 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_4096_8191_bytes_accumulator/pm_tick_d1 | | 13 | 43 | 3.31 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_push_addr_reg1_out | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_13[0] | 5 | 43 | 8.60 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_test_pattern_mismatch_accumulator/pm_tick_d1 | | 16 | 43 | 2.69 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_fcs_accumulator/pm_tick_d1 | | 17 | 43 | 2.53 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_small_accumulator/pm_tick_d1 | | 16 | 43 | 2.69 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_4096_8191_bytes_accumulator/pm_tick_d1 | | 17 | 43 | 2.53 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_broadcast_accumulator/pm_tick_d1 | | 13 | 44 | 3.38 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/FSM_sequential_state_reg[1]_0[0] | | 10 | 44 | 4.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_push_addr_reg1_out | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_15[0] | 5 | 44 | 8.80 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_bytes_accumulator/pm_tick_d1 | | 17 | 44 | 2.59 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/s_ready_i_reg_0 | | 10 | 44 | 4.40 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_csm_ld_xfer | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_cache_reg0 | 5 | 44 | 8.80 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/FSM_sequential_state_reg[1]_0[0] | | 11 | 44 | 4.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_256_511_bytes_accumulator/pm_tick_d1 | | 15 | 44 | 2.93 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_halt_reg_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg0 | 5 | 45 | 9.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AREADY_I_reg_0 | | 24 | 46 | 1.92 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/S_AXI_AREADY_I_reg_0 | | 20 | 46 | 2.30 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/E[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 12 | 46 | 3.83 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_csm_ld_xfer | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_cache_reg0 | 7 | 45 | 6.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_halt_reg_reg | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg0 | 4 | 45 | 11.25 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/S_AXI_AREADY_I_reg_0 | | 21 | 46 | 2.19 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/ram_wr_en_i | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 11 | 46 | 4.18 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_512_1023_bytes_accumulator/pm_tick_d1 | | 17 | 46 | 2.71 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/ram_wr_en_i | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 10 | 46 | 4.60 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 14 | 47 | 3.36 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg[0] | | 13 | 47 | 3.62 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/timeout_counter | 18 | 47 | 2.61 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_vlan_accumulator/pm_tick_d1 | | 20 | 47 | 2.35 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_inrangeerr_accumulator/pm_tick_d1 | | 19 | 48 | 2.53 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | | 3 | 48 | 16.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/E[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 10 | 46 | 4.60 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AREADY_I_reg_0 | | 21 | 46 | 2.19 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/ram_wr_en_i | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 12 | 46 | 3.83 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/timeout_counter | 23 | 47 | 2.04 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | | 3 | 48 | 16.00 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/p_1_in | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 10 | 48 | 4.80 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | | 3 | 48 | 16.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1549_2047_bytes_accumulator/counter_msb[23]_i_1__30_n_0 | 7 | 48 | 6.86 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | | 3 | 48 | 16.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | | 3 | 48 | 16.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/pm_tick_d1 | | 19 | 49 | 2.58 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg[0] | | 6 | 49 | 8.17 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 9 | 49 | 5.44 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1549_2047_bytes_accumulator/pm_tick_d1 | | 19 | 49 | 2.58 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_128_255_bytes_accumulator/pm_tick_d1 | | 23 | 49 | 2.13 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_packets_accumulator/pm_tick_d1 | | 19 | 50 | 2.63 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_4096_8191_bytes_accumulator/pm_tick_d1 | | 19 | 50 | 2.63 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1519_1522_bytes_accumulator/counter_msb[23]_i_1__17_n_0 | 8 | 50 | 6.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_fcs_accumulator/counter_msb[23]_i_1__26_n_0 | 7 | 50 | 7.14 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/counter_msb[23]_i_1__5_n_0 | 8 | 50 | 6.25 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_65_127_bytes_accumulator/pm_tick_d1 | | 20 | 50 | 2.50 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/p_1_in | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 9 | 50 | 5.56 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/pm_tick_d1 | | 18 | 51 | 2.83 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_broadcast_accumulator/pm_tick_d1 | | 20 | 52 | 2.60 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_fcs_accumulator/pm_tick_d1 | | 26 | 53 | 2.04 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_oversize_accumulator/pm_tick_d1 | | 21 | 54 | 2.57 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_vlan_accumulator/pm_tick_d1 | | 26 | 55 | 2.12 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/pm_tick_d1 | | 22 | 55 | 2.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_bytes_accumulator/pm_tick_d1 | | 21 | 55 | 2.62 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/pm_tick_d1 | | 20 | 56 | 2.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_unicast_accumulator/pm_tick_d1 | | 17 | 56 | 3.29 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_bad_fcs_accumulator/pm_tick_d1 | | 23 | 56 | 2.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_bytes_accumulator/pm_tick_d1 | | 21 | 57 | 2.71 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/pm_tick_d1 | | 21 | 57 | 2.71 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_ENCODER/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_SCRAMBLER/reset_flop_out | 24 | 58 | 2.42 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_broadcast_accumulator/pm_tick_d1 | | 21 | 58 | 2.76 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1549_2047_bytes_accumulator/pm_tick_d1 | | 24 | 58 | 2.42 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_jabber_accumulator/pm_tick_d1 | | 20 | 58 | 2.90 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AREADY_I_reg_0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 17 | 58 | 3.41 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_rr_reg_9[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_ctl0_p5_r_reg[1]_0 | 25 | 60 | 2.40 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_code_accumulator/pm_tick_d1 | | 23 | 60 | 2.61 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/E[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 20 | 61 | 3.05 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/pm_tick_d1 | | 22 | 61 | 2.77 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/S_AXI_AREADY_I_reg_0 | | 28 | 61 | 2.18 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1519_1522_bytes_accumulator/pm_tick_d1 | | 27 | 62 | 2.30 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/pm_tick_d1 | | 19 | 63 | 3.32 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 26 | 63 | 2.42 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 37 | 64 | 1.73 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d1 | | 25 | 64 | 2.56 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | | 8 | 64 | 8.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_en | | 10 | 64 | 6.40 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/pm_tick_d1 | | 24 | 64 | 2.67 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup4 | | 10 | 64 | 6.40 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/datain0_r | | 14 | 64 | 4.57 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/i_RX_64B66B_CHECKER/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DECODER/reset_flop_out | 28 | 64 | 2.29 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | | 8 | 64 | 8.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/pm_tick_d1 | | 30 | 65 | 2.17 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DELETE_FCS/tstamp_d2_nxt | | 16 | 66 | 4.12 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_TX_FCS/z_ena[1] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 28 | 67 | 2.39 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_multicast_accumulator/pm_tick_d1 | | 26 | 67 | 2.58 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AREADY_I_reg_0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 23 | 68 | 2.96 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | | 3 | 48 | 16.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_large_accumulator/pm_tick_d1 | | 17 | 48 | 2.82 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_4096_8191_bytes_accumulator/pm_tick_d1 | | 21 | 48 | 2.29 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/pm_tick_d1 | | 24 | 49 | 2.04 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg[0] | | 8 | 49 | 6.12 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 8 | 49 | 6.12 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_64_bytes_accumulator/pm_tick_d1 | | 22 | 49 | 2.23 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 15 | 49 | 3.27 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg[0] | | 15 | 49 | 3.27 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/p_1_in | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 10 | 50 | 5.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/p_1_in | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 13 | 50 | 3.85 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_128_255_bytes_accumulator/pm_tick_d1 | | 20 | 50 | 2.50 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_65_127_bytes_accumulator/pm_tick_d1 | | 17 | 50 | 2.94 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/pm_tick_d1 | | 21 | 50 | 2.38 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_fragment_accumulator/pm_tick_d1 | | 22 | 51 | 2.32 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_vlan_accumulator/pm_tick_d1 | | 19 | 51 | 2.68 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_inrangeerr_accumulator/pm_tick_d1 | | 23 | 51 | 2.22 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/pm_tick_d1 | | 20 | 52 | 2.60 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_512_1023_bytes_accumulator/pm_tick_d1 | | 25 | 52 | 2.08 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_bytes_accumulator/pm_tick_d1 | | 13 | 52 | 4.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/pm_tick_d1 | | 21 | 53 | 2.52 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_65_127_bytes_accumulator/pm_tick_d1 | | 20 | 53 | 2.65 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_multicast_accumulator/pm_tick_d1 | | 23 | 54 | 2.35 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/pm_tick_d1 | | 24 | 54 | 2.25 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1523_1548_bytes_accumulator/pm_tick_d1 | | 21 | 56 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1 | | 24 | 57 | 2.38 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_vlan_accumulator/pm_tick_d1 | | 17 | 57 | 3.35 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/pm_tick_d1 | | 23 | 57 | 2.48 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AREADY_I_reg_0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 20 | 58 | 2.90 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_ENCODER/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_SCRAMBLER/reset_flop_out | 22 | 58 | 2.64 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/pm_tick_d1 | | 21 | 60 | 2.86 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/pm_tick_d1 | | 22 | 60 | 2.73 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_rr_reg_9[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_ctl0_p5_r_reg[1]_0 | 27 | 60 | 2.22 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_cycle_accumulator/pm_tick_d1 | | 22 | 60 | 2.73 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/E[0] | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/aresetn_d | 16 | 61 | 3.81 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_packets_accumulator/pm_tick_d1 | | 24 | 61 | 2.54 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/S_AXI_AREADY_I_reg_0 | | 25 | 61 | 2.44 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_code_accumulator/pm_tick_d1 | | 23 | 63 | 2.74 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | | 9 | 64 | 7.11 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | | 9 | 64 | 7.11 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/datain0_r | | 19 | 64 | 3.37 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d1 | | 24 | 64 | 2.67 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/i_RX_64B66B_CHECKER/E[0] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RESET_FLOP_DECODER/reset_flop_out | 34 | 64 | 1.88 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 23 | 64 | 2.78 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 33 | 64 | 1.94 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_en | | 11 | 64 | 5.82 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DELETE_FCS/tstamp_d2_nxt | | 15 | 66 | 4.40 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_bad_fcs_accumulator/pm_tick_d1 | | 26 | 66 | 2.54 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/i_TX_FCS/z_ena[1] | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 30 | 67 | 2.23 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/S_AXI_AREADY_I_reg_0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 28 | 68 | 2.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1549_2047_bytes_accumulator/pm_tick_d1 | | 21 | 68 | 3.24 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AREADY_I_reg_0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 23 | 68 | 2.96 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_unicast_accumulator/pm_tick_d1 | | 23 | 70 | 3.04 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_fwft.ram_regout_en | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 20 | 72 | 3.60 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_fwft.ram_regout_en | pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 15 | 72 | 4.80 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_fwft.ram_regout_en | pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 16 | 72 | 4.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_pipes_r_b | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/datain0_p0_r | 14 | 72 | 5.14 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_s_ready_dup | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 21 | 73 | 3.48 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_out_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_mvalid_stop_reg_reg[0] | 21 | 73 | 3.48 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_pipes_r_b | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/datain0_p0_r | 20 | 72 | 3.60 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_oversize_accumulator/pm_tick_d1 | | 26 | 72 | 2.77 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_out_reg_0[0] | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/SR[0] | 21 | 73 | 3.48 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out[63]_i_2__1_n_0 | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/SR[0] | 19 | 73 | 3.84 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_s_ready_dup | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 20 | 73 | 3.65 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_s_ready_dup | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO_2/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 | 19 | 73 | 3.84 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/dmacr_i_reg[0][0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/queue_sinit20_out | 22 | 75 | 3.41 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_wren2_new | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/queue_sinit20_out | 22 | 75 | 3.41 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/pm_tick_d1 | | 30 | 74 | 2.47 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/pm_tick_d1 | | 30 | 75 | 2.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_wren2_new | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/queue_sinit20_out | 21 | 75 | 3.57 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/dmacr_i_reg[0][0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/queue_sinit20_out | 21 | 75 | 3.57 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_s_ready_dup | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 12 | 78 | 6.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_data_reg_out_en | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 12 | 78 | 6.50 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | | 5 | 80 | 16.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | | 5 | 80 | 16.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_data_reg_out_en | pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/GEN_ASYNC_CMDSTAT_RESET.SEC2PRIM_RST_SYNCRO/sig_stream_rst | 13 | 78 | 6.00 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_0[0] | 29 | 80 | 2.76 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_fragment_accumulator/pm_tick_d1 | | 27 | 81 | 3.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_small_accumulator/pm_tick_d1 | | 24 | 81 | 3.38 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/S_AXI_AREADY_I_reg_0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 29 | 83 | 2.86 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/FSM_sequential_mm2s_cs_reg[1][0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_1[0] | 26 | 87 | 3.35 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_wren_new | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_1[0] | 26 | 87 | 3.35 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/tx_reset_pulse_len_reg_n_0_[0] | 44 | 96 | 2.18 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | | 5 | 80 | 16.00 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | | 5 | 80 | 16.00 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/S_AXI_AREADY_I_reg_0 | pl_eth_10g_i/zups/rst_ps8_0_99M/U0/interconnect_aresetn[0] | 31 | 83 | 2.68 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_wren_new | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_1[0] | 25 | 87 | 3.48 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_MM2S_SG_IF/GEN_UPDT_FOR_QUEUE.GEN_NO_MICRO_DMA.XFERRED_BYTE_FIFO/I_SRL_FIFO_RBU_F/FSM_sequential_mm2s_cs_reg[1][0] | pl_eth_10g_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.scndry_resetn_reg_1[0] | 24 | 87 | 3.62 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_128_255_bytes_accumulator/pm_tick_d1 | | 28 | 88 | 3.14 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/tx_reset_pulse_len_reg_n_0_[0] | 50 | 96 | 1.92 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DELETE_FCS/ctlfflt2out_ena | | 7 | 104 | 14.86 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_rx_2bit_retiming_sync_serdes_data_valid0_0/rx_serdes_datavalid0 | | 17 | 124 | 7.29 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_AXI_RESET_RX_SYNC/reset_pipe_out_0 | 39 | 128 | 3.28 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d2 | | 45 | 130 | 2.89 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 37 | 131 | 3.54 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.read_data_inst/m_valid_i_reg[0] | | 54 | 131 | 2.43 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_ctl_reg_tx_clk_write_hold_syncer/dataout_reg | | 88 | 131 | 1.49 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/s_ready_i_reg_0 | | 55 | 131 | 2.38 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg[0] | | 53 | 131 | 2.47 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.read_data_inst/E[0] | | 40 | 131 | 3.28 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/s_ready_i_reg_0 | | 40 | 131 | 3.28 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/r.r_pipe/s_ready_i_reg_0 | | 24 | 133 | 5.54 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/r.r_pipe/p_1_in_1 | | 24 | 133 | 5.54 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_pipes_r_b | | 37 | 138 | 3.73 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_AXI_RESET_RX_SYNC/reset_pipe_out_0 | 36 | 128 | 3.56 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/ena_d2 | | 47 | 130 | 2.77 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg[0] | | 54 | 131 | 2.43 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.read_data_inst/m_valid_i_reg[0] | | 53 | 131 | 2.47 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 40 | 131 | 3.28 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.read_data_inst/E[0] | | 37 | 131 | 3.54 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_ctl_reg_tx_clk_write_hold_syncer/dataout_reg | | 83 | 131 | 1.58 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/s_ready_i_reg_0 | | 53 | 131 | 2.47 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/s_ready_i_reg_0 | | 38 | 131 | 3.45 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/r.r_pipe/s_ready_i_reg_0 | | 22 | 133 | 6.05 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/r.r_pipe/p_1_in_1 | | 22 | 133 | 6.05 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_pipes_r_b | | 39 | 138 | 3.54 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/rx_reset_pulse_len_reg_n_0_[0] | 70 | 143 | 2.04 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg[0] | | 46 | 145 | 3.15 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 46 | 145 | 3.15 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/r.r_pipe/s_ready_i_reg_0 | | 44 | 147 | 3.34 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/r.r_pipe/s_ready_i_reg_0 | | 48 | 147 | 3.06 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/chosen_reg[1]_0[0] | | 48 | 147 | 3.06 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/chosen_reg[0]_0[0] | | 44 | 147 | 3.34 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_FCS/o_ena | | 20 | 150 | 7.50 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg[0] | | 39 | 145 | 3.72 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 40 | 145 | 3.62 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/chosen_reg[1]_0[0] | | 44 | 147 | 3.34 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/chosen_reg[0]_0[0] | | 40 | 147 | 3.67 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/r.r_pipe/s_ready_i_reg_0 | | 44 | 147 | 3.34 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/r.r_pipe/s_ready_i_reg_0 | | 39 | 147 | 3.77 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_FCS/o_ena | | 16 | 150 | 9.38 | | pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | | 10 | 160 | 16.00 | | pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | | 11 | 176 | 16.00 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_pipes_r_b | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 66 | 204 | 3.09 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 147 | 389 | 2.65 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_AXI_RESET_TX_SYNC/reset_pipe_out | 119 | 412 | 3.46 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_rr_b | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 106 | 434 | 4.09 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | | 192 | 559 | 2.91 | -| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | | 287 | 1011 | 3.52 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0] | | 334 | 1152 | 3.45 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | | 380 | 1363 | 3.59 | -| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0] | | 514 | 1680 | 3.27 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_pipes_r_b | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 62 | 204 | 3.29 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 146 | 389 | 2.66 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_AXI_RESET_TX_SYNC/reset_pipe_out | 112 | 412 | 3.68 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/stall_rr_b | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out | 105 | 434 | 4.13 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | | | 197 | 559 | 2.84 | +| pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk0 | | | 305 | 1011 | 3.31 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0] | | 336 | 1152 | 3.43 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | | | 376 | 1363 | 3.62 | +| pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/CLK | pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0] | | 498 | 1680 | 3.37 | +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_opted.rpt b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_opted.rpt index 03cf714..5fdb182 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_opted.rpt +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_opted.rpt @@ -1,7 +1,7 @@ Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -| Date : Fri Oct 20 12:56:22 2023 +| Date : Fri Oct 20 19:43:48 2023 | Host : DESKTOP-5FH9OH3 running 64-bit major release (build 9200) | Command : report_drc -file pl_eth_10g_wrapper_drc_opted.rpt -pb pl_eth_10g_wrapper_drc_opted.pb -rpx pl_eth_10g_wrapper_drc_opted.rpx | Design : pl_eth_10g_wrapper diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_opted.rpx b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_opted.rpx index 23769b8..a8b0568 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_opted.rpx and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_opted.rpx differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_routed.rpt b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_routed.rpt index 24e2e91..fc4aa43 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_routed.rpt +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -| Date : Fri Oct 20 13:01:00 2023 +| Date : Fri Oct 20 19:48:05 2023 | Host : DESKTOP-5FH9OH3 running 64-bit major release (build 9200) | Command : report_drc -file pl_eth_10g_wrapper_drc_routed.rpt -pb pl_eth_10g_wrapper_drc_routed.pb -rpx pl_eth_10g_wrapper_drc_routed.rpx | Design : pl_eth_10g_wrapper @@ -43,13 +43,13 @@ pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_c pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, -pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, -pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb (the first 15 of 67 listed). diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_routed.rpx b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_routed.rpx index b28f430..c13fe9d 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_routed.rpx and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_routed.rpx differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_io_placed.rpt b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_io_placed.rpt index 6d07191..d5482a9 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_io_placed.rpt +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_io_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -| Date : Fri Oct 20 12:58:41 2023 +| Date : Fri Oct 20 19:45:58 2023 | Host : DESKTOP-5FH9OH3 running 64-bit major release (build 9200) | Command : report_io -file pl_eth_10g_wrapper_io_placed.rpt | Design : pl_eth_10g_wrapper diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_methodology_drc_routed.rpt b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_methodology_drc_routed.rpt index 65f8c78..ccffc65 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_methodology_drc_routed.rpt +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_methodology_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -| Date : Fri Oct 20 13:01:13 2023 +| Date : Fri Oct 20 19:48:15 2023 | Host : DESKTOP-5FH9OH3 running 64-bit major release (build 9200) | Command : report_methodology -file pl_eth_10g_wrapper_methodology_drc_routed.rpt -pb pl_eth_10g_wrapper_methodology_drc_routed.pb -rpx pl_eth_10g_wrapper_methodology_drc_routed.rpx | Design : pl_eth_10g_wrapper @@ -152,7 +152,7 @@ pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simp pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]/CLR - (the first 15 of 29 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. + (the first 15 of 32 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#12 Warning @@ -212,7 +212,7 @@ pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simp pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]/CLR - (the first 15 of 33 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. + (the first 15 of 32 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#15 Warning @@ -232,7 +232,7 @@ pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simp pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]/CLR - (the first 15 of 34 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. + (the first 15 of 32 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: TIMING-9#1 Warning diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_methodology_drc_routed.rpx b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_methodology_drc_routed.rpx index 8cf6214..26c03fb 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_methodology_drc_routed.rpx and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_methodology_drc_routed.rpx differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_opt.dcp b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_opt.dcp index 0b9b847..fa02146 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_opt.dcp and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_opt.dcp differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_physopt.dcp b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_physopt.dcp index a2f7216..4d3b039 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_physopt.dcp and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_physopt.dcp differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_placed.dcp b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_placed.dcp index 5c907ab..d03548d 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_placed.dcp and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_placed.dcp differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_power_routed.rpt b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_power_routed.rpt index 2faf476..6f1f57b 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_power_routed.rpt +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_power_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -| Date : Fri Oct 20 13:01:30 2023 +| Date : Fri Oct 20 19:48:30 2023 | Host : DESKTOP-5FH9OH3 running 64-bit major release (build 9200) | Command : report_power -file pl_eth_10g_wrapper_power_routed.rpt -pb pl_eth_10g_wrapper_power_summary_routed.pb -rpx pl_eth_10g_wrapper_power_routed.rpx | Design : pl_eth_10g_wrapper @@ -30,14 +30,14 @@ Table of Contents ---------- +--------------------------+--------------+ -| Total On-Chip Power (W) | 4.136 | +| Total On-Chip Power (W) | 4.137 | | Design Power Budget (W) | Unspecified* | | Power Budget Margin (W) | NA | -| Dynamic (W) | 3.400 | +| Dynamic (W) | 3.401 | | Device Static (W) | 0.735 | | Effective TJA (C/W) | 1.0 | -| Max Ambient (C) | 96.0 | -| Junction Temperature (C) | 29.0 | +| Max Ambient (C) | 95.9 | +| Junction Temperature (C) | 29.1 | | Confidence Level | Medium | | Setting File | --- | | Simulation Activity File | --- | @@ -52,25 +52,25 @@ Table of Contents +--------------------------+-----------+----------+-----------+-----------------+ | On-Chip | Power (W) | Used | Available | Utilization (%) | +--------------------------+-----------+----------+-----------+-----------------+ -| Clocks | 0.147 | 12 | --- | --- | -| CLB Logic | 0.047 | 52898 | --- | --- | -| LUT as Logic | 0.038 | 17389 | 230400 | 7.55 | -| Register | 0.005 | 27874 | 460800 | 6.05 | +| Clocks | 0.146 | 12 | --- | --- | +| CLB Logic | 0.047 | 52920 | --- | --- | +| LUT as Logic | 0.037 | 17387 | 230400 | 7.55 | +| Register | 0.005 | 27890 | 460800 | 6.05 | | LUT as Distributed RAM | 0.002 | 430 | 101760 | 0.42 | -| LUT as Shift Register | 0.001 | 384 | 101760 | 0.38 | -| CARRY8 | 0.001 | 677 | 28800 | 2.35 | +| LUT as Shift Register | 0.001 | 386 | 101760 | 0.38 | +| CARRY8 | 0.001 | 678 | 28800 | 2.35 | | BUFG | <0.001 | 3 | 64 | 4.69 | -| Others | 0.000 | 1191 | --- | --- | -| F7/F8 Muxes | 0.000 | 133 | 230400 | 0.06 | -| Signals | 0.058 | 46935 | --- | --- | +| Others | 0.000 | 1193 | --- | --- | +| F7/F8 Muxes | 0.000 | 132 | 230400 | 0.06 | +| Signals | 0.057 | 46963 | --- | --- | | Block RAM | 0.067 | 137 | 312 | 43.91 | | I/O | 0.006 | 1 | 360 | 0.28 | | GTH | 0.306 | 1 | 20 | 5.00 | -| PS8 | 2.769 | 1 | --- | --- | +| PS8 | 2.772 | 1 | --- | --- | | Static Power | 0.735 | | | | | PS Static | 0.099 | | | | | PL Static | 0.636 | | | | -| Total | 4.136 | | | | +| Total | 4.137 | | | | +--------------------------+-----------+----------+-----------+-----------------+ @@ -80,7 +80,7 @@ Table of Contents +-----------------+-------------+-----------+-------------+------------+-------------+-------------+------------+ | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | +-----------------+-------------+-----------+-------------+------------+-------------+-------------+------------+ -| Vccint | 0.850 | 0.576 | 0.419 | 0.157 | NA | Unspecified | NA | +| Vccint | 0.850 | 0.573 | 0.417 | 0.157 | NA | Unspecified | NA | | Vccint_io | 0.850 | 0.072 | 0.001 | 0.071 | NA | Unspecified | NA | | Vccbram | 0.850 | 0.002 | 0.000 | 0.002 | NA | Unspecified | NA | | Vccaux | 1.800 | 0.147 | 0.000 | 0.147 | NA | Unspecified | NA | @@ -94,7 +94,7 @@ Table of Contents | Vcco10 | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vccadc | 1.800 | 0.008 | 0.000 | 0.008 | NA | Unspecified | NA | | VCC_PSINTFP | 0.850 | 1.091 | 1.055 | 0.035 | NA | Unspecified | NA | -| VCC_PSINTLP | 0.850 | 0.284 | 0.277 | 0.007 | NA | Unspecified | NA | +| VCC_PSINTLP | 0.850 | 0.287 | 0.280 | 0.007 | NA | Unspecified | NA | | VPS_MGTRAVCC | 0.850 | 0.190 | 0.189 | 0.001 | NA | Unspecified | NA | | VCC_PSINTFP_DDR | 0.850 | 0.730 | 0.726 | 0.004 | NA | Unspecified | NA | | VCC_PSPLL | 1.200 | 0.075 | 0.073 | 0.002 | NA | Unspecified | NA | @@ -176,20 +176,20 @@ Table of Contents +-------------------------+-----------+ | Name | Power (W) | +-------------------------+-----------+ -| pl_eth_10g_wrapper | 3.400 | -| pl_eth_10g_i | 3.400 | +| pl_eth_10g_wrapper | 3.401 | +| pl_eth_10g_i | 3.401 | | axi_dma_0 | 0.033 | | U0 | 0.033 | | rx_data_fifo | 0.036 | | inst | 0.036 | | tx_data_fifo | 0.036 | | inst | 0.036 | -| xxv_ethernet_0 | 0.468 | -| inst | 0.468 | -| zups | 2.827 | -| axi_pl_ps | 0.028 | -| ps_axi_periph | 0.028 | -| zynq_ultra_ps_e_0 | 2.771 | +| xxv_ethernet_0 | 0.467 | +| inst | 0.467 | +| zups | 2.829 | +| axi_pl_ps | 0.027 | +| ps_axi_periph | 0.027 | +| zynq_ultra_ps_e_0 | 2.774 | +-------------------------+-----------+ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_power_routed.rpx b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_power_routed.rpx index cdd69d1..bae46c2 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_power_routed.rpx and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_power_routed.rpx differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_power_summary_routed.pb b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_power_summary_routed.pb index 48226ed..d0bbc3a 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_power_summary_routed.pb and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_power_summary_routed.pb differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_route_status.pb b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_route_status.pb index deb7035..5050007 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_route_status.pb and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_route_status.pb differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_route_status.rpt b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_route_status.rpt index 5dfe5a7..a5f9ee1 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_route_status.rpt +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_route_status.rpt @@ -1,12 +1,12 @@ Design Route Status : # nets : ------------------------------------------- : ----------- : - # of logical nets.......................... : 61138 : - # of nets not needing routing.......... : 14189 : - # of internally routed nets........ : 13798 : - # of nets with no loads............ : 391 : - # of routable nets..................... : 46949 : - # of fully routed nets............. : 46949 : + # of logical nets.......................... : 61161 : + # of nets not needing routing.......... : 14184 : + # of internally routed nets........ : 13796 : + # of nets with no loads............ : 388 : + # of routable nets..................... : 46977 : + # of fully routed nets............. : 46977 : # of nets with routing errors.......... : 0 : ------------------------------------------- : ----------- : diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_routed.dcp b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_routed.dcp index 3b7652d..552355a 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_routed.dcp and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_routed.dcp differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_timing_summary_routed.pb b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_timing_summary_routed.pb index 5bc6461..faa8ca3 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_timing_summary_routed.pb and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_timing_summary_routed.pb differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_timing_summary_routed.rpt b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_timing_summary_routed.rpt index d9bb4ee..713f1ac 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_timing_summary_routed.rpt +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_timing_summary_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -| Date : Fri Oct 20 13:01:32 2023 +| Date : Fri Oct 20 19:48:32 2023 | Host : DESKTOP-5FH9OH3 running 64-bit major release (build 9200) | Command : report_timing_summary -max_paths 10 -file pl_eth_10g_wrapper_timing_summary_routed.rpt -pb pl_eth_10g_wrapper_timing_summary_routed.pb -rpx pl_eth_10g_wrapper_timing_summary_routed.rpx -warn_on_violation | Design : pl_eth_10g_wrapper @@ -129,7 +129,7 @@ Table of Contents WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - 1.423 0.000 0 74208 0.011 0.000 0 74136 0.351 0.000 0 29530 + 0.870 0.000 0 74257 0.010 0.000 0 74185 0.351 0.000 0 29549 All user specified timing constraints are met. @@ -161,12 +161,12 @@ gt_ref_clk {0.000 3.200} 6.400 156.25 Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -clk_pl_0 3.050 0.000 0 22468 0.011 0.000 0 22468 2.200 0.000 0 9037 +clk_pl_0 2.928 0.000 0 22484 0.012 0.000 0 22484 2.200 0.000 0 9043 rxoutclk_out[0] 0.371 0.000 0 3 - Net 1.423 0.000 0 27907 0.011 0.000 0 27907 0.541 0.000 0 11334 - rxoutclkpcs_out[0] 2.121 0.000 0 34 0.022 0.000 0 34 1.277 0.000 0 15 + Net 0.870 0.000 0 27940 0.011 0.000 0 27940 0.541 0.000 0 11347 + rxoutclkpcs_out[0] 2.002 0.000 0 34 0.068 0.000 0 34 1.277 0.000 0 15 txoutclk_out[0] 0.351 0.000 0 3 - xxv_ethernet_0_tx_clk_out_0 1.643 0.000 0 23315 0.011 0.000 0 23315 0.523 0.000 0 9138 + xxv_ethernet_0_tx_clk_out_0 1.572 0.000 0 23315 0.010 0.000 0 23315 0.523 0.000 0 9138 ------------------------------------------------------------------------------------------------ @@ -176,10 +176,10 @@ clk_pl_0 3.050 0.000 From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -Net clk_pl_0 5.389 0.000 0 52 -xxv_ethernet_0_tx_clk_out_0 clk_pl_0 5.358 0.000 0 48 -clk_pl_0 Net 6.864 0.000 0 20 -clk_pl_0 xxv_ethernet_0_tx_clk_out_0 7.264 0.000 0 16 +Net clk_pl_0 5.329 0.000 0 52 +xxv_ethernet_0_tx_clk_out_0 clk_pl_0 5.906 0.000 0 48 +clk_pl_0 Net 6.958 0.000 0 20 +clk_pl_0 xxv_ethernet_0_tx_clk_out_0 7.432 0.000 0 16 ------------------------------------------------------------------------------------------------ @@ -189,9 +189,9 @@ clk_pl_0 xxv_ethernet_0_tx_clk_out_0 7.264 0.0 Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -**async_default** Net Net 5.132 0.000 0 67 0.104 0.000 0 67 -**async_default** clk_pl_0 clk_pl_0 6.418 0.000 0 301 0.138 0.000 0 301 -**async_default** xxv_ethernet_0_tx_clk_out_0 xxv_ethernet_0_tx_clk_out_0 5.276 0.000 0 44 0.149 0.000 0 44 +**async_default** Net Net 5.152 0.000 0 67 0.114 0.000 0 67 +**async_default** clk_pl_0 clk_pl_0 6.463 0.000 0 301 0.096 0.000 0 301 +**async_default** xxv_ethernet_0_tx_clk_out_0 xxv_ethernet_0_tx_clk_out_0 5.646 0.000 0 44 0.154 0.000 0 44 ------------------------------------------------------------------------------------------------ @@ -204,34 +204,34 @@ Path Group From Clock To Clock From Clock: clk_pl_0 To Clock: clk_pl_0 -Setup : 0 Failing Endpoints, Worst Slack 3.050ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 2.928ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.012ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 2.200ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 3.050ns (required time - arrival time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[10]/C +Slack (MET) : 2.928ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data_reg[4]/D + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r_reg[38]/CE (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 4.772ns (logic 0.496ns (10.394%) route 4.276ns (89.606%)) - Logic Levels: 6 (LUT3=1 LUT5=1 LUT6=4) - Clock Path Skew: -0.081ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.898ns = ( 9.898 - 8.000 ) - Source Clock Delay (SCD): 2.083ns + Data Path Delay: 4.802ns (logic 0.268ns (5.581%) route 4.534ns (94.419%)) + Logic Levels: 3 (LUT2=1 LUT6=2) + Clock Path Skew: -0.088ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.029ns = ( 10.029 - 8.000 ) + Source Clock Delay (SCD): 2.221ns Clock Pessimism Removal (CPR): 0.104ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.875ns (routing 0.643ns, distribution 1.232ns) - Clock Net Delay (Destination): 1.730ns (routing 0.579ns, distribution 1.151ns) + Clock Net Delay (Source): 2.013ns (routing 0.643ns, distribution 1.370ns) + Clock Net Delay (Destination): 1.861ns (routing 0.579ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -241,31 +241,22 @@ Slack (MET) : 3.050ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.875 2.083 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk - SLICE_X51Y236 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[10]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 2.013 2.221 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X39Y244 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X51Y236 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 2.162 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[10]/Q - net (fo=118, routed) 2.433 4.595 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/p_0_in[10] - SLICE_X84Y137 LUT3 (Prop_D6LUT_SLICEM_I2_O) - 0.051 4.646 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[18]_i_15/O - net (fo=33, routed) 0.686 5.332 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[18]_i_15_n_0 - SLICE_X77Y178 LUT6 (Prop_H6LUT_SLICEL_I1_O) - 0.051 5.383 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_22/O - net (fo=15, routed) 0.330 5.713 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_cycle_accumulator/IP2Bus_Data[22]_i_4 - SLICE_X78Y173 LUT5 (Prop_B6LUT_SLICEM_I3_O) - 0.089 5.802 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_cycle_accumulator/IP2Bus_Data[4]_i_41/O - net (fo=1, routed) 0.139 5.941 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_test_pattern_mismatch_accumulator/IP2Bus_Data[4]_i_4_0 - SLICE_X78Y173 LUT6 (Prop_C6LUT_SLICEM_I5_O) - 0.051 5.992 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_test_pattern_mismatch_accumulator/IP2Bus_Data[4]_i_15/O - net (fo=1, routed) 0.265 6.257 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_packets_accumulator/IP2Bus_Data_reg[4]_1 - SLICE_X79Y165 LUT6 (Prop_H6LUT_SLICEM_I5_O) - 0.053 6.310 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_good_packets_accumulator/IP2Bus_Data[4]_i_4/O - net (fo=1, routed) 0.351 6.661 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_broadcast_accumulator/IP2Bus_Data_reg[4]_1 - SLICE_X78Y150 LUT6 (Prop_D6LUT_SLICEM_I3_O) - 0.122 6.783 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_broadcast_accumulator/IP2Bus_Data[4]_i_1/O - net (fo=1, routed) 0.072 6.855 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_broadcast_accumulator_n_33 - SLICE_X78Y150 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data_reg[4]/D + SLICE_X39Y244 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 2.300 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/Q + net (fo=92, routed) 2.647 4.947 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/p_0_in[7] + SLICE_X91Y174 LUT2 (Prop_D6LUT_SLICEL_I0_O) + 0.099 5.046 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3/O + net (fo=19, routed) 0.568 5.614 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3_n_0 + SLICE_X84Y205 LUT6 (Prop_H6LUT_SLICEM_I0_O) + 0.053 5.667 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2/O + net (fo=4, routed) 0.428 6.095 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2_n_0 + SLICE_X96Y189 LUT6 (Prop_D6LUT_SLICEM_I0_O) + 0.037 6.132 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_1/O + net (fo=26, routed) 0.891 7.023 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_1_n_0 + SLICE_X101Y175 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r_reg[38]/CE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -274,38 +265,38 @@ Slack (MET) : 3.050ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.730 9.898 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk - SLICE_X78Y150 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data_reg[4]/C - clock pessimism 0.104 10.002 - clock uncertainty -0.122 9.880 - SLICE_X78Y150 FDRE (Setup_DFF_SLICEM_C_D) - 0.025 9.905 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data_reg[4] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.861 10.029 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X101Y175 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r_reg[38]/C + clock pessimism 0.104 10.133 + clock uncertainty -0.122 10.011 + SLICE_X101Y175 FDRE (Setup_HFF_SLICEL_C_CE) + -0.060 9.951 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r_reg[38] ------------------------------------------------------------------- - required time 9.905 - arrival time -6.855 + required time 9.951 + arrival time -7.023 ------------------------------------------------------------------- - slack 3.050 + slack 2.928 -Slack (MET) : 3.082ns (required time - arrival time) - Source: pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C +Slack (MET) : 2.931ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[0]/R + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[6]/CE (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 4.556ns (logic 0.170ns (3.731%) route 4.386ns (96.269%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.166ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.922ns = ( 9.922 - 8.000 ) - Source Clock Delay (SCD): 2.192ns + Data Path Delay: 4.799ns (logic 0.321ns (6.689%) route 4.478ns (93.311%)) + Logic Levels: 3 (LUT2=1 LUT6=2) + Clock Path Skew: -0.088ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.029ns = ( 10.029 - 8.000 ) + Source Clock Delay (SCD): 2.221ns Clock Pessimism Removal (CPR): 0.104ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.984ns (routing 0.643ns, distribution 1.341ns) - Clock Net Delay (Destination): 1.754ns (routing 0.579ns, distribution 1.175ns) + Clock Net Delay (Source): 2.013ns (routing 0.643ns, distribution 1.370ns) + Clock Net Delay (Destination): 1.861ns (routing 0.579ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -315,16 +306,22 @@ Slack (MET) : 3.082ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.984 2.192 pl_eth_10g_i/zups/rst_ps8_0_99M/U0/slowest_sync_clk - SLICE_X88Y96 FDRE r pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 2.013 2.221 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X39Y244 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y96 FDRE (Prop_BFF2_SLICEM_C_Q) - 0.080 2.272 f pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q - net (fo=286, routed) 2.488 4.760 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/s_axi_aresetn_0 - SLICE_X57Y181 LUT1 (Prop_H6LUT_SLICEM_I0_O) - 0.090 4.850 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_awready_i_1/O - net (fo=65, routed) 1.898 6.748 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/AXI_Reset0 - SLICE_X40Y248 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[0]/R + SLICE_X39Y244 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 2.300 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/Q + net (fo=92, routed) 2.647 4.947 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/p_0_in[7] + SLICE_X91Y174 LUT2 (Prop_D6LUT_SLICEL_I0_O) + 0.099 5.046 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3/O + net (fo=19, routed) 0.568 5.614 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3_n_0 + SLICE_X84Y205 LUT6 (Prop_H6LUT_SLICEM_I0_O) + 0.053 5.667 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2/O + net (fo=4, routed) 0.433 6.100 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2_n_0 + SLICE_X94Y189 LUT6 (Prop_H6LUT_SLICEM_I0_O) + 0.090 6.190 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[31]_i_1/O + net (fo=32, routed) 0.830 7.020 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[31]_i_1_n_0 + SLICE_X102Y175 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -333,38 +330,38 @@ Slack (MET) : 3.082ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.754 9.922 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/dclk - SLICE_X40Y248 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[0]/C - clock pessimism 0.104 10.026 - clock uncertainty -0.122 9.904 - SLICE_X40Y248 FDRE (Setup_HFF2_SLICEL_C_R) - -0.074 9.830 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[0] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.861 10.029 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X102Y175 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[6]/C + clock pessimism 0.104 10.133 + clock uncertainty -0.122 10.011 + SLICE_X102Y175 FDRE (Setup_HFF_SLICEL_C_CE) + -0.060 9.951 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[6] ------------------------------------------------------------------- - required time 9.830 - arrival time -6.748 + required time 9.951 + arrival time -7.020 ------------------------------------------------------------------- - slack 3.082 + slack 2.931 -Slack (MET) : 3.082ns (required time - arrival time) - Source: pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C +Slack (MET) : 2.946ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[2]/R + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[34]/CE (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 4.556ns (logic 0.170ns (3.731%) route 4.386ns (96.269%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.166ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.922ns = ( 9.922 - 8.000 ) - Source Clock Delay (SCD): 2.192ns + Data Path Delay: 4.771ns (logic 0.268ns (5.617%) route 4.503ns (94.383%)) + Logic Levels: 3 (LUT2=1 LUT6=2) + Clock Path Skew: -0.101ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.016ns = ( 10.016 - 8.000 ) + Source Clock Delay (SCD): 2.221ns Clock Pessimism Removal (CPR): 0.104ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.984ns (routing 0.643ns, distribution 1.341ns) - Clock Net Delay (Destination): 1.754ns (routing 0.579ns, distribution 1.175ns) + Clock Net Delay (Source): 2.013ns (routing 0.643ns, distribution 1.370ns) + Clock Net Delay (Destination): 1.848ns (routing 0.579ns, distribution 1.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -374,16 +371,22 @@ Slack (MET) : 3.082ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.984 2.192 pl_eth_10g_i/zups/rst_ps8_0_99M/U0/slowest_sync_clk - SLICE_X88Y96 FDRE r pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 2.013 2.221 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X39Y244 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y96 FDRE (Prop_BFF2_SLICEM_C_Q) - 0.080 2.272 f pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q - net (fo=286, routed) 2.488 4.760 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/s_axi_aresetn_0 - SLICE_X57Y181 LUT1 (Prop_H6LUT_SLICEM_I0_O) - 0.090 4.850 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_awready_i_1/O - net (fo=65, routed) 1.898 6.748 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/AXI_Reset0 - SLICE_X40Y248 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[2]/R + SLICE_X39Y244 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 2.300 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/Q + net (fo=92, routed) 2.647 4.947 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/p_0_in[7] + SLICE_X91Y174 LUT2 (Prop_D6LUT_SLICEL_I0_O) + 0.099 5.046 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3/O + net (fo=19, routed) 0.568 5.614 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3_n_0 + SLICE_X84Y205 LUT6 (Prop_H6LUT_SLICEM_I0_O) + 0.053 5.667 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2/O + net (fo=4, routed) 0.381 6.048 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2_n_0 + SLICE_X94Y189 LUT6 (Prop_D6LUT_SLICEM_I0_O) + 0.037 6.085 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[57]_i_1/O + net (fo=26, routed) 0.907 6.992 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[57]_i_1_n_0 + SLICE_X100Y169 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[34]/CE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -392,38 +395,38 @@ Slack (MET) : 3.082ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.754 9.922 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/dclk - SLICE_X40Y248 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[2]/C - clock pessimism 0.104 10.026 - clock uncertainty -0.122 9.904 - SLICE_X40Y248 FDRE (Setup_GFF_SLICEL_C_R) - -0.074 9.830 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[2] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.848 10.016 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X100Y169 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[34]/C + clock pessimism 0.104 10.120 + clock uncertainty -0.122 9.998 + SLICE_X100Y169 FDRE (Setup_HFF2_SLICEL_C_CE) + -0.060 9.938 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[34] ------------------------------------------------------------------- - required time 9.830 - arrival time -6.748 + required time 9.938 + arrival time -6.992 ------------------------------------------------------------------- - slack 3.082 + slack 2.946 -Slack (MET) : 3.093ns (required time - arrival time) - Source: pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C +Slack (MET) : 2.946ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[1]/R + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[47]/CE (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 4.487ns (logic 0.170ns (3.789%) route 4.317ns (96.211%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.224ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.864ns = ( 9.864 - 8.000 ) - Source Clock Delay (SCD): 2.192ns + Data Path Delay: 4.771ns (logic 0.268ns (5.617%) route 4.503ns (94.383%)) + Logic Levels: 3 (LUT2=1 LUT6=2) + Clock Path Skew: -0.101ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.016ns = ( 10.016 - 8.000 ) + Source Clock Delay (SCD): 2.221ns Clock Pessimism Removal (CPR): 0.104ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.984ns (routing 0.643ns, distribution 1.341ns) - Clock Net Delay (Destination): 1.696ns (routing 0.579ns, distribution 1.117ns) + Clock Net Delay (Source): 2.013ns (routing 0.643ns, distribution 1.370ns) + Clock Net Delay (Destination): 1.848ns (routing 0.579ns, distribution 1.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -433,16 +436,22 @@ Slack (MET) : 3.093ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.984 2.192 pl_eth_10g_i/zups/rst_ps8_0_99M/U0/slowest_sync_clk - SLICE_X88Y96 FDRE r pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 2.013 2.221 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X39Y244 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y96 FDRE (Prop_BFF2_SLICEM_C_Q) - 0.080 2.272 f pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q - net (fo=286, routed) 2.488 4.760 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/s_axi_aresetn_0 - SLICE_X57Y181 LUT1 (Prop_H6LUT_SLICEM_I0_O) - 0.090 4.850 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_awready_i_1/O - net (fo=65, routed) 1.829 6.679 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/AXI_Reset0 - SLICE_X42Y248 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[1]/R + SLICE_X39Y244 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 2.300 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/Q + net (fo=92, routed) 2.647 4.947 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/p_0_in[7] + SLICE_X91Y174 LUT2 (Prop_D6LUT_SLICEL_I0_O) + 0.099 5.046 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3/O + net (fo=19, routed) 0.568 5.614 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3_n_0 + SLICE_X84Y205 LUT6 (Prop_H6LUT_SLICEM_I0_O) + 0.053 5.667 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2/O + net (fo=4, routed) 0.381 6.048 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2_n_0 + SLICE_X94Y189 LUT6 (Prop_D6LUT_SLICEM_I0_O) + 0.037 6.085 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[57]_i_1/O + net (fo=26, routed) 0.907 6.992 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[57]_i_1_n_0 + SLICE_X100Y169 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[47]/CE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -451,38 +460,38 @@ Slack (MET) : 3.093ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.696 9.864 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/dclk - SLICE_X42Y248 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[1]/C - clock pessimism 0.104 9.968 - clock uncertainty -0.122 9.846 - SLICE_X42Y248 FDRE (Setup_DFF_SLICEM_C_R) - -0.074 9.772 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[1] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.848 10.016 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X100Y169 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[47]/C + clock pessimism 0.104 10.120 + clock uncertainty -0.122 9.998 + SLICE_X100Y169 FDRE (Setup_GFF2_SLICEL_C_CE) + -0.060 9.938 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[47] ------------------------------------------------------------------- - required time 9.772 - arrival time -6.679 + required time 9.938 + arrival time -6.992 ------------------------------------------------------------------- - slack 3.093 + slack 2.946 -Slack (MET) : 3.093ns (required time - arrival time) - Source: pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C +Slack (MET) : 2.978ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[3]/R + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[8]/CE (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 4.487ns (logic 0.170ns (3.789%) route 4.317ns (96.211%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.224ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.864ns = ( 9.864 - 8.000 ) - Source Clock Delay (SCD): 2.192ns + Data Path Delay: 4.756ns (logic 0.321ns (6.749%) route 4.435ns (93.251%)) + Logic Levels: 3 (LUT2=1 LUT6=2) + Clock Path Skew: -0.084ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.033ns = ( 10.033 - 8.000 ) + Source Clock Delay (SCD): 2.221ns Clock Pessimism Removal (CPR): 0.104ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.984ns (routing 0.643ns, distribution 1.341ns) - Clock Net Delay (Destination): 1.696ns (routing 0.579ns, distribution 1.117ns) + Clock Net Delay (Source): 2.013ns (routing 0.643ns, distribution 1.370ns) + Clock Net Delay (Destination): 1.865ns (routing 0.579ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -492,16 +501,22 @@ Slack (MET) : 3.093ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.984 2.192 pl_eth_10g_i/zups/rst_ps8_0_99M/U0/slowest_sync_clk - SLICE_X88Y96 FDRE r pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 2.013 2.221 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X39Y244 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y96 FDRE (Prop_BFF2_SLICEM_C_Q) - 0.080 2.272 f pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q - net (fo=286, routed) 2.488 4.760 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/s_axi_aresetn_0 - SLICE_X57Y181 LUT1 (Prop_H6LUT_SLICEM_I0_O) - 0.090 4.850 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_awready_i_1/O - net (fo=65, routed) 1.829 6.679 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/AXI_Reset0 - SLICE_X42Y248 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[3]/R + SLICE_X39Y244 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 2.300 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/Q + net (fo=92, routed) 2.647 4.947 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/p_0_in[7] + SLICE_X91Y174 LUT2 (Prop_D6LUT_SLICEL_I0_O) + 0.099 5.046 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3/O + net (fo=19, routed) 0.568 5.614 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3_n_0 + SLICE_X84Y205 LUT6 (Prop_H6LUT_SLICEM_I0_O) + 0.053 5.667 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2/O + net (fo=4, routed) 0.433 6.100 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2_n_0 + SLICE_X94Y189 LUT6 (Prop_H6LUT_SLICEM_I0_O) + 0.090 6.190 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[31]_i_1/O + net (fo=32, routed) 0.787 6.977 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[31]_i_1_n_0 + SLICE_X101Y174 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[8]/CE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -510,38 +525,38 @@ Slack (MET) : 3.093ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.696 9.864 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/dclk - SLICE_X42Y248 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[3]/C - clock pessimism 0.104 9.968 - clock uncertainty -0.122 9.846 - SLICE_X42Y248 FDRE (Setup_CFF_SLICEM_C_R) - -0.074 9.772 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[3] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.865 10.033 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X101Y174 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[8]/C + clock pessimism 0.104 10.137 + clock uncertainty -0.122 10.015 + SLICE_X101Y174 FDRE (Setup_HFF_SLICEL_C_CE) + -0.060 9.955 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[8] ------------------------------------------------------------------- - required time 9.772 - arrival time -6.679 + required time 9.955 + arrival time -6.977 ------------------------------------------------------------------- - slack 3.093 + slack 2.978 -Slack (MET) : 3.093ns (required time - arrival time) - Source: pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C +Slack (MET) : 2.981ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[7]/R + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[15]/CE (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 4.487ns (logic 0.170ns (3.789%) route 4.317ns (96.211%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.224ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.864ns = ( 9.864 - 8.000 ) - Source Clock Delay (SCD): 2.192ns + Data Path Delay: 4.736ns (logic 0.321ns (6.778%) route 4.415ns (93.222%)) + Logic Levels: 3 (LUT2=1 LUT6=2) + Clock Path Skew: -0.101ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.016ns = ( 10.016 - 8.000 ) + Source Clock Delay (SCD): 2.221ns Clock Pessimism Removal (CPR): 0.104ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.984ns (routing 0.643ns, distribution 1.341ns) - Clock Net Delay (Destination): 1.696ns (routing 0.579ns, distribution 1.117ns) + Clock Net Delay (Source): 2.013ns (routing 0.643ns, distribution 1.370ns) + Clock Net Delay (Destination): 1.848ns (routing 0.579ns, distribution 1.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -551,16 +566,22 @@ Slack (MET) : 3.093ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.984 2.192 pl_eth_10g_i/zups/rst_ps8_0_99M/U0/slowest_sync_clk - SLICE_X88Y96 FDRE r pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 2.013 2.221 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X39Y244 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y96 FDRE (Prop_BFF2_SLICEM_C_Q) - 0.080 2.272 f pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q - net (fo=286, routed) 2.488 4.760 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/s_axi_aresetn_0 - SLICE_X57Y181 LUT1 (Prop_H6LUT_SLICEM_I0_O) - 0.090 4.850 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_awready_i_1/O - net (fo=65, routed) 1.829 6.679 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/AXI_Reset0 - SLICE_X42Y248 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[7]/R + SLICE_X39Y244 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 2.300 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/Q + net (fo=92, routed) 2.647 4.947 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/p_0_in[7] + SLICE_X91Y174 LUT2 (Prop_D6LUT_SLICEL_I0_O) + 0.099 5.046 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3/O + net (fo=19, routed) 0.568 5.614 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3_n_0 + SLICE_X84Y205 LUT6 (Prop_H6LUT_SLICEM_I0_O) + 0.053 5.667 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2/O + net (fo=4, routed) 0.433 6.100 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2_n_0 + SLICE_X94Y189 LUT6 (Prop_H6LUT_SLICEM_I0_O) + 0.090 6.190 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[31]_i_1/O + net (fo=32, routed) 0.767 6.957 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[31]_i_1_n_0 + SLICE_X100Y169 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[15]/CE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -569,38 +590,38 @@ Slack (MET) : 3.093ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.696 9.864 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/dclk - SLICE_X42Y248 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[7]/C - clock pessimism 0.104 9.968 - clock uncertainty -0.122 9.846 - SLICE_X42Y248 FDRE (Setup_BFF_SLICEM_C_R) - -0.074 9.772 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[7] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.848 10.016 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X100Y169 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[15]/C + clock pessimism 0.104 10.120 + clock uncertainty -0.122 9.998 + SLICE_X100Y169 FDRE (Setup_HFF_SLICEL_C_CE) + -0.060 9.938 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[15] ------------------------------------------------------------------- - required time 9.772 - arrival time -6.679 + required time 9.938 + arrival time -6.957 ------------------------------------------------------------------- - slack 3.093 + slack 2.981 -Slack (MET) : 3.093ns (required time - arrival time) - Source: pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C +Slack (MET) : 2.981ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[8]/R + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[2]/CE (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 4.487ns (logic 0.170ns (3.789%) route 4.317ns (96.211%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.224ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.864ns = ( 9.864 - 8.000 ) - Source Clock Delay (SCD): 2.192ns + Data Path Delay: 4.736ns (logic 0.321ns (6.778%) route 4.415ns (93.222%)) + Logic Levels: 3 (LUT2=1 LUT6=2) + Clock Path Skew: -0.101ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.016ns = ( 10.016 - 8.000 ) + Source Clock Delay (SCD): 2.221ns Clock Pessimism Removal (CPR): 0.104ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.984ns (routing 0.643ns, distribution 1.341ns) - Clock Net Delay (Destination): 1.696ns (routing 0.579ns, distribution 1.117ns) + Clock Net Delay (Source): 2.013ns (routing 0.643ns, distribution 1.370ns) + Clock Net Delay (Destination): 1.848ns (routing 0.579ns, distribution 1.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -610,16 +631,22 @@ Slack (MET) : 3.093ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.984 2.192 pl_eth_10g_i/zups/rst_ps8_0_99M/U0/slowest_sync_clk - SLICE_X88Y96 FDRE r pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 2.013 2.221 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X39Y244 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y96 FDRE (Prop_BFF2_SLICEM_C_Q) - 0.080 2.272 f pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q - net (fo=286, routed) 2.488 4.760 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/s_axi_aresetn_0 - SLICE_X57Y181 LUT1 (Prop_H6LUT_SLICEM_I0_O) - 0.090 4.850 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_awready_i_1/O - net (fo=65, routed) 1.829 6.679 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/AXI_Reset0 - SLICE_X42Y248 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[8]/R + SLICE_X39Y244 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 2.300 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/Q + net (fo=92, routed) 2.647 4.947 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/p_0_in[7] + SLICE_X91Y174 LUT2 (Prop_D6LUT_SLICEL_I0_O) + 0.099 5.046 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3/O + net (fo=19, routed) 0.568 5.614 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3_n_0 + SLICE_X84Y205 LUT6 (Prop_H6LUT_SLICEM_I0_O) + 0.053 5.667 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2/O + net (fo=4, routed) 0.433 6.100 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2_n_0 + SLICE_X94Y189 LUT6 (Prop_H6LUT_SLICEM_I0_O) + 0.090 6.190 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[31]_i_1/O + net (fo=32, routed) 0.767 6.957 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[31]_i_1_n_0 + SLICE_X100Y169 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -628,38 +655,38 @@ Slack (MET) : 3.093ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.696 9.864 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/dclk - SLICE_X42Y248 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[8]/C - clock pessimism 0.104 9.968 - clock uncertainty -0.122 9.846 - SLICE_X42Y248 FDRE (Setup_AFF_SLICEM_C_R) - -0.074 9.772 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[8] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.848 10.016 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X100Y169 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[2]/C + clock pessimism 0.104 10.120 + clock uncertainty -0.122 9.998 + SLICE_X100Y169 FDRE (Setup_GFF_SLICEL_C_CE) + -0.060 9.938 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[2] ------------------------------------------------------------------- - required time 9.772 - arrival time -6.679 + required time 9.938 + arrival time -6.957 ------------------------------------------------------------------- - slack 3.093 + slack 2.981 -Slack (MET) : 3.100ns (required time - arrival time) - Source: pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C +Slack (MET) : 2.981ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[11]/R + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[3]/CE (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 4.465ns (logic 0.170ns (3.807%) route 4.295ns (96.193%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.239ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.849ns = ( 9.849 - 8.000 ) - Source Clock Delay (SCD): 2.192ns + Data Path Delay: 4.751ns (logic 0.321ns (6.756%) route 4.430ns (93.244%)) + Logic Levels: 3 (LUT2=1 LUT6=2) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.031ns = ( 10.031 - 8.000 ) + Source Clock Delay (SCD): 2.221ns Clock Pessimism Removal (CPR): 0.104ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.984ns (routing 0.643ns, distribution 1.341ns) - Clock Net Delay (Destination): 1.681ns (routing 0.579ns, distribution 1.102ns) + Clock Net Delay (Source): 2.013ns (routing 0.643ns, distribution 1.370ns) + Clock Net Delay (Destination): 1.863ns (routing 0.579ns, distribution 1.284ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -669,16 +696,22 @@ Slack (MET) : 3.100ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.984 2.192 pl_eth_10g_i/zups/rst_ps8_0_99M/U0/slowest_sync_clk - SLICE_X88Y96 FDRE r pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 2.013 2.221 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X39Y244 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y96 FDRE (Prop_BFF2_SLICEM_C_Q) - 0.080 2.272 f pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q - net (fo=286, routed) 2.488 4.760 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/s_axi_aresetn_0 - SLICE_X57Y181 LUT1 (Prop_H6LUT_SLICEM_I0_O) - 0.090 4.850 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_awready_i_1/O - net (fo=65, routed) 1.807 6.657 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/AXI_Reset0 - SLICE_X43Y246 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[11]/R + SLICE_X39Y244 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 2.300 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/Q + net (fo=92, routed) 2.647 4.947 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/p_0_in[7] + SLICE_X91Y174 LUT2 (Prop_D6LUT_SLICEL_I0_O) + 0.099 5.046 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3/O + net (fo=19, routed) 0.568 5.614 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3_n_0 + SLICE_X84Y205 LUT6 (Prop_H6LUT_SLICEM_I0_O) + 0.053 5.667 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2/O + net (fo=4, routed) 0.433 6.100 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2_n_0 + SLICE_X94Y189 LUT6 (Prop_H6LUT_SLICEM_I0_O) + 0.090 6.190 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[31]_i_1/O + net (fo=32, routed) 0.782 6.972 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[31]_i_1_n_0 + SLICE_X102Y174 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -687,38 +720,38 @@ Slack (MET) : 3.100ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.681 9.849 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/dclk - SLICE_X43Y246 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[11]/C - clock pessimism 0.104 9.953 - clock uncertainty -0.122 9.831 - SLICE_X43Y246 FDRE (Setup_DFF_SLICEL_C_R) - -0.074 9.757 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[11] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.863 10.031 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X102Y174 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[3]/C + clock pessimism 0.104 10.135 + clock uncertainty -0.122 10.013 + SLICE_X102Y174 FDRE (Setup_DFF_SLICEL_C_CE) + -0.060 9.953 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[3] ------------------------------------------------------------------- - required time 9.757 - arrival time -6.657 + required time 9.953 + arrival time -6.972 ------------------------------------------------------------------- - slack 3.100 + slack 2.981 -Slack (MET) : 3.100ns (required time - arrival time) - Source: pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C +Slack (MET) : 2.990ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[6]/R + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[33]/CE (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 4.465ns (logic 0.170ns (3.807%) route 4.295ns (96.193%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.239ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.849ns = ( 9.849 - 8.000 ) - Source Clock Delay (SCD): 2.192ns + Data Path Delay: 4.744ns (logic 0.268ns (5.649%) route 4.476ns (94.351%)) + Logic Levels: 3 (LUT2=1 LUT6=2) + Clock Path Skew: -0.084ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.033ns = ( 10.033 - 8.000 ) + Source Clock Delay (SCD): 2.221ns Clock Pessimism Removal (CPR): 0.104ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.984ns (routing 0.643ns, distribution 1.341ns) - Clock Net Delay (Destination): 1.681ns (routing 0.579ns, distribution 1.102ns) + Clock Net Delay (Source): 2.013ns (routing 0.643ns, distribution 1.370ns) + Clock Net Delay (Destination): 1.865ns (routing 0.579ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -728,16 +761,22 @@ Slack (MET) : 3.100ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.984 2.192 pl_eth_10g_i/zups/rst_ps8_0_99M/U0/slowest_sync_clk - SLICE_X88Y96 FDRE r pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 2.013 2.221 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X39Y244 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y96 FDRE (Prop_BFF2_SLICEM_C_Q) - 0.080 2.272 f pl_eth_10g_i/zups/rst_ps8_0_99M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q - net (fo=286, routed) 2.488 4.760 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/s_axi_aresetn_0 - SLICE_X57Y181 LUT1 (Prop_H6LUT_SLICEM_I0_O) - 0.090 4.850 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_awready_i_1/O - net (fo=65, routed) 1.807 6.657 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/AXI_Reset0 - SLICE_X43Y246 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[6]/R + SLICE_X39Y244 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 2.300 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/Q + net (fo=92, routed) 2.647 4.947 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/p_0_in[7] + SLICE_X91Y174 LUT2 (Prop_D6LUT_SLICEL_I0_O) + 0.099 5.046 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3/O + net (fo=19, routed) 0.568 5.614 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3_n_0 + SLICE_X84Y205 LUT6 (Prop_H6LUT_SLICEM_I0_O) + 0.053 5.667 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2/O + net (fo=4, routed) 0.381 6.048 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2_n_0 + SLICE_X94Y189 LUT6 (Prop_D6LUT_SLICEM_I0_O) + 0.037 6.085 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[57]_i_1/O + net (fo=26, routed) 0.880 6.965 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[57]_i_1_n_0 + SLICE_X102Y174 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[33]/CE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -746,38 +785,38 @@ Slack (MET) : 3.100ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.681 9.849 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/dclk - SLICE_X43Y246 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[6]/C - clock pessimism 0.104 9.953 - clock uncertainty -0.122 9.831 - SLICE_X43Y246 FDRE (Setup_CFF_SLICEL_C_R) - -0.074 9.757 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_axi_slave_2_ipif/axi_araddr_reg[6] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.865 10.033 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X102Y174 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[33]/C + clock pessimism 0.104 10.137 + clock uncertainty -0.122 10.015 + SLICE_X102Y174 FDRE (Setup_HFF_SLICEL_C_CE) + -0.060 9.955 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[33] ------------------------------------------------------------------- - required time 9.757 - arrival time -6.657 + required time 9.955 + arrival time -6.965 ------------------------------------------------------------------- - slack 3.100 + slack 2.990 -Slack (MET) : 3.141ns (required time - arrival time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[10]/C +Slack (MET) : 2.990ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data_reg[0]/D + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[35]/CE (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 4.683ns (logic 0.557ns (11.894%) route 4.126ns (88.106%)) - Logic Levels: 6 (LUT3=1 LUT5=1 LUT6=4) - Clock Path Skew: -0.079ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.900ns = ( 9.900 - 8.000 ) - Source Clock Delay (SCD): 2.083ns + Data Path Delay: 4.744ns (logic 0.268ns (5.649%) route 4.476ns (94.351%)) + Logic Levels: 3 (LUT2=1 LUT6=2) + Clock Path Skew: -0.084ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.033ns = ( 10.033 - 8.000 ) + Source Clock Delay (SCD): 2.221ns Clock Pessimism Removal (CPR): 0.104ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.875ns (routing 0.643ns, distribution 1.232ns) - Clock Net Delay (Destination): 1.732ns (routing 0.579ns, distribution 1.153ns) + Clock Net Delay (Source): 2.013ns (routing 0.643ns, distribution 1.370ns) + Clock Net Delay (Destination): 1.865ns (routing 0.579ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -787,31 +826,22 @@ Slack (MET) : 3.141ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.875 2.083 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk - SLICE_X51Y236 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[10]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 2.013 2.221 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X39Y244 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X51Y236 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 2.162 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[10]/Q - net (fo=118, routed) 2.433 4.595 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/p_0_in[10] - SLICE_X84Y137 LUT3 (Prop_D6LUT_SLICEM_I2_O) - 0.051 4.646 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[18]_i_15/O - net (fo=33, routed) 0.661 5.307 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[18]_i_15_n_0 - SLICE_X78Y177 LUT6 (Prop_H6LUT_SLICEM_I5_O) - 0.101 5.408 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[15]_i_43/O - net (fo=12, routed) 0.346 5.754 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_cycle_accumulator/IP2Bus_Data[15]_i_5 - SLICE_X74Y172 LUT5 (Prop_E6LUT_SLICEM_I4_O) - 0.100 5.854 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_cycle_accumulator/IP2Bus_Data[0]_i_51/O - net (fo=1, routed) 0.147 6.001 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_inrangeerr_accumulator/IP2Bus_Data[0]_i_4_1 - SLICE_X75Y172 LUT6 (Prop_G6LUT_SLICEL_I4_O) - 0.050 6.051 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_inrangeerr_accumulator/IP2Bus_Data[0]_i_19/O - net (fo=1, routed) 0.351 6.402 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_packets_accumulator/IP2Bus_Data_reg[0]_2 - SLICE_X79Y157 LUT6 (Prop_G6LUT_SLICEM_I5_O) - 0.052 6.454 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_total_packets_accumulator/IP2Bus_Data[0]_i_4/O - net (fo=1, routed) 0.139 6.593 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_fcs_accumulator/IP2Bus_Data_reg[0]_1 - SLICE_X80Y156 LUT6 (Prop_B6LUT_SLICEL_I3_O) - 0.124 6.717 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_fcs_accumulator/IP2Bus_Data[0]_i_1/O - net (fo=1, routed) 0.049 6.766 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_bad_fcs_accumulator_n_19 - SLICE_X80Y156 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data_reg[0]/D + SLICE_X39Y244 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 2.300 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/Bus2IP_Addr_reg_reg[7]/Q + net (fo=92, routed) 2.647 4.947 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/p_0_in[7] + SLICE_X91Y174 LUT2 (Prop_D6LUT_SLICEL_I0_O) + 0.099 5.046 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3/O + net (fo=19, routed) 0.568 5.614 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data[31]_i_3_n_0 + SLICE_X84Y205 LUT6 (Prop_H6LUT_SLICEM_I0_O) + 0.053 5.667 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2/O + net (fo=4, routed) 0.381 6.048 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r[57]_i_2_n_0 + SLICE_X94Y189 LUT6 (Prop_D6LUT_SLICEM_I0_O) + 0.037 6.085 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[57]_i_1/O + net (fo=26, routed) 0.880 6.965 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r[57]_i_1_n_0 + SLICE_X102Y174 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[35]/CE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -820,17 +850,17 @@ Slack (MET) : 3.141ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.732 9.900 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk - SLICE_X80Y156 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data_reg[0]/C - clock pessimism 0.104 10.004 - clock uncertainty -0.122 9.882 - SLICE_X80Y156 FDRE (Setup_BFF_SLICEL_C_D) - 0.025 9.907 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/IP2Bus_Data_reg[0] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.865 10.033 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/dclk + SLICE_X102Y174 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[35]/C + clock pessimism 0.104 10.137 + clock uncertainty -0.122 10.015 + SLICE_X102Y174 FDRE (Setup_GFF_SLICEL_C_CE) + -0.060 9.955 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_b_r_reg[35] ------------------------------------------------------------------- - required time 9.907 - arrival time -6.766 + required time 9.955 + arrival time -6.965 ------------------------------------------------------------------- - slack 3.141 + slack 2.990 @@ -838,76 +868,22 @@ Slack (MET) : 3.141ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.011ns (arrival time - required time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[18]/C - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH2.ch2_fetch_address_i_reg[18]/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk_pl_0 - Path Type: Hold (Min at Slow Process Corner) - Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.177ns (logic 0.081ns (45.763%) route 0.096ns (54.237%)) - Logic Levels: 1 (LUT4=1) - Clock Path Skew: 0.106ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.056ns - Source Clock Delay (SCD): 1.785ns - Clock Pessimism Removal (CPR): 0.165ns - Clock Net Delay (Source): 1.617ns (routing 0.579ns, distribution 1.038ns) - Clock Net Delay (Destination): 1.848ns (routing 0.643ns, distribution 1.205ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_pl_0 rise edge) - 0.000 0.000 r - PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] - net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] - BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) - 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.617 1.785 pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/s_axi_lite_aclk - SLICE_X56Y124 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[18]/C - ------------------------------------------------------------------- ------------------- - SLICE_X56Y124 FDRE (Prop_BFF_SLICEM_C_Q) - 0.058 1.843 r pl_eth_10g_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/GEN_DESC_REG_FOR_SG.curdesc_lsb_i_reg[18]/Q - net (fo=2, routed) 0.066 1.909 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_PNTR_FOR_CH2.ch2_fetch_address_i_reg[31][12] - SLICE_X54Y123 LUT4 (Prop_H6LUT_SLICEM_I0_O) - 0.023 1.932 r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_PNTR_FOR_CH2.ch2_fetch_address_i[18]_i_1/O - net (fo=1, routed) 0.030 1.962 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH2.ch2_fetch_address_i_reg[31]_1[12] - SLICE_X54Y123 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH2.ch2_fetch_address_i_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_pl_0 rise edge) - 0.000 0.000 r - PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] - net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] - BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) - 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.848 2.056 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/s_axi_lite_aclk - SLICE_X54Y123 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH2.ch2_fetch_address_i_reg[18]/C - clock pessimism -0.165 1.891 - SLICE_X54Y123 FDRE (Hold_HFF_SLICEM_C_D) - 0.060 1.951 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH2.ch2_fetch_address_i_reg[18] - ------------------------------------------------------------------- - required time -1.951 - arrival time 1.962 - ------------------------------------------------------------------- - slack 0.011 - Slack (MET) : 0.012ns (arrival time - required time) - Source: pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AID_Q_reg[14]/C + Source: pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_depth_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/queue_id_reg[14]/D + Destination: pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_depth_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.173ns (logic 0.058ns (33.526%) route 0.115ns (66.474%)) - Logic Levels: 0 + Data Path Delay: 0.171ns (logic 0.080ns (46.784%) route 0.091ns (53.216%)) + Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.099ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.246ns - Source Clock Delay (SCD): 1.963ns + Destination Clock Delay (DCD): 2.203ns + Source Clock Delay (SCD): 1.920ns Clock Pessimism Removal (CPR): 0.184ns - Clock Net Delay (Source): 1.795ns (routing 0.579ns, distribution 1.216ns) - Clock Net Delay (Destination): 2.038ns (routing 0.643ns, distribution 1.395ns) + Clock Net Delay (Source): 1.752ns (routing 0.579ns, distribution 1.173ns) + Clock Net Delay (Destination): 1.995ns (routing 0.643ns, distribution 1.352ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -917,13 +893,16 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.795 1.963 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/CLK - SLICE_X18Y261 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AID_Q_reg[14]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.752 1.920 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/CLK + SLICE_X31Y265 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_depth_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X18Y261 FDRE (Prop_FFF_SLICEL_C_Q) - 0.058 2.021 r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AID_Q_reg[14]/Q - net (fo=2, routed) 0.115 2.136 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AID_Q[14] - SLICE_X22Y261 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/queue_id_reg[14]/D + SLICE_X31Y265 FDRE (Prop_CFF_SLICEM_C_Q) + 0.058 1.978 r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_depth_reg[1]/Q + net (fo=6, routed) 0.067 2.045 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/Q[1] + SLICE_X30Y265 LUT6 (Prop_C6LUT_SLICEL_I1_O) + 0.022 2.067 r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/USE_B_CHANNEL.cmd_b_depth[4]_i_1/O + net (fo=1, routed) 0.024 2.091 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue_n_28 + SLICE_X30Y265 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_depth_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -932,33 +911,33 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 2.038 2.246 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/CLK - SLICE_X22Y261 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/queue_id_reg[14]/C - clock pessimism -0.184 2.062 - SLICE_X22Y261 FDRE (Hold_FFF2_SLICEL_C_D) - 0.062 2.124 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/queue_id_reg[14] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.995 2.203 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/CLK + SLICE_X30Y265 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_depth_reg[4]/C + clock pessimism -0.184 2.019 + SLICE_X30Y265 FDRE (Hold_CFF_SLICEL_C_D) + 0.060 2.079 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_depth_reg[4] ------------------------------------------------------------------- - required time -2.124 - arrival time 2.136 + required time -2.079 + arrival time 2.091 ------------------------------------------------------------------- slack 0.012 -Slack (MET) : 0.012ns (arrival time - required time) - Source: pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/nxtdesc_int_reg[15]/C +Slack (MET) : 0.014ns (arrival time - required time) + Source: pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/m_payload_i_reg[14]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[15]/D + Destination: pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[1].S_AXI_RDATA_II_reg[46]/D (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.222ns (logic 0.080ns (36.036%) route 0.142ns (63.964%)) - Logic Levels: 1 (LUT4=1) - Clock Path Skew: 0.150ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.057ns - Source Clock Delay (SCD): 1.799ns - Clock Pessimism Removal (CPR): 0.108ns - Clock Net Delay (Source): 1.631ns (routing 0.579ns, distribution 1.052ns) - Clock Net Delay (Destination): 1.849ns (routing 0.643ns, distribution 1.206ns) + Data Path Delay: 0.290ns (logic 0.061ns (21.034%) route 0.229ns (78.966%)) + Logic Levels: 0 + Clock Path Skew: 0.216ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.099ns + Source Clock Delay (SCD): 1.779ns + Clock Pessimism Removal (CPR): 0.104ns + Clock Net Delay (Source): 1.611ns (routing 0.579ns, distribution 1.032ns) + Clock Net Delay (Destination): 1.891ns (routing 0.643ns, distribution 1.248ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -968,16 +947,13 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.631 1.799 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/s_axi_lite_aclk - SLICE_X54Y115 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/nxtdesc_int_reg[15]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.611 1.779 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/aclk + SLICE_X50Y171 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/m_payload_i_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X54Y115 FDRE (Prop_BFF_SLICEM_C_Q) - 0.058 1.857 r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/nxtdesc_int_reg[15]/Q - net (fo=2, routed) 0.113 1.970 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/nxtdesc_int_reg_n_0_[15] - SLICE_X54Y121 LUT4 (Prop_B6LUT_SLICEM_I3_O) - 0.022 1.992 r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_PNTR_FOR_CH1.ch1_fetch_address_i[15]_i_1/O - net (fo=1, routed) 0.029 2.021 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[31]_2[9] - SLICE_X54Y121 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[15]/D + SLICE_X50Y171 FDRE (Prop_DFF2_SLICEM_C_Q) + 0.061 1.840 r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/m_payload_i_reg[14]/Q + net (fo=8, routed) 0.229 2.069 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/m_axi_rdata[14] + SLICE_X51Y184 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[1].S_AXI_RDATA_II_reg[46]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -986,33 +962,33 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.849 2.057 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/s_axi_lite_aclk - SLICE_X54Y121 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[15]/C - clock pessimism -0.108 1.949 - SLICE_X54Y121 FDRE (Hold_BFF_SLICEM_C_D) - 0.060 2.009 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH1.ch1_fetch_address_i_reg[15] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.891 2.099 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/CLK + SLICE_X51Y184 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[1].S_AXI_RDATA_II_reg[46]/C + clock pessimism -0.104 1.995 + SLICE_X51Y184 FDRE (Hold_HFF_SLICEL_C_D) + 0.060 2.055 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[1].S_AXI_RDATA_II_reg[46] ------------------------------------------------------------------- - required time -2.009 - arrival time 2.021 + required time -2.055 + arrival time 2.069 ------------------------------------------------------------------- - slack 0.012 + slack 0.014 -Slack (MET) : 0.013ns (arrival time - required time) - Source: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_mask_q_reg[0]/C +Slack (MET) : 0.015ns (arrival time - required time) + Source: pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_mask_q_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMA/I + Destination: pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMB_D1/I (rising edge-triggered cell RAMD32 clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.225ns (logic 0.058ns (25.778%) route 0.167ns (74.222%)) + Data Path Delay: 0.173ns (logic 0.059ns (34.104%) route 0.114ns (65.896%)) Logic Levels: 0 - Clock Path Skew: 0.137ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.263ns - Source Clock Delay (SCD): 1.942ns - Clock Pessimism Removal (CPR): 0.184ns - Clock Net Delay (Source): 1.774ns (routing 0.579ns, distribution 1.195ns) - Clock Net Delay (Destination): 2.055ns (routing 0.643ns, distribution 1.412ns) + Clock Path Skew: 0.098ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.182ns + Source Clock Delay (SCD): 1.858ns + Clock Pessimism Removal (CPR): 0.226ns + Clock Net Delay (Source): 1.690ns (routing 0.579ns, distribution 1.111ns) + Clock Net Delay (Destination): 1.974ns (routing 0.643ns, distribution 1.331ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1022,13 +998,13 @@ Slack (MET) : 0.013ns (arrival time - required time) net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.774 1.942 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/CLK - SLICE_X35Y247 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_mask_q_reg[0]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.690 1.858 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/CLK + SLICE_X48Y245 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_mask_q_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X35Y247 FDRE (Prop_CFF_SLICEM_C_Q) - 0.058 2.000 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_mask_q_reg[0]/Q - net (fo=3, routed) 0.167 2.167 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/DIA0 - SLICE_X37Y250 RAMD32 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMA/I + SLICE_X48Y245 FDRE (Prop_HFF2_SLICEL_C_Q) + 0.059 1.917 r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_mask_q_reg[3]/Q + net (fo=3, routed) 0.114 2.031 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/DIB1 + SLICE_X47Y246 RAMD32 r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMB_D1/I ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1037,32 +1013,137 @@ Slack (MET) : 0.013ns (arrival time - required time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 2.055 2.263 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/WCLK - SLICE_X37Y250 RAMD32 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMA/CLK - clock pessimism -0.184 2.079 - SLICE_X37Y250 RAMD32 (Hold_A5LUT_SLICEM_CLK_I) - 0.075 2.154 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMA + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.974 2.182 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/WCLK + SLICE_X47Y246 RAMD32 r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMB_D1/CLK + clock pessimism -0.226 1.956 + SLICE_X47Y246 RAMD32 (Hold_B6LUT_SLICEM_CLK_I) + 0.060 2.016 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMB_D1 ------------------------------------------------------------------- - required time -2.154 - arrival time 2.167 + required time -2.016 + arrival time 2.031 ------------------------------------------------------------------- - slack 0.013 + slack 0.015 -Slack (MET) : 0.013ns (arrival time - required time) - Source: pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/update_address_reg[8]/C +Slack (MET) : 0.016ns (arrival time - required time) + Source: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/pushed_commands_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[40]/D + Destination: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/pushed_commands_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.156ns (logic 0.060ns (38.462%) route 0.096ns (61.538%)) + Data Path Delay: 0.173ns (logic 0.080ns (46.243%) route 0.093ns (53.757%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.097ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.236ns + Source Clock Delay (SCD): 1.955ns + Clock Pessimism Removal (CPR): 0.184ns + Clock Net Delay (Source): 1.787ns (routing 0.579ns, distribution 1.208ns) + Clock Net Delay (Destination): 2.028ns (routing 0.643ns, distribution 1.385ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pl_0 rise edge) + 0.000 0.000 r + PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] + net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] + BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) + 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.787 1.955 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/CLK + SLICE_X26Y244 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/pushed_commands_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X26Y244 FDRE (Prop_CFF_SLICEL_C_Q) + 0.058 2.013 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/pushed_commands_reg[3]/Q + net (fo=6, routed) 0.069 2.082 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/pushed_commands_reg[3] + SLICE_X27Y244 LUT6 (Prop_C6LUT_SLICEL_I1_O) + 0.022 2.104 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/pushed_commands[5]_i_1__0/O + net (fo=1, routed) 0.024 2.128 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/p_0_in__0[5] + SLICE_X27Y244 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/pushed_commands_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pl_0 rise edge) + 0.000 0.000 r + PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] + net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] + BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) + 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 2.028 2.236 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/CLK + SLICE_X27Y244 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/pushed_commands_reg[5]/C + clock pessimism -0.184 2.052 + SLICE_X27Y244 FDRE (Hold_CFF_SLICEL_C_D) + 0.060 2.112 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/pushed_commands_reg[5] + ------------------------------------------------------------------- + required time -2.112 + arrival time 2.128 + ------------------------------------------------------------------- + slack 0.016 + +Slack (MET) : 0.016ns (arrival time - required time) + Source: pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[58]/C + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_MSTR_SCC/sig_cmd_addr_reg_reg[26]/D + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: clk_pl_0 + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) + Data Path Delay: 0.131ns (logic 0.060ns (45.801%) route 0.071ns (54.198%)) Logic Levels: 0 - Clock Path Skew: 0.083ns (DCD - SCD - CPR) + Clock Path Skew: 0.053ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.067ns + Source Clock Delay (SCD): 1.795ns + Clock Pessimism Removal (CPR): 0.219ns + Clock Net Delay (Source): 1.627ns (routing 0.579ns, distribution 1.048ns) + Clock Net Delay (Destination): 1.859ns (routing 0.643ns, distribution 1.216ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pl_0 rise edge) + 0.000 0.000 r + PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] + net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] + BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) + 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.627 1.795 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/s_axi_lite_aclk + SLICE_X60Y116 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[58]/C + ------------------------------------------------------------------- ------------------- + SLICE_X60Y116 FDRE (Prop_EFF2_SLICEL_C_Q) + 0.060 1.855 r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[58]/Q + net (fo=1, routed) 0.071 1.926 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_MSTR_SCC/Q[21] + SLICE_X60Y114 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_MSTR_SCC/sig_cmd_addr_reg_reg[26]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pl_0 rise edge) + 0.000 0.000 r + PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] + net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] + BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) + 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.859 2.067 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_MSTR_SCC/s_axi_lite_aclk + SLICE_X60Y114 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_MSTR_SCC/sig_cmd_addr_reg_reg[26]/C + clock pessimism -0.219 1.848 + SLICE_X60Y114 FDRE (Hold_BFF2_SLICEL_C_D) + 0.062 1.910 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_MSTR_SCC/sig_cmd_addr_reg_reg[26] + ------------------------------------------------------------------- + required time -1.910 + arrival time 1.926 + ------------------------------------------------------------------- + slack 0.016 + +Slack (MET) : 0.017ns (arrival time - required time) + Source: pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/CURRENT_BD_32.current_bd_reg[29]/C + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.reg2_reg[88]/D + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: clk_pl_0 + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) + Data Path Delay: 0.127ns (logic 0.058ns (45.669%) route 0.069ns (54.331%)) + Logic Levels: 0 + Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.054ns - Source Clock Delay (SCD): 1.799ns - Clock Pessimism Removal (CPR): 0.172ns - Clock Net Delay (Source): 1.631ns (routing 0.579ns, distribution 1.052ns) + Source Clock Delay (SCD): 1.792ns + Clock Pessimism Removal (CPR): 0.214ns + Clock Net Delay (Source): 1.624ns (routing 0.579ns, distribution 1.045ns) Clock Net Delay (Destination): 1.846ns (routing 0.643ns, distribution 1.203ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1073,13 +1154,13 @@ Slack (MET) : 0.013ns (arrival time - required time) net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.631 1.799 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/s_axi_lite_aclk - SLICE_X59Y119 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/update_address_reg[8]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.624 1.792 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/s_axi_lite_aclk + SLICE_X58Y124 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/CURRENT_BD_32.current_bd_reg[29]/C ------------------------------------------------------------------- ------------------- - SLICE_X59Y119 FDRE (Prop_EFF2_SLICEL_C_Q) - 0.060 1.859 r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/update_address_reg[8]/Q - net (fo=2, routed) 0.096 1.955 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]_0[3] - SLICE_X61Y119 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[40]/D + SLICE_X58Y124 FDRE (Prop_HFF_SLICEL_C_Q) + 0.058 1.850 r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/CURRENT_BD_32.current_bd_reg[29]/Q + net (fo=2, routed) 0.069 1.919 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/current_bd[29] + SLICE_X58Y125 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.reg2_reg[88]/D ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1088,32 +1169,32 @@ Slack (MET) : 0.013ns (arrival time - required time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.846 2.054 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/s_axi_lite_aclk - SLICE_X61Y119 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[40]/C - clock pessimism -0.172 1.882 - SLICE_X61Y119 FDRE (Hold_EFF_SLICEM_C_D) - 0.060 1.942 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[40] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.846 2.054 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/s_axi_lite_aclk + SLICE_X58Y125 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.reg2_reg[88]/C + clock pessimism -0.214 1.840 + SLICE_X58Y125 FDRE (Hold_HFF2_SLICEL_C_D) + 0.062 1.902 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.reg2_reg[88] ------------------------------------------------------------------- - required time -1.942 - arrival time 1.955 + required time -1.902 + arrival time 1.919 ------------------------------------------------------------------- - slack 0.013 + slack 0.017 Slack (MET) : 0.017ns (arrival time - required time) - Source: pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/chosen_reg[3]/C - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/m_valid_i_reg/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Source: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C + (rising edge-triggered cell FDCE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMA/WADR1 + (rising edge-triggered cell RAMD32 clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.176ns (logic 0.082ns (46.591%) route 0.094ns (53.409%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.099ns (DCD - SCD - CPR) + Data Path Delay: 0.249ns (logic 0.059ns (23.695%) route 0.190ns (76.305%)) + Logic Levels: 0 + Clock Path Skew: 0.144ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.259ns - Source Clock Delay (SCD): 1.976ns + Source Clock Delay (SCD): 1.931ns Clock Pessimism Removal (CPR): 0.184ns - Clock Net Delay (Source): 1.808ns (routing 0.579ns, distribution 1.229ns) + Clock Net Delay (Source): 1.763ns (routing 0.579ns, distribution 1.184ns) Clock Net Delay (Destination): 2.051ns (routing 0.643ns, distribution 1.408ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1124,16 +1205,13 @@ Slack (MET) : 0.017ns (arrival time - required time) net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.808 1.976 pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/aclk - SLICE_X21Y244 FDRE r pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/chosen_reg[3]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.763 1.931 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk + SLICE_X38Y253 FDCE r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X21Y244 FDRE (Prop_FFF2_SLICEM_C_Q) - 0.060 2.036 f pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_multi_thread.arbiter_resp_inst/chosen_reg[3]/Q - net (fo=9, routed) 0.070 2.106 pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/Q[0] - SLICE_X20Y244 LUT5 (Prop_C6LUT_SLICEL_I2_O) - 0.022 2.128 r pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/m_valid_i0__0/O - net (fo=1, routed) 0.024 2.152 pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/m_valid_i0 - SLICE_X20Y244 FDRE r pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/m_valid_i_reg/D + SLICE_X38Y253 FDCE (Prop_HFF2_SLICEL_C_Q) + 0.059 1.990 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/Q + net (fo=50, routed) 0.190 2.180 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/ADDRH1 + SLICE_X39Y254 RAMD32 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMA/WADR1 ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1142,33 +1220,33 @@ Slack (MET) : 0.017ns (arrival time - required time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 2.051 2.259 pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/aclk - SLICE_X20Y244 FDRE r pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/m_valid_i_reg/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 2.051 2.259 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/WCLK + SLICE_X39Y254 RAMD32 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMA/CLK clock pessimism -0.184 2.075 - SLICE_X20Y244 FDRE (Hold_CFF_SLICEL_C_D) - 0.060 2.135 pl_eth_10g_i/zups/ps_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[3].reg_slice_mi/r.r_pipe/m_valid_i_reg + SLICE_X39Y254 RAMD32 (Hold_A5LUT_SLICEM_CLK_WADR1) + 0.088 2.163 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMA ------------------------------------------------------------------- - required time -2.135 - arrival time 2.152 + required time -2.163 + arrival time 2.180 ------------------------------------------------------------------- slack 0.017 Slack (MET) : 0.017ns (arrival time - required time) - Source: pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[13]/C - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[13]/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Source: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C + (rising edge-triggered cell FDCE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMA_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.180ns (logic 0.058ns (32.222%) route 0.122ns (67.778%)) + Data Path Delay: 0.249ns (logic 0.059ns (23.695%) route 0.190ns (76.305%)) Logic Levels: 0 - Clock Path Skew: 0.103ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.228ns - Source Clock Delay (SCD): 1.941ns + Clock Path Skew: 0.144ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.259ns + Source Clock Delay (SCD): 1.931ns Clock Pessimism Removal (CPR): 0.184ns - Clock Net Delay (Source): 1.773ns (routing 0.579ns, distribution 1.194ns) - Clock Net Delay (Destination): 2.020ns (routing 0.643ns, distribution 1.377ns) + Clock Net Delay (Source): 1.763ns (routing 0.579ns, distribution 1.184ns) + Clock Net Delay (Destination): 2.051ns (routing 0.643ns, distribution 1.408ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1178,13 +1256,13 @@ Slack (MET) : 0.017ns (arrival time - required time) net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.773 1.941 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/clk - SLICE_X29Y260 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[13]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.763 1.931 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk + SLICE_X38Y253 FDCE r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X29Y260 FDRE (Prop_GFF_SLICEM_C_Q) - 0.058 1.999 r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[13]/Q - net (fo=1, routed) 0.122 2.121 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[13] - SLICE_X27Y262 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[13]/D + SLICE_X38Y253 FDCE (Prop_HFF2_SLICEL_C_Q) + 0.059 1.990 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/Q + net (fo=50, routed) 0.190 2.180 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/ADDRH1 + SLICE_X39Y254 RAMD32 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1193,84 +1271,33 @@ Slack (MET) : 0.017ns (arrival time - required time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 2.020 2.228 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk - SLICE_X27Y262 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[13]/C - clock pessimism -0.184 2.044 - SLICE_X27Y262 FDRE (Hold_EFF_SLICEL_C_D) - 0.060 2.104 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[13] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 2.051 2.259 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/WCLK + SLICE_X39Y254 RAMD32 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMA_D1/CLK + clock pessimism -0.184 2.075 + SLICE_X39Y254 RAMD32 (Hold_A6LUT_SLICEM_CLK_WADR1) + 0.088 2.163 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMA_D1 ------------------------------------------------------------------- - required time -2.104 - arrival time 2.121 + required time -2.163 + arrival time 2.180 ------------------------------------------------------------------- slack 0.017 -Slack (MET) : 0.018ns (arrival time - required time) - Source: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AID_Q_reg[4]/C - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/queue_id_reg[4]/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) +Slack (MET) : 0.017ns (arrival time - required time) + Source: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C + (rising edge-triggered cell FDCE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMB/WADR1 + (rising edge-triggered cell RAMD32 clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.126ns (logic 0.058ns (46.032%) route 0.068ns (53.968%)) + Data Path Delay: 0.249ns (logic 0.059ns (23.695%) route 0.190ns (76.305%)) Logic Levels: 0 - Clock Path Skew: 0.046ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.250ns - Source Clock Delay (SCD): 1.966ns - Clock Pessimism Removal (CPR): 0.238ns - Clock Net Delay (Source): 1.798ns (routing 0.579ns, distribution 1.219ns) - Clock Net Delay (Destination): 2.042ns (routing 0.643ns, distribution 1.399ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_pl_0 rise edge) - 0.000 0.000 r - PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] - net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] - BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) - 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.798 1.966 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/CLK - SLICE_X20Y259 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AID_Q_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X20Y259 FDRE (Prop_AFF_SLICEL_C_Q) - 0.058 2.024 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AID_Q_reg[4]/Q - net (fo=2, routed) 0.068 2.092 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/S_AXI_AID_Q[4] - SLICE_X20Y258 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/queue_id_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_pl_0 rise edge) - 0.000 0.000 r - PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] - net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] - BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) - 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 2.042 2.250 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/CLK - SLICE_X20Y258 FDRE r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/queue_id_reg[4]/C - clock pessimism -0.238 2.012 - SLICE_X20Y258 FDRE (Hold_DFF2_SLICEL_C_D) - 0.062 2.074 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/queue_id_reg[4] - ------------------------------------------------------------------- - required time -2.074 - arrival time 2.092 - ------------------------------------------------------------------- - slack 0.018 - -Slack (MET) : 0.020ns (arrival time - required time) - Source: pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/C - (rising edge-triggered cell FDCE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]/D - (rising edge-triggered cell FDCE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk_pl_0 - Path Type: Hold (Min at Slow Process Corner) - Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.195ns (logic 0.058ns (29.744%) route 0.137ns (70.256%)) - Logic Levels: 0 - Clock Path Skew: 0.113ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.255ns - Source Clock Delay (SCD): 1.958ns + Clock Path Skew: 0.144ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.259ns + Source Clock Delay (SCD): 1.931ns Clock Pessimism Removal (CPR): 0.184ns - Clock Net Delay (Source): 1.790ns (routing 0.579ns, distribution 1.211ns) - Clock Net Delay (Destination): 2.047ns (routing 0.643ns, distribution 1.404ns) + Clock Net Delay (Source): 1.763ns (routing 0.579ns, distribution 1.184ns) + Clock Net Delay (Destination): 2.051ns (routing 0.643ns, distribution 1.408ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1280,13 +1307,13 @@ Slack (MET) : 0.020ns (arrival time - required time) net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.790 1.958 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk - SLICE_X25Y258 FDCE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.763 1.931 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk + SLICE_X38Y253 FDCE r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y258 FDCE (Prop_DFF_SLICEM_C_Q) - 0.058 2.016 r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/Q - net (fo=4, routed) 0.137 2.153 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_pntr_plus1[3] - SLICE_X24Y258 FDCE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]/D + SLICE_X38Y253 FDCE (Prop_HFF2_SLICEL_C_Q) + 0.059 1.990 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/Q + net (fo=50, routed) 0.190 2.180 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/ADDRH1 + SLICE_X39Y254 RAMD32 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMB/WADR1 ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1295,33 +1322,33 @@ Slack (MET) : 0.020ns (arrival time - required time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 2.047 2.255 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk - SLICE_X24Y258 FDCE r pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]/C - clock pessimism -0.184 2.071 - SLICE_X24Y258 FDCE (Hold_GFF2_SLICEL_C_D) - 0.062 2.133 pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 2.051 2.259 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/WCLK + SLICE_X39Y254 RAMD32 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMB/CLK + clock pessimism -0.184 2.075 + SLICE_X39Y254 RAMD32 (Hold_B5LUT_SLICEM_CLK_WADR1) + 0.088 2.163 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMB ------------------------------------------------------------------- - required time -2.133 - arrival time 2.153 + required time -2.163 + arrival time 2.180 ------------------------------------------------------------------- - slack 0.020 + slack 0.017 -Slack (MET) : 0.020ns (arrival time - required time) - Source: pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/nxtdesc_int_reg[14]/C - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH2.ch2_fetch_address_i_reg[14]/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) +Slack (MET) : 0.017ns (arrival time - required time) + Source: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C + (rising edge-triggered cell FDCE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMB_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.229ns (logic 0.083ns (36.245%) route 0.146ns (63.755%)) - Logic Levels: 1 (LUT4=1) - Clock Path Skew: 0.149ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.056ns - Source Clock Delay (SCD): 1.799ns - Clock Pessimism Removal (CPR): 0.108ns - Clock Net Delay (Source): 1.631ns (routing 0.579ns, distribution 1.052ns) - Clock Net Delay (Destination): 1.848ns (routing 0.643ns, distribution 1.205ns) + Data Path Delay: 0.249ns (logic 0.059ns (23.695%) route 0.190ns (76.305%)) + Logic Levels: 0 + Clock Path Skew: 0.144ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.259ns + Source Clock Delay (SCD): 1.931ns + Clock Pessimism Removal (CPR): 0.184ns + Clock Net Delay (Source): 1.763ns (routing 0.579ns, distribution 1.184ns) + Clock Net Delay (Destination): 2.051ns (routing 0.643ns, distribution 1.408ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1331,16 +1358,13 @@ Slack (MET) : 0.020ns (arrival time - required time) net (fo=1, routed) 0.143 0.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 0.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.631 1.799 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/s_axi_lite_aclk - SLICE_X54Y115 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/nxtdesc_int_reg[14]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.763 1.931 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk + SLICE_X38Y253 FDCE r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X54Y115 FDRE (Prop_AFF2_SLICEM_C_Q) - 0.060 1.859 r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/nxtdesc_int_reg[14]/Q - net (fo=2, routed) 0.116 1.975 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/nxtdesc_int_reg_n_0_[14] - SLICE_X54Y121 LUT4 (Prop_H6LUT_SLICEM_I3_O) - 0.023 1.998 r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_PNTR_FOR_CH2.ch2_fetch_address_i[14]_i_1/O - net (fo=1, routed) 0.030 2.028 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH2.ch2_fetch_address_i_reg[31]_1[8] - SLICE_X54Y121 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH2.ch2_fetch_address_i_reg[14]/D + SLICE_X38Y253 FDCE (Prop_HFF2_SLICEL_C_Q) + 0.059 1.990 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/Q + net (fo=50, routed) 0.190 2.180 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/ADDRH1 + SLICE_X39Y254 RAMD32 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMB_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -1349,16 +1373,16 @@ Slack (MET) : 0.020ns (arrival time - required time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.848 2.056 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/s_axi_lite_aclk - SLICE_X54Y121 FDRE r pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH2.ch2_fetch_address_i_reg[14]/C - clock pessimism -0.108 1.948 - SLICE_X54Y121 FDRE (Hold_HFF_SLICEM_C_D) - 0.060 2.008 pl_eth_10g_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH2.ch2_fetch_address_i_reg[14] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 2.051 2.259 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/WCLK + SLICE_X39Y254 RAMD32 r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMB_D1/CLK + clock pessimism -0.184 2.075 + SLICE_X39Y254 RAMD32 (Hold_B6LUT_SLICEM_CLK_WADR1) + 0.088 2.163 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_14_27/RAMB_D1 ------------------------------------------------------------------- - required time -2.008 - arrival time 2.028 + required time -2.163 + arrival time 2.180 ------------------------------------------------------------------- - slack 0.020 + slack 0.017 @@ -1380,8 +1404,8 @@ Min Period n/a RAMB18E2/CLKARDCLK n/a 1.355 8.0 Min Period n/a RAMB36E2/CLKBWRCLK n/a 1.355 8.000 6.645 RAMB36_X1Y13 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Min Period n/a RAMB18E2/CLKBWRCLK n/a 1.355 8.000 6.645 RAMB18_X1Y20 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK Min Period n/a RAMB36E2/CLKBWRCLK n/a 1.355 8.000 6.645 RAMB36_X1Y11 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK -Min Period n/a SRLC32E/CLK n/a 1.064 8.000 6.936 SLICE_X56Y186 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32/CLK -Min Period n/a SRLC32E/CLK n/a 1.064 8.000 6.936 SLICE_X54Y183 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32/CLK +Min Period n/a SRLC32E/CLK n/a 1.064 8.000 6.936 SLICE_X57Y182 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32/CLK +Min Period n/a SRLC32E/CLK n/a 1.064 8.000 6.936 SLICE_X57Y182 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32/CLK Low Pulse Width Slow GTHE4_CHANNEL/DRPCLK n/a 1.800 4.000 2.200 GTHE4_CHANNEL_X0Y10 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Fast GTHE4_CHANNEL/DRPCLK n/a 1.800 4.000 2.200 GTHE4_CHANNEL_X0Y10 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow PS8/SAXIGP2RCLK n/a 1.500 4.000 2.500 PS8_X0Y0 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/SAXIGP2RCLK @@ -1391,7 +1415,7 @@ Low Pulse Width Fast PS8/SAXIGP2RCLK n/a 1.500 4.0 Low Pulse Width Fast PS8/SAXIGP2WCLK n/a 1.500 4.000 2.500 PS8_X0Y0 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/SAXIGP2WCLK Low Pulse Width Slow PS8/MAXIGP2ACLK n/a 1.500 4.000 2.500 PS8_X0Y0 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP2ACLK Low Pulse Width Slow RAMB18E2/CLKARDCLK n/a 0.542 4.000 3.458 RAMB18_X1Y30 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK -Low Pulse Width Fast RAMB18E2/CLKARDCLK n/a 0.542 4.000 3.458 RAMB18_X1Y30 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK +Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 4.000 3.458 RAMB36_X1Y11 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK High Pulse Width Slow GTHE4_CHANNEL/DRPCLK n/a 1.800 4.000 2.200 GTHE4_CHANNEL_X0Y10 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Fast GTHE4_CHANNEL/DRPCLK n/a 1.800 4.000 2.200 GTHE4_CHANNEL_X0Y10 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow PS8/MAXIGP2ACLK n/a 1.500 4.000 2.500 PS8_X0Y0 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP2ACLK @@ -1434,7 +1458,7 @@ Max Skew Fast GTHE4_CHANNEL/RXUSRCLK GTHE4_CHANNEL/RXUSRCLK2 0.603 From Clock: Net To Clock: Net -Setup : 0 Failing Endpoints, Worst Slack 1.423ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 0.870ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.541ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- @@ -1442,25 +1466,79 @@ PW : 0 Failing Endpoints, Worst Slack 0.541ns, Total Vio Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 1.423ns (required time - arrival time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/C +Slack (MET) : 0.870ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[42]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/DINADIN[1] + Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/DINADIN[6] (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 4.937ns (logic 0.077ns (1.560%) route 4.860ns (98.440%)) + Data Path Delay: 5.566ns (logic 0.080ns (1.437%) route 5.486ns (98.563%)) Logic Levels: 0 - Clock Path Skew: 0.300ns (DCD - SCD + CPR) + Clock Path Skew: 0.326ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.113ns = ( 8.513 - 6.400 ) + Source Clock Delay (SCD): 1.864ns + Clock Pessimism Removal (CPR): 0.077ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.621ns (routing 0.401ns, distribution 1.220ns) + Clock Net Delay (Destination): 1.900ns (routing 0.362ns, distribution 1.538ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.621 1.864 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk + SLICE_X84Y238 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[42]/C + ------------------------------------------------------------------- ------------------- + SLICE_X84Y238 FDRE (Prop_AFF2_SLICEM_C_Q) + 0.080 1.944 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[42]/Q + net (fo=32, routed) 5.486 7.430 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[42] + RAMB36_X0Y60 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/DINADIN[6] + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.900 8.513 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X0Y60 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/CLKARDCLK + clock pessimism 0.077 8.590 + clock uncertainty -0.046 8.544 + RAMB36_X0Y60 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[6]) + -0.244 8.300 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50 + ------------------------------------------------------------------- + required time 8.300 + arrival time -7.430 + ------------------------------------------------------------------- + slack 0.870 + +Slack (MET) : 0.882ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[41]/C + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51/DINADIN[5] + (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: Net + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) + Data Path Delay: 5.507ns (logic 0.081ns (1.471%) route 5.426ns (98.529%)) + Logic Levels: 0 + Clock Path Skew: 0.307ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.112ns = ( 8.512 - 6.400 ) - Source Clock Delay (SCD): 1.907ns + Source Clock Delay (SCD): 1.900ns Clock Pessimism Removal (CPR): 0.095ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.664ns (routing 0.401ns, distribution 1.263ns) + Clock Net Delay (Source): 1.657ns (routing 0.401ns, distribution 1.256ns) Clock Net Delay (Destination): 1.899ns (routing 0.362ns, distribution 1.537ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1470,13 +1548,13 @@ Slack (MET) : 1.423ns (required time - arrival time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.664 1.907 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk - SLICE_X78Y258 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.657 1.900 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk + SLICE_X82Y244 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[41]/C ------------------------------------------------------------------- ------------------- - SLICE_X78Y258 FDRE (Prop_AFF_SLICEM_C_Q) - 0.077 1.984 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/Q - net (fo=32, routed) 4.860 6.844 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[37] - RAMB36_X0Y61 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/DINADIN[1] + SLICE_X82Y244 FDRE (Prop_EFF2_SLICEL_C_Q) + 0.081 1.981 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[41]/Q + net (fo=32, routed) 5.426 7.407 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[41] + RAMB36_X0Y61 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51/DINADIN[5] ------------------------------------------------------------------- ------------------- (clock Net rise edge) 6.400 6.400 r @@ -1484,37 +1562,145 @@ Slack (MET) : 1.423ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.899 8.512 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X0Y61 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/CLKARDCLK + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.899 8.512 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X0Y61 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51/CLKARDCLK clock pessimism 0.095 8.607 clock uncertainty -0.046 8.561 - RAMB36_X0Y61 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[1]) - -0.294 8.267 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50 + RAMB36_X0Y61 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[5]) + -0.272 8.289 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51 ------------------------------------------------------------------- - required time 8.267 - arrival time -6.844 + required time 8.289 + arrival time -7.407 ------------------------------------------------------------------- - slack 1.423 + slack 0.882 -Slack (MET) : 1.455ns (required time - arrival time) - Source: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_fwft.gdvld_fwft.data_valid_fwft_reg/C +Slack (MET) : 0.919ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[42]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_67/REGCEB + Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51/DINADIN[6] (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 4.779ns (logic 0.395ns (8.265%) route 4.384ns (91.735%)) - Logic Levels: 3 (LUT2=1 LUT4=1 LUT6=1) - Clock Path Skew: 0.113ns (DCD - SCD + CPR) + Data Path Delay: 5.516ns (logic 0.080ns (1.450%) route 5.436ns (98.550%)) + Logic Levels: 0 + Clock Path Skew: 0.325ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.112ns = ( 8.512 - 6.400 ) + Source Clock Delay (SCD): 1.864ns + Clock Pessimism Removal (CPR): 0.077ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.621ns (routing 0.401ns, distribution 1.220ns) + Clock Net Delay (Destination): 1.899ns (routing 0.362ns, distribution 1.537ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.621 1.864 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk + SLICE_X84Y238 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[42]/C + ------------------------------------------------------------------- ------------------- + SLICE_X84Y238 FDRE (Prop_AFF2_SLICEM_C_Q) + 0.080 1.944 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[42]/Q + net (fo=32, routed) 5.436 7.380 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[42] + RAMB36_X0Y61 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51/DINADIN[6] + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.899 8.512 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X0Y61 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51/CLKARDCLK + clock pessimism 0.077 8.589 + clock uncertainty -0.046 8.543 + RAMB36_X0Y61 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[6]) + -0.244 8.299 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51 + ------------------------------------------------------------------- + required time 8.299 + arrival time -7.380 + ------------------------------------------------------------------- + slack 0.919 + +Slack (MET) : 0.954ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[41]/C + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/DINADIN[5] + (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: Net + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) + Data Path Delay: 5.436ns (logic 0.081ns (1.490%) route 5.355ns (98.510%)) + Logic Levels: 0 + Clock Path Skew: 0.308ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.113ns = ( 8.513 - 6.400 ) + Source Clock Delay (SCD): 1.900ns + Clock Pessimism Removal (CPR): 0.095ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.657ns (routing 0.401ns, distribution 1.256ns) + Clock Net Delay (Destination): 1.900ns (routing 0.362ns, distribution 1.538ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.657 1.900 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk + SLICE_X82Y244 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[41]/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y244 FDRE (Prop_EFF2_SLICEL_C_Q) + 0.081 1.981 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[41]/Q + net (fo=32, routed) 5.355 7.336 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[41] + RAMB36_X0Y60 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/DINADIN[5] + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.900 8.513 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X0Y60 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/CLKARDCLK + clock pessimism 0.095 8.608 + clock uncertainty -0.046 8.562 + RAMB36_X0Y60 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[5]) + -0.272 8.290 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50 + ------------------------------------------------------------------- + required time 8.290 + arrival time -7.336 + ------------------------------------------------------------------- + slack 0.954 + +Slack (MET) : 1.007ns (required time - arrival time) + Source: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/count_value_i_reg[3]/C + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_67/ADDRBWRADDR[4] + (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: Net + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) + Data Path Delay: 5.113ns (logic 0.078ns (1.526%) route 5.035ns (98.474%)) + Logic Levels: 0 + Clock Path Skew: 0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.072ns = ( 8.472 - 6.400 ) - Source Clock Delay (SCD): 2.111ns + Source Clock Delay (SCD): 2.115ns Clock Pessimism Removal (CPR): 0.152ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.868ns (routing 0.401ns, distribution 1.467ns) + Clock Net Delay (Source): 1.872ns (routing 0.401ns, distribution 1.471ns) Clock Net Delay (Destination): 1.859ns (routing 0.362ns, distribution 1.497ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1524,22 +1710,13 @@ Slack (MET) : 1.455ns (required time - arrival time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.868 2.111 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/wr_clk - SLICE_X53Y269 FDRE r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_fwft.gdvld_fwft.data_valid_fwft_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.872 2.115 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/wr_clk + SLICE_X49Y271 FDRE r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/count_value_i_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X53Y269 FDRE (Prop_FFF2_SLICEM_C_Q) - 0.079 2.190 f pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_fwft.gdvld_fwft.data_valid_fwft_reg/Q - net (fo=36, routed) 0.247 2.437 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/data_valid_axis - SLICE_X54Y263 LUT2 (Prop_D5LUT_SLICEM_I0_O) - 0.066 2.503 f pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/m_axis_tvalid_INST_0/O - net (fo=3, routed) 1.552 4.055 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/s_axis_s2mm_tvalid - SLICE_X59Y108 LUT6 (Prop_H6LUT_SLICEL_I3_O) - 0.150 4.205 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_s_ready_dup_i_1__0/O - net (fo=3, routed) 1.506 5.711 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/pwropt - SLICE_X57Y270 LUT4 (Prop_G6LUT_SLICEM_I2_O) - 0.100 5.811 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_67_REGCEB_cooolgate_en_gate_9/O - net (fo=1, routed) 1.079 6.890 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_67_REGCEB_cooolgate_en_sig_5 - RAMB36_X0Y54 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_67/REGCEB + SLICE_X49Y271 FDRE (Prop_DFF_SLICEM_C_Q) + 0.078 2.193 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdp_inst/count_value_i_reg[3]/Q + net (fo=70, routed) 5.035 7.228 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/addrb[3] + RAMB36_X0Y54 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_67/ADDRBWRADDR[4] ------------------------------------------------------------------- ------------------- (clock Net rise edge) 6.400 6.400 r @@ -1547,37 +1724,37 @@ Slack (MET) : 1.455ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.859 8.472 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.859 8.472 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X0Y54 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_67/CLKBWRCLK clock pessimism 0.152 8.624 clock uncertainty -0.046 8.578 - RAMB36_X0Y54 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_REGCEB) - -0.233 8.345 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_67 + RAMB36_X0Y54 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[4]) + -0.343 8.235 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_67 ------------------------------------------------------------------- - required time 8.345 - arrival time -6.890 + required time 8.235 + arrival time -7.228 ------------------------------------------------------------------- - slack 1.455 + slack 1.007 -Slack (MET) : 1.527ns (required time - arrival time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/C +Slack (MET) : 1.026ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[42]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51/DINADIN[1] + Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52/DINADIN[6] (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 4.831ns (logic 0.077ns (1.594%) route 4.754ns (98.406%)) + Data Path Delay: 5.407ns (logic 0.080ns (1.480%) route 5.327ns (98.520%)) Logic Levels: 0 - Clock Path Skew: 0.298ns (DCD - SCD + CPR) + Clock Path Skew: 0.323ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.110ns = ( 8.510 - 6.400 ) - Source Clock Delay (SCD): 1.907ns - Clock Pessimism Removal (CPR): 0.095ns + Source Clock Delay (SCD): 1.864ns + Clock Pessimism Removal (CPR): 0.077ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.664ns (routing 0.401ns, distribution 1.263ns) + Clock Net Delay (Source): 1.621ns (routing 0.401ns, distribution 1.220ns) Clock Net Delay (Destination): 1.897ns (routing 0.362ns, distribution 1.535ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1587,13 +1764,13 @@ Slack (MET) : 1.527ns (required time - arrival time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.664 1.907 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk - SLICE_X78Y258 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.621 1.864 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk + SLICE_X84Y238 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[42]/C ------------------------------------------------------------------- ------------------- - SLICE_X78Y258 FDRE (Prop_AFF_SLICEM_C_Q) - 0.077 1.984 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/Q - net (fo=32, routed) 4.754 6.738 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[37] - RAMB36_X0Y62 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51/DINADIN[1] + SLICE_X84Y238 FDRE (Prop_AFF2_SLICEM_C_Q) + 0.080 1.944 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[42]/Q + net (fo=32, routed) 5.327 7.271 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[42] + RAMB36_X0Y62 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52/DINADIN[6] ------------------------------------------------------------------- ------------------- (clock Net rise edge) 6.400 6.400 r @@ -1601,37 +1778,199 @@ Slack (MET) : 1.527ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.897 8.510 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X0Y62 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51/CLKARDCLK - clock pessimism 0.095 8.605 - clock uncertainty -0.046 8.559 - RAMB36_X0Y62 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[1]) - -0.294 8.265 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51 + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.897 8.510 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X0Y62 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52/CLKARDCLK + clock pessimism 0.077 8.587 + clock uncertainty -0.046 8.541 + RAMB36_X0Y62 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[6]) + -0.244 8.297 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52 ------------------------------------------------------------------- - required time 8.265 - arrival time -6.738 + required time 8.297 + arrival time -7.271 ------------------------------------------------------------------- - slack 1.527 + slack 1.026 -Slack (MET) : 1.533ns (required time - arrival time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/C +Slack (MET) : 1.047ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[41]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52/DINADIN[1] + Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52/DINADIN[5] (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 4.821ns (logic 0.077ns (1.597%) route 4.744ns (98.403%)) + Data Path Delay: 5.340ns (logic 0.081ns (1.517%) route 5.259ns (98.483%)) Logic Levels: 0 - Clock Path Skew: 0.294ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 2.106ns = ( 8.506 - 6.400 ) - Source Clock Delay (SCD): 1.907ns + Clock Path Skew: 0.305ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.110ns = ( 8.510 - 6.400 ) + Source Clock Delay (SCD): 1.900ns Clock Pessimism Removal (CPR): 0.095ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.664ns (routing 0.401ns, distribution 1.263ns) + Clock Net Delay (Source): 1.657ns (routing 0.401ns, distribution 1.256ns) + Clock Net Delay (Destination): 1.897ns (routing 0.362ns, distribution 1.535ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.657 1.900 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk + SLICE_X82Y244 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[41]/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y244 FDRE (Prop_EFF2_SLICEL_C_Q) + 0.081 1.981 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[41]/Q + net (fo=32, routed) 5.259 7.240 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[41] + RAMB36_X0Y62 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52/DINADIN[5] + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.897 8.510 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X0Y62 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52/CLKARDCLK + clock pessimism 0.095 8.605 + clock uncertainty -0.046 8.559 + RAMB36_X0Y62 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[5]) + -0.272 8.287 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52 + ------------------------------------------------------------------- + required time 8.287 + arrival time -7.240 + ------------------------------------------------------------------- + slack 1.047 + +Slack (MET) : 1.075ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[36]/C + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/DINADIN[0] + (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: Net + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) + Data Path Delay: 5.314ns (logic 0.077ns (1.449%) route 5.237ns (98.551%)) + Logic Levels: 0 + Clock Path Skew: 0.326ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.113ns = ( 8.513 - 6.400 ) + Source Clock Delay (SCD): 1.864ns + Clock Pessimism Removal (CPR): 0.077ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.621ns (routing 0.401ns, distribution 1.220ns) + Clock Net Delay (Destination): 1.900ns (routing 0.362ns, distribution 1.538ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.621 1.864 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk + SLICE_X84Y238 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[36]/C + ------------------------------------------------------------------- ------------------- + SLICE_X84Y238 FDRE (Prop_AFF_SLICEM_C_Q) + 0.077 1.941 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[36]/Q + net (fo=32, routed) 5.237 7.178 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[36] + RAMB36_X0Y60 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/DINADIN[0] + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.900 8.513 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X0Y60 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/CLKARDCLK + clock pessimism 0.077 8.590 + clock uncertainty -0.046 8.544 + RAMB36_X0Y60 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[0]) + -0.291 8.253 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50 + ------------------------------------------------------------------- + required time 8.253 + arrival time -7.178 + ------------------------------------------------------------------- + slack 1.075 + +Slack (MET) : 1.121ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[58]/C + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/DINADIN[22] + (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: Net + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) + Data Path Delay: 5.275ns (logic 0.081ns (1.536%) route 5.194ns (98.464%)) + Logic Levels: 0 + Clock Path Skew: 0.308ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.113ns = ( 8.513 - 6.400 ) + Source Clock Delay (SCD): 1.900ns + Clock Pessimism Removal (CPR): 0.095ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.657ns (routing 0.401ns, distribution 1.256ns) + Clock Net Delay (Destination): 1.900ns (routing 0.362ns, distribution 1.538ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.657 1.900 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk + SLICE_X82Y244 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[58]/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y244 FDRE (Prop_GFF2_SLICEL_C_Q) + 0.081 1.981 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[58]/Q + net (fo=32, routed) 5.194 7.175 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[58] + RAMB36_X0Y60 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/DINADIN[22] + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.900 8.513 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X0Y60 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/CLKARDCLK + clock pessimism 0.095 8.608 + clock uncertainty -0.046 8.562 + RAMB36_X0Y60 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[22]) + -0.266 8.296 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50 + ------------------------------------------------------------------- + required time 8.296 + arrival time -7.175 + ------------------------------------------------------------------- + slack 1.121 + +Slack (MET) : 1.137ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[42]/C + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_53/DINADIN[6] + (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: Net + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) + Data Path Delay: 5.292ns (logic 0.080ns (1.512%) route 5.212ns (98.488%)) + Logic Levels: 0 + Clock Path Skew: 0.319ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.106ns = ( 8.506 - 6.400 ) + Source Clock Delay (SCD): 1.864ns + Clock Pessimism Removal (CPR): 0.077ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.621ns (routing 0.401ns, distribution 1.220ns) Clock Net Delay (Destination): 1.893ns (routing 0.362ns, distribution 1.531ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1641,13 +1980,13 @@ Slack (MET) : 1.533ns (required time - arrival time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.664 1.907 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk - SLICE_X78Y258 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.621 1.864 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk + SLICE_X84Y238 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[42]/C ------------------------------------------------------------------- ------------------- - SLICE_X78Y258 FDRE (Prop_AFF_SLICEM_C_Q) - 0.077 1.984 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/Q - net (fo=32, routed) 4.744 6.728 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[37] - RAMB36_X0Y63 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52/DINADIN[1] + SLICE_X84Y238 FDRE (Prop_AFF2_SLICEM_C_Q) + 0.080 1.944 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[42]/Q + net (fo=32, routed) 5.212 7.156 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[42] + RAMB36_X0Y63 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_53/DINADIN[6] ------------------------------------------------------------------- ------------------- (clock Net rise edge) 6.400 6.400 r @@ -1655,350 +1994,17 @@ Slack (MET) : 1.533ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.893 8.506 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X0Y63 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52/CLKARDCLK - clock pessimism 0.095 8.601 - clock uncertainty -0.046 8.555 - RAMB36_X0Y63 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[1]) - -0.294 8.261 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52 + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.893 8.506 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X0Y63 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_53/CLKARDCLK + clock pessimism 0.077 8.583 + clock uncertainty -0.046 8.537 + RAMB36_X0Y63 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[6]) + -0.244 8.293 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_53 ------------------------------------------------------------------- - required time 8.261 - arrival time -6.728 + required time 8.293 + arrival time -7.156 ------------------------------------------------------------------- - slack 1.533 - -Slack (MET) : 1.649ns (required time - arrival time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_54/DINADIN[1] - (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: Net - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 4.693ns (logic 0.077ns (1.641%) route 4.616ns (98.359%)) - Logic Levels: 0 - Clock Path Skew: 0.282ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 2.094ns = ( 8.494 - 6.400 ) - Source Clock Delay (SCD): 1.907ns - Clock Pessimism Removal (CPR): 0.095ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.664ns (routing 0.401ns, distribution 1.263ns) - Clock Net Delay (Destination): 1.881ns (routing 0.362ns, distribution 1.519ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.664 1.907 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk - SLICE_X78Y258 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y258 FDRE (Prop_AFF_SLICEM_C_Q) - 0.077 1.984 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/Q - net (fo=32, routed) 4.616 6.600 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[37] - RAMB36_X0Y65 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_54/DINADIN[1] - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.881 8.494 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X0Y65 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_54/CLKARDCLK - clock pessimism 0.095 8.589 - clock uncertainty -0.046 8.543 - RAMB36_X0Y65 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[1]) - -0.294 8.249 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_54 - ------------------------------------------------------------------- - required time 8.249 - arrival time -6.600 - ------------------------------------------------------------------- - slack 1.649 - -Slack (MET) : 1.701ns (required time - arrival time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_53/DINADIN[1] - (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: Net - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 4.648ns (logic 0.077ns (1.657%) route 4.571ns (98.343%)) - Logic Levels: 0 - Clock Path Skew: 0.289ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 2.101ns = ( 8.501 - 6.400 ) - Source Clock Delay (SCD): 1.907ns - Clock Pessimism Removal (CPR): 0.095ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.664ns (routing 0.401ns, distribution 1.263ns) - Clock Net Delay (Destination): 1.888ns (routing 0.362ns, distribution 1.526ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.664 1.907 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk - SLICE_X78Y258 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y258 FDRE (Prop_AFF_SLICEM_C_Q) - 0.077 1.984 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/Q - net (fo=32, routed) 4.571 6.555 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[37] - RAMB36_X0Y64 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_53/DINADIN[1] - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.888 8.501 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X0Y64 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_53/CLKARDCLK - clock pessimism 0.095 8.596 - clock uncertainty -0.046 8.550 - RAMB36_X0Y64 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[1]) - -0.294 8.256 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_53 - ------------------------------------------------------------------- - required time 8.256 - arrival time -6.555 - ------------------------------------------------------------------- - slack 1.701 - -Slack (MET) : 1.706ns (required time - arrival time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[48]/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_34/DINADIN[12] - (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: Net - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 4.356ns (logic 0.076ns (1.745%) route 4.280ns (98.255%)) - Logic Levels: 0 - Clock Path Skew: -0.055ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.755ns = ( 8.155 - 6.400 ) - Source Clock Delay (SCD): 1.905ns - Clock Pessimism Removal (CPR): 0.095ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.662ns (routing 0.401ns, distribution 1.261ns) - Clock Net Delay (Destination): 1.542ns (routing 0.362ns, distribution 1.180ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.662 1.905 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk - SLICE_X79Y252 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[48]/C - ------------------------------------------------------------------- ------------------- - SLICE_X79Y252 FDRE (Prop_EFF_SLICEM_C_Q) - 0.076 1.981 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[48]/Q - net (fo=32, routed) 4.280 6.261 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[48] - RAMB36_X2Y61 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_34/DINADIN[12] - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.542 8.155 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X2Y61 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_34/CLKARDCLK - clock pessimism 0.095 8.250 - clock uncertainty -0.046 8.204 - RAMB36_X2Y61 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[12]) - -0.237 7.967 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_34 - ------------------------------------------------------------------- - required time 7.967 - arrival time -6.261 - ------------------------------------------------------------------- - slack 1.706 - -Slack (MET) : 1.779ns (required time - arrival time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_55/DINADIN[1] - (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: Net - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 4.555ns (logic 0.077ns (1.690%) route 4.478ns (98.310%)) - Logic Levels: 0 - Clock Path Skew: 0.274ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 2.086ns = ( 8.486 - 6.400 ) - Source Clock Delay (SCD): 1.907ns - Clock Pessimism Removal (CPR): 0.095ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.664ns (routing 0.401ns, distribution 1.263ns) - Clock Net Delay (Destination): 1.873ns (routing 0.362ns, distribution 1.511ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.664 1.907 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk - SLICE_X78Y258 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y258 FDRE (Prop_AFF_SLICEM_C_Q) - 0.077 1.984 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/Q - net (fo=32, routed) 4.478 6.462 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[37] - RAMB36_X0Y66 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_55/DINADIN[1] - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.873 8.486 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X0Y66 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_55/CLKARDCLK - clock pessimism 0.095 8.581 - clock uncertainty -0.046 8.535 - RAMB36_X0Y66 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[1]) - -0.294 8.241 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_55 - ------------------------------------------------------------------- - required time 8.241 - arrival time -6.462 - ------------------------------------------------------------------- - slack 1.779 - -Slack (MET) : 1.808ns (required time - arrival time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_57/DINADIN[1] - (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: Net - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 4.538ns (logic 0.077ns (1.697%) route 4.461ns (98.303%)) - Logic Levels: 0 - Clock Path Skew: 0.286ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 2.098ns = ( 8.498 - 6.400 ) - Source Clock Delay (SCD): 1.907ns - Clock Pessimism Removal (CPR): 0.095ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.664ns (routing 0.401ns, distribution 1.263ns) - Clock Net Delay (Destination): 1.885ns (routing 0.362ns, distribution 1.523ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.664 1.907 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk - SLICE_X78Y258 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y258 FDRE (Prop_AFF_SLICEM_C_Q) - 0.077 1.984 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_axis_tdata_reg[37]/Q - net (fo=32, routed) 4.461 6.445 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[37] - RAMB36_X0Y68 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_57/DINADIN[1] - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.885 8.498 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X0Y68 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_57/CLKARDCLK - clock pessimism 0.095 8.593 - clock uncertainty -0.046 8.547 - RAMB36_X0Y68 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[1]) - -0.294 8.253 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_57 - ------------------------------------------------------------------- - required time 8.253 - arrival time -6.445 - ------------------------------------------------------------------- - slack 1.808 - -Slack (MET) : 1.834ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_s_ready_out_reg/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_18/ENBWREN - (rising edge-triggered cell RAMB36E2 clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: Net - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 3.855ns (logic 0.329ns (8.534%) route 3.526ns (91.466%)) - Logic Levels: 3 (LUT3=1 LUT4=1 LUT6=1) - Clock Path Skew: -0.323ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.699ns = ( 8.099 - 6.400 ) - Source Clock Delay (SCD): 2.099ns - Clock Pessimism Removal (CPR): 0.077ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.856ns (routing 0.401ns, distribution 1.455ns) - Clock Net Delay (Destination): 1.486ns (routing 0.362ns, distribution 1.124ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.856 2.099 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/m_axi_s2mm_aclk - SLICE_X57Y263 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_s_ready_out_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X57Y263 FDRE (Prop_EFF_SLICEM_C_Q) - 0.076 2.175 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_s_ready_out_reg/Q - net (fo=35, routed) 0.234 2.409 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/m_axis_tready - SLICE_X54Y263 LUT3 (Prop_C5LUT_SLICEM_I2_O) - 0.099 2.508 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst_i_1/O - net (fo=11, routed) 0.372 2.880 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdpp1_inst/rd_en - SLICE_X52Y270 LUT4 (Prop_B5LUT_SLICEL_I2_O) - 0.104 2.984 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/rdpp1_inst/gen_sdpram.xpm_memory_base_inst_i_2/O - net (fo=129, routed) 1.007 3.991 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb - SLICE_X59Y305 LUT6 (Prop_C6LUT_SLICEL_I0_O) - 0.050 4.041 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_18_i_2/O - net (fo=2, routed) 1.913 5.954 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_18_i_2_n_0 - RAMB36_X2Y42 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_18/ENBWREN - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.486 8.099 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X2Y42 RAMB36E2 r pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_18/CLKBWRCLK - clock pessimism 0.077 8.176 - clock uncertainty -0.046 8.130 - RAMB36_X2Y42 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN) - -0.342 7.788 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_18 - ------------------------------------------------------------------- - required time 7.788 - arrival time -5.954 - ------------------------------------------------------------------- - slack 1.834 + slack 1.137 @@ -2007,21 +2013,21 @@ Slack (MET) : 1.834ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.011ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/statshold_reg[8]/C + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_rx_64bit_retiming_sync_serdes_data0_0/data_out_2d_reg[44]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/statsout_reg[8]/D + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DESCRAMBLER/poly_reg[44]/D (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.123ns (logic 0.058ns (47.154%) route 0.065ns (52.846%)) + Data Path Delay: 0.175ns (logic 0.059ns (33.714%) route 0.116ns (66.286%)) Logic Levels: 0 - Clock Path Skew: 0.050ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.837ns - Source Clock Delay (SCD): 1.610ns - Clock Pessimism Removal (CPR): 0.177ns - Clock Net Delay (Source): 1.397ns (routing 0.362ns, distribution 1.035ns) - Clock Net Delay (Destination): 1.594ns (routing 0.401ns, distribution 1.193ns) + Clock Path Skew: 0.102ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.976ns + Source Clock Delay (SCD): 1.738ns + Clock Pessimism Removal (CPR): 0.136ns + Clock Net Delay (Source): 1.525ns (routing 0.362ns, distribution 1.163ns) + Clock Net Delay (Destination): 1.733ns (routing 0.401ns, distribution 1.332ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2030,13 +2036,13 @@ Slack (MET) : 0.011ns (arrival time - required time) net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.397 1.610 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/overflow_reg_0 - SLICE_X85Y174 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/statshold_reg[8]/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.525 1.738 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_rx_64bit_retiming_sync_serdes_data0_0/CLK + SLICE_X108Y163 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_rx_64bit_retiming_sync_serdes_data0_0/data_out_2d_reg[44]/C ------------------------------------------------------------------- ------------------- - SLICE_X85Y174 FDRE (Prop_FFF_SLICEL_C_Q) - 0.058 1.668 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/statshold_reg[8]/Q - net (fo=1, routed) 0.065 1.733 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/statshold[8] - SLICE_X85Y173 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/statsout_reg[8]/D + SLICE_X108Y163 FDRE (Prop_EFF_SLICEL_C_Q) + 0.059 1.797 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_rx_64bit_retiming_sync_serdes_data0_0/data_out_2d_reg[44]/Q + net (fo=3, routed) 0.116 1.913 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DESCRAMBLER/rx_serdes_data0[44] + SLICE_X110Y163 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DESCRAMBLER/poly_reg[44]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -2044,33 +2050,33 @@ Slack (MET) : 0.011ns (arrival time - required time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.594 1.837 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/overflow_reg_0 - SLICE_X85Y173 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/statsout_reg[8]/C - clock pessimism -0.177 1.660 - SLICE_X85Y173 FDRE (Hold_GFF2_SLICEL_C_D) - 0.062 1.722 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/statsout_reg[8] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.733 1.976 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DESCRAMBLER/rx_serdes_clk + SLICE_X110Y163 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DESCRAMBLER/poly_reg[44]/C + clock pessimism -0.136 1.840 + SLICE_X110Y163 FDRE (Hold_GFF2_SLICEL_C_D) + 0.062 1.902 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DESCRAMBLER/poly_reg[44] ------------------------------------------------------------------- - required time -1.722 - arrival time 1.733 + required time -1.902 + arrival time 1.913 ------------------------------------------------------------------- slack 0.011 Slack (MET) : 0.011ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/counter_msb_reg[13]/C + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/test_data_reg[61]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/statshold_reg[37]/D + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/data_d2_reg[58]/D (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.190ns (logic 0.058ns (30.526%) route 0.132ns (69.474%)) + Data Path Delay: 0.296ns (logic 0.058ns (19.595%) route 0.238ns (80.405%)) Logic Levels: 0 - Clock Path Skew: 0.117ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.842ns - Source Clock Delay (SCD): 1.595ns - Clock Pessimism Removal (CPR): 0.130ns - Clock Net Delay (Source): 1.382ns (routing 0.362ns, distribution 1.020ns) - Clock Net Delay (Destination): 1.599ns (routing 0.401ns, distribution 1.198ns) + Clock Path Skew: 0.225ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.034ns + Source Clock Delay (SCD): 1.740ns + Clock Pessimism Removal (CPR): 0.069ns + Clock Net Delay (Source): 1.527ns (routing 0.362ns, distribution 1.165ns) + Clock Net Delay (Destination): 1.791ns (routing 0.401ns, distribution 1.390ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2079,13 +2085,13 @@ Slack (MET) : 0.011ns (arrival time - required time) net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.382 1.595 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/overflow_reg_0 - SLICE_X85Y146 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/counter_msb_reg[13]/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.527 1.740 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk + SLICE_X110Y166 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/test_data_reg[61]/C ------------------------------------------------------------------- ------------------- - SLICE_X85Y146 FDRE (Prop_CFF_SLICEL_C_Q) - 0.058 1.653 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/counter_msb_reg[13]/Q - net (fo=2, routed) 0.132 1.785 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/p_0_in1_in[37] - SLICE_X81Y145 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/statshold_reg[37]/D + SLICE_X110Y166 FDRE (Prop_HFF_SLICEL_C_Q) + 0.058 1.798 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/test_data_reg[61]/Q + net (fo=10, routed) 0.238 2.036 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/D[2] + SLICE_X106Y181 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/data_d2_reg[58]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -2093,33 +2099,33 @@ Slack (MET) : 0.011ns (arrival time - required time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.599 1.842 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/overflow_reg_0 - SLICE_X81Y145 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/statshold_reg[37]/C - clock pessimism -0.130 1.712 - SLICE_X81Y145 FDRE (Hold_HFF2_SLICEM_C_D) - 0.062 1.774 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_stomped_fcs_accumulator/statshold_reg[37] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.791 2.034 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/rx_serdes_clk + SLICE_X106Y181 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/data_d2_reg[58]/C + clock pessimism -0.069 1.965 + SLICE_X106Y181 FDRE (Hold_HFF_SLICEL_C_D) + 0.060 2.025 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/data_d2_reg[58] ------------------------------------------------------------------- - required time -1.774 - arrival time 1.785 + required time -2.025 + arrival time 2.036 ------------------------------------------------------------------- slack 0.011 Slack (MET) : 0.012ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/statshold_reg[17]/CE + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/counter_lsb_reg[20]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/counter_lsb_d1_reg[20]/D + (rising edge-triggered cell FDSE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.167ns (logic 0.058ns (34.731%) route 0.109ns (65.269%)) + Data Path Delay: 0.151ns (logic 0.059ns (39.073%) route 0.092ns (60.927%)) Logic Levels: 0 - Clock Path Skew: 0.169ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.901ns - Source Clock Delay (SCD): 1.599ns - Clock Pessimism Removal (CPR): 0.133ns - Clock Net Delay (Source): 1.386ns (routing 0.362ns, distribution 1.024ns) - Clock Net Delay (Destination): 1.658ns (routing 0.401ns, distribution 1.257ns) + Clock Path Skew: 0.079ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.972ns + Source Clock Delay (SCD): 1.753ns + Clock Pessimism Removal (CPR): 0.140ns + Clock Net Delay (Source): 1.540ns (routing 0.362ns, distribution 1.178ns) + Clock Net Delay (Destination): 1.729ns (routing 0.401ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2128,13 +2134,13 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.386 1.599 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/overflow_reg_0 - SLICE_X88Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.540 1.753 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/overflow_reg_0 + SLICE_X101Y207 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/counter_lsb_reg[20]/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y170 FDRE (Prop_AFF_SLICEM_C_Q) - 0.058 1.657 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/Q - net (fo=37, routed) 0.109 1.766 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/pm_tick_d1_alias_2 - SLICE_X91Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/statshold_reg[17]/CE + SLICE_X101Y207 FDRE (Prop_EFF_SLICEL_C_Q) + 0.059 1.812 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/counter_lsb_reg[20]/Q + net (fo=3, routed) 0.092 1.904 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/counter_lsb_reg_n_0_[20] + SLICE_X100Y208 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/counter_lsb_d1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -2142,33 +2148,33 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.658 1.901 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/overflow_reg_0 - SLICE_X91Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/statshold_reg[17]/C - clock pessimism -0.133 1.768 - SLICE_X91Y170 FDRE (Hold_HFF_SLICEL_C_CE) - -0.014 1.754 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/statshold_reg[17] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.729 1.972 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/overflow_reg_0 + SLICE_X100Y208 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/counter_lsb_d1_reg[20]/C + clock pessimism -0.140 1.832 + SLICE_X100Y208 FDSE (Hold_CFF_SLICEL_C_D) + 0.060 1.892 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1523_1548_bytes_accumulator/counter_lsb_d1_reg[20] ------------------------------------------------------------------- - required time -1.754 - arrival time 1.766 + required time -1.892 + arrival time 1.904 ------------------------------------------------------------------- slack 0.012 Slack (MET) : 0.012ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/statshold_reg[19]/CE + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/v_reg/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/gcsram/SP/I + (rising edge-triggered cell RAMS64E clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.167ns (logic 0.058ns (34.731%) route 0.109ns (65.269%)) + Data Path Delay: 0.150ns (logic 0.058ns (38.667%) route 0.092ns (61.333%)) Logic Levels: 0 - Clock Path Skew: 0.169ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.901ns - Source Clock Delay (SCD): 1.599ns - Clock Pessimism Removal (CPR): 0.133ns - Clock Net Delay (Source): 1.386ns (routing 0.362ns, distribution 1.024ns) - Clock Net Delay (Destination): 1.658ns (routing 0.401ns, distribution 1.257ns) + Clock Path Skew: 0.065ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.005ns + Source Clock Delay (SCD): 1.741ns + Clock Pessimism Removal (CPR): 0.199ns + Clock Net Delay (Source): 1.528ns (routing 0.362ns, distribution 1.166ns) + Clock Net Delay (Destination): 1.762ns (routing 0.401ns, distribution 1.361ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2177,13 +2183,13 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.386 1.599 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/overflow_reg_0 - SLICE_X88Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.528 1.741 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/rx_serdes_clk + SLICE_X104Y174 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/v_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y170 FDRE (Prop_AFF_SLICEM_C_Q) - 0.058 1.657 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/Q - net (fo=37, routed) 0.109 1.766 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/pm_tick_d1_alias_2 - SLICE_X91Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/statshold_reg[19]/CE + SLICE_X104Y174 FDRE (Prop_GFF_SLICEM_C_Q) + 0.058 1.799 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/v_reg/Q + net (fo=1, routed) 0.092 1.891 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/gcsram/D + SLICE_X104Y174 RAMS64E r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/gcsram/SP/I ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -2191,33 +2197,33 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.658 1.901 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/overflow_reg_0 - SLICE_X91Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/statshold_reg[19]/C - clock pessimism -0.133 1.768 - SLICE_X91Y170 FDRE (Hold_GFF_SLICEL_C_CE) - -0.014 1.754 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/statshold_reg[19] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.762 2.005 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/gcsram/WCLK + SLICE_X104Y174 RAMS64E r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/gcsram/SP/CLK + clock pessimism -0.199 1.806 + SLICE_X104Y174 RAMS64E (Hold_H6LUT_SLICEM_CLK_I) + 0.073 1.879 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/gcsram/SP ------------------------------------------------------------------- - required time -1.754 - arrival time 1.766 + required time -1.879 + arrival time 1.891 ------------------------------------------------------------------- slack 0.012 Slack (MET) : 0.012ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/statshold_reg[23]/CE + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/counter_lsb_reg[12]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/counter_lsb_d1_reg[12]/D + (rising edge-triggered cell FDSE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.167ns (logic 0.058ns (34.731%) route 0.109ns (65.269%)) + Data Path Delay: 0.169ns (logic 0.059ns (34.911%) route 0.110ns (65.089%)) Logic Levels: 0 - Clock Path Skew: 0.169ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.901ns - Source Clock Delay (SCD): 1.599ns - Clock Pessimism Removal (CPR): 0.133ns - Clock Net Delay (Source): 1.386ns (routing 0.362ns, distribution 1.024ns) - Clock Net Delay (Destination): 1.658ns (routing 0.401ns, distribution 1.257ns) + Clock Path Skew: 0.097ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.894ns + Source Clock Delay (SCD): 1.663ns + Clock Pessimism Removal (CPR): 0.134ns + Clock Net Delay (Source): 1.450ns (routing 0.362ns, distribution 1.088ns) + Clock Net Delay (Destination): 1.651ns (routing 0.401ns, distribution 1.250ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2226,13 +2232,13 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.386 1.599 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/overflow_reg_0 - SLICE_X88Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.450 1.663 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/overflow_reg_0 + SLICE_X80Y184 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/counter_lsb_reg[12]/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y170 FDRE (Prop_AFF_SLICEM_C_Q) - 0.058 1.657 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/Q - net (fo=37, routed) 0.109 1.766 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/pm_tick_d1_alias_2 - SLICE_X92Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/statshold_reg[23]/CE + SLICE_X80Y184 FDRE (Prop_EFF_SLICEL_C_Q) + 0.059 1.722 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/counter_lsb_reg[12]/Q + net (fo=3, routed) 0.110 1.832 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/counter_lsb_reg_n_0_[12] + SLICE_X82Y185 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/counter_lsb_d1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -2240,33 +2246,33 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.658 1.901 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/overflow_reg_0 - SLICE_X92Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/statshold_reg[23]/C - clock pessimism -0.133 1.768 - SLICE_X92Y170 FDRE (Hold_HFF_SLICEL_C_CE) - -0.014 1.754 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1024_1518_bytes_accumulator/statshold_reg[23] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.651 1.894 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/overflow_reg_0 + SLICE_X82Y185 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/counter_lsb_d1_reg[12]/C + clock pessimism -0.134 1.760 + SLICE_X82Y185 FDSE (Hold_AFF_SLICEL_C_D) + 0.060 1.820 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_large_accumulator/counter_lsb_d1_reg[12] ------------------------------------------------------------------- - required time -1.754 - arrival time 1.766 + required time -1.820 + arrival time 1.832 ------------------------------------------------------------------- slack 0.012 -Slack (MET) : 0.012ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/C +Slack (MET) : 0.014ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statshold_reg[24]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/statshold_reg[19]/CE + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statsout_reg[24]/D (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.167ns (logic 0.058ns (34.731%) route 0.109ns (65.269%)) + Data Path Delay: 0.173ns (logic 0.058ns (33.526%) route 0.115ns (66.474%)) Logic Levels: 0 - Clock Path Skew: 0.169ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.901ns - Source Clock Delay (SCD): 1.599ns - Clock Pessimism Removal (CPR): 0.133ns - Clock Net Delay (Source): 1.386ns (routing 0.362ns, distribution 1.024ns) - Clock Net Delay (Destination): 1.658ns (routing 0.401ns, distribution 1.257ns) + Clock Path Skew: 0.099ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.845ns + Source Clock Delay (SCD): 1.616ns + Clock Pessimism Removal (CPR): 0.130ns + Clock Net Delay (Source): 1.403ns (routing 0.362ns, distribution 1.041ns) + Clock Net Delay (Destination): 1.602ns (routing 0.401ns, distribution 1.201ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2275,13 +2281,13 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.386 1.599 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/overflow_reg_0 - SLICE_X88Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.403 1.616 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/overflow_reg_0 + SLICE_X80Y176 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statshold_reg[24]/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y170 FDRE (Prop_AFF_SLICEM_C_Q) - 0.058 1.657 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/Q - net (fo=37, routed) 0.109 1.766 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1 - SLICE_X91Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/statshold_reg[19]/CE + SLICE_X80Y176 FDRE (Prop_FFF_SLICEL_C_Q) + 0.058 1.674 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statshold_reg[24]/Q + net (fo=1, routed) 0.115 1.789 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statshold_reg_n_0_[24] + SLICE_X82Y177 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statsout_reg[24]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -2289,33 +2295,33 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.658 1.901 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/overflow_reg_0 - SLICE_X91Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/statshold_reg[19]/C - clock pessimism -0.133 1.768 - SLICE_X91Y170 FDRE (Hold_FFF_SLICEL_C_CE) - -0.014 1.754 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/statshold_reg[19] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.602 1.845 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/overflow_reg_0 + SLICE_X82Y177 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statsout_reg[24]/C + clock pessimism -0.130 1.715 + SLICE_X82Y177 FDRE (Hold_BFF_SLICEL_C_D) + 0.060 1.775 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statsout_reg[24] ------------------------------------------------------------------- - required time -1.754 - arrival time 1.766 + required time -1.775 + arrival time 1.789 ------------------------------------------------------------------- - slack 0.012 + slack 0.014 -Slack (MET) : 0.012ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/C +Slack (MET) : 0.015ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statshold_reg[5]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/statshold_reg[23]/CE + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statsout_reg[5]/D (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.167ns (logic 0.058ns (34.731%) route 0.109ns (65.269%)) + Data Path Delay: 0.194ns (logic 0.058ns (29.897%) route 0.136ns (70.103%)) Logic Levels: 0 - Clock Path Skew: 0.169ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.901ns - Source Clock Delay (SCD): 1.599ns - Clock Pessimism Removal (CPR): 0.133ns - Clock Net Delay (Source): 1.386ns (routing 0.362ns, distribution 1.024ns) - Clock Net Delay (Destination): 1.658ns (routing 0.401ns, distribution 1.257ns) + Clock Path Skew: 0.117ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.915ns + Source Clock Delay (SCD): 1.664ns + Clock Pessimism Removal (CPR): 0.134ns + Clock Net Delay (Source): 1.451ns (routing 0.362ns, distribution 1.089ns) + Clock Net Delay (Destination): 1.672ns (routing 0.401ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2324,13 +2330,13 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.386 1.599 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/overflow_reg_0 - SLICE_X88Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.451 1.664 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/overflow_reg_0 + SLICE_X79Y182 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statshold_reg[5]/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y170 FDRE (Prop_AFF_SLICEM_C_Q) - 0.058 1.657 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/Q - net (fo=37, routed) 0.109 1.766 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1 - SLICE_X92Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/statshold_reg[23]/CE + SLICE_X79Y182 FDRE (Prop_GFF_SLICEM_C_Q) + 0.058 1.722 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statshold_reg[5]/Q + net (fo=1, routed) 0.136 1.858 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statshold_reg_n_0_[5] + SLICE_X76Y182 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statsout_reg[5]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -2338,33 +2344,33 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.658 1.901 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/overflow_reg_0 - SLICE_X92Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/statshold_reg[23]/C - clock pessimism -0.133 1.768 - SLICE_X92Y170 FDRE (Hold_GFF_SLICEL_C_CE) - -0.014 1.754 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/statshold_reg[23] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.672 1.915 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/overflow_reg_0 + SLICE_X76Y182 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statsout_reg[5]/C + clock pessimism -0.134 1.781 + SLICE_X76Y182 FDRE (Hold_FFF2_SLICEL_C_D) + 0.062 1.843 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_8192_9215_bytes_accumulator/statsout_reg[5] ------------------------------------------------------------------- - required time -1.754 - arrival time 1.766 + required time -1.843 + arrival time 1.858 ------------------------------------------------------------------- - slack 0.012 + slack 0.015 -Slack (MET) : 0.012ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/C +Slack (MET) : 0.016ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/data_d3_reg[22]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/statshold_reg[19]/CE + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/data_d4_reg[22]/D (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.167ns (logic 0.058ns (34.731%) route 0.109ns (65.269%)) + Data Path Delay: 0.306ns (logic 0.058ns (18.954%) route 0.248ns (81.046%)) Logic Levels: 0 - Clock Path Skew: 0.169ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.901ns - Source Clock Delay (SCD): 1.599ns - Clock Pessimism Removal (CPR): 0.133ns - Clock Net Delay (Source): 1.386ns (routing 0.362ns, distribution 1.024ns) - Clock Net Delay (Destination): 1.658ns (routing 0.401ns, distribution 1.257ns) + Clock Path Skew: 0.230ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.035ns + Source Clock Delay (SCD): 1.736ns + Clock Pessimism Removal (CPR): 0.069ns + Clock Net Delay (Source): 1.523ns (routing 0.362ns, distribution 1.161ns) + Clock Net Delay (Destination): 1.792ns (routing 0.401ns, distribution 1.391ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2373,13 +2379,13 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.386 1.599 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/overflow_reg_0 - SLICE_X88Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.523 1.736 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/rx_serdes_clk + SLICE_X109Y176 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/data_d3_reg[22]/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y170 FDRE (Prop_AFF_SLICEM_C_Q) - 0.058 1.657 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/Q - net (fo=37, routed) 0.109 1.766 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/pm_tick_d1_alias_4 - SLICE_X91Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/statshold_reg[19]/CE + SLICE_X109Y176 FDRE (Prop_GFF_SLICEM_C_Q) + 0.058 1.794 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/data_d3_reg[22]/Q + net (fo=1, routed) 0.248 2.042 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/data_d3_reg_n_0_[22] + SLICE_X108Y182 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/data_d4_reg[22]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -2387,33 +2393,33 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.658 1.901 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/overflow_reg_0 - SLICE_X91Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/statshold_reg[19]/C - clock pessimism -0.133 1.768 - SLICE_X91Y170 FDRE (Hold_EFF_SLICEL_C_CE) - -0.014 1.754 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/statshold_reg[19] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.792 2.035 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/rx_serdes_clk + SLICE_X108Y182 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/data_d4_reg[22]/C + clock pessimism -0.069 1.966 + SLICE_X108Y182 FDRE (Hold_GFF_SLICEL_C_D) + 0.060 2.026 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_RX_TOP/i_RX_CORE/i_RX_DESTRIPER/i_RX_DECODER/data_d4_reg[22] ------------------------------------------------------------------- - required time -1.754 - arrival time 1.766 + required time -2.026 + arrival time 2.042 ------------------------------------------------------------------- - slack 0.012 + slack 0.016 -Slack (MET) : 0.012ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/statshold_reg[23]/CE +Slack (MET) : 0.016ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/counter_lsb_d1_reg[17]/C + (rising edge-triggered cell FDSE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/statshold_reg[17]/D (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.167ns (logic 0.058ns (34.731%) route 0.109ns (65.269%)) + Data Path Delay: 0.160ns (logic 0.060ns (37.500%) route 0.100ns (62.500%)) Logic Levels: 0 - Clock Path Skew: 0.169ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.901ns - Source Clock Delay (SCD): 1.599ns - Clock Pessimism Removal (CPR): 0.133ns - Clock Net Delay (Source): 1.386ns (routing 0.362ns, distribution 1.024ns) - Clock Net Delay (Destination): 1.658ns (routing 0.401ns, distribution 1.257ns) + Clock Path Skew: 0.084ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.941ns + Source Clock Delay (SCD): 1.717ns + Clock Pessimism Removal (CPR): 0.140ns + Clock Net Delay (Source): 1.504ns (routing 0.362ns, distribution 1.142ns) + Clock Net Delay (Destination): 1.698ns (routing 0.401ns, distribution 1.297ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2422,13 +2428,13 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.386 1.599 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/overflow_reg_0 - SLICE_X88Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.504 1.717 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/overflow_reg_0 + SLICE_X97Y203 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/counter_lsb_d1_reg[17]/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y170 FDRE (Prop_AFF_SLICEM_C_Q) - 0.058 1.657 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_d1_reg/Q - net (fo=37, routed) 0.109 1.766 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/pm_tick_d1_alias_4 - SLICE_X92Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/statshold_reg[23]/CE + SLICE_X97Y203 FDSE (Prop_EFF2_SLICEL_C_Q) + 0.060 1.777 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/counter_lsb_d1_reg[17]/Q + net (fo=1, routed) 0.100 1.877 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/p_0_in1_in[17] + SLICE_X98Y203 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/statshold_reg[17]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -2436,33 +2442,33 @@ Slack (MET) : 0.012ns (arrival time - required time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.658 1.901 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/overflow_reg_0 - SLICE_X92Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/statshold_reg[23]/C - clock pessimism -0.133 1.768 - SLICE_X92Y170 FDRE (Hold_FFF_SLICEL_C_CE) - -0.014 1.754 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_2048_4095_bytes_accumulator/statshold_reg[23] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.698 1.941 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/overflow_reg_0 + SLICE_X98Y203 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/statshold_reg[17]/C + clock pessimism -0.140 1.801 + SLICE_X98Y203 FDRE (Hold_DFF_SLICEL_C_D) + 0.060 1.861 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_256_511_bytes_accumulator/statshold_reg[17] ------------------------------------------------------------------- - required time -1.754 - arrival time 1.766 + required time -1.861 + arrival time 1.877 ------------------------------------------------------------------- - slack 0.012 + slack 0.016 -Slack (MET) : 0.013ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_r_reg/C +Slack (MET) : 0.017ns (arrival time - required time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_reg[45]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/counter_lsb_reg[6]/D + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[5].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[45]/D (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.222ns (logic 0.110ns (49.550%) route 0.112ns (50.450%)) - Logic Levels: 2 (CARRY8=1 LUT2=1) - Clock Path Skew: 0.149ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.881ns - Source Clock Delay (SCD): 1.599ns - Clock Pessimism Removal (CPR): 0.133ns - Clock Net Delay (Source): 1.386ns (routing 0.362ns, distribution 1.024ns) - Clock Net Delay (Destination): 1.638ns (routing 0.401ns, distribution 1.237ns) + Data Path Delay: 0.187ns (logic 0.080ns (42.781%) route 0.107ns (57.219%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.110ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.054ns + Source Clock Delay (SCD): 1.798ns + Clock Pessimism Removal (CPR): 0.146ns + Clock Net Delay (Source): 1.585ns (routing 0.362ns, distribution 1.223ns) + Clock Net Delay (Destination): 1.811ns (routing 0.401ns, distribution 1.410ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -2471,19 +2477,16 @@ Slack (MET) : 0.013ns (arrival time - required time) net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.386 1.599 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/overflow_reg_0 - SLICE_X88Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_r_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.585 1.798 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/m_axi_s2mm_aclk + SLICE_X51Y97 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_reg[45]/C ------------------------------------------------------------------- ------------------- - SLICE_X88Y170 FDRE (Prop_AFF2_SLICEM_C_Q) - 0.060 1.659 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_r_reg/Q - net (fo=28, routed) 0.087 1.746 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/pm_tick_r - SLICE_X89Y170 LUT2 (Prop_G6LUT_SLICEM_I1_O) - 0.022 1.768 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/counter_lsb[7]_i_4__21/O - net (fo=1, routed) 0.015 1.783 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/counter_lsb[7]_i_4__21_n_0 - SLICE_X89Y170 CARRY8 (Prop_CARRY8_SLICEM_S[6]_O[6]) - 0.028 1.811 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/counter_lsb_reg[7]_i_1__21/O[6] - net (fo=1, routed) 0.010 1.821 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/counter_lsb_reg[7]_i_1__21_n_9 - SLICE_X89Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/counter_lsb_reg[6]/D + SLICE_X51Y97 FDRE (Prop_CFF_SLICEL_C_Q) + 0.058 1.856 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_reg[45]/Q + net (fo=2, routed) 0.085 1.941 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/s_axi_wdata[45] + SLICE_X52Y96 LUT2 (Prop_G6LUT_SLICEL_I0_O) + 0.022 1.963 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[5].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1/O + net (fo=1, routed) 0.022 1.985 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[5].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0 + SLICE_X52Y96 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[5].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[45]/D ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -2491,16 +2494,16 @@ Slack (MET) : 0.013ns (arrival time - required time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.638 1.881 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/overflow_reg_0 - SLICE_X89Y170 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/counter_lsb_reg[6]/C - clock pessimism -0.133 1.748 - SLICE_X89Y170 FDRE (Hold_GFF_SLICEM_C_D) - 0.060 1.808 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_packet_1519_1522_bytes_accumulator/counter_lsb_reg[6] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.811 2.054 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/USE_RTL_LENGTH.length_counter_q_reg[0]_0 + SLICE_X52Y96 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[5].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[45]/C + clock pessimism -0.146 1.908 + SLICE_X52Y96 FDRE (Hold_GFF_SLICEL_C_D) + 0.060 1.968 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[5].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[45] ------------------------------------------------------------------- - required time -1.808 - arrival time 1.821 + required time -1.968 + arrival time 1.985 ------------------------------------------------------------------- - slack 0.013 + slack 0.017 @@ -2514,36 +2517,36 @@ Period(ns): 6.400 Sources: { pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y43 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_19/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X1Y68 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_49/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y52 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_2/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y55 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_5/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y44 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_20/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X0Y61 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y45 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_21/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X0Y62 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X0Y63 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y46 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_22/CLKARDCLK -Low Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y52 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_2/CLKBWRCLK -Low Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X0Y63 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52/CLKBWRCLK -Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y47 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_23/CLKBWRCLK -Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X0Y67 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_56/CLKARDCLK -Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X1Y55 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_60/CLKBWRCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X3Y61 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_19/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X1Y56 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_49/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y49 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_2/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y52 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_5/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X3Y62 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_20/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X0Y60 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X3Y63 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_21/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X0Y61 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X0Y62 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X3Y64 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_22/CLKARDCLK +Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X3Y61 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_19/CLKBWRCLK +Low Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y52 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_5/CLKBWRCLK +Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X1Y20 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/CLKARDCLK +Low Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X0Y63 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_53/CLKBWRCLK +Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X0Y67 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_57/CLKARDCLK +Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X3Y56 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_30/CLKBWRCLK Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X3Y57 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_31/CLKBWRCLK -Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X1Y59 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_64/CLKBWRCLK -Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y63 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_36/CLKARDCLK -Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y57 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_7/CLKBWRCLK -Low Pulse Width Fast RAMB18E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB18_X1Y30 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK -High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X1Y68 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_49/CLKARDCLK -High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y52 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_2/CLKARDCLK -High Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y55 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_5/CLKBWRCLK -High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y44 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_20/CLKBWRCLK -High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X0Y61 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/CLKARDCLK -High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X0Y61 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_50/CLKBWRCLK -High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X0Y62 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51/CLKARDCLK -High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X1Y20 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/CLKARDCLK -High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X1Y20 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/CLKBWRCLK -High Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X0Y63 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_52/CLKBWRCLK +Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y57 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_34/CLKBWRCLK +Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y51 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_4/CLKBWRCLK +Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y63 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_40/CLKARDCLK +High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X1Y56 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_49/CLKARDCLK +High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X1Y56 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_49/CLKBWRCLK +High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y49 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_2/CLKBWRCLK +High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y52 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_5/CLKARDCLK +High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X3Y62 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_20/CLKARDCLK +High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X3Y62 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_20/CLKARDCLK +High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X3Y62 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_20/CLKBWRCLK +High Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X3Y63 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_21/CLKBWRCLK +High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X0Y61 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51/CLKARDCLK +High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X0Y61 pl_eth_10g_i/rx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_51/CLKBWRCLK Max Skew Slow GTHE4_CHANNEL/RXUSRCLK2 GTHE4_CHANNEL/RXUSRCLK 0.737 0.196 0.541 GTHE4_CHANNEL_X0Y10 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Fast GTHE4_CHANNEL/RXUSRCLK2 GTHE4_CHANNEL/RXUSRCLK 0.759 0.123 0.636 GTHE4_CHANNEL_X0Y10 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXUSRCLK2 @@ -2553,15 +2556,15 @@ Max Skew Fast GTHE4_CHANNEL/RXUSRCLK2 GTHE4_CHANNEL/RXUSRCLK 0.759 From Clock: rxoutclkpcs_out[0] To Clock: rxoutclkpcs_out[0] -Setup : 0 Failing Endpoints, Worst Slack 2.121ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.022ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 2.002ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.068ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 1.277ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 2.121ns (required time - arrival time) +Slack (MET) : 2.002ns (required time - arrival time) Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/CE @@ -2569,12 +2572,12 @@ Slack (MET) : 2.121ns (required time - arrival time) Path Group: rxoutclkpcs_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 3.103ns (rxoutclkpcs_out[0] rise@3.103ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.684ns (logic 0.238ns (34.795%) route 0.446ns (65.205%)) + Data Path Delay: 0.893ns (logic 0.214ns (23.964%) route 0.679ns (76.036%)) Logic Levels: 1 (LUT2=1) - Clock Path Skew: -0.204ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 0.242ns = ( 3.345 - 3.103 ) - Source Clock Delay (SCD): 0.460ns - Clock Pessimism Removal (CPR): 0.014ns + Clock Path Skew: -0.114ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.198ns = ( 3.301 - 3.103 ) + Source Clock Delay (SCD): 0.322ns + Clock Pessimism Removal (CPR): 0.010ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns @@ -2586,34 +2589,294 @@ Slack (MET) : 2.121ns (required time - arrival time) (clock rxoutclkpcs_out[0] rise edge) 0.000 0.000 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.460 0.460 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C + net (fo=15, routed) 0.322 0.322 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X108Y150 FDCE (Prop_EFF2_SLICEL_C_Q) - 0.081 0.541 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/Q - net (fo=9, routed) 0.204 0.745 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4] - SLICE_X108Y150 LUT2 (Prop_D5LUT_SLICEL_I0_O) - 0.157 0.902 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[0]_i_1/O - net (fo=1, routed) 0.242 1.144 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[0]_i_1_n_0 - SLICE_X108Y151 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/CE + SLICE_X110Y158 FDCE (Prop_EFF2_SLICEL_C_Q) + 0.081 0.403 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/Q + net (fo=9, routed) 0.379 0.782 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4] + SLICE_X110Y158 LUT2 (Prop_D5LUT_SLICEL_I0_O) + 0.133 0.915 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[0]_i_1/O + net (fo=1, routed) 0.300 1.215 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[0]_i_1_n_0 + SLICE_X110Y159 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock rxoutclkpcs_out[0] rise edge) 3.103 3.103 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 3.103 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.242 3.345 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y151 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/C - clock pessimism 0.014 3.359 - clock uncertainty -0.035 3.324 - SLICE_X108Y151 FDRE (Setup_AFF2_SLICEL_C_CE) - -0.059 3.265 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0] + net (fo=15, routed) 0.198 3.301 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y159 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/C + clock pessimism 0.010 3.311 + clock uncertainty -0.035 3.276 + SLICE_X110Y159 FDRE (Setup_AFF2_SLICEL_C_CE) + -0.059 3.217 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0] ------------------------------------------------------------------- - required time 3.265 - arrival time -1.144 + required time 3.217 + arrival time -1.215 ------------------------------------------------------------------- - slack 2.121 + slack 2.002 -Slack (MET) : 2.464ns (required time - arrival time) +Slack (MET) : 2.228ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C + (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[0]/CE + (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Path Group: rxoutclkpcs_out[0] + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.103ns (rxoutclkpcs_out[0] rise@3.103ns - rxoutclkpcs_out[0] rise@0.000ns) + Data Path Delay: 0.603ns (logic 0.132ns (21.891%) route 0.471ns (78.109%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.177ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.189ns = ( 3.292 - 3.103 ) + Source Clock Delay (SCD): 0.379ns + Clock Pessimism Removal (CPR): 0.013ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock rxoutclkpcs_out[0] rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.379 0.379 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X111Y159 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X111Y159 FDCE (Prop_AFF2_SLICEL_C_Q) + 0.081 0.460 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q + net (fo=4, routed) 0.216 0.676 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm + SLICE_X110Y159 LUT1 (Prop_E6LUT_SLICEL_I0_O) + 0.051 0.727 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O + net (fo=12, routed) 0.255 0.982 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[0]/CE + ------------------------------------------------------------------- ------------------- + + (clock rxoutclkpcs_out[0] rise edge) + 3.103 3.103 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 3.103 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.189 3.292 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[0]/C + clock pessimism 0.013 3.305 + clock uncertainty -0.035 3.269 + SLICE_X110Y158 FDCE (Setup_AFF2_SLICEL_C_CE) + -0.059 3.210 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[0] + ------------------------------------------------------------------- + required time 3.210 + arrival time -0.982 + ------------------------------------------------------------------- + slack 2.228 + +Slack (MET) : 2.228ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C + (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/CE + (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Path Group: rxoutclkpcs_out[0] + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.103ns (rxoutclkpcs_out[0] rise@3.103ns - rxoutclkpcs_out[0] rise@0.000ns) + Data Path Delay: 0.603ns (logic 0.132ns (21.891%) route 0.471ns (78.109%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.177ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.189ns = ( 3.292 - 3.103 ) + Source Clock Delay (SCD): 0.379ns + Clock Pessimism Removal (CPR): 0.013ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock rxoutclkpcs_out[0] rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.379 0.379 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X111Y159 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X111Y159 FDCE (Prop_AFF2_SLICEL_C_Q) + 0.081 0.460 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q + net (fo=4, routed) 0.216 0.676 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm + SLICE_X110Y159 LUT1 (Prop_E6LUT_SLICEL_I0_O) + 0.051 0.727 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O + net (fo=12, routed) 0.255 0.982 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/CE + ------------------------------------------------------------------- ------------------- + + (clock rxoutclkpcs_out[0] rise edge) + 3.103 3.103 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 3.103 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.189 3.292 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/C + clock pessimism 0.013 3.305 + clock uncertainty -0.035 3.269 + SLICE_X110Y158 FDCE (Setup_BFF2_SLICEL_C_CE) + -0.059 3.210 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1] + ------------------------------------------------------------------- + required time 3.210 + arrival time -0.982 + ------------------------------------------------------------------- + slack 2.228 + +Slack (MET) : 2.228ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C + (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/CE + (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Path Group: rxoutclkpcs_out[0] + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.103ns (rxoutclkpcs_out[0] rise@3.103ns - rxoutclkpcs_out[0] rise@0.000ns) + Data Path Delay: 0.603ns (logic 0.132ns (21.891%) route 0.471ns (78.109%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.177ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.189ns = ( 3.292 - 3.103 ) + Source Clock Delay (SCD): 0.379ns + Clock Pessimism Removal (CPR): 0.013ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock rxoutclkpcs_out[0] rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.379 0.379 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X111Y159 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X111Y159 FDCE (Prop_AFF2_SLICEL_C_Q) + 0.081 0.460 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q + net (fo=4, routed) 0.216 0.676 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm + SLICE_X110Y159 LUT1 (Prop_E6LUT_SLICEL_I0_O) + 0.051 0.727 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O + net (fo=12, routed) 0.255 0.982 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/CE + ------------------------------------------------------------------- ------------------- + + (clock rxoutclkpcs_out[0] rise edge) + 3.103 3.103 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 3.103 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.189 3.292 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/C + clock pessimism 0.013 3.305 + clock uncertainty -0.035 3.269 + SLICE_X110Y158 FDCE (Setup_CFF2_SLICEL_C_CE) + -0.059 3.210 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2] + ------------------------------------------------------------------- + required time 3.210 + arrival time -0.982 + ------------------------------------------------------------------- + slack 2.228 + +Slack (MET) : 2.228ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C + (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/CE + (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Path Group: rxoutclkpcs_out[0] + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.103ns (rxoutclkpcs_out[0] rise@3.103ns - rxoutclkpcs_out[0] rise@0.000ns) + Data Path Delay: 0.603ns (logic 0.132ns (21.891%) route 0.471ns (78.109%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.177ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.189ns = ( 3.292 - 3.103 ) + Source Clock Delay (SCD): 0.379ns + Clock Pessimism Removal (CPR): 0.013ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock rxoutclkpcs_out[0] rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.379 0.379 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X111Y159 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X111Y159 FDCE (Prop_AFF2_SLICEL_C_Q) + 0.081 0.460 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q + net (fo=4, routed) 0.216 0.676 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm + SLICE_X110Y159 LUT1 (Prop_E6LUT_SLICEL_I0_O) + 0.051 0.727 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O + net (fo=12, routed) 0.255 0.982 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/CE + ------------------------------------------------------------------- ------------------- + + (clock rxoutclkpcs_out[0] rise edge) + 3.103 3.103 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 3.103 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.189 3.292 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/C + clock pessimism 0.013 3.305 + clock uncertainty -0.035 3.269 + SLICE_X110Y158 FDCE (Setup_DFF2_SLICEL_C_CE) + -0.059 3.210 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3] + ------------------------------------------------------------------- + required time 3.210 + arrival time -0.982 + ------------------------------------------------------------------- + slack 2.228 + +Slack (MET) : 2.299ns (required time - arrival time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C + (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/CE + (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Path Group: rxoutclkpcs_out[0] + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.103ns (rxoutclkpcs_out[0] rise@3.103ns - rxoutclkpcs_out[0] rise@0.000ns) + Data Path Delay: 0.533ns (logic 0.132ns (24.765%) route 0.401ns (75.235%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.175ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.191ns = ( 3.294 - 3.103 ) + Source Clock Delay (SCD): 0.379ns + Clock Pessimism Removal (CPR): 0.013ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock rxoutclkpcs_out[0] rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.379 0.379 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X111Y159 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X111Y159 FDCE (Prop_AFF2_SLICEL_C_Q) + 0.081 0.460 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q + net (fo=4, routed) 0.216 0.676 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm + SLICE_X110Y159 LUT1 (Prop_E6LUT_SLICEL_I0_O) + 0.051 0.727 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O + net (fo=12, routed) 0.185 0.912 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/CE + ------------------------------------------------------------------- ------------------- + + (clock rxoutclkpcs_out[0] rise edge) + 3.103 3.103 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 3.103 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.191 3.294 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C + clock pessimism 0.013 3.307 + clock uncertainty -0.035 3.271 + SLICE_X110Y158 FDCE (Setup_EFF2_SLICEL_C_CE) + -0.060 3.211 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4] + ------------------------------------------------------------------- + required time 3.211 + arrival time -0.912 + ------------------------------------------------------------------- + slack 2.299 + +Slack (MET) : 2.366ns (required time - arrival time) Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[5]/CE @@ -2621,12 +2884,12 @@ Slack (MET) : 2.464ns (required time - arrival time) Path Group: rxoutclkpcs_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 3.103ns (rxoutclkpcs_out[0] rise@3.103ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.437ns (logic 0.131ns (29.977%) route 0.306ns (70.023%)) + Data Path Delay: 0.648ns (logic 0.132ns (20.370%) route 0.516ns (79.630%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.106ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 0.241ns = ( 3.344 - 3.103 ) - Source Clock Delay (SCD): 0.437ns - Clock Pessimism Removal (CPR): 0.090ns + Clock Path Skew: 0.006ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.234ns = ( 3.337 - 3.103 ) + Source Clock Delay (SCD): 0.379ns + Clock Pessimism Removal (CPR): 0.151ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns @@ -2638,34 +2901,34 @@ Slack (MET) : 2.464ns (required time - arrival time) (clock rxoutclkpcs_out[0] rise edge) 0.000 0.000 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.437 0.437 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X109Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C + net (fo=15, routed) 0.379 0.379 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X111Y159 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X109Y150 FDCE (Prop_AFF2_SLICEM_C_Q) - 0.080 0.517 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q - net (fo=4, routed) 0.105 0.622 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm - SLICE_X108Y150 LUT1 (Prop_H6LUT_SLICEL_I0_O) - 0.051 0.673 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O - net (fo=12, routed) 0.201 0.874 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[5]/CE + SLICE_X111Y159 FDCE (Prop_AFF2_SLICEL_C_Q) + 0.081 0.460 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q + net (fo=4, routed) 0.216 0.676 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm + SLICE_X110Y159 LUT1 (Prop_E6LUT_SLICEL_I0_O) + 0.051 0.727 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O + net (fo=12, routed) 0.300 1.027 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock rxoutclkpcs_out[0] rise edge) 3.103 3.103 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 3.103 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.241 3.344 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[5]/C - clock pessimism 0.090 3.434 - clock uncertainty -0.035 3.398 - SLICE_X108Y152 FDRE (Setup_EFF2_SLICEL_C_CE) - -0.060 3.338 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[5] + net (fo=15, routed) 0.234 3.337 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[5]/C + clock pessimism 0.151 3.488 + clock uncertainty -0.035 3.453 + SLICE_X110Y160 FDRE (Setup_EFF2_SLICEL_C_CE) + -0.060 3.393 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[5] ------------------------------------------------------------------- - required time 3.338 - arrival time -0.874 + required time 3.393 + arrival time -1.027 ------------------------------------------------------------------- - slack 2.464 + slack 2.366 -Slack (MET) : 2.464ns (required time - arrival time) +Slack (MET) : 2.366ns (required time - arrival time) Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[6]/CE @@ -2673,12 +2936,12 @@ Slack (MET) : 2.464ns (required time - arrival time) Path Group: rxoutclkpcs_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 3.103ns (rxoutclkpcs_out[0] rise@3.103ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.437ns (logic 0.131ns (29.977%) route 0.306ns (70.023%)) + Data Path Delay: 0.648ns (logic 0.132ns (20.370%) route 0.516ns (79.630%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.106ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 0.241ns = ( 3.344 - 3.103 ) - Source Clock Delay (SCD): 0.437ns - Clock Pessimism Removal (CPR): 0.090ns + Clock Path Skew: 0.006ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.234ns = ( 3.337 - 3.103 ) + Source Clock Delay (SCD): 0.379ns + Clock Pessimism Removal (CPR): 0.151ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns @@ -2690,34 +2953,34 @@ Slack (MET) : 2.464ns (required time - arrival time) (clock rxoutclkpcs_out[0] rise edge) 0.000 0.000 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.437 0.437 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X109Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C + net (fo=15, routed) 0.379 0.379 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X111Y159 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X109Y150 FDCE (Prop_AFF2_SLICEM_C_Q) - 0.080 0.517 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q - net (fo=4, routed) 0.105 0.622 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm - SLICE_X108Y150 LUT1 (Prop_H6LUT_SLICEL_I0_O) - 0.051 0.673 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O - net (fo=12, routed) 0.201 0.874 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[6]/CE + SLICE_X111Y159 FDCE (Prop_AFF2_SLICEL_C_Q) + 0.081 0.460 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q + net (fo=4, routed) 0.216 0.676 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm + SLICE_X110Y159 LUT1 (Prop_E6LUT_SLICEL_I0_O) + 0.051 0.727 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O + net (fo=12, routed) 0.300 1.027 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock rxoutclkpcs_out[0] rise edge) 3.103 3.103 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 3.103 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.241 3.344 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[6]/C - clock pessimism 0.090 3.434 - clock uncertainty -0.035 3.398 - SLICE_X108Y152 FDRE (Setup_FFF2_SLICEL_C_CE) - -0.060 3.338 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[6] + net (fo=15, routed) 0.234 3.337 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[6]/C + clock pessimism 0.151 3.488 + clock uncertainty -0.035 3.453 + SLICE_X110Y160 FDRE (Setup_FFF2_SLICEL_C_CE) + -0.060 3.393 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[6] ------------------------------------------------------------------- - required time 3.338 - arrival time -0.874 + required time 3.393 + arrival time -1.027 ------------------------------------------------------------------- - slack 2.464 + slack 2.366 -Slack (MET) : 2.464ns (required time - arrival time) +Slack (MET) : 2.366ns (required time - arrival time) Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7]/CE @@ -2725,12 +2988,12 @@ Slack (MET) : 2.464ns (required time - arrival time) Path Group: rxoutclkpcs_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 3.103ns (rxoutclkpcs_out[0] rise@3.103ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.437ns (logic 0.131ns (29.977%) route 0.306ns (70.023%)) + Data Path Delay: 0.648ns (logic 0.132ns (20.370%) route 0.516ns (79.630%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.106ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 0.241ns = ( 3.344 - 3.103 ) - Source Clock Delay (SCD): 0.437ns - Clock Pessimism Removal (CPR): 0.090ns + Clock Path Skew: 0.006ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.234ns = ( 3.337 - 3.103 ) + Source Clock Delay (SCD): 0.379ns + Clock Pessimism Removal (CPR): 0.151ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns @@ -2742,34 +3005,34 @@ Slack (MET) : 2.464ns (required time - arrival time) (clock rxoutclkpcs_out[0] rise edge) 0.000 0.000 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.437 0.437 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X109Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C + net (fo=15, routed) 0.379 0.379 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X111Y159 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X109Y150 FDCE (Prop_AFF2_SLICEM_C_Q) - 0.080 0.517 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q - net (fo=4, routed) 0.105 0.622 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm - SLICE_X108Y150 LUT1 (Prop_H6LUT_SLICEL_I0_O) - 0.051 0.673 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O - net (fo=12, routed) 0.201 0.874 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7]/CE + SLICE_X111Y159 FDCE (Prop_AFF2_SLICEL_C_Q) + 0.081 0.460 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q + net (fo=4, routed) 0.216 0.676 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm + SLICE_X110Y159 LUT1 (Prop_E6LUT_SLICEL_I0_O) + 0.051 0.727 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O + net (fo=12, routed) 0.300 1.027 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock rxoutclkpcs_out[0] rise edge) 3.103 3.103 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 3.103 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.241 3.344 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7]/C - clock pessimism 0.090 3.434 - clock uncertainty -0.035 3.398 - SLICE_X108Y152 FDRE (Setup_GFF2_SLICEL_C_CE) - -0.060 3.338 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7] + net (fo=15, routed) 0.234 3.337 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7]/C + clock pessimism 0.151 3.488 + clock uncertainty -0.035 3.453 + SLICE_X110Y160 FDRE (Setup_GFF2_SLICEL_C_CE) + -0.060 3.393 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7] ------------------------------------------------------------------- - required time 3.338 - arrival time -0.874 + required time 3.393 + arrival time -1.027 ------------------------------------------------------------------- - slack 2.464 + slack 2.366 -Slack (MET) : 2.469ns (required time - arrival time) +Slack (MET) : 2.403ns (required time - arrival time) Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/CE @@ -2777,12 +3040,12 @@ Slack (MET) : 2.469ns (required time - arrival time) Path Group: rxoutclkpcs_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 3.103ns (rxoutclkpcs_out[0] rise@3.103ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.431ns (logic 0.131ns (30.394%) route 0.300ns (69.606%)) + Data Path Delay: 0.610ns (logic 0.132ns (21.639%) route 0.478ns (78.361%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.108ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 0.239ns = ( 3.342 - 3.103 ) - Source Clock Delay (SCD): 0.437ns - Clock Pessimism Removal (CPR): 0.090ns + Clock Path Skew: 0.004ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.232ns = ( 3.335 - 3.103 ) + Source Clock Delay (SCD): 0.379ns + Clock Pessimism Removal (CPR): 0.151ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns @@ -2794,286 +3057,32 @@ Slack (MET) : 2.469ns (required time - arrival time) (clock rxoutclkpcs_out[0] rise edge) 0.000 0.000 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.437 0.437 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X109Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C + net (fo=15, routed) 0.379 0.379 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X111Y159 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X109Y150 FDCE (Prop_AFF2_SLICEM_C_Q) - 0.080 0.517 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q - net (fo=4, routed) 0.105 0.622 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm - SLICE_X108Y150 LUT1 (Prop_H6LUT_SLICEL_I0_O) - 0.051 0.673 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O - net (fo=12, routed) 0.195 0.868 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/CE + SLICE_X111Y159 FDCE (Prop_AFF2_SLICEL_C_Q) + 0.081 0.460 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q + net (fo=4, routed) 0.216 0.676 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm + SLICE_X110Y159 LUT1 (Prop_E6LUT_SLICEL_I0_O) + 0.051 0.727 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O + net (fo=12, routed) 0.262 0.989 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock rxoutclkpcs_out[0] rise edge) 3.103 3.103 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 3.103 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.239 3.342 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/C - clock pessimism 0.090 3.432 - clock uncertainty -0.035 3.396 - SLICE_X108Y152 FDRE (Setup_AFF2_SLICEL_C_CE) - -0.059 3.337 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1] + net (fo=15, routed) 0.232 3.335 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/C + clock pessimism 0.151 3.486 + clock uncertainty -0.035 3.451 + SLICE_X110Y160 FDRE (Setup_AFF2_SLICEL_C_CE) + -0.059 3.392 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1] ------------------------------------------------------------------- - required time 3.337 - arrival time -0.868 + required time 3.392 + arrival time -0.989 ------------------------------------------------------------------- - slack 2.469 - -Slack (MET) : 2.469ns (required time - arrival time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C - (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/CE - (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Path Group: rxoutclkpcs_out[0] - Path Type: Setup (Max at Slow Process Corner) - Requirement: 3.103ns (rxoutclkpcs_out[0] rise@3.103ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.431ns (logic 0.131ns (30.394%) route 0.300ns (69.606%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.108ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 0.239ns = ( 3.342 - 3.103 ) - Source Clock Delay (SCD): 0.437ns - Clock Pessimism Removal (CPR): 0.090ns - Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.000ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock rxoutclkpcs_out[0] rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.437 0.437 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X109Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X109Y150 FDCE (Prop_AFF2_SLICEM_C_Q) - 0.080 0.517 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q - net (fo=4, routed) 0.105 0.622 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm - SLICE_X108Y150 LUT1 (Prop_H6LUT_SLICEL_I0_O) - 0.051 0.673 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O - net (fo=12, routed) 0.195 0.868 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/CE - ------------------------------------------------------------------- ------------------- - - (clock rxoutclkpcs_out[0] rise edge) - 3.103 3.103 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 3.103 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.239 3.342 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/C - clock pessimism 0.090 3.432 - clock uncertainty -0.035 3.396 - SLICE_X108Y152 FDRE (Setup_BFF2_SLICEL_C_CE) - -0.059 3.337 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2] - ------------------------------------------------------------------- - required time 3.337 - arrival time -0.868 - ------------------------------------------------------------------- - slack 2.469 - -Slack (MET) : 2.469ns (required time - arrival time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C - (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/CE - (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Path Group: rxoutclkpcs_out[0] - Path Type: Setup (Max at Slow Process Corner) - Requirement: 3.103ns (rxoutclkpcs_out[0] rise@3.103ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.431ns (logic 0.131ns (30.394%) route 0.300ns (69.606%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.108ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 0.239ns = ( 3.342 - 3.103 ) - Source Clock Delay (SCD): 0.437ns - Clock Pessimism Removal (CPR): 0.090ns - Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.000ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock rxoutclkpcs_out[0] rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.437 0.437 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X109Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X109Y150 FDCE (Prop_AFF2_SLICEM_C_Q) - 0.080 0.517 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q - net (fo=4, routed) 0.105 0.622 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm - SLICE_X108Y150 LUT1 (Prop_H6LUT_SLICEL_I0_O) - 0.051 0.673 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O - net (fo=12, routed) 0.195 0.868 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/CE - ------------------------------------------------------------------- ------------------- - - (clock rxoutclkpcs_out[0] rise edge) - 3.103 3.103 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 3.103 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.239 3.342 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/C - clock pessimism 0.090 3.432 - clock uncertainty -0.035 3.396 - SLICE_X108Y152 FDRE (Setup_CFF2_SLICEL_C_CE) - -0.059 3.337 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3] - ------------------------------------------------------------------- - required time 3.337 - arrival time -0.868 - ------------------------------------------------------------------- - slack 2.469 - -Slack (MET) : 2.469ns (required time - arrival time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C - (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4]/CE - (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Path Group: rxoutclkpcs_out[0] - Path Type: Setup (Max at Slow Process Corner) - Requirement: 3.103ns (rxoutclkpcs_out[0] rise@3.103ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.431ns (logic 0.131ns (30.394%) route 0.300ns (69.606%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.108ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 0.239ns = ( 3.342 - 3.103 ) - Source Clock Delay (SCD): 0.437ns - Clock Pessimism Removal (CPR): 0.090ns - Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.000ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock rxoutclkpcs_out[0] rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.437 0.437 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X109Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X109Y150 FDCE (Prop_AFF2_SLICEM_C_Q) - 0.080 0.517 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q - net (fo=4, routed) 0.105 0.622 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm - SLICE_X108Y150 LUT1 (Prop_H6LUT_SLICEL_I0_O) - 0.051 0.673 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1/O - net (fo=12, routed) 0.195 0.868 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4]_i_1_n_0 - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4]/CE - ------------------------------------------------------------------- ------------------- - - (clock rxoutclkpcs_out[0] rise edge) - 3.103 3.103 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 3.103 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.239 3.342 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4]/C - clock pessimism 0.090 3.432 - clock uncertainty -0.035 3.396 - SLICE_X108Y152 FDRE (Setup_DFF2_SLICEL_C_CE) - -0.059 3.337 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4] - ------------------------------------------------------------------- - required time 3.337 - arrival time -0.868 - ------------------------------------------------------------------- - slack 2.469 - -Slack (MET) : 2.493ns (required time - arrival time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C - (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/R - (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Path Group: rxoutclkpcs_out[0] - Path Type: Setup (Max at Slow Process Corner) - Requirement: 3.103ns (rxoutclkpcs_out[0] rise@3.103ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.369ns (logic 0.081ns (21.951%) route 0.288ns (78.049%)) - Logic Levels: 0 - Clock Path Skew: -0.131ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 0.239ns = ( 3.342 - 3.103 ) - Source Clock Delay (SCD): 0.460ns - Clock Pessimism Removal (CPR): 0.090ns - Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.000ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock rxoutclkpcs_out[0] rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.460 0.460 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X108Y150 FDCE (Prop_EFF2_SLICEL_C_Q) - 0.081 0.541 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/Q - net (fo=9, routed) 0.288 0.829 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/R (IS_INVERTED) - ------------------------------------------------------------------- ------------------- - - (clock rxoutclkpcs_out[0] rise edge) - 3.103 3.103 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 3.103 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.239 3.342 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/C - clock pessimism 0.090 3.432 - clock uncertainty -0.035 3.396 - SLICE_X108Y152 FDRE (Setup_AFF2_SLICEL_C_R) - -0.074 3.322 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1] - ------------------------------------------------------------------- - required time 3.322 - arrival time -0.829 - ------------------------------------------------------------------- - slack 2.493 - -Slack (MET) : 2.493ns (required time - arrival time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C - (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/R - (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Path Group: rxoutclkpcs_out[0] - Path Type: Setup (Max at Slow Process Corner) - Requirement: 3.103ns (rxoutclkpcs_out[0] rise@3.103ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.369ns (logic 0.081ns (21.951%) route 0.288ns (78.049%)) - Logic Levels: 0 - Clock Path Skew: -0.131ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 0.239ns = ( 3.342 - 3.103 ) - Source Clock Delay (SCD): 0.460ns - Clock Pessimism Removal (CPR): 0.090ns - Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.000ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock rxoutclkpcs_out[0] rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.460 0.460 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X108Y150 FDCE (Prop_EFF2_SLICEL_C_Q) - 0.081 0.541 f pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/Q - net (fo=9, routed) 0.288 0.829 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/R (IS_INVERTED) - ------------------------------------------------------------------- ------------------- - - (clock rxoutclkpcs_out[0] rise edge) - 3.103 3.103 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 3.103 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.239 3.342 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/C - clock pessimism 0.090 3.432 - clock uncertainty -0.035 3.396 - SLICE_X108Y152 FDRE (Setup_BFF2_SLICEL_C_R) - -0.074 3.322 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2] - ------------------------------------------------------------------- - required time 3.322 - arrival time -0.829 - ------------------------------------------------------------------- - slack 2.493 + slack 2.403 @@ -3081,179 +3090,136 @@ Slack (MET) : 2.493ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.022ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C - (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.pwr_on_fsm_reg/D +Slack (MET) : 0.068ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/C + (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/D (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) Path Group: rxoutclkpcs_out[0] - Path Type: Hold (Min at Slow Process Corner) + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclkpcs_out[0] rise@0.000ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.174ns (logic 0.060ns (34.483%) route 0.114ns (65.517%)) + Data Path Delay: 0.121ns (logic 0.040ns (33.058%) route 0.081ns (66.942%)) Logic Levels: 0 - Clock Path Skew: 0.090ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 0.384ns - Source Clock Delay (SCD): 0.280ns - Clock Pessimism Removal (CPR): 0.014ns + Clock Path Skew: 0.006ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.218ns + Source Clock Delay (SCD): 0.174ns + Clock Pessimism Removal (CPR): 0.038ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclkpcs_out[0] rise edge) 0.000 0.000 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.280 0.280 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X109Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C + net (fo=15, routed) 0.174 0.174 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X109Y150 FDCE (Prop_AFF2_SLICEM_C_Q) - 0.060 0.340 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/Q - net (fo=4, routed) 0.114 0.454 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm - SLICE_X109Y151 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.pwr_on_fsm_reg/D + SLICE_X110Y160 FDRE (Prop_AFF2_SLICEL_C_Q) + 0.040 0.214 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/Q + net (fo=1, routed) 0.081 0.295 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[1] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/D ------------------------------------------------------------------- ------------------- (clock rxoutclkpcs_out[0] rise edge) 0.000 0.000 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.384 0.384 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X109Y151 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.pwr_on_fsm_reg/C - clock pessimism -0.014 0.370 - SLICE_X109Y151 FDRE (Hold_AFF2_SLICEM_C_D) - 0.062 0.432 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.pwr_on_fsm_reg + net (fo=15, routed) 0.218 0.218 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/C + clock pessimism -0.038 0.180 + SLICE_X110Y160 FDRE (Hold_BFF2_SLICEL_C_D) + 0.047 0.227 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2] ------------------------------------------------------------------- - required time -0.432 - arrival time 0.454 + required time -0.227 + arrival time 0.295 ------------------------------------------------------------------- - slack 0.022 + slack 0.068 -Slack (MET) : 0.055ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/C - (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/D - (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Path Group: rxoutclkpcs_out[0] - Path Type: Hold (Min at Slow Process Corner) - Requirement: 0.000ns (rxoutclkpcs_out[0] rise@0.000ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.256ns (logic 0.060ns (23.438%) route 0.196ns (76.562%)) - Logic Levels: 0 - Clock Path Skew: 0.139ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 0.395ns - Source Clock Delay (SCD): 0.242ns - Clock Pessimism Removal (CPR): 0.014ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock rxoutclkpcs_out[0] rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.242 0.242 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y151 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X108Y151 FDRE (Prop_AFF2_SLICEL_C_Q) - 0.060 0.302 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/Q - net (fo=1, routed) 0.196 0.498 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock rxoutclkpcs_out[0] rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.395 0.395 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/C - clock pessimism -0.014 0.381 - SLICE_X108Y152 FDRE (Hold_AFF2_SLICEL_C_D) - 0.062 0.443 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1] - ------------------------------------------------------------------- - required time -0.443 - arrival time 0.498 - ------------------------------------------------------------------- - slack 0.055 - -Slack (MET) : 0.059ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C +Slack (MET) : 0.069ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/C (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/D - (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Path Group: rxoutclkpcs_out[0] - Path Type: Hold (Min at Slow Process Corner) - Requirement: 0.000ns (rxoutclkpcs_out[0] rise@0.000ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.201ns (logic 0.060ns (29.851%) route 0.141ns (70.149%)) - Logic Levels: 0 - Clock Path Skew: 0.080ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 0.376ns - Source Clock Delay (SCD): 0.282ns - Clock Pessimism Removal (CPR): 0.014ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock rxoutclkpcs_out[0] rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.282 0.282 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X108Y150 FDCE (Prop_EFF2_SLICEL_C_Q) - 0.060 0.342 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/Q - net (fo=9, routed) 0.141 0.483 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4] - SLICE_X108Y151 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock rxoutclkpcs_out[0] rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.376 0.376 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y151 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/C - clock pessimism -0.014 0.362 - SLICE_X108Y151 FDRE (Hold_AFF2_SLICEL_C_D) - 0.062 0.424 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0] - ------------------------------------------------------------------- - required time -0.424 - arrival time 0.483 - ------------------------------------------------------------------- - slack 0.059 - -Slack (MET) : 0.093ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/C - (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/D + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/D (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) Path Group: rxoutclkpcs_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclkpcs_out[0] rise@0.000ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.146ns (logic 0.040ns (27.397%) route 0.106ns (72.603%)) + Data Path Delay: 0.122ns (logic 0.040ns (32.787%) route 0.082ns (67.213%)) Logic Levels: 0 Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 0.265ns - Source Clock Delay (SCD): 0.208ns - Clock Pessimism Removal (CPR): 0.051ns + Destination Clock Delay (DCD): 0.176ns + Source Clock Delay (SCD): 0.141ns + Clock Pessimism Removal (CPR): 0.029ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclkpcs_out[0] rise edge) 0.000 0.000 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.208 0.208 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/C + net (fo=15, routed) 0.141 0.141 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X108Y150 FDCE (Prop_BFF2_SLICEL_C_Q) - 0.040 0.248 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/Q - net (fo=1, routed) 0.106 0.354 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[1] - SLICE_X108Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/D + SLICE_X110Y158 FDCE (Prop_CFF2_SLICEL_C_Q) + 0.040 0.181 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/Q + net (fo=1, routed) 0.082 0.263 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[2] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/D ------------------------------------------------------------------- ------------------- (clock rxoutclkpcs_out[0] rise edge) 0.000 0.000 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.265 0.265 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/C - clock pessimism -0.051 0.214 - SLICE_X108Y150 FDCE (Hold_CFF2_SLICEL_C_D) - 0.047 0.261 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2] + net (fo=15, routed) 0.176 0.176 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/C + clock pessimism -0.029 0.147 + SLICE_X110Y158 FDCE (Hold_DFF2_SLICEL_C_D) + 0.047 0.194 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3] ------------------------------------------------------------------- - required time -0.261 - arrival time 0.354 + required time -0.194 + arrival time 0.263 ------------------------------------------------------------------- - slack 0.093 + slack 0.069 -Slack (MET) : 0.109ns (arrival time - required time) +Slack (MET) : 0.069ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/C + (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4]/D + (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Path Group: rxoutclkpcs_out[0] + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (rxoutclkpcs_out[0] rise@0.000ns - rxoutclkpcs_out[0] rise@0.000ns) + Data Path Delay: 0.122ns (logic 0.040ns (32.787%) route 0.082ns (67.213%)) + Logic Levels: 0 + Clock Path Skew: 0.006ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.218ns + Source Clock Delay (SCD): 0.174ns + Clock Pessimism Removal (CPR): 0.038ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock rxoutclkpcs_out[0] rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.174 0.174 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X110Y160 FDRE (Prop_CFF2_SLICEL_C_Q) + 0.040 0.214 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/Q + net (fo=1, routed) 0.082 0.296 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[3] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock rxoutclkpcs_out[0] rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.218 0.218 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4]/C + clock pessimism -0.038 0.180 + SLICE_X110Y160 FDRE (Hold_DFF2_SLICEL_C_D) + 0.047 0.227 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4] + ------------------------------------------------------------------- + required time -0.227 + arrival time 0.296 + ------------------------------------------------------------------- + slack 0.069 + +Slack (MET) : 0.070ns (arrival time - required time) Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4]/C (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[5]/D @@ -3261,10 +3227,182 @@ Slack (MET) : 0.109ns (arrival time - required time) Path Group: rxoutclkpcs_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclkpcs_out[0] rise@0.000ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.171ns (logic 0.041ns (23.977%) route 0.130ns (76.023%)) + Data Path Delay: 0.132ns (logic 0.041ns (31.061%) route 0.091ns (68.939%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 0.231ns + Destination Clock Delay (DCD): 0.222ns + Source Clock Delay (SCD): 0.174ns + Clock Pessimism Removal (CPR): 0.033ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock rxoutclkpcs_out[0] rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.174 0.174 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X110Y160 FDRE (Prop_DFF2_SLICEL_C_Q) + 0.041 0.215 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4]/Q + net (fo=1, routed) 0.091 0.306 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[4] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock rxoutclkpcs_out[0] rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.222 0.222 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[5]/C + clock pessimism -0.033 0.189 + SLICE_X110Y160 FDRE (Hold_EFF2_SLICEL_C_D) + 0.047 0.236 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[5] + ------------------------------------------------------------------- + required time -0.236 + arrival time 0.306 + ------------------------------------------------------------------- + slack 0.070 + +Slack (MET) : 0.070ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/C + (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/D + (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Path Group: rxoutclkpcs_out[0] + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (rxoutclkpcs_out[0] rise@0.000ns - rxoutclkpcs_out[0] rise@0.000ns) + Data Path Delay: 0.132ns (logic 0.041ns (31.061%) route 0.091ns (68.939%)) + Logic Levels: 0 + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.180ns + Source Clock Delay (SCD): 0.141ns + Clock Pessimism Removal (CPR): 0.024ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock rxoutclkpcs_out[0] rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.141 0.141 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X110Y158 FDCE (Prop_DFF2_SLICEL_C_Q) + 0.041 0.182 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/Q + net (fo=1, routed) 0.091 0.273 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[3] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock rxoutclkpcs_out[0] rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.180 0.180 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C + clock pessimism -0.024 0.156 + SLICE_X110Y158 FDCE (Hold_EFF2_SLICEL_C_D) + 0.047 0.203 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4] + ------------------------------------------------------------------- + required time -0.203 + arrival time 0.273 + ------------------------------------------------------------------- + slack 0.070 + +Slack (MET) : 0.080ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C + (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/D + (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Path Group: rxoutclkpcs_out[0] + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (rxoutclkpcs_out[0] rise@0.000ns - rxoutclkpcs_out[0] rise@0.000ns) + Data Path Delay: 0.257ns (logic 0.060ns (23.346%) route 0.197ns (76.654%)) + Logic Levels: 0 + Clock Path Skew: 0.115ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.316ns + Source Clock Delay (SCD): 0.191ns + Clock Pessimism Removal (CPR): 0.010ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock rxoutclkpcs_out[0] rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.191 0.191 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X110Y158 FDCE (Prop_EFF2_SLICEL_C_Q) + 0.060 0.251 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/Q + net (fo=9, routed) 0.197 0.448 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[4] + SLICE_X110Y159 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock rxoutclkpcs_out[0] rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.316 0.316 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y159 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/C + clock pessimism -0.010 0.306 + SLICE_X110Y159 FDRE (Hold_AFF2_SLICEL_C_D) + 0.062 0.368 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0] + ------------------------------------------------------------------- + required time -0.368 + arrival time 0.448 + ------------------------------------------------------------------- + slack 0.080 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[0]/C + (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/D + (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Path Group: rxoutclkpcs_out[0] + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (rxoutclkpcs_out[0] rise@0.000ns - rxoutclkpcs_out[0] rise@0.000ns) + Data Path Delay: 0.139ns (logic 0.040ns (28.777%) route 0.099ns (71.223%)) + Logic Levels: 0 + Clock Path Skew: 0.006ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.176ns + Source Clock Delay (SCD): 0.141ns + Clock Pessimism Removal (CPR): 0.029ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock rxoutclkpcs_out[0] rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.141 0.141 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X110Y158 FDCE (Prop_AFF2_SLICEL_C_Q) + 0.040 0.181 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[0]/Q + net (fo=1, routed) 0.099 0.280 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock rxoutclkpcs_out[0] rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS + net (fo=15, routed) 0.176 0.176 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/C + clock pessimism -0.029 0.147 + SLICE_X110Y158 FDCE (Hold_BFF2_SLICEL_C_D) + 0.047 0.194 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1] + ------------------------------------------------------------------- + required time -0.194 + arrival time 0.280 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[6]/C + (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7]/D + (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) + Path Group: rxoutclkpcs_out[0] + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (rxoutclkpcs_out[0] rise@0.000ns - rxoutclkpcs_out[0] rise@0.000ns) + Data Path Delay: 0.139ns (logic 0.040ns (28.777%) route 0.099ns (71.223%)) + Logic Levels: 0 + Clock Path Skew: 0.006ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.222ns Source Clock Delay (SCD): 0.177ns Clock Pessimism Removal (CPR): 0.039ns @@ -3274,201 +3412,72 @@ Slack (MET) : 0.109ns (arrival time - required time) 0.000 0.000 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS net (fo=15, routed) 0.177 0.177 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4]/C + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[6]/C ------------------------------------------------------------------- ------------------- - SLICE_X108Y152 FDRE (Prop_DFF2_SLICEL_C_Q) - 0.041 0.218 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4]/Q - net (fo=1, routed) 0.130 0.348 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[4] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[5]/D + SLICE_X110Y160 FDRE (Prop_FFF2_SLICEL_C_Q) + 0.040 0.217 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[6]/Q + net (fo=1, routed) 0.099 0.316 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[6] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7]/D ------------------------------------------------------------------- ------------------- (clock rxoutclkpcs_out[0] rise edge) 0.000 0.000 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.231 0.231 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[5]/C - clock pessimism -0.039 0.192 - SLICE_X108Y152 FDRE (Hold_EFF2_SLICEL_C_D) - 0.047 0.239 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[5] - ------------------------------------------------------------------- - required time -0.239 - arrival time 0.348 - ------------------------------------------------------------------- - slack 0.109 - -Slack (MET) : 0.109ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/C - (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/D - (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Path Group: rxoutclkpcs_out[0] - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (rxoutclkpcs_out[0] rise@0.000ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.171ns (logic 0.041ns (23.977%) route 0.130ns (76.023%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 0.269ns - Source Clock Delay (SCD): 0.208ns - Clock Pessimism Removal (CPR): 0.046ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock rxoutclkpcs_out[0] rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.208 0.208 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X108Y150 FDCE (Prop_DFF2_SLICEL_C_Q) - 0.041 0.249 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/Q - net (fo=1, routed) 0.130 0.379 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[3] - SLICE_X108Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock rxoutclkpcs_out[0] rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.269 0.269 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C - clock pessimism -0.046 0.223 - SLICE_X108Y150 FDCE (Hold_EFF2_SLICEL_C_D) - 0.047 0.270 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4] - ------------------------------------------------------------------- - required time -0.270 - arrival time 0.379 - ------------------------------------------------------------------- - slack 0.109 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/C - (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4]/D - (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Path Group: rxoutclkpcs_out[0] - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (rxoutclkpcs_out[0] rise@0.000ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.188ns (logic 0.040ns (21.277%) route 0.148ns (78.723%)) - Logic Levels: 0 - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 0.227ns - Source Clock Delay (SCD): 0.177ns - Clock Pessimism Removal (CPR): 0.044ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock rxoutclkpcs_out[0] rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.177 0.177 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X108Y152 FDRE (Prop_CFF2_SLICEL_C_Q) - 0.040 0.217 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/Q - net (fo=1, routed) 0.148 0.365 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[3] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock rxoutclkpcs_out[0] rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.227 0.227 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4]/C - clock pessimism -0.044 0.183 - SLICE_X108Y152 FDRE (Hold_DFF2_SLICEL_C_D) - 0.047 0.230 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4] + net (fo=15, routed) 0.222 0.222 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7]/C + clock pessimism -0.039 0.183 + SLICE_X110Y160 FDRE (Hold_GFF2_SLICEL_C_D) + 0.047 0.230 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7] ------------------------------------------------------------------- required time -0.230 - arrival time 0.365 + arrival time 0.316 ------------------------------------------------------------------- - slack 0.135 + slack 0.086 -Slack (MET) : 0.139ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[0]/C +Slack (MET) : 0.096ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/C (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/D + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/D (rising edge-triggered cell FDCE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) Path Group: rxoutclkpcs_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclkpcs_out[0] rise@0.000ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.192ns (logic 0.040ns (20.833%) route 0.152ns (79.167%)) + Data Path Delay: 0.149ns (logic 0.040ns (26.846%) route 0.109ns (73.154%)) Logic Levels: 0 Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 0.265ns - Source Clock Delay (SCD): 0.208ns - Clock Pessimism Removal (CPR): 0.051ns + Destination Clock Delay (DCD): 0.176ns + Source Clock Delay (SCD): 0.141ns + Clock Pessimism Removal (CPR): 0.029ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclkpcs_out[0] rise edge) 0.000 0.000 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.208 0.208 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[0]/C + net (fo=15, routed) 0.141 0.141 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X108Y150 FDCE (Prop_AFF2_SLICEL_C_Q) - 0.040 0.248 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[0]/Q - net (fo=1, routed) 0.152 0.400 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[0] - SLICE_X108Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/D + SLICE_X110Y158 FDCE (Prop_BFF2_SLICEL_C_Q) + 0.040 0.181 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/Q + net (fo=1, routed) 0.109 0.290 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r[1] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/D ------------------------------------------------------------------- ------------------- (clock rxoutclkpcs_out[0] rise edge) 0.000 0.000 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.265 0.265 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y150 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/C - clock pessimism -0.051 0.214 - SLICE_X108Y150 FDCE (Hold_BFF2_SLICEL_C_D) - 0.047 0.261 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1] + net (fo=15, routed) 0.176 0.176 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y158 FDCE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/C + clock pessimism -0.029 0.147 + SLICE_X110Y158 FDCE (Hold_CFF2_SLICEL_C_D) + 0.047 0.194 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2] ------------------------------------------------------------------- - required time -0.261 - arrival time 0.400 + required time -0.194 + arrival time 0.290 ------------------------------------------------------------------- - slack 0.139 + slack 0.096 -Slack (MET) : 0.145ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[6]/C - (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7]/D - (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) - Path Group: rxoutclkpcs_out[0] - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (rxoutclkpcs_out[0] rise@0.000ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.198ns (logic 0.040ns (20.202%) route 0.158ns (79.798%)) - Logic Levels: 0 - Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 0.231ns - Source Clock Delay (SCD): 0.180ns - Clock Pessimism Removal (CPR): 0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock rxoutclkpcs_out[0] rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.180 0.180 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X108Y152 FDRE (Prop_FFF2_SLICEL_C_Q) - 0.040 0.220 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[6]/Q - net (fo=1, routed) 0.158 0.378 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[6] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock rxoutclkpcs_out[0] rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.231 0.231 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7]/C - clock pessimism -0.045 0.186 - SLICE_X108Y152 FDRE (Hold_GFF2_SLICEL_C_D) - 0.047 0.233 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7] - ------------------------------------------------------------------- - required time -0.233 - arrival time 0.378 - ------------------------------------------------------------------- - slack 0.145 - -Slack (MET) : 0.153ns (arrival time - required time) +Slack (MET) : 0.096ns (arrival time - required time) Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by rxoutclkpcs_out[0] {rise@0.000ns fall@1.552ns period=3.103ns}) Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/D @@ -3476,40 +3485,40 @@ Slack (MET) : 0.153ns (arrival time - required time) Path Group: rxoutclkpcs_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclkpcs_out[0] rise@0.000ns - rxoutclkpcs_out[0] rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.040ns (19.417%) route 0.166ns (80.583%)) + Data Path Delay: 0.149ns (logic 0.040ns (26.846%) route 0.109ns (73.154%)) Logic Levels: 0 Clock Path Skew: 0.006ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 0.227ns - Source Clock Delay (SCD): 0.177ns - Clock Pessimism Removal (CPR): 0.044ns + Destination Clock Delay (DCD): 0.218ns + Source Clock Delay (SCD): 0.174ns + Clock Pessimism Removal (CPR): 0.038ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclkpcs_out[0] rise edge) 0.000 0.000 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.177 0.177 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/C + net (fo=15, routed) 0.174 0.174 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X108Y152 FDRE (Prop_BFF2_SLICEL_C_Q) - 0.040 0.217 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/Q - net (fo=1, routed) 0.166 0.383 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[2] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/D + SLICE_X110Y160 FDRE (Prop_BFF2_SLICEL_C_Q) + 0.040 0.214 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/Q + net (fo=1, routed) 0.109 0.323 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt[2] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/D ------------------------------------------------------------------- ------------------- (clock rxoutclkpcs_out[0] rise edge) 0.000 0.000 r GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS - net (fo=15, routed) 0.227 0.227 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] - SLICE_X108Y152 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/C - clock pessimism -0.044 0.183 - SLICE_X108Y152 FDRE (Hold_CFF2_SLICEL_C_D) - 0.047 0.230 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3] + net (fo=15, routed) 0.218 0.218 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/rxoutclkpcs_out[0] + SLICE_X110Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/C + clock pessimism -0.038 0.180 + SLICE_X110Y160 FDRE (Hold_CFF2_SLICEL_C_D) + 0.047 0.227 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3] ------------------------------------------------------------------- - required time -0.230 - arrival time 0.383 + required time -0.227 + arrival time 0.323 ------------------------------------------------------------------- - slack 0.153 + slack 0.096 @@ -3523,36 +3532,36 @@ Period(ns): 3.103 Sources: { pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLKPCS } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a FDCE/C n/a 0.550 3.103 2.553 SLICE_X109Y150 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C -Min Period n/a FDCE/C n/a 0.550 3.103 2.553 SLICE_X108Y150 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[0]/C -Min Period n/a FDCE/C n/a 0.550 3.103 2.553 SLICE_X108Y150 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/C -Min Period n/a FDCE/C n/a 0.550 3.103 2.553 SLICE_X108Y150 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/C -Min Period n/a FDCE/C n/a 0.550 3.103 2.553 SLICE_X108Y150 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/C -Min Period n/a FDCE/C n/a 0.550 3.103 2.553 SLICE_X108Y150 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C -Min Period n/a FDRE/C n/a 0.550 3.103 2.553 SLICE_X109Y151 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.pwr_on_fsm_reg/C -Min Period n/a FDRE/C n/a 0.550 3.103 2.553 SLICE_X108Y151 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/C -Min Period n/a FDRE/C n/a 0.550 3.103 2.553 SLICE_X108Y152 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/C -Min Period n/a FDRE/C n/a 0.550 3.103 2.553 SLICE_X108Y152 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/C -Low Pulse Width Slow FDRE/C n/a 0.275 1.552 1.277 SLICE_X109Y151 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.pwr_on_fsm_reg/C -Low Pulse Width Fast FDRE/C n/a 0.275 1.552 1.277 SLICE_X109Y151 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.pwr_on_fsm_reg/C -Low Pulse Width Slow FDRE/C n/a 0.275 1.552 1.277 SLICE_X108Y151 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/C -Low Pulse Width Fast FDCE/C n/a 0.275 1.552 1.277 SLICE_X109Y150 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C -Low Pulse Width Fast FDCE/C n/a 0.275 1.552 1.277 SLICE_X108Y150 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[0]/C -Low Pulse Width Fast FDCE/C n/a 0.275 1.552 1.277 SLICE_X108Y150 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/C -Low Pulse Width Fast FDCE/C n/a 0.275 1.552 1.277 SLICE_X108Y150 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/C -Low Pulse Width Fast FDCE/C n/a 0.275 1.552 1.277 SLICE_X108Y150 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/C -Low Pulse Width Fast FDCE/C n/a 0.275 1.552 1.277 SLICE_X108Y150 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C -Low Pulse Width Fast FDRE/C n/a 0.275 1.552 1.277 SLICE_X108Y151 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/C -High Pulse Width Slow FDCE/C n/a 0.275 1.552 1.277 SLICE_X109Y150 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C -High Pulse Width Slow FDCE/C n/a 0.275 1.552 1.277 SLICE_X108Y150 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C -High Pulse Width Slow FDRE/C n/a 0.275 1.552 1.277 SLICE_X108Y152 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/C -High Pulse Width Slow FDRE/C n/a 0.275 1.552 1.277 SLICE_X108Y152 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/C -High Pulse Width Slow FDRE/C n/a 0.275 1.552 1.277 SLICE_X108Y152 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/C -High Pulse Width Slow FDRE/C n/a 0.275 1.552 1.277 SLICE_X108Y152 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[4]/C -High Pulse Width Slow FDRE/C n/a 0.275 1.552 1.277 SLICE_X108Y152 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[5]/C -High Pulse Width Slow FDRE/C n/a 0.275 1.552 1.277 SLICE_X108Y152 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[6]/C -High Pulse Width Slow FDRE/C n/a 0.275 1.552 1.277 SLICE_X108Y152 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[7]/C -High Pulse Width Fast FDCE/C n/a 0.275 1.552 1.277 SLICE_X109Y150 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C +Min Period n/a FDCE/C n/a 0.550 3.103 2.553 SLICE_X111Y159 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C +Min Period n/a FDCE/C n/a 0.550 3.103 2.553 SLICE_X110Y158 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[0]/C +Min Period n/a FDCE/C n/a 0.550 3.103 2.553 SLICE_X110Y158 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/C +Min Period n/a FDCE/C n/a 0.550 3.103 2.553 SLICE_X110Y158 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/C +Min Period n/a FDCE/C n/a 0.550 3.103 2.553 SLICE_X110Y158 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/C +Min Period n/a FDCE/C n/a 0.550 3.103 2.553 SLICE_X110Y158 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C +Min Period n/a FDRE/C n/a 0.550 3.103 2.553 SLICE_X111Y160 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.pwr_on_fsm_reg/C +Min Period n/a FDRE/C n/a 0.550 3.103 2.553 SLICE_X110Y159 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[0]/C +Min Period n/a FDRE/C n/a 0.550 3.103 2.553 SLICE_X110Y160 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/C +Min Period n/a FDRE/C n/a 0.550 3.103 2.553 SLICE_X110Y160 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/C +Low Pulse Width Fast FDCE/C n/a 0.275 1.552 1.277 SLICE_X111Y159 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C +Low Pulse Width Fast FDCE/C n/a 0.275 1.552 1.277 SLICE_X110Y158 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C +Low Pulse Width Slow FDRE/C n/a 0.275 1.552 1.277 SLICE_X111Y160 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.pwr_on_fsm_reg/C +Low Pulse Width Fast FDRE/C n/a 0.275 1.552 1.277 SLICE_X111Y160 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.pwr_on_fsm_reg/C +Low Pulse Width Slow FDCE/C n/a 0.275 1.552 1.277 SLICE_X111Y159 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.int_pwr_on_fsm_reg/C +Low Pulse Width Slow FDCE/C n/a 0.275 1.552 1.277 SLICE_X110Y158 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[0]/C +Low Pulse Width Slow FDCE/C n/a 0.275 1.552 1.277 SLICE_X110Y158 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/C +Low Pulse Width Slow FDCE/C n/a 0.275 1.552 1.277 SLICE_X110Y158 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/C +Low Pulse Width Slow FDCE/C n/a 0.275 1.552 1.277 SLICE_X110Y158 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/C +Low Pulse Width Slow FDCE/C n/a 0.275 1.552 1.277 SLICE_X110Y158 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[4]/C +High Pulse Width Slow FDCE/C n/a 0.275 1.552 1.277 SLICE_X110Y158 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[0]/C +High Pulse Width Slow FDCE/C n/a 0.275 1.552 1.277 SLICE_X110Y158 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[1]/C +High Pulse Width Slow FDCE/C n/a 0.275 1.552 1.277 SLICE_X110Y158 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[2]/C +High Pulse Width Slow FDCE/C n/a 0.275 1.552 1.277 SLICE_X110Y158 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.intclk_rrst_n_r_reg[3]/C +High Pulse Width Slow FDRE/C n/a 0.275 1.552 1.277 SLICE_X110Y160 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/C +High Pulse Width Fast FDRE/C n/a 0.275 1.552 1.277 SLICE_X110Y160 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[1]/C +High Pulse Width Slow FDRE/C n/a 0.275 1.552 1.277 SLICE_X110Y160 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/C +High Pulse Width Fast FDRE/C n/a 0.275 1.552 1.277 SLICE_X110Y160 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[2]/C +High Pulse Width Slow FDRE/C n/a 0.275 1.552 1.277 SLICE_X110Y160 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/C +High Pulse Width Fast FDRE/C n/a 0.275 1.552 1.277 SLICE_X110Y160 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_pwrgood_delay_inst[0].delay_powergood_inst/gen_powergood_delay.wait_cnt_reg[3]/C @@ -3585,34 +3594,34 @@ Max Skew Fast GTHE4_CHANNEL/TXUSRCLK GTHE4_CHANNEL/TXUSRCLK2 0.572 From Clock: xxv_ethernet_0_tx_clk_out_0 To Clock: xxv_ethernet_0_tx_clk_out_0 -Setup : 0 Failing Endpoints, Worst Slack 1.643ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 1.572ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.010ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.523ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 1.643ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[22]/C +Slack (MET) : 1.572ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_10/DINADIN[22] + Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_13/DINADIN[24] (rising edge-triggered cell RAMB36E2 clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 4.168ns (logic 0.078ns (1.871%) route 4.090ns (98.129%)) + Data Path Delay: 4.341ns (logic 0.079ns (1.820%) route 4.262ns (98.180%)) Logic Levels: 0 - Clock Path Skew: -0.277ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.737ns = ( 8.137 - 6.400 ) - Source Clock Delay (SCD): 2.102ns + Clock Path Skew: -0.176ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.821ns = ( 8.221 - 6.400 ) + Source Clock Delay (SCD): 2.085ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.859ns (routing 0.508ns, distribution 1.351ns) - Clock Net Delay (Destination): 1.524ns (routing 0.454ns, distribution 1.070ns) + Clock Net Delay (Source): 1.842ns (routing 0.508ns, distribution 1.334ns) + Clock Net Delay (Destination): 1.608ns (routing 0.454ns, distribution 1.154ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -3622,13 +3631,13 @@ Slack (MET) : 1.643ns (required time - arrival time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.859 2.102 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk - SLICE_X61Y41 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[22]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.842 2.085 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk + SLICE_X62Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/C ------------------------------------------------------------------- ------------------- - SLICE_X61Y41 FDRE (Prop_CFF_SLICEM_C_Q) - 0.078 2.180 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[22]/Q - net (fo=32, routed) 4.090 6.270 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[22] - RAMB36_X2Y24 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_10/DINADIN[22] + SLICE_X62Y48 FDRE (Prop_CFF_SLICEL_C_Q) + 0.079 2.164 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/Q + net (fo=32, routed) 4.262 6.426 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[24] + RAMB36_X3Y31 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_13/DINADIN[24] ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -3637,94 +3646,38 @@ Slack (MET) : 1.643ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.524 8.137 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X2Y24 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_10/CLKARDCLK - clock pessimism 0.088 8.225 - clock uncertainty -0.046 8.179 - RAMB36_X2Y24 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[22]) - -0.266 7.913 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_10 + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.608 8.221 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X3Y31 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_13/CLKARDCLK + clock pessimism 0.088 8.309 + clock uncertainty -0.046 8.263 + RAMB36_X3Y31 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[24]) + -0.265 7.998 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_13 ------------------------------------------------------------------- - required time 7.913 - arrival time -6.270 + required time 7.998 + arrival time -6.426 ------------------------------------------------------------------- - slack 1.643 + slack 1.572 -Slack (MET) : 1.694ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[26]/C +Slack (MET) : 1.590ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_31/DINADIN[26] + Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_10/DINADIN[24] (rising edge-triggered cell RAMB36E2 clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 4.256ns (logic 0.078ns (1.833%) route 4.178ns (98.167%)) + Data Path Delay: 4.332ns (logic 0.079ns (1.824%) route 4.253ns (98.176%)) Logic Levels: 0 - Clock Path Skew: -0.162ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.855ns = ( 8.255 - 6.400 ) - Source Clock Delay (SCD): 2.101ns - Clock Pessimism Removal (CPR): 0.084ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.858ns (routing 0.508ns, distribution 1.350ns) - Clock Net Delay (Destination): 1.642ns (routing 0.454ns, distribution 1.188ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.858 2.101 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk - SLICE_X61Y40 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[26]/C - ------------------------------------------------------------------- ------------------- - SLICE_X61Y40 FDRE (Prop_DFF_SLICEM_C_Q) - 0.078 2.179 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[26]/Q - net (fo=32, routed) 4.178 6.357 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[26] - RAMB36_X3Y41 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_31/DINADIN[26] - ------------------------------------------------------------------- ------------------- - - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.642 8.255 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X3Y41 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_31/CLKARDCLK - clock pessimism 0.084 8.339 - clock uncertainty -0.046 8.293 - RAMB36_X3Y41 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[26]) - -0.242 8.051 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_31 - ------------------------------------------------------------------- - required time 8.051 - arrival time -6.357 - ------------------------------------------------------------------- - slack 1.694 - -Slack (MET) : 1.751ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[22]/C - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_11/DINADIN[22] - (rising edge-triggered cell RAMB36E2 clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: xxv_ethernet_0_tx_clk_out_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 4.058ns (logic 0.078ns (1.922%) route 3.980ns (98.078%)) - Logic Levels: 0 - Clock Path Skew: -0.279ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.735ns = ( 8.135 - 6.400 ) - Source Clock Delay (SCD): 2.102ns + Clock Path Skew: -0.167ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.830ns = ( 8.230 - 6.400 ) + Source Clock Delay (SCD): 2.085ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.859ns (routing 0.508ns, distribution 1.351ns) - Clock Net Delay (Destination): 1.522ns (routing 0.454ns, distribution 1.068ns) + Clock Net Delay (Source): 1.842ns (routing 0.508ns, distribution 1.334ns) + Clock Net Delay (Destination): 1.617ns (routing 0.454ns, distribution 1.163ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -3734,13 +3687,13 @@ Slack (MET) : 1.751ns (required time - arrival time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.859 2.102 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk - SLICE_X61Y41 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[22]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.842 2.085 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk + SLICE_X62Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/C ------------------------------------------------------------------- ------------------- - SLICE_X61Y41 FDRE (Prop_CFF_SLICEM_C_Q) - 0.078 2.180 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[22]/Q - net (fo=32, routed) 3.980 6.160 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[22] - RAMB36_X2Y25 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_11/DINADIN[22] + SLICE_X62Y48 FDRE (Prop_CFF_SLICEL_C_Q) + 0.079 2.164 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/Q + net (fo=32, routed) 4.253 6.417 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[24] + RAMB36_X3Y28 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_10/DINADIN[24] ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -3749,38 +3702,38 @@ Slack (MET) : 1.751ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.522 8.135 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X2Y25 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_11/CLKARDCLK - clock pessimism 0.088 8.223 - clock uncertainty -0.046 8.177 - RAMB36_X2Y25 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[22]) - -0.266 7.911 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_11 + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.617 8.230 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X3Y28 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_10/CLKARDCLK + clock pessimism 0.088 8.318 + clock uncertainty -0.046 8.272 + RAMB36_X3Y28 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[24]) + -0.265 8.007 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_10 ------------------------------------------------------------------- - required time 7.911 - arrival time -6.160 + required time 8.007 + arrival time -6.417 ------------------------------------------------------------------- - slack 1.751 + slack 1.590 -Slack (MET) : 1.868ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[22]/C +Slack (MET) : 1.605ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[5]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_12/DINADIN[22] + Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_12/DINADIN[5] (rising edge-triggered cell RAMB36E2 clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 3.939ns (logic 0.078ns (1.980%) route 3.861ns (98.020%)) + Data Path Delay: 4.282ns (logic 0.078ns (1.822%) route 4.204ns (98.178%)) Logic Levels: 0 - Clock Path Skew: -0.281ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.733ns = ( 8.133 - 6.400 ) - Source Clock Delay (SCD): 2.102ns + Clock Path Skew: -0.195ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.806ns = ( 8.206 - 6.400 ) + Source Clock Delay (SCD): 2.089ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.859ns (routing 0.508ns, distribution 1.351ns) - Clock Net Delay (Destination): 1.520ns (routing 0.454ns, distribution 1.066ns) + Clock Net Delay (Source): 1.846ns (routing 0.508ns, distribution 1.338ns) + Clock Net Delay (Destination): 1.593ns (routing 0.454ns, distribution 1.139ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -3790,13 +3743,13 @@ Slack (MET) : 1.868ns (required time - arrival time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.859 2.102 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk - SLICE_X61Y41 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[22]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.846 2.089 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk + SLICE_X63Y50 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[5]/C ------------------------------------------------------------------- ------------------- - SLICE_X61Y41 FDRE (Prop_CFF_SLICEM_C_Q) - 0.078 2.180 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[22]/Q - net (fo=32, routed) 3.861 6.041 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[22] - RAMB36_X2Y26 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_12/DINADIN[22] + SLICE_X63Y50 FDRE (Prop_BFF_SLICEM_C_Q) + 0.078 2.167 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[5]/Q + net (fo=32, routed) 4.204 6.371 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[5] + RAMB36_X3Y30 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_12/DINADIN[5] ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -3805,38 +3758,38 @@ Slack (MET) : 1.868ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.520 8.133 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X2Y26 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_12/CLKARDCLK - clock pessimism 0.088 8.221 - clock uncertainty -0.046 8.175 - RAMB36_X2Y26 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[22]) - -0.266 7.909 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_12 + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.593 8.206 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X3Y30 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_12/CLKARDCLK + clock pessimism 0.088 8.294 + clock uncertainty -0.046 8.248 + RAMB36_X3Y30 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[5]) + -0.272 7.976 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_12 ------------------------------------------------------------------- - required time 7.909 - arrival time -6.041 + required time 7.976 + arrival time -6.371 ------------------------------------------------------------------- - slack 1.868 + slack 1.605 -Slack (MET) : 1.956ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[22]/C +Slack (MET) : 1.646ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[5]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_17/DINADIN[22] + Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_10/DINADIN[5] (rising edge-triggered cell RAMB36E2 clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 3.836ns (logic 0.078ns (2.033%) route 3.758ns (97.967%)) + Data Path Delay: 4.265ns (logic 0.078ns (1.829%) route 4.187ns (98.171%)) Logic Levels: 0 - Clock Path Skew: -0.296ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.718ns = ( 8.118 - 6.400 ) - Source Clock Delay (SCD): 2.102ns + Clock Path Skew: -0.171ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.830ns = ( 8.230 - 6.400 ) + Source Clock Delay (SCD): 2.089ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.859ns (routing 0.508ns, distribution 1.351ns) - Clock Net Delay (Destination): 1.505ns (routing 0.454ns, distribution 1.051ns) + Clock Net Delay (Source): 1.846ns (routing 0.508ns, distribution 1.338ns) + Clock Net Delay (Destination): 1.617ns (routing 0.454ns, distribution 1.163ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -3846,13 +3799,13 @@ Slack (MET) : 1.956ns (required time - arrival time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.859 2.102 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk - SLICE_X61Y41 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[22]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.846 2.089 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk + SLICE_X63Y50 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[5]/C ------------------------------------------------------------------- ------------------- - SLICE_X61Y41 FDRE (Prop_CFF_SLICEM_C_Q) - 0.078 2.180 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[22]/Q - net (fo=32, routed) 3.758 5.938 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[22] - RAMB36_X2Y31 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_17/DINADIN[22] + SLICE_X63Y50 FDRE (Prop_BFF_SLICEM_C_Q) + 0.078 2.167 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[5]/Q + net (fo=32, routed) 4.187 6.354 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[5] + RAMB36_X3Y28 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_10/DINADIN[5] ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -3861,118 +3814,38 @@ Slack (MET) : 1.956ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.505 8.118 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X2Y31 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_17/CLKARDCLK - clock pessimism 0.088 8.206 - clock uncertainty -0.046 8.160 - RAMB36_X2Y31 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[22]) - -0.266 7.894 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_17 + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.617 8.230 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X3Y28 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_10/CLKARDCLK + clock pessimism 0.088 8.318 + clock uncertainty -0.046 8.272 + RAMB36_X3Y28 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[5]) + -0.272 8.000 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_10 ------------------------------------------------------------------- - required time 7.894 - arrival time -5.938 + required time 8.000 + arrival time -6.354 ------------------------------------------------------------------- - slack 1.956 + slack 1.646 -Slack (MET) : 1.999ns (required time - arrival time) - Source: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26/CLKBWRCLK - (rising edge-triggered cell RAMB36E2 clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][22]/D +Slack (MET) : 1.683ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: xxv_ethernet_0_tx_clk_out_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 4.054ns (logic 2.495ns (61.544%) route 1.559ns (38.456%)) - Logic Levels: 8 (LUT6=1 RAMB36E2=7) - Clock Path Skew: -0.326ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.772ns = ( 8.172 - 6.400 ) - Source Clock Delay (SCD): 2.182ns - Clock Pessimism Removal (CPR): 0.084ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.939ns (routing 0.508ns, distribution 1.431ns) - Clock Net Delay (Destination): 1.559ns (routing 0.454ns, distribution 1.105ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.939 2.182 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X3Y36 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26/CLKBWRCLK - ------------------------------------------------------------------- ------------------- - RAMB36_X3Y36 RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[22]) - 1.030 3.212 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26/CASDOUTB[22] - net (fo=1, routed) 0.023 3.235 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26_n_45 - RAMB36_X3Y37 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[22]_CASDOUTB[22]) - 0.210 3.445 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_27/CASDOUTB[22] - net (fo=1, routed) 0.023 3.468 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_27_n_45 - RAMB36_X3Y38 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[22]_CASDOUTB[22]) - 0.210 3.678 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_28/CASDOUTB[22] - net (fo=1, routed) 0.023 3.701 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_28_n_45 - RAMB36_X3Y39 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[22]_CASDOUTB[22]) - 0.210 3.911 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_29/CASDOUTB[22] - net (fo=1, routed) 0.023 3.934 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_29_n_45 - RAMB36_X3Y40 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[22]_CASDOUTB[22]) - 0.210 4.144 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_30/CASDOUTB[22] - net (fo=1, routed) 0.023 4.167 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_30_n_45 - RAMB36_X3Y41 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[22]_CASDOUTB[22]) - 0.210 4.377 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_31/CASDOUTB[22] - net (fo=1, routed) 0.023 4.400 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_31_n_45 - RAMB36_X3Y42 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[22]_CASDOUTB[22]) - 0.210 4.610 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_32/CASDOUTB[22] - net (fo=1, routed) 0.023 4.633 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_32_n_45 - RAMB36_X3Y43 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[22]_DOUTBDOUT[22]) - 0.117 4.750 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_33/DOUTBDOUT[22] - net (fo=1, routed) 1.348 6.098 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_33_n_109 - SLICE_X97Y155 LUT6 (Prop_C6LUT_SLICEL_I0_O) - 0.088 6.186 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe[0][22]_i_1/O - net (fo=1, routed) 0.050 6.236 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe[0][22]_i_1_n_0 - SLICE_X97Y155 FDRE r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][22]/D - ------------------------------------------------------------------- ------------------- - - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.559 8.172 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - SLICE_X97Y155 FDRE r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][22]/C - clock pessimism 0.084 8.256 - clock uncertainty -0.046 8.210 - SLICE_X97Y155 FDRE (Setup_CFF_SLICEL_C_D) - 0.025 8.235 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][22] - ------------------------------------------------------------------- - required time 8.235 - arrival time -6.236 - ------------------------------------------------------------------- - slack 1.999 - -Slack (MET) : 2.005ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[22]/C - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_13/DINADIN[22] + Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_11/DINADIN[24] (rising edge-triggered cell RAMB36E2 clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 3.798ns (logic 0.078ns (2.054%) route 3.720ns (97.946%)) + Data Path Delay: 4.223ns (logic 0.079ns (1.871%) route 4.144ns (98.129%)) Logic Levels: 0 - Clock Path Skew: -0.285ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.729ns = ( 8.129 - 6.400 ) - Source Clock Delay (SCD): 2.102ns + Clock Path Skew: -0.183ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.814ns = ( 8.214 - 6.400 ) + Source Clock Delay (SCD): 2.085ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.859ns (routing 0.508ns, distribution 1.351ns) - Clock Net Delay (Destination): 1.516ns (routing 0.454ns, distribution 1.062ns) + Clock Net Delay (Source): 1.842ns (routing 0.508ns, distribution 1.334ns) + Clock Net Delay (Destination): 1.601ns (routing 0.454ns, distribution 1.147ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -3982,13 +3855,13 @@ Slack (MET) : 2.005ns (required time - arrival time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.859 2.102 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk - SLICE_X61Y41 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[22]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.842 2.085 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk + SLICE_X62Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/C ------------------------------------------------------------------- ------------------- - SLICE_X61Y41 FDRE (Prop_CFF_SLICEM_C_Q) - 0.078 2.180 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[22]/Q - net (fo=32, routed) 3.720 5.900 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[22] - RAMB36_X2Y27 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_13/DINADIN[22] + SLICE_X62Y48 FDRE (Prop_CFF_SLICEL_C_Q) + 0.079 2.164 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/Q + net (fo=32, routed) 4.144 6.308 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[24] + RAMB36_X3Y29 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_11/DINADIN[24] ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -3997,38 +3870,38 @@ Slack (MET) : 2.005ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.516 8.129 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X2Y27 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_13/CLKARDCLK - clock pessimism 0.088 8.217 - clock uncertainty -0.046 8.171 - RAMB36_X2Y27 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[22]) - -0.266 7.905 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_13 + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.601 8.214 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X3Y29 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_11/CLKARDCLK + clock pessimism 0.088 8.302 + clock uncertainty -0.046 8.256 + RAMB36_X3Y29 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[24]) + -0.265 7.991 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_11 ------------------------------------------------------------------- - required time 7.905 - arrival time -5.900 + required time 7.991 + arrival time -6.308 ------------------------------------------------------------------- - slack 2.005 + slack 1.683 -Slack (MET) : 2.031ns (required time - arrival time) - Source: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26/CLKBWRCLK - (rising edge-triggered cell RAMB36E2 clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][32]/D +Slack (MET) : 1.700ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_12/DINADIN[24] + (rising edge-triggered cell RAMB36E2 clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 4.027ns (logic 2.520ns (62.578%) route 1.507ns (37.422%)) - Logic Levels: 8 (LUT6=1 RAMB36E2=7) - Clock Path Skew: -0.321ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.777ns = ( 8.177 - 6.400 ) - Source Clock Delay (SCD): 2.182ns - Clock Pessimism Removal (CPR): 0.084ns + Data Path Delay: 4.198ns (logic 0.079ns (1.882%) route 4.119ns (98.118%)) + Logic Levels: 0 + Clock Path Skew: -0.191ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.806ns = ( 8.206 - 6.400 ) + Source Clock Delay (SCD): 2.085ns + Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.939ns (routing 0.508ns, distribution 1.431ns) - Clock Net Delay (Destination): 1.564ns (routing 0.454ns, distribution 1.110ns) + Clock Net Delay (Source): 1.842ns (routing 0.508ns, distribution 1.334ns) + Clock Net Delay (Destination): 1.593ns (routing 0.454ns, distribution 1.139ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -4038,37 +3911,13 @@ Slack (MET) : 2.031ns (required time - arrival time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.939 2.182 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X3Y36 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26/CLKBWRCLK + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.842 2.085 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk + SLICE_X62Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/C ------------------------------------------------------------------- ------------------- - RAMB36_X3Y36 RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTPB[0]) - 1.045 3.227 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26/CASDOUTPB[0] - net (fo=1, routed) 0.031 3.258 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26_n_139 - RAMB36_X3Y37 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINPB[0]_CASDOUTPB[0]) - 0.210 3.468 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_27/CASDOUTPB[0] - net (fo=1, routed) 0.031 3.499 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_27_n_139 - RAMB36_X3Y38 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINPB[0]_CASDOUTPB[0]) - 0.210 3.709 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_28/CASDOUTPB[0] - net (fo=1, routed) 0.031 3.740 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_28_n_139 - RAMB36_X3Y39 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINPB[0]_CASDOUTPB[0]) - 0.210 3.950 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_29/CASDOUTPB[0] - net (fo=1, routed) 0.031 3.981 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_29_n_139 - RAMB36_X3Y40 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINPB[0]_CASDOUTPB[0]) - 0.210 4.191 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_30/CASDOUTPB[0] - net (fo=1, routed) 0.031 4.222 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_30_n_139 - RAMB36_X3Y41 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINPB[0]_CASDOUTPB[0]) - 0.210 4.432 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_31/CASDOUTPB[0] - net (fo=1, routed) 0.031 4.463 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_31_n_139 - RAMB36_X3Y42 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINPB[0]_CASDOUTPB[0]) - 0.210 4.673 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_32/CASDOUTPB[0] - net (fo=1, routed) 0.031 4.704 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_32_n_139 - RAMB36_X3Y43 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINPB[0]_DOUTPBDOUTP[0]) - 0.117 4.821 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_33/DOUTPBDOUTP[0] - net (fo=1, routed) 1.242 6.063 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_33_n_147 - SLICE_X97Y156 LUT6 (Prop_A6LUT_SLICEL_I0_O) - 0.098 6.161 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe[0][32]_i_1/O - net (fo=1, routed) 0.048 6.209 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe[0][32]_i_1_n_0 - SLICE_X97Y156 FDRE r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][32]/D + SLICE_X62Y48 FDRE (Prop_CFF_SLICEL_C_Q) + 0.079 2.164 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/Q + net (fo=32, routed) 4.119 6.283 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[24] + RAMB36_X3Y30 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_12/DINADIN[24] ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -4077,38 +3926,38 @@ Slack (MET) : 2.031ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.564 8.177 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - SLICE_X97Y156 FDRE r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][32]/C - clock pessimism 0.084 8.261 - clock uncertainty -0.046 8.215 - SLICE_X97Y156 FDRE (Setup_AFF_SLICEL_C_D) - 0.025 8.240 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][32] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.593 8.206 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X3Y30 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_12/CLKARDCLK + clock pessimism 0.088 8.294 + clock uncertainty -0.046 8.248 + RAMB36_X3Y30 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[24]) + -0.265 7.983 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_12 ------------------------------------------------------------------- - required time 8.240 - arrival time -6.209 + required time 7.983 + arrival time -6.283 ------------------------------------------------------------------- - slack 2.031 + slack 1.700 -Slack (MET) : 2.046ns (required time - arrival time) - Source: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26/CLKBWRCLK - (rising edge-triggered cell RAMB36E2 clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][20]/D +Slack (MET) : 1.709ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_15/DINADIN[24] + (rising edge-triggered cell RAMB36E2 clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 4.007ns (logic 2.502ns (62.441%) route 1.505ns (37.559%)) - Logic Levels: 8 (LUT6=1 RAMB36E2=7) - Clock Path Skew: -0.326ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.772ns = ( 8.172 - 6.400 ) - Source Clock Delay (SCD): 2.182ns - Clock Pessimism Removal (CPR): 0.084ns + Data Path Delay: 4.207ns (logic 0.079ns (1.878%) route 4.128ns (98.122%)) + Logic Levels: 0 + Clock Path Skew: -0.173ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.824ns = ( 8.224 - 6.400 ) + Source Clock Delay (SCD): 2.085ns + Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.939ns (routing 0.508ns, distribution 1.431ns) - Clock Net Delay (Destination): 1.559ns (routing 0.454ns, distribution 1.105ns) + Clock Net Delay (Source): 1.842ns (routing 0.508ns, distribution 1.334ns) + Clock Net Delay (Destination): 1.611ns (routing 0.454ns, distribution 1.157ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -4118,37 +3967,13 @@ Slack (MET) : 2.046ns (required time - arrival time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.939 2.182 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X3Y36 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26/CLKBWRCLK + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.842 2.085 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk + SLICE_X62Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/C ------------------------------------------------------------------- ------------------- - RAMB36_X3Y36 RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[20]) - 1.036 3.218 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26/CASDOUTB[20] - net (fo=1, routed) 0.025 3.243 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26_n_47 - RAMB36_X3Y37 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[20]_CASDOUTB[20]) - 0.210 3.453 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_27/CASDOUTB[20] - net (fo=1, routed) 0.025 3.478 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_27_n_47 - RAMB36_X3Y38 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[20]_CASDOUTB[20]) - 0.210 3.688 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_28/CASDOUTB[20] - net (fo=1, routed) 0.025 3.713 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_28_n_47 - RAMB36_X3Y39 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[20]_CASDOUTB[20]) - 0.210 3.923 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_29/CASDOUTB[20] - net (fo=1, routed) 0.025 3.948 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_29_n_47 - RAMB36_X3Y40 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[20]_CASDOUTB[20]) - 0.210 4.158 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_30/CASDOUTB[20] - net (fo=1, routed) 0.025 4.183 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_30_n_47 - RAMB36_X3Y41 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[20]_CASDOUTB[20]) - 0.210 4.393 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_31/CASDOUTB[20] - net (fo=1, routed) 0.025 4.418 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_31_n_47 - RAMB36_X3Y42 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[20]_CASDOUTB[20]) - 0.210 4.628 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_32/CASDOUTB[20] - net (fo=1, routed) 0.025 4.653 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_32_n_47 - RAMB36_X3Y43 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[20]_DOUTBDOUT[20]) - 0.117 4.770 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_33/DOUTBDOUT[20] - net (fo=1, routed) 1.281 6.051 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_33_n_111 - SLICE_X97Y155 LUT6 (Prop_D6LUT_SLICEL_I0_O) - 0.089 6.140 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe[0][20]_i_1/O - net (fo=1, routed) 0.049 6.189 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe[0][20]_i_1_n_0 - SLICE_X97Y155 FDRE r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][20]/D + SLICE_X62Y48 FDRE (Prop_CFF_SLICEL_C_Q) + 0.079 2.164 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/Q + net (fo=32, routed) 4.128 6.292 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[24] + RAMB36_X3Y33 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_15/DINADIN[24] ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -4157,38 +3982,38 @@ Slack (MET) : 2.046ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.559 8.172 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - SLICE_X97Y155 FDRE r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][20]/C - clock pessimism 0.084 8.256 - clock uncertainty -0.046 8.210 - SLICE_X97Y155 FDRE (Setup_DFF_SLICEL_C_D) - 0.025 8.235 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][20] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.611 8.224 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X3Y33 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_15/CLKARDCLK + clock pessimism 0.088 8.312 + clock uncertainty -0.046 8.266 + RAMB36_X3Y33 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[24]) + -0.265 8.001 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_15 ------------------------------------------------------------------- - required time 8.235 - arrival time -6.189 + required time 8.001 + arrival time -6.292 ------------------------------------------------------------------- - slack 2.046 + slack 1.709 -Slack (MET) : 2.054ns (required time - arrival time) - Source: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26/CLKBWRCLK - (rising edge-triggered cell RAMB36E2 clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][16]/D +Slack (MET) : 1.821ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[5]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_11/DINADIN[5] + (rising edge-triggered cell RAMB36E2 clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 3.993ns (logic 2.496ns (62.509%) route 1.497ns (37.491%)) - Logic Levels: 8 (LUT6=1 RAMB36E2=7) - Clock Path Skew: -0.332ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.766ns = ( 8.166 - 6.400 ) - Source Clock Delay (SCD): 2.182ns - Clock Pessimism Removal (CPR): 0.084ns + Data Path Delay: 4.074ns (logic 0.078ns (1.915%) route 3.996ns (98.085%)) + Logic Levels: 0 + Clock Path Skew: -0.187ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.814ns = ( 8.214 - 6.400 ) + Source Clock Delay (SCD): 2.089ns + Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.939ns (routing 0.508ns, distribution 1.431ns) - Clock Net Delay (Destination): 1.553ns (routing 0.454ns, distribution 1.099ns) + Clock Net Delay (Source): 1.846ns (routing 0.508ns, distribution 1.338ns) + Clock Net Delay (Destination): 1.601ns (routing 0.454ns, distribution 1.147ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -4198,37 +4023,13 @@ Slack (MET) : 2.054ns (required time - arrival time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.939 2.182 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - RAMB36_X3Y36 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26/CLKBWRCLK + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.846 2.089 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk + SLICE_X63Y50 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[5]/C ------------------------------------------------------------------- ------------------- - RAMB36_X3Y36 RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[16]) - 1.020 3.202 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26/CASDOUTB[16] - net (fo=1, routed) 0.026 3.228 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_26_n_51 - RAMB36_X3Y37 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[16]_CASDOUTB[16]) - 0.210 3.438 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_27/CASDOUTB[16] - net (fo=1, routed) 0.026 3.464 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_27_n_51 - RAMB36_X3Y38 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[16]_CASDOUTB[16]) - 0.210 3.674 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_28/CASDOUTB[16] - net (fo=1, routed) 0.026 3.700 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_28_n_51 - RAMB36_X3Y39 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[16]_CASDOUTB[16]) - 0.210 3.910 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_29/CASDOUTB[16] - net (fo=1, routed) 0.026 3.936 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_29_n_51 - RAMB36_X3Y40 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[16]_CASDOUTB[16]) - 0.210 4.146 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_30/CASDOUTB[16] - net (fo=1, routed) 0.026 4.172 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_30_n_51 - RAMB36_X3Y41 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[16]_CASDOUTB[16]) - 0.210 4.382 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_31/CASDOUTB[16] - net (fo=1, routed) 0.026 4.408 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_31_n_51 - RAMB36_X3Y42 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[16]_CASDOUTB[16]) - 0.210 4.618 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_32/CASDOUTB[16] - net (fo=1, routed) 0.026 4.644 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_32_n_51 - RAMB36_X3Y43 RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[16]_DOUTBDOUT[16]) - 0.117 4.761 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_33/DOUTBDOUT[16] - net (fo=1, routed) 1.266 6.027 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_33_n_115 - SLICE_X97Y154 LUT6 (Prop_D6LUT_SLICEL_I0_O) - 0.099 6.126 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe[0][16]_i_1/O - net (fo=1, routed) 0.049 6.175 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe[0][16]_i_1_n_0 - SLICE_X97Y154 FDRE r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][16]/D + SLICE_X63Y50 FDRE (Prop_BFF_SLICEM_C_Q) + 0.078 2.167 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[5]/Q + net (fo=32, routed) 3.996 6.163 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[5] + RAMB36_X3Y29 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_11/DINADIN[5] ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -4237,17 +4038,129 @@ Slack (MET) : 2.054ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.553 8.166 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka - SLICE_X97Y154 FDRE r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][16]/C - clock pessimism 0.084 8.250 - clock uncertainty -0.046 8.204 - SLICE_X97Y154 FDRE (Setup_DFF_SLICEL_C_D) - 0.025 8.229 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][16] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.601 8.214 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X3Y29 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_11/CLKARDCLK + clock pessimism 0.088 8.302 + clock uncertainty -0.046 8.256 + RAMB36_X3Y29 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[5]) + -0.272 7.984 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_11 ------------------------------------------------------------------- - required time 8.229 - arrival time -6.175 + required time 7.984 + arrival time -6.163 ------------------------------------------------------------------- - slack 2.054 + slack 1.821 + +Slack (MET) : 1.832ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[5]/C + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_14/DINADIN[5] + (rising edge-triggered cell RAMB36E2 clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: xxv_ethernet_0_tx_clk_out_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) + Data Path Delay: 4.076ns (logic 0.078ns (1.914%) route 3.998ns (98.086%)) + Logic Levels: 0 + Clock Path Skew: -0.174ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.827ns = ( 8.227 - 6.400 ) + Source Clock Delay (SCD): 2.089ns + Clock Pessimism Removal (CPR): 0.088ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.846ns (routing 0.508ns, distribution 1.338ns) + Clock Net Delay (Destination): 1.614ns (routing 0.454ns, distribution 1.160ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.846 2.089 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk + SLICE_X63Y50 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X63Y50 FDRE (Prop_BFF_SLICEM_C_Q) + 0.078 2.167 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[5]/Q + net (fo=32, routed) 3.998 6.165 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[5] + RAMB36_X3Y32 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_14/DINADIN[5] + ------------------------------------------------------------------- ------------------- + + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.614 8.227 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X3Y32 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_14/CLKARDCLK + clock pessimism 0.088 8.315 + clock uncertainty -0.046 8.269 + RAMB36_X3Y32 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[5]) + -0.272 7.997 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_14 + ------------------------------------------------------------------- + required time 7.997 + arrival time -6.165 + ------------------------------------------------------------------- + slack 1.832 + +Slack (MET) : 1.851ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/C + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_14/DINADIN[24] + (rising edge-triggered cell RAMB36E2 clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: xxv_ethernet_0_tx_clk_out_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) + Data Path Delay: 4.068ns (logic 0.079ns (1.942%) route 3.989ns (98.058%)) + Logic Levels: 0 + Clock Path Skew: -0.170ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.827ns = ( 8.227 - 6.400 ) + Source Clock Delay (SCD): 2.085ns + Clock Pessimism Removal (CPR): 0.088ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.842ns (routing 0.508ns, distribution 1.334ns) + Clock Net Delay (Destination): 1.614ns (routing 0.454ns, distribution 1.160ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.842 2.085 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/m_axi_mm2s_aclk + SLICE_X62Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y48 FDRE (Prop_CFF_SLICEL_C_Q) + 0.079 2.164 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_reg[24]/Q + net (fo=32, routed) 3.989 6.153 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[24] + RAMB36_X3Y32 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_14/DINADIN[24] + ------------------------------------------------------------------- ------------------- + + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.614 8.227 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka + RAMB36_X3Y32 RAMB36E2 r pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_14/CLKARDCLK + clock pessimism 0.088 8.315 + clock uncertainty -0.046 8.269 + RAMB36_X3Y32 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[24]) + -0.265 8.004 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_14 + ------------------------------------------------------------------- + required time 8.004 + arrival time -6.153 + ------------------------------------------------------------------- + slack 1.851 @@ -4255,340 +4168,22 @@ Slack (MET) : 2.054ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.011ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[123]/C - (rising edge-triggered cell FDSE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat5_p5_r_reg[59]/D - (rising edge-triggered cell FDSE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: xxv_ethernet_0_tx_clk_out_0 - Path Type: Hold (Min at Slow Process Corner) - Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.171ns (logic 0.080ns (46.784%) route 0.091ns (53.216%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.100ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.062ns - Source Clock Delay (SCD): 1.803ns - Clock Pessimism Removal (CPR): 0.159ns - Clock Net Delay (Source): 1.590ns (routing 0.454ns, distribution 1.136ns) - Clock Net Delay (Destination): 1.819ns (routing 0.508ns, distribution 1.311ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.590 1.803 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/tx_clk - SLICE_X93Y112 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[123]/C - ------------------------------------------------------------------- ------------------- - SLICE_X93Y112 FDSE (Prop_HFF_SLICEM_C_Q) - 0.058 1.861 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[123]/Q - net (fo=6, routed) 0.069 1.930 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/pak_dat1_p4_r[59] - SLICE_X92Y112 LUT6 (Prop_G6LUT_SLICEL_I3_O) - 0.022 1.952 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat5_p5_r[59]_i_1/O - net (fo=1, routed) 0.022 1.974 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat5_p5_r[59]_i_1_n_0 - SLICE_X92Y112 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat5_p5_r_reg[59]/D - ------------------------------------------------------------------- ------------------- - - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.819 2.062 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/tx_clk - SLICE_X92Y112 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat5_p5_r_reg[59]/C - clock pessimism -0.159 1.903 - SLICE_X92Y112 FDSE (Hold_GFF_SLICEL_C_D) - 0.060 1.963 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat5_p5_r_reg[59] - ------------------------------------------------------------------- - required time -1.963 - arrival time 1.974 - ------------------------------------------------------------------- - slack 0.011 - -Slack (MET) : 0.012ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[91]/C +Slack (MET) : 0.010ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/datain0_r_reg[5]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat1_p5_r_reg[27]/D + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/datain0_p0_r_reg[5]/D (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.137ns (logic 0.080ns (58.394%) route 0.057ns (41.606%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.065ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.062ns - Source Clock Delay (SCD): 1.790ns - Clock Pessimism Removal (CPR): 0.207ns - Clock Net Delay (Source): 1.577ns (routing 0.454ns, distribution 1.123ns) - Clock Net Delay (Destination): 1.819ns (routing 0.508ns, distribution 1.311ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.577 1.790 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/tx_clk - SLICE_X91Y113 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[91]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y113 FDRE (Prop_CFF_SLICEL_C_Q) - 0.058 1.848 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[91]/Q - net (fo=5, routed) 0.035 1.883 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/pak_dat1_p4_r[27] - SLICE_X91Y112 LUT6 (Prop_G6LUT_SLICEL_I1_O) - 0.022 1.905 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat1_p5_r[27]_i_1/O - net (fo=1, routed) 0.022 1.927 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat1_p5_r[27]_i_1_n_0 - SLICE_X91Y112 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat1_p5_r_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.819 2.062 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/tx_clk - SLICE_X91Y112 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat1_p5_r_reg[27]/C - clock pessimism -0.207 1.855 - SLICE_X91Y112 FDRE (Hold_GFF_SLICEL_C_D) - 0.060 1.915 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat1_p5_r_reg[27] - ------------------------------------------------------------------- - required time -1.915 - arrival time 1.927 - ------------------------------------------------------------------- - slack 0.012 - -Slack (MET) : 0.014ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/counter_msb_reg[18]/C - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/statshold_reg[42]/D - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: xxv_ethernet_0_tx_clk_out_0 - Path Type: Hold (Min at Slow Process Corner) - Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.135ns (logic 0.059ns (43.704%) route 0.076ns (56.296%)) + Data Path Delay: 0.124ns (logic 0.058ns (46.774%) route 0.066ns (53.226%)) Logic Levels: 0 - Clock Path Skew: 0.059ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.972ns - Source Clock Delay (SCD): 1.717ns - Clock Pessimism Removal (CPR): 0.196ns - Clock Net Delay (Source): 1.504ns (routing 0.454ns, distribution 1.050ns) - Clock Net Delay (Destination): 1.729ns (routing 0.508ns, distribution 1.221ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.504 1.717 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/CLK - SLICE_X76Y121 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/counter_msb_reg[18]/C - ------------------------------------------------------------------- ------------------- - SLICE_X76Y121 FDRE (Prop_CFF2_SLICEL_C_Q) - 0.059 1.776 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/counter_msb_reg[18]/Q - net (fo=2, routed) 0.076 1.852 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/p_0_in1_in[42] - SLICE_X76Y122 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/statshold_reg[42]/D - ------------------------------------------------------------------- ------------------- - - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.729 1.972 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/CLK - SLICE_X76Y122 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/statshold_reg[42]/C - clock pessimism -0.196 1.776 - SLICE_X76Y122 FDRE (Hold_FFF2_SLICEL_C_D) - 0.062 1.838 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/statshold_reg[42] - ------------------------------------------------------------------- - required time -1.838 - arrival time 1.852 - ------------------------------------------------------------------- - slack 0.014 - -Slack (MET) : 0.014ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[123]/C - (rising edge-triggered cell FDSE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat1_p5_r_reg[59]/D - (rising edge-triggered cell FDSE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: xxv_ethernet_0_tx_clk_out_0 - Path Type: Hold (Min at Slow Process Corner) - Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.174ns (logic 0.081ns (46.552%) route 0.093ns (53.448%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.100ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.062ns - Source Clock Delay (SCD): 1.803ns - Clock Pessimism Removal (CPR): 0.159ns - Clock Net Delay (Source): 1.590ns (routing 0.454ns, distribution 1.136ns) - Clock Net Delay (Destination): 1.819ns (routing 0.508ns, distribution 1.311ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.590 1.803 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/tx_clk - SLICE_X93Y112 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[123]/C - ------------------------------------------------------------------- ------------------- - SLICE_X93Y112 FDSE (Prop_HFF_SLICEM_C_Q) - 0.058 1.861 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[123]/Q - net (fo=6, routed) 0.069 1.930 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/pak_dat1_p4_r[59] - SLICE_X92Y112 LUT6 (Prop_H6LUT_SLICEL_I1_O) - 0.023 1.953 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat1_p5_r[59]_i_1/O - net (fo=1, routed) 0.024 1.977 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat1_p5_r[59]_i_1_n_0 - SLICE_X92Y112 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat1_p5_r_reg[59]/D - ------------------------------------------------------------------- ------------------- - - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.819 2.062 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/tx_clk - SLICE_X92Y112 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat1_p5_r_reg[59]/C - clock pessimism -0.159 1.903 - SLICE_X92Y112 FDSE (Hold_HFF_SLICEL_C_D) - 0.060 1.963 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat1_p5_r_reg[59] - ------------------------------------------------------------------- - required time -1.963 - arrival time 1.977 - ------------------------------------------------------------------- - slack 0.014 - -Slack (MET) : 0.015ns (arrival time - required time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_adjusted_addr_incr_ireg2_reg[1]/C - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_xfer_len_eq_0_ireg3_reg/D - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: xxv_ethernet_0_tx_clk_out_0 - Path Type: Hold (Min at Slow Process Corner) - Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.162ns (logic 0.091ns (56.173%) route 0.071ns (43.827%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.085ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.114ns - Source Clock Delay (SCD): 1.867ns - Clock Pessimism Removal (CPR): 0.162ns - Clock Net Delay (Source): 1.654ns (routing 0.454ns, distribution 1.200ns) - Clock Net Delay (Destination): 1.871ns (routing 0.508ns, distribution 1.363ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.654 1.867 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/m_axi_mm2s_aclk - SLICE_X58Y49 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_adjusted_addr_incr_ireg2_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X58Y49 FDRE (Prop_BFF_SLICEL_C_Q) - 0.059 1.926 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_adjusted_addr_incr_ireg2_reg[1]/Q - net (fo=5, routed) 0.061 1.987 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_adjusted_addr_incr_ireg2_reg_n_0_[1] - SLICE_X59Y49 LUT5 (Prop_B5LUT_SLICEL_I3_O) - 0.032 2.019 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_xfer_len_eq_0_ireg3_i_1/O - net (fo=1, routed) 0.010 2.029 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_xfer_len_eq_0_im2 - SLICE_X59Y49 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_xfer_len_eq_0_ireg3_reg/D - ------------------------------------------------------------------- ------------------- - - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.871 2.114 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/m_axi_mm2s_aclk - SLICE_X59Y49 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_xfer_len_eq_0_ireg3_reg/C - clock pessimism -0.162 1.952 - SLICE_X59Y49 FDRE (Hold_BFF2_SLICEL_C_D) - 0.062 2.014 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_xfer_len_eq_0_ireg3_reg - ------------------------------------------------------------------- - required time -2.014 - arrival time 2.029 - ------------------------------------------------------------------- - slack 0.015 - -Slack (MET) : 0.016ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/statshold_reg[35]/C - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/statsout_reg[35]/D - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: xxv_ethernet_0_tx_clk_out_0 - Path Type: Hold (Min at Slow Process Corner) - Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.126ns (logic 0.058ns (46.032%) route 0.068ns (53.968%)) - Logic Levels: 0 - Clock Path Skew: 0.048ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.969ns - Source Clock Delay (SCD): 1.725ns - Clock Pessimism Removal (CPR): 0.196ns - Clock Net Delay (Source): 1.512ns (routing 0.454ns, distribution 1.058ns) - Clock Net Delay (Destination): 1.726ns (routing 0.508ns, distribution 1.218ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.512 1.725 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/CLK - SLICE_X75Y128 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/statshold_reg[35]/C - ------------------------------------------------------------------- ------------------- - SLICE_X75Y128 FDRE (Prop_FFF_SLICEL_C_Q) - 0.058 1.783 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/statshold_reg[35]/Q - net (fo=1, routed) 0.068 1.851 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/statshold[35] - SLICE_X75Y129 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/statsout_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.726 1.969 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/CLK - SLICE_X75Y129 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/statsout_reg[35]/C - clock pessimism -0.196 1.773 - SLICE_X75Y129 FDRE (Hold_FFF2_SLICEL_C_D) - 0.062 1.835 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_8192_9215_bytes_accumulator/statsout_reg[35] - ------------------------------------------------------------------- - required time -1.835 - arrival time 1.851 - ------------------------------------------------------------------- - slack 0.016 - -Slack (MET) : 0.016ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/counter_lsb_d1_reg[15]/C - (rising edge-triggered cell FDSE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/statshold_reg[15]/D - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: xxv_ethernet_0_tx_clk_out_0 - Path Type: Hold (Min at Slow Process Corner) - Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.124ns (logic 0.060ns (48.387%) route 0.064ns (51.613%)) - Logic Levels: 0 - Clock Path Skew: 0.046ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.049ns - Source Clock Delay (SCD): 1.800ns + Clock Path Skew: 0.052ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.048ns + Source Clock Delay (SCD): 1.793ns Clock Pessimism Removal (CPR): 0.203ns - Clock Net Delay (Source): 1.587ns (routing 0.454ns, distribution 1.133ns) - Clock Net Delay (Destination): 1.806ns (routing 0.508ns, distribution 1.298ns) + Clock Net Delay (Source): 1.580ns (routing 0.454ns, distribution 1.126ns) + Clock Net Delay (Destination): 1.805ns (routing 0.508ns, distribution 1.297ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -4598,13 +4193,13 @@ Slack (MET) : 0.016ns (arrival time - required time) net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.587 1.800 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/CLK - SLICE_X97Y121 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/counter_lsb_d1_reg[15]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.580 1.793 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/tx_clk + SLICE_X95Y131 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/datain0_r_reg[5]/C ------------------------------------------------------------------- ------------------- - SLICE_X97Y121 FDSE (Prop_BFF2_SLICEL_C_Q) - 0.060 1.860 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/counter_lsb_d1_reg[15]/Q - net (fo=1, routed) 0.064 1.924 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/counter_lsb_d1_reg_n_0_[15] - SLICE_X97Y123 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/statshold_reg[15]/D + SLICE_X95Y131 FDRE (Prop_FFF_SLICEL_C_Q) + 0.058 1.851 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/datain0_r_reg[5]/Q + net (fo=1, routed) 0.066 1.917 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/datain0_r_reg_n_0_[5] + SLICE_X95Y132 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/datain0_p0_r_reg[5]/D ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -4613,87 +4208,33 @@ Slack (MET) : 0.016ns (arrival time - required time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.806 2.049 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/CLK - SLICE_X97Y123 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/statshold_reg[15]/C - clock pessimism -0.203 1.846 - SLICE_X97Y123 FDRE (Hold_DFF2_SLICEL_C_D) - 0.062 1.908 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_good_packets_accumulator/statshold_reg[15] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.805 2.048 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/tx_clk + SLICE_X95Y132 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/datain0_p0_r_reg[5]/C + clock pessimism -0.203 1.845 + SLICE_X95Y132 FDRE (Hold_GFF2_SLICEL_C_D) + 0.062 1.907 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/datain0_p0_r_reg[5] ------------------------------------------------------------------- - required time -1.908 - arrival time 1.924 + required time -1.907 + arrival time 1.917 ------------------------------------------------------------------- - slack 0.016 + slack 0.010 -Slack (MET) : 0.017ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[52]/C +Slack (MET) : 0.013ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/counter_msb_reg[21]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[180]/D + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/statshold_reg[45]/D (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.237ns (logic 0.093ns (39.241%) route 0.144ns (60.759%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.160ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.057ns - Source Clock Delay (SCD): 1.743ns - Clock Pessimism Removal (CPR): 0.154ns - Clock Net Delay (Source): 1.530ns (routing 0.454ns, distribution 1.076ns) - Clock Net Delay (Destination): 1.814ns (routing 0.508ns, distribution 1.306ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.530 1.743 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/tx_clk - SLICE_X86Y104 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[52]/C - ------------------------------------------------------------------- ------------------- - SLICE_X86Y104 FDRE (Prop_BFF_SLICEM_C_Q) - 0.058 1.801 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[52]/Q - net (fo=5, routed) 0.120 1.921 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg_n_0_[52] - SLICE_X90Y104 LUT5 (Prop_F6LUT_SLICEL_I3_O) - 0.035 1.956 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r[180]_i_1/O - net (fo=1, routed) 0.024 1.980 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_nxt[180] - SLICE_X90Y104 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[180]/D - ------------------------------------------------------------------- ------------------- - - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.814 2.057 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/tx_clk - SLICE_X90Y104 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[180]/C - clock pessimism -0.154 1.903 - SLICE_X90Y104 FDRE (Hold_FFF_SLICEL_C_D) - 0.060 1.963 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[180] - ------------------------------------------------------------------- - required time -1.963 - arrival time 1.980 - ------------------------------------------------------------------- - slack 0.017 - -Slack (MET) : 0.017ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat_fmbuf0_r_reg[31]/C - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat_fmbuf0_rr_reg[31]/D - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: xxv_ethernet_0_tx_clk_out_0 - Path Type: Hold (Min at Slow Process Corner) - Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.245ns (logic 0.060ns (24.490%) route 0.185ns (75.510%)) + Data Path Delay: 0.184ns (logic 0.058ns (31.522%) route 0.126ns (68.478%)) Logic Levels: 0 - Clock Path Skew: 0.166ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.060ns - Source Clock Delay (SCD): 1.740ns - Clock Pessimism Removal (CPR): 0.154ns - Clock Net Delay (Source): 1.527ns (routing 0.454ns, distribution 1.073ns) - Clock Net Delay (Destination): 1.817ns (routing 0.508ns, distribution 1.309ns) + Clock Path Skew: 0.109ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.976ns + Source Clock Delay (SCD): 1.722ns + Clock Pessimism Removal (CPR): 0.145ns + Clock Net Delay (Source): 1.509ns (routing 0.454ns, distribution 1.055ns) + Clock Net Delay (Destination): 1.733ns (routing 0.508ns, distribution 1.225ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -4703,13 +4244,13 @@ Slack (MET) : 0.017ns (arrival time - required time) net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.527 1.740 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/tx_clk - SLICE_X82Y109 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat_fmbuf0_r_reg[31]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.509 1.722 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/CLK + SLICE_X83Y168 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/counter_msb_reg[21]/C ------------------------------------------------------------------- ------------------- - SLICE_X82Y109 FDRE (Prop_BFF2_SLICEL_C_Q) - 0.060 1.800 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat_fmbuf0_r_reg[31]/Q - net (fo=1, routed) 0.185 1.985 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat_fmbuf0_r[31] - SLICE_X90Y109 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat_fmbuf0_rr_reg[31]/D + SLICE_X83Y168 FDRE (Prop_CFF_SLICEM_C_Q) + 0.058 1.780 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/counter_msb_reg[21]/Q + net (fo=2, routed) 0.126 1.906 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/p_0_in1_in[45] + SLICE_X81Y169 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/statshold_reg[45]/D ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -4718,33 +4259,138 @@ Slack (MET) : 0.017ns (arrival time - required time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.817 2.060 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/tx_clk - SLICE_X90Y109 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat_fmbuf0_rr_reg[31]/C - clock pessimism -0.154 1.906 - SLICE_X90Y109 FDRE (Hold_EFF2_SLICEL_C_D) - 0.062 1.968 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat_fmbuf0_rr_reg[31] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.733 1.976 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/CLK + SLICE_X81Y169 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/statshold_reg[45]/C + clock pessimism -0.145 1.831 + SLICE_X81Y169 FDRE (Hold_FFF2_SLICEM_C_D) + 0.062 1.893 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_small_accumulator/statshold_reg[45] ------------------------------------------------------------------- - required time -1.968 - arrival time 1.985 + required time -1.893 + arrival time 1.906 ------------------------------------------------------------------- - slack 0.017 + slack 0.013 + +Slack (MET) : 0.014ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_reg[23]/C + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_d1_reg[23]/D + (rising edge-triggered cell FDSE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: xxv_ethernet_0_tx_clk_out_0 + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) + Data Path Delay: 0.174ns (logic 0.058ns (33.333%) route 0.116ns (66.667%)) + Logic Levels: 0 + Clock Path Skew: 0.100ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.964ns + Source Clock Delay (SCD): 1.719ns + Clock Pessimism Removal (CPR): 0.145ns + Clock Net Delay (Source): 1.506ns (routing 0.454ns, distribution 1.052ns) + Clock Net Delay (Destination): 1.721ns (routing 0.508ns, distribution 1.213ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.506 1.719 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/CLK + SLICE_X86Y162 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_reg[23]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y162 FDRE (Prop_HFF_SLICEM_C_Q) + 0.058 1.777 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_reg[23]/Q + net (fo=3, routed) 0.116 1.893 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_reg_n_0_[23] + SLICE_X85Y163 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_d1_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.721 1.964 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/CLK + SLICE_X85Y163 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_d1_reg[23]/C + clock pessimism -0.145 1.819 + SLICE_X85Y163 FDSE (Hold_DFF_SLICEL_C_D) + 0.060 1.879 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_d1_reg[23] + ------------------------------------------------------------------- + required time -1.879 + arrival time 1.893 + ------------------------------------------------------------------- + slack 0.014 + +Slack (MET) : 0.014ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[64]/C + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat4_p5_r_reg[0]/D + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: xxv_ethernet_0_tx_clk_out_0 + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) + Data Path Delay: 0.167ns (logic 0.082ns (49.102%) route 0.085ns (50.898%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.093ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.035ns + Source Clock Delay (SCD): 1.789ns + Clock Pessimism Removal (CPR): 0.153ns + Clock Net Delay (Source): 1.576ns (routing 0.454ns, distribution 1.122ns) + Clock Net Delay (Destination): 1.792ns (routing 0.508ns, distribution 1.284ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.576 1.789 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/tx_clk + SLICE_X97Y141 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[64]/C + ------------------------------------------------------------------- ------------------- + SLICE_X97Y141 FDRE (Prop_BFF_SLICEL_C_Q) + 0.059 1.848 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/dat0_p3_r_reg[64]/Q + net (fo=5, routed) 0.063 1.911 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/pak_dat1_p4_r[0] + SLICE_X95Y141 LUT6 (Prop_B6LUT_SLICEL_I1_O) + 0.023 1.934 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat4_p5_r[0]_i_1/O + net (fo=1, routed) 0.022 1.956 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat4_p5_r[0]_i_1_n_0 + SLICE_X95Y141 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat4_p5_r_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.792 2.035 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/tx_clk + SLICE_X95Y141 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat4_p5_r_reg[0]/C + clock pessimism -0.153 1.882 + SLICE_X95Y141 FDRE (Hold_BFF_SLICEL_C_D) + 0.060 1.942 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_TX_LBUS_ADAPTER/sh_dat4_p5_r_reg[0] + ------------------------------------------------------------------- + required time -1.942 + arrival time 1.956 + ------------------------------------------------------------------- + slack 0.014 Slack (MET) : 0.018ns (arrival time - required time) - Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/counter_lsb_d1_reg[21]/C - (rising edge-triggered cell FDSE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/statshold_reg[21]/D + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_reg_ctl_tx_test_pattern_seed_a_r_syncer/dataout_reg_reg[38]/C + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_out_reg[38]/D (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.152ns (logic 0.059ns (38.816%) route 0.093ns (61.184%)) + Data Path Delay: 0.130ns (logic 0.061ns (46.923%) route 0.069ns (53.077%)) Logic Levels: 0 - Clock Path Skew: 0.072ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 2.000ns - Source Clock Delay (SCD): 1.774ns - Clock Pessimism Removal (CPR): 0.154ns - Clock Net Delay (Source): 1.561ns (routing 0.454ns, distribution 1.107ns) - Clock Net Delay (Destination): 1.757ns (routing 0.508ns, distribution 1.249ns) + Clock Path Skew: 0.050ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.081ns + Source Clock Delay (SCD): 1.827ns + Clock Pessimism Removal (CPR): 0.204ns + Clock Net Delay (Source): 1.614ns (routing 0.454ns, distribution 1.160ns) + Clock Net Delay (Destination): 1.838ns (routing 0.508ns, distribution 1.330ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -4754,13 +4400,13 @@ Slack (MET) : 0.018ns (arrival time - required time) net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.561 1.774 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/CLK - SLICE_X91Y147 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/counter_lsb_d1_reg[21]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.614 1.827 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_reg_ctl_tx_test_pattern_seed_a_r_syncer/CLK + SLICE_X102Y164 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_reg_ctl_tx_test_pattern_seed_a_r_syncer/dataout_reg_reg[38]/C ------------------------------------------------------------------- ------------------- - SLICE_X91Y147 FDSE (Prop_CFF2_SLICEL_C_Q) - 0.059 1.833 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/counter_lsb_d1_reg[21]/Q - net (fo=1, routed) 0.093 1.926 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/p_0_in1_in[21] - SLICE_X93Y147 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/statshold_reg[21]/D + SLICE_X102Y164 FDRE (Prop_DFF2_SLICEL_C_Q) + 0.061 1.888 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_reg_ctl_tx_test_pattern_seed_a_r_syncer/dataout_reg_reg[38]/Q + net (fo=1, routed) 0.069 1.957 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_r_sync[38] + SLICE_X102Y162 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_out_reg[38]/D ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -4769,17 +4415,272 @@ Slack (MET) : 0.018ns (arrival time - required time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.757 2.000 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/CLK - SLICE_X93Y147 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/statshold_reg[21]/C - clock pessimism -0.154 1.846 - SLICE_X93Y147 FDRE (Hold_HFF2_SLICEM_C_D) - 0.062 1.908 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/statshold_reg[21] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.838 2.081 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/CLK + SLICE_X102Y162 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_out_reg[38]/C + clock pessimism -0.204 1.877 + SLICE_X102Y162 FDRE (Hold_EFF2_SLICEL_C_D) + 0.062 1.939 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/ctl_tx_test_pattern_seed_a_out_reg[38] ------------------------------------------------------------------- - required time -1.908 - arrival time 1.926 + required time -1.939 + arrival time 1.957 ------------------------------------------------------------------- slack 0.018 +Slack (MET) : 0.018ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/counter_msb_reg[7]/C + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/statshold_reg[31]/D + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: xxv_ethernet_0_tx_clk_out_0 + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) + Data Path Delay: 0.134ns (logic 0.059ns (44.030%) route 0.075ns (55.970%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.968ns + Source Clock Delay (SCD): 1.717ns + Clock Pessimism Removal (CPR): 0.195ns + Clock Net Delay (Source): 1.504ns (routing 0.454ns, distribution 1.050ns) + Clock Net Delay (Destination): 1.725ns (routing 0.508ns, distribution 1.217ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.504 1.717 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/CLK + SLICE_X85Y169 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/counter_msb_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X85Y169 FDRE (Prop_BFF_SLICEL_C_Q) + 0.059 1.776 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/counter_msb_reg[7]/Q + net (fo=2, routed) 0.075 1.851 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/p_0_in1_in[31] + SLICE_X85Y168 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/statshold_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.725 1.968 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/CLK + SLICE_X85Y168 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/statshold_reg[31]/C + clock pessimism -0.195 1.773 + SLICE_X85Y168 FDRE (Hold_DFF_SLICEL_C_D) + 0.060 1.833 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/statshold_reg[31] + ------------------------------------------------------------------- + required time -1.833 + arrival time 1.851 + ------------------------------------------------------------------- + slack 0.018 + +Slack (MET) : 0.018ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/counter_lsb_reg[14]/C + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/counter_lsb_d1_reg[14]/D + (rising edge-triggered cell FDSE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: xxv_ethernet_0_tx_clk_out_0 + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) + Data Path Delay: 0.181ns (logic 0.059ns (32.597%) route 0.122ns (67.403%)) + Logic Levels: 0 + Clock Path Skew: 0.101ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.028ns + Source Clock Delay (SCD): 1.774ns + Clock Pessimism Removal (CPR): 0.153ns + Clock Net Delay (Source): 1.561ns (routing 0.454ns, distribution 1.107ns) + Clock Net Delay (Destination): 1.785ns (routing 0.508ns, distribution 1.277ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.561 1.774 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/CLK + SLICE_X91Y161 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/counter_lsb_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X91Y161 FDRE (Prop_GFF_SLICEL_C_Q) + 0.059 1.833 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/counter_lsb_reg[14]/Q + net (fo=3, routed) 0.122 1.955 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/counter_lsb_reg_n_0_[14] + SLICE_X89Y162 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/counter_lsb_d1_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.785 2.028 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/CLK + SLICE_X89Y162 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/counter_lsb_d1_reg[14]/C + clock pessimism -0.153 1.875 + SLICE_X89Y162 FDSE (Hold_AFF2_SLICEM_C_D) + 0.062 1.937 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_unicast_accumulator/counter_lsb_d1_reg[14] + ------------------------------------------------------------------- + required time -1.937 + arrival time 1.955 + ------------------------------------------------------------------- + slack 0.018 + +Slack (MET) : 0.019ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/counter_lsb_d1_reg[23]/C + (rising edge-triggered cell FDSE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/statshold_reg[23]/D + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: xxv_ethernet_0_tx_clk_out_0 + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) + Data Path Delay: 0.164ns (logic 0.058ns (35.366%) route 0.106ns (64.634%)) + Logic Levels: 0 + Clock Path Skew: 0.083ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.961ns + Source Clock Delay (SCD): 1.733ns + Clock Pessimism Removal (CPR): 0.145ns + Clock Net Delay (Source): 1.520ns (routing 0.454ns, distribution 1.066ns) + Clock Net Delay (Destination): 1.718ns (routing 0.508ns, distribution 1.210ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.520 1.733 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/CLK + SLICE_X81Y174 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/counter_lsb_d1_reg[23]/C + ------------------------------------------------------------------- ------------------- + SLICE_X81Y174 FDSE (Prop_DFF_SLICEM_C_Q) + 0.058 1.791 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/counter_lsb_d1_reg[23]/Q + net (fo=1, routed) 0.106 1.897 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/p_0_in1_in[23] + SLICE_X80Y173 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/statshold_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.718 1.961 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/CLK + SLICE_X80Y173 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/statshold_reg[23]/C + clock pessimism -0.145 1.816 + SLICE_X80Y173 FDRE (Hold_HFF2_SLICEL_C_D) + 0.062 1.878 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_bad_fcs_accumulator/statshold_reg[23] + ------------------------------------------------------------------- + required time -1.878 + arrival time 1.897 + ------------------------------------------------------------------- + slack 0.019 + +Slack (MET) : 0.019ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_reg[3]/C + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_d1_reg[3]/D + (rising edge-triggered cell FDSE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: xxv_ethernet_0_tx_clk_out_0 + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) + Data Path Delay: 0.178ns (logic 0.059ns (33.146%) route 0.119ns (66.854%)) + Logic Levels: 0 + Clock Path Skew: 0.099ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.960ns + Source Clock Delay (SCD): 1.716ns + Clock Pessimism Removal (CPR): 0.145ns + Clock Net Delay (Source): 1.503ns (routing 0.454ns, distribution 1.049ns) + Clock Net Delay (Destination): 1.717ns (routing 0.508ns, distribution 1.209ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.503 1.716 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/CLK + SLICE_X87Y160 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y160 FDRE (Prop_BFF_SLICEL_C_Q) + 0.059 1.775 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_reg[3]/Q + net (fo=3, routed) 0.119 1.894 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_reg_n_0_[3] + SLICE_X85Y159 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_d1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.717 1.960 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/CLK + SLICE_X85Y159 FDSE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_d1_reg[3]/C + clock pessimism -0.145 1.815 + SLICE_X85Y159 FDSE (Hold_CFF_SLICEL_C_D) + 0.060 1.875 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_packet_1024_1518_bytes_accumulator/counter_lsb_d1_reg[3] + ------------------------------------------------------------------- + required time -1.875 + arrival time 1.894 + ------------------------------------------------------------------- + slack 0.019 + +Slack (MET) : 0.020ns (arrival time - required time) + Source: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/counter_msb_reg[11]/C + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/statshold_reg[35]/D + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: xxv_ethernet_0_tx_clk_out_0 + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) + Data Path Delay: 0.236ns (logic 0.058ns (24.576%) route 0.178ns (75.424%)) + Logic Levels: 0 + Clock Path Skew: 0.156ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.033ns + Source Clock Delay (SCD): 1.729ns + Clock Pessimism Removal (CPR): 0.148ns + Clock Net Delay (Source): 1.516ns (routing 0.454ns, distribution 1.062ns) + Clock Net Delay (Destination): 1.790ns (routing 0.508ns, distribution 1.282ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.099 0.099 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 0.213 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.516 1.729 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/CLK + SLICE_X87Y133 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/counter_msb_reg[11]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y133 FDRE (Prop_CFF_SLICEL_C_Q) + 0.058 1.787 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/counter_msb_reg[11]/Q + net (fo=2, routed) 0.178 1.965 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/counter_msb_reg_n_0_[11] + SLICE_X89Y135 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/statshold_reg[35]/D + ------------------------------------------------------------------- ------------------- + + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.790 2.033 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/CLK + SLICE_X89Y135 FDRE r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/statshold_reg[35]/C + clock pessimism -0.148 1.885 + SLICE_X89Y135 FDRE (Hold_HFF_SLICEM_C_D) + 0.060 1.945 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_total_bytes_accumulator/statshold_reg[35] + ------------------------------------------------------------------- + required time -1.945 + arrival time 1.965 + ------------------------------------------------------------------- + slack 0.020 + @@ -4792,36 +4693,36 @@ Period(ns): 6.400 Sources: { pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y29 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_15/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y19 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_45/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y30 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_16/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y20 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_46/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y31 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_17/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y21 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_47/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y22 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_48/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X3Y4 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_18/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y23 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_49/CLKARDCLK -Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X3Y5 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_19/CLKARDCLK -Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y21 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_47/CLKARDCLK -Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y23 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_49/CLKBWRCLK -Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X3Y7 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_21/CLKBWRCLK -Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y15 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_57/CLKARDCLK -Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y33 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_59/CLKARDCLK -Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X3Y19 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_37/CLKARDCLK -Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y18 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_44/CLKARDCLK -Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y18 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_44/CLKARDCLK -Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y26 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_12/CLKBWRCLK -Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y30 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_16/CLKARDCLK -High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y29 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_15/CLKARDCLK -High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y30 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_16/CLKARDCLK -High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y20 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_46/CLKBWRCLK -High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y31 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_17/CLKBWRCLK -High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y21 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_47/CLKARDCLK -High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X3Y4 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_18/CLKBWRCLK -High Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X3Y4 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_18/CLKBWRCLK -High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X3Y27 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_5/CLKARDCLK -High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X3Y24 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_2/CLKARDCLK -High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X3Y24 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_2/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X3Y33 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_15/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X3Y23 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_45/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X3Y34 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_16/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X3Y24 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_46/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X3Y35 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_17/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X3Y25 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_47/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X3Y26 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_48/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y36 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_18/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X3Y27 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_49/CLKARDCLK +Min Period n/a RAMB36E2/CLKARDCLK n/a 1.569 6.400 4.831 RAMB36_X2Y37 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_19/CLKARDCLK +Low Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X3Y34 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_16/CLKBWRCLK +Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X3Y24 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_46/CLKBWRCLK +Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y40 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_22/CLKBWRCLK +Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y23 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_53/CLKARDCLK +Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y24 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_54/CLKARDCLK +Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y26 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_56/CLKBWRCLK +Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X2Y29 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_3/CLKBWRCLK +Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y15 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_61/CLKARDCLK +Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y18 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_64/CLKARDCLK +Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y18 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_64/CLKARDCLK +High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X3Y33 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_15/CLKARDCLK +High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X3Y33 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_15/CLKARDCLK +High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X3Y23 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_45/CLKBWRCLK +High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X3Y34 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_16/CLKARDCLK +High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X3Y24 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_46/CLKBWRCLK +High Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.542 3.200 2.658 RAMB36_X3Y35 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_17/CLKBWRCLK +High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X3Y25 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_47/CLKARDCLK +High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X2Y36 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_18/CLKARDCLK +High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X3Y27 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_49/CLKARDCLK +High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.542 3.200 2.658 RAMB36_X3Y27 pl_eth_10g_i/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_49/CLKARDCLK Max Skew Slow GTHE4_CHANNEL/TXUSRCLK2 GTHE4_CHANNEL/TXUSRCLK 0.751 0.228 0.523 GTHE4_CHANNEL_X0Y10 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXUSRCLK2 Max Skew Fast GTHE4_CHANNEL/TXUSRCLK2 GTHE4_CHANNEL/TXUSRCLK 0.783 0.145 0.638 GTHE4_CHANNEL_X0Y10 pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXUSRCLK2 @@ -4831,194 +4732,14 @@ Max Skew Fast GTHE4_CHANNEL/TXUSRCLK2 GTHE4_CHANNEL/TXUSRCLK 0.783 From Clock: Net To Clock: clk_pl_0 -Setup : 0 Failing Endpoints, Worst Slack 5.389ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 5.329ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 5.389ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk_pl_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 1.036ns (logic 0.080ns (7.722%) route 0.956ns (92.278%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 6.400ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X65Y83 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C - SLICE_X65Y83 FDRE (Prop_HFF2_SLICEL_C_Q) - 0.080 0.080 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.956 1.036 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] - SLICE_X65Y84 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - ------------------------------------------------------------------- ------------------- - - max delay 6.400 6.400 - SLICE_X65Y84 FDRE (Setup_CFF2_SLICEL_C_D) - 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] - ------------------------------------------------------------------- - required time 6.425 - arrival time -1.036 - ------------------------------------------------------------------- - slack 5.389 - -Slack (MET) : 5.954ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk_pl_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.471ns (logic 0.081ns (17.197%) route 0.390ns (82.803%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 6.400ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C - SLICE_X52Y75 FDRE (Prop_GFF2_SLICEL_C_Q) - 0.081 0.081 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.390 0.471 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2] - SLICE_X57Y76 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - ------------------------------------------------------------------- ------------------- - - max delay 6.400 6.400 - SLICE_X57Y76 FDRE (Setup_DFF2_SLICEM_C_D) - 0.025 6.425 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] - ------------------------------------------------------------------- - required time 6.425 - arrival time -0.471 - ------------------------------------------------------------------- - slack 5.954 - -Slack (MET) : 5.966ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk_pl_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.459ns (logic 0.080ns (17.429%) route 0.379ns (82.571%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 6.400ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C - SLICE_X52Y75 FDRE (Prop_HFF2_SLICEL_C_Q) - 0.080 0.080 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.379 0.459 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1] - SLICE_X56Y77 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - ------------------------------------------------------------------- ------------------- - - max delay 6.400 6.400 - SLICE_X56Y77 FDRE (Setup_HFF2_SLICEM_C_D) - 0.025 6.425 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] - ------------------------------------------------------------------- - required time 6.425 - arrival time -0.459 - ------------------------------------------------------------------- - slack 5.966 - -Slack (MET) : 5.977ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk_pl_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.448ns (logic 0.079ns (17.634%) route 0.369ns (82.366%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 6.400ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X65Y83 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C - SLICE_X65Y83 FDRE (Prop_HFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.369 0.448 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] - SLICE_X65Y83 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D - ------------------------------------------------------------------- ------------------- - - max delay 6.400 6.400 - SLICE_X65Y83 FDRE (Setup_DFF2_SLICEL_C_D) - 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] - ------------------------------------------------------------------- - required time 6.425 - arrival time -0.448 - ------------------------------------------------------------------- - slack 5.977 - -Slack (MET) : 6.011ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk_pl_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.414ns (logic 0.079ns (19.082%) route 0.335ns (80.918%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 6.400ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C - SLICE_X52Y75 FDRE (Prop_HFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.335 0.414 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0] - SLICE_X55Y76 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D - ------------------------------------------------------------------- ------------------- - - max delay 6.400 6.400 - SLICE_X55Y76 FDRE (Setup_DFF2_SLICEL_C_D) - 0.025 6.425 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] - ------------------------------------------------------------------- - required time 6.425 - arrival time -0.414 - ------------------------------------------------------------------- - slack 6.011 - -Slack (MET) : 6.013ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk_pl_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.412ns (logic 0.079ns (19.175%) route 0.333ns (80.825%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 6.400ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X52Y74 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C - SLICE_X52Y74 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.333 0.412 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3] - SLICE_X52Y74 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D - ------------------------------------------------------------------- ------------------- - - max delay 6.400 6.400 - SLICE_X52Y74 FDRE (Setup_DFF2_SLICEL_C_D) - 0.025 6.425 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] - ------------------------------------------------------------------- - required time 6.425 - arrival time -0.412 - ------------------------------------------------------------------- - slack 6.013 - -Slack (MET) : 6.032ns (required time - arrival time) +Slack (MET) : 5.329ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D @@ -5026,29 +4747,29 @@ Slack (MET) : 6.032ns (required time - arrival time) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.393ns (logic 0.078ns (19.847%) route 0.315ns (80.153%)) + Data Path Delay: 1.096ns (logic 0.079ns (7.208%) route 1.017ns (92.792%)) Logic Levels: 0 Timing Exception: MaxDelay Path 6.400ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X64Y95 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C - SLICE_X64Y95 FDRE (Prop_DFF_SLICEM_C_Q) - 0.078 0.078 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.315 0.393 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] - SLICE_X64Y96 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + SLICE_X68Y86 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X68Y86 FDRE (Prop_HFF_SLICEL_C_Q) + 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 1.017 1.096 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X68Y87 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- max delay 6.400 6.400 - SLICE_X64Y96 FDRE (Setup_DFF2_SLICEM_C_D) + SLICE_X68Y87 FDRE (Setup_DFF2_SLICEL_C_D) 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- required time 6.425 - arrival time -0.393 + arrival time -1.096 ------------------------------------------------------------------- - slack 6.032 + slack 5.329 -Slack (MET) : 6.043ns (required time - arrival time) +Slack (MET) : 5.908ns (required time - arrival time) Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D @@ -5056,59 +4777,149 @@ Slack (MET) : 6.043ns (required time - arrival time) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.382ns (logic 0.079ns (20.681%) route 0.303ns (79.319%)) + Data Path Delay: 0.517ns (logic 0.078ns (15.087%) route 0.439ns (84.913%)) Logic Levels: 0 Timing Exception: MaxDelay Path 6.400ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X59Y68 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C - SLICE_X59Y68 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.303 0.382 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0] - SLICE_X60Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + SLICE_X56Y68 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X56Y68 FDRE (Prop_DFF_SLICEM_C_Q) + 0.078 0.078 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.439 0.517 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0] + SLICE_X57Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- max delay 6.400 6.400 - SLICE_X60Y68 FDRE (Setup_HFF2_SLICEL_C_D) + SLICE_X57Y68 FDRE (Setup_HFF2_SLICEM_C_D) 0.025 6.425 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- required time 6.425 - arrival time -0.382 + arrival time -0.517 ------------------------------------------------------------------- - slack 6.043 + slack 5.908 -Slack (MET) : 6.074ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C +Slack (MET) : 5.999ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.351ns (logic 0.079ns (22.507%) route 0.272ns (77.493%)) + Data Path Delay: 0.426ns (logic 0.077ns (18.075%) route 0.349ns (81.925%)) Logic Levels: 0 Timing Exception: MaxDelay Path 6.400ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X65Y81 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C - SLICE_X65Y81 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.272 0.351 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] - SLICE_X65Y81 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X67Y85 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X67Y85 FDRE (Prop_AFF_SLICEM_C_Q) + 0.077 0.077 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.349 0.426 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X67Y85 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- max delay 6.400 6.400 - SLICE_X65Y81 FDRE (Setup_DFF2_SLICEL_C_D) - 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + SLICE_X67Y85 FDRE (Setup_HFF2_SLICEM_C_D) + 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- required time 6.425 - arrival time -0.351 + arrival time -0.426 ------------------------------------------------------------------- - slack 6.074 + slack 5.999 -Slack (MET) : 6.074ns (required time - arrival time) +Slack (MET) : 6.021ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: clk_pl_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (MaxDelay Path 6.400ns) + Data Path Delay: 0.404ns (logic 0.079ns (19.554%) route 0.325ns (80.446%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 6.400ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X58Y68 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X58Y68 FDRE (Prop_EFF_SLICEL_C_Q) + 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.325 0.404 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3] + SLICE_X58Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + max delay 6.400 6.400 + SLICE_X58Y68 FDRE (Setup_DFF2_SLICEL_C_D) + 0.025 6.425 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + required time 6.425 + arrival time -0.404 + ------------------------------------------------------------------- + slack 6.021 + +Slack (MET) : 6.032ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: clk_pl_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (MaxDelay Path 6.400ns) + Data Path Delay: 0.393ns (logic 0.080ns (20.356%) route 0.313ns (79.644%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 6.400ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X53Y74 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X53Y74 FDRE (Prop_DFF2_SLICEM_C_Q) + 0.080 0.080 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.313 0.393 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1] + SLICE_X53Y74 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 6.400 6.400 + SLICE_X53Y74 FDRE (Setup_HFF2_SLICEM_C_D) + 0.025 6.425 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 6.425 + arrival time -0.393 + ------------------------------------------------------------------- + slack 6.032 + +Slack (MET) : 6.049ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: clk_pl_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (MaxDelay Path 6.400ns) + Data Path Delay: 0.376ns (logic 0.078ns (20.745%) route 0.298ns (79.255%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 6.400ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X56Y95 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X56Y95 FDRE (Prop_DFF_SLICEM_C_Q) + 0.078 0.078 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.298 0.376 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X56Y94 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + max delay 6.400 6.400 + SLICE_X56Y94 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + required time 6.425 + arrival time -0.376 + ------------------------------------------------------------------- + slack 6.049 + +Slack (MET) : 6.055ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D @@ -5116,27 +4927,117 @@ Slack (MET) : 6.074ns (required time - arrival time) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.351ns (logic 0.079ns (22.507%) route 0.272ns (77.493%)) + Data Path Delay: 0.370ns (logic 0.076ns (20.541%) route 0.294ns (79.459%)) Logic Levels: 0 Timing Exception: MaxDelay Path 6.400ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X55Y94 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C - SLICE_X55Y94 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.272 0.351 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] - SLICE_X55Y94 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X56Y91 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X56Y91 FDRE (Prop_EFF_SLICEM_C_Q) + 0.076 0.076 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.294 0.370 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X56Y91 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- max delay 6.400 6.400 - SLICE_X55Y94 FDRE (Setup_DFF2_SLICEL_C_D) + SLICE_X56Y91 FDRE (Setup_DFF2_SLICEM_C_D) 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- required time 6.425 - arrival time -0.351 + arrival time -0.370 ------------------------------------------------------------------- - slack 6.074 + slack 6.055 + +Slack (MET) : 6.067ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: clk_pl_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (MaxDelay Path 6.400ns) + Data Path Delay: 0.358ns (logic 0.079ns (22.067%) route 0.279ns (77.933%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 6.400ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X64Y87 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X64Y87 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.279 0.358 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X64Y87 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + max delay 6.400 6.400 + SLICE_X64Y87 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + required time 6.425 + arrival time -0.358 + ------------------------------------------------------------------- + slack 6.067 + +Slack (MET) : 6.068ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: clk_pl_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (MaxDelay Path 6.400ns) + Data Path Delay: 0.357ns (logic 0.080ns (22.409%) route 0.277ns (77.591%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 6.400ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X56Y95 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X56Y95 FDRE (Prop_DFF2_SLICEM_C_Q) + 0.080 0.080 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.277 0.357 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X56Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 6.400 6.400 + SLICE_X56Y95 FDRE (Setup_GFF2_SLICEM_C_D) + 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 6.425 + arrival time -0.357 + ------------------------------------------------------------------- + slack 6.068 + +Slack (MET) : 6.072ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: clk_pl_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (MaxDelay Path 6.400ns) + Data Path Delay: 0.353ns (logic 0.079ns (22.380%) route 0.274ns (77.620%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 6.400ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X65Y85 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + SLICE_X65Y85 FDRE (Prop_DFF_SLICEL_C_Q) + 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.274 0.353 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X65Y85 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + max delay 6.400 6.400 + SLICE_X65Y85 FDRE (Setup_HFF2_SLICEL_C_D) + 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + required time 6.425 + arrival time -0.353 + ------------------------------------------------------------------- + slack 6.072 @@ -5146,194 +5047,44 @@ Slack (MET) : 6.074ns (required time - arrival time) From Clock: xxv_ethernet_0_tx_clk_out_0 To Clock: clk_pl_0 -Setup : 0 Failing Endpoints, Worst Slack 5.358ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 5.906ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 5.358ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C +Slack (MET) : 5.906ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 1.067ns (logic 0.081ns (7.591%) route 0.986ns (92.409%)) + Data Path Delay: 0.519ns (logic 0.080ns (15.414%) route 0.439ns (84.586%)) Logic Levels: 0 Timing Exception: MaxDelay Path 6.400ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X65Y63 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C - SLICE_X65Y63 FDRE (Prop_DFF2_SLICEL_C_Q) - 0.081 0.081 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.986 1.067 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] - SLICE_X65Y63 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + SLICE_X60Y67 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X60Y67 FDRE (Prop_HFF2_SLICEL_C_Q) + 0.080 0.080 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.439 0.519 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X63Y68 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D ------------------------------------------------------------------- ------------------- max delay 6.400 6.400 - SLICE_X65Y63 FDRE (Setup_HFF2_SLICEL_C_D) - 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + SLICE_X63Y68 FDRE (Setup_HFF2_SLICEM_C_D) + 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] ------------------------------------------------------------------- required time 6.425 - arrival time -1.067 + arrival time -0.519 ------------------------------------------------------------------- - slack 5.358 + slack 5.906 -Slack (MET) : 5.925ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk_pl_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.500ns (logic 0.079ns (15.800%) route 0.421ns (84.200%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 6.400ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X64Y62 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C - SLICE_X64Y62 FDRE (Prop_HFF_SLICEM_C_Q) - 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.421 0.500 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] - SLICE_X63Y62 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - ------------------------------------------------------------------- ------------------- - - max delay 6.400 6.400 - SLICE_X63Y62 FDRE (Setup_DFF2_SLICEM_C_D) - 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] - ------------------------------------------------------------------- - required time 6.425 - arrival time -0.500 - ------------------------------------------------------------------- - slack 5.925 - -Slack (MET) : 5.963ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk_pl_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.462ns (logic 0.080ns (17.316%) route 0.382ns (82.684%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 6.400ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X49Y51 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C - SLICE_X49Y51 FDRE (Prop_DFF2_SLICEM_C_Q) - 0.080 0.080 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.382 0.462 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1] - SLICE_X52Y52 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - ------------------------------------------------------------------- ------------------- - - max delay 6.400 6.400 - SLICE_X52Y52 FDRE (Setup_DFF2_SLICEL_C_D) - 0.025 6.425 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] - ------------------------------------------------------------------- - required time 6.425 - arrival time -0.462 - ------------------------------------------------------------------- - slack 5.963 - -Slack (MET) : 6.034ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk_pl_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.391ns (logic 0.079ns (20.205%) route 0.312ns (79.795%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 6.400ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X62Y67 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C - SLICE_X62Y67 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.312 0.391 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] - SLICE_X65Y68 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D - ------------------------------------------------------------------- ------------------- - - max delay 6.400 6.400 - SLICE_X65Y68 FDRE (Setup_DFF2_SLICEL_C_D) - 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] - ------------------------------------------------------------------- - required time 6.425 - arrival time -0.391 - ------------------------------------------------------------------- - slack 6.034 - -Slack (MET) : 6.040ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk_pl_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.385ns (logic 0.078ns (20.260%) route 0.307ns (79.740%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 6.400ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X54Y57 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C - SLICE_X54Y57 FDRE (Prop_CFF_SLICEM_C_Q) - 0.078 0.078 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.307 0.385 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2] - SLICE_X55Y57 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - ------------------------------------------------------------------- ------------------- - - max delay 6.400 6.400 - SLICE_X55Y57 FDRE (Setup_DFF2_SLICEL_C_D) - 0.025 6.425 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] - ------------------------------------------------------------------- - required time 6.425 - arrival time -0.385 - ------------------------------------------------------------------- - slack 6.040 - -Slack (MET) : 6.050ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: clk_pl_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.375ns (logic 0.079ns (21.067%) route 0.296ns (78.933%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 6.400ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X52Y53 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C - SLICE_X52Y53 FDRE (Prop_HFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.296 0.375 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2] - SLICE_X53Y53 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - ------------------------------------------------------------------- ------------------- - - max delay 6.400 6.400 - SLICE_X53Y53 FDRE (Setup_HFF2_SLICEM_C_D) - 0.025 6.425 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] - ------------------------------------------------------------------- - required time 6.425 - arrival time -0.375 - ------------------------------------------------------------------- - slack 6.050 - -Slack (MET) : 6.071ns (required time - arrival time) +Slack (MET) : 5.936ns (required time - arrival time) Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D @@ -5341,89 +5092,149 @@ Slack (MET) : 6.071ns (required time - arrival time) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.354ns (logic 0.076ns (21.469%) route 0.278ns (78.531%)) + Data Path Delay: 0.489ns (logic 0.078ns (15.951%) route 0.411ns (84.049%)) Logic Levels: 0 Timing Exception: MaxDelay Path 6.400ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X53Y49 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C - SLICE_X53Y49 FDRE (Prop_EFF_SLICEM_C_Q) - 0.076 0.076 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.278 0.354 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3] - SLICE_X53Y49 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X53Y47 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X53Y47 FDRE (Prop_HFF2_SLICEM_C_Q) + 0.078 0.078 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.411 0.489 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3] + SLICE_X53Y47 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- max delay 6.400 6.400 - SLICE_X53Y49 FDRE (Setup_CFF2_SLICEM_C_D) + SLICE_X53Y47 FDRE (Setup_DFF2_SLICEM_C_D) 0.025 6.425 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- required time 6.425 - arrival time -0.354 + arrival time -0.489 ------------------------------------------------------------------- - slack 6.071 + slack 5.936 -Slack (MET) : 6.072ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C +Slack (MET) : 5.940ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.353ns (logic 0.078ns (22.096%) route 0.275ns (77.904%)) + Data Path Delay: 0.485ns (logic 0.079ns (16.289%) route 0.406ns (83.711%)) Logic Levels: 0 Timing Exception: MaxDelay Path 6.400ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X49Y51 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C - SLICE_X49Y51 FDRE (Prop_DFF_SLICEM_C_Q) - 0.078 0.078 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.275 0.353 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0] - SLICE_X49Y51 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + SLICE_X60Y67 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X60Y67 FDRE (Prop_HFF_SLICEL_C_Q) + 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.406 0.485 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X63Y68 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- max delay 6.400 6.400 - SLICE_X49Y51 FDRE (Setup_HFF2_SLICEM_C_D) - 0.025 6.425 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + SLICE_X63Y68 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- required time 6.425 - arrival time -0.353 + arrival time -0.485 ------------------------------------------------------------------- - slack 6.072 + slack 5.940 -Slack (MET) : 6.072ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C +Slack (MET) : 5.968ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.353ns (logic 0.078ns (22.096%) route 0.275ns (77.904%)) + Data Path Delay: 0.457ns (logic 0.076ns (16.630%) route 0.381ns (83.370%)) Logic Levels: 0 Timing Exception: MaxDelay Path 6.400ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X63Y67 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C - SLICE_X63Y67 FDRE (Prop_DFF_SLICEM_C_Q) - 0.078 0.078 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.275 0.353 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] - SLICE_X63Y67 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + SLICE_X54Y57 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X54Y57 FDRE (Prop_EFF_SLICEM_C_Q) + 0.076 0.076 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.381 0.457 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3] + SLICE_X54Y57 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- max delay 6.400 6.400 - SLICE_X63Y67 FDRE (Setup_HFF2_SLICEM_C_D) - 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + SLICE_X54Y57 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 6.425 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- required time 6.425 - arrival time -0.353 + arrival time -0.457 ------------------------------------------------------------------- - slack 6.072 + slack 5.968 -Slack (MET) : 6.076ns (required time - arrival time) +Slack (MET) : 6.023ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: clk_pl_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (MaxDelay Path 6.400ns) + Data Path Delay: 0.402ns (logic 0.078ns (19.403%) route 0.324ns (80.597%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 6.400ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X63Y66 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X63Y66 FDRE (Prop_HFF2_SLICEM_C_Q) + 0.078 0.078 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.324 0.402 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X64Y66 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 6.400 6.400 + SLICE_X64Y66 FDRE (Setup_GFF2_SLICEM_C_D) + 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 6.425 + arrival time -0.402 + ------------------------------------------------------------------- + slack 6.023 + +Slack (MET) : 6.065ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: clk_pl_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (MaxDelay Path 6.400ns) + Data Path Delay: 0.360ns (logic 0.079ns (21.944%) route 0.281ns (78.056%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 6.400ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X64Y63 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X64Y63 FDRE (Prop_GFF2_SLICEM_C_Q) + 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.281 0.360 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X64Y64 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + max delay 6.400 6.400 + SLICE_X64Y64 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + required time 6.425 + arrival time -0.360 + ------------------------------------------------------------------- + slack 6.065 + +Slack (MET) : 6.068ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D @@ -5431,27 +5242,117 @@ Slack (MET) : 6.076ns (required time - arrival time) Path Group: clk_pl_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (MaxDelay Path 6.400ns) - Data Path Delay: 0.349ns (logic 0.079ns (22.636%) route 0.270ns (77.364%)) + Data Path Delay: 0.357ns (logic 0.079ns (22.129%) route 0.278ns (77.871%)) Logic Levels: 0 Timing Exception: MaxDelay Path 6.400ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X65Y63 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C - SLICE_X65Y63 FDRE (Prop_DFF_SLICEL_C_Q) + SLICE_X63Y66 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X63Y66 FDRE (Prop_HFF_SLICEM_C_Q) 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.270 0.349 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] - SLICE_X63Y62 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + net (fo=1, routed) 0.278 0.357 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X63Y66 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- max delay 6.400 6.400 - SLICE_X63Y62 FDRE (Setup_HFF2_SLICEM_C_D) + SLICE_X63Y66 FDRE (Setup_DFF2_SLICEM_C_D) 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- required time 6.425 - arrival time -0.349 + arrival time -0.357 ------------------------------------------------------------------- - slack 6.076 + slack 6.068 + +Slack (MET) : 6.078ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: clk_pl_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (MaxDelay Path 6.400ns) + Data Path Delay: 0.347ns (logic 0.078ns (22.478%) route 0.269ns (77.522%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 6.400ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X54Y57 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X54Y57 FDRE (Prop_HFF2_SLICEM_C_Q) + 0.078 0.078 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.269 0.347 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1] + SLICE_X53Y57 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 6.400 6.400 + SLICE_X53Y57 FDRE (Setup_HFF2_SLICEM_C_D) + 0.025 6.425 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 6.425 + arrival time -0.347 + ------------------------------------------------------------------- + slack 6.078 + +Slack (MET) : 6.089ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: clk_pl_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (MaxDelay Path 6.400ns) + Data Path Delay: 0.336ns (logic 0.079ns (23.512%) route 0.257ns (76.488%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 6.400ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X60Y67 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X60Y67 FDRE (Prop_EFF_SLICEL_C_Q) + 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.257 0.336 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X60Y67 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + max delay 6.400 6.400 + SLICE_X60Y67 FDRE (Setup_DFF2_SLICEL_C_D) + 0.025 6.425 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + required time 6.425 + arrival time -0.336 + ------------------------------------------------------------------- + slack 6.089 + +Slack (MET) : 6.102ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: clk_pl_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.400ns (MaxDelay Path 6.400ns) + Data Path Delay: 0.323ns (logic 0.079ns (24.458%) route 0.244ns (75.542%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 6.400ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X52Y49 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X52Y49 FDRE (Prop_HFF_SLICEL_C_Q) + 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.244 0.323 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0] + SLICE_X52Y46 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + max delay 6.400 6.400 + SLICE_X52Y46 FDRE (Setup_DFF2_SLICEL_C_D) + 0.025 6.425 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + required time 6.425 + arrival time -0.323 + ------------------------------------------------------------------- + slack 6.102 @@ -5461,14 +5362,44 @@ Slack (MET) : 6.076ns (required time - arrival time) From Clock: clk_pl_0 To Clock: Net -Setup : 0 Failing Endpoints, Worst Slack 6.864ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 6.958ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 6.864ns (required time - arrival time) +Slack (MET) : 6.958ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: Net + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (MaxDelay Path 8.000ns) + Data Path Delay: 1.067ns (logic 0.081ns (7.591%) route 0.986ns (92.409%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 8.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X65Y86 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X65Y86 FDRE (Prop_DFF2_SLICEL_C_Q) + 0.081 0.081 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.986 1.067 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X65Y86 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 8.000 8.000 + SLICE_X65Y86 FDRE (Setup_HFF2_SLICEL_C_D) + 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 8.025 + arrival time -1.067 + ------------------------------------------------------------------- + slack 6.958 + +Slack (MET) : 7.254ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D @@ -5476,89 +5407,89 @@ Slack (MET) : 6.864ns (required time - arrival time) Path Group: Net Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 1.161ns (logic 0.079ns (6.804%) route 1.082ns (93.196%)) + Data Path Delay: 0.771ns (logic 0.077ns (9.987%) route 0.694ns (90.013%)) Logic Levels: 0 Timing Exception: MaxDelay Path 8.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X65Y83 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C - SLICE_X65Y83 FDRE (Prop_AFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 1.082 1.161 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] - SLICE_X65Y83 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X64Y87 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X64Y87 FDRE (Prop_AFF_SLICEM_C_Q) + 0.077 0.077 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.694 0.771 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X64Y87 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- max delay 8.000 8.000 - SLICE_X65Y83 FDRE (Setup_GFF2_SLICEL_C_D) + SLICE_X64Y87 FDRE (Setup_GFF2_SLICEM_C_D) 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] - ------------------------------------------------------------------- - required time 8.025 - arrival time -1.161 - ------------------------------------------------------------------- - slack 6.864 - -Slack (MET) : 7.254ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: Net - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.771ns (logic 0.076ns (9.857%) route 0.695ns (90.143%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 8.000ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X64Y95 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C - SLICE_X64Y95 FDRE (Prop_FFF_SLICEM_C_Q) - 0.076 0.076 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.695 0.771 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] - SLICE_X64Y95 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - ------------------------------------------------------------------- ------------------- - - max delay 8.000 8.000 - SLICE_X64Y95 FDRE (Setup_CFF2_SLICEM_C_D) - 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- required time 8.025 arrival time -0.771 ------------------------------------------------------------------- slack 7.254 -Slack (MET) : 7.577ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C +Slack (MET) : 7.328ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.448ns (logic 0.079ns (17.634%) route 0.369ns (82.366%)) + Data Path Delay: 0.697ns (logic 0.079ns (11.334%) route 0.618ns (88.666%)) Logic Levels: 0 Timing Exception: MaxDelay Path 8.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X65Y82 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C - SLICE_X65Y82 FDRE (Prop_HFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.369 0.448 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] - SLICE_X65Y82 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + SLICE_X56Y95 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X56Y95 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.618 0.697 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X56Y96 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- max delay 8.000 8.000 - SLICE_X65Y82 FDRE (Setup_DFF2_SLICEL_C_D) - 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + SLICE_X56Y96 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- required time 8.025 - arrival time -0.448 + arrival time -0.697 ------------------------------------------------------------------- - slack 7.577 + slack 7.328 -Slack (MET) : 7.582ns (required time - arrival time) +Slack (MET) : 7.538ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: Net + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (MaxDelay Path 8.000ns) + Data Path Delay: 0.487ns (logic 0.079ns (16.222%) route 0.408ns (83.778%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 8.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X52Y73 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + SLICE_X52Y73 FDRE (Prop_CFF_SLICEL_C_Q) + 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.408 0.487 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2] + SLICE_X52Y73 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + max delay 8.000 8.000 + SLICE_X52Y73 FDRE (Setup_GFF2_SLICEL_C_D) + 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + required time 8.025 + arrival time -0.487 + ------------------------------------------------------------------- + slack 7.538 + +Slack (MET) : 7.547ns (required time - arrival time) Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D @@ -5566,119 +5497,29 @@ Slack (MET) : 7.582ns (required time - arrival time) Path Group: Net Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.443ns (logic 0.078ns (17.607%) route 0.365ns (82.393%)) + Data Path Delay: 0.478ns (logic 0.079ns (16.527%) route 0.399ns (83.473%)) Logic Levels: 0 Timing Exception: MaxDelay Path 8.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X56Y77 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C - SLICE_X56Y77 FDRE (Prop_DFF_SLICEM_C_Q) - 0.078 0.078 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.365 0.443 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0] - SLICE_X59Y75 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + SLICE_X52Y73 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X52Y73 FDRE (Prop_DFF_SLICEL_C_Q) + 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.399 0.478 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0] + SLICE_X54Y73 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- max delay 8.000 8.000 - SLICE_X59Y75 FDRE (Setup_HFF2_SLICEL_C_D) + SLICE_X54Y73 FDRE (Setup_HFF2_SLICEM_C_D) 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- required time 8.025 - arrival time -0.443 + arrival time -0.478 ------------------------------------------------------------------- - slack 7.582 + slack 7.547 -Slack (MET) : 7.589ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: Net - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.436ns (logic 0.078ns (17.890%) route 0.358ns (82.110%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 8.000ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X57Y68 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C - SLICE_X57Y68 FDRE (Prop_HFF2_SLICEM_C_Q) - 0.078 0.078 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.358 0.436 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1] - SLICE_X58Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - ------------------------------------------------------------------- ------------------- - - max delay 8.000 8.000 - SLICE_X58Y68 FDRE (Setup_HFF2_SLICEL_C_D) - 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] - ------------------------------------------------------------------- - required time 8.025 - arrival time -0.436 - ------------------------------------------------------------------- - slack 7.589 - -Slack (MET) : 7.626ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: Net - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.399ns (logic 0.079ns (19.799%) route 0.320ns (80.201%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 8.000ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X58Y68 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C - SLICE_X58Y68 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.320 0.399 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2] - SLICE_X59Y68 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D - ------------------------------------------------------------------- ------------------- - - max delay 8.000 8.000 - SLICE_X59Y68 FDRE (Setup_HFF2_SLICEL_C_D) - 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] - ------------------------------------------------------------------- - required time 8.025 - arrival time -0.399 - ------------------------------------------------------------------- - slack 7.626 - -Slack (MET) : 7.630ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D - (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: Net - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.395ns (logic 0.079ns (20.000%) route 0.316ns (80.000%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 8.000ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X57Y68 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C - SLICE_X57Y68 FDRE (Prop_HFF_SLICEM_C_Q) - 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.316 0.395 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0] - SLICE_X58Y67 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D - ------------------------------------------------------------------- ------------------- - - max delay 8.000 8.000 - SLICE_X58Y67 FDRE (Setup_DFF2_SLICEL_C_D) - 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] - ------------------------------------------------------------------- - required time 8.025 - arrival time -0.395 - ------------------------------------------------------------------- - slack 7.630 - -Slack (MET) : 7.635ns (required time - arrival time) +Slack (MET) : 7.578ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D @@ -5686,29 +5527,29 @@ Slack (MET) : 7.635ns (required time - arrival time) Path Group: Net Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.390ns (logic 0.079ns (20.256%) route 0.311ns (79.744%)) + Data Path Delay: 0.447ns (logic 0.076ns (17.002%) route 0.371ns (82.998%)) Logic Levels: 0 Timing Exception: MaxDelay Path 8.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X60Y94 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C - SLICE_X60Y94 FDRE (Prop_EFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.311 0.390 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] - SLICE_X60Y94 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X57Y96 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X57Y96 FDRE (Prop_EFF_SLICEM_C_Q) + 0.076 0.076 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.371 0.447 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X57Y96 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- max delay 8.000 8.000 - SLICE_X60Y94 FDRE (Setup_DFF2_SLICEL_C_D) + SLICE_X57Y96 FDRE (Setup_DFF2_SLICEM_C_D) 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- required time 8.025 - arrival time -0.390 + arrival time -0.447 ------------------------------------------------------------------- - slack 7.635 + slack 7.578 -Slack (MET) : 7.647ns (required time - arrival time) +Slack (MET) : 7.622ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D @@ -5716,57 +5557,117 @@ Slack (MET) : 7.647ns (required time - arrival time) Path Group: Net Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.378ns (logic 0.076ns (20.106%) route 0.302ns (79.894%)) + Data Path Delay: 0.403ns (logic 0.079ns (19.603%) route 0.324ns (80.397%)) Logic Levels: 0 Timing Exception: MaxDelay Path 8.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X64Y91 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C - SLICE_X64Y91 FDRE (Prop_EFF_SLICEM_C_Q) - 0.076 0.076 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.302 0.378 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] - SLICE_X64Y91 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X68Y85 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X68Y85 FDRE (Prop_EFF_SLICEL_C_Q) + 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.324 0.403 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X68Y85 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- max delay 8.000 8.000 - SLICE_X64Y91 FDRE (Setup_DFF2_SLICEM_C_D) + SLICE_X68Y85 FDRE (Setup_DFF2_SLICEL_C_D) 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- required time 8.025 - arrival time -0.378 + arrival time -0.403 ------------------------------------------------------------------- - slack 7.647 + slack 7.622 -Slack (MET) : 7.663ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C +Slack (MET) : 7.623ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: Net Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.362ns (logic 0.079ns (21.823%) route 0.283ns (78.177%)) + Data Path Delay: 0.402ns (logic 0.079ns (19.652%) route 0.323ns (80.348%)) Logic Levels: 0 Timing Exception: MaxDelay Path 8.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X55Y94 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C - SLICE_X55Y94 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.283 0.362 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] - SLICE_X58Y93 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + SLICE_X54Y67 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X54Y67 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.323 0.402 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0] + SLICE_X56Y67 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- max delay 8.000 8.000 - SLICE_X58Y93 FDRE (Setup_DFF2_SLICEL_C_D) - 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + SLICE_X56Y67 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- required time 8.025 - arrival time -0.362 + arrival time -0.402 ------------------------------------------------------------------- - slack 7.663 + slack 7.623 + +Slack (MET) : 7.654ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: Net + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (MaxDelay Path 8.000ns) + Data Path Delay: 0.371ns (logic 0.079ns (21.294%) route 0.292ns (78.706%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 8.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X54Y69 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X54Y69 FDRE (Prop_EFF2_SLICEM_C_Q) + 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.292 0.371 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3] + SLICE_X54Y69 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + max delay 8.000 8.000 + SLICE_X54Y69 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + required time 8.025 + arrival time -0.371 + ------------------------------------------------------------------- + slack 7.654 + +Slack (MET) : 7.655ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: Net + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (MaxDelay Path 8.000ns) + Data Path Delay: 0.370ns (logic 0.081ns (21.892%) route 0.289ns (78.108%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 8.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X52Y73 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X52Y73 FDRE (Prop_DFF2_SLICEL_C_Q) + 0.081 0.081 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.289 0.370 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1] + SLICE_X55Y73 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 8.000 8.000 + SLICE_X55Y73 FDRE (Setup_DFF2_SLICEL_C_D) + 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 8.025 + arrival time -0.370 + ------------------------------------------------------------------- + slack 7.655 @@ -5776,44 +5677,104 @@ Slack (MET) : 7.663ns (required time - arrival time) From Clock: clk_pl_0 To Clock: xxv_ethernet_0_tx_clk_out_0 -Setup : 0 Failing Endpoints, Worst Slack 7.264ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 7.432ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 7.264ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C +Slack (MET) : 7.432ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.761ns (logic 0.077ns (10.118%) route 0.684ns (89.882%)) + Data Path Delay: 0.593ns (logic 0.078ns (13.153%) route 0.515ns (86.847%)) Logic Levels: 0 Timing Exception: MaxDelay Path 8.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X64Y62 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C - SLICE_X64Y62 FDRE (Prop_AFF_SLICEM_C_Q) - 0.077 0.077 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.684 0.761 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] - SLICE_X64Y62 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X53Y48 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X53Y48 FDRE (Prop_DFF_SLICEM_C_Q) + 0.078 0.078 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.515 0.593 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0] + SLICE_X54Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- max delay 8.000 8.000 - SLICE_X64Y62 FDRE (Setup_HFF2_SLICEM_C_D) - 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + SLICE_X54Y48 FDRE (Setup_HFF2_SLICEM_C_D) + 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- required time 8.025 - arrival time -0.761 + arrival time -0.593 ------------------------------------------------------------------- - slack 7.264 + slack 7.432 -Slack (MET) : 7.377ns (required time - arrival time) +Slack (MET) : 7.511ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: xxv_ethernet_0_tx_clk_out_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (MaxDelay Path 8.000ns) + Data Path Delay: 0.514ns (logic 0.079ns (15.370%) route 0.435ns (84.630%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 8.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X62Y63 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X62Y63 FDRE (Prop_DFF_SLICEL_C_Q) + 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.435 0.514 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X62Y63 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + max delay 8.000 8.000 + SLICE_X62Y63 FDRE (Setup_HFF2_SLICEL_C_D) + 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + required time 8.025 + arrival time -0.514 + ------------------------------------------------------------------- + slack 7.511 + +Slack (MET) : 7.556ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: xxv_ethernet_0_tx_clk_out_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (MaxDelay Path 8.000ns) + Data Path Delay: 0.469ns (logic 0.081ns (17.271%) route 0.388ns (82.729%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 8.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X62Y63 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X62Y63 FDRE (Prop_DFF2_SLICEL_C_Q) + 0.081 0.081 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.388 0.469 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X64Y63 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 8.000 8.000 + SLICE_X64Y63 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 8.025 + arrival time -0.469 + ------------------------------------------------------------------- + slack 7.556 + +Slack (MET) : 7.577ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D @@ -5821,59 +5782,119 @@ Slack (MET) : 7.377ns (required time - arrival time) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.648ns (logic 0.079ns (12.191%) route 0.569ns (87.809%)) + Data Path Delay: 0.448ns (logic 0.079ns (17.634%) route 0.369ns (82.366%)) Logic Levels: 0 Timing Exception: MaxDelay Path 8.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X62Y66 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C - SLICE_X62Y66 FDRE (Prop_HFF_SLICEL_C_Q) + SLICE_X58Y65 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X58Y65 FDRE (Prop_HFF_SLICEL_C_Q) 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.569 0.648 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] - SLICE_X62Y66 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + net (fo=1, routed) 0.369 0.448 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X58Y65 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- max delay 8.000 8.000 - SLICE_X62Y66 FDRE (Setup_DFF2_SLICEL_C_D) + SLICE_X58Y65 FDRE (Setup_DFF2_SLICEL_C_D) 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- required time 8.025 - arrival time -0.648 + arrival time -0.448 ------------------------------------------------------------------- - slack 7.377 + slack 7.577 -Slack (MET) : 7.559ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C +Slack (MET) : 7.598ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.466ns (logic 0.076ns (16.309%) route 0.390ns (83.691%)) + Data Path Delay: 0.427ns (logic 0.077ns (18.033%) route 0.350ns (81.967%)) Logic Levels: 0 Timing Exception: MaxDelay Path 8.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X53Y53 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C - SLICE_X53Y53 FDRE (Prop_EFF_SLICEM_C_Q) - 0.076 0.076 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.390 0.466 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3] - SLICE_X53Y53 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X63Y66 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X63Y66 FDRE (Prop_AFF_SLICEM_C_Q) + 0.077 0.077 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.350 0.427 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X63Y66 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- max delay 8.000 8.000 - SLICE_X53Y53 FDRE (Setup_DFF2_SLICEM_C_D) - 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + SLICE_X63Y66 FDRE (Setup_GFF2_SLICEM_C_D) + 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- required time 8.025 - arrival time -0.466 + arrival time -0.427 ------------------------------------------------------------------- - slack 7.559 + slack 7.598 -Slack (MET) : 7.559ns (required time - arrival time) +Slack (MET) : 7.647ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: xxv_ethernet_0_tx_clk_out_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (MaxDelay Path 8.000ns) + Data Path Delay: 0.378ns (logic 0.076ns (20.106%) route 0.302ns (79.894%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 8.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X54Y47 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X54Y47 FDRE (Prop_EFF_SLICEM_C_Q) + 0.076 0.076 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.302 0.378 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3] + SLICE_X54Y47 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + max delay 8.000 8.000 + SLICE_X54Y47 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + required time 8.025 + arrival time -0.378 + ------------------------------------------------------------------- + slack 7.647 + +Slack (MET) : 7.648ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: xxv_ethernet_0_tx_clk_out_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (MaxDelay Path 8.000ns) + Data Path Delay: 0.377ns (logic 0.079ns (20.955%) route 0.298ns (79.045%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 8.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X53Y57 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + SLICE_X53Y57 FDRE (Prop_HFF_SLICEM_C_Q) + 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.298 0.377 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2] + SLICE_X53Y57 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + max delay 8.000 8.000 + SLICE_X53Y57 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + required time 8.025 + arrival time -0.377 + ------------------------------------------------------------------- + slack 7.648 + +Slack (MET) : 7.649ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D @@ -5881,122 +5902,32 @@ Slack (MET) : 7.559ns (required time - arrival time) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.466ns (logic 0.076ns (16.309%) route 0.390ns (83.691%)) + Data Path Delay: 0.376ns (logic 0.079ns (21.011%) route 0.297ns (78.989%)) Logic Levels: 0 Timing Exception: MaxDelay Path 8.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X63Y67 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C - SLICE_X63Y67 FDRE (Prop_EFF_SLICEM_C_Q) - 0.076 0.076 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.390 0.466 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] - SLICE_X63Y67 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X58Y66 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X58Y66 FDRE (Prop_EFF_SLICEL_C_Q) + 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.297 0.376 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X58Y66 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- max delay 8.000 8.000 - SLICE_X63Y67 FDRE (Setup_DFF2_SLICEM_C_D) + SLICE_X58Y66 FDRE (Setup_DFF2_SLICEL_C_D) 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- required time 8.025 - arrival time -0.466 + arrival time -0.376 ------------------------------------------------------------------- - slack 7.559 - -Slack (MET) : 7.588ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: xxv_ethernet_0_tx_clk_out_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.437ns (logic 0.080ns (18.307%) route 0.357ns (81.693%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 8.000ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X62Y66 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C - SLICE_X62Y66 FDRE (Prop_HFF2_SLICEL_C_Q) - 0.080 0.080 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.357 0.437 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] - SLICE_X61Y66 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - ------------------------------------------------------------------- ------------------- - - max delay 8.000 8.000 - SLICE_X61Y66 FDRE (Setup_DFF2_SLICEM_C_D) - 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] - ------------------------------------------------------------------- - required time 8.025 - arrival time -0.437 - ------------------------------------------------------------------- - slack 7.588 - -Slack (MET) : 7.610ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: xxv_ethernet_0_tx_clk_out_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.415ns (logic 0.079ns (19.036%) route 0.336ns (80.964%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 8.000ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X52Y56 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C - SLICE_X52Y56 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.336 0.415 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0] - SLICE_X52Y56 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D - ------------------------------------------------------------------- ------------------- - - max delay 8.000 8.000 - SLICE_X52Y56 FDRE (Setup_HFF2_SLICEL_C_D) - 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] - ------------------------------------------------------------------- - required time 8.025 - arrival time -0.415 - ------------------------------------------------------------------- - slack 7.610 - -Slack (MET) : 7.641ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: xxv_ethernet_0_tx_clk_out_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.384ns (logic 0.081ns (21.094%) route 0.303ns (78.906%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 8.000ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X52Y48 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C - SLICE_X52Y48 FDRE (Prop_DFF2_SLICEL_C_Q) - 0.081 0.081 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.303 0.384 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1] - SLICE_X52Y48 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - ------------------------------------------------------------------- ------------------- - - max delay 8.000 8.000 - SLICE_X52Y48 FDRE (Setup_HFF2_SLICEL_C_D) - 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] - ------------------------------------------------------------------- - required time 8.025 - arrival time -0.384 - ------------------------------------------------------------------- - slack 7.641 + slack 7.649 Slack (MET) : 7.671ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Setup (Max at Slow Process Corner) @@ -6007,81 +5938,51 @@ Slack (MET) : 7.671ns (required time - arrival time) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X52Y56 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C - SLICE_X52Y56 FDRE (Prop_CFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.275 0.354 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2] - SLICE_X54Y56 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + SLICE_X62Y63 0.000 0.000 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + SLICE_X62Y63 FDRE (Prop_CFF_SLICEL_C_Q) + 0.079 0.079 r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.275 0.354 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X64Y63 FDRE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- max delay 8.000 8.000 - SLICE_X54Y56 FDRE (Setup_HFF2_SLICEM_C_D) - 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + SLICE_X64Y63 FDRE (Setup_HFF2_SLICEM_C_D) + 0.025 8.025 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- required time 8.025 arrival time -0.354 ------------------------------------------------------------------- slack 7.671 -Slack (MET) : 7.689ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C +Slack (MET) : 7.673ns (required time - arrival time) + Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: xxv_ethernet_0_tx_clk_out_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.336ns (logic 0.079ns (23.512%) route 0.257ns (76.488%)) + Data Path Delay: 0.352ns (logic 0.078ns (22.159%) route 0.274ns (77.841%)) Logic Levels: 0 Timing Exception: MaxDelay Path 8.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X52Y48 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C - SLICE_X52Y48 FDRE (Prop_DFF_SLICEL_C_Q) - 0.079 0.079 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.257 0.336 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0] - SLICE_X53Y47 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + SLICE_X53Y58 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X53Y58 FDRE (Prop_BFF_SLICEM_C_Q) + 0.078 0.078 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.274 0.352 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0] + SLICE_X53Y54 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- max delay 8.000 8.000 - SLICE_X53Y47 FDRE (Setup_HFF2_SLICEM_C_D) - 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + SLICE_X53Y54 FDRE (Setup_DFF2_SLICEM_C_D) + 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- required time 8.025 - arrival time -0.336 + arrival time -0.352 ------------------------------------------------------------------- - slack 7.689 - -Slack (MET) : 7.689ns (required time - arrival time) - Source: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - (rising edge-triggered cell FDRE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: xxv_ethernet_0_tx_clk_out_0 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 8.000ns (MaxDelay Path 8.000ns) - Data Path Delay: 0.336ns (logic 0.081ns (24.107%) route 0.255ns (75.893%)) - Logic Levels: 0 - Timing Exception: MaxDelay Path 8.000ns -datapath_only - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - SLICE_X52Y56 0.000 0.000 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C - SLICE_X52Y56 FDRE (Prop_DFF2_SLICEL_C_Q) - 0.081 0.081 r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.255 0.336 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1] - SLICE_X53Y55 FDRE r pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D - ------------------------------------------------------------------- ------------------- - - max delay 8.000 8.000 - SLICE_X53Y55 FDRE (Setup_HFF2_SLICEM_C_D) - 0.025 8.025 pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_ASYNC_FIFO.I_ASYNC_FIFO/I_ASYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] - ------------------------------------------------------------------- - required time 8.025 - arrival time -0.336 - ------------------------------------------------------------------- - slack 7.689 + slack 7.673 @@ -6092,122 +5993,14 @@ Path Group: **async_default** From Clock: Net To Clock: Net -Setup : 0 Failing Endpoints, Worst Slack 5.132ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.104ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 5.152ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.114ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 5.132ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg/PRE - (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 1.095ns (logic 0.081ns (7.397%) route 1.014ns (92.603%)) - Logic Levels: 0 - Clock Path Skew: -0.061ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.774ns = ( 8.174 - 6.400 ) - Source Clock Delay (SCD): 1.981ns - Clock Pessimism Removal (CPR): 0.146ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.738ns (routing 0.401ns, distribution 1.337ns) - Clock Net Delay (Destination): 1.561ns (routing 0.362ns, distribution 1.199ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.738 1.981 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk - SLICE_X65Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y90 FDPE (Prop_AFF2_SLICEL_C_Q) - 0.081 2.062 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q - net (fo=9, routed) 1.014 3.076 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_wr_reg2 - SLICE_X64Y86 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg/PRE - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.561 8.174 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk - SLICE_X64Y86 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg/C - clock pessimism 0.146 8.320 - clock uncertainty -0.046 8.274 - SLICE_X64Y86 FDPE (Recov_AFF2_SLICEM_C_PRE) - -0.066 8.208 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg - ------------------------------------------------------------------- - required time 8.208 - arrival time -3.076 - ------------------------------------------------------------------- - slack 5.132 - -Slack (MET) : 5.132ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/PRE - (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 1.095ns (logic 0.081ns (7.397%) route 1.014ns (92.603%)) - Logic Levels: 0 - Clock Path Skew: -0.061ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.774ns = ( 8.174 - 6.400 ) - Source Clock Delay (SCD): 1.981ns - Clock Pessimism Removal (CPR): 0.146ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.738ns (routing 0.401ns, distribution 1.337ns) - Clock Net Delay (Destination): 1.561ns (routing 0.362ns, distribution 1.199ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.738 1.981 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk - SLICE_X65Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y90 FDPE (Prop_AFF2_SLICEL_C_Q) - 0.081 2.062 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q - net (fo=9, routed) 1.014 3.076 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_wr_reg2 - SLICE_X64Y86 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/PRE - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.561 8.174 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk - SLICE_X64Y86 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C - clock pessimism 0.146 8.320 - clock uncertainty -0.046 8.274 - SLICE_X64Y86 FDPE (Recov_AFF_SLICEM_C_PRE) - -0.066 8.208 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg - ------------------------------------------------------------------- - required time 8.208 - arrival time -3.076 - ------------------------------------------------------------------- - slack 5.132 - -Slack (MET) : 5.132ns (required time - arrival time) +Slack (MET) : 5.152ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d3_reg/PRE @@ -6215,18 +6008,18 @@ Slack (MET) : 5.132ns (required time - arrival time) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 1.095ns (logic 0.081ns (7.397%) route 1.014ns (92.603%)) + Data Path Delay: 1.063ns (logic 0.081ns (7.620%) route 0.982ns (92.380%)) Logic Levels: 0 - Clock Path Skew: -0.061ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.774ns = ( 8.174 - 6.400 ) - Source Clock Delay (SCD): 1.981ns + Clock Path Skew: -0.073ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.751ns = ( 8.151 - 6.400 ) + Source Clock Delay (SCD): 1.970ns Clock Pessimism Removal (CPR): 0.146ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.738ns (routing 0.401ns, distribution 1.337ns) - Clock Net Delay (Destination): 1.561ns (routing 0.362ns, distribution 1.199ns) + Clock Net Delay (Source): 1.727ns (routing 0.401ns, distribution 1.326ns) + Clock Net Delay (Destination): 1.538ns (routing 0.362ns, distribution 1.176ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -6235,13 +6028,13 @@ Slack (MET) : 5.132ns (required time - arrival time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.738 1.981 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.727 1.970 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk SLICE_X65Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y90 FDPE (Prop_AFF2_SLICEL_C_Q) - 0.081 2.062 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q - net (fo=9, routed) 1.014 3.076 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_wr_reg2 - SLICE_X64Y86 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d3_reg/PRE + 0.081 2.051 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q + net (fo=9, routed) 0.982 3.033 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_wr_reg2 + SLICE_X65Y89 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d3_reg/PRE ------------------------------------------------------------------- ------------------- (clock Net rise edge) 6.400 6.400 r @@ -6249,343 +6042,19 @@ Slack (MET) : 5.132ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.561 8.174 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk - SLICE_X64Y86 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d3_reg/C - clock pessimism 0.146 8.320 - clock uncertainty -0.046 8.274 - SLICE_X64Y86 FDPE (Recov_DFF2_SLICEM_C_PRE) - -0.066 8.208 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d3_reg + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.538 8.151 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk + SLICE_X65Y89 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d3_reg/C + clock pessimism 0.146 8.297 + clock uncertainty -0.046 8.251 + SLICE_X65Y89 FDPE (Recov_DFF2_SLICEL_C_PRE) + -0.066 8.185 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d3_reg ------------------------------------------------------------------- - required time 8.208 - arrival time -3.076 + required time 8.185 + arrival time -3.033 ------------------------------------------------------------------- - slack 5.132 + slack 5.152 -Slack (MET) : 5.132ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/PRE - (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 1.095ns (logic 0.081ns (7.397%) route 1.014ns (92.603%)) - Logic Levels: 0 - Clock Path Skew: -0.061ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.774ns = ( 8.174 - 6.400 ) - Source Clock Delay (SCD): 1.981ns - Clock Pessimism Removal (CPR): 0.146ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.738ns (routing 0.401ns, distribution 1.337ns) - Clock Net Delay (Destination): 1.561ns (routing 0.362ns, distribution 1.199ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.738 1.981 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk - SLICE_X65Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y90 FDPE (Prop_AFF2_SLICEL_C_Q) - 0.081 2.062 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q - net (fo=9, routed) 1.014 3.076 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_wr_reg2 - SLICE_X64Y86 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/PRE - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.561 8.174 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk - SLICE_X64Y86 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C - clock pessimism 0.146 8.320 - clock uncertainty -0.046 8.274 - SLICE_X64Y86 FDPE (Recov_CFF2_SLICEM_C_PRE) - -0.066 8.208 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg - ------------------------------------------------------------------- - required time 8.208 - arrival time -3.076 - ------------------------------------------------------------------- - slack 5.132 - -Slack (MET) : 5.132ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_reg/PRE - (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 1.095ns (logic 0.081ns (7.397%) route 1.014ns (92.603%)) - Logic Levels: 0 - Clock Path Skew: -0.061ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.774ns = ( 8.174 - 6.400 ) - Source Clock Delay (SCD): 1.981ns - Clock Pessimism Removal (CPR): 0.146ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.738ns (routing 0.401ns, distribution 1.337ns) - Clock Net Delay (Destination): 1.561ns (routing 0.362ns, distribution 1.199ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.738 1.981 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk - SLICE_X65Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y90 FDPE (Prop_AFF2_SLICEL_C_Q) - 0.081 2.062 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q - net (fo=9, routed) 1.014 3.076 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_wr_reg2 - SLICE_X64Y86 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_reg/PRE - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.561 8.174 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk - SLICE_X64Y86 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_reg/C - clock pessimism 0.146 8.320 - clock uncertainty -0.046 8.274 - SLICE_X64Y86 FDPE (Recov_BFF2_SLICEM_C_PRE) - -0.066 8.208 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_reg - ------------------------------------------------------------------- - required time 8.208 - arrival time -3.076 - ------------------------------------------------------------------- - slack 5.132 - -Slack (MET) : 5.134ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0]/CLR - (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 1.092ns (logic 0.081ns (7.418%) route 1.011ns (92.582%)) - Logic Levels: 0 - Clock Path Skew: -0.062ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.773ns = ( 8.173 - 6.400 ) - Source Clock Delay (SCD): 1.981ns - Clock Pessimism Removal (CPR): 0.146ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.738ns (routing 0.401ns, distribution 1.337ns) - Clock Net Delay (Destination): 1.560ns (routing 0.362ns, distribution 1.198ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.738 1.981 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk - SLICE_X65Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y90 FDPE (Prop_AFF2_SLICEL_C_Q) - 0.081 2.062 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q - net (fo=9, routed) 1.011 3.073 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_wr_reg2 - SLICE_X64Y86 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.560 8.173 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk - SLICE_X64Y86 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0]/C - clock pessimism 0.146 8.319 - clock uncertainty -0.046 8.273 - SLICE_X64Y86 FDCE (Recov_EFF_SLICEM_C_CLR) - -0.066 8.207 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0] - ------------------------------------------------------------------- - required time 8.207 - arrival time -3.073 - ------------------------------------------------------------------- - slack 5.134 - -Slack (MET) : 5.134ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1]/CLR - (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 1.092ns (logic 0.081ns (7.418%) route 1.011ns (92.582%)) - Logic Levels: 0 - Clock Path Skew: -0.062ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.773ns = ( 8.173 - 6.400 ) - Source Clock Delay (SCD): 1.981ns - Clock Pessimism Removal (CPR): 0.146ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.738ns (routing 0.401ns, distribution 1.337ns) - Clock Net Delay (Destination): 1.560ns (routing 0.362ns, distribution 1.198ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.738 1.981 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk - SLICE_X65Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y90 FDPE (Prop_AFF2_SLICEL_C_Q) - 0.081 2.062 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q - net (fo=9, routed) 1.011 3.073 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_wr_reg2 - SLICE_X64Y86 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.560 8.173 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk - SLICE_X64Y86 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1]/C - clock pessimism 0.146 8.319 - clock uncertainty -0.046 8.273 - SLICE_X64Y86 FDCE (Recov_EFF2_SLICEM_C_CLR) - -0.066 8.207 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1] - ------------------------------------------------------------------- - required time 8.207 - arrival time -3.073 - ------------------------------------------------------------------- - slack 5.134 - -Slack (MET) : 5.134ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2]/CLR - (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 1.092ns (logic 0.081ns (7.418%) route 1.011ns (92.582%)) - Logic Levels: 0 - Clock Path Skew: -0.062ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.773ns = ( 8.173 - 6.400 ) - Source Clock Delay (SCD): 1.981ns - Clock Pessimism Removal (CPR): 0.146ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.738ns (routing 0.401ns, distribution 1.337ns) - Clock Net Delay (Destination): 1.560ns (routing 0.362ns, distribution 1.198ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.738 1.981 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk - SLICE_X65Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y90 FDPE (Prop_AFF2_SLICEL_C_Q) - 0.081 2.062 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q - net (fo=9, routed) 1.011 3.073 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_wr_reg2 - SLICE_X64Y86 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.560 8.173 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk - SLICE_X64Y86 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2]/C - clock pessimism 0.146 8.319 - clock uncertainty -0.046 8.273 - SLICE_X64Y86 FDCE (Recov_FFF_SLICEM_C_CLR) - -0.066 8.207 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2] - ------------------------------------------------------------------- - required time 8.207 - arrival time -3.073 - ------------------------------------------------------------------- - slack 5.134 - -Slack (MET) : 5.134ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3]/CLR - (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 1.092ns (logic 0.081ns (7.418%) route 1.011ns (92.582%)) - Logic Levels: 0 - Clock Path Skew: -0.062ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.773ns = ( 8.173 - 6.400 ) - Source Clock Delay (SCD): 1.981ns - Clock Pessimism Removal (CPR): 0.146ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.738ns (routing 0.401ns, distribution 1.337ns) - Clock Net Delay (Destination): 1.560ns (routing 0.362ns, distribution 1.198ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.738 1.981 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk - SLICE_X65Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y90 FDPE (Prop_AFF2_SLICEL_C_Q) - 0.081 2.062 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q - net (fo=9, routed) 1.011 3.073 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_wr_reg2 - SLICE_X64Y86 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.560 8.173 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk - SLICE_X64Y86 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3]/C - clock pessimism 0.146 8.319 - clock uncertainty -0.046 8.273 - SLICE_X64Y86 FDCE (Recov_FFF2_SLICEM_C_CLR) - -0.066 8.207 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3] - ------------------------------------------------------------------- - required time 8.207 - arrival time -3.073 - ------------------------------------------------------------------- - slack 5.134 - -Slack (MET) : 5.233ns (required time - arrival time) +Slack (MET) : 5.258ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR @@ -6593,18 +6062,18 @@ Slack (MET) : 5.233ns (required time - arrival time) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) - Data Path Delay: 1.006ns (logic 0.077ns (7.654%) route 0.929ns (92.346%)) + Data Path Delay: 0.963ns (logic 0.081ns (8.411%) route 0.882ns (91.589%)) Logic Levels: 0 - Clock Path Skew: -0.048ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.771ns = ( 8.171 - 6.400 ) - Source Clock Delay (SCD): 2.019ns - Clock Pessimism Removal (CPR): 0.200ns + Clock Path Skew: -0.067ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.770ns = ( 8.170 - 6.400 ) + Source Clock Delay (SCD): 1.983ns + Clock Pessimism Removal (CPR): 0.146ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.776ns (routing 0.401ns, distribution 1.375ns) - Clock Net Delay (Destination): 1.558ns (routing 0.362ns, distribution 1.196ns) + Clock Net Delay (Source): 1.740ns (routing 0.401ns, distribution 1.339ns) + Clock Net Delay (Destination): 1.557ns (routing 0.362ns, distribution 1.195ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -6613,13 +6082,13 @@ Slack (MET) : 5.233ns (required time - arrival time) net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.776 2.019 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk - SLICE_X64Y86 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.740 1.983 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk + SLICE_X65Y91 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y86 FDPE (Prop_CFF2_SLICEM_C_Q) - 0.077 2.096 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.929 3.025 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X65Y85 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR + SLICE_X65Y91 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.064 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.882 2.946 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y85 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock Net rise edge) 6.400 6.400 r @@ -6627,17 +6096,449 @@ Slack (MET) : 5.233ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.558 8.171 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk - SLICE_X65Y85 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/C - clock pessimism 0.200 8.371 - clock uncertainty -0.046 8.324 - SLICE_X65Y85 FDCE (Recov_CFF2_SLICEL_C_CLR) - -0.066 8.258 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.557 8.170 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y85 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/C + clock pessimism 0.146 8.316 + clock uncertainty -0.046 8.270 + SLICE_X64Y85 FDCE (Recov_CFF2_SLICEM_C_CLR) + -0.066 8.204 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0] ------------------------------------------------------------------- - required time 8.258 - arrival time -3.025 + required time 8.204 + arrival time -2.946 ------------------------------------------------------------------- - slack 5.233 + slack 5.258 + +Slack (MET) : 5.258ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE + (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) + Data Path Delay: 0.963ns (logic 0.081ns (8.411%) route 0.882ns (91.589%)) + Logic Levels: 0 + Clock Path Skew: -0.067ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.770ns = ( 8.170 - 6.400 ) + Source Clock Delay (SCD): 1.983ns + Clock Pessimism Removal (CPR): 0.146ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.740ns (routing 0.401ns, distribution 1.339ns) + Clock Net Delay (Destination): 1.557ns (routing 0.362ns, distribution 1.195ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.740 1.983 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk + SLICE_X65Y91 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y91 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.064 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.882 2.946 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y85 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.557 8.170 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y85 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/C + clock pessimism 0.146 8.316 + clock uncertainty -0.046 8.270 + SLICE_X64Y85 FDPE (Recov_BFF2_SLICEM_C_PRE) + -0.066 8.204 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1] + ------------------------------------------------------------------- + required time 8.204 + arrival time -2.946 + ------------------------------------------------------------------- + slack 5.258 + +Slack (MET) : 5.258ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/CLR + (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) + Data Path Delay: 0.963ns (logic 0.081ns (8.411%) route 0.882ns (91.589%)) + Logic Levels: 0 + Clock Path Skew: -0.067ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.770ns = ( 8.170 - 6.400 ) + Source Clock Delay (SCD): 1.983ns + Clock Pessimism Removal (CPR): 0.146ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.740ns (routing 0.401ns, distribution 1.339ns) + Clock Net Delay (Destination): 1.557ns (routing 0.362ns, distribution 1.195ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.740 1.983 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk + SLICE_X65Y91 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y91 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.064 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.882 2.946 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y85 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.557 8.170 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y85 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/C + clock pessimism 0.146 8.316 + clock uncertainty -0.046 8.270 + SLICE_X64Y85 FDCE (Recov_DFF_SLICEM_C_CLR) + -0.066 8.204 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2] + ------------------------------------------------------------------- + required time 8.204 + arrival time -2.946 + ------------------------------------------------------------------- + slack 5.258 + +Slack (MET) : 5.258ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/CLR + (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) + Data Path Delay: 0.963ns (logic 0.081ns (8.411%) route 0.882ns (91.589%)) + Logic Levels: 0 + Clock Path Skew: -0.067ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.770ns = ( 8.170 - 6.400 ) + Source Clock Delay (SCD): 1.983ns + Clock Pessimism Removal (CPR): 0.146ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.740ns (routing 0.401ns, distribution 1.339ns) + Clock Net Delay (Destination): 1.557ns (routing 0.362ns, distribution 1.195ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.740 1.983 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk + SLICE_X65Y91 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y91 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.064 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.882 2.946 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y85 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.557 8.170 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y85 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/C + clock pessimism 0.146 8.316 + clock uncertainty -0.046 8.270 + SLICE_X64Y85 FDCE (Recov_DFF2_SLICEM_C_CLR) + -0.066 8.204 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3] + ------------------------------------------------------------------- + required time 8.204 + arrival time -2.946 + ------------------------------------------------------------------- + slack 5.258 + +Slack (MET) : 5.260ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE + (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) + Data Path Delay: 0.960ns (logic 0.081ns (8.437%) route 0.879ns (91.562%)) + Logic Levels: 0 + Clock Path Skew: -0.068ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.769ns = ( 8.169 - 6.400 ) + Source Clock Delay (SCD): 1.983ns + Clock Pessimism Removal (CPR): 0.146ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.740ns (routing 0.401ns, distribution 1.339ns) + Clock Net Delay (Destination): 1.556ns (routing 0.362ns, distribution 1.194ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.740 1.983 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk + SLICE_X65Y91 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y91 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.064 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.879 2.943 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y85 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.556 8.169 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y85 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/C + clock pessimism 0.146 8.315 + clock uncertainty -0.046 8.269 + SLICE_X64Y85 FDPE (Recov_EFF_SLICEM_C_PRE) + -0.066 8.203 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0] + ------------------------------------------------------------------- + required time 8.203 + arrival time -2.943 + ------------------------------------------------------------------- + slack 5.260 + +Slack (MET) : 5.260ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR + (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) + Data Path Delay: 0.960ns (logic 0.081ns (8.437%) route 0.879ns (91.562%)) + Logic Levels: 0 + Clock Path Skew: -0.068ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.769ns = ( 8.169 - 6.400 ) + Source Clock Delay (SCD): 1.983ns + Clock Pessimism Removal (CPR): 0.146ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.740ns (routing 0.401ns, distribution 1.339ns) + Clock Net Delay (Destination): 1.556ns (routing 0.362ns, distribution 1.194ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.740 1.983 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk + SLICE_X65Y91 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y91 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.064 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.879 2.943 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y85 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.556 8.169 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y85 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/C + clock pessimism 0.146 8.315 + clock uncertainty -0.046 8.269 + SLICE_X64Y85 FDCE (Recov_EFF2_SLICEM_C_CLR) + -0.066 8.203 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1] + ------------------------------------------------------------------- + required time 8.203 + arrival time -2.943 + ------------------------------------------------------------------- + slack 5.260 + +Slack (MET) : 5.260ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR + (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) + Data Path Delay: 0.960ns (logic 0.081ns (8.437%) route 0.879ns (91.562%)) + Logic Levels: 0 + Clock Path Skew: -0.068ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.769ns = ( 8.169 - 6.400 ) + Source Clock Delay (SCD): 1.983ns + Clock Pessimism Removal (CPR): 0.146ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.740ns (routing 0.401ns, distribution 1.339ns) + Clock Net Delay (Destination): 1.556ns (routing 0.362ns, distribution 1.194ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.740 1.983 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk + SLICE_X65Y91 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y91 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.064 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.879 2.943 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y85 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.556 8.169 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y85 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/C + clock pessimism 0.146 8.315 + clock uncertainty -0.046 8.269 + SLICE_X64Y85 FDCE (Recov_FFF_SLICEM_C_CLR) + -0.066 8.203 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2] + ------------------------------------------------------------------- + required time 8.203 + arrival time -2.943 + ------------------------------------------------------------------- + slack 5.260 + +Slack (MET) : 5.260ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR + (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) + Data Path Delay: 0.960ns (logic 0.081ns (8.437%) route 0.879ns (91.562%)) + Logic Levels: 0 + Clock Path Skew: -0.068ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.769ns = ( 8.169 - 6.400 ) + Source Clock Delay (SCD): 1.983ns + Clock Pessimism Removal (CPR): 0.146ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.740ns (routing 0.401ns, distribution 1.339ns) + Clock Net Delay (Destination): 1.556ns (routing 0.362ns, distribution 1.194ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.740 1.983 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk + SLICE_X65Y91 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y91 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.064 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.879 2.943 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y85 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.556 8.169 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y85 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/C + clock pessimism 0.146 8.315 + clock uncertainty -0.046 8.269 + SLICE_X64Y85 FDCE (Recov_FFF2_SLICEM_C_CLR) + -0.066 8.203 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3] + ------------------------------------------------------------------- + required time 8.203 + arrival time -2.943 + ------------------------------------------------------------------- + slack 5.260 + +Slack (MET) : 5.260ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR + (recovery check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 6.400ns (Net rise@6.400ns - Net rise@0.000ns) + Data Path Delay: 0.960ns (logic 0.081ns (8.437%) route 0.879ns (91.562%)) + Logic Levels: 0 + Clock Path Skew: -0.068ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.769ns = ( 8.169 - 6.400 ) + Source Clock Delay (SCD): 1.983ns + Clock Pessimism Removal (CPR): 0.146ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.740ns (routing 0.401ns, distribution 1.339ns) + Clock Net Delay (Destination): 1.556ns (routing 0.362ns, distribution 1.194ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.740 1.983 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk + SLICE_X65Y91 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y91 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.064 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.879 2.943 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y85 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.556 8.169 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y85 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/C + clock pessimism 0.146 8.315 + clock uncertainty -0.046 8.269 + SLICE_X64Y85 FDCE (Recov_GFF_SLICEM_C_CLR) + -0.066 8.203 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0] + ------------------------------------------------------------------- + required time 8.203 + arrival time -2.943 + ------------------------------------------------------------------- + slack 5.260 @@ -6645,22 +6546,120 @@ Slack (MET) : 5.233ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.104ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C +Slack (MET) : 0.114ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR (removal check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.136ns (logic 0.041ns (30.147%) route 0.095ns (69.853%)) + Data Path Delay: 0.150ns (logic 0.040ns (26.667%) route 0.110ns (73.333%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.180ns + Source Clock Delay (SCD): 1.035ns + Clock Pessimism Removal (CPR): 0.089ns + Clock Net Delay (Source): 0.888ns (routing 0.219ns, distribution 0.669ns) + Clock Net Delay (Destination): 1.012ns (routing 0.243ns, distribution 0.769ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.074 0.074 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.073 0.147 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 0.888 1.035 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X66Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X66Y90 FDPE (Prop_AFF2_SLICEL_C_Q) + 0.040 1.075 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q + net (fo=3, routed) 0.110 1.185 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/rst_rd_reg2 + SLICE_X66Y89 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.086 0.086 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.082 0.168 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.012 1.180 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/s_aclk + SLICE_X66Y89 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/C + clock pessimism -0.089 1.091 + SLICE_X66Y89 FDCE (Remov_EFF_SLICEL_C_CLR) + -0.020 1.071 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0] + ------------------------------------------------------------------- + required time -1.071 + arrival time 1.185 + ------------------------------------------------------------------- + slack 0.114 + +Slack (MET) : 0.114ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[1]/CLR + (removal check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) + Data Path Delay: 0.150ns (logic 0.040ns (26.667%) route 0.110ns (73.333%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.180ns + Source Clock Delay (SCD): 1.035ns + Clock Pessimism Removal (CPR): 0.089ns + Clock Net Delay (Source): 0.888ns (routing 0.219ns, distribution 0.669ns) + Clock Net Delay (Destination): 1.012ns (routing 0.243ns, distribution 0.769ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.074 0.074 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.073 0.147 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 0.888 1.035 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X66Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X66Y90 FDPE (Prop_AFF2_SLICEL_C_Q) + 0.040 1.075 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q + net (fo=3, routed) 0.110 1.185 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/rst_rd_reg2 + SLICE_X66Y89 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock Net rise edge) 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK + net (fo=3, routed) 0.086 0.086 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] + BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) + 0.082 0.168 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.012 1.180 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/s_aclk + SLICE_X66Y89 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[1]/C + clock pessimism -0.089 1.091 + SLICE_X66Y89 FDCE (Remov_EFF2_SLICEL_C_CLR) + -0.020 1.071 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[1] + ------------------------------------------------------------------- + required time -1.071 + arrival time 1.185 + ------------------------------------------------------------------- + slack 0.114 + +Slack (MET) : 0.118ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/PRE + (removal check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) + Data Path Delay: 0.150ns (logic 0.040ns (26.667%) route 0.110ns (73.333%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.270ns - Source Clock Delay (SCD): 1.123ns - Clock Pessimism Removal (CPR): 0.095ns - Clock Net Delay (Source): 0.976ns (routing 0.219ns, distribution 0.757ns) - Clock Net Delay (Destination): 1.102ns (routing 0.243ns, distribution 0.859ns) + Destination Clock Delay (DCD): 1.176ns + Source Clock Delay (SCD): 1.035ns + Clock Pessimism Removal (CPR): 0.089ns + Clock Net Delay (Source): 0.888ns (routing 0.219ns, distribution 0.669ns) + Clock Net Delay (Destination): 1.008ns (routing 0.243ns, distribution 0.765ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -6669,13 +6668,13 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.074 0.074 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.073 0.147 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 0.976 1.123 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/s_aclk - SLICE_X61Y92 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 0.888 1.035 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X66Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X61Y92 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.164 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.095 1.259 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X58Y92 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE + SLICE_X66Y90 FDPE (Prop_AFF2_SLICEL_C_Q) + 0.040 1.075 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q + net (fo=3, routed) 0.110 1.185 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/rst_rd_reg2 + SLICE_X66Y89 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/PRE ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -6683,33 +6682,33 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.086 0.086 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.082 0.168 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.102 1.270 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk - SLICE_X58Y92 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/C - clock pessimism -0.095 1.175 - SLICE_X58Y92 FDPE (Remov_EFF_SLICEL_C_PRE) - -0.020 1.155 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.008 1.176 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/s_aclk + SLICE_X66Y89 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + clock pessimism -0.089 1.087 + SLICE_X66Y89 FDPE (Remov_DFF2_SLICEL_C_PRE) + -0.020 1.067 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg ------------------------------------------------------------------- - required time -1.155 - arrival time 1.259 + required time -1.067 + arrival time 1.185 ------------------------------------------------------------------- - slack 0.104 + slack 0.118 -Slack (MET) : 0.104ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C +Slack (MET) : 0.132ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0]/CLR (removal check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.136ns (logic 0.041ns (30.147%) route 0.095ns (69.853%)) + Data Path Delay: 0.137ns (logic 0.040ns (29.197%) route 0.097ns (70.803%)) Logic Levels: 0 - Clock Path Skew: 0.052ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.270ns - Source Clock Delay (SCD): 1.123ns - Clock Pessimism Removal (CPR): 0.095ns - Clock Net Delay (Source): 0.976ns (routing 0.219ns, distribution 0.757ns) - Clock Net Delay (Destination): 1.102ns (routing 0.243ns, distribution 0.859ns) + Clock Path Skew: 0.025ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.252ns + Source Clock Delay (SCD): 1.100ns + Clock Pessimism Removal (CPR): 0.127ns + Clock Net Delay (Source): 0.953ns (routing 0.219ns, distribution 0.734ns) + Clock Net Delay (Destination): 1.084ns (routing 0.243ns, distribution 0.841ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -6718,13 +6717,13 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.074 0.074 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.073 0.147 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 0.976 1.123 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/s_aclk - SLICE_X61Y92 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 0.953 1.100 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X65Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X61Y92 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.164 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.095 1.259 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X58Y92 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR + SLICE_X65Y90 FDPE (Prop_AFF2_SLICEL_C_Q) + 0.040 1.140 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q + net (fo=9, routed) 0.097 1.237 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_wr_reg2 + SLICE_X65Y91 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -6732,33 +6731,33 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.086 0.086 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.082 0.168 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.102 1.270 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk - SLICE_X58Y92 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/C - clock pessimism -0.095 1.175 - SLICE_X58Y92 FDCE (Remov_EFF2_SLICEL_C_CLR) - -0.020 1.155 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.084 1.252 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk + SLICE_X65Y91 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0]/C + clock pessimism -0.127 1.125 + SLICE_X65Y91 FDCE (Remov_EFF_SLICEL_C_CLR) + -0.020 1.105 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0] ------------------------------------------------------------------- - required time -1.155 - arrival time 1.259 + required time -1.105 + arrival time 1.237 ------------------------------------------------------------------- - slack 0.104 + slack 0.132 -Slack (MET) : 0.104ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C +Slack (MET) : 0.132ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1]/CLR (removal check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.136ns (logic 0.041ns (30.147%) route 0.095ns (69.853%)) + Data Path Delay: 0.137ns (logic 0.040ns (29.197%) route 0.097ns (70.803%)) Logic Levels: 0 - Clock Path Skew: 0.052ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.270ns - Source Clock Delay (SCD): 1.123ns - Clock Pessimism Removal (CPR): 0.095ns - Clock Net Delay (Source): 0.976ns (routing 0.219ns, distribution 0.757ns) - Clock Net Delay (Destination): 1.102ns (routing 0.243ns, distribution 0.859ns) + Clock Path Skew: 0.025ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.252ns + Source Clock Delay (SCD): 1.100ns + Clock Pessimism Removal (CPR): 0.127ns + Clock Net Delay (Source): 0.953ns (routing 0.219ns, distribution 0.734ns) + Clock Net Delay (Destination): 1.084ns (routing 0.243ns, distribution 0.841ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -6767,13 +6766,13 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.074 0.074 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.073 0.147 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 0.976 1.123 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/s_aclk - SLICE_X61Y92 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 0.953 1.100 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X65Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X61Y92 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.164 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.095 1.259 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X58Y92 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR + SLICE_X65Y90 FDPE (Prop_AFF2_SLICEL_C_Q) + 0.040 1.140 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q + net (fo=9, routed) 0.097 1.237 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_wr_reg2 + SLICE_X65Y91 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -6781,33 +6780,33 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.086 0.086 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.082 0.168 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.102 1.270 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk - SLICE_X58Y92 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/C - clock pessimism -0.095 1.175 - SLICE_X58Y92 FDCE (Remov_FFF_SLICEL_C_CLR) - -0.020 1.155 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.084 1.252 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk + SLICE_X65Y91 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1]/C + clock pessimism -0.127 1.125 + SLICE_X65Y91 FDCE (Remov_EFF2_SLICEL_C_CLR) + -0.020 1.105 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1] ------------------------------------------------------------------- - required time -1.155 - arrival time 1.259 + required time -1.105 + arrival time 1.237 ------------------------------------------------------------------- - slack 0.104 + slack 0.132 -Slack (MET) : 0.104ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C +Slack (MET) : 0.132ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2]/CLR (removal check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.136ns (logic 0.041ns (30.147%) route 0.095ns (69.853%)) + Data Path Delay: 0.137ns (logic 0.040ns (29.197%) route 0.097ns (70.803%)) Logic Levels: 0 - Clock Path Skew: 0.052ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.270ns - Source Clock Delay (SCD): 1.123ns - Clock Pessimism Removal (CPR): 0.095ns - Clock Net Delay (Source): 0.976ns (routing 0.219ns, distribution 0.757ns) - Clock Net Delay (Destination): 1.102ns (routing 0.243ns, distribution 0.859ns) + Clock Path Skew: 0.025ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.252ns + Source Clock Delay (SCD): 1.100ns + Clock Pessimism Removal (CPR): 0.127ns + Clock Net Delay (Source): 0.953ns (routing 0.219ns, distribution 0.734ns) + Clock Net Delay (Destination): 1.084ns (routing 0.243ns, distribution 0.841ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -6816,13 +6815,13 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.074 0.074 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.073 0.147 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 0.976 1.123 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/s_aclk - SLICE_X61Y92 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 0.953 1.100 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X65Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X61Y92 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.164 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.095 1.259 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X58Y92 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR + SLICE_X65Y90 FDPE (Prop_AFF2_SLICEL_C_Q) + 0.040 1.140 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q + net (fo=9, routed) 0.097 1.237 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_wr_reg2 + SLICE_X65Y91 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -6830,33 +6829,33 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.086 0.086 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.082 0.168 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.102 1.270 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk - SLICE_X58Y92 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/C - clock pessimism -0.095 1.175 - SLICE_X58Y92 FDCE (Remov_FFF2_SLICEL_C_CLR) - -0.020 1.155 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.084 1.252 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk + SLICE_X65Y91 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2]/C + clock pessimism -0.127 1.125 + SLICE_X65Y91 FDCE (Remov_FFF_SLICEL_C_CLR) + -0.020 1.105 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2] ------------------------------------------------------------------- - required time -1.155 - arrival time 1.259 + required time -1.105 + arrival time 1.237 ------------------------------------------------------------------- - slack 0.104 + slack 0.132 -Slack (MET) : 0.104ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C +Slack (MET) : 0.132ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3]/CLR (removal check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.136ns (logic 0.041ns (30.147%) route 0.095ns (69.853%)) + Data Path Delay: 0.137ns (logic 0.040ns (29.197%) route 0.097ns (70.803%)) Logic Levels: 0 - Clock Path Skew: 0.052ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.270ns - Source Clock Delay (SCD): 1.123ns - Clock Pessimism Removal (CPR): 0.095ns - Clock Net Delay (Source): 0.976ns (routing 0.219ns, distribution 0.757ns) - Clock Net Delay (Destination): 1.102ns (routing 0.243ns, distribution 0.859ns) + Clock Path Skew: 0.025ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.252ns + Source Clock Delay (SCD): 1.100ns + Clock Pessimism Removal (CPR): 0.127ns + Clock Net Delay (Source): 0.953ns (routing 0.219ns, distribution 0.734ns) + Clock Net Delay (Destination): 1.084ns (routing 0.243ns, distribution 0.841ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -6865,13 +6864,13 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.074 0.074 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.073 0.147 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 0.976 1.123 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/s_aclk - SLICE_X61Y92 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 0.953 1.100 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X65Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X61Y92 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.164 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.095 1.259 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X58Y92 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR + SLICE_X65Y90 FDPE (Prop_AFF2_SLICEL_C_Q) + 0.040 1.140 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q + net (fo=9, routed) 0.097 1.237 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_wr_reg2 + SLICE_X65Y91 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -6879,33 +6878,33 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.086 0.086 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.082 0.168 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.102 1.270 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk - SLICE_X58Y92 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/C - clock pessimism -0.095 1.175 - SLICE_X58Y92 FDCE (Remov_GFF_SLICEL_C_CLR) - -0.020 1.155 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.084 1.252 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk + SLICE_X65Y91 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3]/C + clock pessimism -0.127 1.125 + SLICE_X65Y91 FDCE (Remov_FFF2_SLICEL_C_CLR) + -0.020 1.105 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3] ------------------------------------------------------------------- - required time -1.155 - arrival time 1.259 + required time -1.105 + arrival time 1.237 ------------------------------------------------------------------- - slack 0.104 + slack 0.132 -Slack (MET) : 0.104ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C +Slack (MET) : 0.136ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/PRE (removal check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.136ns (logic 0.041ns (30.147%) route 0.095ns (69.853%)) + Data Path Delay: 0.132ns (logic 0.039ns (29.545%) route 0.093ns (70.455%)) Logic Levels: 0 - Clock Path Skew: 0.052ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.270ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.267ns Source Clock Delay (SCD): 1.123ns - Clock Pessimism Removal (CPR): 0.095ns + Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.976ns (routing 0.219ns, distribution 0.757ns) - Clock Net Delay (Destination): 1.102ns (routing 0.243ns, distribution 0.859ns) + Clock Net Delay (Destination): 1.099ns (routing 0.243ns, distribution 0.856ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -6914,13 +6913,13 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.074 0.074 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.073 0.147 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 0.976 1.123 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/s_aclk - SLICE_X61Y92 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 0.976 1.123 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/s_aclk + SLICE_X59Y96 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X61Y92 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.164 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.095 1.259 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X58Y92 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/CLR + SLICE_X59Y96 FDPE (Prop_AFF_SLICEL_C_Q) + 0.039 1.162 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q + net (fo=3, routed) 0.093 1.255 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/out + SLICE_X59Y95 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/PRE ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -6928,33 +6927,33 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.086 0.086 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.082 0.168 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.102 1.270 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk - SLICE_X58Y92 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C - clock pessimism -0.095 1.175 - SLICE_X58Y92 FDCE (Remov_GFF2_SLICEL_C_CLR) - -0.020 1.155 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.099 1.267 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/s_aclk + SLICE_X59Y95 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/C + clock pessimism -0.128 1.139 + SLICE_X59Y95 FDPE (Remov_EFF_SLICEL_C_PRE) + -0.020 1.119 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg ------------------------------------------------------------------- - required time -1.155 - arrival time 1.259 + required time -1.119 + arrival time 1.255 ------------------------------------------------------------------- - slack 0.104 + slack 0.136 -Slack (MET) : 0.104ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C +Slack (MET) : 0.136ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/PRE (removal check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.136ns (logic 0.041ns (30.147%) route 0.095ns (69.853%)) + Data Path Delay: 0.132ns (logic 0.039ns (29.545%) route 0.093ns (70.455%)) Logic Levels: 0 - Clock Path Skew: 0.052ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.270ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.267ns Source Clock Delay (SCD): 1.123ns - Clock Pessimism Removal (CPR): 0.095ns + Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.976ns (routing 0.219ns, distribution 0.757ns) - Clock Net Delay (Destination): 1.102ns (routing 0.243ns, distribution 0.859ns) + Clock Net Delay (Destination): 1.099ns (routing 0.243ns, distribution 0.856ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -6963,13 +6962,13 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.074 0.074 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.073 0.147 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 0.976 1.123 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/s_aclk - SLICE_X61Y92 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 0.976 1.123 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/s_aclk + SLICE_X59Y96 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X61Y92 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.164 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.095 1.259 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X58Y92 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/CLR + SLICE_X59Y96 FDPE (Prop_AFF_SLICEL_C_Q) + 0.039 1.162 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q + net (fo=3, routed) 0.093 1.255 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/out + SLICE_X59Y95 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/PRE ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -6977,33 +6976,33 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.086 0.086 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.082 0.168 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.102 1.270 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk - SLICE_X58Y92 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/C - clock pessimism -0.095 1.175 - SLICE_X58Y92 FDCE (Remov_HFF_SLICEL_C_CLR) - -0.020 1.155 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.099 1.267 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/s_aclk + SLICE_X59Y95 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/C + clock pessimism -0.128 1.139 + SLICE_X59Y95 FDPE (Remov_EFF2_SLICEL_C_PRE) + -0.020 1.119 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg ------------------------------------------------------------------- - required time -1.155 - arrival time 1.259 + required time -1.119 + arrival time 1.255 ------------------------------------------------------------------- - slack 0.104 + slack 0.136 -Slack (MET) : 0.104ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C +Slack (MET) : 0.136ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg/PRE (removal check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.136ns (logic 0.041ns (30.147%) route 0.095ns (69.853%)) + Data Path Delay: 0.137ns (logic 0.040ns (29.197%) route 0.097ns (70.803%)) Logic Levels: 0 - Clock Path Skew: 0.052ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.270ns - Source Clock Delay (SCD): 1.123ns - Clock Pessimism Removal (CPR): 0.095ns - Clock Net Delay (Source): 0.976ns (routing 0.219ns, distribution 0.757ns) - Clock Net Delay (Destination): 1.102ns (routing 0.243ns, distribution 0.859ns) + Clock Path Skew: 0.021ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.248ns + Source Clock Delay (SCD): 1.100ns + Clock Pessimism Removal (CPR): 0.127ns + Clock Net Delay (Source): 0.953ns (routing 0.219ns, distribution 0.734ns) + Clock Net Delay (Destination): 1.080ns (routing 0.243ns, distribution 0.837ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7012,13 +7011,13 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.074 0.074 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.073 0.147 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 0.976 1.123 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/s_aclk - SLICE_X61Y92 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 0.953 1.100 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X65Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X61Y92 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.164 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.095 1.259 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X58Y92 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3]/CLR + SLICE_X65Y90 FDPE (Prop_AFF2_SLICEL_C_Q) + 0.040 1.140 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q + net (fo=9, routed) 0.097 1.237 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/rst_wr_reg2 + SLICE_X65Y91 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg/PRE ------------------------------------------------------------------- ------------------- (clock Net rise edge) 0.000 0.000 r @@ -7026,114 +7025,16 @@ Slack (MET) : 0.104ns (arrival time - required time) net (fo=3, routed) 0.086 0.086 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.082 0.168 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.102 1.270 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk - SLICE_X58Y92 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3]/C - clock pessimism -0.095 1.175 - SLICE_X58Y92 FDCE (Remov_HFF2_SLICEL_C_CLR) - -0.020 1.155 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3] + X2Y2 (CLOCK_ROOT) net (fo=11347, routed) 1.080 1.248 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/s_aclk + SLICE_X65Y91 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg/C + clock pessimism -0.127 1.121 + SLICE_X65Y91 FDPE (Remov_BFF2_SLICEL_C_PRE) + -0.020 1.101 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg ------------------------------------------------------------------- - required time -1.155 - arrival time 1.259 + required time -1.101 + arrival time 1.237 ------------------------------------------------------------------- - slack 0.104 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C - (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR - (removal check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.136ns (logic 0.041ns (30.147%) route 0.095ns (69.853%)) - Logic Levels: 0 - Clock Path Skew: 0.048ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.266ns - Source Clock Delay (SCD): 1.123ns - Clock Pessimism Removal (CPR): 0.095ns - Clock Net Delay (Source): 0.976ns (routing 0.219ns, distribution 0.757ns) - Clock Net Delay (Destination): 1.098ns (routing 0.243ns, distribution 0.855ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.074 0.074 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.073 0.147 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 0.976 1.123 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/s_aclk - SLICE_X61Y92 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X61Y92 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.164 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.095 1.259 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X58Y92 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.086 0.086 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.082 0.168 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.098 1.266 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk - SLICE_X58Y92 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/C - clock pessimism -0.095 1.171 - SLICE_X58Y92 FDCE (Remov_CFF2_SLICEL_C_CLR) - -0.020 1.151 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0] - ------------------------------------------------------------------- - required time -1.151 - arrival time 1.259 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C - (rising edge-triggered cell FDPE clocked by Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE - (removal check against rising-edge clock Net {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (Net rise@0.000ns - Net rise@0.000ns) - Data Path Delay: 0.136ns (logic 0.041ns (30.147%) route 0.095ns (69.853%)) - Logic Levels: 0 - Clock Path Skew: 0.048ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.266ns - Source Clock Delay (SCD): 1.123ns - Clock Pessimism Removal (CPR): 0.095ns - Clock Net Delay (Source): 0.976ns (routing 0.219ns, distribution 0.757ns) - Clock Net Delay (Destination): 1.098ns (routing 0.243ns, distribution 0.855ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.074 0.074 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.073 0.147 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 0.976 1.123 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/s_aclk - SLICE_X61Y92 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X61Y92 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.164 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.095 1.259 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X58Y92 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE - ------------------------------------------------------------------- ------------------- - - (clock Net rise edge) 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK - net (fo=3, routed) 0.086 0.086 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/rxoutclk_out[0] - BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) - 0.082 0.168 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=11334, routed) 1.098 1.266 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk - SLICE_X58Y92 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/C - clock pessimism -0.095 1.171 - SLICE_X58Y92 FDPE (Remov_BFF2_SLICEL_C_PRE) - -0.020 1.151 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1] - ------------------------------------------------------------------- - required time -1.151 - arrival time 1.259 - ------------------------------------------------------------------- - slack 0.108 + slack 0.136 @@ -7144,151 +7045,33 @@ Path Group: **async_default** From Clock: clk_pl_0 To Clock: clk_pl_0 -Setup : 0 Failing Endpoints, Worst Slack 6.418ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.138ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 6.463ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.096ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 6.418ns (required time - arrival time) - Source: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C +Slack (MET) : 6.463ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR (recovery check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 1.315ns (logic 0.205ns (15.589%) route 1.110ns (84.411%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: -0.079ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.946ns = ( 9.946 - 8.000 ) - Source Clock Delay (SCD): 2.209ns - Clock Pessimism Removal (CPR): 0.184ns - Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.235ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 2.001ns (routing 0.643ns, distribution 1.358ns) - Clock Net Delay (Destination): 1.778ns (routing 0.579ns, distribution 1.199ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_pl_0 rise edge) - 0.000 0.000 r - PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] - net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] - BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) - 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 2.001 2.209 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk - SLICE_X27Y252 FDPE r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y252 FDPE (Prop_AFF2_SLICEL_C_Q) - 0.081 2.290 f pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q - net (fo=3, routed) 0.310 2.600 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_wr_reg2 - SLICE_X26Y252 LUT3 (Prop_B6LUT_SLICEL_I2_O) - 0.124 2.724 f pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O - net (fo=34, routed) 0.800 3.524 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X24Y255 FDCE f pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock clk_pl_0 rise edge) - 8.000 8.000 r - PS8_X0Y0 PS8 0.000 8.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] - net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] - BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) - 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.778 9.946 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk - SLICE_X24Y255 FDCE r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/C - clock pessimism 0.184 10.130 - clock uncertainty -0.122 10.008 - SLICE_X24Y255 FDCE (Recov_DFF_SLICEL_C_CLR) - -0.066 9.942 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3] - ------------------------------------------------------------------- - required time 9.942 - arrival time -3.524 - ------------------------------------------------------------------- - slack 6.418 - -Slack (MET) : 6.418ns (required time - arrival time) - Source: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]/CLR - (recovery check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 1.315ns (logic 0.205ns (15.589%) route 1.110ns (84.411%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: -0.079ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.946ns = ( 9.946 - 8.000 ) - Source Clock Delay (SCD): 2.209ns - Clock Pessimism Removal (CPR): 0.184ns - Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.235ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 2.001ns (routing 0.643ns, distribution 1.358ns) - Clock Net Delay (Destination): 1.778ns (routing 0.579ns, distribution 1.199ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_pl_0 rise edge) - 0.000 0.000 r - PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] - net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] - BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) - 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 2.001 2.209 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk - SLICE_X27Y252 FDPE r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y252 FDPE (Prop_AFF2_SLICEL_C_Q) - 0.081 2.290 f pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q - net (fo=3, routed) 0.310 2.600 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_wr_reg2 - SLICE_X26Y252 LUT3 (Prop_B6LUT_SLICEL_I2_O) - 0.124 2.724 f pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O - net (fo=34, routed) 0.800 3.524 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X24Y255 FDCE f pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock clk_pl_0 rise edge) - 8.000 8.000 r - PS8_X0Y0 PS8 0.000 8.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] - net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] - BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) - 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.778 9.946 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk - SLICE_X24Y255 FDCE r pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]/C - clock pessimism 0.184 10.130 - clock uncertainty -0.122 10.008 - SLICE_X24Y255 FDCE (Recov_DFF2_SLICEL_C_CLR) - -0.066 9.942 pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4] - ------------------------------------------------------------------- - required time 9.942 - arrival time -3.524 - ------------------------------------------------------------------- - slack 6.418 - -Slack (MET) : 6.468ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C - (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/PRE - (recovery check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 1.332ns (logic 0.081ns (6.081%) route 1.251ns (93.919%)) + Data Path Delay: 1.253ns (logic 0.081ns (6.464%) route 1.172ns (93.536%)) Logic Levels: 0 - Clock Path Skew: -0.012ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.816ns = ( 9.816 - 8.000 ) - Source Clock Delay (SCD): 2.052ns - Clock Pessimism Removal (CPR): 0.224ns + Clock Path Skew: -0.096ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.881ns = ( 9.881 - 8.000 ) + Source Clock Delay (SCD): 2.158ns + Clock Pessimism Removal (CPR): 0.181ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.844ns (routing 0.643ns, distribution 1.201ns) - Clock Net Delay (Destination): 1.648ns (routing 0.579ns, distribution 1.069ns) + Clock Net Delay (Source): 1.950ns (routing 0.643ns, distribution 1.307ns) + Clock Net Delay (Destination): 1.713ns (routing 0.579ns, distribution 1.134ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7298,13 +7081,13 @@ Slack (MET) : 6.468ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.844 2.052 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/m_aclk - SLICE_X65Y88 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.950 2.158 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y88 FDPE (Prop_DFF2_SLICEL_C_Q) - 0.081 2.133 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 1.251 3.384 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X64Y84 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/PRE + SLICE_X68Y90 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.239 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 1.172 3.411 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X68Y88 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -7313,38 +7096,38 @@ Slack (MET) : 6.468ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.648 9.816 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/m_aclk - SLICE_X64Y84 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/C - clock pessimism 0.224 10.040 - clock uncertainty -0.122 9.918 - SLICE_X64Y84 FDPE (Recov_CFF2_SLICEM_C_PRE) - -0.066 9.852 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.713 9.881 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk + SLICE_X68Y88 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/C + clock pessimism 0.181 10.062 + clock uncertainty -0.122 9.940 + SLICE_X68Y88 FDCE (Recov_CFF2_SLICEL_C_CLR) + -0.066 9.874 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0] ------------------------------------------------------------------- - required time 9.852 - arrival time -3.384 + required time 9.874 + arrival time -3.411 ------------------------------------------------------------------- - slack 6.468 + slack 6.463 -Slack (MET) : 6.468ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C +Slack (MET) : 6.463ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE (recovery check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 1.332ns (logic 0.081ns (6.081%) route 1.251ns (93.919%)) + Data Path Delay: 1.253ns (logic 0.081ns (6.464%) route 1.172ns (93.536%)) Logic Levels: 0 - Clock Path Skew: -0.012ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.816ns = ( 9.816 - 8.000 ) - Source Clock Delay (SCD): 2.052ns - Clock Pessimism Removal (CPR): 0.224ns + Clock Path Skew: -0.096ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.881ns = ( 9.881 - 8.000 ) + Source Clock Delay (SCD): 2.158ns + Clock Pessimism Removal (CPR): 0.181ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.844ns (routing 0.643ns, distribution 1.201ns) - Clock Net Delay (Destination): 1.648ns (routing 0.579ns, distribution 1.069ns) + Clock Net Delay (Source): 1.950ns (routing 0.643ns, distribution 1.307ns) + Clock Net Delay (Destination): 1.713ns (routing 0.579ns, distribution 1.134ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7354,13 +7137,13 @@ Slack (MET) : 6.468ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.844 2.052 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/m_aclk - SLICE_X65Y88 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.950 2.158 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y88 FDPE (Prop_DFF2_SLICEL_C_Q) - 0.081 2.133 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 1.251 3.384 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X64Y84 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR + SLICE_X68Y90 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.239 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 1.172 3.411 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X68Y88 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -7369,38 +7152,38 @@ Slack (MET) : 6.468ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.648 9.816 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/m_aclk - SLICE_X64Y84 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/C - clock pessimism 0.224 10.040 - clock uncertainty -0.122 9.918 - SLICE_X64Y84 FDCE (Recov_BFF2_SLICEM_C_CLR) - -0.066 9.852 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.713 9.881 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk + SLICE_X68Y88 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/C + clock pessimism 0.181 10.062 + clock uncertainty -0.122 9.940 + SLICE_X68Y88 FDPE (Recov_BFF2_SLICEL_C_PRE) + -0.066 9.874 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1] ------------------------------------------------------------------- - required time 9.852 - arrival time -3.384 + required time 9.874 + arrival time -3.411 ------------------------------------------------------------------- - slack 6.468 + slack 6.463 -Slack (MET) : 6.468ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C +Slack (MET) : 6.463ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/CLR (recovery check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 1.332ns (logic 0.081ns (6.081%) route 1.251ns (93.919%)) + Data Path Delay: 1.253ns (logic 0.081ns (6.464%) route 1.172ns (93.536%)) Logic Levels: 0 - Clock Path Skew: -0.012ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.816ns = ( 9.816 - 8.000 ) - Source Clock Delay (SCD): 2.052ns - Clock Pessimism Removal (CPR): 0.224ns + Clock Path Skew: -0.096ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.881ns = ( 9.881 - 8.000 ) + Source Clock Delay (SCD): 2.158ns + Clock Pessimism Removal (CPR): 0.181ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.844ns (routing 0.643ns, distribution 1.201ns) - Clock Net Delay (Destination): 1.648ns (routing 0.579ns, distribution 1.069ns) + Clock Net Delay (Source): 1.950ns (routing 0.643ns, distribution 1.307ns) + Clock Net Delay (Destination): 1.713ns (routing 0.579ns, distribution 1.134ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7410,13 +7193,13 @@ Slack (MET) : 6.468ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.844 2.052 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/m_aclk - SLICE_X65Y88 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.950 2.158 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y88 FDPE (Prop_DFF2_SLICEL_C_Q) - 0.081 2.133 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 1.251 3.384 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X64Y84 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR + SLICE_X68Y90 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.239 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 1.172 3.411 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X68Y88 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -7425,38 +7208,38 @@ Slack (MET) : 6.468ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.648 9.816 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/m_aclk - SLICE_X64Y84 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/C - clock pessimism 0.224 10.040 - clock uncertainty -0.122 9.918 - SLICE_X64Y84 FDCE (Recov_DFF_SLICEM_C_CLR) - -0.066 9.852 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.713 9.881 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk + SLICE_X68Y88 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/C + clock pessimism 0.181 10.062 + clock uncertainty -0.122 9.940 + SLICE_X68Y88 FDCE (Recov_DFF_SLICEL_C_CLR) + -0.066 9.874 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2] ------------------------------------------------------------------- - required time 9.852 - arrival time -3.384 + required time 9.874 + arrival time -3.411 ------------------------------------------------------------------- - slack 6.468 + slack 6.463 -Slack (MET) : 6.468ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C +Slack (MET) : 6.463ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/CLR (recovery check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 1.332ns (logic 0.081ns (6.081%) route 1.251ns (93.919%)) + Data Path Delay: 1.253ns (logic 0.081ns (6.464%) route 1.172ns (93.536%)) Logic Levels: 0 - Clock Path Skew: -0.012ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.816ns = ( 9.816 - 8.000 ) - Source Clock Delay (SCD): 2.052ns - Clock Pessimism Removal (CPR): 0.224ns + Clock Path Skew: -0.096ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.881ns = ( 9.881 - 8.000 ) + Source Clock Delay (SCD): 2.158ns + Clock Pessimism Removal (CPR): 0.181ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.844ns (routing 0.643ns, distribution 1.201ns) - Clock Net Delay (Destination): 1.648ns (routing 0.579ns, distribution 1.069ns) + Clock Net Delay (Source): 1.950ns (routing 0.643ns, distribution 1.307ns) + Clock Net Delay (Destination): 1.713ns (routing 0.579ns, distribution 1.134ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7466,13 +7249,13 @@ Slack (MET) : 6.468ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.844 2.052 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/m_aclk - SLICE_X65Y88 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.950 2.158 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y88 FDPE (Prop_DFF2_SLICEL_C_Q) - 0.081 2.133 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 1.251 3.384 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X64Y84 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR + SLICE_X68Y90 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.239 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 1.172 3.411 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X68Y88 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -7481,38 +7264,38 @@ Slack (MET) : 6.468ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.648 9.816 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/m_aclk - SLICE_X64Y84 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/C - clock pessimism 0.224 10.040 - clock uncertainty -0.122 9.918 - SLICE_X64Y84 FDCE (Recov_DFF2_SLICEM_C_CLR) - -0.066 9.852 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.713 9.881 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk + SLICE_X68Y88 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/C + clock pessimism 0.181 10.062 + clock uncertainty -0.122 9.940 + SLICE_X68Y88 FDCE (Recov_DFF2_SLICEL_C_CLR) + -0.066 9.874 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3] ------------------------------------------------------------------- - required time 9.852 - arrival time -3.384 + required time 9.874 + arrival time -3.411 ------------------------------------------------------------------- - slack 6.468 + slack 6.463 -Slack (MET) : 6.470ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C +Slack (MET) : 6.466ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE (recovery check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 1.329ns (logic 0.081ns (6.095%) route 1.248ns (93.905%)) + Data Path Delay: 1.252ns (logic 0.081ns (6.470%) route 1.171ns (93.530%)) Logic Levels: 0 - Clock Path Skew: -0.013ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.815ns = ( 9.815 - 8.000 ) - Source Clock Delay (SCD): 2.052ns - Clock Pessimism Removal (CPR): 0.224ns + Clock Path Skew: -0.094ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.883ns = ( 9.883 - 8.000 ) + Source Clock Delay (SCD): 2.158ns + Clock Pessimism Removal (CPR): 0.181ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.844ns (routing 0.643ns, distribution 1.201ns) - Clock Net Delay (Destination): 1.647ns (routing 0.579ns, distribution 1.068ns) + Clock Net Delay (Source): 1.950ns (routing 0.643ns, distribution 1.307ns) + Clock Net Delay (Destination): 1.715ns (routing 0.579ns, distribution 1.136ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7522,13 +7305,13 @@ Slack (MET) : 6.470ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.844 2.052 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/m_aclk - SLICE_X65Y88 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.950 2.158 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y88 FDPE (Prop_DFF2_SLICEL_C_Q) - 0.081 2.133 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 1.248 3.381 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X64Y84 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR + SLICE_X68Y90 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.239 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 1.171 3.410 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X68Y88 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -7537,38 +7320,38 @@ Slack (MET) : 6.470ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.647 9.815 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/m_aclk - SLICE_X64Y84 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/C - clock pessimism 0.224 10.039 - clock uncertainty -0.122 9.917 - SLICE_X64Y84 FDCE (Recov_EFF_SLICEM_C_CLR) - -0.066 9.851 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.715 9.883 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk + SLICE_X68Y88 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/C + clock pessimism 0.181 10.064 + clock uncertainty -0.122 9.942 + SLICE_X68Y88 FDPE (Recov_EFF_SLICEL_C_PRE) + -0.066 9.876 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0] ------------------------------------------------------------------- - required time 9.851 - arrival time -3.381 + required time 9.876 + arrival time -3.410 ------------------------------------------------------------------- - slack 6.470 + slack 6.466 -Slack (MET) : 6.470ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C +Slack (MET) : 6.466ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR (recovery check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 1.329ns (logic 0.081ns (6.095%) route 1.248ns (93.905%)) + Data Path Delay: 1.252ns (logic 0.081ns (6.470%) route 1.171ns (93.530%)) Logic Levels: 0 - Clock Path Skew: -0.013ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.815ns = ( 9.815 - 8.000 ) - Source Clock Delay (SCD): 2.052ns - Clock Pessimism Removal (CPR): 0.224ns + Clock Path Skew: -0.094ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.883ns = ( 9.883 - 8.000 ) + Source Clock Delay (SCD): 2.158ns + Clock Pessimism Removal (CPR): 0.181ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.844ns (routing 0.643ns, distribution 1.201ns) - Clock Net Delay (Destination): 1.647ns (routing 0.579ns, distribution 1.068ns) + Clock Net Delay (Source): 1.950ns (routing 0.643ns, distribution 1.307ns) + Clock Net Delay (Destination): 1.715ns (routing 0.579ns, distribution 1.136ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7578,13 +7361,13 @@ Slack (MET) : 6.470ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.844 2.052 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/m_aclk - SLICE_X65Y88 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.950 2.158 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y88 FDPE (Prop_DFF2_SLICEL_C_Q) - 0.081 2.133 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 1.248 3.381 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X64Y84 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR + SLICE_X68Y90 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.239 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 1.171 3.410 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X68Y88 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -7593,38 +7376,38 @@ Slack (MET) : 6.470ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.647 9.815 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/m_aclk - SLICE_X64Y84 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/C - clock pessimism 0.224 10.039 - clock uncertainty -0.122 9.917 - SLICE_X64Y84 FDCE (Recov_EFF2_SLICEM_C_CLR) - -0.066 9.851 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.715 9.883 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk + SLICE_X68Y88 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/C + clock pessimism 0.181 10.064 + clock uncertainty -0.122 9.942 + SLICE_X68Y88 FDCE (Recov_EFF2_SLICEL_C_CLR) + -0.066 9.876 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1] ------------------------------------------------------------------- - required time 9.851 - arrival time -3.381 + required time 9.876 + arrival time -3.410 ------------------------------------------------------------------- - slack 6.470 + slack 6.466 -Slack (MET) : 6.470ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C +Slack (MET) : 6.466ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR (recovery check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 1.329ns (logic 0.081ns (6.095%) route 1.248ns (93.905%)) + Data Path Delay: 1.252ns (logic 0.081ns (6.470%) route 1.171ns (93.530%)) Logic Levels: 0 - Clock Path Skew: -0.013ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.815ns = ( 9.815 - 8.000 ) - Source Clock Delay (SCD): 2.052ns - Clock Pessimism Removal (CPR): 0.224ns + Clock Path Skew: -0.094ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.883ns = ( 9.883 - 8.000 ) + Source Clock Delay (SCD): 2.158ns + Clock Pessimism Removal (CPR): 0.181ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.844ns (routing 0.643ns, distribution 1.201ns) - Clock Net Delay (Destination): 1.647ns (routing 0.579ns, distribution 1.068ns) + Clock Net Delay (Source): 1.950ns (routing 0.643ns, distribution 1.307ns) + Clock Net Delay (Destination): 1.715ns (routing 0.579ns, distribution 1.136ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7634,13 +7417,13 @@ Slack (MET) : 6.470ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.844 2.052 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/m_aclk - SLICE_X65Y88 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.950 2.158 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y88 FDPE (Prop_DFF2_SLICEL_C_Q) - 0.081 2.133 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 1.248 3.381 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X64Y84 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR + SLICE_X68Y90 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.239 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 1.171 3.410 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X68Y88 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -7649,38 +7432,38 @@ Slack (MET) : 6.470ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.647 9.815 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/m_aclk - SLICE_X64Y84 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/C - clock pessimism 0.224 10.039 - clock uncertainty -0.122 9.917 - SLICE_X64Y84 FDCE (Recov_FFF_SLICEM_C_CLR) - -0.066 9.851 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.715 9.883 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk + SLICE_X68Y88 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/C + clock pessimism 0.181 10.064 + clock uncertainty -0.122 9.942 + SLICE_X68Y88 FDCE (Recov_FFF_SLICEL_C_CLR) + -0.066 9.876 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2] ------------------------------------------------------------------- - required time 9.851 - arrival time -3.381 + required time 9.876 + arrival time -3.410 ------------------------------------------------------------------- - slack 6.470 + slack 6.466 -Slack (MET) : 6.470ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C +Slack (MET) : 6.466ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR (recovery check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 1.329ns (logic 0.081ns (6.095%) route 1.248ns (93.905%)) + Data Path Delay: 1.252ns (logic 0.081ns (6.470%) route 1.171ns (93.530%)) Logic Levels: 0 - Clock Path Skew: -0.013ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.815ns = ( 9.815 - 8.000 ) - Source Clock Delay (SCD): 2.052ns - Clock Pessimism Removal (CPR): 0.224ns + Clock Path Skew: -0.094ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.883ns = ( 9.883 - 8.000 ) + Source Clock Delay (SCD): 2.158ns + Clock Pessimism Removal (CPR): 0.181ns Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.235ns Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.844ns (routing 0.643ns, distribution 1.201ns) - Clock Net Delay (Destination): 1.647ns (routing 0.579ns, distribution 1.068ns) + Clock Net Delay (Source): 1.950ns (routing 0.643ns, distribution 1.307ns) + Clock Net Delay (Destination): 1.715ns (routing 0.579ns, distribution 1.136ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7690,13 +7473,13 @@ Slack (MET) : 6.470ns (required time - arrival time) net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.844 2.052 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/m_aclk - SLICE_X65Y88 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.950 2.158 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y88 FDPE (Prop_DFF2_SLICEL_C_Q) - 0.081 2.133 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 1.248 3.381 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X64Y84 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR + SLICE_X68Y90 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.239 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 1.171 3.410 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X68Y88 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -7705,17 +7488,129 @@ Slack (MET) : 6.470ns (required time - arrival time) net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.647 9.815 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/m_aclk - SLICE_X64Y84 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/C - clock pessimism 0.224 10.039 - clock uncertainty -0.122 9.917 - SLICE_X64Y84 FDCE (Recov_FFF2_SLICEM_C_CLR) - -0.066 9.851 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.715 9.883 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk + SLICE_X68Y88 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/C + clock pessimism 0.181 10.064 + clock uncertainty -0.122 9.942 + SLICE_X68Y88 FDCE (Recov_FFF2_SLICEL_C_CLR) + -0.066 9.876 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3] ------------------------------------------------------------------- - required time 9.851 - arrival time -3.381 + required time 9.876 + arrival time -3.410 ------------------------------------------------------------------- - slack 6.470 + slack 6.466 + +Slack (MET) : 6.466ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR + (recovery check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) + Data Path Delay: 1.252ns (logic 0.081ns (6.470%) route 1.171ns (93.530%)) + Logic Levels: 0 + Clock Path Skew: -0.094ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.883ns = ( 9.883 - 8.000 ) + Source Clock Delay (SCD): 2.158ns + Clock Pessimism Removal (CPR): 0.181ns + Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.235ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.950ns (routing 0.643ns, distribution 1.307ns) + Clock Net Delay (Destination): 1.715ns (routing 0.579ns, distribution 1.136ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pl_0 rise edge) + 0.000 0.000 r + PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] + net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] + BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) + 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.950 2.158 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.239 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 1.171 3.410 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X68Y88 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pl_0 rise edge) + 8.000 8.000 r + PS8_X0Y0 PS8 0.000 8.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] + net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] + BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) + 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.715 9.883 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk + SLICE_X68Y88 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/C + clock pessimism 0.181 10.064 + clock uncertainty -0.122 9.942 + SLICE_X68Y88 FDCE (Recov_GFF_SLICEL_C_CLR) + -0.066 9.876 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0] + ------------------------------------------------------------------- + required time 9.876 + arrival time -3.410 + ------------------------------------------------------------------- + slack 6.466 + +Slack (MET) : 6.466ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/CLR + (recovery check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 8.000ns (clk_pl_0 rise@8.000ns - clk_pl_0 rise@0.000ns) + Data Path Delay: 1.252ns (logic 0.081ns (6.470%) route 1.171ns (93.530%)) + Logic Levels: 0 + Clock Path Skew: -0.094ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.883ns = ( 9.883 - 8.000 ) + Source Clock Delay (SCD): 2.158ns + Clock Pessimism Removal (CPR): 0.181ns + Clock Uncertainty: 0.122ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.235ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.950ns (routing 0.643ns, distribution 1.307ns) + Clock Net Delay (Destination): 1.715ns (routing 0.579ns, distribution 1.136ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pl_0 rise edge) + 0.000 0.000 r + PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] + net (fo=1, routed) 0.180 0.180 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] + BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) + 0.028 0.208 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.950 2.158 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y90 FDPE (Prop_DFF2_SLICEL_C_Q) + 0.081 2.239 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 1.171 3.410 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X68Y88 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pl_0 rise edge) + 8.000 8.000 r + PS8_X0Y0 PS8 0.000 8.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] + net (fo=1, routed) 0.143 8.143 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] + BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) + 0.025 8.168 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.715 9.883 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk + SLICE_X68Y88 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C + clock pessimism 0.181 10.064 + clock uncertainty -0.122 9.942 + SLICE_X68Y88 FDCE (Recov_GFF2_SLICEL_C_CLR) + -0.066 9.876 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1] + ------------------------------------------------------------------- + required time 9.876 + arrival time -3.410 + ------------------------------------------------------------------- + slack 6.466 @@ -7723,22 +7618,22 @@ Slack (MET) : 6.470ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.138ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C +Slack (MET) : 0.096ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0]/CLR (removal check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.134ns (logic 0.039ns (29.104%) route 0.095ns (70.896%)) + Data Path Delay: 0.138ns (logic 0.040ns (28.985%) route 0.098ns (71.014%)) Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.350ns - Source Clock Delay (SCD): 1.183ns - Clock Pessimism Removal (CPR): 0.151ns - Clock Net Delay (Source): 1.044ns (routing 0.352ns, distribution 0.692ns) - Clock Net Delay (Destination): 1.178ns (routing 0.398ns, distribution 0.780ns) + Clock Path Skew: 0.062ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.385ns + Source Clock Delay (SCD): 1.198ns + Clock Pessimism Removal (CPR): 0.125ns + Clock Net Delay (Source): 1.059ns (routing 0.352ns, distribution 0.707ns) + Clock Net Delay (Destination): 1.213ns (routing 0.398ns, distribution 0.815ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7748,13 +7643,13 @@ Slack (MET) : 0.138ns (arrival time - required time) net (fo=1, routed) 0.122 0.122 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.017 0.139 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.044 1.183 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk - SLICE_X64Y56 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.059 1.198 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X66Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y56 FDPE (Prop_EFF2_SLICEM_C_Q) - 0.039 1.222 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q - net (fo=3, routed) 0.095 1.317 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/rst_rd_reg2 - SLICE_X65Y57 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + SLICE_X66Y90 FDPE (Prop_EFF2_SLICEL_C_Q) + 0.040 1.238 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q + net (fo=9, routed) 0.098 1.336 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/rst_wr_reg2 + SLICE_X68Y90 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -7763,33 +7658,33 @@ Slack (MET) : 0.138ns (arrival time - required time) net (fo=1, routed) 0.154 0.154 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.018 0.172 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.178 1.350 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/m_aclk - SLICE_X65Y57 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/C - clock pessimism -0.151 1.199 - SLICE_X65Y57 FDCE (Remov_EFF_SLICEL_C_CLR) - -0.020 1.179 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.213 1.385 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0]/C + clock pessimism -0.125 1.260 + SLICE_X68Y90 FDCE (Remov_EFF_SLICEL_C_CLR) + -0.020 1.240 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0] ------------------------------------------------------------------- - required time -1.179 - arrival time 1.317 + required time -1.240 + arrival time 1.336 ------------------------------------------------------------------- - slack 0.138 + slack 0.096 -Slack (MET) : 0.138ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C +Slack (MET) : 0.096ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[1]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1]/CLR (removal check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.134ns (logic 0.039ns (29.104%) route 0.095ns (70.896%)) + Data Path Delay: 0.138ns (logic 0.040ns (28.985%) route 0.098ns (71.014%)) Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.350ns - Source Clock Delay (SCD): 1.183ns - Clock Pessimism Removal (CPR): 0.151ns - Clock Net Delay (Source): 1.044ns (routing 0.352ns, distribution 0.692ns) - Clock Net Delay (Destination): 1.178ns (routing 0.398ns, distribution 0.780ns) + Clock Path Skew: 0.062ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.385ns + Source Clock Delay (SCD): 1.198ns + Clock Pessimism Removal (CPR): 0.125ns + Clock Net Delay (Source): 1.059ns (routing 0.352ns, distribution 0.707ns) + Clock Net Delay (Destination): 1.213ns (routing 0.398ns, distribution 0.815ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7799,13 +7694,13 @@ Slack (MET) : 0.138ns (arrival time - required time) net (fo=1, routed) 0.122 0.122 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.017 0.139 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.044 1.183 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk - SLICE_X64Y56 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.059 1.198 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X66Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y56 FDPE (Prop_EFF2_SLICEM_C_Q) - 0.039 1.222 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q - net (fo=3, routed) 0.095 1.317 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/rst_rd_reg2 - SLICE_X65Y57 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[1]/CLR + SLICE_X66Y90 FDPE (Prop_EFF2_SLICEL_C_Q) + 0.040 1.238 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q + net (fo=9, routed) 0.098 1.336 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/rst_wr_reg2 + SLICE_X68Y90 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -7814,33 +7709,33 @@ Slack (MET) : 0.138ns (arrival time - required time) net (fo=1, routed) 0.154 0.154 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.018 0.172 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.178 1.350 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/m_aclk - SLICE_X65Y57 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[1]/C - clock pessimism -0.151 1.199 - SLICE_X65Y57 FDCE (Remov_EFF2_SLICEL_C_CLR) - -0.020 1.179 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[1] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.213 1.385 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1]/C + clock pessimism -0.125 1.260 + SLICE_X68Y90 FDCE (Remov_EFF2_SLICEL_C_CLR) + -0.020 1.240 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1] ------------------------------------------------------------------- - required time -1.179 - arrival time 1.317 + required time -1.240 + arrival time 1.336 ------------------------------------------------------------------- - slack 0.138 + slack 0.096 -Slack (MET) : 0.142ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C +Slack (MET) : 0.096ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/PRE + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2]/CLR (removal check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.134ns (logic 0.039ns (29.104%) route 0.095ns (70.896%)) + Data Path Delay: 0.138ns (logic 0.040ns (28.985%) route 0.098ns (71.014%)) Logic Levels: 0 - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.346ns - Source Clock Delay (SCD): 1.183ns - Clock Pessimism Removal (CPR): 0.151ns - Clock Net Delay (Source): 1.044ns (routing 0.352ns, distribution 0.692ns) - Clock Net Delay (Destination): 1.174ns (routing 0.398ns, distribution 0.776ns) + Clock Path Skew: 0.062ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.385ns + Source Clock Delay (SCD): 1.198ns + Clock Pessimism Removal (CPR): 0.125ns + Clock Net Delay (Source): 1.059ns (routing 0.352ns, distribution 0.707ns) + Clock Net Delay (Destination): 1.213ns (routing 0.398ns, distribution 0.815ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7850,13 +7745,13 @@ Slack (MET) : 0.142ns (arrival time - required time) net (fo=1, routed) 0.122 0.122 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.017 0.139 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.044 1.183 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk - SLICE_X64Y56 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.059 1.198 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X66Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y56 FDPE (Prop_EFF2_SLICEM_C_Q) - 0.039 1.222 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q - net (fo=3, routed) 0.095 1.317 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/rst_rd_reg2 - SLICE_X65Y57 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/PRE + SLICE_X66Y90 FDPE (Prop_EFF2_SLICEL_C_Q) + 0.040 1.238 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q + net (fo=9, routed) 0.098 1.336 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/rst_wr_reg2 + SLICE_X68Y90 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -7865,18 +7760,171 @@ Slack (MET) : 0.142ns (arrival time - required time) net (fo=1, routed) 0.154 0.154 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.018 0.172 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.174 1.346 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/m_aclk - SLICE_X65Y57 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C - clock pessimism -0.151 1.195 - SLICE_X65Y57 FDPE (Remov_DFF2_SLICEL_C_PRE) - -0.020 1.175 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.213 1.385 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2]/C + clock pessimism -0.125 1.260 + SLICE_X68Y90 FDCE (Remov_FFF_SLICEL_C_CLR) + -0.020 1.240 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2] ------------------------------------------------------------------- - required time -1.175 - arrival time 1.317 + required time -1.240 + arrival time 1.336 ------------------------------------------------------------------- - slack 0.142 + slack 0.096 -Slack (MET) : 0.146ns (arrival time - required time) +Slack (MET) : 0.096ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3]/CLR + (removal check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) + Data Path Delay: 0.138ns (logic 0.040ns (28.985%) route 0.098ns (71.014%)) + Logic Levels: 0 + Clock Path Skew: 0.062ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.385ns + Source Clock Delay (SCD): 1.198ns + Clock Pessimism Removal (CPR): 0.125ns + Clock Net Delay (Source): 1.059ns (routing 0.352ns, distribution 0.707ns) + Clock Net Delay (Destination): 1.213ns (routing 0.398ns, distribution 0.815ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pl_0 rise edge) + 0.000 0.000 r + PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] + net (fo=1, routed) 0.122 0.122 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] + BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) + 0.017 0.139 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.059 1.198 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X66Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X66Y90 FDPE (Prop_EFF2_SLICEL_C_Q) + 0.040 1.238 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q + net (fo=9, routed) 0.098 1.336 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/rst_wr_reg2 + SLICE_X68Y90 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pl_0 rise edge) + 0.000 0.000 r + PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] + net (fo=1, routed) 0.154 0.154 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] + BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) + 0.018 0.172 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.213 1.385 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3]/C + clock pessimism -0.125 1.260 + SLICE_X68Y90 FDCE (Remov_FFF2_SLICEL_C_CLR) + -0.020 1.240 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3] + ------------------------------------------------------------------- + required time -1.240 + arrival time 1.336 + ------------------------------------------------------------------- + slack 0.096 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/PRE + (removal check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) + Data Path Delay: 0.138ns (logic 0.040ns (28.985%) route 0.098ns (71.014%)) + Logic Levels: 0 + Clock Path Skew: 0.058ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.381ns + Source Clock Delay (SCD): 1.198ns + Clock Pessimism Removal (CPR): 0.125ns + Clock Net Delay (Source): 1.059ns (routing 0.352ns, distribution 0.707ns) + Clock Net Delay (Destination): 1.209ns (routing 0.398ns, distribution 0.811ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pl_0 rise edge) + 0.000 0.000 r + PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] + net (fo=1, routed) 0.122 0.122 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] + BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) + 0.017 0.139 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.059 1.198 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X66Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X66Y90 FDPE (Prop_EFF2_SLICEL_C_Q) + 0.040 1.238 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q + net (fo=9, routed) 0.098 1.336 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/rst_wr_reg2 + SLICE_X68Y90 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pl_0 rise edge) + 0.000 0.000 r + PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] + net (fo=1, routed) 0.154 0.154 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] + BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) + 0.018 0.172 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.209 1.381 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + clock pessimism -0.125 1.256 + SLICE_X68Y90 FDPE (Remov_DFF2_SLICEL_C_PRE) + -0.020 1.236 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg + ------------------------------------------------------------------- + required time -1.236 + arrival time 1.336 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_reg/PRE + (removal check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) + Data Path Delay: 0.138ns (logic 0.040ns (28.985%) route 0.098ns (71.014%)) + Logic Levels: 0 + Clock Path Skew: 0.058ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.381ns + Source Clock Delay (SCD): 1.198ns + Clock Pessimism Removal (CPR): 0.125ns + Clock Net Delay (Source): 1.059ns (routing 0.352ns, distribution 0.707ns) + Clock Net Delay (Destination): 1.209ns (routing 0.398ns, distribution 0.811ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pl_0 rise edge) + 0.000 0.000 r + PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] + net (fo=1, routed) 0.122 0.122 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] + BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) + 0.017 0.139 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.059 1.198 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X66Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X66Y90 FDPE (Prop_EFF2_SLICEL_C_Q) + 0.040 1.238 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q + net (fo=9, routed) 0.098 1.336 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/rst_wr_reg2 + SLICE_X68Y90 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_reg/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pl_0 rise edge) + 0.000 0.000 r + PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] + net (fo=1, routed) 0.154 0.154 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] + BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) + 0.018 0.172 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.209 1.381 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y90 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_reg/C + clock pessimism -0.125 1.256 + SLICE_X68Y90 FDPE (Remov_CFF2_SLICEL_C_PRE) + -0.020 1.236 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_reg + ------------------------------------------------------------------- + required time -1.236 + arrival time 1.336 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.113ns (arrival time - required time) Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/PRE @@ -7884,14 +7932,14 @@ Slack (MET) : 0.146ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.168ns (logic 0.039ns (23.214%) route 0.129ns (76.786%)) + Data Path Delay: 0.108ns (logic 0.040ns (37.037%) route 0.068ns (62.963%)) Logic Levels: 0 - Clock Path Skew: 0.042ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.331ns - Source Clock Delay (SCD): 1.169ns - Clock Pessimism Removal (CPR): 0.120ns - Clock Net Delay (Source): 1.030ns (routing 0.352ns, distribution 0.678ns) - Clock Net Delay (Destination): 1.159ns (routing 0.398ns, distribution 0.761ns) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.330ns + Source Clock Delay (SCD): 1.160ns + Clock Pessimism Removal (CPR): 0.155ns + Clock Net Delay (Source): 1.021ns (routing 0.352ns, distribution 0.669ns) + Clock Net Delay (Destination): 1.158ns (routing 0.398ns, distribution 0.760ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7901,13 +7949,13 @@ Slack (MET) : 0.146ns (arrival time - required time) net (fo=1, routed) 0.122 0.122 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.017 0.139 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.030 1.169 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/m_aclk - SLICE_X64Y70 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.021 1.160 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/m_aclk + SLICE_X62Y68 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y70 FDPE (Prop_AFF2_SLICEM_C_Q) - 0.039 1.208 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q - net (fo=3, routed) 0.129 1.337 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/out - SLICE_X63Y69 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/PRE + SLICE_X62Y68 FDPE (Prop_AFF2_SLICEL_C_Q) + 0.040 1.200 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q + net (fo=3, routed) 0.068 1.268 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/out + SLICE_X62Y68 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -7916,18 +7964,18 @@ Slack (MET) : 0.146ns (arrival time - required time) net (fo=1, routed) 0.154 0.154 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.018 0.172 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.159 1.331 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/m_aclk - SLICE_X63Y69 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/C - clock pessimism -0.120 1.211 - SLICE_X63Y69 FDPE (Remov_EFF_SLICEM_C_PRE) - -0.020 1.191 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.158 1.330 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/m_aclk + SLICE_X62Y68 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/C + clock pessimism -0.155 1.175 + SLICE_X62Y68 FDPE (Remov_EFF_SLICEL_C_PRE) + -0.020 1.155 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg ------------------------------------------------------------------- - required time -1.191 - arrival time 1.337 + required time -1.155 + arrival time 1.268 ------------------------------------------------------------------- - slack 0.146 + slack 0.113 -Slack (MET) : 0.146ns (arrival time - required time) +Slack (MET) : 0.113ns (arrival time - required time) Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/PRE @@ -7935,14 +7983,14 @@ Slack (MET) : 0.146ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.168ns (logic 0.039ns (23.214%) route 0.129ns (76.786%)) + Data Path Delay: 0.108ns (logic 0.040ns (37.037%) route 0.068ns (62.963%)) Logic Levels: 0 - Clock Path Skew: 0.042ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.331ns - Source Clock Delay (SCD): 1.169ns - Clock Pessimism Removal (CPR): 0.120ns - Clock Net Delay (Source): 1.030ns (routing 0.352ns, distribution 0.678ns) - Clock Net Delay (Destination): 1.159ns (routing 0.398ns, distribution 0.761ns) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.330ns + Source Clock Delay (SCD): 1.160ns + Clock Pessimism Removal (CPR): 0.155ns + Clock Net Delay (Source): 1.021ns (routing 0.352ns, distribution 0.669ns) + Clock Net Delay (Destination): 1.158ns (routing 0.398ns, distribution 0.760ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7952,13 +8000,13 @@ Slack (MET) : 0.146ns (arrival time - required time) net (fo=1, routed) 0.122 0.122 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.017 0.139 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.030 1.169 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/m_aclk - SLICE_X64Y70 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.021 1.160 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/m_aclk + SLICE_X62Y68 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y70 FDPE (Prop_AFF2_SLICEM_C_Q) - 0.039 1.208 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q - net (fo=3, routed) 0.129 1.337 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/out - SLICE_X63Y69 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/PRE + SLICE_X62Y68 FDPE (Prop_AFF2_SLICEL_C_Q) + 0.040 1.200 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q + net (fo=3, routed) 0.068 1.268 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/out + SLICE_X62Y68 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -7967,33 +8015,33 @@ Slack (MET) : 0.146ns (arrival time - required time) net (fo=1, routed) 0.154 0.154 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.018 0.172 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.159 1.331 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/m_aclk - SLICE_X63Y69 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/C - clock pessimism -0.120 1.211 - SLICE_X63Y69 FDPE (Remov_EFF2_SLICEM_C_PRE) - -0.020 1.191 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.158 1.330 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/m_aclk + SLICE_X62Y68 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/C + clock pessimism -0.155 1.175 + SLICE_X62Y68 FDPE (Remov_EFF2_SLICEL_C_PRE) + -0.020 1.155 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg ------------------------------------------------------------------- - required time -1.191 - arrival time 1.337 + required time -1.155 + arrival time 1.268 ------------------------------------------------------------------- - slack 0.146 + slack 0.113 -Slack (MET) : 0.162ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C +Slack (MET) : 0.114ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/PRE (removal check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.172ns (logic 0.041ns (23.837%) route 0.131ns (76.163%)) + Data Path Delay: 0.109ns (logic 0.040ns (36.697%) route 0.069ns (63.303%)) Logic Levels: 0 - Clock Path Skew: 0.030ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.346ns - Source Clock Delay (SCD): 1.169ns - Clock Pessimism Removal (CPR): 0.147ns - Clock Net Delay (Source): 1.030ns (routing 0.352ns, distribution 0.678ns) - Clock Net Delay (Destination): 1.174ns (routing 0.398ns, distribution 0.776ns) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.378ns + Source Clock Delay (SCD): 1.204ns + Clock Pessimism Removal (CPR): 0.159ns + Clock Net Delay (Source): 1.065ns (routing 0.352ns, distribution 0.713ns) + Clock Net Delay (Destination): 1.206ns (routing 0.398ns, distribution 0.808ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -8003,13 +8051,13 @@ Slack (MET) : 0.162ns (arrival time - required time) net (fo=1, routed) 0.122 0.122 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.017 0.139 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.030 1.169 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/m_aclk - SLICE_X64Y70 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.065 1.204 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y89 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y70 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.210 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.131 1.341 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X64Y68 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR + SLICE_X68Y89 FDPE (Prop_AFF2_SLICEL_C_Q) + 0.040 1.244 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q + net (fo=3, routed) 0.069 1.313 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/out + SLICE_X68Y89 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -8018,33 +8066,33 @@ Slack (MET) : 0.162ns (arrival time - required time) net (fo=1, routed) 0.154 0.154 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.018 0.172 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.174 1.346 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk - SLICE_X64Y68 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/C - clock pessimism -0.147 1.199 - SLICE_X64Y68 FDCE (Remov_CFF2_SLICEM_C_CLR) - -0.020 1.179 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.206 1.378 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/m_aclk + SLICE_X68Y89 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/C + clock pessimism -0.159 1.219 + SLICE_X68Y89 FDPE (Remov_EFF_SLICEL_C_PRE) + -0.020 1.199 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg ------------------------------------------------------------------- - required time -1.179 - arrival time 1.341 + required time -1.199 + arrival time 1.313 ------------------------------------------------------------------- - slack 0.162 + slack 0.114 -Slack (MET) : 0.162ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C +Slack (MET) : 0.114ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE + Destination: pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/PRE (removal check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.172ns (logic 0.041ns (23.837%) route 0.131ns (76.163%)) + Data Path Delay: 0.109ns (logic 0.040ns (36.697%) route 0.069ns (63.303%)) Logic Levels: 0 - Clock Path Skew: 0.030ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.346ns - Source Clock Delay (SCD): 1.169ns - Clock Pessimism Removal (CPR): 0.147ns - Clock Net Delay (Source): 1.030ns (routing 0.352ns, distribution 0.678ns) - Clock Net Delay (Destination): 1.174ns (routing 0.398ns, distribution 0.776ns) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.378ns + Source Clock Delay (SCD): 1.204ns + Clock Pessimism Removal (CPR): 0.159ns + Clock Net Delay (Source): 1.065ns (routing 0.352ns, distribution 0.713ns) + Clock Net Delay (Destination): 1.206ns (routing 0.398ns, distribution 0.808ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -8054,13 +8102,13 @@ Slack (MET) : 0.162ns (arrival time - required time) net (fo=1, routed) 0.122 0.122 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.017 0.139 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.030 1.169 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/m_aclk - SLICE_X64Y70 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.065 1.204 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/m_aclk + SLICE_X68Y89 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y70 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.210 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.131 1.341 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X64Y68 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE + SLICE_X68Y89 FDPE (Prop_AFF2_SLICEL_C_Q) + 0.040 1.244 f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q + net (fo=3, routed) 0.069 1.313 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/out + SLICE_X68Y89 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk_pl_0 rise edge) @@ -8069,169 +8117,16 @@ Slack (MET) : 0.162ns (arrival time - required time) net (fo=1, routed) 0.154 0.154 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) 0.018 0.172 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.174 1.346 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk - SLICE_X64Y68 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/C - clock pessimism -0.147 1.199 - SLICE_X64Y68 FDPE (Remov_BFF2_SLICEM_C_PRE) - -0.020 1.179 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1] + X1Y2 (CLOCK_ROOT) net (fo=9045, routed) 1.206 1.378 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/m_aclk + SLICE_X68Y89 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/C + clock pessimism -0.159 1.219 + SLICE_X68Y89 FDPE (Remov_EFF2_SLICEL_C_PRE) + -0.020 1.199 pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg ------------------------------------------------------------------- - required time -1.179 - arrival time 1.341 + required time -1.199 + arrival time 1.313 ------------------------------------------------------------------- - slack 0.162 - -Slack (MET) : 0.162ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C - (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/CLR - (removal check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.172ns (logic 0.041ns (23.837%) route 0.131ns (76.163%)) - Logic Levels: 0 - Clock Path Skew: 0.030ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.346ns - Source Clock Delay (SCD): 1.169ns - Clock Pessimism Removal (CPR): 0.147ns - Clock Net Delay (Source): 1.030ns (routing 0.352ns, distribution 0.678ns) - Clock Net Delay (Destination): 1.174ns (routing 0.398ns, distribution 0.776ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_pl_0 rise edge) - 0.000 0.000 r - PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] - net (fo=1, routed) 0.122 0.122 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] - BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) - 0.017 0.139 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.030 1.169 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/m_aclk - SLICE_X64Y70 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X64Y70 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.210 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.131 1.341 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X64Y68 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock clk_pl_0 rise edge) - 0.000 0.000 r - PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] - net (fo=1, routed) 0.154 0.154 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] - BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) - 0.018 0.172 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.174 1.346 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk - SLICE_X64Y68 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/C - clock pessimism -0.147 1.199 - SLICE_X64Y68 FDCE (Remov_DFF_SLICEM_C_CLR) - -0.020 1.179 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2] - ------------------------------------------------------------------- - required time -1.179 - arrival time 1.341 - ------------------------------------------------------------------- - slack 0.162 - -Slack (MET) : 0.162ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C - (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/CLR - (removal check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.172ns (logic 0.041ns (23.837%) route 0.131ns (76.163%)) - Logic Levels: 0 - Clock Path Skew: 0.030ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.346ns - Source Clock Delay (SCD): 1.169ns - Clock Pessimism Removal (CPR): 0.147ns - Clock Net Delay (Source): 1.030ns (routing 0.352ns, distribution 0.678ns) - Clock Net Delay (Destination): 1.174ns (routing 0.398ns, distribution 0.776ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_pl_0 rise edge) - 0.000 0.000 r - PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] - net (fo=1, routed) 0.122 0.122 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] - BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) - 0.017 0.139 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.030 1.169 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/m_aclk - SLICE_X64Y70 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X64Y70 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.210 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.131 1.341 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X64Y68 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock clk_pl_0 rise edge) - 0.000 0.000 r - PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] - net (fo=1, routed) 0.154 0.154 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] - BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) - 0.018 0.172 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.174 1.346 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk - SLICE_X64Y68 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/C - clock pessimism -0.147 1.199 - SLICE_X64Y68 FDCE (Remov_DFF2_SLICEM_C_CLR) - -0.020 1.179 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3] - ------------------------------------------------------------------- - required time -1.179 - arrival time 1.341 - ------------------------------------------------------------------- - slack 0.162 - -Slack (MET) : 0.162ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C - (rising edge-triggered cell FDPE clocked by clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE - (removal check against rising-edge clock clk_pl_0 {rise@0.000ns fall@4.000ns period=8.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns) - Data Path Delay: 0.171ns (logic 0.041ns (23.977%) route 0.130ns (76.023%)) - Logic Levels: 0 - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.345ns - Source Clock Delay (SCD): 1.169ns - Clock Pessimism Removal (CPR): 0.147ns - Clock Net Delay (Source): 1.030ns (routing 0.352ns, distribution 0.678ns) - Clock Net Delay (Destination): 1.173ns (routing 0.398ns, distribution 0.775ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_pl_0 rise edge) - 0.000 0.000 r - PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] - net (fo=1, routed) 0.122 0.122 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] - BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) - 0.017 0.139 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.030 1.169 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/m_aclk - SLICE_X64Y70 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X64Y70 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.210 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q - net (fo=15, routed) 0.130 1.340 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] - SLICE_X64Y68 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE - ------------------------------------------------------------------- ------------------- - - (clock clk_pl_0 rise edge) - 0.000 0.000 r - PS8_X0Y0 PS8 0.000 0.000 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] - net (fo=1, routed) 0.154 0.154 pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0] - BUFG_PS_X0Y84 BUFG_PS (Prop_BUFG_PS_I_O) - 0.018 0.172 r pl_eth_10g_i/zups/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O - X1Y2 (CLOCK_ROOT) net (fo=9039, routed) 1.173 1.345 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/m_aclk - SLICE_X64Y68 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/C - clock pessimism -0.147 1.198 - SLICE_X64Y68 FDPE (Remov_EFF_SLICEM_C_PRE) - -0.020 1.178 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0] - ------------------------------------------------------------------- - required time -1.178 - arrival time 1.340 - ------------------------------------------------------------------- - slack 0.162 + slack 0.114 @@ -8242,137 +8137,25 @@ Path Group: **async_default** From Clock: xxv_ethernet_0_tx_clk_out_0 To Clock: xxv_ethernet_0_tx_clk_out_0 -Setup : 0 Failing Endpoints, Worst Slack 5.276ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.149ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 5.646ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.154ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 5.276ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C - (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/PRE - (recovery check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.983ns (logic 0.080ns (8.138%) route 0.903ns (91.862%)) - Logic Levels: 0 - Clock Path Skew: -0.029ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.844ns = ( 8.244 - 6.400 ) - Source Clock Delay (SCD): 2.085ns - Clock Pessimism Removal (CPR): 0.212ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.842ns (routing 0.508ns, distribution 1.334ns) - Clock Net Delay (Destination): 1.631ns (routing 0.454ns, distribution 1.177ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.842 2.085 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk - SLICE_X64Y57 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X64Y57 FDPE (Prop_AFF2_SLICEM_C_Q) - 0.080 2.165 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q - net (fo=3, routed) 0.903 3.068 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/out - SLICE_X64Y58 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/PRE - ------------------------------------------------------------------- ------------------- - - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.631 8.244 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/s_aclk - SLICE_X64Y58 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/C - clock pessimism 0.212 8.456 - clock uncertainty -0.046 8.410 - SLICE_X64Y58 FDPE (Recov_EFF_SLICEM_C_PRE) - -0.066 8.344 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg - ------------------------------------------------------------------- - required time 8.344 - arrival time -3.068 - ------------------------------------------------------------------- - slack 5.276 - -Slack (MET) : 5.276ns (required time - arrival time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C - (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/PRE - (recovery check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.983ns (logic 0.080ns (8.138%) route 0.903ns (91.862%)) - Logic Levels: 0 - Clock Path Skew: -0.029ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.844ns = ( 8.244 - 6.400 ) - Source Clock Delay (SCD): 2.085ns - Clock Pessimism Removal (CPR): 0.212ns - Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.060ns - Phase Error (PE): 0.000ns - Clock Net Delay (Source): 1.842ns (routing 0.508ns, distribution 1.334ns) - Clock Net Delay (Destination): 1.631ns (routing 0.454ns, distribution 1.177ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.842 2.085 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk - SLICE_X64Y57 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X64Y57 FDPE (Prop_AFF2_SLICEM_C_Q) - 0.080 2.165 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/Q - net (fo=3, routed) 0.903 3.068 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/out - SLICE_X64Y58 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/PRE - ------------------------------------------------------------------- ------------------- - - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 6.400 6.400 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.631 8.244 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/s_aclk - SLICE_X64Y58 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/C - clock pessimism 0.212 8.456 - clock uncertainty -0.046 8.410 - SLICE_X64Y58 FDPE (Recov_EFF2_SLICEM_C_PRE) - -0.066 8.344 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg - ------------------------------------------------------------------- - required time 8.344 - arrival time -3.068 - ------------------------------------------------------------------- - slack 5.276 - -Slack (MET) : 5.626ns (required time - arrival time) +Slack (MET) : 5.646ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/PRE (recovery check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.581ns (logic 0.080ns (13.769%) route 0.501ns (86.231%)) + Data Path Delay: 0.577ns (logic 0.080ns (13.865%) route 0.497ns (86.135%)) Logic Levels: 0 - Clock Path Skew: -0.081ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.827ns = ( 8.227 - 6.400 ) + Clock Path Skew: -0.065ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.843ns = ( 8.243 - 6.400 ) Source Clock Delay (SCD): 2.066ns Clock Pessimism Removal (CPR): 0.158ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -8380,7 +8163,7 @@ Slack (MET) : 5.626ns (required time - arrival time) Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.823ns (routing 0.508ns, distribution 1.315ns) - Clock Net Delay (Destination): 1.614ns (routing 0.454ns, distribution 1.160ns) + Clock Net Delay (Destination): 1.630ns (routing 0.454ns, distribution 1.176ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -8395,8 +8178,8 @@ Slack (MET) : 5.626ns (required time - arrival time) ------------------------------------------------------------------- ------------------- SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) 0.080 2.146 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.501 2.647 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0 - SLICE_X62Y63 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE + net (fo=21, routed) 0.497 2.643 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 + SLICE_X59Y66 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/PRE ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -8405,30 +8188,30 @@ Slack (MET) : 5.626ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.614 8.227 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/s_aclk - SLICE_X62Y63 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/C - clock pessimism 0.158 8.385 - clock uncertainty -0.046 8.339 - SLICE_X62Y63 FDPE (Recov_AFF_SLICEL_C_PRE) - -0.066 8.273 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.630 8.243 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk + SLICE_X59Y66 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/C + clock pessimism 0.158 8.401 + clock uncertainty -0.046 8.355 + SLICE_X59Y66 FDPE (Recov_CFF2_SLICEL_C_PRE) + -0.066 8.289 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0] ------------------------------------------------------------------- - required time 8.273 - arrival time -2.647 + required time 8.289 + arrival time -2.643 ------------------------------------------------------------------- - slack 5.626 + slack 5.646 -Slack (MET) : 5.626ns (required time - arrival time) +Slack (MET) : 5.646ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR (recovery check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.581ns (logic 0.080ns (13.769%) route 0.501ns (86.231%)) + Data Path Delay: 0.577ns (logic 0.080ns (13.865%) route 0.497ns (86.135%)) Logic Levels: 0 - Clock Path Skew: -0.081ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.827ns = ( 8.227 - 6.400 ) + Clock Path Skew: -0.065ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.843ns = ( 8.243 - 6.400 ) Source Clock Delay (SCD): 2.066ns Clock Pessimism Removal (CPR): 0.158ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -8436,7 +8219,7 @@ Slack (MET) : 5.626ns (required time - arrival time) Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.823ns (routing 0.508ns, distribution 1.315ns) - Clock Net Delay (Destination): 1.614ns (routing 0.454ns, distribution 1.160ns) + Clock Net Delay (Destination): 1.630ns (routing 0.454ns, distribution 1.176ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -8451,8 +8234,8 @@ Slack (MET) : 5.626ns (required time - arrival time) ------------------------------------------------------------------- ------------------- SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) 0.080 2.146 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.501 2.647 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0 - SLICE_X62Y63 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE + net (fo=21, routed) 0.497 2.643 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 + SLICE_X59Y66 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -8461,30 +8244,30 @@ Slack (MET) : 5.626ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.614 8.227 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/s_aclk - SLICE_X62Y63 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/C - clock pessimism 0.158 8.385 - clock uncertainty -0.046 8.339 - SLICE_X62Y63 FDPE (Recov_DFF2_SLICEL_C_PRE) - -0.066 8.273 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.630 8.243 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk + SLICE_X59Y66 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/C + clock pessimism 0.158 8.401 + clock uncertainty -0.046 8.355 + SLICE_X59Y66 FDCE (Recov_BFF2_SLICEL_C_CLR) + -0.066 8.289 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1] ------------------------------------------------------------------- - required time 8.273 - arrival time -2.647 + required time 8.289 + arrival time -2.643 ------------------------------------------------------------------- - slack 5.626 + slack 5.646 -Slack (MET) : 5.626ns (required time - arrival time) +Slack (MET) : 5.646ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR (recovery check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.581ns (logic 0.080ns (13.769%) route 0.501ns (86.231%)) + Data Path Delay: 0.577ns (logic 0.080ns (13.865%) route 0.497ns (86.135%)) Logic Levels: 0 - Clock Path Skew: -0.081ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.827ns = ( 8.227 - 6.400 ) + Clock Path Skew: -0.065ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.843ns = ( 8.243 - 6.400 ) Source Clock Delay (SCD): 2.066ns Clock Pessimism Removal (CPR): 0.158ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -8492,7 +8275,7 @@ Slack (MET) : 5.626ns (required time - arrival time) Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.823ns (routing 0.508ns, distribution 1.315ns) - Clock Net Delay (Destination): 1.614ns (routing 0.454ns, distribution 1.160ns) + Clock Net Delay (Destination): 1.630ns (routing 0.454ns, distribution 1.176ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -8507,8 +8290,8 @@ Slack (MET) : 5.626ns (required time - arrival time) ------------------------------------------------------------------- ------------------- SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) 0.080 2.146 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.501 2.647 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0 - SLICE_X62Y63 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE + net (fo=21, routed) 0.497 2.643 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 + SLICE_X59Y66 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -8517,30 +8300,30 @@ Slack (MET) : 5.626ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.614 8.227 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/s_aclk - SLICE_X62Y63 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/C - clock pessimism 0.158 8.385 - clock uncertainty -0.046 8.339 - SLICE_X62Y63 FDPE (Recov_AFF2_SLICEL_C_PRE) - -0.066 8.273 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.630 8.243 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk + SLICE_X59Y66 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/C + clock pessimism 0.158 8.401 + clock uncertainty -0.046 8.355 + SLICE_X59Y66 FDCE (Recov_DFF_SLICEL_C_CLR) + -0.066 8.289 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2] ------------------------------------------------------------------- - required time 8.273 - arrival time -2.647 + required time 8.289 + arrival time -2.643 ------------------------------------------------------------------- - slack 5.626 + slack 5.646 -Slack (MET) : 5.626ns (required time - arrival time) +Slack (MET) : 5.646ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR (recovery check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.581ns (logic 0.080ns (13.769%) route 0.501ns (86.231%)) + Data Path Delay: 0.577ns (logic 0.080ns (13.865%) route 0.497ns (86.135%)) Logic Levels: 0 - Clock Path Skew: -0.081ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.827ns = ( 8.227 - 6.400 ) + Clock Path Skew: -0.065ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.843ns = ( 8.243 - 6.400 ) Source Clock Delay (SCD): 2.066ns Clock Pessimism Removal (CPR): 0.158ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -8548,7 +8331,7 @@ Slack (MET) : 5.626ns (required time - arrival time) Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.823ns (routing 0.508ns, distribution 1.315ns) - Clock Net Delay (Destination): 1.614ns (routing 0.454ns, distribution 1.160ns) + Clock Net Delay (Destination): 1.630ns (routing 0.454ns, distribution 1.176ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -8563,8 +8346,8 @@ Slack (MET) : 5.626ns (required time - arrival time) ------------------------------------------------------------------- ------------------- SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) 0.080 2.146 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.501 2.647 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0 - SLICE_X62Y63 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR + net (fo=21, routed) 0.497 2.643 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 + SLICE_X59Y66 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -8573,30 +8356,30 @@ Slack (MET) : 5.626ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.614 8.227 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/s_aclk - SLICE_X62Y63 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/C - clock pessimism 0.158 8.385 - clock uncertainty -0.046 8.339 - SLICE_X62Y63 FDCE (Recov_CFF_SLICEL_C_CLR) - -0.066 8.273 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.630 8.243 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk + SLICE_X59Y66 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/C + clock pessimism 0.158 8.401 + clock uncertainty -0.046 8.355 + SLICE_X59Y66 FDCE (Recov_DFF2_SLICEL_C_CLR) + -0.066 8.289 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3] ------------------------------------------------------------------- - required time 8.273 - arrival time -2.647 + required time 8.289 + arrival time -2.643 ------------------------------------------------------------------- - slack 5.626 + slack 5.646 -Slack (MET) : 5.626ns (required time - arrival time) +Slack (MET) : 5.649ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/PRE (recovery check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.581ns (logic 0.080ns (13.769%) route 0.501ns (86.231%)) + Data Path Delay: 0.576ns (logic 0.080ns (13.889%) route 0.496ns (86.111%)) Logic Levels: 0 - Clock Path Skew: -0.081ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.827ns = ( 8.227 - 6.400 ) + Clock Path Skew: -0.063ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.845ns = ( 8.245 - 6.400 ) Source Clock Delay (SCD): 2.066ns Clock Pessimism Removal (CPR): 0.158ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -8604,7 +8387,7 @@ Slack (MET) : 5.626ns (required time - arrival time) Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.823ns (routing 0.508ns, distribution 1.315ns) - Clock Net Delay (Destination): 1.614ns (routing 0.454ns, distribution 1.160ns) + Clock Net Delay (Destination): 1.632ns (routing 0.454ns, distribution 1.178ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -8619,8 +8402,8 @@ Slack (MET) : 5.626ns (required time - arrival time) ------------------------------------------------------------------- ------------------- SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) 0.080 2.146 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.501 2.647 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0 - SLICE_X62Y63 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR + net (fo=21, routed) 0.496 2.642 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg_0 + SLICE_X59Y66 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/PRE ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -8629,30 +8412,30 @@ Slack (MET) : 5.626ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.614 8.227 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/s_aclk - SLICE_X62Y63 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/C - clock pessimism 0.158 8.385 - clock uncertainty -0.046 8.339 - SLICE_X62Y63 FDCE (Recov_CFF2_SLICEL_C_CLR) - -0.066 8.273 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.632 8.245 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/s_aclk + SLICE_X59Y66 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/C + clock pessimism 0.158 8.403 + clock uncertainty -0.046 8.357 + SLICE_X59Y66 FDPE (Recov_HFF_SLICEL_C_PRE) + -0.066 8.291 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg ------------------------------------------------------------------- - required time 8.273 - arrival time -2.647 + required time 8.291 + arrival time -2.642 ------------------------------------------------------------------- - slack 5.626 + slack 5.649 -Slack (MET) : 5.626ns (required time - arrival time) +Slack (MET) : 5.649ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/PRE (recovery check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.581ns (logic 0.080ns (13.769%) route 0.501ns (86.231%)) + Data Path Delay: 0.576ns (logic 0.080ns (13.889%) route 0.496ns (86.111%)) Logic Levels: 0 - Clock Path Skew: -0.081ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.827ns = ( 8.227 - 6.400 ) + Clock Path Skew: -0.063ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.845ns = ( 8.245 - 6.400 ) Source Clock Delay (SCD): 2.066ns Clock Pessimism Removal (CPR): 0.158ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -8660,7 +8443,7 @@ Slack (MET) : 5.626ns (required time - arrival time) Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.823ns (routing 0.508ns, distribution 1.315ns) - Clock Net Delay (Destination): 1.614ns (routing 0.454ns, distribution 1.160ns) + Clock Net Delay (Destination): 1.632ns (routing 0.454ns, distribution 1.178ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -8675,8 +8458,8 @@ Slack (MET) : 5.626ns (required time - arrival time) ------------------------------------------------------------------- ------------------- SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) 0.080 2.146 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.501 2.647 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0 - SLICE_X62Y63 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR + net (fo=21, routed) 0.496 2.642 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg_0 + SLICE_X59Y66 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/PRE ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -8685,30 +8468,30 @@ Slack (MET) : 5.626ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.614 8.227 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/s_aclk - SLICE_X62Y63 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/C - clock pessimism 0.158 8.385 - clock uncertainty -0.046 8.339 - SLICE_X62Y63 FDCE (Recov_BFF2_SLICEL_C_CLR) - -0.066 8.273 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.632 8.245 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/s_aclk + SLICE_X59Y66 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C + clock pessimism 0.158 8.403 + clock uncertainty -0.046 8.357 + SLICE_X59Y66 FDPE (Recov_GFF_SLICEL_C_PRE) + -0.066 8.291 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg ------------------------------------------------------------------- - required time 8.273 - arrival time -2.647 + required time 8.291 + arrival time -2.642 ------------------------------------------------------------------- - slack 5.626 + slack 5.649 -Slack (MET) : 5.629ns (required time - arrival time) +Slack (MET) : 5.649ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR (recovery check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.580ns (logic 0.080ns (13.793%) route 0.500ns (86.207%)) + Data Path Delay: 0.576ns (logic 0.080ns (13.889%) route 0.496ns (86.111%)) Logic Levels: 0 - Clock Path Skew: -0.079ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.829ns = ( 8.229 - 6.400 ) + Clock Path Skew: -0.063ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.845ns = ( 8.245 - 6.400 ) Source Clock Delay (SCD): 2.066ns Clock Pessimism Removal (CPR): 0.158ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -8716,7 +8499,7 @@ Slack (MET) : 5.629ns (required time - arrival time) Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.823ns (routing 0.508ns, distribution 1.315ns) - Clock Net Delay (Destination): 1.616ns (routing 0.454ns, distribution 1.162ns) + Clock Net Delay (Destination): 1.632ns (routing 0.454ns, distribution 1.178ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -8731,8 +8514,8 @@ Slack (MET) : 5.629ns (required time - arrival time) ------------------------------------------------------------------- ------------------- SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) 0.080 2.146 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.500 2.646 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0 - SLICE_X62Y63 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE + net (fo=21, routed) 0.496 2.642 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 + SLICE_X59Y66 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -8741,30 +8524,30 @@ Slack (MET) : 5.629ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.616 8.229 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/s_aclk - SLICE_X62Y63 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/C - clock pessimism 0.158 8.387 - clock uncertainty -0.046 8.341 - SLICE_X62Y63 FDPE (Recov_EFF_SLICEL_C_PRE) - -0.066 8.275 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.632 8.245 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk + SLICE_X59Y66 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/C + clock pessimism 0.158 8.403 + clock uncertainty -0.046 8.357 + SLICE_X59Y66 FDCE (Recov_HFF2_SLICEL_C_CLR) + -0.066 8.291 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0] ------------------------------------------------------------------- - required time 8.275 - arrival time -2.646 + required time 8.291 + arrival time -2.642 ------------------------------------------------------------------- - slack 5.629 + slack 5.649 -Slack (MET) : 5.629ns (required time - arrival time) +Slack (MET) : 5.649ns (required time - arrival time) Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR (recovery check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.580ns (logic 0.080ns (13.793%) route 0.500ns (86.207%)) + Data Path Delay: 0.576ns (logic 0.080ns (13.889%) route 0.496ns (86.111%)) Logic Levels: 0 - Clock Path Skew: -0.079ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 1.829ns = ( 8.229 - 6.400 ) + Clock Path Skew: -0.063ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.845ns = ( 8.245 - 6.400 ) Source Clock Delay (SCD): 2.066ns Clock Pessimism Removal (CPR): 0.158ns Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -8772,7 +8555,7 @@ Slack (MET) : 5.629ns (required time - arrival time) Discrete Jitter (DJ): 0.060ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.823ns (routing 0.508ns, distribution 1.315ns) - Clock Net Delay (Destination): 1.616ns (routing 0.454ns, distribution 1.162ns) + Clock Net Delay (Destination): 1.632ns (routing 0.454ns, distribution 1.178ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -8787,8 +8570,8 @@ Slack (MET) : 5.629ns (required time - arrival time) ------------------------------------------------------------------- ------------------- SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) 0.080 2.146 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.500 2.646 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0 - SLICE_X62Y63 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE + net (fo=21, routed) 0.496 2.642 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 + SLICE_X59Y66 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -8797,17 +8580,129 @@ Slack (MET) : 5.629ns (required time - arrival time) net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.616 8.229 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/s_aclk - SLICE_X62Y63 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/C - clock pessimism 0.158 8.387 - clock uncertainty -0.046 8.341 - SLICE_X62Y63 FDPE (Recov_EFF2_SLICEL_C_PRE) - -0.066 8.275 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.632 8.245 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk + SLICE_X59Y66 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/C + clock pessimism 0.158 8.403 + clock uncertainty -0.046 8.357 + SLICE_X59Y66 FDCE (Recov_GFF2_SLICEL_C_CLR) + -0.066 8.291 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1] ------------------------------------------------------------------- - required time 8.275 - arrival time -2.646 + required time 8.291 + arrival time -2.642 ------------------------------------------------------------------- - slack 5.629 + slack 5.649 + +Slack (MET) : 5.649ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR + (recovery check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) + Data Path Delay: 0.576ns (logic 0.080ns (13.889%) route 0.496ns (86.111%)) + Logic Levels: 0 + Clock Path Skew: -0.063ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.845ns = ( 8.245 - 6.400 ) + Source Clock Delay (SCD): 2.066ns + Clock Pessimism Removal (CPR): 0.158ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.823ns (routing 0.508ns, distribution 1.315ns) + Clock Net Delay (Destination): 1.632ns (routing 0.454ns, distribution 1.178ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.823 2.066 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/s_aclk + SLICE_X64Y65 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) + 0.080 2.146 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q + net (fo=21, routed) 0.496 2.642 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 + SLICE_X59Y66 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.632 8.245 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk + SLICE_X59Y66 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/C + clock pessimism 0.158 8.403 + clock uncertainty -0.046 8.357 + SLICE_X59Y66 FDCE (Recov_FFF2_SLICEL_C_CLR) + -0.066 8.291 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2] + ------------------------------------------------------------------- + required time 8.291 + arrival time -2.642 + ------------------------------------------------------------------- + slack 5.649 + +Slack (MET) : 5.649ns (required time - arrival time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR + (recovery check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 6.400ns (xxv_ethernet_0_tx_clk_out_0 rise@6.400ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) + Data Path Delay: 0.576ns (logic 0.080ns (13.889%) route 0.496ns (86.111%)) + Logic Levels: 0 + Clock Path Skew: -0.063ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.845ns = ( 8.245 - 6.400 ) + Source Clock Delay (SCD): 2.066ns + Clock Pessimism Removal (CPR): 0.158ns + Clock Uncertainty: 0.046ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.060ns + Phase Error (PE): 0.000ns + Clock Net Delay (Source): 1.823ns (routing 0.508ns, distribution 1.315ns) + Clock Net Delay (Destination): 1.632ns (routing 0.454ns, distribution 1.178ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.113 0.113 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.130 0.243 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.823 2.066 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/s_aclk + SLICE_X64Y65 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) + 0.080 2.146 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q + net (fo=21, routed) 0.496 2.642 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 + SLICE_X59Y66 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 6.400 6.400 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 6.400 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.099 6.499 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.114 6.613 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.632 8.245 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk + SLICE_X59Y66 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/C + clock pessimism 0.158 8.403 + clock uncertainty -0.046 8.357 + SLICE_X59Y66 FDCE (Recov_EFF2_SLICEL_C_CLR) + -0.066 8.291 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3] + ------------------------------------------------------------------- + required time 8.291 + arrival time -2.642 + ------------------------------------------------------------------- + slack 5.649 @@ -8815,225 +8710,21 @@ Slack (MET) : 5.629ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.149ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C +Slack (MET) : 0.154ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR (removal check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.184ns (logic 0.041ns (22.283%) route 0.143ns (77.717%)) + Data Path Delay: 0.150ns (logic 0.040ns (26.667%) route 0.110ns (73.333%)) Logic Levels: 0 - Clock Path Skew: 0.055ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.318ns - Source Clock Delay (SCD): 1.156ns - Clock Pessimism Removal (CPR): 0.107ns - Clock Net Delay (Source): 1.010ns (routing 0.285ns, distribution 0.725ns) - Clock Net Delay (Destination): 1.151ns (routing 0.323ns, distribution 0.828ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.073 0.073 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.073 0.146 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.010 1.156 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/s_aclk - SLICE_X64Y65 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.197 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.143 1.340 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X62Y65 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.085 0.085 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.082 0.167 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.151 1.318 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk - SLICE_X62Y65 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/C - clock pessimism -0.107 1.211 - SLICE_X62Y65 FDCE (Remov_EFF_SLICEL_C_CLR) - -0.020 1.191 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0] - ------------------------------------------------------------------- - required time -1.191 - arrival time 1.340 - ------------------------------------------------------------------- - slack 0.149 - -Slack (MET) : 0.149ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C - (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR - (removal check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.184ns (logic 0.041ns (22.283%) route 0.143ns (77.717%)) - Logic Levels: 0 - Clock Path Skew: 0.055ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.318ns - Source Clock Delay (SCD): 1.156ns - Clock Pessimism Removal (CPR): 0.107ns - Clock Net Delay (Source): 1.010ns (routing 0.285ns, distribution 0.725ns) - Clock Net Delay (Destination): 1.151ns (routing 0.323ns, distribution 0.828ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.073 0.073 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.073 0.146 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.010 1.156 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/s_aclk - SLICE_X64Y65 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.197 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.143 1.340 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X62Y65 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.085 0.085 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.082 0.167 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.151 1.318 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk - SLICE_X62Y65 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/C - clock pessimism -0.107 1.211 - SLICE_X62Y65 FDCE (Remov_EFF2_SLICEL_C_CLR) - -0.020 1.191 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1] - ------------------------------------------------------------------- - required time -1.191 - arrival time 1.340 - ------------------------------------------------------------------- - slack 0.149 - -Slack (MET) : 0.149ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C - (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR - (removal check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.184ns (logic 0.041ns (22.283%) route 0.143ns (77.717%)) - Logic Levels: 0 - Clock Path Skew: 0.055ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.318ns - Source Clock Delay (SCD): 1.156ns - Clock Pessimism Removal (CPR): 0.107ns - Clock Net Delay (Source): 1.010ns (routing 0.285ns, distribution 0.725ns) - Clock Net Delay (Destination): 1.151ns (routing 0.323ns, distribution 0.828ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.073 0.073 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.073 0.146 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.010 1.156 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/s_aclk - SLICE_X64Y65 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.197 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.143 1.340 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X62Y65 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.085 0.085 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.082 0.167 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.151 1.318 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk - SLICE_X62Y65 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/C - clock pessimism -0.107 1.211 - SLICE_X62Y65 FDCE (Remov_FFF_SLICEL_C_CLR) - -0.020 1.191 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2] - ------------------------------------------------------------------- - required time -1.191 - arrival time 1.340 - ------------------------------------------------------------------- - slack 0.149 - -Slack (MET) : 0.149ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C - (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR - (removal check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.184ns (logic 0.041ns (22.283%) route 0.143ns (77.717%)) - Logic Levels: 0 - Clock Path Skew: 0.055ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.318ns - Source Clock Delay (SCD): 1.156ns - Clock Pessimism Removal (CPR): 0.107ns - Clock Net Delay (Source): 1.010ns (routing 0.285ns, distribution 0.725ns) - Clock Net Delay (Destination): 1.151ns (routing 0.323ns, distribution 0.828ns) - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.073 0.073 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.073 0.146 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.010 1.156 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/s_aclk - SLICE_X64Y65 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.197 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.143 1.340 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X62Y65 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock xxv_ethernet_0_tx_clk_out_0 rise edge) - 0.000 0.000 r - GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK - net (fo=3, routed) 0.085 0.085 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] - BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) - 0.082 0.167 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.151 1.318 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk - SLICE_X62Y65 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/C - clock pessimism -0.107 1.211 - SLICE_X62Y65 FDCE (Remov_FFF2_SLICEL_C_CLR) - -0.020 1.191 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3] - ------------------------------------------------------------------- - required time -1.191 - arrival time 1.340 - ------------------------------------------------------------------- - slack 0.149 - -Slack (MET) : 0.153ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C - (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/PRE - (removal check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.184ns (logic 0.041ns (22.283%) route 0.143ns (77.717%)) - Logic Levels: 0 - Clock Path Skew: 0.051ns (DCD - SCD - CPR) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.314ns - Source Clock Delay (SCD): 1.156ns - Clock Pessimism Removal (CPR): 0.107ns - Clock Net Delay (Source): 1.010ns (routing 0.285ns, distribution 0.725ns) + Source Clock Delay (SCD): 1.160ns + Clock Pessimism Removal (CPR): 0.138ns + Clock Net Delay (Source): 1.014ns (routing 0.285ns, distribution 0.729ns) Clock Net Delay (Destination): 1.147ns (routing 0.323ns, distribution 0.824ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -9044,13 +8735,13 @@ Slack (MET) : 0.153ns (arrival time - required time) net (fo=3, routed) 0.073 0.073 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.073 0.146 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.010 1.156 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/s_aclk - SLICE_X64Y65 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.014 1.160 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk + SLICE_X65Y63 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.197 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.143 1.340 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X62Y65 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/PRE + SLICE_X65Y63 FDPE (Prop_CFF2_SLICEL_C_Q) + 0.040 1.200 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.110 1.310 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y62 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -9059,32 +8750,32 @@ Slack (MET) : 0.153ns (arrival time - required time) net (fo=3, routed) 0.085 0.085 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.082 0.167 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.147 1.314 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk - SLICE_X62Y65 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/C - clock pessimism -0.107 1.207 - SLICE_X62Y65 FDPE (Remov_CFF2_SLICEL_C_PRE) - -0.020 1.187 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.147 1.314 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y62 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/C + clock pessimism -0.138 1.176 + SLICE_X64Y62 FDCE (Remov_CFF2_SLICEM_C_CLR) + -0.020 1.156 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0] ------------------------------------------------------------------- - required time -1.187 - arrival time 1.340 + required time -1.156 + arrival time 1.310 ------------------------------------------------------------------- - slack 0.153 + slack 0.154 -Slack (MET) : 0.153ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C +Slack (MET) : 0.154ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE (removal check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.184ns (logic 0.041ns (22.283%) route 0.143ns (77.717%)) + Data Path Delay: 0.150ns (logic 0.040ns (26.667%) route 0.110ns (73.333%)) Logic Levels: 0 - Clock Path Skew: 0.051ns (DCD - SCD - CPR) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.314ns - Source Clock Delay (SCD): 1.156ns - Clock Pessimism Removal (CPR): 0.107ns - Clock Net Delay (Source): 1.010ns (routing 0.285ns, distribution 0.725ns) + Source Clock Delay (SCD): 1.160ns + Clock Pessimism Removal (CPR): 0.138ns + Clock Net Delay (Source): 1.014ns (routing 0.285ns, distribution 0.729ns) Clock Net Delay (Destination): 1.147ns (routing 0.323ns, distribution 0.824ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -9095,13 +8786,13 @@ Slack (MET) : 0.153ns (arrival time - required time) net (fo=3, routed) 0.073 0.073 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.073 0.146 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.010 1.156 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/s_aclk - SLICE_X64Y65 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.014 1.160 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk + SLICE_X65Y63 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.197 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.143 1.340 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X62Y65 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR + SLICE_X65Y63 FDPE (Prop_CFF2_SLICEL_C_Q) + 0.040 1.200 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.110 1.310 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y62 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -9110,32 +8801,32 @@ Slack (MET) : 0.153ns (arrival time - required time) net (fo=3, routed) 0.085 0.085 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.082 0.167 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.147 1.314 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk - SLICE_X62Y65 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/C - clock pessimism -0.107 1.207 - SLICE_X62Y65 FDCE (Remov_BFF2_SLICEL_C_CLR) - -0.020 1.187 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.147 1.314 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y62 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/C + clock pessimism -0.138 1.176 + SLICE_X64Y62 FDPE (Remov_BFF2_SLICEM_C_PRE) + -0.020 1.156 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1] ------------------------------------------------------------------- - required time -1.187 - arrival time 1.340 + required time -1.156 + arrival time 1.310 ------------------------------------------------------------------- - slack 0.153 + slack 0.154 -Slack (MET) : 0.153ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C +Slack (MET) : 0.154ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/CLR (removal check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.184ns (logic 0.041ns (22.283%) route 0.143ns (77.717%)) + Data Path Delay: 0.150ns (logic 0.040ns (26.667%) route 0.110ns (73.333%)) Logic Levels: 0 - Clock Path Skew: 0.051ns (DCD - SCD - CPR) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.314ns - Source Clock Delay (SCD): 1.156ns - Clock Pessimism Removal (CPR): 0.107ns - Clock Net Delay (Source): 1.010ns (routing 0.285ns, distribution 0.725ns) + Source Clock Delay (SCD): 1.160ns + Clock Pessimism Removal (CPR): 0.138ns + Clock Net Delay (Source): 1.014ns (routing 0.285ns, distribution 0.729ns) Clock Net Delay (Destination): 1.147ns (routing 0.323ns, distribution 0.824ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -9146,13 +8837,13 @@ Slack (MET) : 0.153ns (arrival time - required time) net (fo=3, routed) 0.073 0.073 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.073 0.146 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.010 1.156 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/s_aclk - SLICE_X64Y65 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.014 1.160 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk + SLICE_X65Y63 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.197 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.143 1.340 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X62Y65 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR + SLICE_X65Y63 FDPE (Prop_CFF2_SLICEL_C_Q) + 0.040 1.200 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.110 1.310 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y62 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -9161,32 +8852,32 @@ Slack (MET) : 0.153ns (arrival time - required time) net (fo=3, routed) 0.085 0.085 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.082 0.167 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.147 1.314 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk - SLICE_X62Y65 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/C - clock pessimism -0.107 1.207 - SLICE_X62Y65 FDCE (Remov_DFF_SLICEL_C_CLR) - -0.020 1.187 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.147 1.314 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y62 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/C + clock pessimism -0.138 1.176 + SLICE_X64Y62 FDCE (Remov_DFF_SLICEM_C_CLR) + -0.020 1.156 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2] ------------------------------------------------------------------- - required time -1.187 - arrival time 1.340 + required time -1.156 + arrival time 1.310 ------------------------------------------------------------------- - slack 0.153 + slack 0.154 -Slack (MET) : 0.153ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C +Slack (MET) : 0.154ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/CLR (removal check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.184ns (logic 0.041ns (22.283%) route 0.143ns (77.717%)) + Data Path Delay: 0.150ns (logic 0.040ns (26.667%) route 0.110ns (73.333%)) Logic Levels: 0 - Clock Path Skew: 0.051ns (DCD - SCD - CPR) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.314ns - Source Clock Delay (SCD): 1.156ns - Clock Pessimism Removal (CPR): 0.107ns - Clock Net Delay (Source): 1.010ns (routing 0.285ns, distribution 0.725ns) + Source Clock Delay (SCD): 1.160ns + Clock Pessimism Removal (CPR): 0.138ns + Clock Net Delay (Source): 1.014ns (routing 0.285ns, distribution 0.729ns) Clock Net Delay (Destination): 1.147ns (routing 0.323ns, distribution 0.824ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -9197,13 +8888,13 @@ Slack (MET) : 0.153ns (arrival time - required time) net (fo=3, routed) 0.073 0.073 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.073 0.146 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.010 1.156 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/s_aclk - SLICE_X64Y65 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.014 1.160 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk + SLICE_X65Y63 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y65 FDPE (Prop_DFF2_SLICEM_C_Q) - 0.041 1.197 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/Q - net (fo=21, routed) 0.143 1.340 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]_0 - SLICE_X62Y65 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR + SLICE_X65Y63 FDPE (Prop_CFF2_SLICEL_C_Q) + 0.040 1.200 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.110 1.310 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y62 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -9212,33 +8903,33 @@ Slack (MET) : 0.153ns (arrival time - required time) net (fo=3, routed) 0.085 0.085 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.082 0.167 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.147 1.314 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_aclk - SLICE_X62Y65 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/C - clock pessimism -0.107 1.207 - SLICE_X62Y65 FDCE (Remov_DFF2_SLICEL_C_CLR) - -0.020 1.187 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3] + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.147 1.314 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y62 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/C + clock pessimism -0.138 1.176 + SLICE_X64Y62 FDCE (Remov_DFF2_SLICEM_C_CLR) + -0.020 1.156 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3] ------------------------------------------------------------------- - required time -1.187 - arrival time 1.340 + required time -1.156 + arrival time 1.310 ------------------------------------------------------------------- - slack 0.153 + slack 0.154 -Slack (MET) : 0.160ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C +Slack (MET) : 0.155ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg/PRE + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE (removal check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.163ns (logic 0.039ns (23.926%) route 0.124ns (76.074%)) + Data Path Delay: 0.149ns (logic 0.040ns (26.846%) route 0.109ns (73.154%)) Logic Levels: 0 - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.332ns - Source Clock Delay (SCD): 1.166ns - Clock Pessimism Removal (CPR): 0.143ns - Clock Net Delay (Source): 1.020ns (routing 0.285ns, distribution 0.735ns) - Clock Net Delay (Destination): 1.165ns (routing 0.323ns, distribution 0.842ns) + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.312ns + Source Clock Delay (SCD): 1.160ns + Clock Pessimism Removal (CPR): 0.138ns + Clock Net Delay (Source): 1.014ns (routing 0.285ns, distribution 0.729ns) + Clock Net Delay (Destination): 1.145ns (routing 0.323ns, distribution 0.822ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -9248,13 +8939,13 @@ Slack (MET) : 0.160ns (arrival time - required time) net (fo=3, routed) 0.073 0.073 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.073 0.146 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.020 1.166 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk - SLICE_X64Y56 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.014 1.160 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk + SLICE_X65Y63 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y56 FDPE (Prop_AFF2_SLICEM_C_Q) - 0.039 1.205 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q - net (fo=9, routed) 0.124 1.329 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/rst_wr_reg2 - SLICE_X64Y57 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg/PRE + SLICE_X65Y63 FDPE (Prop_CFF2_SLICEL_C_Q) + 0.040 1.200 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.109 1.309 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y62 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -9263,33 +8954,33 @@ Slack (MET) : 0.160ns (arrival time - required time) net (fo=3, routed) 0.085 0.085 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.082 0.167 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.165 1.332 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk - SLICE_X64Y57 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg/C - clock pessimism -0.143 1.189 - SLICE_X64Y57 FDPE (Remov_BFF2_SLICEM_C_PRE) - -0.020 1.169 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.145 1.312 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y62 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/C + clock pessimism -0.138 1.174 + SLICE_X64Y62 FDPE (Remov_EFF_SLICEM_C_PRE) + -0.020 1.154 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0] ------------------------------------------------------------------- - required time -1.169 - arrival time 1.329 + required time -1.154 + arrival time 1.309 ------------------------------------------------------------------- - slack 0.160 + slack 0.155 -Slack (MET) : 0.160ns (arrival time - required time) - Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C +Slack (MET) : 0.155ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) - Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/PRE + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR (removal check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) - Data Path Delay: 0.163ns (logic 0.039ns (23.926%) route 0.124ns (76.074%)) + Data Path Delay: 0.149ns (logic 0.040ns (26.846%) route 0.109ns (73.154%)) Logic Levels: 0 - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.332ns - Source Clock Delay (SCD): 1.166ns - Clock Pessimism Removal (CPR): 0.143ns - Clock Net Delay (Source): 1.020ns (routing 0.285ns, distribution 0.735ns) - Clock Net Delay (Destination): 1.165ns (routing 0.323ns, distribution 0.842ns) + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.312ns + Source Clock Delay (SCD): 1.160ns + Clock Pessimism Removal (CPR): 0.138ns + Clock Net Delay (Source): 1.014ns (routing 0.285ns, distribution 0.729ns) + Clock Net Delay (Destination): 1.145ns (routing 0.323ns, distribution 0.822ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -9299,13 +8990,13 @@ Slack (MET) : 0.160ns (arrival time - required time) net (fo=3, routed) 0.073 0.073 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.073 0.146 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.020 1.166 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk - SLICE_X64Y56 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.014 1.160 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk + SLICE_X65Y63 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X64Y56 FDPE (Prop_AFF2_SLICEM_C_Q) - 0.039 1.205 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q - net (fo=9, routed) 0.124 1.329 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/rst_wr_reg2 - SLICE_X64Y57 FDPE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/PRE + SLICE_X65Y63 FDPE (Prop_CFF2_SLICEL_C_Q) + 0.040 1.200 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.109 1.309 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y62 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock xxv_ethernet_0_tx_clk_out_0 rise edge) @@ -9314,16 +9005,220 @@ Slack (MET) : 0.160ns (arrival time - required time) net (fo=3, routed) 0.085 0.085 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) 0.082 0.167 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O - X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.165 1.332 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk - SLICE_X64Y57 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C - clock pessimism -0.143 1.189 - SLICE_X64Y57 FDPE (Remov_AFF2_SLICEM_C_PRE) - -0.020 1.169 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.145 1.312 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y62 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/C + clock pessimism -0.138 1.174 + SLICE_X64Y62 FDCE (Remov_EFF2_SLICEM_C_CLR) + -0.020 1.154 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1] ------------------------------------------------------------------- - required time -1.169 - arrival time 1.329 + required time -1.154 + arrival time 1.309 ------------------------------------------------------------------- - slack 0.160 + slack 0.155 + +Slack (MET) : 0.155ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR + (removal check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) + Data Path Delay: 0.149ns (logic 0.040ns (26.846%) route 0.109ns (73.154%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.312ns + Source Clock Delay (SCD): 1.160ns + Clock Pessimism Removal (CPR): 0.138ns + Clock Net Delay (Source): 1.014ns (routing 0.285ns, distribution 0.729ns) + Clock Net Delay (Destination): 1.145ns (routing 0.323ns, distribution 0.822ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.073 0.073 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.073 0.146 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.014 1.160 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk + SLICE_X65Y63 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y63 FDPE (Prop_CFF2_SLICEL_C_Q) + 0.040 1.200 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.109 1.309 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y62 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.085 0.085 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.082 0.167 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.145 1.312 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y62 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/C + clock pessimism -0.138 1.174 + SLICE_X64Y62 FDCE (Remov_FFF_SLICEM_C_CLR) + -0.020 1.154 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2] + ------------------------------------------------------------------- + required time -1.154 + arrival time 1.309 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR + (removal check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) + Data Path Delay: 0.149ns (logic 0.040ns (26.846%) route 0.109ns (73.154%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.312ns + Source Clock Delay (SCD): 1.160ns + Clock Pessimism Removal (CPR): 0.138ns + Clock Net Delay (Source): 1.014ns (routing 0.285ns, distribution 0.729ns) + Clock Net Delay (Destination): 1.145ns (routing 0.323ns, distribution 0.822ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.073 0.073 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.073 0.146 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.014 1.160 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk + SLICE_X65Y63 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y63 FDPE (Prop_CFF2_SLICEL_C_Q) + 0.040 1.200 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.109 1.309 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y62 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.085 0.085 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.082 0.167 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.145 1.312 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y62 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/C + clock pessimism -0.138 1.174 + SLICE_X64Y62 FDCE (Remov_FFF2_SLICEM_C_CLR) + -0.020 1.154 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3] + ------------------------------------------------------------------- + required time -1.154 + arrival time 1.309 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR + (removal check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) + Data Path Delay: 0.149ns (logic 0.040ns (26.846%) route 0.109ns (73.154%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.312ns + Source Clock Delay (SCD): 1.160ns + Clock Pessimism Removal (CPR): 0.138ns + Clock Net Delay (Source): 1.014ns (routing 0.285ns, distribution 0.729ns) + Clock Net Delay (Destination): 1.145ns (routing 0.323ns, distribution 0.822ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.073 0.073 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.073 0.146 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.014 1.160 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk + SLICE_X65Y63 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y63 FDPE (Prop_CFF2_SLICEL_C_Q) + 0.040 1.200 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.109 1.309 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y62 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.085 0.085 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.082 0.167 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.145 1.312 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y62 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/C + clock pessimism -0.138 1.174 + SLICE_X64Y62 FDCE (Remov_GFF_SLICEM_C_CLR) + -0.020 1.154 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0] + ------------------------------------------------------------------- + required time -1.154 + arrival time 1.309 + ------------------------------------------------------------------- + slack 0.155 + +Slack (MET) : 0.155ns (arrival time - required time) + Source: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Destination: pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/CLR + (removal check against rising-edge clock xxv_ethernet_0_tx_clk_out_0 {rise@0.000ns fall@3.200ns period=6.400ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (xxv_ethernet_0_tx_clk_out_0 rise@0.000ns - xxv_ethernet_0_tx_clk_out_0 rise@0.000ns) + Data Path Delay: 0.149ns (logic 0.040ns (26.846%) route 0.109ns (73.154%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.312ns + Source Clock Delay (SCD): 1.160ns + Clock Pessimism Removal (CPR): 0.138ns + Clock Net Delay (Source): 1.014ns (routing 0.285ns, distribution 0.729ns) + Clock Net Delay (Destination): 1.145ns (routing 0.323ns, distribution 0.822ns) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.073 0.073 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.073 0.146 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.014 1.160 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk + SLICE_X65Y63 FDPE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y63 FDPE (Prop_CFF2_SLICEL_C_Q) + 0.040 1.200 f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.109 1.309 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X64Y62 FDCE f pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock xxv_ethernet_0_tx_clk_out_0 rise edge) + 0.000 0.000 r + GTHE4_CHANNEL_X0Y10 GTHE4_CHANNEL 0.000 0.000 r pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK + net (fo=3, routed) 0.085 0.085 pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/txoutclk_out[0] + BUFG_GT_X0Y48 BUFG_GT (Prop_BUFG_GT_I_O) + 0.082 0.167 r pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O + X2Y2 (CLOCK_ROOT) net (fo=9138, routed) 1.145 1.312 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X64Y62 FDCE r pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C + clock pessimism -0.138 1.174 + SLICE_X64Y62 FDCE (Remov_GFF2_SLICEM_C_CLR) + -0.020 1.154 pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1] + ------------------------------------------------------------------- + required time -1.154 + arrival time 1.309 + ------------------------------------------------------------------- + slack 0.155 diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_timing_summary_routed.rpx b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_timing_summary_routed.rpx index d3f733b..331351b 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_timing_summary_routed.rpx and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_timing_summary_routed.rpx differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_utilization_placed.pb b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_utilization_placed.pb index 9a159b9..0d0ea62 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_utilization_placed.pb and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_utilization_placed.pb differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_utilization_placed.rpt b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_utilization_placed.rpt index b6835b0..45a5285 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_utilization_placed.rpt +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_utilization_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -| Date : Fri Oct 20 12:58:41 2023 +| Date : Fri Oct 20 19:45:59 2023 | Host : DESKTOP-5FH9OH3 running 64-bit major release (build 9200) | Command : report_utilization -file pl_eth_10g_wrapper_utilization_placed.rpt -pb pl_eth_10g_wrapper_utilization_placed.pb | Design : pl_eth_10g_wrapper @@ -33,15 +33,15 @@ Table of Contents | Site Type | Used | Fixed | Available | Util% | +----------------------------+-------+-------+-----------+-------+ | CLB LUTs | 18203 | 0 | 230400 | 7.90 | -| LUT as Logic | 17389 | 0 | 230400 | 7.55 | -| LUT as Memory | 814 | 0 | 101760 | 0.80 | +| LUT as Logic | 17387 | 0 | 230400 | 7.55 | +| LUT as Memory | 816 | 0 | 101760 | 0.80 | | LUT as Distributed RAM | 430 | 0 | | | -| LUT as Shift Register | 384 | 0 | | | -| CLB Registers | 27874 | 0 | 460800 | 6.05 | -| Register as Flip Flop | 27874 | 0 | 460800 | 6.05 | +| LUT as Shift Register | 386 | 0 | | | +| CLB Registers | 27890 | 0 | 460800 | 6.05 | +| Register as Flip Flop | 27890 | 0 | 460800 | 6.05 | | Register as Latch | 0 | 0 | 460800 | 0.00 | -| CARRY8 | 677 | 0 | 28800 | 2.35 | -| F7 Muxes | 133 | 0 | 115200 | 0.12 | +| CARRY8 | 678 | 0 | 28800 | 2.35 | +| F7 Muxes | 132 | 0 | 115200 | 0.11 | | F8 Muxes | 0 | 0 | 57600 | 0.00 | | F9 Muxes | 0 | 0 | 28800 | 0.00 | +----------------------------+-------+-------+-----------+-------+ @@ -62,7 +62,7 @@ Table of Contents | 261 | Yes | - | Set | | 286 | Yes | - | Reset | | 1919 | Yes | Set | - | -| 25408 | Yes | Reset | - | +| 25424 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -72,28 +72,28 @@ Table of Contents +--------------------------------------------+-------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +--------------------------------------------+-------+-------+-----------+-------+ -| CLB | 5066 | 0 | 28800 | 17.59 | -| CLBL | 2600 | 0 | | | -| CLBM | 2466 | 0 | | | -| LUT as Logic | 17389 | 0 | 230400 | 7.55 | +| CLB | 5100 | 0 | 28800 | 17.71 | +| CLBL | 2876 | 0 | | | +| CLBM | 2224 | 0 | | | +| LUT as Logic | 17387 | 0 | 230400 | 7.55 | | using O5 output only | 524 | | | | -| using O6 output only | 12600 | | | | -| using O5 and O6 | 4265 | | | | -| LUT as Memory | 814 | 0 | 101760 | 0.80 | +| using O6 output only | 12595 | | | | +| using O5 and O6 | 4268 | | | | +| LUT as Memory | 816 | 0 | 101760 | 0.80 | | LUT as Distributed RAM | 430 | 0 | | | | using O5 output only | 0 | | | | | using O6 output only | 2 | | | | | using O5 and O6 | 428 | | | | -| LUT as Shift Register | 384 | 0 | | | +| LUT as Shift Register | 386 | 0 | | | | using O5 output only | 0 | | | | -| using O6 output only | 260 | | | | -| using O5 and O6 | 124 | | | | -| CLB Registers | 27874 | 0 | 460800 | 6.05 | -| Register driven from within the CLB | 13012 | | | | -| Register driven from outside the CLB | 14862 | | | | -| LUT in front of the register is unused | 11514 | | | | -| LUT in front of the register is used | 3348 | | | | -| Unique Control Sets | 1083 | | 57600 | 1.88 | +| using O6 output only | 261 | | | | +| using O5 and O6 | 125 | | | | +| CLB Registers | 27890 | 0 | 460800 | 6.05 | +| Register driven from within the CLB | 12934 | | | | +| Register driven from outside the CLB | 14956 | | | | +| LUT in front of the register is unused | 11569 | | | | +| LUT in front of the register is used | 3387 | | | | +| Unique Control Sets | 1082 | | 57600 | 1.88 | +--------------------------------------------+-------+-------+-----------+-------+ * * Note: Available Control Sets calculated as Slices * 2, Review the Control Sets Report for more information regarding control sets. @@ -206,22 +206,22 @@ Table of Contents +---------------+-------+---------------------+ | Ref Name | Used | Functional Category | +---------------+-------+---------------------+ -| FDRE | 25408 | Register | -| LUT6 | 7190 | CLB | -| LUT2 | 5495 | CLB | -| LUT3 | 3335 | CLB | -| LUT5 | 2862 | CLB | -| LUT4 | 2386 | CLB | +| FDRE | 25424 | Register | +| LUT6 | 7183 | CLB | +| LUT2 | 5489 | CLB | +| LUT3 | 3345 | CLB | +| LUT5 | 2857 | CLB | +| LUT4 | 2395 | CLB | | FDSE | 1919 | Register | | RAMD32 | 736 | CLB | -| CARRY8 | 677 | CLB | +| CARRY8 | 678 | CLB | | LUT1 | 386 | CLB | -| SRL16E | 356 | CLB | +| SRL16E | 358 | CLB | | FDCE | 286 | Register | | FDPE | 261 | Register | -| SRLC32E | 152 | CLB | +| SRLC32E | 153 | CLB | | RAMB36E2 | 135 | BLOCKRAM | -| MUXF7 | 133 | CLB | +| MUXF7 | 132 | CLB | | RAMS32 | 120 | CLB | | RAMB18E2 | 4 | BLOCKRAM | | BUFG_GT | 4 | Clock | diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/place_design.pb b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/place_design.pb index 6e0a9ae..2591838 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/place_design.pb and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/place_design.pb differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/route_design.pb b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/route_design.pb index f1922d3..ca7d90c 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/route_design.pb and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/route_design.pb differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/runme.log b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/runme.log index 0cace8d..f032da8 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/runme.log +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/runme.log @@ -13,12 +13,12 @@ source pl_eth_10g_wrapper.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'. -add_files: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1144.477 ; gain = 0.000 +add_files: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1144.215 ; gain = 0.000 Command: link_design -top pl_eth_10g_wrapper -part xczu7ev-ffvc1156-2-e Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.816 . Memory (MB): peak = 1762.703 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.810 . Memory (MB): peak = 1759.492 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 876 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 @@ -53,7 +53,7 @@ Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardwar Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_clocks.xdc:16] INFO: [Timing 38-2] Deriving generated clocks [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_clocks.xdc:16] -all_fanout: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2297.480 ; gain = 330.117 +all_fanout: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2295.293 ; gain = 328.082 Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_0/pl_eth_10g_auto_cc_0_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst' Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst' Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_us_2/pl_eth_10g_auto_us_2_clocks.xdc] for cell 'pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_us/inst' @@ -66,7 +66,7 @@ Finished Parsing XDC File [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardwar INFO: [Project 1-1715] 7 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 18 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2299.633 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2297.664 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 62 instances were transformed. RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 13 instances @@ -75,7 +75,7 @@ INFO: [Project 1-111] Unisim Transformation Summary: 14 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:31 . Memory (MB): peak = 2299.633 ; gain = 1155.156 +link_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:31 . Memory (MB): peak = 2297.664 ; gain = 1153.449 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' @@ -86,58 +86,58 @@ INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2299.633 ; gain = 0.000 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2297.664 ; gain = 0.000 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: d5ae2a81 +Ending Cache Timing Information Task | Checksum: 138337785 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2299.633 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2297.664 ; gain = 0.000 Starting Logic Optimization Task Phase 1 Retarget -INFO: [Opt 31-138] Pushed 41 inverter(s) to 2272 load pin(s). +INFO: [Opt 31-138] Pushed 41 inverter(s) to 2274 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 261221661 +Phase 1 Retarget | Checksum: 12f7198c8 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2487.625 ; gain = 2.207 -INFO: [Opt 31-389] Phase Retarget created 9 cells and removed 434 cells +Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2482.816 ; gain = 2.074 +INFO: [Opt 31-389] Phase Retarget created 9 cells and removed 433 cells INFO: [Opt 31-1021] In phase Retarget, 143 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 1e002a5df +Phase 2 Constant propagation | Checksum: 13a3a3d4f -Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2487.625 ; gain = 2.207 -INFO: [Opt 31-389] Phase Constant propagation created 492 cells and removed 1260 cells +Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2482.816 ; gain = 2.074 +INFO: [Opt 31-389] Phase Constant propagation created 490 cells and removed 1256 cells INFO: [Opt 31-1021] In phase Constant propagation, 142 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Sweep -Phase 3 Sweep | Checksum: 20d6b0d7d +Phase 3 Sweep | Checksum: 17dc2c8da -Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2487.625 ; gain = 2.207 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2482.816 ; gain = 2.074 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1051 cells INFO: [Opt 31-1021] In phase Sweep, 407 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT. -Phase 4 BUFG optimization | Checksum: 20d6b0d7d +Phase 4 BUFG optimization | Checksum: 17dc2c8da -Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2487.625 ; gain = 2.207 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2482.816 ; gain = 2.074 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 5 Shift Register Optimization | Checksum: 20d6b0d7d +Phase 5 Shift Register Optimization | Checksum: 17dc2c8da -Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2487.625 ; gain = 2.207 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2482.816 ; gain = 2.074 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 20d6b0d7d +Phase 6 Post Processing Netlist | Checksum: 17dc2c8da -Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 2487.625 ; gain = 2.207 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2482.816 ; gain = 2.074 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 175 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary @@ -147,8 +147,8 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- -| Retarget | 9 | 434 | 143 | -| Constant propagation | 492 | 1260 | 142 | +| Retarget | 9 | 433 | 143 | +| Constant propagation | 490 | 1256 | 142 | | Sweep | 0 | 1051 | 407 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | @@ -159,10 +159,10 @@ Opt_design Change Summary Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 2487.625 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 1e5ca8a39 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.109 . Memory (MB): peak = 2482.816 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 2040f7235 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2487.625 ; gain = 2.207 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2482.816 ; gain = 2.074 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. @@ -179,43 +179,43 @@ INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 139 ha INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 133 WE to EN ports Number of BRAM Ports augmented: 5 newly gated: 133 Total Ports: 278 -Ending PowerOpt Patch Enables Task | Checksum: 1d101fdd6 +Ending PowerOpt Patch Enables Task | Checksum: 2397c5aae -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Ending Power Optimization Task | Checksum: 1d101fdd6 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Ending Power Optimization Task | Checksum: 2397c5aae -Time (s): cpu = 00:00:38 ; elapsed = 00:00:44 . Memory (MB): peak = 4688.359 ; gain = 2200.734 +Time (s): cpu = 00:00:50 ; elapsed = 00:00:47 . Memory (MB): peak = 4670.074 ; gain = 2187.258 Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 1d101fdd6 +Ending Final Cleanup Task | Checksum: 2397c5aae -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4670.074 ; gain = 0.000 Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.094 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 1d9522167 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 1e978e3e4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.094 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 42 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:58 . Memory (MB): peak = 4688.359 ; gain = 2388.727 +opt_design: Time (s): cpu = 00:01:04 ; elapsed = 00:01:01 . Memory (MB): peak = 4670.074 ; gain = 2372.410 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.064 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_opt.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [runtcl-4] Executing : report_drc -file pl_eth_10g_wrapper_drc_opted.rpt -pb pl_eth_10g_wrapper_drc_opted.pb -rpx pl_eth_10g_wrapper_drc_opted.rpx Command: report_drc -file pl_eth_10g_wrapper_drc_opted.rpt -pb pl_eth_10g_wrapper_drc_opted.pb -rpx pl_eth_10g_wrapper_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_opted.rpt. report_drc completed successfully -report_drc: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 4688.359 ; gain = 0.000 +report_drc: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' @@ -234,29 +234,29 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 135b4e4ba +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14ac46bc1 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14ad04f73 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a4892a73 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 1bf2762b0 +Phase 1.3 Build Placer Netlist Model | Checksum: a636ca79 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 1bf2762b0 +Phase 1.4 Constrain Clocks/Macros | Checksum: a636ca79 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 1bf2762b0 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: a636ca79 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2 Global Placement @@ -265,61 +265,61 @@ Phase 2.1 Floorplanning Phase 2.1.1 Partition Driven Placement Phase 2.1.1.1 PBP: Partition Driven Placement -Phase 2.1.1.1 PBP: Partition Driven Placement | Checksum: 24259bfbd +Phase 2.1.1.1 PBP: Partition Driven Placement | Checksum: be748173 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:28 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.1.1.2 PBP: Clock Region Placement -Phase 2.1.1.2 PBP: Clock Region Placement | Checksum: 182bf8902 +Phase 2.1.1.2 PBP: Clock Region Placement | Checksum: a4c8b2cf -Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.1.1.3 PBP: Discrete Incremental -Phase 2.1.1.3 PBP: Discrete Incremental | Checksum: 1683ce54b +Phase 2.1.1.3 PBP: Discrete Incremental | Checksum: 19273f8f0 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.1.1.4 PBP: Compute Congestion -Phase 2.1.1.4 PBP: Compute Congestion | Checksum: 1683ce54b +Phase 2.1.1.4 PBP: Compute Congestion | Checksum: 19273f8f0 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.1.1.5 PBP: Macro Placement -Phase 2.1.1.5 PBP: Macro Placement | Checksum: 1b60fd256 +Phase 2.1.1.5 PBP: Macro Placement | Checksum: a17d3753 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.1.1.6 PBP: UpdateTiming -Phase 2.1.1.6 PBP: UpdateTiming | Checksum: 1de9913ba +Phase 2.1.1.6 PBP: UpdateTiming | Checksum: af3a95f3 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.1.1.7 PBP: Add part constraints -Phase 2.1.1.7 PBP: Add part constraints | Checksum: 1de9913ba +Phase 2.1.1.7 PBP: Add part constraints | Checksum: af3a95f3 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 2.1.1 Partition Driven Placement | Checksum: 1de9913ba +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 2.1.1 Partition Driven Placement | Checksum: af3a95f3 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 2.1 Floorplanning | Checksum: 1de9913ba +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 2.1 Floorplanning | Checksum: af3a95f3 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.2 Update Timing before SLR Path Opt -Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1de9913ba +Phase 2.2 Update Timing before SLR Path Opt | Checksum: af3a95f3 -Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer -INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 938 LUT instances to create LUTNM shape +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 927 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-775] End 1 Pass. Optimized 367 nets or cells. Created 0 new cell, deleted 367 existing cells and moved 0 existing cell -INFO: [Physopt 32-1030] Pass 1. Identified 33 candidate driver sets for equivalent driver rewiring. -INFO: [Physopt 32-661] Optimized 22 nets. Re-placed 244 instances. -INFO: [Physopt 32-775] End 1 Pass. Optimized 22 nets or cells. Created 0 new cell, deleted 1 existing cell and moved 244 existing cells -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.198 . Memory (MB): peak = 4688.359 ; gain = 0.000 +INFO: [Physopt 32-1030] Pass 1. Identified 31 candidate driver sets for equivalent driver rewiring. +INFO: [Physopt 32-661] Optimized 24 nets. Re-placed 265 instances. +INFO: [Physopt 32-775] End 1 Pass. Optimized 24 nets or cells. Created 0 new cell, deleted 0 existing cell and moved 265 existing cells +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.154 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell @@ -330,7 +330,7 @@ INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 4670.074 ; gain = 0.000 Summary of Physical Synthesis Optimizations ============================================ @@ -340,7 +340,7 @@ Summary of Physical Synthesis Optimizations | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 367 | 367 | 0 | 1 | 00:00:01 | -| Equivalent Driver Rewiring | 0 | 1 | 22 | 0 | 1 | 00:00:03 | +| Equivalent Driver Rewiring | 0 | 0 | 24 | 0 | 1 | 00:00:03 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | @@ -348,64 +348,64 @@ Summary of Physical Synthesis Optimizations | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 368 | 389 | 0 | 4 | 00:00:04 | +| Total | 0 | 367 | 391 | 0 | 4 | 00:00:04 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- -Phase 2.3.1 Physical Synthesis In Placer | Checksum: 22a901e76 +Phase 2.3.1 Physical Synthesis In Placer | Checksum: 139138c10 -Time (s): cpu = 00:00:52 ; elapsed = 00:01:21 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 2.3 Global Placement Core | Checksum: 184ba6d65 +Time (s): cpu = 00:01:03 ; elapsed = 00:01:14 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 2.3 Global Placement Core | Checksum: 167c195fa -Time (s): cpu = 00:00:55 ; elapsed = 00:01:26 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 184ba6d65 +Time (s): cpu = 00:01:07 ; elapsed = 00:01:18 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 167c195fa -Time (s): cpu = 00:00:55 ; elapsed = 00:01:26 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:07 ; elapsed = 00:01:18 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 1829a8e06 +Phase 3.1 Commit Multi Column Macros | Checksum: 1599f8778 -Time (s): cpu = 00:00:57 ; elapsed = 00:01:28 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:09 ; elapsed = 00:01:21 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c2077e23 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 132be9d92 -Time (s): cpu = 00:00:58 ; elapsed = 00:01:31 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:12 ; elapsed = 00:01:23 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 3.3 Small Shape DP Phase 3.3.1 Small Shape Clustering -Phase 3.3.1 Small Shape Clustering | Checksum: 10bc04dd4 +Phase 3.3.1 Small Shape Clustering | Checksum: a1b5ebd2 -Time (s): cpu = 00:01:02 ; elapsed = 00:01:35 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:17 ; elapsed = 00:01:28 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 3.3.2 Flow Legalize Slice Clusters -Phase 3.3.2 Flow Legalize Slice Clusters | Checksum: e00bb846 +Phase 3.3.2 Flow Legalize Slice Clusters | Checksum: 66bdfa70 -Time (s): cpu = 00:01:03 ; elapsed = 00:01:35 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:17 ; elapsed = 00:01:28 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 3.3.3 Slice Area Swap -Phase 3.3.3 Slice Area Swap | Checksum: 13cea96ba +Phase 3.3.3 Slice Area Swap | Checksum: b4a03078 -Time (s): cpu = 00:01:04 ; elapsed = 00:01:42 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 3.3 Small Shape DP | Checksum: 1e9d05258 +Time (s): cpu = 00:01:18 ; elapsed = 00:01:31 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 3.3 Small Shape DP | Checksum: f3e77f5a -Time (s): cpu = 00:01:12 ; elapsed = 00:01:48 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:27 ; elapsed = 00:01:37 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 3.4 Re-assign LUT pins -Phase 3.4 Re-assign LUT pins | Checksum: 1cc66f7a9 +Phase 3.4 Re-assign LUT pins | Checksum: 1ccb856d8 -Time (s): cpu = 00:01:13 ; elapsed = 00:01:52 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:29 ; elapsed = 00:01:41 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 3.5 Pipeline Register Optimization -Phase 3.5 Pipeline Register Optimization | Checksum: f627ec5f +Phase 3.5 Pipeline Register Optimization | Checksum: 1646d4a6a -Time (s): cpu = 00:01:14 ; elapsed = 00:01:52 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: f627ec5f +Time (s): cpu = 00:01:30 ; elapsed = 00:01:42 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 1646d4a6a -Time (s): cpu = 00:01:14 ; elapsed = 00:01:52 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:30 ; elapsed = 00:01:42 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up @@ -413,7 +413,7 @@ Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 10661162e +Post Placement Optimization Initialization | Checksum: 21ad82e5a Phase 4.1.1.1 BUFG Insertion @@ -421,33 +421,33 @@ Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.577 | TNS=0.000 | -Phase 1 Physical Synthesis Initialization | Checksum: 1c374d8b9 +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.637 | TNS=0.000 | +Phase 1 Physical Synthesis Initialization | Checksum: 1947f44a7 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Place 46-35] Processed net pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_rx_undersize_accumulator/E[0], inserted BUFG to drive 1680 loads. INFO: [Place 46-35] Processed net pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out, inserted BUFG to drive 1159 loads. INFO: [Place 46-45] Replicated bufg driver pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE/i_TX_TOP/i_TX_CORE/i_TX_CORE_STRIPER/i_RESET_FLOP_TX_LBA/reset_flop_out_reg_replica INFO: [Place 46-35] Processed net pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_axi_if_top/i_pif_registers/i_stats_stat_tx_frame_error_accumulator/E[0], inserted BUFG to drive 1152 loads. INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 3, Replicated BUFG Driver: 1, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. -Ending Physical Synthesis Task | Checksum: b7d053a7 +Ending Physical Synthesis Task | Checksum: 161227327 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 4.1.1.1 BUFG Insertion | Checksum: a2080de3 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 4.1.1.1 BUFG Insertion | Checksum: 1b3d14eea -Time (s): cpu = 00:01:24 ; elapsed = 00:02:05 . Memory (MB): peak = 4688.359 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=1.577. For the most accurate timing information please run report_timing. +Time (s): cpu = 00:01:42 ; elapsed = 00:01:56 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Place 30-746] Post Placement Timing Summary WNS=1.637. For the most accurate timing information please run report_timing. -Time (s): cpu = 00:01:24 ; elapsed = 00:02:05 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: d011626d +Time (s): cpu = 00:01:42 ; elapsed = 00:01:56 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 4.1 Post Commit Optimization | Checksum: 18af3dba2 -Time (s): cpu = 00:01:24 ; elapsed = 00:02:06 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:42 ; elapsed = 00:01:57 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 1a4375091 +Phase 4.2 Post Placement Cleanup | Checksum: 1fb723624 -Time (s): cpu = 00:01:27 ; elapsed = 00:02:09 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:46 ; elapsed = 00:02:00 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 4.3 Placer Reporting @@ -466,40 +466,40 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion | West| 1x1| 1x1| 4x4| |___________|___________________|___________________|___________________| -Phase 4.3.1 Print Estimated Congestion | Checksum: 1a4375091 +Phase 4.3.1 Print Estimated Congestion | Checksum: 1fb723624 -Time (s): cpu = 00:01:27 ; elapsed = 00:02:09 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 4.3 Placer Reporting | Checksum: 1a4375091 +Time (s): cpu = 00:01:46 ; elapsed = 00:02:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 4.3 Placer Reporting | Checksum: 1fb723624 -Time (s): cpu = 00:01:28 ; elapsed = 00:02:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:46 ; elapsed = 00:02:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 4670.074 ; gain = 0.000 -Time (s): cpu = 00:01:28 ; elapsed = 00:02:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21b3ac3a0 +Time (s): cpu = 00:01:46 ; elapsed = 00:02:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 269a85b9d -Time (s): cpu = 00:01:28 ; elapsed = 00:02:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Ending Placer Task | Checksum: 1779cef7d +Time (s): cpu = 00:01:47 ; elapsed = 00:02:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Ending Placer Task | Checksum: 1e2aa1291 -Time (s): cpu = 00:01:28 ; elapsed = 00:02:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:01:47 ; elapsed = 00:02:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 84 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. place_design completed successfully -place_design: Time (s): cpu = 00:01:30 ; elapsed = 00:02:12 . Memory (MB): peak = 4688.359 ; gain = 0.000 +place_design: Time (s): cpu = 00:01:50 ; elapsed = 00:02:04 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_placed.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 4688.359 ; gain = 0.000 +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [runtcl-4] Executing : report_io -file pl_eth_10g_wrapper_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.071 . Memory (MB): peak = 4688.359 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.080 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file pl_eth_10g_wrapper_utilization_placed.rpt -pb pl_eth_10g_wrapper_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file pl_eth_10g_wrapper_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 4688.359 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.127 . Memory (MB): peak = 4670.074 ; gain = 0.000 Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' @@ -508,15 +508,15 @@ INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 93 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully -phys_opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 4688.359 ; gain = 0.000 +phys_opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_physopt.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 4688.359 ; gain = 0.000 +write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' @@ -528,150 +528,153 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: 1cdd801d ConstDB: 0 ShapeSum: 8699813c RouteDB: d425ee24 +Checksum: PlaceDB: ba17791b ConstDB: 0 ShapeSum: b8143ef4 RouteDB: 707e5a82 Phase 1 Build RT Design -Nodegraph reading from file. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 1 Build RT Design | Checksum: 121342218 +Nodegraph reading from file. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 1 Build RT Design | Checksum: 1ccd8f4d8 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Post Restoration Checksum: NetGraph: f18a6085 NumContArr: 2d83f4b7 Constraints: 7fa99f0d Timing: 0 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Post Restoration Checksum: NetGraph: eaea5d6 NumContArr: 4d575875 Constraints: c401714a Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: 19eb7f449 +Phase 2.1 Create Timer | Checksum: 120076f95 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: 19eb7f449 +Phase 2.2 Fix Topology Constraints | Checksum: 120076f95 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: 19eb7f449 +Phase 2.3 Pre Route Cleanup | Checksum: 120076f95 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.4 Global Clock Net Routing Number of Nodes with overlaps = 0 -Phase 2.4 Global Clock Net Routing | Checksum: 12230a291 +Phase 2.4 Global Clock Net Routing | Checksum: 12fb7e7e6 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 2.5 Update Timing -Phase 2.5 Update Timing | Checksum: 213dbeb6f +Phase 2.5 Update Timing | Checksum: 265dc8b5b -Time (s): cpu = 00:00:12 ; elapsed = 00:00:24 . Memory (MB): peak = 4688.359 ; gain = 0.000 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.730 | TNS=0.000 | WHS=-0.156 | THS=-20.586| +Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.822 | TNS=0.000 | WHS=-0.190 | THS=-26.919| Phase 2.6 Update Timing for Bus Skew Phase 2.6.1 Update Timing -Phase 2.6.1 Update Timing | Checksum: 24e59fe80 +Phase 2.6.1 Update Timing | Checksum: 27464ca79 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:38 . Memory (MB): peak = 4688.359 ; gain = 0.000 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.730 | TNS=0.000 | WHS=N/A | THS=N/A | +Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.822 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 2.6 Update Timing for Bus Skew | Checksum: 24f74bfa0 +Phase 2.6 Update Timing for Bus Skew | Checksum: 24be47c62 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:38 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 2 Router Initialization | Checksum: 21144913e +Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 2 Router Initialization | Checksum: 227779a70 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:38 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 4670.074 ; gain = 0.000 Router Utilization Summary - Global Vertical Routing Utilization = 0.000163859 % - Global Horizontal Routing Utilization = 0.000207685 % + Global Vertical Routing Utilization = 5.04182e-05 % + Global Horizontal Routing Utilization = 0.000129803 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. - Number of Failed Nets = 46937 + Number of Failed Nets = 46965 (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 40192 - Number of Partially Routed Nets = 6745 + Number of Unrouted Nets = 40223 + Number of Partially Routed Nets = 6742 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing -Phase 3.1 Global Routing | Checksum: 21144913e +Phase 3.1 Global Routing | Checksum: 227779a70 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:39 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 3 Initial Routing | Checksum: 4368cb15 +Time (s): cpu = 00:00:25 ; elapsed = 00:00:33 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 3 Initial Routing | Checksum: 1d65e8aff -Time (s): cpu = 00:00:28 ; elapsed = 00:00:46 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 6167 - Number of Nodes with overlaps = 386 - Number of Nodes with overlaps = 11 - Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 5873 + Number of Nodes with overlaps = 350 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.870 | TNS=0.000 | WHS=-0.040 | THS=-0.082 | + +Phase 4.1 Global Iteration 0 | Checksum: 13fe249c9 + +Time (s): cpu = 00:00:45 ; elapsed = 00:01:11 . Memory (MB): peak = 4670.074 ; gain = 0.000 + +Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.423 | TNS=0.000 | WHS=-0.005 | THS=-0.006 | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.870 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 4.1 Global Iteration 0 | Checksum: 1f712922e +Phase 4.2 Global Iteration 1 | Checksum: 1ca0d0fbb -Time (s): cpu = 00:00:42 ; elapsed = 00:01:21 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:48 ; elapsed = 00:01:15 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 4 Rip-up And Reroute | Checksum: 1ca0d0fbb -Phase 4.2 Additional Iteration for Hold -Phase 4.2 Additional Iteration for Hold | Checksum: 1fbb3bf88 - -Time (s): cpu = 00:00:43 ; elapsed = 00:01:21 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 4 Rip-up And Reroute | Checksum: 1fbb3bf88 - -Time (s): cpu = 00:00:43 ; elapsed = 00:01:21 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:48 ; elapsed = 00:01:15 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing -Phase 5.1.1 Update Timing | Checksum: 25dbf9062 +Phase 5.1.1 Update Timing | Checksum: 1b62e6b82 -Time (s): cpu = 00:00:46 ; elapsed = 00:01:26 . Memory (MB): peak = 4688.359 ; gain = 0.000 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.423 | TNS=0.000 | WHS=0.011 | THS=0.000 | +Time (s): cpu = 00:00:52 ; elapsed = 00:01:20 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.870 | TNS=0.000 | WHS=0.010 | THS=0.000 | -Phase 5.1 Delay CleanUp | Checksum: 1e7c15182 +Phase 5.1 Delay CleanUp | Checksum: 22b577808 -Time (s): cpu = 00:00:46 ; elapsed = 00:01:27 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:52 ; elapsed = 00:01:20 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 1e7c15182 +Phase 5.2 Clock Skew Optimization | Checksum: 22b577808 -Time (s): cpu = 00:00:46 ; elapsed = 00:01:27 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 5 Delay and Skew Optimization | Checksum: 1e7c15182 +Time (s): cpu = 00:00:52 ; elapsed = 00:01:21 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 5 Delay and Skew Optimization | Checksum: 22b577808 -Time (s): cpu = 00:00:46 ; elapsed = 00:01:27 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:52 ; elapsed = 00:01:21 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 21862d4aa +Phase 6.1.1 Update Timing | Checksum: 1805b0dba -Time (s): cpu = 00:00:48 ; elapsed = 00:01:31 . Memory (MB): peak = 4688.359 ; gain = 0.000 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.423 | TNS=0.000 | WHS=0.011 | THS=0.000 | +Time (s): cpu = 00:00:55 ; elapsed = 00:01:24 . Memory (MB): peak = 4670.074 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.870 | TNS=0.000 | WHS=0.010 | THS=0.000 | -Phase 6.1 Hold Fix Iter | Checksum: 28e5b0a03 +Phase 6.1 Hold Fix Iter | Checksum: 16069ca04 -Time (s): cpu = 00:00:48 ; elapsed = 00:01:32 . Memory (MB): peak = 4688.359 ; gain = 0.000 -Phase 6 Post Hold Fix | Checksum: 28e5b0a03 +Time (s): cpu = 00:00:56 ; elapsed = 00:01:25 . Memory (MB): peak = 4670.074 ; gain = 0.000 +Phase 6 Post Hold Fix | Checksum: 16069ca04 -Time (s): cpu = 00:00:48 ; elapsed = 00:01:32 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:56 ; elapsed = 00:01:25 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 3.24213 % - Global Horizontal Routing Utilization = 2.86314 % + Global Vertical Routing Utilization = 3.18683 % + Global Horizontal Routing Utilization = 2.82098 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -681,61 +684,61 @@ Router Utilization Summary Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 7 Route finalize | Checksum: 28559f170 +Phase 7 Route finalize | Checksum: 1cf9de95a -Time (s): cpu = 00:00:49 ; elapsed = 00:01:32 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:57 ; elapsed = 00:01:25 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 28559f170 +Phase 8 Verifying routed nets | Checksum: 1cf9de95a -Time (s): cpu = 00:00:49 ; elapsed = 00:01:33 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:57 ; elapsed = 00:01:26 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 9 Depositing Routes INFO: [Route 35-467] Router swapped GT pin pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_common_wrapper/pl_eth_10g_xxv_ethernet_0_0_gt_gthe4_common_wrapper_i/common_inst/gthe4_common_gen.GTHE4_COMMON_PRIM_INST/GTREFCLK00 to physical pin GTHE4_COMMON_X0Y2/COM0_REFCLKOUT5 -Phase 9 Depositing Routes | Checksum: 28559f170 +Phase 9 Depositing Routes | Checksum: 1cf9de95a -Time (s): cpu = 00:00:50 ; elapsed = 00:01:38 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:59 ; elapsed = 00:01:30 . Memory (MB): peak = 4670.074 ; gain = 0.000 Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=1.423 | TNS=0.000 | WHS=0.011 | THS=0.000 | +INFO: [Route 35-57] Estimated Timing Summary | WNS=0.870 | TNS=0.000 | WHS=0.010 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 28559f170 +Phase 10 Post Router Timing | Checksum: 1cf9de95a -Time (s): cpu = 00:00:51 ; elapsed = 00:01:38 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:59 ; elapsed = 00:01:30 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Route 35-16] Router Completed Successfully -Time (s): cpu = 00:00:51 ; elapsed = 00:01:38 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Time (s): cpu = 00:00:59 ; elapsed = 00:01:30 . Memory (MB): peak = 4670.074 ; gain = 0.000 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation -110 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. +111 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:55 ; elapsed = 00:01:43 . Memory (MB): peak = 4688.359 ; gain = 0.000 +route_design: Time (s): cpu = 00:01:05 ; elapsed = 00:01:35 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 4688.359 ; gain = 0.000 +Write XDEF Complete: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_routed.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 4688.359 ; gain = 0.000 +write_checkpoint: Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [runtcl-4] Executing : report_drc -file pl_eth_10g_wrapper_drc_routed.rpt -pb pl_eth_10g_wrapper_drc_routed.pb -rpx pl_eth_10g_wrapper_drc_routed.rpx Command: report_drc -file pl_eth_10g_wrapper_drc_routed.rpt -pb pl_eth_10g_wrapper_drc_routed.pb -rpx pl_eth_10g_wrapper_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_drc_routed.rpt. report_drc completed successfully -report_drc: Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 4688.359 ; gain = 0.000 +report_drc: Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [runtcl-4] Executing : report_methodology -file pl_eth_10g_wrapper_methodology_drc_routed.rpt -pb pl_eth_10g_wrapper_methodology_drc_routed.pb -rpx pl_eth_10g_wrapper_methodology_drc_routed.rpx Command: report_methodology -file pl_eth_10g_wrapper_methodology_drc_routed.rpt -pb pl_eth_10g_wrapper_methodology_drc_routed.pb -rpx pl_eth_10g_wrapper_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads INFO: [Coretcl 2-1520] The results of Report Methodology are in file E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper_methodology_drc_routed.rpt. report_methodology completed successfully -report_methodology: Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 4688.359 ; gain = 0.000 +report_methodology: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [runtcl-4] Executing : report_power -file pl_eth_10g_wrapper_power_routed.rpt -pb pl_eth_10g_wrapper_power_summary_routed.pb -rpx pl_eth_10g_wrapper_power_routed.rpx Command: report_power -file pl_eth_10g_wrapper_power_routed.rpt -pb pl_eth_10g_wrapper_power_summary_routed.pb -rpx pl_eth_10g_wrapper_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. @@ -744,9 +747,9 @@ Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. -122 Infos, 3 Warnings, 1 Critical Warnings and 0 Errors encountered. +123 Infos, 3 Warnings, 1 Critical Warnings and 0 Errors encountered. report_power completed successfully -report_power: Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 4688.359 ; gain = 0.000 +report_power: Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 4670.074 ; gain = 0.000 INFO: [runtcl-4] Executing : report_route_status -file pl_eth_10g_wrapper_route_status.rpt -pb pl_eth_10g_wrapper_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file pl_eth_10g_wrapper_timing_summary_routed.rpt -pb pl_eth_10g_wrapper_timing_summary_routed.pb -rpx pl_eth_10g_wrapper_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. @@ -755,11 +758,10 @@ WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Pl INFO: [runtcl-4] Executing : report_incremental_reuse -file pl_eth_10g_wrapper_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file pl_eth_10g_wrapper_clock_utilization_routed.rpt -report_clock_utilization: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 4688.359 ; gain = 0.000 INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file pl_eth_10g_wrapper_bus_skew_routed.rpt -pb pl_eth_10g_wrapper_bus_skew_routed.pb -rpx pl_eth_10g_wrapper_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Fri Oct 20 13:01:38 2023... +INFO: [Common 17-206] Exiting Vivado at Fri Oct 20 19:48:36 2023... *** Running vivado with args -log pl_eth_10g_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source pl_eth_10g_wrapper.tcl -notrace @@ -776,9 +778,9 @@ Command: open_checkpoint pl_eth_10g_wrapper_routed.dcp Starting open_checkpoint Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1126.957 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1143.684 ; gain = 0.000 INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e -Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.816 . Memory (MB): peak = 1691.883 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.753 . Memory (MB): peak = 1691.023 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 872 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 @@ -790,10 +792,10 @@ INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. -Read XDEF File: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2282.707 ; gain = 79.668 +Read XDEF File: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2278.703 ; gain = 78.188 Restored from archive | CPU: 4.000000 secs | Memory: 0.000000 MB | -Finished XDEF File Restore: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2282.707 ; gain = 79.668 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 2748.277 ; gain = 0.000 +Finished XDEF File Restore: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2278.703 ; gain = 78.188 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 2746.234 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 68 instances were transformed. RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 13 instances @@ -802,7 +804,7 @@ INFO: [Project 1-111] Unisim Transformation Summary: SRLC32E => SRL16E: 6 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2020.2 (64-bit) build 3064766 -open_checkpoint: Time (s): cpu = 00:00:26 ; elapsed = 00:00:42 . Memory (MB): peak = 2748.277 ; gain = 1621.320 +open_checkpoint: Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2746.234 ; gain = 1602.551 INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. @@ -830,7 +832,7 @@ INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'. INFO: [DRC 23-27] Running DRC with 2 threads -WARNING: [DRC RTSTAT-10] No routable loads: 111 net(s) have no routable loads. The problem bus(es) and/or net(s) are pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb... and (the first 15 of 67 listed). +WARNING: [DRC RTSTAT-10] No routable loads: 111 net(s) have no routable loads. The problem bus(es) and/or net(s) are pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s02_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/axi_pl_ps/s01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, pl_eth_10g_i/zups/ps_axi_periph/m01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb... and (the first 15 of 67 listed). INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1934] RAMB18E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. INFO: [DRC REQP-1935] RAMB36E2_nochange_collision_advisory: Synchronous clocking is detected for BRAM (pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with NO_CHANGE write-mode. This is the preferred mode for best power characteristics. However, NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. @@ -849,5 +851,5 @@ INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Common 17-83] Releasing license: Implementation 34 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3419.621 ; gain = 671.344 -INFO: [Common 17-206] Exiting Vivado at Fri Oct 20 13:03:35 2023... +write_bitstream: Time (s): cpu = 00:00:50 ; elapsed = 00:00:46 . Memory (MB): peak = 3409.320 ; gain = 663.086 +INFO: [Common 17-206] Exiting Vivado at Fri Oct 20 19:50:35 2023... diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/vivado.jou b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/vivado.jou index ead2788..01025c6 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/vivado.jou +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2020.2 (64-bit) # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 -# Start of session at: Fri Oct 20 13:01:57 2023 -# Process ID: 167024 +# Start of session at: Fri Oct 20 19:49:09 2023 +# Process ID: 77788 # Current directory: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1 # Command line: vivado.exe -log pl_eth_10g_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source pl_eth_10g_wrapper.tcl -notrace # Log file: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.vdi diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/vivado.pb b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/vivado.pb index aad6264..3ff7353 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/vivado.pb and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/vivado.pb differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/vivado_171500.backup.jou b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/vivado_171500.backup.jou new file mode 100644 index 0000000..e4d7665 --- /dev/null +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/vivado_171500.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2020.2 (64-bit) +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 +# Start of session at: Fri Oct 20 19:41:49 2023 +# Process ID: 171500 +# Current directory: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1 +# Command line: vivado.exe -log pl_eth_10g_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source pl_eth_10g_wrapper.tcl -notrace +# Log file: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/pl_eth_10g_wrapper.vdi +# Journal file: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source pl_eth_10g_wrapper.tcl -notrace diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/write_bitstream.pb b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/write_bitstream.pb index 9e023c3..162593f 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/write_bitstream.pb and b/src/pl_eth_10g_hw/pl_eth_10g.runs/impl_1/write_bitstream.pb differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/.vivado.begin.rst b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/.vivado.begin.rst index 15fe5a0..3f0aab4 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/.vivado.begin.rst +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/gen_run.xml b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/gen_run.xml index c3e5416..273f679 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/gen_run.xml +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper.dcp b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper.dcp index a9dbe72..b274ae7 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper.dcp and b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper.dcp differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper.vds b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper.vds index 495b29a..ed7a3ee 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper.vds +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper.vds @@ -2,8 +2,8 @@ # Vivado v2020.2 (64-bit) # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 -# Start of session at: Fri Oct 20 12:45:24 2023 -# Process ID: 55912 +# Start of session at: Fri Oct 20 19:30:05 2023 +# Process ID: 145272 # Current directory: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/synth_1 # Command line: vivado.exe -log pl_eth_10g_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source pl_eth_10g_wrapper.tcl # Log file: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper.vds @@ -13,7 +13,7 @@ source pl_eth_10g_wrapper.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'. -add_files: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1144.660 ; gain = 0.000 +add_files: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1144.133 ; gain = 0.000 Command: synth_design -top pl_eth_10g_wrapper -part xczu7ev-ffvc1156-2-e Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xczu7ev' @@ -21,7 +21,7 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu7ev INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 22868 +INFO: [Synth 8-7075] Helper process launched with PID 166004 WARNING: [Synth 8-2507] parameter declaration becomes local in xxv_ethernet_v3_3_0_cl73autoneg_an_pcontrol with formal parameter declaration list [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/05d5/hdl/xxv_ethernet_v3_3_vl_rfs.sv:186854] WARNING: [Synth 8-2507] parameter declaration becomes local in xxv_ethernet_v3_3_0_cl73autoneg_an_pcontrol with formal parameter declaration list [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/05d5/hdl/xxv_ethernet_v3_3_vl_rfs.sv:186876] WARNING: [Synth 8-2507] parameter declaration becomes local in xxv_ethernet_v3_3_0_cl73autoneg_10G_an_pcontrol with formal parameter declaration list [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/05d5/hdl/xxv_ethernet_v3_3_vl_rfs.sv:190663] @@ -31,7 +31,7 @@ WARNING: [Synth 8-2507] parameter declaration becomes local in xxv_ethernet_v3_3 WARNING: [Synth 8-2507] parameter declaration becomes local in xxv_ethernet_v1_0_xilinx_cl73autoneg_an_pcontrol with formal parameter declaration list [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/05d5/hdl/xxv_ethernet_v3_3_vl_rfs.sv:279046] WARNING: [Synth 8-2507] parameter declaration becomes local in xxv_ethernet_v1_0_xilinx_cl73autoneg_an_pcontrol with formal parameter declaration list [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/05d5/hdl/xxv_ethernet_v3_3_vl_rfs.sv:279057] --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:10 . Memory (MB): peak = 2051.668 ; gain = 296.125 +Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 2055.477 ; gain = 295.695 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'pl_eth_10g_wrapper' [E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hdl/pl_eth_10g_wrapper.v:12] INFO: [Synth 8-6157] synthesizing module 'pl_eth_10g' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/synth/pl_eth_10g.v:1403] @@ -61,7 +61,7 @@ INFO: [Synth 8-638] synthesizing module 'pl_eth_10g_axi_dma_0_0' [e:/Photonic/ZC Parameter C_INCLUDE_MM2S_DRE bound to: 1 - type: integer Parameter C_INCLUDE_S2MM bound to: 1 - type: integer Parameter C_INCLUDE_S2MM_SF bound to: 1 - type: integer - Parameter C_S2MM_BURST_SIZE bound to: 8 - type: integer + Parameter C_S2MM_BURST_SIZE bound to: 16 - type: integer Parameter C_M_AXI_S2MM_ADDR_WIDTH bound to: 32 - type: integer Parameter C_M_AXI_S2MM_DATA_WIDTH bound to: 64 - type: integer Parameter C_S_AXIS_S2MM_TDATA_WIDTH bound to: 64 - type: integer @@ -92,7 +92,7 @@ INFO: [Synth 8-638] synthesizing module 'axi_dma' [e:/Photonic/ZCU106_ethernet/p Parameter C_INCLUDE_S2MM bound to: 1 - type: integer Parameter C_INCLUDE_S2MM_SF bound to: 1 - type: integer Parameter C_INCLUDE_S2MM_DRE bound to: 1 - type: integer - Parameter C_S2MM_BURST_SIZE bound to: 8 - type: integer + Parameter C_S2MM_BURST_SIZE bound to: 16 - type: integer Parameter C_M_AXI_S2MM_ADDR_WIDTH bound to: 32 - type: integer Parameter C_M_AXI_S2MM_DATA_WIDTH bound to: 64 - type: integer Parameter C_S_AXIS_S2MM_TDATA_WIDTH bound to: 64 - type: integer @@ -1348,7 +1348,7 @@ INFO: [Synth 8-638] synthesizing module 'axi_datamover' [e:/Photonic/ZCU106_ethe Parameter C_S2MM_STSCMD_FIFO_DEPTH bound to: 4 - type: integer Parameter C_S2MM_STSCMD_IS_ASYNC bound to: 1 - type: integer Parameter C_INCLUDE_S2MM_DRE bound to: 1 - type: integer - Parameter C_S2MM_BURST_SIZE bound to: 8 - type: integer + Parameter C_S2MM_BURST_SIZE bound to: 16 - type: integer Parameter C_S2MM_BTT_USED bound to: 16 - type: integer Parameter C_S2MM_SUPPORT_INDET_BTT bound to: 1 - type: integer Parameter C_S2MM_ADDR_PIPE_DEPTH bound to: 4 - type: integer @@ -2319,7 +2319,7 @@ INFO: [Synth 8-638] synthesizing module 'axi_datamover_s2mm_full_wrap' [e:/Photo Parameter C_S2MM_STSCMD_FIFO_DEPTH bound to: 16 - type: integer Parameter C_S2MM_STSCMD_IS_ASYNC bound to: 1 - type: integer Parameter C_INCLUDE_S2MM_DRE bound to: 1 - type: integer - Parameter C_S2MM_BURST_SIZE bound to: 8 - type: integer + Parameter C_S2MM_BURST_SIZE bound to: 16 - type: integer Parameter C_S2MM_BTT_USED bound to: 16 - type: integer Parameter C_S2MM_SUPPORT_INDET_BTT bound to: 1 - type: integer Parameter C_S2MM_ADDR_PIPE_DEPTH bound to: 4 - type: integer @@ -2621,12 +2621,12 @@ INFO: [Synth 8-256] done synthesizing module 'srl_fifo_f__parameterized6' (78#1) INFO: [Synth 8-256] done synthesizing module 'axi_datamover_fifo__parameterized6' (78#1) [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:1886] INFO: [Synth 8-256] done synthesizing module 'axi_datamover_wr_status_cntl' (79#1) [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:17704] INFO: [Synth 8-638] synthesizing module 'axi_datamover_ibttcc' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:25731] - Parameter C_SF_XFER_BYTES_WIDTH bound to: 7 - type: integer + Parameter C_SF_XFER_BYTES_WIDTH bound to: 8 - type: integer Parameter C_DRE_ALIGN_WIDTH bound to: 3 - type: integer Parameter C_SEL_ADDR_WIDTH bound to: 3 - type: integer Parameter C_ADDR_WIDTH bound to: 32 - type: integer Parameter C_STREAM_DWIDTH bound to: 64 - type: integer - Parameter C_MAX_BURST_LEN bound to: 8 - type: integer + Parameter C_MAX_BURST_LEN bound to: 16 - type: integer Parameter C_CMD_WIDTH bound to: 71 - type: integer Parameter C_TAG_WIDTH bound to: 4 - type: integer Parameter C_BTT_USED bound to: 16 - type: integer @@ -2724,9 +2724,9 @@ INFO: [Synth 8-256] done synthesizing module 'axi_datamover_s2mm_scatter' (85#1) INFO: [Synth 8-256] done synthesizing module 'axi_datamover_s2mm_realign' (86#1) [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:47011] INFO: [Synth 8-638] synthesizing module 'axi_datamover_indet_btt' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:28430] Parameter C_SF_FIFO_DEPTH bound to: 128 - type: integer - Parameter C_IBTT_XFER_BYTES_WIDTH bound to: 7 - type: integer + Parameter C_IBTT_XFER_BYTES_WIDTH bound to: 8 - type: integer Parameter C_STRT_OFFSET_WIDTH bound to: 1 - type: integer - Parameter C_MAX_BURST_LEN bound to: 8 - type: integer + Parameter C_MAX_BURST_LEN bound to: 16 - type: integer Parameter C_MMAP_DWIDTH bound to: 64 - type: integer Parameter C_STREAM_DWIDTH bound to: 64 - type: integer Parameter C_ENABLE_SKID_BUF bound to: 11111 - type: string @@ -2737,7 +2737,7 @@ INFO: [Synth 8-638] synthesizing module 'axi_datamover_stbs_set' [e:/Photonic/ZC Parameter C_STROBE_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'axi_datamover_stbs_set' (87#1) [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:23410] INFO: [Synth 8-638] synthesizing module 'axi_datamover_sfifo_autord__parameterized0' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:1295] - Parameter C_DWIDTH bound to: 9 - type: integer + Parameter C_DWIDTH bound to: 10 - type: integer Parameter C_DEPTH bound to: 16 - type: integer Parameter C_DATA_CNT_WIDTH bound to: 5 - type: integer Parameter C_NEED_ALMOST_EMPTY bound to: 0 - type: integer @@ -2758,26 +2758,26 @@ INFO: [Synth 8-638] synthesizing module 'sync_fifo_fg__parameterized0' [e:/Photo Parameter C_PORTS_DIFFER bound to: 0 - type: integer Parameter C_RD_ACK_LOW bound to: 0 - type: integer Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer - Parameter C_READ_DATA_WIDTH bound to: 9 - type: integer + Parameter C_READ_DATA_WIDTH bound to: 10 - type: integer Parameter C_READ_DEPTH bound to: 16 - type: integer Parameter C_RD_ERR_LOW bound to: 0 - type: integer Parameter C_WR_ACK_LOW bound to: 0 - type: integer Parameter C_WR_ERR_LOW bound to: 0 - type: integer Parameter C_PRELOAD_REGS bound to: 1 - type: integer Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer - Parameter C_WRITE_DATA_WIDTH bound to: 9 - type: integer + Parameter C_WRITE_DATA_WIDTH bound to: 10 - type: integer Parameter C_WRITE_DEPTH bound to: 16 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer Parameter C_XPM_FIFO bound to: 1 - type: integer Parameter FIFO_MEMORY_TYPE bound to: auto - type: string Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer - Parameter WRITE_DATA_WIDTH bound to: 9 - type: integer + Parameter WRITE_DATA_WIDTH bound to: 10 - type: integer Parameter READ_MODE bound to: fwft - type: string Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string - Parameter READ_DATA_WIDTH bound to: 9 - type: integer + Parameter READ_DATA_WIDTH bound to: 10 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 4 - type: integer @@ -2793,14 +2793,14 @@ INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized1' [C:/Xil Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer - Parameter WRITE_DATA_WIDTH bound to: 9 - type: integer + Parameter WRITE_DATA_WIDTH bound to: 10 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_MODE bound to: fwft - type: string Parameter FIFO_READ_LATENCY bound to: 0 - type: integer - Parameter READ_DATA_WIDTH bound to: 9 - type: integer + Parameter READ_DATA_WIDTH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 4 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string @@ -2819,13 +2819,13 @@ INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized3' [C:/Xil Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer - Parameter WRITE_DATA_WIDTH bound to: 9 - type: integer + Parameter WRITE_DATA_WIDTH bound to: 10 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_MODE bound to: 1 - type: integer Parameter FIFO_READ_LATENCY bound to: 0 - type: integer - Parameter READ_DATA_WIDTH bound to: 9 - type: integer + Parameter READ_DATA_WIDTH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 4 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string @@ -2842,7 +2842,7 @@ INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized3' [C:/Xil Parameter RD_MODE bound to: 1 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 16 - type: integer - Parameter FIFO_SIZE bound to: 144 - type: integer + Parameter FIFO_SIZE bound to: 160 - type: integer Parameter WR_WIDTH_LOG bound to: 4 - type: integer Parameter WR_DEPTH_LOG bound to: 4 - type: integer Parameter WR_PNTR_WIDTH bound to: 4 - type: integer @@ -2874,7 +2874,7 @@ INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized3' [C:/Xil Parameter EN_DVLD bound to: 1'b1 INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized3' [C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer - Parameter MEMORY_SIZE bound to: 144 - type: integer + Parameter MEMORY_SIZE bound to: 160 - type: integer Parameter MEMORY_PRIMITIVE bound to: 0 - type: integer Parameter CLOCKING_MODE bound to: 0 - type: integer Parameter ECC_MODE bound to: 0 - type: integer @@ -2891,32 +2891,32 @@ INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized3' [C:/X Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer - Parameter WRITE_DATA_WIDTH_A bound to: 9 - type: integer - Parameter READ_DATA_WIDTH_A bound to: 9 - type: integer - Parameter BYTE_WRITE_WIDTH_A bound to: 9 - type: integer + Parameter WRITE_DATA_WIDTH_A bound to: 10 - type: integer + Parameter READ_DATA_WIDTH_A bound to: 10 - type: integer + Parameter BYTE_WRITE_WIDTH_A bound to: 10 - type: integer Parameter ADDR_WIDTH_A bound to: 4 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter RST_MODE_A bound to: SYNC - type: string - Parameter WRITE_DATA_WIDTH_B bound to: 9 - type: integer - Parameter READ_DATA_WIDTH_B bound to: 9 - type: integer - Parameter BYTE_WRITE_WIDTH_B bound to: 9 - type: integer + Parameter WRITE_DATA_WIDTH_B bound to: 10 - type: integer + Parameter READ_DATA_WIDTH_B bound to: 10 - type: integer + Parameter BYTE_WRITE_WIDTH_B bound to: 10 - type: integer Parameter ADDR_WIDTH_B bound to: 4 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 2 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: auto - type: string - Parameter P_MIN_WIDTH_DATA_A bound to: 9 - type: integer - Parameter P_MIN_WIDTH_DATA_B bound to: 9 - type: integer - Parameter P_MIN_WIDTH_DATA bound to: 9 - type: integer - Parameter P_MIN_WIDTH_DATA_ECC bound to: 9 - type: integer + Parameter P_MIN_WIDTH_DATA_A bound to: 10 - type: integer + Parameter P_MIN_WIDTH_DATA_B bound to: 10 - type: integer + Parameter P_MIN_WIDTH_DATA bound to: 10 - type: integer + Parameter P_MIN_WIDTH_DATA_ECC bound to: 10 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 16 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string - Parameter P_WIDTH_COL_WRITE_A bound to: 9 - type: integer - Parameter P_WIDTH_COL_WRITE_B bound to: 9 - type: integer + Parameter P_WIDTH_COL_WRITE_A bound to: 10 - type: integer + Parameter P_WIDTH_COL_WRITE_B bound to: 10 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer @@ -2938,7 +2938,7 @@ INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized3' [C:/X Parameter rstb_loop_iter bound to: 12 - type: integer Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer - Parameter P_MIN_WIDTH_DATA_SHFT bound to: 9 - type: integer + Parameter P_MIN_WIDTH_DATA_SHFT bound to: 10 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. [C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:488] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized3' (87#1) [C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] @@ -11468,18 +11468,18 @@ WARNING: [Synth 8-7023] instance 'PS8_i' of module 'PS8' has 1015 connections de WARNING: [Synth 8-7023] instance 'inst' of module 'zynq_ultra_ps_e_v3_3_3_zynq_ultra_ps_e' has 1491 connections declared, but only 1487 given [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/synth/pl_eth_10g_zynq_ultra_ps_e_0_0.v:363] WARNING: [Synth 8-7023] instance 'zynq_ultra_ps_e_0' of module 'pl_eth_10g_zynq_ultra_ps_e_0_0' has 84 connections declared, but only 83 given [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/synth/pl_eth_10g.v:5770] --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:26 ; elapsed = 00:00:35 . Memory (MB): peak = 2787.715 ; gain = 1032.172 +Finished RTL Elaboration : Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2788.516 ; gain = 1028.734 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:30 ; elapsed = 00:00:39 . Memory (MB): peak = 2806.020 ; gain = 1050.477 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:30 ; elapsed = 00:00:38 . Memory (MB): peak = 2807.832 ; gain = 1048.051 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:39 . Memory (MB): peak = 2806.020 ; gain = 1050.477 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:38 . Memory (MB): peak = 2807.832 ; gain = 1048.051 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2806.020 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2807.832 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 756 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization @@ -11535,7 +11535,7 @@ Resolution: To avoid this warning, move constraints listed in [.Xil/pl_eth_10g_w INFO: [Project 1-1715] 7 XPM XDC files have been applied to the design. Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 2844.043 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 2848.312 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 756 instances were transformed. FDR => FDRE: 714 instances @@ -11543,9 +11543,9 @@ INFO: [Project 1-111] Unisim Transformation Summary: RAM64X1S => RAM64X1S (RAMS64E): 2 instances SRL16 => SRL16E: 1 instance -Constraint Validation Runtime : Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.786 . Memory (MB): peak = 2844.043 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.613 . Memory (MB): peak = 2848.312 ; gain = 0.000 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:01:01 ; elapsed = 00:01:16 . Memory (MB): peak = 2844.043 ; gain = 1088.500 +Finished Constraint Validation : Time (s): cpu = 00:01:03 ; elapsed = 00:01:14 . Memory (MB): peak = 2848.312 ; gain = 1088.531 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information @@ -11553,7 +11553,7 @@ Start Loading Part and Timing Information Loading part: xczu7ev-ffvc1156-2-e INFO: [Synth 8-6742] Reading net delay rules and data --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:01:01 ; elapsed = 00:01:16 . Memory (MB): peak = 2844.043 ; gain = 1088.500 +Finished Loading Part and Timing Information : Time (s): cpu = 00:01:03 ; elapsed = 00:01:14 . Memory (MB): peak = 2848.312 ; gain = 1088.531 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints @@ -11744,7 +11744,7 @@ Applied set_property KEEP_HIERARCHY = SOFT for pl_eth_10g_i/axi_dma_0/U0/I_PRMRY Applied set_property KEEP_HIERARCHY = SOFT for pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER /\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT /I_DATA_FIFO/\BLK_MEM.I_SYNC_FIFOGEN_FIFO /\xpm_fifo_instance.xpm_fifo_sync_inst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for pl_eth_10g_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER /\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT /I_XD_FIFO/\NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO /\xpm_fifo_instance.xpm_fifo_sync_inst . (constraint file auto generated constraint). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:02 ; elapsed = 00:01:17 . Memory (MB): peak = 2844.043 ; gain = 1088.500 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:03 ; elapsed = 00:01:15 . Memory (MB): peak = 2848.312 ; gain = 1088.531 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'ftch_cs_reg' in module 'axi_sg_ftch_sm' INFO: [Synth 8-802] inferred FSM for state register 'updt_cs_reg' in module 'axi_sg_updt_sm' @@ -12049,7 +12049,7 @@ INFO: [Synth 8-3354] encoded FSM with state register 'sig_psm_state_reg' using e chk_pop_second | 101 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sig_cmdcntl_sm_state_reg' using encoding 'sequential' in module 'axi_datamover_s2mm_realign' -INFO: [Synth 8-6904] The RAM "xpm_memory_base__parameterized3:/gen_wr_a.gen_word_narrow.mem_reg" of size (depth=16 x width=9) is automatically implemented using LUTRAM. BRAM implementation would be inefficient +INFO: [Synth 8-6904] The RAM "xpm_memory_base__parameterized3:/gen_wr_a.gen_word_narrow.mem_reg" of size (depth=16 x width=10) is automatically implemented using LUTRAM. BRAM implementation would be inefficient --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- @@ -12514,7 +12514,7 @@ INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_axi.write_cs_reg' using encoding 'one-hot' in module 'axi_crossbar_v2_1_23_decerr_slave__parameterized0' --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:16 ; elapsed = 00:01:45 . Memory (MB): peak = 2844.043 ; gain = 1088.500 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:23 ; elapsed = 00:01:41 . Memory (MB): peak = 2848.312 ; gain = 1088.531 --------------------------------------------------------------------------------- INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE @@ -12904,7 +12904,7 @@ INFO: [Synth 8-4471] merging register 'GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATU INFO: [Synth 8-4471] merging register 'sig_stop_request_reg' into 'sig_sready_stop_reg_reg' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:19578] INFO: [Synth 8-4471] merging register 'GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_reset_reg_reg' into 'I_DRE_CNTL_FIFO/sig_init_reg_reg' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:44276] INFO: [Synth 8-4471] merging register 'GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_stop_request_reg' into 'GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_sready_stop_reg_reg' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:44271] -INFO: [Synth 8-6904] The RAM "axi_dma_0/U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER /\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT /\I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst /gen_wr_a.gen_word_narrow.mem_reg" of size (depth=16 x width=9) is automatically implemented using LUTRAM. BRAM implementation would be inefficient +INFO: [Synth 8-6904] The RAM "axi_dma_0/U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER /\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT /\I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst /gen_wr_a.gen_word_narrow.mem_reg" of size (depth=16 x width=10) is automatically implemented using LUTRAM. BRAM implementation would be inefficient INFO: [Synth 8-4471] merging register 'ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_stop_request_reg' into 'ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_sready_stop_reg_reg' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:19578] INFO: [Synth 8-5546] ROM "DIFF_WIDTH_OR_DRE.I_IBTTCC_STBS_SET/lvar_num_set" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "DIFF_WIDTH_OR_DRE_WDC.I_WDC_STBS_SET/lvar_num_set" won't be mapped to RAM because it is too sparse @@ -12941,7 +12941,7 @@ INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM INFO: [Synth 8-5784] Optimized 10 bits of RAM "gen_wr_a.gen_word_narrow.mem_reg" due to constant propagation. Old ram width 35 bits, new ram width 25 bits. INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-7082] The signal gen_wr_a.gen_word_narrow.mem_reg is implemented as Block RAM but is better mapped onto distributed LUT RAM for the following reason(s): The depth (4 address bits) is shallow. Please use attribute (* ram_style = "distributed" *) to instruct Vivado to infer distributed LUT RAM. -INFO: [Synth 8-6904] The RAM "axi_dma_0/U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER /\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst /gen_wr_a.gen_word_narrow.mem_reg" of size (depth=16 x width=9) is automatically implemented using LUTRAM. BRAM implementation would be inefficient +INFO: [Synth 8-6904] The RAM "axi_dma_0/U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER /\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst /gen_wr_a.gen_word_narrow.mem_reg" of size (depth=16 x width=10) is automatically implemented using LUTRAM. BRAM implementation would be inefficient INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE @@ -13077,7 +13077,7 @@ INFO: [Synth 8-3332] Sequential element (GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:02:02 ; elapsed = 00:03:00 . Memory (MB): peak = 2844.043 ; gain = 1088.500 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:02:19 ; elapsed = 00:02:42 . Memory (MB): peak = 2848.312 ; gain = 1088.531 --------------------------------------------------------------------------------- INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE @@ -13095,7 +13095,7 @@ INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:12 ; elapsed = 00:03:17 . Memory (MB): peak = 3960.871 ; gain = 2205.328 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:31 ; elapsed = 00:02:58 . Memory (MB): peak = 3968.555 ; gain = 2208.773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization @@ -13140,7 +13140,7 @@ INFO: [Synth 8-5555] Implemented Block Ram Cascade chain of height 8 and width 3 INFO: [Synth 8-5555] Implemented Block Ram Cascade chain of height 8 and width 36 for RAM "pl_eth_10g_i/i_0/tx_data_fifo/\inst/gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst /gen_wr_a.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 1 for RAM "pl_eth_10g_i/i_0/tx_data_fifo/\inst/gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst /gen_wr_a.gen_word_narrow.mem_reg" --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:04:36 ; elapsed = 00:06:47 . Memory (MB): peak = 4409.379 ; gain = 2653.836 +Finished Timing Optimization : Time (s): cpu = 00:05:34 ; elapsed = 00:06:14 . Memory (MB): peak = 4417.777 ; gain = 2657.996 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping @@ -13162,7 +13162,7 @@ INFO: [Synth 8-7052] The timing for the instance pl_eth_10g_i/i_0/tx_data_fifo/i INFO: [Synth 8-7052] The timing for the instance pl_eth_10g_i/i_0/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_57 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance pl_eth_10g_i/i_0/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_65 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:04:45 ; elapsed = 00:07:24 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished Technology Mapping : Time (s): cpu = 00:05:46 ; elapsed = 00:06:53 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -13398,37 +13398,37 @@ WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/ WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/af2c/hdl/axi_register_slice_v2_1_vl_rfs.v:1756] INFO: [Common 17-14] Message 'Synth 8-5396' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:04:56 ; elapsed = 00:07:46 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished IO Insertion : Time (s): cpu = 00:06:03 ; elapsed = 00:07:11 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:04:56 ; elapsed = 00:07:46 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished Renaming Generated Instances : Time (s): cpu = 00:06:03 ; elapsed = 00:07:11 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:05:01 ; elapsed = 00:07:55 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:06:11 ; elapsed = 00:07:20 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:05:02 ; elapsed = 00:07:55 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished Renaming Generated Ports : Time (s): cpu = 00:06:12 ; elapsed = 00:07:20 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:05:03 ; elapsed = 00:07:57 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished Handling Custom Attributes : Time (s): cpu = 00:06:13 ; elapsed = 00:07:22 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:05:03 ; elapsed = 00:07:57 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished Renaming Generated Nets : Time (s): cpu = 00:06:13 ; elapsed = 00:07:22 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -13446,17 +13446,17 @@ Report Cell Usage: +------+--------------+------+ |1 |BUFG_GT | 4| |2 |BUFG_PS | 1| -|3 |CARRY8 | 681| +|3 |CARRY8 | 682| |4 |GTHE4_CHANNEL | 1| |5 |GTHE4_COMMON | 1| |6 |IBUFDS_GTE4 | 1| -|7 |LUT1 | 817| -|8 |LUT2 | 5305| -|9 |LUT3 | 3355| -|10 |LUT4 | 2350| -|11 |LUT5 | 3299| -|12 |LUT6 | 7470| -|13 |MUXF7 | 133| +|7 |LUT1 | 816| +|8 |LUT2 | 5300| +|9 |LUT3 | 3364| +|10 |LUT4 | 2359| +|11 |LUT5 | 3295| +|12 |LUT6 | 7462| +|13 |MUXF7 | 132| |14 |PS8 | 1| |15 |RAM32M | 13| |16 |RAM32M16 | 47| @@ -13464,30 +13464,30 @@ Report Cell Usage: |18 |RAMB18E2 | 4| |21 |RAMB36E2 | 135| |29 |SRL16 | 1| -|30 |SRL16E | 357| +|30 |SRL16E | 359| |31 |SRLC32E | 208| |32 |FDCE | 286| |33 |FDPE | 272| |34 |FDR | 331| -|35 |FDRE | 26290| +|35 |FDRE | 26304| |36 |FDSE | 1950| |37 |OBUF | 1| +------+--------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:05:03 ; elapsed = 00:07:57 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished Writing Synthesis Report : Time (s): cpu = 00:06:14 ; elapsed = 00:07:22 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 3718 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:04:05 ; elapsed = 00:07:28 . Memory (MB): peak = 4413.344 ; gain = 2619.777 -Synthesis Optimization Complete : Time (s): cpu = 00:05:03 ; elapsed = 00:08:00 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Synthesis finished with 0 errors, 0 critical warnings and 3719 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:05:15 ; elapsed = 00:06:54 . Memory (MB): peak = 4421.750 ; gain = 2621.488 +Synthesis Optimization Complete : Time (s): cpu = 00:06:14 ; elapsed = 00:07:24 . Memory (MB): peak = 4421.750 ; gain = 2661.969 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4426.688 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4435.031 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 1208 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-441] Inserted BUFG_GT_SYNC pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC for BUFG_GT pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst INFO: [Opt 31-441] Inserted BUFG_GT_SYNC pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_1 for BUFG_GT pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 4447.328 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 4455.641 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 394 instances were transformed. FDR => FDRE: 331 instances @@ -13499,9 +13499,9 @@ INFO: [Project 1-111] Unisim Transformation Summary: INFO: [Common 17-83] Releasing license: Synthesis 1401 Infos, 456 Warnings, 1 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:05:18 ; elapsed = 00:08:23 . Memory (MB): peak = 4447.328 ; gain = 3302.668 +synth_design: Time (s): cpu = 00:06:33 ; elapsed = 00:07:47 . Memory (MB): peak = 4455.641 ; gain = 3311.508 INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING INFO: [Common 17-1381] The checkpoint 'E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 4447.328 ; gain = 0.000 +write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 4455.641 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file pl_eth_10g_wrapper_utilization_synth.rpt -pb pl_eth_10g_wrapper_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Oct 20 12:54:06 2023... +INFO: [Common 17-206] Exiting Vivado at Fri Oct 20 19:38:10 2023... diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper_utilization_synth.pb b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper_utilization_synth.pb index a4c9470..b9a85a5 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper_utilization_synth.pb and b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper_utilization_synth.pb differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper_utilization_synth.rpt b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper_utilization_synth.rpt index 6284e38..b712753 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper_utilization_synth.rpt +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 -| Date : Fri Oct 20 12:54:06 2023 +| Date : Fri Oct 20 19:38:10 2023 | Host : DESKTOP-5FH9OH3 running 64-bit major release (build 9200) | Command : report_utilization -file pl_eth_10g_wrapper_utilization_synth.rpt -pb pl_eth_10g_wrapper_utilization_synth.pb | Design : pl_eth_10g_wrapper @@ -31,16 +31,16 @@ Table of Contents +----------------------------+-------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------------------+-------+-------+-----------+-------+ -| CLB LUTs* | 19622 | 0 | 230400 | 8.52 | +| CLB LUTs* | 19624 | 0 | 230400 | 8.52 | | LUT as Logic | 18626 | 0 | 230400 | 8.08 | -| LUT as Memory | 996 | 0 | 101760 | 0.98 | +| LUT as Memory | 998 | 0 | 101760 | 0.98 | | LUT as Distributed RAM | 430 | 0 | | | -| LUT as Shift Register | 566 | 0 | | | -| CLB Registers | 29129 | 0 | 460800 | 6.32 | -| Register as Flip Flop | 29129 | 0 | 460800 | 6.32 | +| LUT as Shift Register | 568 | 0 | | | +| CLB Registers | 29143 | 0 | 460800 | 6.32 | +| Register as Flip Flop | 29143 | 0 | 460800 | 6.32 | | Register as Latch | 0 | 0 | 460800 | 0.00 | -| CARRY8 | 681 | 0 | 28800 | 2.36 | -| F7 Muxes | 133 | 0 | 115200 | 0.12 | +| CARRY8 | 682 | 0 | 28800 | 2.37 | +| F7 Muxes | 132 | 0 | 115200 | 0.11 | | F8 Muxes | 0 | 0 | 57600 | 0.00 | | F9 Muxes | 0 | 0 | 28800 | 0.00 | +----------------------------+-------+-------+-----------+-------+ @@ -62,7 +62,7 @@ Table of Contents | 272 | Yes | - | Set | | 286 | Yes | - | Reset | | 1950 | Yes | Set | - | -| 26621 | Yes | Reset | - | +| 26635 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -159,22 +159,22 @@ Table of Contents +---------------+-------+---------------------+ | Ref Name | Used | Functional Category | +---------------+-------+---------------------+ -| FDRE | 26621 | Register | -| LUT6 | 7470 | CLB | -| LUT2 | 5305 | CLB | -| LUT3 | 3355 | CLB | -| LUT5 | 3299 | CLB | -| LUT4 | 2350 | CLB | +| FDRE | 26635 | Register | +| LUT6 | 7462 | CLB | +| LUT2 | 5300 | CLB | +| LUT3 | 3364 | CLB | +| LUT5 | 3295 | CLB | +| LUT4 | 2359 | CLB | | FDSE | 1950 | Register | -| LUT1 | 817 | CLB | +| LUT1 | 816 | CLB | | RAMD32 | 736 | CLB | -| CARRY8 | 681 | CLB | -| SRL16E | 358 | CLB | +| CARRY8 | 682 | CLB | +| SRL16E | 360 | CLB | | FDCE | 286 | Register | | FDPE | 272 | Register | | SRLC32E | 208 | CLB | | RAMB36E2 | 135 | BLOCKRAM | -| MUXF7 | 133 | CLB | +| MUXF7 | 132 | CLB | | RAMS32 | 120 | CLB | | RAMB18E2 | 4 | BLOCKRAM | | BUFG_GT | 4 | Clock | diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/runme.log b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/runme.log index 30f0b8e..906e0d6 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/runme.log +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/runme.log @@ -13,7 +13,7 @@ source pl_eth_10g_wrapper.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'. -add_files: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1144.660 ; gain = 0.000 +add_files: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1144.133 ; gain = 0.000 Command: synth_design -top pl_eth_10g_wrapper -part xczu7ev-ffvc1156-2-e Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xczu7ev' @@ -21,7 +21,7 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu7ev INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 22868 +INFO: [Synth 8-7075] Helper process launched with PID 166004 WARNING: [Synth 8-2507] parameter declaration becomes local in xxv_ethernet_v3_3_0_cl73autoneg_an_pcontrol with formal parameter declaration list [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/05d5/hdl/xxv_ethernet_v3_3_vl_rfs.sv:186854] WARNING: [Synth 8-2507] parameter declaration becomes local in xxv_ethernet_v3_3_0_cl73autoneg_an_pcontrol with formal parameter declaration list [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/05d5/hdl/xxv_ethernet_v3_3_vl_rfs.sv:186876] WARNING: [Synth 8-2507] parameter declaration becomes local in xxv_ethernet_v3_3_0_cl73autoneg_10G_an_pcontrol with formal parameter declaration list [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/05d5/hdl/xxv_ethernet_v3_3_vl_rfs.sv:190663] @@ -31,7 +31,7 @@ WARNING: [Synth 8-2507] parameter declaration becomes local in xxv_ethernet_v3_3 WARNING: [Synth 8-2507] parameter declaration becomes local in xxv_ethernet_v1_0_xilinx_cl73autoneg_an_pcontrol with formal parameter declaration list [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/05d5/hdl/xxv_ethernet_v3_3_vl_rfs.sv:279046] WARNING: [Synth 8-2507] parameter declaration becomes local in xxv_ethernet_v1_0_xilinx_cl73autoneg_an_pcontrol with formal parameter declaration list [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/05d5/hdl/xxv_ethernet_v3_3_vl_rfs.sv:279057] --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:10 . Memory (MB): peak = 2051.668 ; gain = 296.125 +Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 2055.477 ; gain = 295.695 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'pl_eth_10g_wrapper' [E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/hdl/pl_eth_10g_wrapper.v:12] INFO: [Synth 8-6157] synthesizing module 'pl_eth_10g' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/synth/pl_eth_10g.v:1403] @@ -61,7 +61,7 @@ INFO: [Synth 8-638] synthesizing module 'pl_eth_10g_axi_dma_0_0' [e:/Photonic/ZC Parameter C_INCLUDE_MM2S_DRE bound to: 1 - type: integer Parameter C_INCLUDE_S2MM bound to: 1 - type: integer Parameter C_INCLUDE_S2MM_SF bound to: 1 - type: integer - Parameter C_S2MM_BURST_SIZE bound to: 8 - type: integer + Parameter C_S2MM_BURST_SIZE bound to: 16 - type: integer Parameter C_M_AXI_S2MM_ADDR_WIDTH bound to: 32 - type: integer Parameter C_M_AXI_S2MM_DATA_WIDTH bound to: 64 - type: integer Parameter C_S_AXIS_S2MM_TDATA_WIDTH bound to: 64 - type: integer @@ -92,7 +92,7 @@ INFO: [Synth 8-638] synthesizing module 'axi_dma' [e:/Photonic/ZCU106_ethernet/p Parameter C_INCLUDE_S2MM bound to: 1 - type: integer Parameter C_INCLUDE_S2MM_SF bound to: 1 - type: integer Parameter C_INCLUDE_S2MM_DRE bound to: 1 - type: integer - Parameter C_S2MM_BURST_SIZE bound to: 8 - type: integer + Parameter C_S2MM_BURST_SIZE bound to: 16 - type: integer Parameter C_M_AXI_S2MM_ADDR_WIDTH bound to: 32 - type: integer Parameter C_M_AXI_S2MM_DATA_WIDTH bound to: 64 - type: integer Parameter C_S_AXIS_S2MM_TDATA_WIDTH bound to: 64 - type: integer @@ -1348,7 +1348,7 @@ INFO: [Synth 8-638] synthesizing module 'axi_datamover' [e:/Photonic/ZCU106_ethe Parameter C_S2MM_STSCMD_FIFO_DEPTH bound to: 4 - type: integer Parameter C_S2MM_STSCMD_IS_ASYNC bound to: 1 - type: integer Parameter C_INCLUDE_S2MM_DRE bound to: 1 - type: integer - Parameter C_S2MM_BURST_SIZE bound to: 8 - type: integer + Parameter C_S2MM_BURST_SIZE bound to: 16 - type: integer Parameter C_S2MM_BTT_USED bound to: 16 - type: integer Parameter C_S2MM_SUPPORT_INDET_BTT bound to: 1 - type: integer Parameter C_S2MM_ADDR_PIPE_DEPTH bound to: 4 - type: integer @@ -2319,7 +2319,7 @@ INFO: [Synth 8-638] synthesizing module 'axi_datamover_s2mm_full_wrap' [e:/Photo Parameter C_S2MM_STSCMD_FIFO_DEPTH bound to: 16 - type: integer Parameter C_S2MM_STSCMD_IS_ASYNC bound to: 1 - type: integer Parameter C_INCLUDE_S2MM_DRE bound to: 1 - type: integer - Parameter C_S2MM_BURST_SIZE bound to: 8 - type: integer + Parameter C_S2MM_BURST_SIZE bound to: 16 - type: integer Parameter C_S2MM_BTT_USED bound to: 16 - type: integer Parameter C_S2MM_SUPPORT_INDET_BTT bound to: 1 - type: integer Parameter C_S2MM_ADDR_PIPE_DEPTH bound to: 4 - type: integer @@ -2621,12 +2621,12 @@ INFO: [Synth 8-256] done synthesizing module 'srl_fifo_f__parameterized6' (78#1) INFO: [Synth 8-256] done synthesizing module 'axi_datamover_fifo__parameterized6' (78#1) [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:1886] INFO: [Synth 8-256] done synthesizing module 'axi_datamover_wr_status_cntl' (79#1) [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:17704] INFO: [Synth 8-638] synthesizing module 'axi_datamover_ibttcc' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:25731] - Parameter C_SF_XFER_BYTES_WIDTH bound to: 7 - type: integer + Parameter C_SF_XFER_BYTES_WIDTH bound to: 8 - type: integer Parameter C_DRE_ALIGN_WIDTH bound to: 3 - type: integer Parameter C_SEL_ADDR_WIDTH bound to: 3 - type: integer Parameter C_ADDR_WIDTH bound to: 32 - type: integer Parameter C_STREAM_DWIDTH bound to: 64 - type: integer - Parameter C_MAX_BURST_LEN bound to: 8 - type: integer + Parameter C_MAX_BURST_LEN bound to: 16 - type: integer Parameter C_CMD_WIDTH bound to: 71 - type: integer Parameter C_TAG_WIDTH bound to: 4 - type: integer Parameter C_BTT_USED bound to: 16 - type: integer @@ -2724,9 +2724,9 @@ INFO: [Synth 8-256] done synthesizing module 'axi_datamover_s2mm_scatter' (85#1) INFO: [Synth 8-256] done synthesizing module 'axi_datamover_s2mm_realign' (86#1) [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:47011] INFO: [Synth 8-638] synthesizing module 'axi_datamover_indet_btt' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:28430] Parameter C_SF_FIFO_DEPTH bound to: 128 - type: integer - Parameter C_IBTT_XFER_BYTES_WIDTH bound to: 7 - type: integer + Parameter C_IBTT_XFER_BYTES_WIDTH bound to: 8 - type: integer Parameter C_STRT_OFFSET_WIDTH bound to: 1 - type: integer - Parameter C_MAX_BURST_LEN bound to: 8 - type: integer + Parameter C_MAX_BURST_LEN bound to: 16 - type: integer Parameter C_MMAP_DWIDTH bound to: 64 - type: integer Parameter C_STREAM_DWIDTH bound to: 64 - type: integer Parameter C_ENABLE_SKID_BUF bound to: 11111 - type: string @@ -2737,7 +2737,7 @@ INFO: [Synth 8-638] synthesizing module 'axi_datamover_stbs_set' [e:/Photonic/ZC Parameter C_STROBE_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'axi_datamover_stbs_set' (87#1) [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:23410] INFO: [Synth 8-638] synthesizing module 'axi_datamover_sfifo_autord__parameterized0' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:1295] - Parameter C_DWIDTH bound to: 9 - type: integer + Parameter C_DWIDTH bound to: 10 - type: integer Parameter C_DEPTH bound to: 16 - type: integer Parameter C_DATA_CNT_WIDTH bound to: 5 - type: integer Parameter C_NEED_ALMOST_EMPTY bound to: 0 - type: integer @@ -2758,26 +2758,26 @@ INFO: [Synth 8-638] synthesizing module 'sync_fifo_fg__parameterized0' [e:/Photo Parameter C_PORTS_DIFFER bound to: 0 - type: integer Parameter C_RD_ACK_LOW bound to: 0 - type: integer Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer - Parameter C_READ_DATA_WIDTH bound to: 9 - type: integer + Parameter C_READ_DATA_WIDTH bound to: 10 - type: integer Parameter C_READ_DEPTH bound to: 16 - type: integer Parameter C_RD_ERR_LOW bound to: 0 - type: integer Parameter C_WR_ACK_LOW bound to: 0 - type: integer Parameter C_WR_ERR_LOW bound to: 0 - type: integer Parameter C_PRELOAD_REGS bound to: 1 - type: integer Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer - Parameter C_WRITE_DATA_WIDTH bound to: 9 - type: integer + Parameter C_WRITE_DATA_WIDTH bound to: 10 - type: integer Parameter C_WRITE_DEPTH bound to: 16 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer Parameter C_XPM_FIFO bound to: 1 - type: integer Parameter FIFO_MEMORY_TYPE bound to: auto - type: string Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer - Parameter WRITE_DATA_WIDTH bound to: 9 - type: integer + Parameter WRITE_DATA_WIDTH bound to: 10 - type: integer Parameter READ_MODE bound to: fwft - type: string Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string - Parameter READ_DATA_WIDTH bound to: 9 - type: integer + Parameter READ_DATA_WIDTH bound to: 10 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 4 - type: integer @@ -2793,14 +2793,14 @@ INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_sync__parameterized1' [C:/Xil Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer - Parameter WRITE_DATA_WIDTH bound to: 9 - type: integer + Parameter WRITE_DATA_WIDTH bound to: 10 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_MODE bound to: fwft - type: string Parameter FIFO_READ_LATENCY bound to: 0 - type: integer - Parameter READ_DATA_WIDTH bound to: 9 - type: integer + Parameter READ_DATA_WIDTH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 4 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string @@ -2819,13 +2819,13 @@ INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized3' [C:/Xil Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 16 - type: integer - Parameter WRITE_DATA_WIDTH bound to: 9 - type: integer + Parameter WRITE_DATA_WIDTH bound to: 10 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 5 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_MODE bound to: 1 - type: integer Parameter FIFO_READ_LATENCY bound to: 0 - type: integer - Parameter READ_DATA_WIDTH bound to: 9 - type: integer + Parameter READ_DATA_WIDTH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 4 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string @@ -2842,7 +2842,7 @@ INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized3' [C:/Xil Parameter RD_MODE bound to: 1 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 16 - type: integer - Parameter FIFO_SIZE bound to: 144 - type: integer + Parameter FIFO_SIZE bound to: 160 - type: integer Parameter WR_WIDTH_LOG bound to: 4 - type: integer Parameter WR_DEPTH_LOG bound to: 4 - type: integer Parameter WR_PNTR_WIDTH bound to: 4 - type: integer @@ -2874,7 +2874,7 @@ INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized3' [C:/Xil Parameter EN_DVLD bound to: 1'b1 INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized3' [C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer - Parameter MEMORY_SIZE bound to: 144 - type: integer + Parameter MEMORY_SIZE bound to: 160 - type: integer Parameter MEMORY_PRIMITIVE bound to: 0 - type: integer Parameter CLOCKING_MODE bound to: 0 - type: integer Parameter ECC_MODE bound to: 0 - type: integer @@ -2891,32 +2891,32 @@ INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized3' [C:/X Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer - Parameter WRITE_DATA_WIDTH_A bound to: 9 - type: integer - Parameter READ_DATA_WIDTH_A bound to: 9 - type: integer - Parameter BYTE_WRITE_WIDTH_A bound to: 9 - type: integer + Parameter WRITE_DATA_WIDTH_A bound to: 10 - type: integer + Parameter READ_DATA_WIDTH_A bound to: 10 - type: integer + Parameter BYTE_WRITE_WIDTH_A bound to: 10 - type: integer Parameter ADDR_WIDTH_A bound to: 4 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter RST_MODE_A bound to: SYNC - type: string - Parameter WRITE_DATA_WIDTH_B bound to: 9 - type: integer - Parameter READ_DATA_WIDTH_B bound to: 9 - type: integer - Parameter BYTE_WRITE_WIDTH_B bound to: 9 - type: integer + Parameter WRITE_DATA_WIDTH_B bound to: 10 - type: integer + Parameter READ_DATA_WIDTH_B bound to: 10 - type: integer + Parameter BYTE_WRITE_WIDTH_B bound to: 10 - type: integer Parameter ADDR_WIDTH_B bound to: 4 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 2 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: auto - type: string - Parameter P_MIN_WIDTH_DATA_A bound to: 9 - type: integer - Parameter P_MIN_WIDTH_DATA_B bound to: 9 - type: integer - Parameter P_MIN_WIDTH_DATA bound to: 9 - type: integer - Parameter P_MIN_WIDTH_DATA_ECC bound to: 9 - type: integer + Parameter P_MIN_WIDTH_DATA_A bound to: 10 - type: integer + Parameter P_MIN_WIDTH_DATA_B bound to: 10 - type: integer + Parameter P_MIN_WIDTH_DATA bound to: 10 - type: integer + Parameter P_MIN_WIDTH_DATA_ECC bound to: 10 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 16 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string - Parameter P_WIDTH_COL_WRITE_A bound to: 9 - type: integer - Parameter P_WIDTH_COL_WRITE_B bound to: 9 - type: integer + Parameter P_WIDTH_COL_WRITE_A bound to: 10 - type: integer + Parameter P_WIDTH_COL_WRITE_B bound to: 10 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer @@ -2938,7 +2938,7 @@ INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base__parameterized3' [C:/X Parameter rstb_loop_iter bound to: 12 - type: integer Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer - Parameter P_MIN_WIDTH_DATA_SHFT bound to: 9 - type: integer + Parameter P_MIN_WIDTH_DATA_SHFT bound to: 10 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. [C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:488] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base__parameterized3' (87#1) [C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] @@ -11468,18 +11468,18 @@ WARNING: [Synth 8-7023] instance 'PS8_i' of module 'PS8' has 1015 connections de WARNING: [Synth 8-7023] instance 'inst' of module 'zynq_ultra_ps_e_v3_3_3_zynq_ultra_ps_e' has 1491 connections declared, but only 1487 given [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/synth/pl_eth_10g_zynq_ultra_ps_e_0_0.v:363] WARNING: [Synth 8-7023] instance 'zynq_ultra_ps_e_0' of module 'pl_eth_10g_zynq_ultra_ps_e_0_0' has 84 connections declared, but only 83 given [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/synth/pl_eth_10g.v:5770] --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:26 ; elapsed = 00:00:35 . Memory (MB): peak = 2787.715 ; gain = 1032.172 +Finished RTL Elaboration : Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2788.516 ; gain = 1028.734 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:30 ; elapsed = 00:00:39 . Memory (MB): peak = 2806.020 ; gain = 1050.477 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:30 ; elapsed = 00:00:38 . Memory (MB): peak = 2807.832 ; gain = 1048.051 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:39 . Memory (MB): peak = 2806.020 ; gain = 1050.477 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:38 . Memory (MB): peak = 2807.832 ; gain = 1048.051 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2806.020 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2807.832 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 756 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization @@ -11535,7 +11535,7 @@ Resolution: To avoid this warning, move constraints listed in [.Xil/pl_eth_10g_w INFO: [Project 1-1715] 7 XPM XDC files have been applied to the design. Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 2844.043 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 2848.312 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 756 instances were transformed. FDR => FDRE: 714 instances @@ -11543,9 +11543,9 @@ INFO: [Project 1-111] Unisim Transformation Summary: RAM64X1S => RAM64X1S (RAMS64E): 2 instances SRL16 => SRL16E: 1 instance -Constraint Validation Runtime : Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.786 . Memory (MB): peak = 2844.043 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.613 . Memory (MB): peak = 2848.312 ; gain = 0.000 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:01:01 ; elapsed = 00:01:16 . Memory (MB): peak = 2844.043 ; gain = 1088.500 +Finished Constraint Validation : Time (s): cpu = 00:01:03 ; elapsed = 00:01:14 . Memory (MB): peak = 2848.312 ; gain = 1088.531 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information @@ -11855,7 +11855,7 @@ INFO: [Synth 8-3354] encoded FSM with state register 'sig_psm_state_reg' using e chk_pop_second | 101 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sig_cmdcntl_sm_state_reg' using encoding 'sequential' in module 'axi_datamover_s2mm_realign' -INFO: [Synth 8-6904] The RAM "xpm_memory_base__parameterized3:/gen_wr_a.gen_word_narrow.mem_reg" of size (depth=16 x width=9) is automatically implemented using LUTRAM. BRAM implementation would be inefficient +INFO: [Synth 8-6904] The RAM "xpm_memory_base__parameterized3:/gen_wr_a.gen_word_narrow.mem_reg" of size (depth=16 x width=10) is automatically implemented using LUTRAM. BRAM implementation would be inefficient --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- @@ -12320,7 +12320,7 @@ INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_axi.write_cs_reg' using encoding 'one-hot' in module 'axi_crossbar_v2_1_23_decerr_slave__parameterized0' --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:16 ; elapsed = 00:01:45 . Memory (MB): peak = 2844.043 ; gain = 1088.500 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:23 ; elapsed = 00:01:41 . Memory (MB): peak = 2848.312 ; gain = 1088.531 --------------------------------------------------------------------------------- INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE @@ -12710,7 +12710,7 @@ INFO: [Synth 8-4471] merging register 'GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATU INFO: [Synth 8-4471] merging register 'sig_stop_request_reg' into 'sig_sready_stop_reg_reg' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:19578] INFO: [Synth 8-4471] merging register 'GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_reset_reg_reg' into 'I_DRE_CNTL_FIFO/sig_init_reg_reg' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:44276] INFO: [Synth 8-4471] merging register 'GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_stop_request_reg' into 'GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_sready_stop_reg_reg' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:44271] -INFO: [Synth 8-6904] The RAM "axi_dma_0/U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER /\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT /\I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst /gen_wr_a.gen_word_narrow.mem_reg" of size (depth=16 x width=9) is automatically implemented using LUTRAM. BRAM implementation would be inefficient +INFO: [Synth 8-6904] The RAM "axi_dma_0/U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER /\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT /\I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst /gen_wr_a.gen_word_narrow.mem_reg" of size (depth=16 x width=10) is automatically implemented using LUTRAM. BRAM implementation would be inefficient INFO: [Synth 8-4471] merging register 'ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_stop_request_reg' into 'ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_sready_stop_reg_reg' [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/4ab6/hdl/axi_datamover_v5_1_vh_rfs.vhd:19578] INFO: [Synth 8-5546] ROM "DIFF_WIDTH_OR_DRE.I_IBTTCC_STBS_SET/lvar_num_set" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "DIFF_WIDTH_OR_DRE_WDC.I_WDC_STBS_SET/lvar_num_set" won't be mapped to RAM because it is too sparse @@ -12747,7 +12747,7 @@ INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM INFO: [Synth 8-5784] Optimized 10 bits of RAM "gen_wr_a.gen_word_narrow.mem_reg" due to constant propagation. Old ram width 35 bits, new ram width 25 bits. INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-7082] The signal gen_wr_a.gen_word_narrow.mem_reg is implemented as Block RAM but is better mapped onto distributed LUT RAM for the following reason(s): The depth (4 address bits) is shallow. Please use attribute (* ram_style = "distributed" *) to instruct Vivado to infer distributed LUT RAM. -INFO: [Synth 8-6904] The RAM "axi_dma_0/U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER /\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst /gen_wr_a.gen_word_narrow.mem_reg" of size (depth=16 x width=9) is automatically implemented using LUTRAM. BRAM implementation would be inefficient +INFO: [Synth 8-6904] The RAM "axi_dma_0/U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER /\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst /gen_wr_a.gen_word_narrow.mem_reg" of size (depth=16 x width=10) is automatically implemented using LUTRAM. BRAM implementation would be inefficient INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE @@ -12883,7 +12883,7 @@ INFO: [Synth 8-3332] Sequential element (GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:02:02 ; elapsed = 00:03:00 . Memory (MB): peak = 2844.043 ; gain = 1088.500 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:02:19 ; elapsed = 00:02:42 . Memory (MB): peak = 2848.312 ; gain = 1088.531 --------------------------------------------------------------------------------- INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM gen_wr_a.gen_word_narrow.mem_reg. Setting write mode to NO_CHANGE @@ -12901,7 +12901,7 @@ INFO: [Synth 8-5775] Found 'rw_addr_collision' attribute set to 'no' on SDP RAM Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:12 ; elapsed = 00:03:17 . Memory (MB): peak = 3960.871 ; gain = 2205.328 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:31 ; elapsed = 00:02:58 . Memory (MB): peak = 3968.555 ; gain = 2208.773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization @@ -12946,7 +12946,7 @@ INFO: [Synth 8-5555] Implemented Block Ram Cascade chain of height 8 and width 3 INFO: [Synth 8-5555] Implemented Block Ram Cascade chain of height 8 and width 36 for RAM "pl_eth_10g_i/i_0/tx_data_fifo/\inst/gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst /gen_wr_a.gen_word_narrow.mem_reg" INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of width 1 for RAM "pl_eth_10g_i/i_0/tx_data_fifo/\inst/gen_fifo.xpm_fifo_axis_inst /xpm_fifo_base_inst/\gen_sdpram.xpm_memory_base_inst /gen_wr_a.gen_word_narrow.mem_reg" --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:04:36 ; elapsed = 00:06:47 . Memory (MB): peak = 4409.379 ; gain = 2653.836 +Finished Timing Optimization : Time (s): cpu = 00:05:34 ; elapsed = 00:06:14 . Memory (MB): peak = 4417.777 ; gain = 2657.996 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping @@ -12968,7 +12968,7 @@ INFO: [Synth 8-7052] The timing for the instance pl_eth_10g_i/i_0/tx_data_fifo/i INFO: [Synth 8-7052] The timing for the instance pl_eth_10g_i/i_0/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_57 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance pl_eth_10g_i/i_0/tx_data_fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_65 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:04:45 ; elapsed = 00:07:24 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished Technology Mapping : Time (s): cpu = 00:05:46 ; elapsed = 00:06:53 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -13204,37 +13204,37 @@ WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/ WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [e:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.gen/sources_1/bd/pl_eth_10g/ipshared/af2c/hdl/axi_register_slice_v2_1_vl_rfs.v:1756] INFO: [Common 17-14] Message 'Synth 8-5396' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:04:56 ; elapsed = 00:07:46 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished IO Insertion : Time (s): cpu = 00:06:03 ; elapsed = 00:07:11 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:04:56 ; elapsed = 00:07:46 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished Renaming Generated Instances : Time (s): cpu = 00:06:03 ; elapsed = 00:07:11 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:05:01 ; elapsed = 00:07:55 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:06:11 ; elapsed = 00:07:20 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:05:02 ; elapsed = 00:07:55 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished Renaming Generated Ports : Time (s): cpu = 00:06:12 ; elapsed = 00:07:20 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:05:03 ; elapsed = 00:07:57 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished Handling Custom Attributes : Time (s): cpu = 00:06:13 ; elapsed = 00:07:22 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:05:03 ; elapsed = 00:07:57 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished Renaming Generated Nets : Time (s): cpu = 00:06:13 ; elapsed = 00:07:22 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -13252,17 +13252,17 @@ Report Cell Usage: +------+--------------+------+ |1 |BUFG_GT | 4| |2 |BUFG_PS | 1| -|3 |CARRY8 | 681| +|3 |CARRY8 | 682| |4 |GTHE4_CHANNEL | 1| |5 |GTHE4_COMMON | 1| |6 |IBUFDS_GTE4 | 1| -|7 |LUT1 | 817| -|8 |LUT2 | 5305| -|9 |LUT3 | 3355| -|10 |LUT4 | 2350| -|11 |LUT5 | 3299| -|12 |LUT6 | 7470| -|13 |MUXF7 | 133| +|7 |LUT1 | 816| +|8 |LUT2 | 5300| +|9 |LUT3 | 3364| +|10 |LUT4 | 2359| +|11 |LUT5 | 3295| +|12 |LUT6 | 7462| +|13 |MUXF7 | 132| |14 |PS8 | 1| |15 |RAM32M | 13| |16 |RAM32M16 | 47| @@ -13270,30 +13270,30 @@ Report Cell Usage: |18 |RAMB18E2 | 4| |21 |RAMB36E2 | 135| |29 |SRL16 | 1| -|30 |SRL16E | 357| +|30 |SRL16E | 359| |31 |SRLC32E | 208| |32 |FDCE | 286| |33 |FDPE | 272| |34 |FDR | 331| -|35 |FDRE | 26290| +|35 |FDRE | 26304| |36 |FDSE | 1950| |37 |OBUF | 1| +------+--------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:05:03 ; elapsed = 00:07:57 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Finished Writing Synthesis Report : Time (s): cpu = 00:06:14 ; elapsed = 00:07:22 . Memory (MB): peak = 4421.750 ; gain = 2661.969 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 3718 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:04:05 ; elapsed = 00:07:28 . Memory (MB): peak = 4413.344 ; gain = 2619.777 -Synthesis Optimization Complete : Time (s): cpu = 00:05:03 ; elapsed = 00:08:00 . Memory (MB): peak = 4413.344 ; gain = 2657.801 +Synthesis finished with 0 errors, 0 critical warnings and 3719 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:05:15 ; elapsed = 00:06:54 . Memory (MB): peak = 4421.750 ; gain = 2621.488 +Synthesis Optimization Complete : Time (s): cpu = 00:06:14 ; elapsed = 00:07:24 . Memory (MB): peak = 4421.750 ; gain = 2661.969 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4426.688 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4435.031 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 1208 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-441] Inserted BUFG_GT_SYNC pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC for BUFG_GT pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_rx_inst_0/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk2_inst INFO: [Opt 31-441] Inserted BUFG_GT_SYNC pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_gt/inst/gen_gtwizard_gthe4_top.pl_eth_10g_xxv_ethernet_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_1 for BUFG_GT pl_eth_10g_i/xxv_ethernet_0/inst/i_core_gtwiz_userclk_tx_inst_0/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 4447.328 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 4455.641 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 394 instances were transformed. FDR => FDRE: 331 instances @@ -13305,9 +13305,9 @@ INFO: [Project 1-111] Unisim Transformation Summary: INFO: [Common 17-83] Releasing license: Synthesis 1401 Infos, 456 Warnings, 1 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:05:18 ; elapsed = 00:08:23 . Memory (MB): peak = 4447.328 ; gain = 3302.668 +synth_design: Time (s): cpu = 00:06:33 ; elapsed = 00:07:47 . Memory (MB): peak = 4455.641 ; gain = 3311.508 INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING INFO: [Common 17-1381] The checkpoint 'E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper.dcp' has been generated. -write_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 4447.328 ; gain = 0.000 +write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 4455.641 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file pl_eth_10g_wrapper_utilization_synth.rpt -pb pl_eth_10g_wrapper_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Oct 20 12:54:06 2023... +INFO: [Common 17-206] Exiting Vivado at Fri Oct 20 19:38:10 2023... diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/vivado.jou b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/vivado.jou index e070193..4d55b70 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/vivado.jou +++ b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2020.2 (64-bit) # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 -# Start of session at: Fri Oct 20 12:45:24 2023 -# Process ID: 55912 +# Start of session at: Fri Oct 20 19:30:05 2023 +# Process ID: 145272 # Current directory: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/synth_1 # Command line: vivado.exe -log pl_eth_10g_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source pl_eth_10g_wrapper.tcl # Log file: E:/Photonic/ZCU106_ethernet/pl_eth_10g_zcu106/Hardware/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/pl_eth_10g_wrapper.vds diff --git a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/vivado.pb b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/vivado.pb index fb4d1cd..7a917a1 100644 Binary files a/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/vivado.pb and b/src/pl_eth_10g_hw/pl_eth_10g.runs/synth_1/vivado.pb differ diff --git a/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1.xci b/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1.xci index 50263e1..56c601c 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1.xci +++ b/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_auto_cc_1/pl_eth_10g_auto_cc_1.xci @@ -37,7 +37,7 @@ 1 0 0 - 4 + 8 2 1 16 @@ -78,7 +78,7 @@ 1 0 0 - 4 + 8 2 1 16 @@ -240,13 +240,13 @@ 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"0","logical_left":"31","logical_right":"0"},"AWLEN":{"physical_name":"m_axi_awlen","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0"},"AWSIZE":{"physical_name":"m_axi_awsize","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0"},"AWBURST":{"physical_name":"m_axi_awburst","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0"},"AWLOCK":{"physical_name":"m_axi_awlock","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"AWCACHE":{"physical_name":"m_axi_awcache","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0"},"AWPROT":{"physical_name":"m_axi_awprot","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0"},"AWREGION":{"physical_name":"m_axi_awregion","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0"},"AWQOS":{"physical_name":"m_axi_awqos","physical_left":"3","physical_right":"0","logical_left" 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+","logical_left":"0","logical_right":"0"},"WVALID":{"physical_name":"m_axi_wvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"WREADY":{"physical_name":"m_axi_wready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"BRESP":{"physical_name":"m_axi_bresp","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0"},"BVALID":{"physical_name":"m_axi_bvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"BREADY":{"physical_name":"m_axi_bready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"CLK":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"FREQ_HZ":[{"value":"156250000"},{"value_src":"user_prop"},{"value_permission":"bd"},{"resolve_type":"user"}],"FREQ_TOLERANCE_HZ":[{"value":"0"},{"value_src":"default"},{"value_permission":"bd"},{"resolve_type":"generated +"}],"PHASE":[{"value":"0"},{"value_src":"user_prop"},{"value_permission":"bd"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":"pl_eth_10g_xxv_ethernet_0_0_rx_clk_out_0"},{"value_src":"default_prop"},{"value_permission":"bd"},{"resolve_type":"generated"}],"ASSOCIATED_BUSIF":[{"value":"S_AXI:M_AXI"},{"value_src":"default"},{"value_permission":"bd"},{"resolve_type":"generated"}],"ASSOCIATED_RESET":[{"value":"ARESETN"},{"value_src":"default"},{"value_permission":"bd"},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"CLK":{"physical_name":"aclk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"RST":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"POLARITY":[{"value":"ACTIVE_LOW"},{"value_src":"constant"},{"value_permission":"bd"},{"resolve_type":"generated"}],"INSERT_VIP":[{"valu +e":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}],"TYPE":[{"value":"INTERCONNECT"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}]},"port_maps":{"RST":{"physical_name":"aresetn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}}}}}"/>     diff --git a/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/pl_eth_10g_zynq_ultra_ps_e_0_0.xci b/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/pl_eth_10g_zynq_ultra_ps_e_0_0.xci index a7bf183..03485a8 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/pl_eth_10g_zynq_ultra_ps_e_0_0.xci +++ b/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ip/pl_eth_10g_zynq_ultra_ps_e_0_0/pl_eth_10g_zynq_ultra_ps_e_0_0.xci @@ -1450,7 +1450,7 @@ MIO 24 .. 25 1199.988037 1 - 1200 + 1333.333 APLL 0 667 @@ -1544,7 +1544,7 @@ APLL 499.994995 1 - 500 + 600 IOPLL -1 -1 @@ -1576,7 +1576,7 @@ 3 499.994995 3 - 500 + 533.333 IOPLL 500 3 @@ -1600,7 +1600,7 @@ IOPLL 499.994995 3 - 500 + 533.333 IOPLL 500 4 @@ -1661,7 +1661,7 @@ 3 249.997498 6 - 250 + 267 IOPLL 99.999001 15 @@ -1669,7 +1669,7 @@ IOPLL 499.994995 3 - 500 + 533.333 IOPLL 100 15 @@ -1704,10 +1704,10 @@ 1 100 RPLL - 124.998749 - 12 + 299.997009 + 5 1 - 125 + 300 IOPLL 1 90 diff --git a/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/pl_eth_10g.bd b/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/pl_eth_10g.bd index 7132375..767fc0c 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/pl_eth_10g.bd +++ b/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/pl_eth_10g.bd @@ -114,7 +114,7 @@ "value": "64" }, "c_s2mm_burst_size": { - "value": "8" + "value": "16" }, "c_sg_include_stscntrl_strm": { "value": "0" @@ -902,17 +902,17 @@ "auto_us/S_AXI" ] }, - "auto_us_to_auto_cc": { - "interface_ports": [ - "auto_us/M_AXI", - "auto_cc/S_AXI" - ] - }, "auto_cc_to_s02_couplers": { "interface_ports": [ "M_AXI", "auto_cc/M_AXI" ] + }, + "auto_us_to_auto_cc": { + "interface_ports": [ + "auto_us/M_AXI", + "auto_cc/S_AXI" + ] } }, "nets": { @@ -1048,16 +1048,10 @@ "xbar/S00_AXI" ] }, - "xbar_to_m00_couplers": { + "m00_couplers_to_axi_pl_ps": { "interface_ports": [ - "xbar/M00_AXI", - "m00_couplers/S_AXI" - ] - }, - "s01_couplers_to_xbar": { - "interface_ports": [ - "s01_couplers/M_AXI", - "xbar/S01_AXI" + "M00_AXI", + "m00_couplers/M_AXI" ] }, "s02_couplers_to_xbar": { @@ -1066,10 +1060,16 @@ "xbar/S02_AXI" ] }, - "m00_couplers_to_axi_pl_ps": { + "xbar_to_m00_couplers": { "interface_ports": [ - "M00_AXI", - "m00_couplers/M_AXI" + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + }, + "S01_AXI_1": { + "interface_ports": [ + "S01_AXI", + "s01_mmu/S_AXI" ] }, "s01_mmu_M_AXI": { @@ -1078,6 +1078,18 @@ "s01_couplers/S_AXI" ] }, + "s00_mmu_M_AXI": { + "interface_ports": [ + "s00_mmu/M_AXI", + "s00_couplers/S_AXI" + ] + }, + "S00_AXI_1": { + "interface_ports": [ + "S00_AXI", + "s00_mmu/S_AXI" + ] + }, "s02_mmu_M_AXI": { "interface_ports": [ "s02_mmu/M_AXI", @@ -1090,22 +1102,10 @@ "s02_mmu/S_AXI" ] }, - "S01_AXI_1": { + "s01_couplers_to_xbar": { "interface_ports": [ - "S01_AXI", - "s01_mmu/S_AXI" - ] - }, - "S00_AXI_1": { - "interface_ports": [ - "S00_AXI", - "s00_mmu/S_AXI" - ] - }, - "s00_mmu_M_AXI": { - "interface_ports": [ - "s00_mmu/M_AXI", - "s00_couplers/S_AXI" + "s01_couplers/M_AXI", + "xbar/S01_AXI" ] } }, @@ -1598,10 +1598,10 @@ } }, "interface_nets": { - "auto_ds_to_auto_pc": { + "m01_couplers_to_auto_ds": { "interface_ports": [ - "auto_ds/M_AXI", - "auto_pc/S_AXI" + "S_AXI", + "auto_ds/S_AXI" ] }, "auto_pc_to_m01_couplers": { @@ -1610,10 +1610,10 @@ "auto_pc/M_AXI" ] }, - "m01_couplers_to_auto_ds": { + "auto_ds_to_auto_pc": { "interface_ports": [ - "S_AXI", - "auto_ds/S_AXI" + "auto_ds/M_AXI", + "auto_pc/S_AXI" ] } }, @@ -1690,16 +1690,28 @@ } }, "interface_nets": { + "m02_couplers_to_ps_axi_periph": { + "interface_ports": [ + "M02_AXI", + "m02_couplers/M_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + }, "xbar_to_m02_couplers": { "interface_ports": [ "xbar/M02_AXI", "m02_couplers/S_AXI" ] }, - "ps_axi_periph_to_s00_couplers": { + "m01_couplers_to_ps_axi_periph": { "interface_ports": [ - "S00_AXI", - "s00_couplers/S_AXI" + "M01_AXI", + "m01_couplers/M_AXI" ] }, "s00_couplers_to_xbar": { @@ -1714,29 +1726,17 @@ "m00_couplers/M_AXI" ] }, + "ps_axi_periph_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, "xbar_to_m01_couplers": { "interface_ports": [ "xbar/M01_AXI", "m01_couplers/S_AXI" ] - }, - "xbar_to_m00_couplers": { - "interface_ports": [ - "xbar/M00_AXI", - "m00_couplers/S_AXI" - ] - }, - "m01_couplers_to_ps_axi_periph": { - "interface_ports": [ - "M01_AXI", - "m01_couplers/M_AXI" - ] - }, - "m02_couplers_to_ps_axi_periph": { - "interface_ports": [ - "M02_AXI", - "m02_couplers/M_AXI" - ] } }, "nets": { @@ -2764,7 +2764,7 @@ "value": "1199.988037" }, "PSU__CRF_APB__ACPU_CTRL__FREQMHZ": { - "value": "1200" + "value": "1333.333" }, "PSU__CRF_APB__ACPU_CTRL__SRCSEL": { "value": "APLL" @@ -2974,7 +2974,7 @@ "value": "499.994995" }, "PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ": { - "value": "500" + "value": "600" }, "PSU__CRF_APB__GPU_REF_CTRL__SRCSEL": { "value": "IOPLL" @@ -3040,7 +3040,7 @@ "value": "499.994995" }, "PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ": { - "value": "500" + "value": "533.333" }, "PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL": { "value": "IOPLL" @@ -3088,7 +3088,7 @@ "value": "499.994995" }, "PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ": { - "value": "500" + "value": "533.333" }, "PSU__CRL_APB__CPU_R5_CTRL__SRCSEL": { "value": "IOPLL" @@ -3208,7 +3208,7 @@ "value": "249.997498" }, "PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ": { - "value": "250" + "value": "267" }, "PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL": { "value": "IOPLL" @@ -3226,7 +3226,7 @@ "value": "499.994995" }, "PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ": { - "value": "500" + "value": "533.333" }, "PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL": { "value": "IOPLL" @@ -3286,10 +3286,10 @@ "value": "100" }, "PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ": { - "value": "124.998749" + "value": "299.997009" }, "PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ": { - "value": "125" + "value": "300" }, "PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL": { "value": "IOPLL" @@ -4973,16 +4973,10 @@ } }, "interface_nets": { - "Conn5": { + "Conn1": { "interface_ports": [ - "M01_AXI", - "ps_axi_periph/M01_AXI" - ] - }, - "Conn2": { - "interface_ports": [ - "S02_AXI", - "axi_pl_ps/S02_AXI" + "S00_AXI", + "axi_pl_ps/S00_AXI" ] }, "S00_AXI_1": { @@ -4991,10 +4985,16 @@ "zynq_ultra_ps_e_0/M_AXI_HPM0_LPD" ] }, - "Conn1": { + "Conn2": { "interface_ports": [ - "S00_AXI", - "axi_pl_ps/S00_AXI" + "S02_AXI", + "axi_pl_ps/S02_AXI" + ] + }, + "Conn5": { + "interface_ports": [ + "M01_AXI", + "ps_axi_periph/M01_AXI" ] }, "Conn3": { @@ -5003,17 +5003,17 @@ "axi_pl_ps/S01_AXI" ] }, - "axi_pl_ps_M00_AXI": { - "interface_ports": [ - "axi_pl_ps/M00_AXI", - "zynq_ultra_ps_e_0/S_AXI_HP0_FPD" - ] - }, "Conn4": { "interface_ports": [ "M00_AXI", "ps_axi_periph/M00_AXI" ] + }, + "axi_pl_ps_M00_AXI": { + "interface_ports": [ + "axi_pl_ps/M00_AXI", + "zynq_ultra_ps_e_0/S_AXI_HP0_FPD" + ] } }, "nets": { @@ -5118,10 +5118,16 @@ } }, "interface_nets": { - "axis_data_fifo_1_M_AXIS": { + "axi_dma_0_M_AXI_S2MM": { "interface_ports": [ - "axi_dma_0/S_AXIS_S2MM", - "rx_data_fifo/M_AXIS" + "axi_dma_0/M_AXI_S2MM", + "zups/S02_AXI" + ] + }, + "xxv_ethernet_0_gt_tx": { + "interface_ports": [ + "gt_tx", + "xxv_ethernet_0/gt_tx" ] }, "axi_dma_0_M_AXI_MM2S": { @@ -5136,24 +5142,6 @@ "zups/S00_AXI" ] }, - "xxv_ethernet_0_gt_tx": { - "interface_ports": [ - "gt_tx", - "xxv_ethernet_0/gt_tx" - ] - }, - "axi_dma_0_M_AXI_S2MM": { - "interface_ports": [ - "axi_dma_0/M_AXI_S2MM", - "zups/S02_AXI" - ] - }, - "axi_dma_0_M_AXIS_MM2S": { - "interface_ports": [ - "axi_dma_0/M_AXIS_MM2S", - "tx_data_fifo/S_AXIS" - ] - }, "gt_rx_1": { "interface_ports": [ "gt_rx", @@ -5166,6 +5154,30 @@ "zups/M00_AXI" ] }, + "axi_dma_0_M_AXIS_MM2S": { + "interface_ports": [ + "axi_dma_0/M_AXIS_MM2S", + "tx_data_fifo/S_AXIS" + ] + }, + "zups_M01_AXI": { + "interface_ports": [ + "xxv_ethernet_0/s_axi_0", + "zups/M01_AXI" + ] + }, + "axis_data_fifo_1_M_AXIS": { + "interface_ports": [ + "axi_dma_0/S_AXIS_S2MM", + "rx_data_fifo/M_AXIS" + ] + }, + "axis_data_fifo_0_M_AXIS": { + "interface_ports": [ + "tx_data_fifo/M_AXIS", + "xxv_ethernet_0/axis_tx_0" + ] + }, "gt_ref_clk_1": { "interface_ports": [ "gt_ref_clk", @@ -5177,18 +5189,6 @@ "rx_data_fifo/S_AXIS", "xxv_ethernet_0/axis_rx_0" ] - }, - "zups_M01_AXI": { - "interface_ports": [ - "xxv_ethernet_0/s_axi_0", - "zups/M01_AXI" - ] - }, - "axis_data_fifo_0_M_AXIS": { - "interface_ports": [ - "tx_data_fifo/M_AXIS", - "xxv_ethernet_0/axis_tx_0" - ] } }, "nets": { diff --git a/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/pl_eth_10g.bda b/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/pl_eth_10g.bda index d142c62..a8efa14 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/pl_eth_10g.bda +++ b/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/pl_eth_10g.bda @@ -21,6 +21,101 @@ + 0xC0000000 + C_BASEADDR + 0xDFFFFFFF + C_HIGHADDR + Data_S2MM + /axi_dma_0 + M_AXI_S2MM + SEG_zynq_ultra_ps_e_0_HP0_QSPI + xilinx.com:ip:axi_dma:7.1 + both + /zups/zynq_ultra_ps_e_0 + S_AXI_HP0_FPD + HP0_QSPI + xilinx.com:ip:zynq_ultra_ps_e:3.3 + memory + AC + + + 0xE0000000 + C_BASEADDR + 0xEFFFFFFF + C_HIGHADDR + Data_SG + /axi_dma_0 + M_AXI_SG + SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW + xilinx.com:ip:axi_dma:7.1 + both + /zups/zynq_ultra_ps_e_0 + S_AXI_HP0_FPD + HP0_PCIE_LOW + xilinx.com:ip:zynq_ultra_ps_e:3.3 + memory + AC + + + 0xC0000000 + C_BASEADDR + 0xDFFFFFFF + C_HIGHADDR + Data_SG + /axi_dma_0 + M_AXI_SG + SEG_zynq_ultra_ps_e_0_HP0_QSPI + xilinx.com:ip:axi_dma:7.1 + both + /zups/zynq_ultra_ps_e_0 + S_AXI_HP0_FPD + HP0_QSPI + xilinx.com:ip:zynq_ultra_ps_e:3.3 + memory + AC + + + 0xC0000000 + C_BASEADDR + 0xDFFFFFFF + C_HIGHADDR + Data_MM2S + /axi_dma_0 + M_AXI_MM2S + SEG_zynq_ultra_ps_e_0_HP0_QSPI + xilinx.com:ip:axi_dma:7.1 + both + /zups/zynq_ultra_ps_e_0 + S_AXI_HP0_FPD + HP0_QSPI + xilinx.com:ip:zynq_ultra_ps_e:3.3 + memory + AC + + + 2 + pl_eth_10g + VR + + + 0xE0000000 + C_BASEADDR + 0xEFFFFFFF + C_HIGHADDR + Data_MM2S + /axi_dma_0 + M_AXI_MM2S + SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW + xilinx.com:ip:axi_dma:7.1 + both + /zups/zynq_ultra_ps_e_0 + S_AXI_HP0_FPD + HP0_PCIE_LOW + xilinx.com:ip:zynq_ultra_ps_e:3.3 + memory + AC + + 0x00000000 C_BASEADDR 0x7FFFFFFF @@ -38,52 +133,7 @@ memory AC - - active - 2 - PM - - - pl_eth_10g - BC - - - 0xE0000000 - C_BASEADDR - 0xEFFFFFFF - C_HIGHADDR - Data_S2MM - /axi_dma_0 - M_AXI_S2MM - SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW - xilinx.com:ip:axi_dma:7.1 - both - /zups/zynq_ultra_ps_e_0 - S_AXI_HP0_FPD - HP0_PCIE_LOW - xilinx.com:ip:zynq_ultra_ps_e:3.3 - memory - AC - - - 0xE0000000 - C_BASEADDR - 0xEFFFFFFF - C_HIGHADDR - Data_MM2S - /axi_dma_0 - M_AXI_MM2S - SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW - xilinx.com:ip:axi_dma:7.1 - both - /zups/zynq_ultra_ps_e_0 - S_AXI_HP0_FPD - HP0_PCIE_LOW - xilinx.com:ip:zynq_ultra_ps_e:3.3 - memory - AC - - + 0x0080010000 C_BASEADDR 0x008001FFFF @@ -101,61 +151,7 @@ register AC - - 0xE0000000 - C_BASEADDR - 0xEFFFFFFF - C_HIGHADDR - Data_SG - /axi_dma_0 - M_AXI_SG - SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW - xilinx.com:ip:axi_dma:7.1 - both - /zups/zynq_ultra_ps_e_0 - S_AXI_HP0_FPD - HP0_PCIE_LOW - xilinx.com:ip:zynq_ultra_ps_e:3.3 - memory - AC - - - 0xC0000000 - C_BASEADDR - 0xDFFFFFFF - C_HIGHADDR - Data_SG - /axi_dma_0 - M_AXI_SG - SEG_zynq_ultra_ps_e_0_HP0_QSPI - xilinx.com:ip:axi_dma:7.1 - both - /zups/zynq_ultra_ps_e_0 - S_AXI_HP0_FPD - HP0_QSPI - xilinx.com:ip:zynq_ultra_ps_e:3.3 - memory - AC - - 0xC0000000 - C_BASEADDR - 0xDFFFFFFF - C_HIGHADDR - Data_MM2S - /axi_dma_0 - M_AXI_MM2S - SEG_zynq_ultra_ps_e_0_HP0_QSPI - xilinx.com:ip:axi_dma:7.1 - both - /zups/zynq_ultra_ps_e_0 - S_AXI_HP0_FPD - HP0_QSPI - xilinx.com:ip:zynq_ultra_ps_e:3.3 - memory - AC - - 0x0080000000 C_BASEADDR 0x008000FFFF @@ -173,7 +169,7 @@ register AC - + 0x00000000 C_BASEADDR 0x7FFFFFFF @@ -191,7 +187,7 @@ memory AC - + 0x00000000 C_BASEADDR 0x7FFFFFFF @@ -209,30 +205,29 @@ memory AC + + pl_eth_10g + BC + - 0xC0000000 + 0xE0000000 C_BASEADDR - 0xDFFFFFFF + 0xEFFFFFFF C_HIGHADDR Data_S2MM /axi_dma_0 M_AXI_S2MM - SEG_zynq_ultra_ps_e_0_HP0_QSPI + SEG_zynq_ultra_ps_e_0_HP0_PCIE_LOW xilinx.com:ip:axi_dma:7.1 both /zups/zynq_ultra_ps_e_0 S_AXI_HP0_FPD - HP0_QSPI + HP0_PCIE_LOW xilinx.com:ip:zynq_ultra_ps_e:3.3 memory AC - 2 - pl_eth_10g - VR - - 0xFF000000 C_BASEADDR 0xFFFFFFFF @@ -250,44 +245,49 @@ register AC - + + active + 2 + PM + + - + - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 - + 2 diff --git a/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ui/bd_293b12bf.ui b/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ui/bd_293b12bf.ui index b3908ac..1498245 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ui/bd_293b12bf.ui +++ b/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ui/bd_293b12bf.ui @@ -1,7 +1,7 @@ { "ActiveEmotionalView":"Default View", "Default View_ScaleFactor":"0.632957", - "Default View_TopLeft":"-395,-13", + "Default View_TopLeft":"68,-13", "ExpandedHierarchyInLayout":"", "comment_0":"PL ETHERNET 10G", "comment_1":"PL ETHERNET 10G", @@ -57,18 +57,18 @@ preplace netloc xxv_ethernet_0_user_tx_reset_0 1 2 4 700 1130 NJ 1130 NJ 1130 19 preplace netloc zups_Res 1 4 1 1490 140n preplace netloc zups_peripheral_aresetn 1 2 3 690 450 NJ 450 1460 preplace netloc zups_peripheral_reset 1 4 1 1470 180n -preplace netloc axi_dma_0_M_AXI_S2MM 1 3 1 N 110 +preplace netloc axis_data_fifo_1_M_AXIS 1 2 1 N 100 +preplace netloc axi_dma_0_M_AXI_MM2S 1 3 1 N 90 preplace netloc axi_dma_0_M_AXI_SG 1 3 1 N 70 +preplace netloc xxv_ethernet_0_gt_tx 1 5 1 NJ 580 +preplace netloc axi_dma_0_M_AXI_S2MM 1 3 1 N 110 +preplace netloc axi_dma_0_M_AXIS_MM2S 1 3 1 1040 130n preplace netloc gt_rx_1 1 0 5 NJ 530 NJ 530 NJ 530 NJ 530 NJ preplace netloc zups_M00_AXI 1 2 3 680 430 NJ 430 1440 -preplace netloc xxv_ethernet_0_gt_tx 1 5 1 NJ 580 -preplace netloc axis_data_fifo_1_M_AXIS 1 2 1 N 100 -preplace netloc axis_data_fifo_0_M_AXIS 1 4 1 1480 320n preplace netloc gt_ref_clk_1 1 0 5 NJ 510 NJ 510 NJ 510 NJ 510 NJ -preplace netloc axi_dma_0_M_AXI_MM2S 1 3 1 N 90 -preplace netloc axi_dma_0_M_AXIS_MM2S 1 3 1 1040 130n preplace netloc xxv_ethernet_0_axis_rx_0 1 1 5 330 420 NJ 420 NJ 420 NJ 420 1920 preplace netloc zups_M01_AXI 1 4 1 1510 120n +preplace netloc axis_data_fifo_0_M_AXIS 1 4 1 1480 320n preplace cgraphic comment_3 place top 0 0 textcolor 4 linecolor 3 preplace cgraphic comment_2 place top 0 0 textcolor 4 linecolor 3 preplace cgraphic comment_1 place top 0 0 textcolor 4 linecolor 3 diff --git a/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ui/bd_c090a0bd.ui b/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ui/bd_c090a0bd.ui index 4d9580b..b235494 100644 --- a/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ui/bd_c090a0bd.ui +++ b/src/pl_eth_10g_hw/pl_eth_10g.srcs/sources_1/bd/pl_eth_10g/ui/bd_c090a0bd.ui @@ -39,15 +39,15 @@ preplace netloc util_vector_logic_0_Res 1 3 1 NJ 470 preplace netloc xlconcat_0_dout 1 1 1 340 230n preplace netloc zynq_ultra_ps_e_0_pl_clk0 1 0 4 10 500 330 290 960 110 NJ preplace netloc zynq_ultra_ps_e_0_pl_resetn0 1 1 2 350 430 950 -preplace netloc Conn4 1 3 1 NJ 250 preplace netloc Conn5 1 3 1 NJ 270 -preplace netloc S00_AXI_1 1 2 1 N 170 -preplace netloc axi_pl_ps_M00_AXI 1 1 1 N 170 -preplace netloc Conn1 1 0 1 NJ 50 preplace netloc Conn2 1 0 1 NJ 90 +preplace netloc S00_AXI_1 1 2 1 N 170 +preplace netloc Conn1 1 0 1 NJ 50 preplace netloc Conn3 1 0 1 NJ 70 +preplace netloc axi_pl_ps_M00_AXI 1 1 1 N 170 +preplace netloc Conn4 1 3 1 NJ 250 levelinfo -pg 1 -10 180 650 1130 1300 pagesize -pg 1 -db -bbox -sgen -160 -10 1500 640 " } - +0 diff --git a/src/pre-built/pl_eth_10g_wrapper.xsa b/src/pre-built/pl_eth_10g_wrapper.xsa index 14ae698..c792f43 100644 Binary files a/src/pre-built/pl_eth_10g_wrapper.xsa and b/src/pre-built/pl_eth_10g_wrapper.xsa differ